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Categories: aosp clang clang.exp clang_fast libcxx libunwind lld lldb lldb.exp llvm openmp polly rev_iter sanitizer
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aosp clang clang.exp clang_fast libcxx libunwind lld lldb lldb.exp llvm openmp polly rev_iter sanitizer
326011 rampitec
[AMDGPU] Shrinking V_SUBBREV_U32

V_SUBBREV_U32 is a commute opcode for V_SUBB_U32. However, when
we try to commute V_SUBB_U32 in order to shrink it we do not then
process V_SUBBREV_U32 and it stay VOP3. This is fixed.

Differential Revision: https://reviews.llvm.org/D43699
326008 kamil
Correct ctype(3) functions with NLS on NetBSD

Summary:
The setlocale(3) function reloads the ctype(3) arrays from
external files. This happens behind the scenes in the internals
of libc (citrus library, runes functions etc).

ctype(3) functions like isspace(3) can be provided with two
variations on NetBSD: inlined or via a global symbol in libc:

```
#if defined(_NETBSD_SOURCE) && !defined(_CTYPE_NOINLINE) && \
    !defined(__cplusplus)
#include <sys/ctype_inline.h>
#else
#include <sys/ctype_bits.h>
#endif
```

The in-lined versions are de-facto array lookup operations.

```
#define isspace(c)      ((int)((_ctype_tab_ + 1)[(c)] & _CTYPE_S))
```

After setting setlocale(3) the ctype(3) arrays (_ctype_tab_,
_toupper_tab_, _tolower_tab_) are reload behind the scenes
and they are required to be marked as initialized.

Set them initialized inside the common setlocale(3) interceptor.

The arrays are of size of 257 elements: 0..255 + 1 (EOF).

This corrects errors on NetBSD/amd64 in applications
prebuilt with MS...
326007 alekseyshl
[Sanitizers] Increase allocated chunk limit for LargeMmapAllocator

Summary:
There are applications out there which allocate more than 1 << 18 large chunks
of memory (those handled by LargeMmapAllocator, aka secondary allocator).

For 64 bits, secondary allocator stores allocated chunks in a growing on
demand region of memory, growing in blocks of 128K, up to 1 << 20 chunks total.

Sanitizer internal allocator's secondary uses fixed size array storing up
to 1 << 15 chunks (down to 256K from 2Mb of memory used for that array).

Nothing is changed for 32 bits, chunks are still stored in the fixed size
array (up to 1 << 15 chunks).

Reviewers: eugenis

Subscribers: kubamracek, delcypher, #sanitizers, llvm-commits

Differential Revision: https://reviews.llvm.org/D43693
326006 labath
Fix build breakage from r326003

- an ambiguous reference to Optional<T> in llvm-dwarfdump.cpp (fixed
  with an explicit prefix).
- a missing base class initialization in Entry copy constructor (fixed
  by using the implicitly default constructor, which is possible after
  some changes which were done during review).
326005 alexshap
[llvm-objcopy] Fix typo in setSymTab

This diff fixes the name of the argument of
setSymTab and makes setSymTab/setStrTab private
(to make the public interface a bit cleaner).

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D43661
326004 aheejin
[WebAssembly] Add exception handling option and feature

Summary:
Add a llc command line option and WebAssembly architecture feature for
exception handling.

Reviewers: dschuff

Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D43683
  • clang-ppc64le-linux-lnt: ninja all failed -  stdiowarnings (21)
  • clang-with-thin-lto-windows: stage 1 build -  stdio
326003 labath
Implement equal_range for the DWARF v5 accelerator table

Summary:
This patch implements the name lookup functionality of the .debug_names
accelerator table and hooks it up to "llvm-dwarfdump -find". To make the
interface of the two kinds of accelerator tables more consistent, I've
created an abstract "DWARFAcceleratorTable::Entry" class, which provides
a consistent interface to access the common functionality of the table
entries (such as getting the die offset, die tag, etc.). I've also
modified the apple table to vend entries conforming to this interface.

Reviewers: JDevlieghere, aprantl, probinson, dblaikie

Subscribers: vleschuk, clayborg, echristo, llvm-commits

Differential Revision: https://reviews.llvm.org/D43067
326002 vedantk
Delete dead code in MachVMMemory.cpp, NFC

This addresses a compiler warning.
326001 vedantk
[unittests] Disable lldb-server tests if an external debug server is in use

The lldb-server unit tests don't test the right thing when the debug
server in use is copied from somewhere else. This can lead to spurious
test failures.

Disable these unit tests when an external debug server is in use.

Fixes llvm.org/PR36494.
326000 gbiv
[MemorySSA] Remove a redundant dyn_cast.

StartingAccess is a MemoryUseOrDef. No need to check again.
325999 ctopper
[X86] Remove checks for '(scalar_to_vector (i8 (trunc GR32:)))' from scalar masked move patterns.

This portion can be matched by other patterns. We don't need it to make the larger pattern valid. It's sufficient to have a v1i1 mask input without caring where it came from.
325998 rsmith
Add another test for PR36157.
325997 vsapsai
[ExprConstant] Fix crash when initialize an indirect field with another field.

When indirect field is initialized with another field, you have
MemberExpr with CXXThisExpr that corresponds to the field's immediate
anonymous parent. But 'this' was referring to the non-anonymous parent.
So when we were building LValue Designator, it was incorrect as it had
wrong starting point. Usage of such designator would cause unexpected
APValue changes and crashes.

The fix is in adjusting 'this' for indirect fields from non-anonymous
parent to the field's immediate parent.

Discovered by OSS-Fuzz:
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=4985

rdar://problem/36359187

Reviewers: rsmith, efriedma

Reviewed By: rsmith

Subscribers: cfe-commits, jkorous-apple

Differential Revision: https://reviews.llvm.org/D42498

325996 yhs
bpf: Hook target feature "alu32" with LLVM

LLVM has supported a new target feature "alu32" which could be enabled or
disabled by "-mattr=[+|-]alu32" when using llc.

This patch link Clang with it, so it could be also done by passing related
options to Clang, for example:

  -Xclang -target-feature -Xclang +alu32

Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
325995 rampitec
[AMDGPU] Fixed madak.ll test on VI, added GFX10. NFC.
325994 arphaman
[Sema][ObjC] Process category attributes before checking protocol uses

This ensures that any availability attributes are attached to the
category before the availability for the referenced protocols is checked.

rdar://37829755
325993 yhs
bpf: New disassembler testcases for 32-bit subregister support

This patch test disassembler output for load/store instructions when
-mattr=+alu32 specified for which we want to use "w" register format.

Also, this patch extended the existing insn-unit.s and insn-unit-32.s to
make sure disassemblers for all other instructions are not affected.

Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
325992 yhs
bpf: New codegen testcases for 32-bit subregister support

This patch adds some unit tests for 32-bit subregister support.
We want to make sure ALU32, subregister load/store and new peephole
optimization are truely enabled once -mattr=+alu32 specified.

Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
325991 yhs
bpf: New optimization pass for eliminating unnecessary i32 promotions

This pass performs peephole optimizations to cleanup ugly code sequences at
MachineInstruction layer.

Currently, the only optimization in this pass is to eliminate type
promotion
sequences for zero extending 32-bit subregisters to 64-bit registers.

If the compiler could prove the zero extended source come from 32-bit
subregistere then it is safe to erase those promotion sequece, because the
upper half of the underlying 64-bit registers were zeroed implicitly
already.

Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
325990 yhs
bpf: New decoder namespace for 32-bit subregister load/store

When -mattr=+alu32 passed to the disassembler, use decoder namespace for
32-bit subregister.

This is to disassemble load and store instructions in preferred B format
as described in previous commit:

      w = *(u8 *) (r + off) // BPF_LDX | BPF_B
      w = *(u16 *)(r + off) // BPF_LDX | BPF_H
      w = *(u32 *)(r + off) // BPF_LDX | BPF_W

      *(u8 *) (r + off) = w // BPF_STX | BPF_B
      *(u16 *)(r + off) = w // BPF_STX | BPF_H
      *(u32 *)(r + off) = w // BPF_STX | BPF_W

NOTE: all other instructions should still use the default decoder
      namespace.

Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
325989 yhs
bpf: Enable 32-bit subregister support for -mattr=+alu32

After all those preparation patches, now we could enable 32-bit subregister
support once -mattr=+alu32 specified.

Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
325988 yhs
bpf: Support 32-bit subregister in various InstrInfo hooks

This patch support 32-bit subregister in three InstrInfo hooks, i.e.
copyPhysReg, loadRegFromStackSlot and storeRegToStackSlot,

Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
325987 yhs
bpf: New instruction patterns for 32-bit subregister load and store

The instruction mapping between eBPF/arm64/x86_64 are:

        eBPF              arm64        x86_64
LD1  BPF_LDX | BPF_B      ldrb        movzbl
LD2  BPF_LDX | BPF_H      ldrh        movzwl
LD4  BPF_LDX | BPF_W      ldr        movl

movzbl/movzwl/movl on x86_64 accept 32-bit sub-register, for example %eax,
the same for ldrb/ldrh on arm64 which accept 32-bit "w" register. And
actually these instructions only accept sub-registers. There is no point
to have LD1/2/4 (unsigned) for 64-bit register, because on these arches,
upper 32-bits are guaranteed to be zeroed by hardware or VM, so load into
the smallest available register class is the best choice for maintaining
type information.

For eBPF we should adopt the same philosophy, to change current
format (A):

  r = *(u8 *) (r + off) // BPF_LDX | BPF_B
  r = *(u16 *)(r + off) // BPF_LDX | BPF_H
  r = *(u32 *)(r + off) // BPF_LDX | BPF_W

  *(u8 *) (r + off) = r // BPF_STX | BPF_B
  ...
325986 yhs
bpf: Support i32 in getScalarShiftAmountTy method

getScalarShiftAmount method should be implemented for eBPF backend to make
sure shift amount could still get correct type once 32-bit subregisters
support are enabled.

Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
325985 yhs
bpf: Support condition comparison on i32

We need to support condition comparison on i32. All these comparisons are
supposed to be combined into BPF_J* instructions which only support i64.

For ISD::BR_CC we need to promote it to i64 first, then do custom lowering.

For ISD::SET_CC, just expand to SELECT_CC like what's been done for i64.

For ISD::SELECT_CC, we also want to do custom lower for i32. However, after
32-bit subregister support enabled, it is possible the comparison operands
are i32 while the selected value are i64, or the comparison operands are
i64 while the selected value are i32. We need to define extra instruction
pattern and support them in custom instruction inserter.

Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>