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295676 ctopper
[X86] FileCheckize one of the rotate tests.
295675 steven_wu
Fix use-after-free found by ASAN

DenseMap::lookup returns copy of the value in the map. Returning the
address of the temporary return value will cause use-after-free.
295674 arphaman
[Sema][ObjC] perform-selector ARC check should see @selector in parens
295673 ctopper
[AVX-512] Add a few more patterns for selecting masked vpternlog with broadcast loads where the passthru operand is not operand 0.
295672 meinersbur
[Cmake] Bump required cmake version to 3.4.3.

This is currently the minimum required version by LLVM. Since LLVM is
needed to build Polly, we also require at least that version.

Suggested-by: Philip Pfaffe <philip.pfaffe@gmail.com>
295671 meinersbur
[Cmake] Install the isl headers into the install tree.

isl headers are currently missing in a Polly installation. Because the
Polly headers depend on those, code can't be compiled against an
installed Polly.

This patch installs the isl headers. I left a TODO, as optionally it
should be possible to use a system version of isl instead of the one
shipped with Polly.

When compiling, clients of the installation need to add
-I${PREFIX}/include/polly/ to there include path right now, because
there currently is no way to export this path automatically.

Contributed-by: Philip Pfaffe <philip.pfaffe@gmail.com>

Differential Revision: https://reviews.llvm.org/D29931
295670 rksimon
[X86] Tidyup combineExtractVectorElt. NFCI.

Pull out repeated code for extraction index operand and source vector value type.

Use isNullConstant helper to check for zero extraction index.
295669 rksimon
[X86][SSE] Regenerate extracted bitcasted constant tests and add 32-bit test target
295668 dsanders
[globalisel] OperandPredicateMatcher's shouldn't need to generate the MachineOperand expr. NFC

Each OperandPredicateMatcher shouldn't need to know how to generate the expression
to reference a MachineOperand. The OperandMatcher should provide it.

In addition to separating responsibilities, this also lays some groundwork for
decoupling source patterns from destination patterns to allow invented operands
or operands provided by GlobalISel's equivalent to the ComplexPattern<> class.

Depends on D29709

Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar

Reviewed By: ab

Subscribers: dberris, kristof.beyls, llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D29710
295667 rovka
Revert "[tsan] Provide external tags (object types) via debugging API"

This reverts commit r295318 as the test is flaky on AArch64.
295666 rksimon
[X86][SSE] Regenerate re-materialized store tests and add 64-bit test target
295665 rksimon
[X86][SSE] Regenerate vselect widening tests and add 32-bit test target
295664 rengolin
Revert "[PGO] Suspend SIGKILL for PR_SET_PDEATHSIG in profile-write"

Revert "[PGO] remove unintended debug trace. NFC"

This reverts commit r295469, r295364, as they are unstable on ARM/AArch64.
295663 djasper
clang-format: [JS] Improve line-wrapping behavior of template strings.

Specifically, similar to other blocks, clang-format now wraps both
after "${" and before the corresponding "}", if the contained
expression spans multiple lines.
295662 rovka
[ARM] GlobalISel: Don't select atomic loads

There used to be a check in the IRTranslator that prevented us from having to
deal with atomic loads/stores. That check has been removed in r294993 and the
AArch64 backend was updated accordingly. This commit does the same thing for the
ARM backend.

In general, in the ARM backend we introduce fences during the atomic expand
pass, so we don't have to worry about atomics, *except* for the 32-bit ARMv8
target, which handles atomics more like AArch64. Since we don't want to worry
about that yet, just bail out of instruction selection if we find any atomic
295661 dsanders
[globalisel] Separate the SelectionDAG importer from the emitter. NFC

In the near future the rules will be sorted between these two steps to
ensure that more important rules are not prevented by less important ones.

Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar

Reviewed By: ab

Subscribers: dberris, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D29709
295660 ibreger
[X86] Fix EXTRACT_VECTOR_ELT with variable index from v32i16 and v64i8 vector.

Its more profitable to go through memory (1 cycles throughput)
than using VMOVD + VPERMV/PSHUFB sequence ( 2/3 cycles throughput) to implement EXTRACT_VECTOR_ELT with variable index.
IACA tool was used to get performace estimation (https://software.intel.com/en-us/articles/intel-architecture-code-analyzer)
For example for var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8 test from vector-shuffle-variable-128.ll I get 26 cycles vs 79 cycles.
Removing the VINSERT node, we don't need it any more.

Differential Revision: https://reviews.llvm.org/D29690

295659 djasper
clang-format: Prevent weird line-wraps in complex lambda introducers

      [aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa]() -> ::std::
  unordered_set<aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa> {

  -> ::std::unordered_set<
      aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa> {
295658 djasper
clang-format: [JS/TS] Improve detection for array subscripts in types.

  var someValue = (v as aaaaaaaaaaaaaaaaaaaa<T>[

  var someValue = (v as aaaaaaaaaaaaaaaaaaaa<T>[])
295657 abataev
[SLP] Additional test for vectorization of cal/invoke args vectorization
295656 rksimon
[X86][AVX512] Add support for ASHR v2i64/v4i64 support without VLX

Use v8i64 ASHR instructions if we don't have VLX.

Differential Revision: https://reviews.llvm.org/D28537
295655 sanwou01
[ARM] Add a div regression test for Cortex-M23

This file was missed in the commit for Cortex-M23 and Cortex-M33
support.  See https://reviews.llvm.org/D29073?id=85814 .

Reviewers: rengolin, javed.absar, samparker

Reviewed By: samparker

Subscribers: llvm-commits, aemerson

Differential Revision: https://reviews.llvm.org/D30162
295654 a.sidorin
[ASTImporter] Support default argument initialization of ParmVarDecls

Patch by Peter Szecsi!

Differential Revision: https://reviews.llvm.org/D29612
295653 rksimon
Strip trailing whitespace.
295652 rksimon
[SelectionDAG] Add scalarization support for ISD::*_EXTEND_VECTOR_INREG opcodes.

Thanks to Mikael Holmén for the initial test case