/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/clang-build/lib/Target/AArch64/AArch64GenCallingConv.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Calling Convention Implementation Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | static bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, |
10 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
11 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
12 | | static bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, |
13 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
14 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
15 | | static bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, |
16 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
17 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
18 | | static bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT, |
19 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
20 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
21 | | static bool CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, |
22 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
23 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
24 | | static bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, |
25 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
26 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
27 | | static bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, |
28 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
29 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
30 | | static bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, |
31 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
32 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
33 | | |
34 | | |
35 | | static bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, |
36 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
37 | 18.5k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
38 | 18.5k | |
39 | 18.5k | if (LocVT == MVT::iPTR18.5k ) { |
40 | 0 | LocVT = MVT::i64; |
41 | 0 | LocInfo = CCValAssign::BCvt; |
42 | 0 | } |
43 | 18.5k | |
44 | 18.5k | if (LocVT == MVT::v2f3218.5k ) { |
45 | 396 | LocVT = MVT::v2i32; |
46 | 396 | LocInfo = CCValAssign::BCvt; |
47 | 396 | } |
48 | 18.5k | |
49 | 18.5k | if (LocVT == MVT::v2f64 || |
50 | 18.5k | LocVT == MVT::v4f3218.1k ) { |
51 | 904 | LocVT = MVT::v2i64; |
52 | 904 | LocInfo = CCValAssign::BCvt; |
53 | 904 | } |
54 | 18.5k | |
55 | 18.5k | if (State.getMachineFunction().getDataLayout().isBigEndian()18.5k ) { |
56 | 1.15k | if (LocVT == MVT::v2i32 || |
57 | 1.08k | LocVT == MVT::v2f32 || |
58 | 1.08k | LocVT == MVT::v4i16 || |
59 | 1.05k | LocVT == MVT::v4f16 || |
60 | 1.15k | LocVT == MVT::v8i81.04k ) { |
61 | 139 | LocVT = MVT::f64; |
62 | 139 | LocInfo = CCValAssign::BCvt; |
63 | 139 | } |
64 | 1.15k | } |
65 | 18.5k | |
66 | 18.5k | if (State.getMachineFunction().getDataLayout().isBigEndian()18.5k ) { |
67 | 1.15k | if (LocVT == MVT::v2i64 || |
68 | 1.06k | LocVT == MVT::v2f64 || |
69 | 1.06k | LocVT == MVT::v4i32 || |
70 | 1.03k | LocVT == MVT::v4f32 || |
71 | 1.03k | LocVT == MVT::v8i16 || |
72 | 997 | LocVT == MVT::v8f16 || |
73 | 1.15k | LocVT == MVT::v16i8994 ) { |
74 | 192 | LocVT = MVT::f128; |
75 | 192 | LocInfo = CCValAssign::BCvt; |
76 | 192 | } |
77 | 1.15k | } |
78 | 18.5k | |
79 | 18.5k | if (ArgFlags.isSRet()18.5k ) { |
80 | 13 | if (LocVT == MVT::i6413 ) { |
81 | 13 | if (unsigned Reg13 = State.AllocateReg(AArch64::X8, AArch64::W8)) { |
82 | 13 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
83 | 13 | return false; |
84 | 13 | } |
85 | 13 | } |
86 | 13 | } |
87 | 18.5k | |
88 | 18.5k | if (18.5k ArgFlags.isByVal()18.5k ) { |
89 | 14 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); |
90 | 14 | return false; |
91 | 14 | } |
92 | 18.5k | |
93 | 18.5k | if (18.5k ArgFlags.isNest()18.5k ) { |
94 | 2 | if (unsigned Reg2 = State.AllocateReg(AArch64::X18)) { |
95 | 2 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
96 | 2 | return false; |
97 | 2 | } |
98 | 2 | } |
99 | 18.5k | |
100 | 18.5k | if (18.5k ArgFlags.isSwiftSelf()18.5k ) { |
101 | 14 | if (LocVT == MVT::i6414 ) { |
102 | 14 | if (unsigned Reg14 = State.AllocateReg(AArch64::X20, AArch64::W20)) { |
103 | 14 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
104 | 14 | return false; |
105 | 14 | } |
106 | 14 | } |
107 | 14 | } |
108 | 18.5k | |
109 | 18.5k | if (18.5k ArgFlags.isSwiftError()18.5k ) { |
110 | 2 | if (LocVT == MVT::i642 ) { |
111 | 2 | if (unsigned Reg2 = State.AllocateReg(AArch64::X21, AArch64::W21)) { |
112 | 2 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
113 | 2 | return false; |
114 | 2 | } |
115 | 2 | } |
116 | 2 | } |
117 | 18.5k | |
118 | 18.5k | if (18.5k ArgFlags.isInConsecutiveRegs()18.5k ) { |
119 | 869 | if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
120 | 349 | return false; |
121 | 869 | } |
122 | 18.5k | |
123 | 18.1k | if (18.1k LocVT == MVT::i1 || |
124 | 18.1k | LocVT == MVT::i8 || |
125 | 18.1k | LocVT == MVT::i1617.7k ) { |
126 | 895 | LocVT = MVT::i32; |
127 | 895 | if (ArgFlags.isSExt()) |
128 | 6 | LocInfo = CCValAssign::SExt; |
129 | 889 | else if (889 ArgFlags.isZExt()889 ) |
130 | 18 | LocInfo = CCValAssign::ZExt; |
131 | 889 | else |
132 | 871 | LocInfo = CCValAssign::AExt; |
133 | 895 | } |
134 | 18.1k | |
135 | 18.1k | if (LocVT == MVT::i3218.1k ) { |
136 | 3.41k | static const MCPhysReg RegList1[] = { |
137 | 3.41k | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
138 | 3.41k | }; |
139 | 3.41k | static const MCPhysReg RegList2[] = { |
140 | 3.41k | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
141 | 3.41k | }; |
142 | 3.41k | if (unsigned Reg3.41k = State.AllocateReg(RegList1, RegList2)) { |
143 | 3.35k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
144 | 3.35k | return false; |
145 | 3.35k | } |
146 | 3.41k | } |
147 | 18.1k | |
148 | 14.8k | if (14.8k LocVT == MVT::i6414.8k ) { |
149 | 5.64k | if (ArgFlags.isSplit()5.64k ) { |
150 | 122 | static const MCPhysReg RegList3[] = { |
151 | 122 | AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6 |
152 | 122 | }; |
153 | 122 | static const MCPhysReg RegList4[] = { |
154 | 122 | AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5 |
155 | 122 | }; |
156 | 122 | if (unsigned Reg122 = State.AllocateReg(RegList3, RegList4)) { |
157 | 73 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
158 | 73 | return false; |
159 | 73 | } |
160 | 122 | } |
161 | 5.64k | } |
162 | 14.8k | |
163 | 14.7k | if (14.7k LocVT == MVT::i6414.7k ) { |
164 | 5.57k | if (ArgFlags.isSplit()5.57k ) { |
165 | 49 | static const MCPhysReg ShadowRegList5[] = { |
166 | 49 | AArch64::X7 |
167 | 49 | }; |
168 | 49 | unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5); |
169 | 49 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); |
170 | 49 | return false; |
171 | 49 | } |
172 | 5.57k | } |
173 | 14.7k | |
174 | 14.7k | if (14.7k LocVT == MVT::i6414.7k ) { |
175 | 5.52k | static const MCPhysReg RegList7[] = { |
176 | 5.52k | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
177 | 5.52k | }; |
178 | 5.52k | static const MCPhysReg RegList8[] = { |
179 | 5.52k | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
180 | 5.52k | }; |
181 | 5.52k | if (unsigned Reg5.52k = State.AllocateReg(RegList7, RegList8)) { |
182 | 5.42k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
183 | 5.42k | return false; |
184 | 5.42k | } |
185 | 5.52k | } |
186 | 14.7k | |
187 | 9.27k | if (9.27k LocVT == MVT::f169.27k ) { |
188 | 235 | static const MCPhysReg RegList9[] = { |
189 | 235 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 |
190 | 235 | }; |
191 | 235 | static const MCPhysReg RegList10[] = { |
192 | 235 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
193 | 235 | }; |
194 | 235 | if (unsigned Reg235 = State.AllocateReg(RegList9, RegList10)) { |
195 | 235 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
196 | 235 | return false; |
197 | 235 | } |
198 | 235 | } |
199 | 9.27k | |
200 | 9.04k | if (9.04k LocVT == MVT::f329.04k ) { |
201 | 750 | static const MCPhysReg RegList11[] = { |
202 | 750 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 |
203 | 750 | }; |
204 | 750 | static const MCPhysReg RegList12[] = { |
205 | 750 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
206 | 750 | }; |
207 | 750 | if (unsigned Reg750 = State.AllocateReg(RegList11, RegList12)) { |
208 | 745 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
209 | 745 | return false; |
210 | 745 | } |
211 | 750 | } |
212 | 9.04k | |
213 | 8.29k | if (8.29k LocVT == MVT::f648.29k ) { |
214 | 704 | static const MCPhysReg RegList13[] = { |
215 | 704 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
216 | 704 | }; |
217 | 704 | static const MCPhysReg RegList14[] = { |
218 | 704 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
219 | 704 | }; |
220 | 704 | if (unsigned Reg704 = State.AllocateReg(RegList13, RegList14)) { |
221 | 686 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
222 | 686 | return false; |
223 | 686 | } |
224 | 704 | } |
225 | 8.29k | |
226 | 7.61k | if (7.61k LocVT == MVT::v1i64 || |
227 | 7.43k | LocVT == MVT::v2i32 || |
228 | 6.32k | LocVT == MVT::v4i16 || |
229 | 5.48k | LocVT == MVT::v8i8 || |
230 | 5.02k | LocVT == MVT::v1f64 || |
231 | 4.91k | LocVT == MVT::v2f32 || |
232 | 7.61k | LocVT == MVT::v4f164.91k ) { |
233 | 2.87k | static const MCPhysReg RegList15[] = { |
234 | 2.87k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
235 | 2.87k | }; |
236 | 2.87k | static const MCPhysReg RegList16[] = { |
237 | 2.87k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
238 | 2.87k | }; |
239 | 2.87k | if (unsigned Reg2.87k = State.AllocateReg(RegList15, RegList16)) { |
240 | 2.87k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
241 | 2.87k | return false; |
242 | 2.87k | } |
243 | 2.87k | } |
244 | 7.61k | |
245 | 4.73k | if (4.73k LocVT == MVT::f128 || |
246 | 4.22k | LocVT == MVT::v2i64 || |
247 | 2.82k | LocVT == MVT::v4i32 || |
248 | 1.76k | LocVT == MVT::v8i16 || |
249 | 891 | LocVT == MVT::v16i8 || |
250 | 366 | LocVT == MVT::v4f32 || |
251 | 366 | LocVT == MVT::v2f64 || |
252 | 4.73k | LocVT == MVT::v8f16366 ) { |
253 | 4.54k | static const MCPhysReg RegList17[] = { |
254 | 4.54k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
255 | 4.54k | }; |
256 | 4.54k | if (unsigned Reg4.54k = State.AllocateReg(RegList17)) { |
257 | 4.53k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
258 | 4.53k | return false; |
259 | 4.53k | } |
260 | 4.54k | } |
261 | 4.73k | |
262 | 199 | if (199 LocVT == MVT::i1 || |
263 | 199 | LocVT == MVT::i8 || |
264 | 199 | LocVT == MVT::i16 || |
265 | 199 | LocVT == MVT::f16199 ) { |
266 | 0 | unsigned Offset18 = State.AllocateStack(8, 8); |
267 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo)); |
268 | 0 | return false; |
269 | 0 | } |
270 | 199 | |
271 | 199 | if (199 LocVT == MVT::i32 || |
272 | 199 | LocVT == MVT::f32135 ) { |
273 | 69 | unsigned Offset19 = State.AllocateStack(8, 8); |
274 | 69 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo)); |
275 | 69 | return false; |
276 | 69 | } |
277 | 199 | |
278 | 130 | if (130 LocVT == MVT::i64 || |
279 | 29 | LocVT == MVT::f64 || |
280 | 11 | LocVT == MVT::v1f64 || |
281 | 11 | LocVT == MVT::v2f32 || |
282 | 11 | LocVT == MVT::v1i64 || |
283 | 11 | LocVT == MVT::v2i32 || |
284 | 11 | LocVT == MVT::v4i16 || |
285 | 11 | LocVT == MVT::v8i8 || |
286 | 130 | LocVT == MVT::v4f1611 ) { |
287 | 120 | unsigned Offset20 = State.AllocateStack(8, 8); |
288 | 120 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo)); |
289 | 120 | return false; |
290 | 120 | } |
291 | 130 | |
292 | 10 | if (10 LocVT == MVT::f128 || |
293 | 9 | LocVT == MVT::v2i64 || |
294 | 6 | LocVT == MVT::v4i32 || |
295 | 6 | LocVT == MVT::v8i16 || |
296 | 6 | LocVT == MVT::v16i8 || |
297 | 6 | LocVT == MVT::v4f32 || |
298 | 6 | LocVT == MVT::v2f64 || |
299 | 10 | LocVT == MVT::v8f166 ) { |
300 | 5 | unsigned Offset21 = State.AllocateStack(16, 16); |
301 | 5 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo)); |
302 | 5 | return false; |
303 | 5 | } |
304 | 10 | |
305 | 5 | return true; // CC didn't match. |
306 | 18.5k | } AArch64FastISel.cpp:CC_AArch64_AAPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 37 | 65 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 38 | 65 | | 39 | 65 | if (LocVT == MVT::iPTR65 ) { | 40 | 0 | LocVT = MVT::i64; | 41 | 0 | LocInfo = CCValAssign::BCvt; | 42 | 0 | } | 43 | 65 | | 44 | 65 | if (LocVT == MVT::v2f3265 ) { | 45 | 2 | LocVT = MVT::v2i32; | 46 | 2 | LocInfo = CCValAssign::BCvt; | 47 | 2 | } | 48 | 65 | | 49 | 65 | if (LocVT == MVT::v2f64 || | 50 | 65 | LocVT == MVT::v4f3265 ) { | 51 | 0 | LocVT = MVT::v2i64; | 52 | 0 | LocInfo = CCValAssign::BCvt; | 53 | 0 | } | 54 | 65 | | 55 | 65 | if (State.getMachineFunction().getDataLayout().isBigEndian()65 ) { | 56 | 57 | if (LocVT == MVT::v2i32 || | 57 | 53 | LocVT == MVT::v2f32 || | 58 | 53 | LocVT == MVT::v4i16 || | 59 | 51 | LocVT == MVT::v4f16 || | 60 | 57 | LocVT == MVT::v8i851 ) { | 61 | 8 | LocVT = MVT::f64; | 62 | 8 | LocInfo = CCValAssign::BCvt; | 63 | 8 | } | 64 | 57 | } | 65 | 65 | | 66 | 65 | if (State.getMachineFunction().getDataLayout().isBigEndian()65 ) { | 67 | 57 | if (LocVT == MVT::v2i64 || | 68 | 57 | LocVT == MVT::v2f64 || | 69 | 57 | LocVT == MVT::v4i32 || | 70 | 57 | LocVT == MVT::v4f32 || | 71 | 57 | LocVT == MVT::v8i16 || | 72 | 57 | LocVT == MVT::v8f16 || | 73 | 57 | LocVT == MVT::v16i857 ) { | 74 | 0 | LocVT = MVT::f128; | 75 | 0 | LocInfo = CCValAssign::BCvt; | 76 | 0 | } | 77 | 57 | } | 78 | 65 | | 79 | 65 | if (ArgFlags.isSRet()65 ) { | 80 | 0 | if (LocVT == MVT::i640 ) { | 81 | 0 | if (unsigned Reg0 = State.AllocateReg(AArch64::X8, AArch64::W8)) { | 82 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 83 | 0 | return false; | 84 | 0 | } | 85 | 0 | } | 86 | 0 | } | 87 | 65 | | 88 | 65 | if (65 ArgFlags.isByVal()65 ) { | 89 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); | 90 | 0 | return false; | 91 | 0 | } | 92 | 65 | | 93 | 65 | if (65 ArgFlags.isNest()65 ) { | 94 | 0 | if (unsigned Reg0 = State.AllocateReg(AArch64::X18)) { | 95 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 96 | 0 | return false; | 97 | 0 | } | 98 | 0 | } | 99 | 65 | | 100 | 65 | if (65 ArgFlags.isSwiftSelf()65 ) { | 101 | 0 | if (LocVT == MVT::i640 ) { | 102 | 0 | if (unsigned Reg0 = State.AllocateReg(AArch64::X20, AArch64::W20)) { | 103 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 104 | 0 | return false; | 105 | 0 | } | 106 | 0 | } | 107 | 0 | } | 108 | 65 | | 109 | 65 | if (65 ArgFlags.isSwiftError()65 ) { | 110 | 0 | if (LocVT == MVT::i640 ) { | 111 | 0 | if (unsigned Reg0 = State.AllocateReg(AArch64::X21, AArch64::W21)) { | 112 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 113 | 0 | return false; | 114 | 0 | } | 115 | 0 | } | 116 | 0 | } | 117 | 65 | | 118 | 65 | if (65 ArgFlags.isInConsecutiveRegs()65 ) { | 119 | 0 | if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 120 | 0 | return false; | 121 | 0 | } | 122 | 65 | | 123 | 65 | if (65 LocVT == MVT::i1 || | 124 | 63 | LocVT == MVT::i8 || | 125 | 65 | LocVT == MVT::i1642 ) { | 126 | 26 | LocVT = MVT::i32; | 127 | 26 | if (ArgFlags.isSExt()) | 128 | 3 | LocInfo = CCValAssign::SExt; | 129 | 23 | else if (23 ArgFlags.isZExt()23 ) | 130 | 14 | LocInfo = CCValAssign::ZExt; | 131 | 23 | else | 132 | 9 | LocInfo = CCValAssign::AExt; | 133 | 26 | } | 134 | 65 | | 135 | 65 | if (LocVT == MVT::i3265 ) { | 136 | 32 | static const MCPhysReg RegList1[] = { | 137 | 32 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 138 | 32 | }; | 139 | 32 | static const MCPhysReg RegList2[] = { | 140 | 32 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 141 | 32 | }; | 142 | 32 | if (unsigned Reg32 = State.AllocateReg(RegList1, RegList2)) { | 143 | 30 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 144 | 30 | return false; | 145 | 30 | } | 146 | 32 | } | 147 | 65 | | 148 | 35 | if (35 LocVT == MVT::i6435 ) { | 149 | 14 | if (ArgFlags.isSplit()14 ) { | 150 | 0 | static const MCPhysReg RegList3[] = { | 151 | 0 | AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6 | 152 | 0 | }; | 153 | 0 | static const MCPhysReg RegList4[] = { | 154 | 0 | AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5 | 155 | 0 | }; | 156 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList3, RegList4)) { | 157 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 158 | 0 | return false; | 159 | 0 | } | 160 | 0 | } | 161 | 14 | } | 162 | 35 | | 163 | 35 | if (35 LocVT == MVT::i6435 ) { | 164 | 14 | if (ArgFlags.isSplit()14 ) { | 165 | 0 | static const MCPhysReg ShadowRegList5[] = { | 166 | 0 | AArch64::X7 | 167 | 0 | }; | 168 | 0 | unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5); | 169 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); | 170 | 0 | return false; | 171 | 0 | } | 172 | 14 | } | 173 | 35 | | 174 | 35 | if (35 LocVT == MVT::i6435 ) { | 175 | 14 | static const MCPhysReg RegList7[] = { | 176 | 14 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 177 | 14 | }; | 178 | 14 | static const MCPhysReg RegList8[] = { | 179 | 14 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 180 | 14 | }; | 181 | 14 | if (unsigned Reg14 = State.AllocateReg(RegList7, RegList8)) { | 182 | 14 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 183 | 14 | return false; | 184 | 14 | } | 185 | 14 | } | 186 | 35 | | 187 | 21 | if (21 LocVT == MVT::f1621 ) { | 188 | 0 | static const MCPhysReg RegList9[] = { | 189 | 0 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 | 190 | 0 | }; | 191 | 0 | static const MCPhysReg RegList10[] = { | 192 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 193 | 0 | }; | 194 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList9, RegList10)) { | 195 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 196 | 0 | return false; | 197 | 0 | } | 198 | 0 | } | 199 | 21 | | 200 | 21 | if (21 LocVT == MVT::f3221 ) { | 201 | 1 | static const MCPhysReg RegList11[] = { | 202 | 1 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 | 203 | 1 | }; | 204 | 1 | static const MCPhysReg RegList12[] = { | 205 | 1 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 206 | 1 | }; | 207 | 1 | if (unsigned Reg1 = State.AllocateReg(RegList11, RegList12)) { | 208 | 1 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 209 | 1 | return false; | 210 | 1 | } | 211 | 1 | } | 212 | 21 | | 213 | 20 | if (20 LocVT == MVT::f6420 ) { | 214 | 16 | static const MCPhysReg RegList13[] = { | 215 | 16 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 216 | 16 | }; | 217 | 16 | static const MCPhysReg RegList14[] = { | 218 | 16 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 219 | 16 | }; | 220 | 16 | if (unsigned Reg16 = State.AllocateReg(RegList13, RegList14)) { | 221 | 16 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 222 | 16 | return false; | 223 | 16 | } | 224 | 16 | } | 225 | 20 | | 226 | 4 | if (4 LocVT == MVT::v1i64 || | 227 | 2 | LocVT == MVT::v2i32 || | 228 | 2 | LocVT == MVT::v4i16 || | 229 | 2 | LocVT == MVT::v8i8 || | 230 | 2 | LocVT == MVT::v1f64 || | 231 | 2 | LocVT == MVT::v2f32 || | 232 | 4 | LocVT == MVT::v4f162 ) { | 233 | 2 | static const MCPhysReg RegList15[] = { | 234 | 2 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 235 | 2 | }; | 236 | 2 | static const MCPhysReg RegList16[] = { | 237 | 2 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 238 | 2 | }; | 239 | 2 | if (unsigned Reg2 = State.AllocateReg(RegList15, RegList16)) { | 240 | 2 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 241 | 2 | return false; | 242 | 2 | } | 243 | 2 | } | 244 | 4 | | 245 | 2 | if (2 LocVT == MVT::f128 || | 246 | 2 | LocVT == MVT::v2i64 || | 247 | 2 | LocVT == MVT::v4i32 || | 248 | 2 | LocVT == MVT::v8i16 || | 249 | 2 | LocVT == MVT::v16i8 || | 250 | 2 | LocVT == MVT::v4f32 || | 251 | 2 | LocVT == MVT::v2f64 || | 252 | 2 | LocVT == MVT::v8f162 ) { | 253 | 0 | static const MCPhysReg RegList17[] = { | 254 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 255 | 0 | }; | 256 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList17)) { | 257 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 258 | 0 | return false; | 259 | 0 | } | 260 | 0 | } | 261 | 2 | | 262 | 2 | if (2 LocVT == MVT::i1 || | 263 | 2 | LocVT == MVT::i8 || | 264 | 2 | LocVT == MVT::i16 || | 265 | 2 | LocVT == MVT::f162 ) { | 266 | 0 | unsigned Offset18 = State.AllocateStack(8, 8); | 267 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo)); | 268 | 0 | return false; | 269 | 0 | } | 270 | 2 | | 271 | 2 | if (2 LocVT == MVT::i32 || | 272 | 2 | LocVT == MVT::f320 ) { | 273 | 2 | unsigned Offset19 = State.AllocateStack(8, 8); | 274 | 2 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo)); | 275 | 2 | return false; | 276 | 2 | } | 277 | 2 | | 278 | 0 | if (0 LocVT == MVT::i64 || | 279 | 0 | LocVT == MVT::f64 || | 280 | 0 | LocVT == MVT::v1f64 || | 281 | 0 | LocVT == MVT::v2f32 || | 282 | 0 | LocVT == MVT::v1i64 || | 283 | 0 | LocVT == MVT::v2i32 || | 284 | 0 | LocVT == MVT::v4i16 || | 285 | 0 | LocVT == MVT::v8i8 || | 286 | 0 | LocVT == MVT::v4f160 ) { | 287 | 0 | unsigned Offset20 = State.AllocateStack(8, 8); | 288 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo)); | 289 | 0 | return false; | 290 | 0 | } | 291 | 0 |
| 292 | 0 | if (0 LocVT == MVT::f128 || | 293 | 0 | LocVT == MVT::v2i64 || | 294 | 0 | LocVT == MVT::v4i32 || | 295 | 0 | LocVT == MVT::v8i16 || | 296 | 0 | LocVT == MVT::v16i8 || | 297 | 0 | LocVT == MVT::v4f32 || | 298 | 0 | LocVT == MVT::v2f64 || | 299 | 0 | LocVT == MVT::v8f160 ) { | 300 | 0 | unsigned Offset21 = State.AllocateStack(16, 16); | 301 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo)); | 302 | 0 | return false; | 303 | 0 | } | 304 | 0 |
| 305 | 0 | return true; // CC didn't match. | 306 | 65 | } |
AArch64ISelLowering.cpp:CC_AArch64_AAPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 37 | 18.5k | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 38 | 18.5k | | 39 | 18.5k | if (LocVT == MVT::iPTR18.5k ) { | 40 | 0 | LocVT = MVT::i64; | 41 | 0 | LocInfo = CCValAssign::BCvt; | 42 | 0 | } | 43 | 18.5k | | 44 | 18.5k | if (LocVT == MVT::v2f3218.5k ) { | 45 | 394 | LocVT = MVT::v2i32; | 46 | 394 | LocInfo = CCValAssign::BCvt; | 47 | 394 | } | 48 | 18.5k | | 49 | 18.5k | if (LocVT == MVT::v2f64 || | 50 | 18.5k | LocVT == MVT::v4f3218.0k ) { | 51 | 904 | LocVT = MVT::v2i64; | 52 | 904 | LocInfo = CCValAssign::BCvt; | 53 | 904 | } | 54 | 18.5k | | 55 | 18.5k | if (State.getMachineFunction().getDataLayout().isBigEndian()18.5k ) { | 56 | 1.09k | if (LocVT == MVT::v2i32 || | 57 | 1.03k | LocVT == MVT::v2f32 || | 58 | 1.03k | LocVT == MVT::v4i16 || | 59 | 999 | LocVT == MVT::v4f16 || | 60 | 1.09k | LocVT == MVT::v8i8997 ) { | 61 | 131 | LocVT = MVT::f64; | 62 | 131 | LocInfo = CCValAssign::BCvt; | 63 | 131 | } | 64 | 1.09k | } | 65 | 18.5k | | 66 | 18.5k | if (State.getMachineFunction().getDataLayout().isBigEndian()18.5k ) { | 67 | 1.09k | if (LocVT == MVT::v2i64 || | 68 | 1.01k | LocVT == MVT::v2f64 || | 69 | 1.01k | LocVT == MVT::v4i32 || | 70 | 976 | LocVT == MVT::v4f32 || | 71 | 976 | LocVT == MVT::v8i16 || | 72 | 940 | LocVT == MVT::v8f16 || | 73 | 1.09k | LocVT == MVT::v16i8937 ) { | 74 | 192 | LocVT = MVT::f128; | 75 | 192 | LocInfo = CCValAssign::BCvt; | 76 | 192 | } | 77 | 1.09k | } | 78 | 18.5k | | 79 | 18.5k | if (ArgFlags.isSRet()18.5k ) { | 80 | 13 | if (LocVT == MVT::i6413 ) { | 81 | 13 | if (unsigned Reg13 = State.AllocateReg(AArch64::X8, AArch64::W8)) { | 82 | 13 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 83 | 13 | return false; | 84 | 13 | } | 85 | 13 | } | 86 | 13 | } | 87 | 18.5k | | 88 | 18.4k | if (18.4k ArgFlags.isByVal()18.4k ) { | 89 | 14 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); | 90 | 14 | return false; | 91 | 14 | } | 92 | 18.4k | | 93 | 18.4k | if (18.4k ArgFlags.isNest()18.4k ) { | 94 | 2 | if (unsigned Reg2 = State.AllocateReg(AArch64::X18)) { | 95 | 2 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 96 | 2 | return false; | 97 | 2 | } | 98 | 2 | } | 99 | 18.4k | | 100 | 18.4k | if (18.4k ArgFlags.isSwiftSelf()18.4k ) { | 101 | 14 | if (LocVT == MVT::i6414 ) { | 102 | 14 | if (unsigned Reg14 = State.AllocateReg(AArch64::X20, AArch64::W20)) { | 103 | 14 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 104 | 14 | return false; | 105 | 14 | } | 106 | 14 | } | 107 | 14 | } | 108 | 18.4k | | 109 | 18.4k | if (18.4k ArgFlags.isSwiftError()18.4k ) { | 110 | 2 | if (LocVT == MVT::i642 ) { | 111 | 2 | if (unsigned Reg2 = State.AllocateReg(AArch64::X21, AArch64::W21)) { | 112 | 2 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 113 | 2 | return false; | 114 | 2 | } | 115 | 2 | } | 116 | 2 | } | 117 | 18.4k | | 118 | 18.4k | if (18.4k ArgFlags.isInConsecutiveRegs()18.4k ) { | 119 | 869 | if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 120 | 349 | return false; | 121 | 869 | } | 122 | 18.4k | | 123 | 18.1k | if (18.1k LocVT == MVT::i1 || | 124 | 18.1k | LocVT == MVT::i8 || | 125 | 18.1k | LocVT == MVT::i1617.6k ) { | 126 | 869 | LocVT = MVT::i32; | 127 | 869 | if (ArgFlags.isSExt()) | 128 | 3 | LocInfo = CCValAssign::SExt; | 129 | 866 | else if (866 ArgFlags.isZExt()866 ) | 130 | 4 | LocInfo = CCValAssign::ZExt; | 131 | 866 | else | 132 | 862 | LocInfo = CCValAssign::AExt; | 133 | 869 | } | 134 | 18.1k | | 135 | 18.1k | if (LocVT == MVT::i3218.1k ) { | 136 | 3.38k | static const MCPhysReg RegList1[] = { | 137 | 3.38k | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 138 | 3.38k | }; | 139 | 3.38k | static const MCPhysReg RegList2[] = { | 140 | 3.38k | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 141 | 3.38k | }; | 142 | 3.38k | if (unsigned Reg3.38k = State.AllocateReg(RegList1, RegList2)) { | 143 | 3.32k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 144 | 3.32k | return false; | 145 | 3.32k | } | 146 | 3.38k | } | 147 | 18.1k | | 148 | 14.7k | if (14.7k LocVT == MVT::i6414.7k ) { | 149 | 5.63k | if (ArgFlags.isSplit()5.63k ) { | 150 | 122 | static const MCPhysReg RegList3[] = { | 151 | 122 | AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6 | 152 | 122 | }; | 153 | 122 | static const MCPhysReg RegList4[] = { | 154 | 122 | AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5 | 155 | 122 | }; | 156 | 122 | if (unsigned Reg122 = State.AllocateReg(RegList3, RegList4)) { | 157 | 73 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 158 | 73 | return false; | 159 | 73 | } | 160 | 122 | } | 161 | 5.63k | } | 162 | 14.7k | | 163 | 14.7k | if (14.7k LocVT == MVT::i6414.7k ) { | 164 | 5.55k | if (ArgFlags.isSplit()5.55k ) { | 165 | 49 | static const MCPhysReg ShadowRegList5[] = { | 166 | 49 | AArch64::X7 | 167 | 49 | }; | 168 | 49 | unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5); | 169 | 49 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); | 170 | 49 | return false; | 171 | 49 | } | 172 | 5.55k | } | 173 | 14.7k | | 174 | 14.6k | if (14.6k LocVT == MVT::i6414.6k ) { | 175 | 5.50k | static const MCPhysReg RegList7[] = { | 176 | 5.50k | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 177 | 5.50k | }; | 178 | 5.50k | static const MCPhysReg RegList8[] = { | 179 | 5.50k | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 180 | 5.50k | }; | 181 | 5.50k | if (unsigned Reg5.50k = State.AllocateReg(RegList7, RegList8)) { | 182 | 5.40k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 183 | 5.40k | return false; | 184 | 5.40k | } | 185 | 5.50k | } | 186 | 14.6k | | 187 | 9.25k | if (9.25k LocVT == MVT::f169.25k ) { | 188 | 235 | static const MCPhysReg RegList9[] = { | 189 | 235 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 | 190 | 235 | }; | 191 | 235 | static const MCPhysReg RegList10[] = { | 192 | 235 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 193 | 235 | }; | 194 | 235 | if (unsigned Reg235 = State.AllocateReg(RegList9, RegList10)) { | 195 | 235 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 196 | 235 | return false; | 197 | 235 | } | 198 | 235 | } | 199 | 9.25k | | 200 | 9.02k | if (9.02k LocVT == MVT::f329.02k ) { | 201 | 749 | static const MCPhysReg RegList11[] = { | 202 | 749 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 | 203 | 749 | }; | 204 | 749 | static const MCPhysReg RegList12[] = { | 205 | 749 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 206 | 749 | }; | 207 | 749 | if (unsigned Reg749 = State.AllocateReg(RegList11, RegList12)) { | 208 | 744 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 209 | 744 | return false; | 210 | 744 | } | 211 | 749 | } | 212 | 9.02k | | 213 | 8.27k | if (8.27k LocVT == MVT::f648.27k ) { | 214 | 688 | static const MCPhysReg RegList13[] = { | 215 | 688 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 216 | 688 | }; | 217 | 688 | static const MCPhysReg RegList14[] = { | 218 | 688 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 219 | 688 | }; | 220 | 688 | if (unsigned Reg688 = State.AllocateReg(RegList13, RegList14)) { | 221 | 670 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 222 | 670 | return false; | 223 | 670 | } | 224 | 688 | } | 225 | 8.27k | | 226 | 7.60k | if (7.60k LocVT == MVT::v1i64 || | 227 | 7.43k | LocVT == MVT::v2i32 || | 228 | 6.32k | LocVT == MVT::v4i16 || | 229 | 5.48k | LocVT == MVT::v8i8 || | 230 | 5.02k | LocVT == MVT::v1f64 || | 231 | 4.91k | LocVT == MVT::v2f32 || | 232 | 7.60k | LocVT == MVT::v4f164.91k ) { | 233 | 2.87k | static const MCPhysReg RegList15[] = { | 234 | 2.87k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 235 | 2.87k | }; | 236 | 2.87k | static const MCPhysReg RegList16[] = { | 237 | 2.87k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 238 | 2.87k | }; | 239 | 2.87k | if (unsigned Reg2.87k = State.AllocateReg(RegList15, RegList16)) { | 240 | 2.87k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 241 | 2.87k | return false; | 242 | 2.87k | } | 243 | 2.87k | } | 244 | 7.60k | | 245 | 4.73k | if (4.73k LocVT == MVT::f128 || | 246 | 4.22k | LocVT == MVT::v2i64 || | 247 | 2.82k | LocVT == MVT::v4i32 || | 248 | 1.76k | LocVT == MVT::v8i16 || | 249 | 889 | LocVT == MVT::v16i8 || | 250 | 364 | LocVT == MVT::v4f32 || | 251 | 364 | LocVT == MVT::v2f64 || | 252 | 4.73k | LocVT == MVT::v8f16364 ) { | 253 | 4.54k | static const MCPhysReg RegList17[] = { | 254 | 4.54k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 255 | 4.54k | }; | 256 | 4.54k | if (unsigned Reg4.54k = State.AllocateReg(RegList17)) { | 257 | 4.53k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 258 | 4.53k | return false; | 259 | 4.53k | } | 260 | 4.54k | } | 261 | 4.73k | | 262 | 197 | if (197 LocVT == MVT::i1 || | 263 | 197 | LocVT == MVT::i8 || | 264 | 197 | LocVT == MVT::i16 || | 265 | 197 | LocVT == MVT::f16197 ) { | 266 | 0 | unsigned Offset18 = State.AllocateStack(8, 8); | 267 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo)); | 268 | 0 | return false; | 269 | 0 | } | 270 | 197 | | 271 | 197 | if (197 LocVT == MVT::i32 || | 272 | 197 | LocVT == MVT::f32135 ) { | 273 | 67 | unsigned Offset19 = State.AllocateStack(8, 8); | 274 | 67 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo)); | 275 | 67 | return false; | 276 | 67 | } | 277 | 197 | | 278 | 130 | if (130 LocVT == MVT::i64 || | 279 | 29 | LocVT == MVT::f64 || | 280 | 11 | LocVT == MVT::v1f64 || | 281 | 11 | LocVT == MVT::v2f32 || | 282 | 11 | LocVT == MVT::v1i64 || | 283 | 11 | LocVT == MVT::v2i32 || | 284 | 11 | LocVT == MVT::v4i16 || | 285 | 11 | LocVT == MVT::v8i8 || | 286 | 130 | LocVT == MVT::v4f1611 ) { | 287 | 120 | unsigned Offset20 = State.AllocateStack(8, 8); | 288 | 120 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo)); | 289 | 120 | return false; | 290 | 120 | } | 291 | 130 | | 292 | 10 | if (10 LocVT == MVT::f128 || | 293 | 9 | LocVT == MVT::v2i64 || | 294 | 6 | LocVT == MVT::v4i32 || | 295 | 6 | LocVT == MVT::v8i16 || | 296 | 6 | LocVT == MVT::v16i8 || | 297 | 6 | LocVT == MVT::v4f32 || | 298 | 6 | LocVT == MVT::v2f64 || | 299 | 10 | LocVT == MVT::v8f166 ) { | 300 | 5 | unsigned Offset21 = State.AllocateStack(16, 16); | 301 | 5 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo)); | 302 | 5 | return false; | 303 | 5 | } | 304 | 10 | | 305 | 5 | return true; // CC didn't match. | 306 | 18.5k | } |
|
307 | | |
308 | | |
309 | | static bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, |
310 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
311 | 8.41M | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
312 | 8.41M | |
313 | 8.41M | if (LocVT == MVT::iPTR8.41M ) { |
314 | 0 | LocVT = MVT::i64; |
315 | 0 | LocInfo = CCValAssign::BCvt; |
316 | 0 | } |
317 | 8.41M | |
318 | 8.41M | if (LocVT == MVT::v2f328.41M ) { |
319 | 98 | LocVT = MVT::v2i32; |
320 | 98 | LocInfo = CCValAssign::BCvt; |
321 | 98 | } |
322 | 8.41M | |
323 | 8.41M | if (LocVT == MVT::v2f64 || |
324 | 8.41M | LocVT == MVT::v4f32 || |
325 | 8.41M | LocVT == MVT::f1288.41M ) { |
326 | 257 | LocVT = MVT::v2i64; |
327 | 257 | LocInfo = CCValAssign::BCvt; |
328 | 257 | } |
329 | 8.41M | |
330 | 8.41M | if (ArgFlags.isSRet()8.41M ) { |
331 | 8.03k | if (LocVT == MVT::i648.03k ) { |
332 | 8.03k | if (unsigned Reg8.03k = State.AllocateReg(AArch64::X8, AArch64::W8)) { |
333 | 8.03k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
334 | 8.03k | return false; |
335 | 8.03k | } |
336 | 8.03k | } |
337 | 8.03k | } |
338 | 8.41M | |
339 | 8.41M | if (8.41M ArgFlags.isByVal()8.41M ) { |
340 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); |
341 | 0 | return false; |
342 | 0 | } |
343 | 8.41M | |
344 | 8.41M | if (8.41M ArgFlags.isSwiftSelf()8.41M ) { |
345 | 43 | if (LocVT == MVT::i6443 ) { |
346 | 43 | if (unsigned Reg43 = State.AllocateReg(AArch64::X20, AArch64::W20)) { |
347 | 43 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
348 | 43 | return false; |
349 | 43 | } |
350 | 43 | } |
351 | 43 | } |
352 | 8.41M | |
353 | 8.41M | if (8.41M ArgFlags.isSwiftError()8.41M ) { |
354 | 46 | if (LocVT == MVT::i6446 ) { |
355 | 46 | if (unsigned Reg46 = State.AllocateReg(AArch64::X21, AArch64::W21)) { |
356 | 46 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
357 | 46 | return false; |
358 | 46 | } |
359 | 46 | } |
360 | 46 | } |
361 | 8.41M | |
362 | 8.41M | if (8.41M ArgFlags.isInConsecutiveRegs()8.41M ) { |
363 | 1.38k | if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
364 | 1.38k | return false; |
365 | 1.38k | } |
366 | 8.41M | |
367 | 8.40M | if (8.40M LocVT == MVT::i1 || |
368 | 8.40M | LocVT == MVT::i8 || |
369 | 8.40M | LocVT == MVT::i168.38M ) { |
370 | 40.1k | LocVT = MVT::i32; |
371 | 40.1k | if (ArgFlags.isSExt()) |
372 | 2.85k | LocInfo = CCValAssign::SExt; |
373 | 37.3k | else if (37.3k ArgFlags.isZExt()37.3k ) |
374 | 20.1k | LocInfo = CCValAssign::ZExt; |
375 | 37.3k | else |
376 | 17.1k | LocInfo = CCValAssign::AExt; |
377 | 40.1k | } |
378 | 8.40M | |
379 | 8.40M | if (LocVT == MVT::i328.40M ) { |
380 | 1.14M | static const MCPhysReg RegList1[] = { |
381 | 1.14M | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
382 | 1.14M | }; |
383 | 1.14M | static const MCPhysReg RegList2[] = { |
384 | 1.14M | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
385 | 1.14M | }; |
386 | 1.14M | if (unsigned Reg1.14M = State.AllocateReg(RegList1, RegList2)) { |
387 | 1.14M | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
388 | 1.14M | return false; |
389 | 1.14M | } |
390 | 1.14M | } |
391 | 8.40M | |
392 | 7.26M | if (7.26M LocVT == MVT::i647.26M ) { |
393 | 7.18M | if (ArgFlags.isSplit()7.18M ) { |
394 | 180 | static const MCPhysReg RegList3[] = { |
395 | 180 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6 |
396 | 180 | }; |
397 | 180 | static const MCPhysReg RegList4[] = { |
398 | 180 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6 |
399 | 180 | }; |
400 | 180 | if (unsigned Reg180 = State.AllocateReg(RegList3, RegList4)) { |
401 | 160 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
402 | 160 | return false; |
403 | 160 | } |
404 | 180 | } |
405 | 7.18M | } |
406 | 7.26M | |
407 | 7.26M | if (7.26M LocVT == MVT::i647.26M ) { |
408 | 7.18M | if (ArgFlags.isSplit()7.18M ) { |
409 | 20 | static const MCPhysReg ShadowRegList5[] = { |
410 | 20 | AArch64::X7 |
411 | 20 | }; |
412 | 20 | unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5); |
413 | 20 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); |
414 | 20 | return false; |
415 | 20 | } |
416 | 7.18M | } |
417 | 7.26M | |
418 | 7.26M | if (7.26M LocVT == MVT::i647.26M ) { |
419 | 7.18M | static const MCPhysReg RegList7[] = { |
420 | 7.18M | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
421 | 7.18M | }; |
422 | 7.18M | static const MCPhysReg RegList8[] = { |
423 | 7.18M | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
424 | 7.18M | }; |
425 | 7.18M | if (unsigned Reg7.18M = State.AllocateReg(RegList7, RegList8)) { |
426 | 7.08M | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
427 | 7.08M | return false; |
428 | 7.08M | } |
429 | 7.18M | } |
430 | 7.26M | |
431 | 177k | if (177k LocVT == MVT::f16177k ) { |
432 | 10 | static const MCPhysReg RegList9[] = { |
433 | 10 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 |
434 | 10 | }; |
435 | 10 | static const MCPhysReg RegList10[] = { |
436 | 10 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
437 | 10 | }; |
438 | 10 | if (unsigned Reg10 = State.AllocateReg(RegList9, RegList10)) { |
439 | 10 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
440 | 10 | return false; |
441 | 10 | } |
442 | 10 | } |
443 | 177k | |
444 | 177k | if (177k LocVT == MVT::f32177k ) { |
445 | 2.11k | static const MCPhysReg RegList11[] = { |
446 | 2.11k | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 |
447 | 2.11k | }; |
448 | 2.11k | static const MCPhysReg RegList12[] = { |
449 | 2.11k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
450 | 2.11k | }; |
451 | 2.11k | if (unsigned Reg2.11k = State.AllocateReg(RegList11, RegList12)) { |
452 | 2.10k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
453 | 2.10k | return false; |
454 | 2.10k | } |
455 | 2.11k | } |
456 | 177k | |
457 | 174k | if (174k LocVT == MVT::f64174k ) { |
458 | 73.6k | static const MCPhysReg RegList13[] = { |
459 | 73.6k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
460 | 73.6k | }; |
461 | 73.6k | static const MCPhysReg RegList14[] = { |
462 | 73.6k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
463 | 73.6k | }; |
464 | 73.6k | if (unsigned Reg73.6k = State.AllocateReg(RegList13, RegList14)) { |
465 | 73.6k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
466 | 73.6k | return false; |
467 | 73.6k | } |
468 | 73.6k | } |
469 | 174k | |
470 | 101k | if (101k LocVT == MVT::v1i64 || |
471 | 101k | LocVT == MVT::v2i32 || |
472 | 101k | LocVT == MVT::v4i16 || |
473 | 101k | LocVT == MVT::v8i8 || |
474 | 100k | LocVT == MVT::v1f64 || |
475 | 100k | LocVT == MVT::v2f32 || |
476 | 101k | LocVT == MVT::v4f16100k ) { |
477 | 538 | static const MCPhysReg RegList15[] = { |
478 | 538 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
479 | 538 | }; |
480 | 538 | static const MCPhysReg RegList16[] = { |
481 | 538 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
482 | 538 | }; |
483 | 538 | if (unsigned Reg538 = State.AllocateReg(RegList15, RegList16)) { |
484 | 534 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
485 | 534 | return false; |
486 | 534 | } |
487 | 538 | } |
488 | 101k | |
489 | 100k | if (100k LocVT == MVT::v2i64 || |
490 | 100k | LocVT == MVT::v4i32 || |
491 | 100k | LocVT == MVT::v8i16 || |
492 | 100k | LocVT == MVT::v16i8 || |
493 | 100k | LocVT == MVT::v4f32 || |
494 | 100k | LocVT == MVT::v2f64 || |
495 | 100k | LocVT == MVT::v8f16100k ) { |
496 | 719 | static const MCPhysReg RegList17[] = { |
497 | 719 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
498 | 719 | }; |
499 | 719 | if (unsigned Reg719 = State.AllocateReg(RegList17)) { |
500 | 715 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
501 | 715 | return false; |
502 | 715 | } |
503 | 719 | } |
504 | 100k | |
505 | 100k | if (100k ValVT == MVT::i1 || 100k ValVT == MVT::i8100k ) { |
506 | 87 | unsigned Offset18 = State.AllocateStack(1, 1); |
507 | 87 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo)); |
508 | 87 | return false; |
509 | 87 | } |
510 | 100k | |
511 | 100k | if (100k ValVT == MVT::i16 || 100k ValVT == MVT::f16100k ) { |
512 | 50 | unsigned Offset19 = State.AllocateStack(2, 2); |
513 | 50 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo)); |
514 | 50 | return false; |
515 | 50 | } |
516 | 100k | |
517 | 100k | if (100k LocVT == MVT::i32 || |
518 | 100k | LocVT == MVT::f3297.5k ) { |
519 | 2.48k | unsigned Offset20 = State.AllocateStack(4, 4); |
520 | 2.48k | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo)); |
521 | 2.48k | return false; |
522 | 2.48k | } |
523 | 100k | |
524 | 97.5k | if (97.5k LocVT == MVT::i64 || |
525 | 45 | LocVT == MVT::f64 || |
526 | 8 | LocVT == MVT::v1f64 || |
527 | 8 | LocVT == MVT::v2f32 || |
528 | 8 | LocVT == MVT::v1i64 || |
529 | 8 | LocVT == MVT::v2i32 || |
530 | 4 | LocVT == MVT::v4i16 || |
531 | 4 | LocVT == MVT::v8i8 || |
532 | 97.5k | LocVT == MVT::v4f164 ) { |
533 | 97.5k | unsigned Offset21 = State.AllocateStack(8, 8); |
534 | 97.5k | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo)); |
535 | 97.5k | return false; |
536 | 97.5k | } |
537 | 97.5k | |
538 | 4 | if (4 LocVT == MVT::v2i64 || |
539 | 4 | LocVT == MVT::v4i32 || |
540 | 0 | LocVT == MVT::v8i16 || |
541 | 0 | LocVT == MVT::v16i8 || |
542 | 0 | LocVT == MVT::v4f32 || |
543 | 0 | LocVT == MVT::v2f64 || |
544 | 4 | LocVT == MVT::v8f160 ) { |
545 | 4 | unsigned Offset22 = State.AllocateStack(16, 16); |
546 | 4 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset22, LocVT, LocInfo)); |
547 | 4 | return false; |
548 | 4 | } |
549 | 4 | |
550 | 0 | return true; // CC didn't match. |
551 | 8.41M | } AArch64FastISel.cpp:CC_AArch64_DarwinPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 311 | 1.30k | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 312 | 1.30k | | 313 | 1.30k | if (LocVT == MVT::iPTR1.30k ) { | 314 | 0 | LocVT = MVT::i64; | 315 | 0 | LocInfo = CCValAssign::BCvt; | 316 | 0 | } | 317 | 1.30k | | 318 | 1.30k | if (LocVT == MVT::v2f321.30k ) { | 319 | 0 | LocVT = MVT::v2i32; | 320 | 0 | LocInfo = CCValAssign::BCvt; | 321 | 0 | } | 322 | 1.30k | | 323 | 1.30k | if (LocVT == MVT::v2f64 || | 324 | 1.30k | LocVT == MVT::v4f32 || | 325 | 1.30k | LocVT == MVT::f1281.30k ) { | 326 | 0 | LocVT = MVT::v2i64; | 327 | 0 | LocInfo = CCValAssign::BCvt; | 328 | 0 | } | 329 | 1.30k | | 330 | 1.30k | if (ArgFlags.isSRet()1.30k ) { | 331 | 0 | if (LocVT == MVT::i640 ) { | 332 | 0 | if (unsigned Reg0 = State.AllocateReg(AArch64::X8, AArch64::W8)) { | 333 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 334 | 0 | return false; | 335 | 0 | } | 336 | 0 | } | 337 | 0 | } | 338 | 1.30k | | 339 | 1.30k | if (1.30k ArgFlags.isByVal()1.30k ) { | 340 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); | 341 | 0 | return false; | 342 | 0 | } | 343 | 1.30k | | 344 | 1.30k | if (1.30k ArgFlags.isSwiftSelf()1.30k ) { | 345 | 0 | if (LocVT == MVT::i640 ) { | 346 | 0 | if (unsigned Reg0 = State.AllocateReg(AArch64::X20, AArch64::W20)) { | 347 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 348 | 0 | return false; | 349 | 0 | } | 350 | 0 | } | 351 | 0 | } | 352 | 1.30k | | 353 | 1.30k | if (1.30k ArgFlags.isSwiftError()1.30k ) { | 354 | 0 | if (LocVT == MVT::i640 ) { | 355 | 0 | if (unsigned Reg0 = State.AllocateReg(AArch64::X21, AArch64::W21)) { | 356 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 357 | 0 | return false; | 358 | 0 | } | 359 | 0 | } | 360 | 0 | } | 361 | 1.30k | | 362 | 1.30k | if (1.30k ArgFlags.isInConsecutiveRegs()1.30k ) { | 363 | 0 | if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 364 | 0 | return false; | 365 | 0 | } | 366 | 1.30k | | 367 | 1.30k | if (1.30k LocVT == MVT::i1 || | 368 | 1.28k | LocVT == MVT::i8 || | 369 | 1.30k | LocVT == MVT::i161.23k ) { | 370 | 73 | LocVT = MVT::i32; | 371 | 73 | if (ArgFlags.isSExt()) | 372 | 12 | LocInfo = CCValAssign::SExt; | 373 | 61 | else if (61 ArgFlags.isZExt()61 ) | 374 | 40 | LocInfo = CCValAssign::ZExt; | 375 | 61 | else | 376 | 21 | LocInfo = CCValAssign::AExt; | 377 | 73 | } | 378 | 1.30k | | 379 | 1.30k | if (LocVT == MVT::i321.30k ) { | 380 | 109 | static const MCPhysReg RegList1[] = { | 381 | 109 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 382 | 109 | }; | 383 | 109 | static const MCPhysReg RegList2[] = { | 384 | 109 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 385 | 109 | }; | 386 | 109 | if (unsigned Reg109 = State.AllocateReg(RegList1, RegList2)) { | 387 | 93 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 388 | 93 | return false; | 389 | 93 | } | 390 | 109 | } | 391 | 1.30k | | 392 | 1.21k | if (1.21k LocVT == MVT::i641.21k ) { | 393 | 1.15k | if (ArgFlags.isSplit()1.15k ) { | 394 | 0 | static const MCPhysReg RegList3[] = { | 395 | 0 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6 | 396 | 0 | }; | 397 | 0 | static const MCPhysReg RegList4[] = { | 398 | 0 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6 | 399 | 0 | }; | 400 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList3, RegList4)) { | 401 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 402 | 0 | return false; | 403 | 0 | } | 404 | 0 | } | 405 | 1.15k | } | 406 | 1.21k | | 407 | 1.21k | if (1.21k LocVT == MVT::i641.21k ) { | 408 | 1.15k | if (ArgFlags.isSplit()1.15k ) { | 409 | 0 | static const MCPhysReg ShadowRegList5[] = { | 410 | 0 | AArch64::X7 | 411 | 0 | }; | 412 | 0 | unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5); | 413 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); | 414 | 0 | return false; | 415 | 0 | } | 416 | 1.15k | } | 417 | 1.21k | | 418 | 1.21k | if (1.21k LocVT == MVT::i641.21k ) { | 419 | 1.15k | static const MCPhysReg RegList7[] = { | 420 | 1.15k | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 421 | 1.15k | }; | 422 | 1.15k | static const MCPhysReg RegList8[] = { | 423 | 1.15k | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 424 | 1.15k | }; | 425 | 1.15k | if (unsigned Reg1.15k = State.AllocateReg(RegList7, RegList8)) { | 426 | 125 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 427 | 125 | return false; | 428 | 125 | } | 429 | 1.15k | } | 430 | 1.21k | | 431 | 1.08k | if (1.08k LocVT == MVT::f161.08k ) { | 432 | 0 | static const MCPhysReg RegList9[] = { | 433 | 0 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 | 434 | 0 | }; | 435 | 0 | static const MCPhysReg RegList10[] = { | 436 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 437 | 0 | }; | 438 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList9, RegList10)) { | 439 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 440 | 0 | return false; | 441 | 0 | } | 442 | 0 | } | 443 | 1.08k | | 444 | 1.08k | if (1.08k LocVT == MVT::f321.08k ) { | 445 | 20 | static const MCPhysReg RegList11[] = { | 446 | 20 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 | 447 | 20 | }; | 448 | 20 | static const MCPhysReg RegList12[] = { | 449 | 20 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 450 | 20 | }; | 451 | 20 | if (unsigned Reg20 = State.AllocateReg(RegList11, RegList12)) { | 452 | 20 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 453 | 20 | return false; | 454 | 20 | } | 455 | 20 | } | 456 | 1.08k | | 457 | 1.06k | if (1.06k LocVT == MVT::f641.06k ) { | 458 | 20 | static const MCPhysReg RegList13[] = { | 459 | 20 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 460 | 20 | }; | 461 | 20 | static const MCPhysReg RegList14[] = { | 462 | 20 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 463 | 20 | }; | 464 | 20 | if (unsigned Reg20 = State.AllocateReg(RegList13, RegList14)) { | 465 | 20 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 466 | 20 | return false; | 467 | 20 | } | 468 | 20 | } | 469 | 1.06k | | 470 | 1.04k | if (1.04k LocVT == MVT::v1i64 || | 471 | 1.04k | LocVT == MVT::v2i32 || | 472 | 1.04k | LocVT == MVT::v4i16 || | 473 | 1.04k | LocVT == MVT::v8i8 || | 474 | 1.04k | LocVT == MVT::v1f64 || | 475 | 1.04k | LocVT == MVT::v2f32 || | 476 | 1.04k | LocVT == MVT::v4f161.04k ) { | 477 | 0 | static const MCPhysReg RegList15[] = { | 478 | 0 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 479 | 0 | }; | 480 | 0 | static const MCPhysReg RegList16[] = { | 481 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 482 | 0 | }; | 483 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList15, RegList16)) { | 484 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 485 | 0 | return false; | 486 | 0 | } | 487 | 0 | } | 488 | 1.04k | | 489 | 1.04k | if (1.04k LocVT == MVT::v2i64 || | 490 | 1.04k | LocVT == MVT::v4i32 || | 491 | 1.04k | LocVT == MVT::v8i16 || | 492 | 1.04k | LocVT == MVT::v16i8 || | 493 | 1.04k | LocVT == MVT::v4f32 || | 494 | 1.04k | LocVT == MVT::v2f64 || | 495 | 1.04k | LocVT == MVT::v8f161.04k ) { | 496 | 0 | static const MCPhysReg RegList17[] = { | 497 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 498 | 0 | }; | 499 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList17)) { | 500 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 501 | 0 | return false; | 502 | 0 | } | 503 | 0 | } | 504 | 1.04k | | 505 | 1.04k | if (1.04k ValVT == MVT::i1 || 1.04k ValVT == MVT::i81.04k ) { | 506 | 13 | unsigned Offset18 = State.AllocateStack(1, 1); | 507 | 13 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo)); | 508 | 13 | return false; | 509 | 13 | } | 510 | 1.04k | | 511 | 1.03k | if (1.03k ValVT == MVT::i16 || 1.03k ValVT == MVT::f161.03k ) { | 512 | 1 | unsigned Offset19 = State.AllocateStack(2, 2); | 513 | 1 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo)); | 514 | 1 | return false; | 515 | 1 | } | 516 | 1.03k | | 517 | 1.03k | if (1.03k LocVT == MVT::i32 || | 518 | 1.03k | LocVT == MVT::f321.03k ) { | 519 | 2 | unsigned Offset20 = State.AllocateStack(4, 4); | 520 | 2 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo)); | 521 | 2 | return false; | 522 | 2 | } | 523 | 1.03k | | 524 | 1.03k | if (1.03k LocVT == MVT::i64 || | 525 | 0 | LocVT == MVT::f64 || | 526 | 0 | LocVT == MVT::v1f64 || | 527 | 0 | LocVT == MVT::v2f32 || | 528 | 0 | LocVT == MVT::v1i64 || | 529 | 0 | LocVT == MVT::v2i32 || | 530 | 0 | LocVT == MVT::v4i16 || | 531 | 0 | LocVT == MVT::v8i8 || | 532 | 1.03k | LocVT == MVT::v4f160 ) { | 533 | 1.03k | unsigned Offset21 = State.AllocateStack(8, 8); | 534 | 1.03k | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo)); | 535 | 1.03k | return false; | 536 | 1.03k | } | 537 | 1.03k | | 538 | 0 | if (0 LocVT == MVT::v2i64 || | 539 | 0 | LocVT == MVT::v4i32 || | 540 | 0 | LocVT == MVT::v8i16 || | 541 | 0 | LocVT == MVT::v16i8 || | 542 | 0 | LocVT == MVT::v4f32 || | 543 | 0 | LocVT == MVT::v2f64 || | 544 | 0 | LocVT == MVT::v8f160 ) { | 545 | 0 | unsigned Offset22 = State.AllocateStack(16, 16); | 546 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset22, LocVT, LocInfo)); | 547 | 0 | return false; | 548 | 0 | } | 549 | 0 |
| 550 | 0 | return true; // CC didn't match. | 551 | 1.30k | } |
AArch64ISelLowering.cpp:CC_AArch64_DarwinPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 311 | 8.41M | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 312 | 8.41M | | 313 | 8.41M | if (LocVT == MVT::iPTR8.41M ) { | 314 | 0 | LocVT = MVT::i64; | 315 | 0 | LocInfo = CCValAssign::BCvt; | 316 | 0 | } | 317 | 8.41M | | 318 | 8.41M | if (LocVT == MVT::v2f328.41M ) { | 319 | 98 | LocVT = MVT::v2i32; | 320 | 98 | LocInfo = CCValAssign::BCvt; | 321 | 98 | } | 322 | 8.41M | | 323 | 8.41M | if (LocVT == MVT::v2f64 || | 324 | 8.41M | LocVT == MVT::v4f32 || | 325 | 8.41M | LocVT == MVT::f1288.41M ) { | 326 | 257 | LocVT = MVT::v2i64; | 327 | 257 | LocInfo = CCValAssign::BCvt; | 328 | 257 | } | 329 | 8.41M | | 330 | 8.41M | if (ArgFlags.isSRet()8.41M ) { | 331 | 8.03k | if (LocVT == MVT::i648.03k ) { | 332 | 8.03k | if (unsigned Reg8.03k = State.AllocateReg(AArch64::X8, AArch64::W8)) { | 333 | 8.03k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 334 | 8.03k | return false; | 335 | 8.03k | } | 336 | 8.03k | } | 337 | 8.03k | } | 338 | 8.41M | | 339 | 8.40M | if (8.40M ArgFlags.isByVal()8.40M ) { | 340 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); | 341 | 0 | return false; | 342 | 0 | } | 343 | 8.40M | | 344 | 8.40M | if (8.40M ArgFlags.isSwiftSelf()8.40M ) { | 345 | 43 | if (LocVT == MVT::i6443 ) { | 346 | 43 | if (unsigned Reg43 = State.AllocateReg(AArch64::X20, AArch64::W20)) { | 347 | 43 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 348 | 43 | return false; | 349 | 43 | } | 350 | 43 | } | 351 | 43 | } | 352 | 8.40M | | 353 | 8.40M | if (8.40M ArgFlags.isSwiftError()8.40M ) { | 354 | 46 | if (LocVT == MVT::i6446 ) { | 355 | 46 | if (unsigned Reg46 = State.AllocateReg(AArch64::X21, AArch64::W21)) { | 356 | 46 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 357 | 46 | return false; | 358 | 46 | } | 359 | 46 | } | 360 | 46 | } | 361 | 8.40M | | 362 | 8.40M | if (8.40M ArgFlags.isInConsecutiveRegs()8.40M ) { | 363 | 1.38k | if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 364 | 1.38k | return false; | 365 | 1.38k | } | 366 | 8.40M | | 367 | 8.40M | if (8.40M LocVT == MVT::i1 || | 368 | 8.40M | LocVT == MVT::i8 || | 369 | 8.40M | LocVT == MVT::i168.38M ) { | 370 | 40.1k | LocVT = MVT::i32; | 371 | 40.1k | if (ArgFlags.isSExt()) | 372 | 2.84k | LocInfo = CCValAssign::SExt; | 373 | 37.2k | else if (37.2k ArgFlags.isZExt()37.2k ) | 374 | 20.1k | LocInfo = CCValAssign::ZExt; | 375 | 37.2k | else | 376 | 17.1k | LocInfo = CCValAssign::AExt; | 377 | 40.1k | } | 378 | 8.40M | | 379 | 8.40M | if (LocVT == MVT::i328.40M ) { | 380 | 1.14M | static const MCPhysReg RegList1[] = { | 381 | 1.14M | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 382 | 1.14M | }; | 383 | 1.14M | static const MCPhysReg RegList2[] = { | 384 | 1.14M | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 385 | 1.14M | }; | 386 | 1.14M | if (unsigned Reg1.14M = State.AllocateReg(RegList1, RegList2)) { | 387 | 1.14M | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 388 | 1.14M | return false; | 389 | 1.14M | } | 390 | 1.14M | } | 391 | 8.40M | | 392 | 7.26M | if (7.26M LocVT == MVT::i647.26M ) { | 393 | 7.18M | if (ArgFlags.isSplit()7.18M ) { | 394 | 180 | static const MCPhysReg RegList3[] = { | 395 | 180 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6 | 396 | 180 | }; | 397 | 180 | static const MCPhysReg RegList4[] = { | 398 | 180 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6 | 399 | 180 | }; | 400 | 180 | if (unsigned Reg180 = State.AllocateReg(RegList3, RegList4)) { | 401 | 160 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 402 | 160 | return false; | 403 | 160 | } | 404 | 180 | } | 405 | 7.18M | } | 406 | 7.26M | | 407 | 7.26M | if (7.26M LocVT == MVT::i647.26M ) { | 408 | 7.18M | if (ArgFlags.isSplit()7.18M ) { | 409 | 20 | static const MCPhysReg ShadowRegList5[] = { | 410 | 20 | AArch64::X7 | 411 | 20 | }; | 412 | 20 | unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5); | 413 | 20 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); | 414 | 20 | return false; | 415 | 20 | } | 416 | 7.18M | } | 417 | 7.26M | | 418 | 7.26M | if (7.26M LocVT == MVT::i647.26M ) { | 419 | 7.18M | static const MCPhysReg RegList7[] = { | 420 | 7.18M | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 421 | 7.18M | }; | 422 | 7.18M | static const MCPhysReg RegList8[] = { | 423 | 7.18M | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 424 | 7.18M | }; | 425 | 7.18M | if (unsigned Reg7.18M = State.AllocateReg(RegList7, RegList8)) { | 426 | 7.08M | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 427 | 7.08M | return false; | 428 | 7.08M | } | 429 | 7.18M | } | 430 | 7.26M | | 431 | 176k | if (176k LocVT == MVT::f16176k ) { | 432 | 10 | static const MCPhysReg RegList9[] = { | 433 | 10 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 | 434 | 10 | }; | 435 | 10 | static const MCPhysReg RegList10[] = { | 436 | 10 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 437 | 10 | }; | 438 | 10 | if (unsigned Reg10 = State.AllocateReg(RegList9, RegList10)) { | 439 | 10 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 440 | 10 | return false; | 441 | 10 | } | 442 | 10 | } | 443 | 176k | | 444 | 176k | if (176k LocVT == MVT::f32176k ) { | 445 | 2.09k | static const MCPhysReg RegList11[] = { | 446 | 2.09k | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 | 447 | 2.09k | }; | 448 | 2.09k | static const MCPhysReg RegList12[] = { | 449 | 2.09k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 450 | 2.09k | }; | 451 | 2.09k | if (unsigned Reg2.09k = State.AllocateReg(RegList11, RegList12)) { | 452 | 2.08k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 453 | 2.08k | return false; | 454 | 2.08k | } | 455 | 2.09k | } | 456 | 176k | | 457 | 173k | if (173k LocVT == MVT::f64173k ) { | 458 | 73.6k | static const MCPhysReg RegList13[] = { | 459 | 73.6k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 460 | 73.6k | }; | 461 | 73.6k | static const MCPhysReg RegList14[] = { | 462 | 73.6k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 463 | 73.6k | }; | 464 | 73.6k | if (unsigned Reg73.6k = State.AllocateReg(RegList13, RegList14)) { | 465 | 73.5k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 466 | 73.5k | return false; | 467 | 73.5k | } | 468 | 73.6k | } | 469 | 173k | | 470 | 100k | if (100k LocVT == MVT::v1i64 || | 471 | 100k | LocVT == MVT::v2i32 || | 472 | 100k | LocVT == MVT::v4i16 || | 473 | 99.9k | LocVT == MVT::v8i8 || | 474 | 99.8k | LocVT == MVT::v1f64 || | 475 | 99.8k | LocVT == MVT::v2f32 || | 476 | 100k | LocVT == MVT::v4f1699.8k ) { | 477 | 538 | static const MCPhysReg RegList15[] = { | 478 | 538 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 479 | 538 | }; | 480 | 538 | static const MCPhysReg RegList16[] = { | 481 | 538 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 482 | 538 | }; | 483 | 538 | if (unsigned Reg538 = State.AllocateReg(RegList15, RegList16)) { | 484 | 534 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 485 | 534 | return false; | 486 | 534 | } | 487 | 538 | } | 488 | 100k | | 489 | 99.8k | if (99.8k LocVT == MVT::v2i64 || | 490 | 99.4k | LocVT == MVT::v4i32 || | 491 | 99.3k | LocVT == MVT::v8i16 || | 492 | 99.2k | LocVT == MVT::v16i8 || | 493 | 99.0k | LocVT == MVT::v4f32 || | 494 | 99.0k | LocVT == MVT::v2f64 || | 495 | 99.8k | LocVT == MVT::v8f1699.0k ) { | 496 | 719 | static const MCPhysReg RegList17[] = { | 497 | 719 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 498 | 719 | }; | 499 | 719 | if (unsigned Reg719 = State.AllocateReg(RegList17)) { | 500 | 715 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 501 | 715 | return false; | 502 | 715 | } | 503 | 719 | } | 504 | 99.8k | | 505 | 99.0k | if (99.0k ValVT == MVT::i1 || 99.0k ValVT == MVT::i899.0k ) { | 506 | 74 | unsigned Offset18 = State.AllocateStack(1, 1); | 507 | 74 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo)); | 508 | 74 | return false; | 509 | 74 | } | 510 | 99.0k | | 511 | 99.0k | if (99.0k ValVT == MVT::i16 || 99.0k ValVT == MVT::f1698.9k ) { | 512 | 49 | unsigned Offset19 = State.AllocateStack(2, 2); | 513 | 49 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo)); | 514 | 49 | return false; | 515 | 49 | } | 516 | 99.0k | | 517 | 98.9k | if (98.9k LocVT == MVT::i32 || | 518 | 98.9k | LocVT == MVT::f3296.5k ) { | 519 | 2.47k | unsigned Offset20 = State.AllocateStack(4, 4); | 520 | 2.47k | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo)); | 521 | 2.47k | return false; | 522 | 2.47k | } | 523 | 98.9k | | 524 | 96.4k | if (96.4k LocVT == MVT::i64 || | 525 | 45 | LocVT == MVT::f64 || | 526 | 8 | LocVT == MVT::v1f64 || | 527 | 8 | LocVT == MVT::v2f32 || | 528 | 8 | LocVT == MVT::v1i64 || | 529 | 8 | LocVT == MVT::v2i32 || | 530 | 4 | LocVT == MVT::v4i16 || | 531 | 4 | LocVT == MVT::v8i8 || | 532 | 96.4k | LocVT == MVT::v4f164 ) { | 533 | 96.4k | unsigned Offset21 = State.AllocateStack(8, 8); | 534 | 96.4k | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo)); | 535 | 96.4k | return false; | 536 | 96.4k | } | 537 | 96.4k | | 538 | 4 | if (4 LocVT == MVT::v2i64 || | 539 | 4 | LocVT == MVT::v4i32 || | 540 | 0 | LocVT == MVT::v8i16 || | 541 | 0 | LocVT == MVT::v16i8 || | 542 | 0 | LocVT == MVT::v4f32 || | 543 | 0 | LocVT == MVT::v2f64 || | 544 | 4 | LocVT == MVT::v8f160 ) { | 545 | 4 | unsigned Offset22 = State.AllocateStack(16, 16); | 546 | 4 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset22, LocVT, LocInfo)); | 547 | 4 | return false; | 548 | 4 | } | 549 | 4 | | 550 | 0 | return true; // CC didn't match. | 551 | 8.41M | } |
|
552 | | |
553 | | |
554 | | static bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, |
555 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
556 | 129k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
557 | 129k | |
558 | 129k | if (LocVT == MVT::iPTR129k ) { |
559 | 0 | LocVT = MVT::i64; |
560 | 0 | LocInfo = CCValAssign::BCvt; |
561 | 0 | } |
562 | 129k | |
563 | 129k | if (LocVT == MVT::v2f32129k ) { |
564 | 0 | LocVT = MVT::v2i32; |
565 | 0 | LocInfo = CCValAssign::BCvt; |
566 | 0 | } |
567 | 129k | |
568 | 129k | if (LocVT == MVT::v2f64 || |
569 | 129k | LocVT == MVT::v4f32 || |
570 | 129k | LocVT == MVT::f128129k ) { |
571 | 0 | LocVT = MVT::v2i64; |
572 | 0 | LocInfo = CCValAssign::BCvt; |
573 | 0 | } |
574 | 129k | |
575 | 129k | if (ArgFlags.isInConsecutiveRegs()129k ) { |
576 | 23 | if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
577 | 23 | return false; |
578 | 23 | } |
579 | 129k | |
580 | 129k | if (129k LocVT == MVT::i8 || |
581 | 129k | LocVT == MVT::i16 || |
582 | 129k | LocVT == MVT::i32129k ) { |
583 | 41.2k | LocVT = MVT::i64; |
584 | 41.2k | if (ArgFlags.isSExt()) |
585 | 1 | LocInfo = CCValAssign::SExt; |
586 | 41.2k | else if (41.2k ArgFlags.isZExt()41.2k ) |
587 | 0 | LocInfo = CCValAssign::ZExt; |
588 | 41.2k | else |
589 | 41.2k | LocInfo = CCValAssign::AExt; |
590 | 41.2k | } |
591 | 129k | |
592 | 129k | if (LocVT == MVT::f16 || |
593 | 129k | LocVT == MVT::f32129k ) { |
594 | 2 | LocVT = MVT::f64; |
595 | 2 | LocInfo = CCValAssign::FPExt; |
596 | 2 | } |
597 | 129k | |
598 | 129k | if (LocVT == MVT::i64129k ) { |
599 | 115k | if (ArgFlags.isSplit()115k ) { |
600 | 1 | unsigned Offset1 = State.AllocateStack(8, 16); |
601 | 1 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); |
602 | 1 | return false; |
603 | 1 | } |
604 | 115k | } |
605 | 129k | |
606 | 129k | if (129k LocVT == MVT::i64 || |
607 | 14.4k | LocVT == MVT::f64 || |
608 | 1 | LocVT == MVT::v1i64 || |
609 | 1 | LocVT == MVT::v2i32 || |
610 | 1 | LocVT == MVT::v4i16 || |
611 | 1 | LocVT == MVT::v8i8 || |
612 | 1 | LocVT == MVT::v1f64 || |
613 | 1 | LocVT == MVT::v2f32 || |
614 | 129k | LocVT == MVT::v4f161 ) { |
615 | 129k | unsigned Offset2 = State.AllocateStack(8, 8); |
616 | 129k | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); |
617 | 129k | return false; |
618 | 129k | } |
619 | 129k | |
620 | 1 | if (1 LocVT == MVT::v2i64 || |
621 | 1 | LocVT == MVT::v4i32 || |
622 | 0 | LocVT == MVT::v8i16 || |
623 | 0 | LocVT == MVT::v16i8 || |
624 | 0 | LocVT == MVT::v4f32 || |
625 | 0 | LocVT == MVT::v2f64 || |
626 | 1 | LocVT == MVT::v8f160 ) { |
627 | 1 | unsigned Offset3 = State.AllocateStack(16, 16); |
628 | 1 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); |
629 | 1 | return false; |
630 | 1 | } |
631 | 1 | |
632 | 0 | return true; // CC didn't match. |
633 | 129k | } AArch64ISelLowering.cpp:CC_AArch64_DarwinPCS_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 556 | 129k | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 557 | 129k | | 558 | 129k | if (LocVT == MVT::iPTR129k ) { | 559 | 0 | LocVT = MVT::i64; | 560 | 0 | LocInfo = CCValAssign::BCvt; | 561 | 0 | } | 562 | 129k | | 563 | 129k | if (LocVT == MVT::v2f32129k ) { | 564 | 0 | LocVT = MVT::v2i32; | 565 | 0 | LocInfo = CCValAssign::BCvt; | 566 | 0 | } | 567 | 129k | | 568 | 129k | if (LocVT == MVT::v2f64 || | 569 | 129k | LocVT == MVT::v4f32 || | 570 | 129k | LocVT == MVT::f128129k ) { | 571 | 0 | LocVT = MVT::v2i64; | 572 | 0 | LocInfo = CCValAssign::BCvt; | 573 | 0 | } | 574 | 129k | | 575 | 129k | if (ArgFlags.isInConsecutiveRegs()129k ) { | 576 | 23 | if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 577 | 23 | return false; | 578 | 23 | } | 579 | 129k | | 580 | 129k | if (129k LocVT == MVT::i8 || | 581 | 129k | LocVT == MVT::i16 || | 582 | 129k | LocVT == MVT::i32129k ) { | 583 | 41.2k | LocVT = MVT::i64; | 584 | 41.2k | if (ArgFlags.isSExt()) | 585 | 1 | LocInfo = CCValAssign::SExt; | 586 | 41.2k | else if (41.2k ArgFlags.isZExt()41.2k ) | 587 | 0 | LocInfo = CCValAssign::ZExt; | 588 | 41.2k | else | 589 | 41.2k | LocInfo = CCValAssign::AExt; | 590 | 41.2k | } | 591 | 129k | | 592 | 129k | if (LocVT == MVT::f16 || | 593 | 129k | LocVT == MVT::f32129k ) { | 594 | 2 | LocVT = MVT::f64; | 595 | 2 | LocInfo = CCValAssign::FPExt; | 596 | 2 | } | 597 | 129k | | 598 | 129k | if (LocVT == MVT::i64129k ) { | 599 | 115k | if (ArgFlags.isSplit()115k ) { | 600 | 1 | unsigned Offset1 = State.AllocateStack(8, 16); | 601 | 1 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); | 602 | 1 | return false; | 603 | 1 | } | 604 | 115k | } | 605 | 129k | | 606 | 129k | if (129k LocVT == MVT::i64 || | 607 | 14.4k | LocVT == MVT::f64 || | 608 | 1 | LocVT == MVT::v1i64 || | 609 | 1 | LocVT == MVT::v2i32 || | 610 | 1 | LocVT == MVT::v4i16 || | 611 | 1 | LocVT == MVT::v8i8 || | 612 | 1 | LocVT == MVT::v1f64 || | 613 | 1 | LocVT == MVT::v2f32 || | 614 | 129k | LocVT == MVT::v4f161 ) { | 615 | 129k | unsigned Offset2 = State.AllocateStack(8, 8); | 616 | 129k | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); | 617 | 129k | return false; | 618 | 129k | } | 619 | 129k | | 620 | 1 | if (1 LocVT == MVT::v2i64 || | 621 | 1 | LocVT == MVT::v4i32 || | 622 | 0 | LocVT == MVT::v8i16 || | 623 | 0 | LocVT == MVT::v16i8 || | 624 | 0 | LocVT == MVT::v4f32 || | 625 | 0 | LocVT == MVT::v2f64 || | 626 | 1 | LocVT == MVT::v8f160 ) { | 627 | 1 | unsigned Offset3 = State.AllocateStack(16, 16); | 628 | 1 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); | 629 | 1 | return false; | 630 | 1 | } | 631 | 1 | | 632 | 0 | return true; // CC didn't match. | 633 | 129k | } |
Unexecuted instantiation: AArch64FastISel.cpp:CC_AArch64_DarwinPCS_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
634 | | |
635 | | |
636 | | static bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT, |
637 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
638 | 8 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
639 | 8 | |
640 | 8 | if (LocVT == MVT::iPTR8 ) { |
641 | 0 | LocVT = MVT::i64; |
642 | 0 | LocInfo = CCValAssign::BCvt; |
643 | 0 | } |
644 | 8 | |
645 | 8 | if (LocVT == MVT::v1i64 || |
646 | 8 | LocVT == MVT::v2i32 || |
647 | 8 | LocVT == MVT::v4i16 || |
648 | 8 | LocVT == MVT::v8i8 || |
649 | 8 | LocVT == MVT::v2f328 ) { |
650 | 0 | LocVT = MVT::f64; |
651 | 0 | LocInfo = CCValAssign::BCvt; |
652 | 0 | } |
653 | 8 | |
654 | 8 | if (LocVT == MVT::v2i64 || |
655 | 8 | LocVT == MVT::v4i32 || |
656 | 8 | LocVT == MVT::v8i16 || |
657 | 8 | LocVT == MVT::v16i8 || |
658 | 8 | LocVT == MVT::v4f32 || |
659 | 8 | LocVT == MVT::f1288 ) { |
660 | 0 | LocVT = MVT::v2f64; |
661 | 0 | LocInfo = CCValAssign::BCvt; |
662 | 0 | } |
663 | 8 | |
664 | 8 | if (LocVT == MVT::v2f648 ) { |
665 | 0 | static const MCPhysReg RegList1[] = { |
666 | 0 | AArch64::Q4, AArch64::Q5 |
667 | 0 | }; |
668 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList1)) { |
669 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
670 | 0 | return false; |
671 | 0 | } |
672 | 0 | } |
673 | 8 | |
674 | 8 | if (8 LocVT == MVT::f328 ) { |
675 | 2 | static const MCPhysReg RegList2[] = { |
676 | 2 | AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11 |
677 | 2 | }; |
678 | 2 | if (unsigned Reg2 = State.AllocateReg(RegList2)) { |
679 | 2 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
680 | 2 | return false; |
681 | 2 | } |
682 | 2 | } |
683 | 8 | |
684 | 6 | if (6 LocVT == MVT::f646 ) { |
685 | 1 | static const MCPhysReg RegList3[] = { |
686 | 1 | AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15 |
687 | 1 | }; |
688 | 1 | if (unsigned Reg1 = State.AllocateReg(RegList3)) { |
689 | 1 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
690 | 1 | return false; |
691 | 1 | } |
692 | 1 | } |
693 | 6 | |
694 | 5 | if (5 LocVT == MVT::i8 || |
695 | 5 | LocVT == MVT::i16 || |
696 | 5 | LocVT == MVT::i325 ) { |
697 | 0 | LocVT = MVT::i64; |
698 | 0 | if (ArgFlags.isSExt()) |
699 | 0 | LocInfo = CCValAssign::SExt; |
700 | 0 | else if (0 ArgFlags.isZExt()0 ) |
701 | 0 | LocInfo = CCValAssign::ZExt; |
702 | 0 | else |
703 | 0 | LocInfo = CCValAssign::AExt; |
704 | 0 | } |
705 | 5 | |
706 | 5 | if (LocVT == MVT::i645 ) { |
707 | 5 | static const MCPhysReg RegList4[] = { |
708 | 5 | AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28 |
709 | 5 | }; |
710 | 5 | if (unsigned Reg5 = State.AllocateReg(RegList4)) { |
711 | 5 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
712 | 5 | return false; |
713 | 5 | } |
714 | 5 | } |
715 | 5 | |
716 | 0 | return true; // CC didn't match. |
717 | 8 | } AArch64ISelLowering.cpp:CC_AArch64_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 638 | 8 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 639 | 8 | | 640 | 8 | if (LocVT == MVT::iPTR8 ) { | 641 | 0 | LocVT = MVT::i64; | 642 | 0 | LocInfo = CCValAssign::BCvt; | 643 | 0 | } | 644 | 8 | | 645 | 8 | if (LocVT == MVT::v1i64 || | 646 | 8 | LocVT == MVT::v2i32 || | 647 | 8 | LocVT == MVT::v4i16 || | 648 | 8 | LocVT == MVT::v8i8 || | 649 | 8 | LocVT == MVT::v2f328 ) { | 650 | 0 | LocVT = MVT::f64; | 651 | 0 | LocInfo = CCValAssign::BCvt; | 652 | 0 | } | 653 | 8 | | 654 | 8 | if (LocVT == MVT::v2i64 || | 655 | 8 | LocVT == MVT::v4i32 || | 656 | 8 | LocVT == MVT::v8i16 || | 657 | 8 | LocVT == MVT::v16i8 || | 658 | 8 | LocVT == MVT::v4f32 || | 659 | 8 | LocVT == MVT::f1288 ) { | 660 | 0 | LocVT = MVT::v2f64; | 661 | 0 | LocInfo = CCValAssign::BCvt; | 662 | 0 | } | 663 | 8 | | 664 | 8 | if (LocVT == MVT::v2f648 ) { | 665 | 0 | static const MCPhysReg RegList1[] = { | 666 | 0 | AArch64::Q4, AArch64::Q5 | 667 | 0 | }; | 668 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList1)) { | 669 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 670 | 0 | return false; | 671 | 0 | } | 672 | 0 | } | 673 | 8 | | 674 | 8 | if (8 LocVT == MVT::f328 ) { | 675 | 2 | static const MCPhysReg RegList2[] = { | 676 | 2 | AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11 | 677 | 2 | }; | 678 | 2 | if (unsigned Reg2 = State.AllocateReg(RegList2)) { | 679 | 2 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 680 | 2 | return false; | 681 | 2 | } | 682 | 2 | } | 683 | 8 | | 684 | 6 | if (6 LocVT == MVT::f646 ) { | 685 | 1 | static const MCPhysReg RegList3[] = { | 686 | 1 | AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15 | 687 | 1 | }; | 688 | 1 | if (unsigned Reg1 = State.AllocateReg(RegList3)) { | 689 | 1 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 690 | 1 | return false; | 691 | 1 | } | 692 | 1 | } | 693 | 6 | | 694 | 5 | if (5 LocVT == MVT::i8 || | 695 | 5 | LocVT == MVT::i16 || | 696 | 5 | LocVT == MVT::i325 ) { | 697 | 0 | LocVT = MVT::i64; | 698 | 0 | if (ArgFlags.isSExt()) | 699 | 0 | LocInfo = CCValAssign::SExt; | 700 | 0 | else if (0 ArgFlags.isZExt()0 ) | 701 | 0 | LocInfo = CCValAssign::ZExt; | 702 | 0 | else | 703 | 0 | LocInfo = CCValAssign::AExt; | 704 | 0 | } | 705 | 5 | | 706 | 5 | if (LocVT == MVT::i645 ) { | 707 | 5 | static const MCPhysReg RegList4[] = { | 708 | 5 | AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28 | 709 | 5 | }; | 710 | 5 | if (unsigned Reg5 = State.AllocateReg(RegList4)) { | 711 | 5 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 712 | 5 | return false; | 713 | 5 | } | 714 | 5 | } | 715 | 5 | | 716 | 0 | return true; // CC didn't match. | 717 | 8 | } |
Unexecuted instantiation: AArch64FastISel.cpp:CC_AArch64_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
718 | | |
719 | | |
720 | | static bool CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, |
721 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
722 | 129 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
723 | 129 | |
724 | 129 | if (LocVT == MVT::i1 || |
725 | 129 | LocVT == MVT::i8 || |
726 | 129 | LocVT == MVT::i16129 ) { |
727 | 6 | LocVT = MVT::i32; |
728 | 6 | if (ArgFlags.isSExt()) |
729 | 0 | LocInfo = CCValAssign::SExt; |
730 | 6 | else if (6 ArgFlags.isZExt()6 ) |
731 | 6 | LocInfo = CCValAssign::ZExt; |
732 | 6 | else |
733 | 0 | LocInfo = CCValAssign::AExt; |
734 | 6 | } |
735 | 129 | |
736 | 129 | if (LocVT == MVT::i32129 ) { |
737 | 27 | if (unsigned Reg27 = State.AllocateReg(AArch64::W0, AArch64::X0)) { |
738 | 3 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
739 | 3 | return false; |
740 | 3 | } |
741 | 27 | } |
742 | 129 | |
743 | 126 | if (126 LocVT == MVT::i64126 ) { |
744 | 102 | if (unsigned Reg102 = State.AllocateReg(AArch64::X0, AArch64::W0)) { |
745 | 17 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
746 | 17 | return false; |
747 | 17 | } |
748 | 102 | } |
749 | 126 | |
750 | 109 | if (109 LocVT == MVT::i32 || |
751 | 109 | LocVT == MVT::f3285 ) { |
752 | 24 | unsigned Offset1 = State.AllocateStack(4, 4); |
753 | 24 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); |
754 | 24 | return false; |
755 | 24 | } |
756 | 109 | |
757 | 85 | if (85 LocVT == MVT::i64 || |
758 | 85 | LocVT == MVT::f640 ) { |
759 | 85 | unsigned Offset2 = State.AllocateStack(8, 8); |
760 | 85 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); |
761 | 85 | return false; |
762 | 85 | } |
763 | 85 | |
764 | 0 | return true; // CC didn't match. |
765 | 129 | } AArch64FastISel.cpp:CC_AArch64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 722 | 23 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 723 | 23 | | 724 | 23 | if (LocVT == MVT::i1 || | 725 | 23 | LocVT == MVT::i8 || | 726 | 23 | LocVT == MVT::i1623 ) { | 727 | 0 | LocVT = MVT::i32; | 728 | 0 | if (ArgFlags.isSExt()) | 729 | 0 | LocInfo = CCValAssign::SExt; | 730 | 0 | else if (0 ArgFlags.isZExt()0 ) | 731 | 0 | LocInfo = CCValAssign::ZExt; | 732 | 0 | else | 733 | 0 | LocInfo = CCValAssign::AExt; | 734 | 0 | } | 735 | 23 | | 736 | 23 | if (LocVT == MVT::i3223 ) { | 737 | 7 | if (unsigned Reg7 = State.AllocateReg(AArch64::W0, AArch64::X0)) { | 738 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 739 | 0 | return false; | 740 | 0 | } | 741 | 7 | } | 742 | 23 | | 743 | 23 | if (23 LocVT == MVT::i6423 ) { | 744 | 16 | if (unsigned Reg16 = State.AllocateReg(AArch64::X0, AArch64::W0)) { | 745 | 7 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 746 | 7 | return false; | 747 | 7 | } | 748 | 16 | } | 749 | 23 | | 750 | 16 | if (16 LocVT == MVT::i32 || | 751 | 16 | LocVT == MVT::f329 ) { | 752 | 7 | unsigned Offset1 = State.AllocateStack(4, 4); | 753 | 7 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); | 754 | 7 | return false; | 755 | 7 | } | 756 | 16 | | 757 | 9 | if (9 LocVT == MVT::i64 || | 758 | 9 | LocVT == MVT::f640 ) { | 759 | 9 | unsigned Offset2 = State.AllocateStack(8, 8); | 760 | 9 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); | 761 | 9 | return false; | 762 | 9 | } | 763 | 9 | | 764 | 0 | return true; // CC didn't match. | 765 | 23 | } |
AArch64ISelLowering.cpp:CC_AArch64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 722 | 106 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 723 | 106 | | 724 | 106 | if (LocVT == MVT::i1 || | 725 | 106 | LocVT == MVT::i8 || | 726 | 106 | LocVT == MVT::i16106 ) { | 727 | 6 | LocVT = MVT::i32; | 728 | 6 | if (ArgFlags.isSExt()) | 729 | 0 | LocInfo = CCValAssign::SExt; | 730 | 6 | else if (6 ArgFlags.isZExt()6 ) | 731 | 6 | LocInfo = CCValAssign::ZExt; | 732 | 6 | else | 733 | 0 | LocInfo = CCValAssign::AExt; | 734 | 6 | } | 735 | 106 | | 736 | 106 | if (LocVT == MVT::i32106 ) { | 737 | 20 | if (unsigned Reg20 = State.AllocateReg(AArch64::W0, AArch64::X0)) { | 738 | 3 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 739 | 3 | return false; | 740 | 3 | } | 741 | 20 | } | 742 | 106 | | 743 | 103 | if (103 LocVT == MVT::i64103 ) { | 744 | 86 | if (unsigned Reg86 = State.AllocateReg(AArch64::X0, AArch64::W0)) { | 745 | 10 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 746 | 10 | return false; | 747 | 10 | } | 748 | 86 | } | 749 | 103 | | 750 | 93 | if (93 LocVT == MVT::i32 || | 751 | 93 | LocVT == MVT::f3276 ) { | 752 | 17 | unsigned Offset1 = State.AllocateStack(4, 4); | 753 | 17 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); | 754 | 17 | return false; | 755 | 17 | } | 756 | 93 | | 757 | 76 | if (76 LocVT == MVT::i64 || | 758 | 76 | LocVT == MVT::f640 ) { | 759 | 76 | unsigned Offset2 = State.AllocateStack(8, 8); | 760 | 76 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); | 761 | 76 | return false; | 762 | 76 | } | 763 | 76 | | 764 | 0 | return true; // CC didn't match. | 765 | 106 | } |
|
766 | | |
767 | | |
768 | | static bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, |
769 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
770 | 19 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
771 | 19 | |
772 | 19 | if (LocVT == MVT::f16 || |
773 | 19 | LocVT == MVT::f3219 ) { |
774 | 0 | LocVT = MVT::f64; |
775 | 0 | LocInfo = CCValAssign::FPExt; |
776 | 0 | } |
777 | 19 | |
778 | 19 | if (LocVT == MVT::f6419 ) { |
779 | 10 | LocVT = MVT::i64; |
780 | 10 | LocInfo = CCValAssign::BCvt; |
781 | 10 | } |
782 | 19 | |
783 | 19 | if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
784 | 19 | return false; |
785 | 19 | |
786 | 0 | return true; // CC didn't match. |
787 | 19 | } AArch64ISelLowering.cpp:CC_AArch64_Win64_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 770 | 19 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 771 | 19 | | 772 | 19 | if (LocVT == MVT::f16 || | 773 | 19 | LocVT == MVT::f3219 ) { | 774 | 0 | LocVT = MVT::f64; | 775 | 0 | LocInfo = CCValAssign::FPExt; | 776 | 0 | } | 777 | 19 | | 778 | 19 | if (LocVT == MVT::f6419 ) { | 779 | 10 | LocVT = MVT::i64; | 780 | 10 | LocInfo = CCValAssign::BCvt; | 781 | 10 | } | 782 | 19 | | 783 | 19 | if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 784 | 19 | return false; | 785 | 19 | | 786 | 0 | return true; // CC didn't match. | 787 | 19 | } |
Unexecuted instantiation: AArch64FastISel.cpp:CC_AArch64_Win64_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
788 | | |
789 | | |
790 | | static bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, |
791 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
792 | 3.69M | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
793 | 3.69M | |
794 | 3.69M | if (LocVT == MVT::iPTR3.69M ) { |
795 | 0 | LocVT = MVT::i64; |
796 | 0 | LocInfo = CCValAssign::BCvt; |
797 | 0 | } |
798 | 3.69M | |
799 | 3.69M | if (LocVT == MVT::v2f323.69M ) { |
800 | 675 | LocVT = MVT::v2i32; |
801 | 675 | LocInfo = CCValAssign::BCvt; |
802 | 675 | } |
803 | 3.69M | |
804 | 3.69M | if (LocVT == MVT::v2f64 || |
805 | 3.69M | LocVT == MVT::v4f323.69M ) { |
806 | 1.60k | LocVT = MVT::v2i64; |
807 | 1.60k | LocInfo = CCValAssign::BCvt; |
808 | 1.60k | } |
809 | 3.69M | |
810 | 3.69M | if (ArgFlags.isSwiftError()3.69M ) { |
811 | 50 | if (LocVT == MVT::i6450 ) { |
812 | 50 | if (unsigned Reg50 = State.AllocateReg(AArch64::X21, AArch64::W21)) { |
813 | 50 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
814 | 50 | return false; |
815 | 50 | } |
816 | 50 | } |
817 | 50 | } |
818 | 3.69M | |
819 | 3.69M | if (3.69M State.getMachineFunction().getDataLayout().isBigEndian()3.69M ) { |
820 | 1.34k | if (LocVT == MVT::v2i32 || |
821 | 1.22k | LocVT == MVT::v2f32 || |
822 | 1.22k | LocVT == MVT::v4i16 || |
823 | 1.16k | LocVT == MVT::v4f16 || |
824 | 1.34k | LocVT == MVT::v8i81.16k ) { |
825 | 240 | LocVT = MVT::f64; |
826 | 240 | LocInfo = CCValAssign::BCvt; |
827 | 240 | } |
828 | 1.34k | } |
829 | 3.69M | |
830 | 3.69M | if (State.getMachineFunction().getDataLayout().isBigEndian()3.69M ) { |
831 | 1.34k | if (LocVT == MVT::v2i64 || |
832 | 1.16k | LocVT == MVT::v2f64 || |
833 | 1.16k | LocVT == MVT::v4i32 || |
834 | 1.10k | LocVT == MVT::v4f32 || |
835 | 1.10k | LocVT == MVT::v8i16 || |
836 | 1.04k | LocVT == MVT::v8f16 || |
837 | 1.34k | LocVT == MVT::v16i81.04k ) { |
838 | 360 | LocVT = MVT::f128; |
839 | 360 | LocInfo = CCValAssign::BCvt; |
840 | 360 | } |
841 | 1.34k | } |
842 | 3.69M | |
843 | 3.69M | if (LocVT == MVT::i1 || |
844 | 3.66M | LocVT == MVT::i8 || |
845 | 3.69M | LocVT == MVT::i163.66M ) { |
846 | 24.7k | LocVT = MVT::i32; |
847 | 24.7k | if (ArgFlags.isSExt()) |
848 | 222 | LocInfo = CCValAssign::SExt; |
849 | 24.5k | else if (24.5k ArgFlags.isZExt()24.5k ) |
850 | 24.5k | LocInfo = CCValAssign::ZExt; |
851 | 24.5k | else |
852 | 2 | LocInfo = CCValAssign::AExt; |
853 | 24.7k | } |
854 | 3.69M | |
855 | 3.69M | if (LocVT == MVT::i323.69M ) { |
856 | 1.42M | static const MCPhysReg RegList1[] = { |
857 | 1.42M | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
858 | 1.42M | }; |
859 | 1.42M | static const MCPhysReg RegList2[] = { |
860 | 1.42M | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
861 | 1.42M | }; |
862 | 1.42M | if (unsigned Reg1.42M = State.AllocateReg(RegList1, RegList2)) { |
863 | 1.42M | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
864 | 1.42M | return false; |
865 | 1.42M | } |
866 | 1.42M | } |
867 | 3.69M | |
868 | 2.26M | if (2.26M LocVT == MVT::i642.26M ) { |
869 | 2.22M | static const MCPhysReg RegList3[] = { |
870 | 2.22M | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
871 | 2.22M | }; |
872 | 2.22M | static const MCPhysReg RegList4[] = { |
873 | 2.22M | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
874 | 2.22M | }; |
875 | 2.22M | if (unsigned Reg2.22M = State.AllocateReg(RegList3, RegList4)) { |
876 | 2.22M | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
877 | 2.22M | return false; |
878 | 2.22M | } |
879 | 2.22M | } |
880 | 2.26M | |
881 | 47.9k | if (47.9k LocVT == MVT::f1647.9k ) { |
882 | 284 | static const MCPhysReg RegList5[] = { |
883 | 284 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 |
884 | 284 | }; |
885 | 284 | static const MCPhysReg RegList6[] = { |
886 | 284 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
887 | 284 | }; |
888 | 284 | if (unsigned Reg284 = State.AllocateReg(RegList5, RegList6)) { |
889 | 284 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
890 | 284 | return false; |
891 | 284 | } |
892 | 284 | } |
893 | 47.9k | |
894 | 47.6k | if (47.6k LocVT == MVT::f3247.6k ) { |
895 | 13.9k | static const MCPhysReg RegList7[] = { |
896 | 13.9k | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 |
897 | 13.9k | }; |
898 | 13.9k | static const MCPhysReg RegList8[] = { |
899 | 13.9k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
900 | 13.9k | }; |
901 | 13.9k | if (unsigned Reg13.9k = State.AllocateReg(RegList7, RegList8)) { |
902 | 13.9k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
903 | 13.9k | return false; |
904 | 13.9k | } |
905 | 13.9k | } |
906 | 47.6k | |
907 | 33.7k | if (33.7k LocVT == MVT::f6433.7k ) { |
908 | 20.9k | static const MCPhysReg RegList9[] = { |
909 | 20.9k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
910 | 20.9k | }; |
911 | 20.9k | static const MCPhysReg RegList10[] = { |
912 | 20.9k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
913 | 20.9k | }; |
914 | 20.9k | if (unsigned Reg20.9k = State.AllocateReg(RegList9, RegList10)) { |
915 | 20.9k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
916 | 20.9k | return false; |
917 | 20.9k | } |
918 | 20.9k | } |
919 | 33.7k | |
920 | 12.7k | if (12.7k LocVT == MVT::v1i64 || |
921 | 12.3k | LocVT == MVT::v2i32 || |
922 | 10.6k | LocVT == MVT::v4i16 || |
923 | 9.44k | LocVT == MVT::v8i8 || |
924 | 8.42k | LocVT == MVT::v1f64 || |
925 | 8.14k | LocVT == MVT::v2f32 || |
926 | 12.7k | LocVT == MVT::v4f168.14k ) { |
927 | 4.87k | static const MCPhysReg RegList11[] = { |
928 | 4.87k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
929 | 4.87k | }; |
930 | 4.87k | static const MCPhysReg RegList12[] = { |
931 | 4.87k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
932 | 4.87k | }; |
933 | 4.87k | if (unsigned Reg4.87k = State.AllocateReg(RegList11, RegList12)) { |
934 | 4.87k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
935 | 4.87k | return false; |
936 | 4.87k | } |
937 | 4.87k | } |
938 | 12.7k | |
939 | 7.91k | if (7.91k LocVT == MVT::f128 || |
940 | 7.21k | LocVT == MVT::v2i64 || |
941 | 4.42k | LocVT == MVT::v4i32 || |
942 | 2.59k | LocVT == MVT::v8i16 || |
943 | 1.23k | LocVT == MVT::v16i8 || |
944 | 242 | LocVT == MVT::v4f32 || |
945 | 242 | LocVT == MVT::v2f64 || |
946 | 7.91k | LocVT == MVT::v8f16242 ) { |
947 | 7.90k | static const MCPhysReg RegList13[] = { |
948 | 7.90k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
949 | 7.90k | }; |
950 | 7.90k | if (unsigned Reg7.90k = State.AllocateReg(RegList13)) { |
951 | 7.90k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
952 | 7.90k | return false; |
953 | 7.90k | } |
954 | 7.90k | } |
955 | 7.91k | |
956 | 12 | return true; // CC didn't match. |
957 | 3.69M | } AArch64ISelLowering.cpp:RetCC_AArch64_AAPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 792 | 3.69M | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 793 | 3.69M | | 794 | 3.69M | if (LocVT == MVT::iPTR3.69M ) { | 795 | 0 | LocVT = MVT::i64; | 796 | 0 | LocInfo = CCValAssign::BCvt; | 797 | 0 | } | 798 | 3.69M | | 799 | 3.69M | if (LocVT == MVT::v2f323.69M ) { | 800 | 666 | LocVT = MVT::v2i32; | 801 | 666 | LocInfo = CCValAssign::BCvt; | 802 | 666 | } | 803 | 3.69M | | 804 | 3.69M | if (LocVT == MVT::v2f64 || | 805 | 3.69M | LocVT == MVT::v4f323.69M ) { | 806 | 1.58k | LocVT = MVT::v2i64; | 807 | 1.58k | LocInfo = CCValAssign::BCvt; | 808 | 1.58k | } | 809 | 3.69M | | 810 | 3.69M | if (ArgFlags.isSwiftError()3.69M ) { | 811 | 50 | if (LocVT == MVT::i6450 ) { | 812 | 50 | if (unsigned Reg50 = State.AllocateReg(AArch64::X21, AArch64::W21)) { | 813 | 50 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 814 | 50 | return false; | 815 | 50 | } | 816 | 50 | } | 817 | 50 | } | 818 | 3.69M | | 819 | 3.69M | if (3.69M State.getMachineFunction().getDataLayout().isBigEndian()3.69M ) { | 820 | 1.24k | if (LocVT == MVT::v2i32 || | 821 | 1.13k | LocVT == MVT::v2f32 || | 822 | 1.13k | LocVT == MVT::v4i16 || | 823 | 1.08k | LocVT == MVT::v4f16 || | 824 | 1.24k | LocVT == MVT::v8i81.08k ) { | 825 | 216 | LocVT = MVT::f64; | 826 | 216 | LocInfo = CCValAssign::BCvt; | 827 | 216 | } | 828 | 1.24k | } | 829 | 3.69M | | 830 | 3.69M | if (State.getMachineFunction().getDataLayout().isBigEndian()3.69M ) { | 831 | 1.24k | if (LocVT == MVT::v2i64 || | 832 | 1.08k | LocVT == MVT::v2f64 || | 833 | 1.08k | LocVT == MVT::v4i32 || | 834 | 1.03k | LocVT == MVT::v4f32 || | 835 | 1.03k | LocVT == MVT::v8i16 || | 836 | 977 | LocVT == MVT::v8f16 || | 837 | 1.24k | LocVT == MVT::v16i8977 ) { | 838 | 324 | LocVT = MVT::f128; | 839 | 324 | LocInfo = CCValAssign::BCvt; | 840 | 324 | } | 841 | 1.24k | } | 842 | 3.69M | | 843 | 3.69M | if (LocVT == MVT::i1 || | 844 | 3.66M | LocVT == MVT::i8 || | 845 | 3.69M | LocVT == MVT::i163.66M ) { | 846 | 24.7k | LocVT = MVT::i32; | 847 | 24.7k | if (ArgFlags.isSExt()) | 848 | 222 | LocInfo = CCValAssign::SExt; | 849 | 24.5k | else if (24.5k ArgFlags.isZExt()24.5k ) | 850 | 24.5k | LocInfo = CCValAssign::ZExt; | 851 | 24.5k | else | 852 | 2 | LocInfo = CCValAssign::AExt; | 853 | 24.7k | } | 854 | 3.69M | | 855 | 3.69M | if (LocVT == MVT::i323.69M ) { | 856 | 1.42M | static const MCPhysReg RegList1[] = { | 857 | 1.42M | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 858 | 1.42M | }; | 859 | 1.42M | static const MCPhysReg RegList2[] = { | 860 | 1.42M | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 861 | 1.42M | }; | 862 | 1.42M | if (unsigned Reg1.42M = State.AllocateReg(RegList1, RegList2)) { | 863 | 1.42M | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 864 | 1.42M | return false; | 865 | 1.42M | } | 866 | 1.42M | } | 867 | 3.69M | | 868 | 2.26M | if (2.26M LocVT == MVT::i642.26M ) { | 869 | 2.22M | static const MCPhysReg RegList3[] = { | 870 | 2.22M | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 871 | 2.22M | }; | 872 | 2.22M | static const MCPhysReg RegList4[] = { | 873 | 2.22M | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 874 | 2.22M | }; | 875 | 2.22M | if (unsigned Reg2.22M = State.AllocateReg(RegList3, RegList4)) { | 876 | 2.22M | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 877 | 2.22M | return false; | 878 | 2.22M | } | 879 | 2.22M | } | 880 | 2.26M | | 881 | 47.7k | if (47.7k LocVT == MVT::f1647.7k ) { | 882 | 274 | static const MCPhysReg RegList5[] = { | 883 | 274 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 | 884 | 274 | }; | 885 | 274 | static const MCPhysReg RegList6[] = { | 886 | 274 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 887 | 274 | }; | 888 | 274 | if (unsigned Reg274 = State.AllocateReg(RegList5, RegList6)) { | 889 | 274 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 890 | 274 | return false; | 891 | 274 | } | 892 | 274 | } | 893 | 47.7k | | 894 | 47.4k | if (47.4k LocVT == MVT::f3247.4k ) { | 895 | 13.8k | static const MCPhysReg RegList7[] = { | 896 | 13.8k | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 | 897 | 13.8k | }; | 898 | 13.8k | static const MCPhysReg RegList8[] = { | 899 | 13.8k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 900 | 13.8k | }; | 901 | 13.8k | if (unsigned Reg13.8k = State.AllocateReg(RegList7, RegList8)) { | 902 | 13.8k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 903 | 13.8k | return false; | 904 | 13.8k | } | 905 | 13.8k | } | 906 | 47.4k | | 907 | 33.5k | if (33.5k LocVT == MVT::f6433.5k ) { | 908 | 20.8k | static const MCPhysReg RegList9[] = { | 909 | 20.8k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 910 | 20.8k | }; | 911 | 20.8k | static const MCPhysReg RegList10[] = { | 912 | 20.8k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 913 | 20.8k | }; | 914 | 20.8k | if (unsigned Reg20.8k = State.AllocateReg(RegList9, RegList10)) { | 915 | 20.8k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 916 | 20.8k | return false; | 917 | 20.8k | } | 918 | 20.8k | } | 919 | 33.5k | | 920 | 12.7k | if (12.7k LocVT == MVT::v1i64 || | 921 | 12.2k | LocVT == MVT::v2i32 || | 922 | 10.5k | LocVT == MVT::v4i16 || | 923 | 9.37k | LocVT == MVT::v8i8 || | 924 | 8.36k | LocVT == MVT::v1f64 || | 925 | 8.08k | LocVT == MVT::v2f32 || | 926 | 12.7k | LocVT == MVT::v4f168.08k ) { | 927 | 4.85k | static const MCPhysReg RegList11[] = { | 928 | 4.85k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 929 | 4.85k | }; | 930 | 4.85k | static const MCPhysReg RegList12[] = { | 931 | 4.85k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 932 | 4.85k | }; | 933 | 4.85k | if (unsigned Reg4.85k = State.AllocateReg(RegList11, RegList12)) { | 934 | 4.85k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 935 | 4.85k | return false; | 936 | 4.85k | } | 937 | 4.85k | } | 938 | 12.7k | | 939 | 7.85k | if (7.85k LocVT == MVT::f128 || | 940 | 7.19k | LocVT == MVT::v2i64 || | 941 | 4.41k | LocVT == MVT::v4i32 || | 942 | 2.59k | LocVT == MVT::v8i16 || | 943 | 1.23k | LocVT == MVT::v16i8 || | 944 | 242 | LocVT == MVT::v4f32 || | 945 | 242 | LocVT == MVT::v2f64 || | 946 | 7.85k | LocVT == MVT::v8f16242 ) { | 947 | 7.83k | static const MCPhysReg RegList13[] = { | 948 | 7.83k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 949 | 7.83k | }; | 950 | 7.83k | if (unsigned Reg7.83k = State.AllocateReg(RegList13)) { | 951 | 7.83k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 952 | 7.83k | return false; | 953 | 7.83k | } | 954 | 7.83k | } | 955 | 7.85k | | 956 | 12 | return true; // CC didn't match. | 957 | 3.69M | } |
AArch64FastISel.cpp:RetCC_AArch64_AAPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 792 | 1.00k | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 793 | 1.00k | | 794 | 1.00k | if (LocVT == MVT::iPTR1.00k ) { | 795 | 0 | LocVT = MVT::i64; | 796 | 0 | LocInfo = CCValAssign::BCvt; | 797 | 0 | } | 798 | 1.00k | | 799 | 1.00k | if (LocVT == MVT::v2f321.00k ) { | 800 | 9 | LocVT = MVT::v2i32; | 801 | 9 | LocInfo = CCValAssign::BCvt; | 802 | 9 | } | 803 | 1.00k | | 804 | 1.00k | if (LocVT == MVT::v2f64 || | 805 | 1.00k | LocVT == MVT::v4f32994 ) { | 806 | 22 | LocVT = MVT::v2i64; | 807 | 22 | LocInfo = CCValAssign::BCvt; | 808 | 22 | } | 809 | 1.00k | | 810 | 1.00k | if (ArgFlags.isSwiftError()1.00k ) { | 811 | 0 | if (LocVT == MVT::i640 ) { | 812 | 0 | if (unsigned Reg0 = State.AllocateReg(AArch64::X21, AArch64::W21)) { | 813 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 814 | 0 | return false; | 815 | 0 | } | 816 | 0 | } | 817 | 0 | } | 818 | 1.00k | | 819 | 1.00k | if (1.00k State.getMachineFunction().getDataLayout().isBigEndian()1.00k ) { | 820 | 102 | if (LocVT == MVT::v2i32 || | 821 | 90 | LocVT == MVT::v2f32 || | 822 | 90 | LocVT == MVT::v4i16 || | 823 | 84 | LocVT == MVT::v4f16 || | 824 | 102 | LocVT == MVT::v8i884 ) { | 825 | 24 | LocVT = MVT::f64; | 826 | 24 | LocInfo = CCValAssign::BCvt; | 827 | 24 | } | 828 | 102 | } | 829 | 1.00k | | 830 | 1.00k | if (State.getMachineFunction().getDataLayout().isBigEndian()1.00k ) { | 831 | 102 | if (LocVT == MVT::v2i64 || | 832 | 84 | LocVT == MVT::v2f64 || | 833 | 84 | LocVT == MVT::v4i32 || | 834 | 78 | LocVT == MVT::v4f32 || | 835 | 78 | LocVT == MVT::v8i16 || | 836 | 72 | LocVT == MVT::v8f16 || | 837 | 102 | LocVT == MVT::v16i872 ) { | 838 | 36 | LocVT = MVT::f128; | 839 | 36 | LocInfo = CCValAssign::BCvt; | 840 | 36 | } | 841 | 102 | } | 842 | 1.00k | | 843 | 1.00k | if (LocVT == MVT::i1 || | 844 | 1.00k | LocVT == MVT::i8 || | 845 | 1.00k | LocVT == MVT::i161.00k ) { | 846 | 0 | LocVT = MVT::i32; | 847 | 0 | if (ArgFlags.isSExt()) | 848 | 0 | LocInfo = CCValAssign::SExt; | 849 | 0 | else if (0 ArgFlags.isZExt()0 ) | 850 | 0 | LocInfo = CCValAssign::ZExt; | 851 | 0 | else | 852 | 0 | LocInfo = CCValAssign::AExt; | 853 | 0 | } | 854 | 1.00k | | 855 | 1.00k | if (LocVT == MVT::i321.00k ) { | 856 | 554 | static const MCPhysReg RegList1[] = { | 857 | 554 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 858 | 554 | }; | 859 | 554 | static const MCPhysReg RegList2[] = { | 860 | 554 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 861 | 554 | }; | 862 | 554 | if (unsigned Reg554 = State.AllocateReg(RegList1, RegList2)) { | 863 | 554 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 864 | 554 | return false; | 865 | 554 | } | 866 | 554 | } | 867 | 1.00k | | 868 | 450 | if (450 LocVT == MVT::i64450 ) { | 869 | 222 | static const MCPhysReg RegList3[] = { | 870 | 222 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 871 | 222 | }; | 872 | 222 | static const MCPhysReg RegList4[] = { | 873 | 222 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 874 | 222 | }; | 875 | 222 | if (unsigned Reg222 = State.AllocateReg(RegList3, RegList4)) { | 876 | 222 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 877 | 222 | return false; | 878 | 222 | } | 879 | 222 | } | 880 | 450 | | 881 | 228 | if (228 LocVT == MVT::f16228 ) { | 882 | 10 | static const MCPhysReg RegList5[] = { | 883 | 10 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 | 884 | 10 | }; | 885 | 10 | static const MCPhysReg RegList6[] = { | 886 | 10 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 887 | 10 | }; | 888 | 10 | if (unsigned Reg10 = State.AllocateReg(RegList5, RegList6)) { | 889 | 10 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 890 | 10 | return false; | 891 | 10 | } | 892 | 10 | } | 893 | 228 | | 894 | 218 | if (218 LocVT == MVT::f32218 ) { | 895 | 65 | static const MCPhysReg RegList7[] = { | 896 | 65 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 | 897 | 65 | }; | 898 | 65 | static const MCPhysReg RegList8[] = { | 899 | 65 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 900 | 65 | }; | 901 | 65 | if (unsigned Reg65 = State.AllocateReg(RegList7, RegList8)) { | 902 | 65 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 903 | 65 | return false; | 904 | 65 | } | 905 | 65 | } | 906 | 218 | | 907 | 153 | if (153 LocVT == MVT::f64153 ) { | 908 | 68 | static const MCPhysReg RegList9[] = { | 909 | 68 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 910 | 68 | }; | 911 | 68 | static const MCPhysReg RegList10[] = { | 912 | 68 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 913 | 68 | }; | 914 | 68 | if (unsigned Reg68 = State.AllocateReg(RegList9, RegList10)) { | 915 | 68 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 916 | 68 | return false; | 917 | 68 | } | 918 | 68 | } | 919 | 153 | | 920 | 85 | if (85 LocVT == MVT::v1i64 || | 921 | 79 | LocVT == MVT::v2i32 || | 922 | 72 | LocVT == MVT::v4i16 || | 923 | 71 | LocVT == MVT::v8i8 || | 924 | 68 | LocVT == MVT::v1f64 || | 925 | 68 | LocVT == MVT::v2f32 || | 926 | 85 | LocVT == MVT::v4f1668 ) { | 927 | 17 | static const MCPhysReg RegList11[] = { | 928 | 17 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 929 | 17 | }; | 930 | 17 | static const MCPhysReg RegList12[] = { | 931 | 17 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 932 | 17 | }; | 933 | 17 | if (unsigned Reg17 = State.AllocateReg(RegList11, RegList12)) { | 934 | 17 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 935 | 17 | return false; | 936 | 17 | } | 937 | 17 | } | 938 | 85 | | 939 | 68 | if (68 LocVT == MVT::f128 || | 940 | 22 | LocVT == MVT::v2i64 || | 941 | 10 | LocVT == MVT::v4i32 || | 942 | 7 | LocVT == MVT::v8i16 || | 943 | 4 | LocVT == MVT::v16i8 || | 944 | 0 | LocVT == MVT::v4f32 || | 945 | 0 | LocVT == MVT::v2f64 || | 946 | 68 | LocVT == MVT::v8f160 ) { | 947 | 68 | static const MCPhysReg RegList13[] = { | 948 | 68 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 949 | 68 | }; | 950 | 68 | if (unsigned Reg68 = State.AllocateReg(RegList13)) { | 951 | 68 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 952 | 68 | return false; | 953 | 68 | } | 954 | 68 | } | 955 | 68 | | 956 | 0 | return true; // CC didn't match. | 957 | 1.00k | } |
|
958 | | |
959 | | |
960 | | static bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, |
961 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
962 | 21 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
963 | 21 | |
964 | 21 | if (LocVT == MVT::i3221 ) { |
965 | 6 | static const MCPhysReg RegList1[] = { |
966 | 6 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
967 | 6 | }; |
968 | 6 | static const MCPhysReg RegList2[] = { |
969 | 6 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
970 | 6 | }; |
971 | 6 | if (unsigned Reg6 = State.AllocateReg(RegList1, RegList2)) { |
972 | 6 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
973 | 6 | return false; |
974 | 6 | } |
975 | 6 | } |
976 | 21 | |
977 | 15 | if (15 LocVT == MVT::i6415 ) { |
978 | 15 | static const MCPhysReg RegList3[] = { |
979 | 15 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
980 | 15 | }; |
981 | 15 | static const MCPhysReg RegList4[] = { |
982 | 15 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
983 | 15 | }; |
984 | 15 | if (unsigned Reg15 = State.AllocateReg(RegList3, RegList4)) { |
985 | 15 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
986 | 15 | return false; |
987 | 15 | } |
988 | 15 | } |
989 | 15 | |
990 | 0 | if (0 LocVT == MVT::f320 ) { |
991 | 0 | static const MCPhysReg RegList5[] = { |
992 | 0 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 |
993 | 0 | }; |
994 | 0 | static const MCPhysReg RegList6[] = { |
995 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
996 | 0 | }; |
997 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList5, RegList6)) { |
998 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
999 | 0 | return false; |
1000 | 0 | } |
1001 | 0 | } |
1002 | 0 |
|
1003 | 0 | if (0 LocVT == MVT::f640 ) { |
1004 | 0 | static const MCPhysReg RegList7[] = { |
1005 | 0 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
1006 | 0 | }; |
1007 | 0 | static const MCPhysReg RegList8[] = { |
1008 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
1009 | 0 | }; |
1010 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList7, RegList8)) { |
1011 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1012 | 0 | return false; |
1013 | 0 | } |
1014 | 0 | } |
1015 | 0 |
|
1016 | 0 | return true; // CC didn't match. |
1017 | 21 | } AArch64FastISel.cpp:RetCC_AArch64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 962 | 1 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 963 | 1 | | 964 | 1 | if (LocVT == MVT::i321 ) { | 965 | 1 | static const MCPhysReg RegList1[] = { | 966 | 1 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 967 | 1 | }; | 968 | 1 | static const MCPhysReg RegList2[] = { | 969 | 1 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 970 | 1 | }; | 971 | 1 | if (unsigned Reg1 = State.AllocateReg(RegList1, RegList2)) { | 972 | 1 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 973 | 1 | return false; | 974 | 1 | } | 975 | 1 | } | 976 | 1 | | 977 | 0 | if (0 LocVT == MVT::i640 ) { | 978 | 0 | static const MCPhysReg RegList3[] = { | 979 | 0 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 980 | 0 | }; | 981 | 0 | static const MCPhysReg RegList4[] = { | 982 | 0 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 983 | 0 | }; | 984 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList3, RegList4)) { | 985 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 986 | 0 | return false; | 987 | 0 | } | 988 | 0 | } | 989 | 0 |
| 990 | 0 | if (0 LocVT == MVT::f320 ) { | 991 | 0 | static const MCPhysReg RegList5[] = { | 992 | 0 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 | 993 | 0 | }; | 994 | 0 | static const MCPhysReg RegList6[] = { | 995 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 996 | 0 | }; | 997 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList5, RegList6)) { | 998 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 999 | 0 | return false; | 1000 | 0 | } | 1001 | 0 | } | 1002 | 0 |
| 1003 | 0 | if (0 LocVT == MVT::f640 ) { | 1004 | 0 | static const MCPhysReg RegList7[] = { | 1005 | 0 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 1006 | 0 | }; | 1007 | 0 | static const MCPhysReg RegList8[] = { | 1008 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 1009 | 0 | }; | 1010 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList7, RegList8)) { | 1011 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 1012 | 0 | return false; | 1013 | 0 | } | 1014 | 0 | } | 1015 | 0 |
| 1016 | 0 | return true; // CC didn't match. | 1017 | 1 | } |
AArch64ISelLowering.cpp:RetCC_AArch64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 962 | 20 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 963 | 20 | | 964 | 20 | if (LocVT == MVT::i3220 ) { | 965 | 5 | static const MCPhysReg RegList1[] = { | 966 | 5 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 967 | 5 | }; | 968 | 5 | static const MCPhysReg RegList2[] = { | 969 | 5 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 970 | 5 | }; | 971 | 5 | if (unsigned Reg5 = State.AllocateReg(RegList1, RegList2)) { | 972 | 5 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 973 | 5 | return false; | 974 | 5 | } | 975 | 5 | } | 976 | 20 | | 977 | 15 | if (15 LocVT == MVT::i6415 ) { | 978 | 15 | static const MCPhysReg RegList3[] = { | 979 | 15 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 | 980 | 15 | }; | 981 | 15 | static const MCPhysReg RegList4[] = { | 982 | 15 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 | 983 | 15 | }; | 984 | 15 | if (unsigned Reg15 = State.AllocateReg(RegList3, RegList4)) { | 985 | 15 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 986 | 15 | return false; | 987 | 15 | } | 988 | 15 | } | 989 | 15 | | 990 | 0 | if (0 LocVT == MVT::f320 ) { | 991 | 0 | static const MCPhysReg RegList5[] = { | 992 | 0 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 | 993 | 0 | }; | 994 | 0 | static const MCPhysReg RegList6[] = { | 995 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 996 | 0 | }; | 997 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList5, RegList6)) { | 998 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 999 | 0 | return false; | 1000 | 0 | } | 1001 | 0 | } | 1002 | 0 |
| 1003 | 0 | if (0 LocVT == MVT::f640 ) { | 1004 | 0 | static const MCPhysReg RegList7[] = { | 1005 | 0 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 | 1006 | 0 | }; | 1007 | 0 | static const MCPhysReg RegList8[] = { | 1008 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 | 1009 | 0 | }; | 1010 | 0 | if (unsigned Reg0 = State.AllocateReg(RegList7, RegList8)) { | 1011 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 1012 | 0 | return false; | 1013 | 0 | } | 1014 | 0 | } | 1015 | 0 |
| 1016 | 0 | return true; // CC didn't match. | 1017 | 20 | } |
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