/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/clang-build/lib/Target/ARM/ARMGenMCPseudoLowering.inc
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1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Pseudo-instruction MC lowering Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | bool ARMAsmPrinter:: |
10 | | emitPseudoExpansionLowering(MCStreamer &OutStreamer, |
11 | 375k | const MachineInstr *MI) { |
12 | 375k | switch (MI->getOpcode()) { |
13 | 361k | default: return false; |
14 | 217 | case ARM::B: { |
15 | 217 | MCInst TmpInst; |
16 | 217 | MCOperand MCOp; |
17 | 217 | TmpInst.setOpcode(ARM::Bcc); |
18 | 217 | // Operand: target |
19 | 217 | lowerOperand(MI->getOperand(0), MCOp); |
20 | 217 | TmpInst.addOperand(MCOp); |
21 | 217 | // Operand: p |
22 | 217 | TmpInst.addOperand(MCOperand::createImm(14)); |
23 | 217 | TmpInst.addOperand(MCOperand::createReg(0)); |
24 | 217 | EmitToStreamer(OutStreamer, TmpInst); |
25 | 217 | break; |
26 | 375k | } |
27 | 1.36k | case ARM::LDMIA_RET: { |
28 | 1.36k | MCInst TmpInst; |
29 | 1.36k | MCOperand MCOp; |
30 | 1.36k | TmpInst.setOpcode(ARM::LDMIA_UPD); |
31 | 1.36k | // Operand: wb |
32 | 1.36k | lowerOperand(MI->getOperand(0), MCOp); |
33 | 1.36k | TmpInst.addOperand(MCOp); |
34 | 1.36k | // Operand: Rn |
35 | 1.36k | lowerOperand(MI->getOperand(1), MCOp); |
36 | 1.36k | TmpInst.addOperand(MCOp); |
37 | 1.36k | // Operand: p |
38 | 1.36k | lowerOperand(MI->getOperand(2), MCOp); |
39 | 1.36k | TmpInst.addOperand(MCOp); |
40 | 1.36k | lowerOperand(MI->getOperand(3), MCOp); |
41 | 1.36k | TmpInst.addOperand(MCOp); |
42 | 1.36k | // Operand: regs |
43 | 1.36k | lowerOperand(MI->getOperand(4), MCOp); |
44 | 1.36k | TmpInst.addOperand(MCOp); |
45 | 1.36k | // variable_ops |
46 | 5.23k | for (unsigned i = 5, e = MI->getNumOperands(); i != e5.23k ; ++i3.86k ) |
47 | 3.86k | if (3.86k lowerOperand(MI->getOperand(i), MCOp)3.86k ) |
48 | 2.58k | TmpInst.addOperand(MCOp); |
49 | 1.36k | EmitToStreamer(OutStreamer, TmpInst); |
50 | 1.36k | break; |
51 | 375k | } |
52 | 26 | case ARM::MLAv5: { |
53 | 26 | MCInst TmpInst; |
54 | 26 | MCOperand MCOp; |
55 | 26 | TmpInst.setOpcode(ARM::MLA); |
56 | 26 | // Operand: Rd |
57 | 26 | lowerOperand(MI->getOperand(0), MCOp); |
58 | 26 | TmpInst.addOperand(MCOp); |
59 | 26 | // Operand: Rn |
60 | 26 | lowerOperand(MI->getOperand(1), MCOp); |
61 | 26 | TmpInst.addOperand(MCOp); |
62 | 26 | // Operand: Rm |
63 | 26 | lowerOperand(MI->getOperand(2), MCOp); |
64 | 26 | TmpInst.addOperand(MCOp); |
65 | 26 | // Operand: Ra |
66 | 26 | lowerOperand(MI->getOperand(3), MCOp); |
67 | 26 | TmpInst.addOperand(MCOp); |
68 | 26 | // Operand: p |
69 | 26 | lowerOperand(MI->getOperand(4), MCOp); |
70 | 26 | TmpInst.addOperand(MCOp); |
71 | 26 | lowerOperand(MI->getOperand(5), MCOp); |
72 | 26 | TmpInst.addOperand(MCOp); |
73 | 26 | // Operand: s |
74 | 26 | lowerOperand(MI->getOperand(6), MCOp); |
75 | 26 | TmpInst.addOperand(MCOp); |
76 | 26 | EmitToStreamer(OutStreamer, TmpInst); |
77 | 26 | break; |
78 | 375k | } |
79 | 0 | case ARM::MOVPCRX: { |
80 | 0 | MCInst TmpInst; |
81 | 0 | MCOperand MCOp; |
82 | 0 | TmpInst.setOpcode(ARM::MOVr); |
83 | 0 | // Operand: Rd |
84 | 0 | TmpInst.addOperand(MCOperand::createReg(ARM::PC)); |
85 | 0 | // Operand: Rm |
86 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
87 | 0 | TmpInst.addOperand(MCOp); |
88 | 0 | // Operand: p |
89 | 0 | TmpInst.addOperand(MCOperand::createImm(14)); |
90 | 0 | TmpInst.addOperand(MCOperand::createReg(0)); |
91 | 0 | // Operand: s |
92 | 0 | TmpInst.addOperand(MCOperand::createReg(0)); |
93 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
94 | 0 | break; |
95 | 375k | } |
96 | 51 | case ARM::MULv5: { |
97 | 51 | MCInst TmpInst; |
98 | 51 | MCOperand MCOp; |
99 | 51 | TmpInst.setOpcode(ARM::MUL); |
100 | 51 | // Operand: Rd |
101 | 51 | lowerOperand(MI->getOperand(0), MCOp); |
102 | 51 | TmpInst.addOperand(MCOp); |
103 | 51 | // Operand: Rn |
104 | 51 | lowerOperand(MI->getOperand(1), MCOp); |
105 | 51 | TmpInst.addOperand(MCOp); |
106 | 51 | // Operand: Rm |
107 | 51 | lowerOperand(MI->getOperand(2), MCOp); |
108 | 51 | TmpInst.addOperand(MCOp); |
109 | 51 | // Operand: p |
110 | 51 | lowerOperand(MI->getOperand(3), MCOp); |
111 | 51 | TmpInst.addOperand(MCOp); |
112 | 51 | lowerOperand(MI->getOperand(4), MCOp); |
113 | 51 | TmpInst.addOperand(MCOp); |
114 | 51 | // Operand: s |
115 | 51 | lowerOperand(MI->getOperand(5), MCOp); |
116 | 51 | TmpInst.addOperand(MCOp); |
117 | 51 | EmitToStreamer(OutStreamer, TmpInst); |
118 | 51 | break; |
119 | 375k | } |
120 | 9 | case ARM::SMLALv5: { |
121 | 9 | MCInst TmpInst; |
122 | 9 | MCOperand MCOp; |
123 | 9 | TmpInst.setOpcode(ARM::SMLAL); |
124 | 9 | // Operand: RdLo |
125 | 9 | lowerOperand(MI->getOperand(0), MCOp); |
126 | 9 | TmpInst.addOperand(MCOp); |
127 | 9 | // Operand: RdHi |
128 | 9 | lowerOperand(MI->getOperand(1), MCOp); |
129 | 9 | TmpInst.addOperand(MCOp); |
130 | 9 | // Operand: Rn |
131 | 9 | lowerOperand(MI->getOperand(2), MCOp); |
132 | 9 | TmpInst.addOperand(MCOp); |
133 | 9 | // Operand: Rm |
134 | 9 | lowerOperand(MI->getOperand(3), MCOp); |
135 | 9 | TmpInst.addOperand(MCOp); |
136 | 9 | // Operand: RLo |
137 | 9 | lowerOperand(MI->getOperand(4), MCOp); |
138 | 9 | TmpInst.addOperand(MCOp); |
139 | 9 | // Operand: RHi |
140 | 9 | lowerOperand(MI->getOperand(5), MCOp); |
141 | 9 | TmpInst.addOperand(MCOp); |
142 | 9 | // Operand: p |
143 | 9 | lowerOperand(MI->getOperand(6), MCOp); |
144 | 9 | TmpInst.addOperand(MCOp); |
145 | 9 | lowerOperand(MI->getOperand(7), MCOp); |
146 | 9 | TmpInst.addOperand(MCOp); |
147 | 9 | // Operand: s |
148 | 9 | lowerOperand(MI->getOperand(8), MCOp); |
149 | 9 | TmpInst.addOperand(MCOp); |
150 | 9 | EmitToStreamer(OutStreamer, TmpInst); |
151 | 9 | break; |
152 | 375k | } |
153 | 29 | case ARM::SMULLv5: { |
154 | 29 | MCInst TmpInst; |
155 | 29 | MCOperand MCOp; |
156 | 29 | TmpInst.setOpcode(ARM::SMULL); |
157 | 29 | // Operand: RdLo |
158 | 29 | lowerOperand(MI->getOperand(0), MCOp); |
159 | 29 | TmpInst.addOperand(MCOp); |
160 | 29 | // Operand: RdHi |
161 | 29 | lowerOperand(MI->getOperand(1), MCOp); |
162 | 29 | TmpInst.addOperand(MCOp); |
163 | 29 | // Operand: Rn |
164 | 29 | lowerOperand(MI->getOperand(2), MCOp); |
165 | 29 | TmpInst.addOperand(MCOp); |
166 | 29 | // Operand: Rm |
167 | 29 | lowerOperand(MI->getOperand(3), MCOp); |
168 | 29 | TmpInst.addOperand(MCOp); |
169 | 29 | // Operand: p |
170 | 29 | lowerOperand(MI->getOperand(4), MCOp); |
171 | 29 | TmpInst.addOperand(MCOp); |
172 | 29 | lowerOperand(MI->getOperand(5), MCOp); |
173 | 29 | TmpInst.addOperand(MCOp); |
174 | 29 | // Operand: s |
175 | 29 | lowerOperand(MI->getOperand(6), MCOp); |
176 | 29 | TmpInst.addOperand(MCOp); |
177 | 29 | EmitToStreamer(OutStreamer, TmpInst); |
178 | 29 | break; |
179 | 375k | } |
180 | 181 | case ARM::TAILJMPd: { |
181 | 181 | MCInst TmpInst; |
182 | 181 | MCOperand MCOp; |
183 | 181 | TmpInst.setOpcode(ARM::Bcc); |
184 | 181 | // Operand: target |
185 | 181 | lowerOperand(MI->getOperand(0), MCOp); |
186 | 181 | TmpInst.addOperand(MCOp); |
187 | 181 | // Operand: p |
188 | 181 | TmpInst.addOperand(MCOperand::createImm(14)); |
189 | 181 | TmpInst.addOperand(MCOperand::createReg(0)); |
190 | 181 | EmitToStreamer(OutStreamer, TmpInst); |
191 | 181 | break; |
192 | 375k | } |
193 | 6 | case ARM::TAILJMPr: { |
194 | 6 | MCInst TmpInst; |
195 | 6 | MCOperand MCOp; |
196 | 6 | TmpInst.setOpcode(ARM::BX); |
197 | 6 | // Operand: dst |
198 | 6 | lowerOperand(MI->getOperand(0), MCOp); |
199 | 6 | TmpInst.addOperand(MCOp); |
200 | 6 | EmitToStreamer(OutStreamer, TmpInst); |
201 | 6 | break; |
202 | 375k | } |
203 | 3 | case ARM::TAILJMPr4: { |
204 | 3 | MCInst TmpInst; |
205 | 3 | MCOperand MCOp; |
206 | 3 | TmpInst.setOpcode(ARM::MOVr); |
207 | 3 | // Operand: Rd |
208 | 3 | TmpInst.addOperand(MCOperand::createReg(ARM::PC)); |
209 | 3 | // Operand: Rm |
210 | 3 | lowerOperand(MI->getOperand(0), MCOp); |
211 | 3 | TmpInst.addOperand(MCOp); |
212 | 3 | // Operand: p |
213 | 3 | TmpInst.addOperand(MCOperand::createImm(14)); |
214 | 3 | TmpInst.addOperand(MCOperand::createReg(0)); |
215 | 3 | // Operand: s |
216 | 3 | TmpInst.addOperand(MCOperand::createReg(0)); |
217 | 3 | EmitToStreamer(OutStreamer, TmpInst); |
218 | 3 | break; |
219 | 375k | } |
220 | 12 | case ARM::UMLALv5: { |
221 | 12 | MCInst TmpInst; |
222 | 12 | MCOperand MCOp; |
223 | 12 | TmpInst.setOpcode(ARM::UMLAL); |
224 | 12 | // Operand: RdLo |
225 | 12 | lowerOperand(MI->getOperand(0), MCOp); |
226 | 12 | TmpInst.addOperand(MCOp); |
227 | 12 | // Operand: RdHi |
228 | 12 | lowerOperand(MI->getOperand(1), MCOp); |
229 | 12 | TmpInst.addOperand(MCOp); |
230 | 12 | // Operand: Rn |
231 | 12 | lowerOperand(MI->getOperand(2), MCOp); |
232 | 12 | TmpInst.addOperand(MCOp); |
233 | 12 | // Operand: Rm |
234 | 12 | lowerOperand(MI->getOperand(3), MCOp); |
235 | 12 | TmpInst.addOperand(MCOp); |
236 | 12 | // Operand: RLo |
237 | 12 | lowerOperand(MI->getOperand(4), MCOp); |
238 | 12 | TmpInst.addOperand(MCOp); |
239 | 12 | // Operand: RHi |
240 | 12 | lowerOperand(MI->getOperand(5), MCOp); |
241 | 12 | TmpInst.addOperand(MCOp); |
242 | 12 | // Operand: p |
243 | 12 | lowerOperand(MI->getOperand(6), MCOp); |
244 | 12 | TmpInst.addOperand(MCOp); |
245 | 12 | lowerOperand(MI->getOperand(7), MCOp); |
246 | 12 | TmpInst.addOperand(MCOp); |
247 | 12 | // Operand: s |
248 | 12 | lowerOperand(MI->getOperand(8), MCOp); |
249 | 12 | TmpInst.addOperand(MCOp); |
250 | 12 | EmitToStreamer(OutStreamer, TmpInst); |
251 | 12 | break; |
252 | 375k | } |
253 | 20 | case ARM::UMULLv5: { |
254 | 20 | MCInst TmpInst; |
255 | 20 | MCOperand MCOp; |
256 | 20 | TmpInst.setOpcode(ARM::UMULL); |
257 | 20 | // Operand: RdLo |
258 | 20 | lowerOperand(MI->getOperand(0), MCOp); |
259 | 20 | TmpInst.addOperand(MCOp); |
260 | 20 | // Operand: RdHi |
261 | 20 | lowerOperand(MI->getOperand(1), MCOp); |
262 | 20 | TmpInst.addOperand(MCOp); |
263 | 20 | // Operand: Rn |
264 | 20 | lowerOperand(MI->getOperand(2), MCOp); |
265 | 20 | TmpInst.addOperand(MCOp); |
266 | 20 | // Operand: Rm |
267 | 20 | lowerOperand(MI->getOperand(3), MCOp); |
268 | 20 | TmpInst.addOperand(MCOp); |
269 | 20 | // Operand: p |
270 | 20 | lowerOperand(MI->getOperand(4), MCOp); |
271 | 20 | TmpInst.addOperand(MCOp); |
272 | 20 | lowerOperand(MI->getOperand(5), MCOp); |
273 | 20 | TmpInst.addOperand(MCOp); |
274 | 20 | // Operand: s |
275 | 20 | lowerOperand(MI->getOperand(6), MCOp); |
276 | 20 | TmpInst.addOperand(MCOp); |
277 | 20 | EmitToStreamer(OutStreamer, TmpInst); |
278 | 20 | break; |
279 | 375k | } |
280 | 2 | case ARM::VMOVD0: { |
281 | 2 | MCInst TmpInst; |
282 | 2 | MCOperand MCOp; |
283 | 2 | TmpInst.setOpcode(ARM::VMOVv2i32); |
284 | 2 | // Operand: Vd |
285 | 2 | lowerOperand(MI->getOperand(0), MCOp); |
286 | 2 | TmpInst.addOperand(MCOp); |
287 | 2 | // Operand: SIMM |
288 | 2 | TmpInst.addOperand(MCOperand::createImm(0)); |
289 | 2 | // Operand: p |
290 | 2 | TmpInst.addOperand(MCOperand::createImm(14)); |
291 | 2 | TmpInst.addOperand(MCOperand::createReg(0)); |
292 | 2 | EmitToStreamer(OutStreamer, TmpInst); |
293 | 2 | break; |
294 | 375k | } |
295 | 2 | case ARM::VMOVQ0: { |
296 | 2 | MCInst TmpInst; |
297 | 2 | MCOperand MCOp; |
298 | 2 | TmpInst.setOpcode(ARM::VMOVv4i32); |
299 | 2 | // Operand: Vd |
300 | 2 | lowerOperand(MI->getOperand(0), MCOp); |
301 | 2 | TmpInst.addOperand(MCOp); |
302 | 2 | // Operand: SIMM |
303 | 2 | TmpInst.addOperand(MCOperand::createImm(0)); |
304 | 2 | // Operand: p |
305 | 2 | TmpInst.addOperand(MCOperand::createImm(14)); |
306 | 2 | TmpInst.addOperand(MCOperand::createReg(0)); |
307 | 2 | EmitToStreamer(OutStreamer, TmpInst); |
308 | 2 | break; |
309 | 375k | } |
310 | 204 | case ARM::t2LDMIA_RET: { |
311 | 204 | MCInst TmpInst; |
312 | 204 | MCOperand MCOp; |
313 | 204 | TmpInst.setOpcode(ARM::t2LDMIA_UPD); |
314 | 204 | // Operand: wb |
315 | 204 | lowerOperand(MI->getOperand(0), MCOp); |
316 | 204 | TmpInst.addOperand(MCOp); |
317 | 204 | // Operand: Rn |
318 | 204 | lowerOperand(MI->getOperand(1), MCOp); |
319 | 204 | TmpInst.addOperand(MCOp); |
320 | 204 | // Operand: p |
321 | 204 | lowerOperand(MI->getOperand(2), MCOp); |
322 | 204 | TmpInst.addOperand(MCOp); |
323 | 204 | lowerOperand(MI->getOperand(3), MCOp); |
324 | 204 | TmpInst.addOperand(MCOp); |
325 | 204 | // Operand: regs |
326 | 204 | lowerOperand(MI->getOperand(4), MCOp); |
327 | 204 | TmpInst.addOperand(MCOp); |
328 | 204 | // variable_ops |
329 | 1.52k | for (unsigned i = 5, e = MI->getNumOperands(); i != e1.52k ; ++i1.32k ) |
330 | 1.32k | if (1.32k lowerOperand(MI->getOperand(i), MCOp)1.32k ) |
331 | 1.06k | TmpInst.addOperand(MCOp); |
332 | 204 | EmitToStreamer(OutStreamer, TmpInst); |
333 | 204 | break; |
334 | 375k | } |
335 | 20 | case ARM::tBRIND: { |
336 | 20 | MCInst TmpInst; |
337 | 20 | MCOperand MCOp; |
338 | 20 | TmpInst.setOpcode(ARM::tMOVr); |
339 | 20 | // Operand: Rd |
340 | 20 | TmpInst.addOperand(MCOperand::createReg(ARM::PC)); |
341 | 20 | // Operand: Rm |
342 | 20 | lowerOperand(MI->getOperand(0), MCOp); |
343 | 20 | TmpInst.addOperand(MCOp); |
344 | 20 | // Operand: p |
345 | 20 | lowerOperand(MI->getOperand(1), MCOp); |
346 | 20 | TmpInst.addOperand(MCOp); |
347 | 20 | lowerOperand(MI->getOperand(2), MCOp); |
348 | 20 | TmpInst.addOperand(MCOp); |
349 | 20 | EmitToStreamer(OutStreamer, TmpInst); |
350 | 20 | break; |
351 | 375k | } |
352 | 5.80k | case ARM::tBX_RET: { |
353 | 5.80k | MCInst TmpInst; |
354 | 5.80k | MCOperand MCOp; |
355 | 5.80k | TmpInst.setOpcode(ARM::tBX); |
356 | 5.80k | // Operand: Rm |
357 | 5.80k | TmpInst.addOperand(MCOperand::createReg(ARM::LR)); |
358 | 5.80k | // Operand: p |
359 | 5.80k | lowerOperand(MI->getOperand(0), MCOp); |
360 | 5.80k | TmpInst.addOperand(MCOp); |
361 | 5.80k | lowerOperand(MI->getOperand(1), MCOp); |
362 | 5.80k | TmpInst.addOperand(MCOp); |
363 | 5.80k | EmitToStreamer(OutStreamer, TmpInst); |
364 | 5.80k | break; |
365 | 375k | } |
366 | 0 | case ARM::tBX_RET_vararg: { |
367 | 0 | MCInst TmpInst; |
368 | 0 | MCOperand MCOp; |
369 | 0 | TmpInst.setOpcode(ARM::tBX); |
370 | 0 | // Operand: Rm |
371 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
372 | 0 | TmpInst.addOperand(MCOp); |
373 | 0 | // Operand: p |
374 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
375 | 0 | TmpInst.addOperand(MCOp); |
376 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
377 | 0 | TmpInst.addOperand(MCOp); |
378 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
379 | 0 | break; |
380 | 375k | } |
381 | 0 | case ARM::tBfar: { |
382 | 0 | MCInst TmpInst; |
383 | 0 | MCOperand MCOp; |
384 | 0 | TmpInst.setOpcode(ARM::tBL); |
385 | 0 | // Operand: p |
386 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
387 | 0 | TmpInst.addOperand(MCOp); |
388 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
389 | 0 | TmpInst.addOperand(MCOp); |
390 | 0 | // Operand: func |
391 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
392 | 0 | TmpInst.addOperand(MCOp); |
393 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
394 | 0 | break; |
395 | 375k | } |
396 | 48 | case ARM::tLDMIA_UPD: { |
397 | 48 | MCInst TmpInst; |
398 | 48 | MCOperand MCOp; |
399 | 48 | TmpInst.setOpcode(ARM::tLDMIA); |
400 | 48 | // Operand: Rn |
401 | 48 | lowerOperand(MI->getOperand(1), MCOp); |
402 | 48 | TmpInst.addOperand(MCOp); |
403 | 48 | // Operand: p |
404 | 48 | lowerOperand(MI->getOperand(2), MCOp); |
405 | 48 | TmpInst.addOperand(MCOp); |
406 | 48 | lowerOperand(MI->getOperand(3), MCOp); |
407 | 48 | TmpInst.addOperand(MCOp); |
408 | 48 | // Operand: regs |
409 | 48 | lowerOperand(MI->getOperand(4), MCOp); |
410 | 48 | TmpInst.addOperand(MCOp); |
411 | 48 | // variable_ops |
412 | 140 | for (unsigned i = 5, e = MI->getNumOperands(); i != e140 ; ++i92 ) |
413 | 92 | if (92 lowerOperand(MI->getOperand(i), MCOp)92 ) |
414 | 92 | TmpInst.addOperand(MCOp); |
415 | 48 | EmitToStreamer(OutStreamer, TmpInst); |
416 | 48 | break; |
417 | 375k | } |
418 | 5.60k | case ARM::tPOP_RET: { |
419 | 5.60k | MCInst TmpInst; |
420 | 5.60k | MCOperand MCOp; |
421 | 5.60k | TmpInst.setOpcode(ARM::tPOP); |
422 | 5.60k | // Operand: p |
423 | 5.60k | lowerOperand(MI->getOperand(0), MCOp); |
424 | 5.60k | TmpInst.addOperand(MCOp); |
425 | 5.60k | lowerOperand(MI->getOperand(1), MCOp); |
426 | 5.60k | TmpInst.addOperand(MCOp); |
427 | 5.60k | // Operand: regs |
428 | 5.60k | lowerOperand(MI->getOperand(2), MCOp); |
429 | 5.60k | TmpInst.addOperand(MCOp); |
430 | 5.60k | // variable_ops |
431 | 27.8k | for (unsigned i = 3, e = MI->getNumOperands(); i != e27.8k ; ++i22.2k ) |
432 | 22.2k | if (22.2k lowerOperand(MI->getOperand(i), MCOp)22.2k ) |
433 | 15.5k | TmpInst.addOperand(MCOp); |
434 | 5.60k | EmitToStreamer(OutStreamer, TmpInst); |
435 | 5.60k | break; |
436 | 375k | } |
437 | 822 | case ARM::tTAILJMPd: { |
438 | 822 | MCInst TmpInst; |
439 | 822 | MCOperand MCOp; |
440 | 822 | TmpInst.setOpcode(ARM::t2B); |
441 | 822 | // Operand: target |
442 | 822 | lowerOperand(MI->getOperand(0), MCOp); |
443 | 822 | TmpInst.addOperand(MCOp); |
444 | 822 | // Operand: p |
445 | 822 | lowerOperand(MI->getOperand(1), MCOp); |
446 | 822 | TmpInst.addOperand(MCOp); |
447 | 822 | lowerOperand(MI->getOperand(2), MCOp); |
448 | 822 | TmpInst.addOperand(MCOp); |
449 | 822 | EmitToStreamer(OutStreamer, TmpInst); |
450 | 822 | break; |
451 | 375k | } |
452 | 244 | case ARM::tTAILJMPdND: { |
453 | 244 | MCInst TmpInst; |
454 | 244 | MCOperand MCOp; |
455 | 244 | TmpInst.setOpcode(ARM::tB); |
456 | 244 | // Operand: target |
457 | 244 | lowerOperand(MI->getOperand(0), MCOp); |
458 | 244 | TmpInst.addOperand(MCOp); |
459 | 244 | // Operand: p |
460 | 244 | lowerOperand(MI->getOperand(1), MCOp); |
461 | 244 | TmpInst.addOperand(MCOp); |
462 | 244 | lowerOperand(MI->getOperand(2), MCOp); |
463 | 244 | TmpInst.addOperand(MCOp); |
464 | 244 | EmitToStreamer(OutStreamer, TmpInst); |
465 | 244 | break; |
466 | 375k | } |
467 | 64 | case ARM::tTAILJMPr: { |
468 | 64 | MCInst TmpInst; |
469 | 64 | MCOperand MCOp; |
470 | 64 | TmpInst.setOpcode(ARM::tBX); |
471 | 64 | // Operand: Rm |
472 | 64 | lowerOperand(MI->getOperand(0), MCOp); |
473 | 64 | TmpInst.addOperand(MCOp); |
474 | 64 | // Operand: p |
475 | 64 | TmpInst.addOperand(MCOperand::createImm(14)); |
476 | 64 | TmpInst.addOperand(MCOperand::createReg(0)); |
477 | 64 | EmitToStreamer(OutStreamer, TmpInst); |
478 | 64 | break; |
479 | 375k | } |
480 | 375k | } |
481 | 14.7k | return true; |
482 | 375k | } |
483 | | |