Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/clang-build/lib/Target/ARM/ARMGenRegisterInfo.inc
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass ARMMCRegisterClasses[];
17
18
namespace ARM {
19
enum {
20
  NoRegister,
21
  APSR = 1,
22
  APSR_NZCV = 2,
23
  CPSR = 3,
24
  FPEXC = 4,
25
  FPINST = 5,
26
  FPSCR = 6,
27
  FPSCR_NZCV = 7,
28
  FPSID = 8,
29
  ITSTATE = 9,
30
  LR = 10,
31
  PC = 11,
32
  SP = 12,
33
  SPSR = 13,
34
  D0 = 14,
35
  D1 = 15,
36
  D2 = 16,
37
  D3 = 17,
38
  D4 = 18,
39
  D5 = 19,
40
  D6 = 20,
41
  D7 = 21,
42
  D8 = 22,
43
  D9 = 23,
44
  D10 = 24,
45
  D11 = 25,
46
  D12 = 26,
47
  D13 = 27,
48
  D14 = 28,
49
  D15 = 29,
50
  D16 = 30,
51
  D17 = 31,
52
  D18 = 32,
53
  D19 = 33,
54
  D20 = 34,
55
  D21 = 35,
56
  D22 = 36,
57
  D23 = 37,
58
  D24 = 38,
59
  D25 = 39,
60
  D26 = 40,
61
  D27 = 41,
62
  D28 = 42,
63
  D29 = 43,
64
  D30 = 44,
65
  D31 = 45,
66
  FPINST2 = 46,
67
  MVFR0 = 47,
68
  MVFR1 = 48,
69
  MVFR2 = 49,
70
  Q0 = 50,
71
  Q1 = 51,
72
  Q2 = 52,
73
  Q3 = 53,
74
  Q4 = 54,
75
  Q5 = 55,
76
  Q6 = 56,
77
  Q7 = 57,
78
  Q8 = 58,
79
  Q9 = 59,
80
  Q10 = 60,
81
  Q11 = 61,
82
  Q12 = 62,
83
  Q13 = 63,
84
  Q14 = 64,
85
  Q15 = 65,
86
  R0 = 66,
87
  R1 = 67,
88
  R2 = 68,
89
  R3 = 69,
90
  R4 = 70,
91
  R5 = 71,
92
  R6 = 72,
93
  R7 = 73,
94
  R8 = 74,
95
  R9 = 75,
96
  R10 = 76,
97
  R11 = 77,
98
  R12 = 78,
99
  S0 = 79,
100
  S1 = 80,
101
  S2 = 81,
102
  S3 = 82,
103
  S4 = 83,
104
  S5 = 84,
105
  S6 = 85,
106
  S7 = 86,
107
  S8 = 87,
108
  S9 = 88,
109
  S10 = 89,
110
  S11 = 90,
111
  S12 = 91,
112
  S13 = 92,
113
  S14 = 93,
114
  S15 = 94,
115
  S16 = 95,
116
  S17 = 96,
117
  S18 = 97,
118
  S19 = 98,
119
  S20 = 99,
120
  S21 = 100,
121
  S22 = 101,
122
  S23 = 102,
123
  S24 = 103,
124
  S25 = 104,
125
  S26 = 105,
126
  S27 = 106,
127
  S28 = 107,
128
  S29 = 108,
129
  S30 = 109,
130
  S31 = 110,
131
  D0_D2 = 111,
132
  D1_D3 = 112,
133
  D2_D4 = 113,
134
  D3_D5 = 114,
135
  D4_D6 = 115,
136
  D5_D7 = 116,
137
  D6_D8 = 117,
138
  D7_D9 = 118,
139
  D8_D10 = 119,
140
  D9_D11 = 120,
141
  D10_D12 = 121,
142
  D11_D13 = 122,
143
  D12_D14 = 123,
144
  D13_D15 = 124,
145
  D14_D16 = 125,
146
  D15_D17 = 126,
147
  D16_D18 = 127,
148
  D17_D19 = 128,
149
  D18_D20 = 129,
150
  D19_D21 = 130,
151
  D20_D22 = 131,
152
  D21_D23 = 132,
153
  D22_D24 = 133,
154
  D23_D25 = 134,
155
  D24_D26 = 135,
156
  D25_D27 = 136,
157
  D26_D28 = 137,
158
  D27_D29 = 138,
159
  D28_D30 = 139,
160
  D29_D31 = 140,
161
  Q0_Q1 = 141,
162
  Q1_Q2 = 142,
163
  Q2_Q3 = 143,
164
  Q3_Q4 = 144,
165
  Q4_Q5 = 145,
166
  Q5_Q6 = 146,
167
  Q6_Q7 = 147,
168
  Q7_Q8 = 148,
169
  Q8_Q9 = 149,
170
  Q9_Q10 = 150,
171
  Q10_Q11 = 151,
172
  Q11_Q12 = 152,
173
  Q12_Q13 = 153,
174
  Q13_Q14 = 154,
175
  Q14_Q15 = 155,
176
  Q0_Q1_Q2_Q3 = 156,
177
  Q1_Q2_Q3_Q4 = 157,
178
  Q2_Q3_Q4_Q5 = 158,
179
  Q3_Q4_Q5_Q6 = 159,
180
  Q4_Q5_Q6_Q7 = 160,
181
  Q5_Q6_Q7_Q8 = 161,
182
  Q6_Q7_Q8_Q9 = 162,
183
  Q7_Q8_Q9_Q10 = 163,
184
  Q8_Q9_Q10_Q11 = 164,
185
  Q9_Q10_Q11_Q12 = 165,
186
  Q10_Q11_Q12_Q13 = 166,
187
  Q11_Q12_Q13_Q14 = 167,
188
  Q12_Q13_Q14_Q15 = 168,
189
  R12_SP = 169,
190
  R0_R1 = 170,
191
  R2_R3 = 171,
192
  R4_R5 = 172,
193
  R6_R7 = 173,
194
  R8_R9 = 174,
195
  R10_R11 = 175,
196
  D0_D1_D2 = 176,
197
  D1_D2_D3 = 177,
198
  D2_D3_D4 = 178,
199
  D3_D4_D5 = 179,
200
  D4_D5_D6 = 180,
201
  D5_D6_D7 = 181,
202
  D6_D7_D8 = 182,
203
  D7_D8_D9 = 183,
204
  D8_D9_D10 = 184,
205
  D9_D10_D11 = 185,
206
  D10_D11_D12 = 186,
207
  D11_D12_D13 = 187,
208
  D12_D13_D14 = 188,
209
  D13_D14_D15 = 189,
210
  D14_D15_D16 = 190,
211
  D15_D16_D17 = 191,
212
  D16_D17_D18 = 192,
213
  D17_D18_D19 = 193,
214
  D18_D19_D20 = 194,
215
  D19_D20_D21 = 195,
216
  D20_D21_D22 = 196,
217
  D21_D22_D23 = 197,
218
  D22_D23_D24 = 198,
219
  D23_D24_D25 = 199,
220
  D24_D25_D26 = 200,
221
  D25_D26_D27 = 201,
222
  D26_D27_D28 = 202,
223
  D27_D28_D29 = 203,
224
  D28_D29_D30 = 204,
225
  D29_D30_D31 = 205,
226
  D0_D2_D4 = 206,
227
  D1_D3_D5 = 207,
228
  D2_D4_D6 = 208,
229
  D3_D5_D7 = 209,
230
  D4_D6_D8 = 210,
231
  D5_D7_D9 = 211,
232
  D6_D8_D10 = 212,
233
  D7_D9_D11 = 213,
234
  D8_D10_D12 = 214,
235
  D9_D11_D13 = 215,
236
  D10_D12_D14 = 216,
237
  D11_D13_D15 = 217,
238
  D12_D14_D16 = 218,
239
  D13_D15_D17 = 219,
240
  D14_D16_D18 = 220,
241
  D15_D17_D19 = 221,
242
  D16_D18_D20 = 222,
243
  D17_D19_D21 = 223,
244
  D18_D20_D22 = 224,
245
  D19_D21_D23 = 225,
246
  D20_D22_D24 = 226,
247
  D21_D23_D25 = 227,
248
  D22_D24_D26 = 228,
249
  D23_D25_D27 = 229,
250
  D24_D26_D28 = 230,
251
  D25_D27_D29 = 231,
252
  D26_D28_D30 = 232,
253
  D27_D29_D31 = 233,
254
  D0_D2_D4_D6 = 234,
255
  D1_D3_D5_D7 = 235,
256
  D2_D4_D6_D8 = 236,
257
  D3_D5_D7_D9 = 237,
258
  D4_D6_D8_D10 = 238,
259
  D5_D7_D9_D11 = 239,
260
  D6_D8_D10_D12 = 240,
261
  D7_D9_D11_D13 = 241,
262
  D8_D10_D12_D14 = 242,
263
  D9_D11_D13_D15 = 243,
264
  D10_D12_D14_D16 = 244,
265
  D11_D13_D15_D17 = 245,
266
  D12_D14_D16_D18 = 246,
267
  D13_D15_D17_D19 = 247,
268
  D14_D16_D18_D20 = 248,
269
  D15_D17_D19_D21 = 249,
270
  D16_D18_D20_D22 = 250,
271
  D17_D19_D21_D23 = 251,
272
  D18_D20_D22_D24 = 252,
273
  D19_D21_D23_D25 = 253,
274
  D20_D22_D24_D26 = 254,
275
  D21_D23_D25_D27 = 255,
276
  D22_D24_D26_D28 = 256,
277
  D23_D25_D27_D29 = 257,
278
  D24_D26_D28_D30 = 258,
279
  D25_D27_D29_D31 = 259,
280
  D1_D2 = 260,
281
  D3_D4 = 261,
282
  D5_D6 = 262,
283
  D7_D8 = 263,
284
  D9_D10 = 264,
285
  D11_D12 = 265,
286
  D13_D14 = 266,
287
  D15_D16 = 267,
288
  D17_D18 = 268,
289
  D19_D20 = 269,
290
  D21_D22 = 270,
291
  D23_D24 = 271,
292
  D25_D26 = 272,
293
  D27_D28 = 273,
294
  D29_D30 = 274,
295
  D1_D2_D3_D4 = 275,
296
  D3_D4_D5_D6 = 276,
297
  D5_D6_D7_D8 = 277,
298
  D7_D8_D9_D10 = 278,
299
  D9_D10_D11_D12 = 279,
300
  D11_D12_D13_D14 = 280,
301
  D13_D14_D15_D16 = 281,
302
  D15_D16_D17_D18 = 282,
303
  D17_D18_D19_D20 = 283,
304
  D19_D20_D21_D22 = 284,
305
  D21_D22_D23_D24 = 285,
306
  D23_D24_D25_D26 = 286,
307
  D25_D26_D27_D28 = 287,
308
  D27_D28_D29_D30 = 288,
309
  NUM_TARGET_REGS   // 289
310
};
311
} // end namespace ARM
312
313
// Register classes
314
315
namespace ARM {
316
enum {
317
  SPRRegClassID = 0,
318
  GPRRegClassID = 1,
319
  GPRwithAPSRRegClassID = 2,
320
  SPR_8RegClassID = 3,
321
  GPRnopcRegClassID = 4,
322
  rGPRRegClassID = 5,
323
  tGPRwithpcRegClassID = 6,
324
  hGPRRegClassID = 7,
325
  tGPRRegClassID = 8,
326
  GPRnopc_and_hGPRRegClassID = 9,
327
  hGPR_and_rGPRRegClassID = 10,
328
  tcGPRRegClassID = 11,
329
  tGPR_and_tcGPRRegClassID = 12,
330
  CCRRegClassID = 13,
331
  GPRspRegClassID = 14,
332
  hGPR_and_tGPRwithpcRegClassID = 15,
333
  hGPR_and_tcGPRRegClassID = 16,
334
  DPRRegClassID = 17,
335
  DPR_VFP2RegClassID = 18,
336
  DPR_8RegClassID = 19,
337
  GPRPairRegClassID = 20,
338
  GPRPair_with_gsub_1_in_rGPRRegClassID = 21,
339
  GPRPair_with_gsub_0_in_tGPRRegClassID = 22,
340
  GPRPair_with_gsub_0_in_hGPRRegClassID = 23,
341
  GPRPair_with_gsub_0_in_tcGPRRegClassID = 24,
342
  GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 25,
343
  GPRPair_with_gsub_1_in_tcGPRRegClassID = 26,
344
  GPRPair_with_gsub_1_in_GPRspRegClassID = 27,
345
  DPairSpcRegClassID = 28,
346
  DPairSpc_with_ssub_0RegClassID = 29,
347
  DPairSpc_with_ssub_4RegClassID = 30,
348
  DPairSpc_with_dsub_0_in_DPR_8RegClassID = 31,
349
  DPairSpc_with_dsub_2_in_DPR_8RegClassID = 32,
350
  DPairRegClassID = 33,
351
  DPair_with_ssub_0RegClassID = 34,
352
  QPRRegClassID = 35,
353
  DPair_with_ssub_2RegClassID = 36,
354
  DPair_with_dsub_0_in_DPR_8RegClassID = 37,
355
  QPR_VFP2RegClassID = 38,
356
  DPair_with_dsub_1_in_DPR_8RegClassID = 39,
357
  QPR_8RegClassID = 40,
358
  DTripleRegClassID = 41,
359
  DTripleSpcRegClassID = 42,
360
  DTripleSpc_with_ssub_0RegClassID = 43,
361
  DTriple_with_ssub_0RegClassID = 44,
362
  DTriple_with_qsub_0_in_QPRRegClassID = 45,
363
  DTriple_with_ssub_2RegClassID = 46,
364
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 47,
365
  DTripleSpc_with_ssub_4RegClassID = 48,
366
  DTriple_with_ssub_4RegClassID = 49,
367
  DTripleSpc_with_ssub_8RegClassID = 50,
368
  DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 51,
369
  DTriple_with_dsub_0_in_DPR_8RegClassID = 52,
370
  DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 53,
371
  DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 54,
372
  DTriple_with_dsub_1_in_DPR_8RegClassID = 55,
373
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 56,
374
  DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID = 57,
375
  DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 58,
376
  DTriple_with_dsub_2_in_DPR_8RegClassID = 59,
377
  DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 60,
378
  DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 61,
379
  DTriple_with_qsub_0_in_QPR_8RegClassID = 62,
380
  DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 63,
381
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 64,
382
  DQuadSpcRegClassID = 65,
383
  DQuadSpc_with_ssub_0RegClassID = 66,
384
  DQuadSpc_with_ssub_4RegClassID = 67,
385
  DQuadSpc_with_ssub_8RegClassID = 68,
386
  DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 69,
387
  DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 70,
388
  DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 71,
389
  DQuadRegClassID = 72,
390
  DQuad_with_ssub_0RegClassID = 73,
391
  DQuad_with_ssub_2RegClassID = 74,
392
  QQPRRegClassID = 75,
393
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 76,
394
  DQuad_with_ssub_4RegClassID = 77,
395
  DQuad_with_ssub_6RegClassID = 78,
396
  DQuad_with_dsub_0_in_DPR_8RegClassID = 79,
397
  DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 80,
398
  DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 81,
399
  DQuad_with_dsub_1_in_DPR_8RegClassID = 82,
400
  DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 83,
401
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 84,
402
  DQuad_with_dsub_2_in_DPR_8RegClassID = 85,
403
  DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 86,
404
  DQuad_with_dsub_3_in_DPR_8RegClassID = 87,
405
  DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 88,
406
  DQuad_with_qsub_0_in_QPR_8RegClassID = 89,
407
  DQuad_with_qsub_1_in_QPR_8RegClassID = 90,
408
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 91,
409
  DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 92,
410
  QQQQPRRegClassID = 93,
411
  QQQQPR_with_ssub_0RegClassID = 94,
412
  QQQQPR_with_ssub_4RegClassID = 95,
413
  QQQQPR_with_ssub_8RegClassID = 96,
414
  QQQQPR_with_ssub_12RegClassID = 97,
415
  QQQQPR_with_dsub_0_in_DPR_8RegClassID = 98,
416
  QQQQPR_with_dsub_2_in_DPR_8RegClassID = 99,
417
  QQQQPR_with_dsub_4_in_DPR_8RegClassID = 100,
418
  QQQQPR_with_dsub_6_in_DPR_8RegClassID = 101,
419
420
  };
421
} // end namespace ARM
422
423
424
// Subregister indices
425
426
namespace ARM {
427
enum {
428
  NoSubRegister,
429
  dsub_0, // 1
430
  dsub_1, // 2
431
  dsub_2, // 3
432
  dsub_3, // 4
433
  dsub_4, // 5
434
  dsub_5, // 6
435
  dsub_6, // 7
436
  dsub_7, // 8
437
  gsub_0, // 9
438
  gsub_1, // 10
439
  qqsub_0,  // 11
440
  qqsub_1,  // 12
441
  qsub_0, // 13
442
  qsub_1, // 14
443
  qsub_2, // 15
444
  qsub_3, // 16
445
  ssub_0, // 17
446
  ssub_1, // 18
447
  ssub_2, // 19
448
  ssub_3, // 20
449
  ssub_4, // 21
450
  ssub_5, // 22
451
  ssub_6, // 23
452
  ssub_7, // 24
453
  ssub_8, // 25
454
  ssub_9, // 26
455
  ssub_10,  // 27
456
  ssub_11,  // 28
457
  ssub_12,  // 29
458
  ssub_13,  // 30
459
  dsub_7_then_ssub_0, // 31
460
  dsub_7_then_ssub_1, // 32
461
  ssub_0_ssub_1_ssub_4_ssub_5,  // 33
462
  ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5,  // 34
463
  ssub_2_ssub_3_ssub_6_ssub_7,  // 35
464
  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7,  // 36
465
  ssub_2_ssub_3_ssub_4_ssub_5,  // 37
466
  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9,  // 38
467
  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,  // 39
468
  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40
469
  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7,  // 41
470
  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,  // 42
471
  ssub_4_ssub_5_ssub_8_ssub_9,  // 43
472
  ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,  // 44
473
  ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,  // 45
474
  ssub_6_ssub_7_dsub_5, // 46
475
  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47
476
  ssub_6_ssub_7_dsub_5_dsub_7,  // 48
477
  ssub_6_ssub_7_ssub_8_ssub_9,  // 49
478
  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50
479
  ssub_8_ssub_9_ssub_12_ssub_13,  // 51
480
  ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52
481
  dsub_5_dsub_7,  // 53
482
  dsub_5_ssub_12_ssub_13_dsub_7,  // 54
483
  dsub_5_ssub_12_ssub_13, // 55
484
  ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56
485
  NUM_TARGET_SUBREGS
486
};
487
} // end namespace ARM
488
489
} // end namespace llvm
490
491
#endif // GET_REGINFO_ENUM
492
493
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
494
|*                                                                            *|
495
|* MC Register Information                                                    *|
496
|*                                                                            *|
497
|* Automatically generated file, do not edit!                                 *|
498
|*                                                                            *|
499
\*===----------------------------------------------------------------------===*/
500
501
502
#ifdef GET_REGINFO_MC_DESC
503
#undef GET_REGINFO_MC_DESC
504
505
namespace llvm {
506
507
extern const MCPhysReg ARMRegDiffLists[] = {
508
  /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
509
  /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
510
  /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
511
  /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
512
  /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0,
513
  /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0,
514
  /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0,
515
  /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0,
516
  /* 91 */ 40, 1, 1, 1, 1, 1, 0,
517
  /* 98 */ 65196, 1, 1, 1, 1, 1, 0,
518
  /* 105 */ 40, 1, 1, 1, 1, 0,
519
  /* 111 */ 42, 1, 1, 1, 1, 0,
520
  /* 117 */ 42, 1, 1, 1, 0,
521
  /* 122 */ 64510, 1, 1, 1, 0,
522
  /* 127 */ 65015, 1, 1, 1, 0,
523
  /* 132 */ 65282, 1, 1, 1, 0,
524
  /* 137 */ 65348, 1, 1, 1, 0,
525
  /* 142 */ 13, 1, 1, 0,
526
  /* 146 */ 42, 1, 1, 0,
527
  /* 150 */ 65388, 1, 1, 0,
528
  /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0,
529
  /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0,
530
  /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0,
531
  /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0,
532
  /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0,
533
  /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0,
534
  /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0,
535
  /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0,
536
  /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0,
537
  /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0,
538
  /* 254 */ 65489, 133, 65416, 1, 1, 0,
539
  /* 260 */ 65490, 133, 65416, 1, 1, 0,
540
  /* 266 */ 65491, 133, 65416, 1, 1, 0,
541
  /* 272 */ 65492, 133, 65416, 1, 1, 0,
542
  /* 278 */ 65493, 133, 65416, 1, 1, 0,
543
  /* 284 */ 65494, 133, 65416, 1, 1, 0,
544
  /* 290 */ 65495, 133, 65416, 1, 1, 0,
545
  /* 296 */ 65496, 133, 65416, 1, 1, 0,
546
  /* 302 */ 65497, 133, 65416, 1, 1, 0,
547
  /* 308 */ 65498, 133, 65416, 1, 1, 0,
548
  /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0,
549
  /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0,
550
  /* 332 */ 65136, 1, 3, 1, 3, 1, 0,
551
  /* 339 */ 65326, 1, 3, 1, 0,
552
  /* 344 */ 13, 1, 0,
553
  /* 347 */ 14, 1, 0,
554
  /* 350 */ 65, 1, 0,
555
  /* 353 */ 65500, 65, 1, 65471, 66, 1, 0,
556
  /* 360 */ 65291, 66, 1, 65470, 67, 1, 0,
557
  /* 367 */ 65439, 65, 1, 65472, 67, 1, 0,
558
  /* 374 */ 65501, 67, 1, 65469, 68, 1, 0,
559
  /* 381 */ 65439, 66, 1, 65471, 68, 1, 0,
560
  /* 388 */ 65292, 68, 1, 65468, 69, 1, 0,
561
  /* 395 */ 65439, 67, 1, 65470, 69, 1, 0,
562
  /* 402 */ 65502, 69, 1, 65467, 70, 1, 0,
563
  /* 409 */ 65439, 68, 1, 65469, 70, 1, 0,
564
  /* 416 */ 65293, 70, 1, 65466, 71, 1, 0,
565
  /* 423 */ 65439, 69, 1, 65468, 71, 1, 0,
566
  /* 430 */ 65503, 71, 1, 65465, 72, 1, 0,
567
  /* 437 */ 65439, 70, 1, 65467, 72, 1, 0,
568
  /* 444 */ 65294, 72, 1, 65464, 73, 1, 0,
569
  /* 451 */ 65439, 71, 1, 65466, 73, 1, 0,
570
  /* 458 */ 65504, 73, 1, 65463, 74, 1, 0,
571
  /* 465 */ 65439, 72, 1, 65465, 74, 1, 0,
572
  /* 472 */ 65295, 74, 1, 65462, 75, 1, 0,
573
  /* 479 */ 65439, 73, 1, 65464, 75, 1, 0,
574
  /* 486 */ 65505, 75, 1, 65461, 76, 1, 0,
575
  /* 493 */ 65439, 74, 1, 65463, 76, 1, 0,
576
  /* 500 */ 65296, 76, 1, 65460, 77, 1, 0,
577
  /* 507 */ 65439, 75, 1, 65462, 77, 1, 0,
578
  /* 514 */ 65506, 77, 1, 65459, 78, 1, 0,
579
  /* 521 */ 65439, 76, 1, 65461, 78, 1, 0,
580
  /* 528 */ 65297, 78, 1, 65458, 79, 1, 0,
581
  /* 535 */ 65439, 77, 1, 65460, 79, 1, 0,
582
  /* 542 */ 65507, 79, 1, 65457, 80, 1, 0,
583
  /* 549 */ 65439, 78, 1, 65459, 80, 1, 0,
584
  /* 556 */ 65045, 1, 0,
585
  /* 559 */ 65260, 1, 0,
586
  /* 562 */ 65299, 1, 0,
587
  /* 565 */ 65300, 1, 0,
588
  /* 568 */ 65301, 1, 0,
589
  /* 571 */ 65302, 1, 0,
590
  /* 574 */ 65303, 1, 0,
591
  /* 577 */ 65304, 1, 0,
592
  /* 580 */ 65305, 1, 0,
593
  /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0,
594
  /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0,
595
  /* 600 */ 65488, 13, 121, 65416, 1, 0,
596
  /* 606 */ 65489, 13, 121, 65416, 1, 0,
597
  /* 612 */ 65490, 13, 121, 65416, 1, 0,
598
  /* 618 */ 65491, 13, 121, 65416, 1, 0,
599
  /* 624 */ 65492, 13, 121, 65416, 1, 0,
600
  /* 630 */ 65493, 13, 121, 65416, 1, 0,
601
  /* 636 */ 65494, 13, 121, 65416, 1, 0,
602
  /* 642 */ 65495, 13, 121, 65416, 1, 0,
603
  /* 648 */ 65496, 13, 121, 65416, 1, 0,
604
  /* 654 */ 65497, 13, 121, 65416, 1, 0,
605
  /* 660 */ 65498, 13, 121, 65416, 1, 0,
606
  /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0,
607
  /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0,
608
  /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0,
609
  /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0,
610
  /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0,
611
  /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0,
612
  /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0,
613
  /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0,
614
  /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0,
615
  /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0,
616
  /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0,
617
  /* 765 */ 65488, 133, 65416, 1, 0,
618
  /* 770 */ 65499, 134, 65416, 1, 0,
619
  /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0,
620
  /* 783 */ 65432, 1, 0,
621
  /* 786 */ 65433, 1, 0,
622
  /* 789 */ 65434, 1, 0,
623
  /* 792 */ 65435, 1, 0,
624
  /* 795 */ 65436, 1, 0,
625
  /* 798 */ 65437, 1, 0,
626
  /* 801 */ 65464, 1, 0,
627
  /* 804 */ 65508, 1, 0,
628
  /* 807 */ 65509, 1, 0,
629
  /* 810 */ 65510, 1, 0,
630
  /* 813 */ 65511, 1, 0,
631
  /* 816 */ 65512, 1, 0,
632
  /* 819 */ 65513, 1, 0,
633
  /* 822 */ 65514, 1, 0,
634
  /* 825 */ 65515, 1, 0,
635
  /* 828 */ 65520, 1, 0,
636
  /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0,
637
  /* 839 */ 65136, 1, 3, 1, 2, 0,
638
  /* 845 */ 65326, 1, 2, 0,
639
  /* 849 */ 65080, 1, 3, 1, 2, 2, 0,
640
  /* 856 */ 65136, 1, 2, 2, 0,
641
  /* 861 */ 65080, 1, 2, 2, 2, 0,
642
  /* 867 */ 65330, 2, 2, 2, 0,
643
  /* 872 */ 65080, 1, 3, 2, 2, 0,
644
  /* 878 */ 65358, 2, 2, 0,
645
  /* 882 */ 65080, 1, 3, 1, 3, 2, 0,
646
  /* 889 */ 65136, 1, 3, 2, 0,
647
  /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0,
648
  /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0,
649
  /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0,
650
  /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0,
651
  /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0,
652
  /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0,
653
  /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0,
654
  /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0,
655
  /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0,
656
  /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0,
657
  /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0,
658
  /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0,
659
  /* 1038 */ 65344, 2, 2, 93, 2, 0,
660
  /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0,
661
  /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0,
662
  /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0,
663
  /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0,
664
  /* 1080 */ 65439, 2, 0,
665
  /* 1083 */ 65453, 2, 0,
666
  /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0,
667
  /* 1094 */ 65136, 1, 3, 1, 3, 0,
668
  /* 1100 */ 65326, 1, 3, 0,
669
  /* 1104 */ 5, 0,
670
  /* 1106 */ 140, 65486, 13, 0,
671
  /* 1110 */ 14, 0,
672
  /* 1112 */ 126, 65501, 15, 0,
673
  /* 1116 */ 10, 66, 0,
674
  /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0,
675
  /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0,
676
  /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0,
677
  /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0,
678
  /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0,
679
  /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0,
680
  /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0,
681
  /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0,
682
  /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0,
683
  /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0,
684
  /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0,
685
  /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0,
686
  /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0,
687
  /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0,
688
  /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0,
689
  /* 1359 */ 91, 0,
690
  /* 1361 */ 98, 0,
691
  /* 1363 */ 99, 0,
692
  /* 1365 */ 100, 0,
693
  /* 1367 */ 101, 0,
694
  /* 1369 */ 102, 0,
695
  /* 1371 */ 103, 0,
696
  /* 1373 */ 104, 0,
697
  /* 1375 */ 65374, 1, 1, 20, 75, 135, 0,
698
  /* 1382 */ 65374, 1, 1, 21, 74, 136, 0,
699
  /* 1389 */ 65374, 1, 1, 22, 73, 137, 0,
700
  /* 1396 */ 65374, 1, 1, 23, 72, 138, 0,
701
  /* 1403 */ 65374, 1, 1, 24, 71, 139, 0,
702
  /* 1410 */ 65374, 1, 1, 25, 70, 140, 0,
703
  /* 1417 */ 65374, 1, 1, 26, 69, 141, 0,
704
  /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0,
705
  /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0,
706
  /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0,
707
  /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0,
708
  /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0,
709
  /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0,
710
  /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0,
711
  /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0,
712
  /* 1526 */ 157, 0,
713
  /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0,
714
  /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0,
715
  /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0,
716
  /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0,
717
  /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0,
718
  /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0,
719
  /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0,
720
  /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0,
721
  /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0,
722
  /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0,
723
  /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0,
724
  /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0,
725
  /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0,
726
  /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0,
727
  /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0,
728
  /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0,
729
  /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0,
730
  /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0,
731
  /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0,
732
  /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0,
733
  /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0,
734
  /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0,
735
  /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0,
736
  /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0,
737
  /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0,
738
  /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0,
739
  /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0,
740
  /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0,
741
  /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0,
742
  /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0,
743
  /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0,
744
  /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0,
745
  /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0,
746
  /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0,
747
  /* 2455 */ 65487, 13, 121, 65416, 0,
748
  /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0,
749
  /* 2468 */ 65466, 1, 65486, 133, 65416, 0,
750
  /* 2474 */ 65487, 133, 65416, 0,
751
  /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
752
  /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
753
  /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0,
754
  /* 2509 */ 65452, 1, 65500, 134, 65417, 0,
755
  /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0,
756
  /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0,
757
  /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0,
758
  /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0,
759
  /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0,
760
  /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0,
761
  /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0,
762
  /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0,
763
  /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0,
764
  /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0,
765
  /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0,
766
  /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0,
767
  /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0,
768
  /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0,
769
  /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0,
770
  /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0,
771
  /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0,
772
  /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0,
773
  /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0,
774
  /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0,
775
  /* 2832 */ 26, 65446, 92, 65445, 0,
776
  /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0,
777
  /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0,
778
  /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0,
779
  /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0,
780
  /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
781
  /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
782
  /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0,
783
  /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0,
784
  /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
785
  /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
786
  /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0,
787
  /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0,
788
  /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
789
  /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
790
  /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0,
791
  /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0,
792
  /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
793
  /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
794
  /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
795
  /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
796
  /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0,
797
  /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
798
  /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
799
  /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
800
  /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
801
  /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0,
802
  /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
803
  /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
804
  /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
805
  /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
806
  /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
807
  /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0,
808
  /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
809
  /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
810
  /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
811
  /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
812
  /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
813
  /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0,
814
  /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
815
  /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
816
  /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
817
  /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
818
  /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
819
  /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0,
820
  /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
821
  /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
822
  /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
823
  /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
824
  /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
825
  /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0,
826
  /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
827
  /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
828
  /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
829
  /* 3839 */ 65298, 80, 1, 65456, 0,
830
  /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
831
  /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
832
  /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0,
833
  /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
834
  /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
835
  /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0,
836
  /* 3948 */ 65439, 80, 1, 65457, 0,
837
  /* 3953 */ 28, 65457, 0,
838
  /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
839
  /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
840
  /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
841
  /* 4002 */ 26, 65458, 80, 65457, 0,
842
  /* 4007 */ 65439, 79, 1, 65458, 0,
843
  /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0,
844
  /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0,
845
  /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0,
846
  /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0,
847
  /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0,
848
  /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0,
849
  /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0,
850
  /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0,
851
  /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0,
852
  /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0,
853
  /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0,
854
  /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0,
855
  /* 4114 */ 65445, 65470, 0,
856
  /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0,
857
  /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0,
858
  /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0,
859
  /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0,
860
  /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0,
861
  /* 4182 */ 65534, 0,
862
  /* 4184 */ 65535, 0,
863
};
864
865
extern const LaneBitmask ARMLaneMaskLists[] = {
866
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
867
  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
868
  /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask::getAll(),
869
  /* 8 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
870
  /* 11 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
871
  /* 16 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask::getAll(),
872
  /* 20 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask::getAll(),
873
  /* 23 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
874
  /* 28 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
875
  /* 35 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
876
  /* 39 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
877
  /* 42 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
878
  /* 48 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
879
  /* 53 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
880
  /* 57 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask::getAll(),
881
  /* 66 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000300), LaneBitmask::getAll(),
882
  /* 74 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
883
  /* 81 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
884
  /* 87 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
885
  /* 92 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask::getAll(),
886
  /* 99 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
887
  /* 105 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
888
  /* 110 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
889
  /* 114 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask::getAll(),
890
  /* 123 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
891
  /* 131 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
892
  /* 138 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
893
  /* 144 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
894
  /* 149 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask(0x00010000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
895
  /* 166 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
896
  /* 181 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
897
  /* 194 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
898
  /* 205 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
899
};
900
901
extern const uint16_t ARMSubRegIdxLists[] = {
902
  /* 0 */ 1, 2, 0,
903
  /* 3 */ 1, 17, 18, 2, 0,
904
  /* 8 */ 1, 3, 0,
905
  /* 11 */ 1, 17, 18, 3, 0,
906
  /* 16 */ 9, 10, 0,
907
  /* 19 */ 17, 18, 0,
908
  /* 22 */ 1, 17, 18, 2, 19, 20, 0,
909
  /* 29 */ 1, 17, 18, 3, 21, 22, 0,
910
  /* 36 */ 1, 2, 3, 13, 33, 37, 0,
911
  /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0,
912
  /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0,
913
  /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0,
914
  /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0,
915
  /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0,
916
  /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
917
  /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
918
  /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0,
919
  /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0,
920
  /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0,
921
  /* 188 */ 1, 3, 5, 33, 43, 0,
922
  /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0,
923
  /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0,
924
  /* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0,
925
  /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0,
926
  /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0,
927
  /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0,
928
  /* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0,
929
  /* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0,
930
  /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
931
  /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
932
  /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
933
  /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
934
  /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
935
};
936
937
extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[] = {
938
  { 65535, 65535 },
939
  { 0, 64 },  // dsub_0
940
  { 64, 64 }, // dsub_1
941
  { 128, 64 },  // dsub_2
942
  { 192, 64 },  // dsub_3
943
  { 256, 64 },  // dsub_4
944
  { 320, 64 },  // dsub_5
945
  { 384, 64 },  // dsub_6
946
  { 448, 64 },  // dsub_7
947
  { 0, 32 },  // gsub_0
948
  { 32, 32 }, // gsub_1
949
  { 0, 256 }, // qqsub_0
950
  { 256, 256 }, // qqsub_1
951
  { 0, 128 }, // qsub_0
952
  { 128, 128 }, // qsub_1
953
  { 256, 128 }, // qsub_2
954
  { 384, 128 }, // qsub_3
955
  { 0, 32 },  // ssub_0
956
  { 32, 32 }, // ssub_1
957
  { 64, 32 }, // ssub_2
958
  { 96, 32 }, // ssub_3
959
  { 128, 32 },  // ssub_4
960
  { 160, 32 },  // ssub_5
961
  { 192, 32 },  // ssub_6
962
  { 224, 32 },  // ssub_7
963
  { 256, 32 },  // ssub_8
964
  { 288, 32 },  // ssub_9
965
  { 320, 32 },  // ssub_10
966
  { 352, 32 },  // ssub_11
967
  { 384, 32 },  // ssub_12
968
  { 416, 32 },  // ssub_13
969
  { 448, 32 },  // dsub_7_then_ssub_0
970
  { 480, 32 },  // dsub_7_then_ssub_1
971
  { 65535, 128 }, // ssub_0_ssub_1_ssub_4_ssub_5
972
  { 0, 192 }, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
973
  { 65535, 128 }, // ssub_2_ssub_3_ssub_6_ssub_7
974
  { 64, 192 },  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
975
  { 64, 128 },  // ssub_2_ssub_3_ssub_4_ssub_5
976
  { 65535, 192 }, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
977
  { 65535, 256 }, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
978
  { 65535, 192 }, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
979
  { 65535, 256 }, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
980
  { 64, 256 },  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
981
  { 65535, 128 }, // ssub_4_ssub_5_ssub_8_ssub_9
982
  { 128, 192 }, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
983
  { 65535, 192 }, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
984
  { 65535, 128 }, // ssub_6_ssub_7_dsub_5
985
  { 192, 192 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
986
  { 65535, 192 }, // ssub_6_ssub_7_dsub_5_dsub_7
987
  { 192, 128 }, // ssub_6_ssub_7_ssub_8_ssub_9
988
  { 192, 256 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
989
  { 65535, 128 }, // ssub_8_ssub_9_ssub_12_ssub_13
990
  { 256, 192 }, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
991
  { 65535, 128 }, // dsub_5_dsub_7
992
  { 320, 192 }, // dsub_5_ssub_12_ssub_13_dsub_7
993
  { 320, 128 }, // dsub_5_ssub_12_ssub_13
994
  { 128, 256 }, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
995
};
996
997
extern const char ARMRegStrings[] = {
998
  /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
999
  /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
1000
  /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
1001
  /* 39 */ 'R', '1', '0', 0,
1002
  /* 43 */ 'S', '1', '0', 0,
1003
  /* 47 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
1004
  /* 63 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
1005
  /* 79 */ 'S', '2', '0', 0,
1006
  /* 83 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
1007
  /* 99 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
1008
  /* 115 */ 'S', '3', '0', 0,
1009
  /* 119 */ 'D', '0', 0,
1010
  /* 122 */ 'Q', '0', 0,
1011
  /* 125 */ 'M', 'V', 'F', 'R', '0', 0,
1012
  /* 131 */ 'S', '0', 0,
1013
  /* 134 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
1014
  /* 145 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
1015
  /* 158 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
1016
  /* 172 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
1017
  /* 180 */ 'S', '1', '1', 0,
1018
  /* 184 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
1019
  /* 196 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
1020
  /* 212 */ 'S', '2', '1', 0,
1021
  /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
1022
  /* 228 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
1023
  /* 244 */ 'S', '3', '1', 0,
1024
  /* 248 */ 'D', '1', 0,
1025
  /* 251 */ 'Q', '0', '_', 'Q', '1', 0,
1026
  /* 257 */ 'M', 'V', 'F', 'R', '1', 0,
1027
  /* 263 */ 'R', '0', '_', 'R', '1', 0,
1028
  /* 269 */ 'S', '1', 0,
1029
  /* 272 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
1030
  /* 286 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
1031
  /* 301 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
1032
  /* 316 */ 'R', '1', '2', 0,
1033
  /* 320 */ 'S', '1', '2', 0,
1034
  /* 324 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
1035
  /* 340 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
1036
  /* 356 */ 'S', '2', '2', 0,
1037
  /* 360 */ 'D', '0', '_', 'D', '2', 0,
1038
  /* 366 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
1039
  /* 375 */ 'Q', '1', '_', 'Q', '2', 0,
1040
  /* 381 */ 'M', 'V', 'F', 'R', '2', 0,
1041
  /* 387 */ 'S', '2', 0,
1042
  /* 390 */ 'F', 'P', 'I', 'N', 'S', 'T', '2', 0,
1043
  /* 398 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
1044
  /* 412 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
1045
  /* 424 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
1046
  /* 440 */ 'S', '1', '3', 0,
1047
  /* 444 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
1048
  /* 460 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
1049
  /* 472 */ 'S', '2', '3', 0,
1050
  /* 476 */ 'D', '1', '_', 'D', '3', 0,
1051
  /* 482 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
1052
  /* 491 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
1053
  /* 503 */ 'R', '2', '_', 'R', '3', 0,
1054
  /* 509 */ 'S', '3', 0,
1055
  /* 512 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
1056
  /* 527 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
1057
  /* 543 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
1058
  /* 559 */ 'S', '1', '4', 0,
1059
  /* 563 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
1060
  /* 579 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
1061
  /* 595 */ 'S', '2', '4', 0,
1062
  /* 599 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
1063
  /* 608 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
1064
  /* 620 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
1065
  /* 632 */ 'R', '4', 0,
1066
  /* 635 */ 'S', '4', 0,
1067
  /* 638 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
1068
  /* 653 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
1069
  /* 665 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
1070
  /* 681 */ 'S', '1', '5', 0,
1071
  /* 685 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
1072
  /* 701 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
1073
  /* 713 */ 'S', '2', '5', 0,
1074
  /* 717 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
1075
  /* 726 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
1076
  /* 735 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
1077
  /* 747 */ 'R', '4', '_', 'R', '5', 0,
1078
  /* 753 */ 'S', '5', 0,
1079
  /* 756 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
1080
  /* 772 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
1081
  /* 788 */ 'S', '1', '6', 0,
1082
  /* 792 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
1083
  /* 808 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
1084
  /* 824 */ 'S', '2', '6', 0,
1085
  /* 828 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
1086
  /* 840 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
1087
  /* 852 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
1088
  /* 864 */ 'R', '6', 0,
1089
  /* 867 */ 'S', '6', 0,
1090
  /* 870 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
1091
  /* 886 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
1092
  /* 898 */ 'S', '1', '7', 0,
1093
  /* 902 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
1094
  /* 918 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
1095
  /* 930 */ 'S', '2', '7', 0,
1096
  /* 934 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
1097
  /* 946 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
1098
  /* 955 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
1099
  /* 967 */ 'R', '6', '_', 'R', '7', 0,
1100
  /* 973 */ 'S', '7', 0,
1101
  /* 976 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
1102
  /* 992 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
1103
  /* 1008 */ 'S', '1', '8', 0,
1104
  /* 1012 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
1105
  /* 1028 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
1106
  /* 1044 */ 'S', '2', '8', 0,
1107
  /* 1048 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
1108
  /* 1060 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
1109
  /* 1072 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
1110
  /* 1084 */ 'R', '8', 0,
1111
  /* 1087 */ 'S', '8', 0,
1112
  /* 1090 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
1113
  /* 1106 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
1114
  /* 1118 */ 'S', '1', '9', 0,
1115
  /* 1122 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
1116
  /* 1138 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
1117
  /* 1150 */ 'S', '2', '9', 0,
1118
  /* 1154 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
1119
  /* 1166 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
1120
  /* 1175 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
1121
  /* 1187 */ 'R', '8', '_', 'R', '9', 0,
1122
  /* 1193 */ 'S', '9', 0,
1123
  /* 1196 */ 'P', 'C', 0,
1124
  /* 1199 */ 'F', 'P', 'E', 'X', 'C', 0,
1125
  /* 1205 */ 'F', 'P', 'S', 'I', 'D', 0,
1126
  /* 1211 */ 'I', 'T', 'S', 'T', 'A', 'T', 'E', 0,
1127
  /* 1219 */ 'R', '1', '2', '_', 'S', 'P', 0,
1128
  /* 1226 */ 'F', 'P', 'S', 'C', 'R', 0,
1129
  /* 1232 */ 'L', 'R', 0,
1130
  /* 1235 */ 'A', 'P', 'S', 'R', 0,
1131
  /* 1240 */ 'C', 'P', 'S', 'R', 0,
1132
  /* 1245 */ 'S', 'P', 'S', 'R', 0,
1133
  /* 1250 */ 'F', 'P', 'I', 'N', 'S', 'T', 0,
1134
  /* 1257 */ 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 0,
1135
  /* 1268 */ 'A', 'P', 'S', 'R', '_', 'N', 'Z', 'C', 'V', 0,
1136
};
1137
1138
extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors
1139
  { 12, 0, 0, 0, 0, 0 },
1140
  { 1235, 16, 16, 2, 66945, 0 },
1141
  { 1268, 16, 16, 2, 66945, 0 },
1142
  { 1240, 16, 16, 2, 66945, 0 },
1143
  { 1199, 16, 16, 2, 66945, 0 },
1144
  { 1250, 16, 16, 2, 66945, 0 },
1145
  { 1226, 16, 16, 2, 17664, 0 },
1146
  { 1257, 16, 16, 2, 17664, 0 },
1147
  { 1205, 16, 16, 2, 66913, 0 },
1148
  { 1211, 16, 16, 2, 66913, 0 },
1149
  { 1232, 16, 16, 2, 66913, 0 },
1150
  { 1196, 16, 16, 2, 66913, 0 },
1151
  { 1223, 16, 1526, 2, 66913, 0 },
1152
  { 1245, 16, 16, 2, 66913, 0 },
1153
  { 119, 350, 4013, 19, 13250, 8 },
1154
  { 248, 357, 2479, 19, 13250, 8 },
1155
  { 363, 364, 3957, 19, 13250, 8 },
1156
  { 479, 378, 3845, 19, 13250, 8 },
1157
  { 605, 392, 3893, 19, 13250, 8 },
1158
  { 723, 406, 3724, 19, 13250, 8 },
1159
  { 837, 420, 3780, 19, 13250, 8 },
1160
  { 943, 434, 3604, 19, 13250, 8 },
1161
  { 1057, 448, 3664, 19, 13250, 8 },
1162
  { 1163, 462, 3484, 19, 13250, 8 },
1163
  { 9, 476, 3544, 19, 13250, 8 },
1164
  { 141, 490, 3364, 19, 13250, 8 },
1165
  { 282, 504, 3424, 19, 13250, 8 },
1166
  { 408, 518, 3244, 19, 13250, 8 },
1167
  { 523, 532, 3304, 19, 13250, 8 },
1168
  { 649, 546, 3149, 19, 13250, 8 },
1169
  { 768, 16, 3208, 2, 17761, 0 },
1170
  { 882, 16, 3078, 2, 17761, 0 },
1171
  { 988, 16, 3113, 2, 17761, 0 },
1172
  { 1102, 16, 3008, 2, 17761, 0 },
1173
  { 59, 16, 3043, 2, 17761, 0 },
1174
  { 192, 16, 2938, 2, 17761, 0 },
1175
  { 336, 16, 2973, 2, 17761, 0 },
1176
  { 456, 16, 2868, 2, 17761, 0 },
1177
  { 575, 16, 2903, 2, 17761, 0 },
1178
  { 697, 16, 2797, 2, 17761, 0 },
1179
  { 804, 16, 2837, 2, 17761, 0 },
1180
  { 914, 16, 2363, 2, 17761, 0 },
1181
  { 1024, 16, 2411, 2, 17761, 0 },
1182
  { 1134, 16, 2384, 2, 17761, 0 },
1183
  { 95, 16, 2429, 2, 17761, 0 },
1184
  { 224, 16, 2789, 2, 17761, 0 },
1185
  { 390, 16, 16, 2, 17761, 0 },
1186
  { 125, 16, 16, 2, 17761, 0 },
1187
  { 257, 16, 16, 2, 17761, 0 },
1188
  { 381, 16, 16, 2, 17761, 0 },
1189
  { 122, 353, 1112, 22, 2196, 11 },
1190
  { 254, 374, 775, 22, 2196, 11 },
1191
  { 378, 402, 314, 22, 2196, 11 },
1192
  { 500, 430, 244, 22, 2196, 11 },
1193
  { 629, 458, 234, 22, 2196, 11 },
1194
  { 744, 486, 224, 22, 2196, 11 },
1195
  { 861, 514, 214, 22, 2196, 11 },
1196
  { 964, 542, 204, 22, 2196, 11 },
1197
  { 1081, 804, 194, 0, 12818, 20 },
1198
  { 1184, 807, 184, 0, 12818, 20 },
1199
  { 35, 810, 174, 0, 12818, 20 },
1200
  { 168, 813, 164, 0, 12818, 20 },
1201
  { 312, 816, 154, 0, 12818, 20 },
1202
  { 436, 819, 591, 0, 12818, 20 },
1203
  { 555, 822, 2447, 0, 12818, 20 },
1204
  { 677, 825, 1106, 0, 12818, 20 },
1205
  { 128, 16, 1373, 2, 66913, 0 },
1206
  { 260, 16, 1371, 2, 66913, 0 },
1207
  { 384, 16, 1371, 2, 66913, 0 },
1208
  { 506, 16, 1369, 2, 66913, 0 },
1209
  { 632, 16, 1369, 2, 66913, 0 },
1210
  { 750, 16, 1367, 2, 66913, 0 },
1211
  { 864, 16, 1367, 2, 66913, 0 },
1212
  { 970, 16, 1365, 2, 66913, 0 },
1213
  { 1084, 16, 1365, 2, 66913, 0 },
1214
  { 1190, 16, 1363, 2, 66913, 0 },
1215
  { 39, 16, 1363, 2, 66913, 0 },
1216
  { 176, 16, 1361, 2, 66913, 0 },
1217
  { 316, 16, 1359, 2, 66913, 0 },
1218
  { 131, 16, 4021, 2, 65585, 0 },
1219
  { 269, 16, 4012, 2, 65585, 0 },
1220
  { 387, 16, 2490, 2, 65585, 0 },
1221
  { 509, 16, 2478, 2, 65585, 0 },
1222
  { 635, 16, 3974, 2, 65585, 0 },
1223
  { 753, 16, 3956, 2, 65585, 0 },
1224
  { 867, 16, 3863, 2, 65585, 0 },
1225
  { 973, 16, 3844, 2, 65585, 0 },
1226
  { 1087, 16, 3914, 2, 65585, 0 },
1227
  { 1193, 16, 3892, 2, 65585, 0 },
1228
  { 43, 16, 3745, 2, 65585, 0 },
1229
  { 180, 16, 3723, 2, 65585, 0 },
1230
  { 320, 16, 3803, 2, 65585, 0 },
1231
  { 440, 16, 3779, 2, 65585, 0 },
1232
  { 559, 16, 3627, 2, 65585, 0 },
1233
  { 681, 16, 3603, 2, 65585, 0 },
1234
  { 788, 16, 3687, 2, 65585, 0 },
1235
  { 898, 16, 3663, 2, 65585, 0 },
1236
  { 1008, 16, 3507, 2, 65585, 0 },
1237
  { 1118, 16, 3483, 2, 65585, 0 },
1238
  { 79, 16, 3567, 2, 65585, 0 },
1239
  { 212, 16, 3543, 2, 65585, 0 },
1240
  { 356, 16, 3387, 2, 65585, 0 },
1241
  { 472, 16, 3363, 2, 65585, 0 },
1242
  { 595, 16, 3447, 2, 65585, 0 },
1243
  { 713, 16, 3423, 2, 65585, 0 },
1244
  { 824, 16, 3267, 2, 65585, 0 },
1245
  { 930, 16, 3243, 2, 65585, 0 },
1246
  { 1044, 16, 3327, 2, 65585, 0 },
1247
  { 1150, 16, 3303, 2, 65585, 0 },
1248
  { 115, 16, 3172, 2, 65585, 0 },
1249
  { 244, 16, 3148, 2, 65585, 0 },
1250
  { 360, 367, 4015, 29, 5426, 23 },
1251
  { 476, 381, 2502, 29, 5426, 23 },
1252
  { 602, 395, 3992, 29, 5426, 23 },
1253
  { 720, 409, 3882, 29, 5426, 23 },
1254
  { 834, 423, 3936, 29, 5426, 23 },
1255
  { 940, 437, 3767, 29, 5426, 23 },
1256
  { 1054, 451, 3827, 29, 5426, 23 },
1257
  { 1160, 465, 3651, 29, 5426, 23 },
1258
  { 6, 479, 3711, 29, 5426, 23 },
1259
  { 151, 493, 3531, 29, 5426, 23 },
1260
  { 278, 507, 3591, 29, 5426, 23 },
1261
  { 404, 521, 3411, 29, 5426, 23 },
1262
  { 519, 535, 3471, 29, 5426, 23 },
1263
  { 645, 549, 3291, 29, 5426, 23 },
1264
  { 764, 4007, 3351, 11, 17602, 35 },
1265
  { 878, 3948, 3196, 11, 13522, 35 },
1266
  { 984, 1080, 3231, 8, 17329, 39 },
1267
  { 1098, 1080, 3101, 8, 17329, 39 },
1268
  { 55, 1080, 3136, 8, 17329, 39 },
1269
  { 204, 1080, 3031, 8, 17329, 39 },
1270
  { 332, 1080, 3066, 8, 17329, 39 },
1271
  { 452, 1080, 2961, 8, 17329, 39 },
1272
  { 571, 1080, 2996, 8, 17329, 39 },
1273
  { 693, 1080, 2891, 8, 17329, 39 },
1274
  { 800, 1080, 2926, 8, 17329, 39 },
1275
  { 910, 1080, 2820, 8, 17329, 39 },
1276
  { 1020, 1080, 2858, 8, 17329, 39 },
1277
  { 1130, 1080, 2401, 8, 17329, 39 },
1278
  { 91, 1080, 2440, 8, 17329, 39 },
1279
  { 236, 1080, 2791, 8, 17329, 39 },
1280
  { 251, 1339, 1114, 168, 1044, 57 },
1281
  { 375, 1319, 347, 168, 1044, 57 },
1282
  { 497, 1299, 142, 168, 1044, 57 },
1283
  { 626, 1279, 142, 168, 1044, 57 },
1284
  { 741, 1259, 142, 168, 1044, 57 },
1285
  { 858, 1239, 142, 168, 1044, 57 },
1286
  { 961, 1219, 142, 168, 1044, 57 },
1287
  { 1078, 1203, 142, 88, 1456, 74 },
1288
  { 1181, 1191, 142, 76, 2114, 87 },
1289
  { 32, 1179, 142, 76, 2114, 87 },
1290
  { 164, 1167, 142, 76, 2114, 87 },
1291
  { 308, 1155, 142, 76, 2114, 87 },
1292
  { 432, 1143, 142, 76, 2114, 87 },
1293
  { 551, 1131, 344, 76, 2114, 87 },
1294
  { 673, 1119, 1108, 76, 2114, 87 },
1295
  { 491, 2156, 16, 474, 4, 149 },
1296
  { 620, 2101, 16, 474, 4, 149 },
1297
  { 735, 2046, 16, 474, 4, 149 },
1298
  { 852, 1991, 16, 474, 4, 149 },
1299
  { 955, 1936, 16, 474, 4, 149 },
1300
  { 1072, 1885, 16, 423, 272, 166 },
1301
  { 1175, 1838, 16, 376, 512, 181 },
1302
  { 26, 1795, 16, 333, 720, 194 },
1303
  { 158, 1756, 16, 294, 1186, 205 },
1304
  { 301, 1717, 16, 294, 1186, 205 },
1305
  { 424, 1678, 16, 294, 1186, 205 },
1306
  { 543, 1639, 16, 294, 1186, 205 },
1307
  { 665, 1600, 16, 294, 1186, 205 },
1308
  { 1219, 4114, 16, 16, 17856, 2 },
1309
  { 263, 783, 16, 16, 8946, 5 },
1310
  { 503, 786, 16, 16, 8946, 5 },
1311
  { 747, 789, 16, 16, 8946, 5 },
1312
  { 967, 792, 16, 16, 8946, 5 },
1313
  { 1187, 795, 16, 16, 8946, 5 },
1314
  { 172, 798, 16, 16, 8946, 5 },
1315
  { 366, 1513, 1113, 63, 1570, 28 },
1316
  { 482, 4169, 2511, 63, 1570, 28 },
1317
  { 611, 1500, 778, 63, 1570, 28 },
1318
  { 726, 4156, 770, 63, 1570, 28 },
1319
  { 843, 1487, 317, 63, 1570, 28 },
1320
  { 946, 4143, 660, 63, 1570, 28 },
1321
  { 1063, 1474, 308, 63, 1570, 28 },
1322
  { 1166, 4130, 654, 63, 1570, 28 },
1323
  { 16, 1461, 302, 63, 1570, 28 },
1324
  { 134, 4117, 648, 63, 1570, 28 },
1325
  { 289, 1448, 296, 63, 1570, 28 },
1326
  { 412, 4101, 642, 63, 1570, 28 },
1327
  { 531, 1435, 290, 63, 1570, 28 },
1328
  { 653, 4088, 636, 63, 1570, 28 },
1329
  { 776, 1424, 284, 52, 1680, 42 },
1330
  { 886, 4079, 630, 43, 1872, 48 },
1331
  { 996, 1417, 278, 36, 2401, 53 },
1332
  { 1106, 4072, 624, 36, 2401, 53 },
1333
  { 67, 1410, 272, 36, 2401, 53 },
1334
  { 184, 4065, 618, 36, 2401, 53 },
1335
  { 344, 1403, 266, 36, 2401, 53 },
1336
  { 460, 4058, 612, 36, 2401, 53 },
1337
  { 583, 1396, 260, 36, 2401, 53 },
1338
  { 701, 4051, 606, 36, 2401, 53 },
1339
  { 812, 1389, 254, 36, 2401, 53 },
1340
  { 918, 4044, 600, 36, 2401, 53 },
1341
  { 1032, 1382, 765, 36, 2401, 53 },
1342
  { 1138, 4037, 2455, 36, 2401, 53 },
1343
  { 103, 1375, 2474, 36, 2401, 53 },
1344
  { 216, 4030, 1107, 36, 2401, 53 },
1345
  { 599, 1026, 4018, 212, 5314, 92 },
1346
  { 717, 1014, 3953, 212, 5314, 92 },
1347
  { 831, 1002, 4002, 212, 5314, 92 },
1348
  { 937, 990, 3909, 212, 5314, 92 },
1349
  { 1051, 978, 3909, 212, 5314, 92 },
1350
  { 1157, 966, 3798, 212, 5314, 92 },
1351
  { 3, 954, 3798, 212, 5314, 92 },
1352
  { 148, 942, 3682, 212, 5314, 92 },
1353
  { 275, 930, 3682, 212, 5314, 92 },
1354
  { 401, 918, 3562, 212, 5314, 92 },
1355
  { 515, 906, 3562, 212, 5314, 92 },
1356
  { 641, 894, 3442, 212, 5314, 92 },
1357
  { 760, 1070, 3442, 202, 17506, 99 },
1358
  { 874, 1060, 3322, 202, 13426, 99 },
1359
  { 980, 1052, 3322, 194, 14226, 105 },
1360
  { 1094, 1044, 3226, 194, 13698, 105 },
1361
  { 51, 1038, 3226, 188, 14049, 110 },
1362
  { 200, 1038, 3131, 188, 14049, 110 },
1363
  { 328, 1038, 3131, 188, 14049, 110 },
1364
  { 448, 1038, 3061, 188, 14049, 110 },
1365
  { 567, 1038, 3061, 188, 14049, 110 },
1366
  { 689, 1038, 2991, 188, 14049, 110 },
1367
  { 796, 1038, 2991, 188, 14049, 110 },
1368
  { 906, 1038, 2921, 188, 14049, 110 },
1369
  { 1016, 1038, 2921, 188, 14049, 110 },
1370
  { 1126, 1038, 2832, 188, 14049, 110 },
1371
  { 87, 1038, 2855, 188, 14049, 110 },
1372
  { 232, 1038, 2794, 188, 14049, 110 },
1373
  { 828, 2677, 4010, 276, 5170, 114 },
1374
  { 934, 2659, 3951, 276, 5170, 114 },
1375
  { 1048, 2641, 3951, 276, 5170, 114 },
1376
  { 1154, 2623, 3842, 276, 5170, 114 },
1377
  { 0, 2605, 3842, 276, 5170, 114 },
1378
  { 145, 2587, 3743, 276, 5170, 114 },
1379
  { 272, 2569, 3743, 276, 5170, 114 },
1380
  { 398, 2551, 3625, 276, 5170, 114 },
1381
  { 512, 2533, 3625, 276, 5170, 114 },
1382
  { 638, 2515, 3505, 276, 5170, 114 },
1383
  { 756, 2773, 3505, 260, 17378, 123 },
1384
  { 870, 2757, 3385, 260, 13298, 123 },
1385
  { 976, 2743, 3385, 246, 14114, 131 },
1386
  { 1090, 2729, 3265, 246, 13586, 131 },
1387
  { 47, 2717, 3265, 234, 13954, 138 },
1388
  { 196, 2705, 3170, 234, 13778, 138 },
1389
  { 324, 2695, 3170, 224, 13873, 144 },
1390
  { 444, 2695, 3099, 224, 13873, 144 },
1391
  { 563, 2695, 3099, 224, 13873, 144 },
1392
  { 685, 2695, 3029, 224, 13873, 144 },
1393
  { 792, 2695, 3029, 224, 13873, 144 },
1394
  { 902, 2695, 2959, 224, 13873, 144 },
1395
  { 1012, 2695, 2959, 224, 13873, 144 },
1396
  { 1122, 2695, 2856, 224, 13873, 144 },
1397
  { 83, 2695, 2856, 224, 13873, 144 },
1398
  { 228, 2695, 2795, 224, 13873, 144 },
1399
  { 369, 360, 2509, 22, 1956, 11 },
1400
  { 614, 388, 583, 22, 1956, 11 },
1401
  { 846, 416, 756, 22, 1956, 11 },
1402
  { 1066, 444, 747, 22, 1956, 11 },
1403
  { 19, 472, 738, 22, 1956, 11 },
1404
  { 293, 500, 729, 22, 1956, 11 },
1405
  { 535, 528, 720, 22, 1956, 11 },
1406
  { 780, 3839, 711, 3, 2336, 16 },
1407
  { 1000, 562, 702, 0, 8898, 20 },
1408
  { 71, 565, 693, 0, 8898, 20 },
1409
  { 348, 568, 684, 0, 8898, 20 },
1410
  { 587, 571, 675, 0, 8898, 20 },
1411
  { 816, 574, 666, 0, 8898, 20 },
1412
  { 1036, 577, 2460, 0, 8898, 20 },
1413
  { 107, 580, 2468, 0, 8898, 20 },
1414
  { 608, 2343, 2488, 148, 900, 57 },
1415
  { 840, 2323, 588, 148, 900, 57 },
1416
  { 1060, 2303, 588, 148, 900, 57 },
1417
  { 13, 2283, 588, 148, 900, 57 },
1418
  { 286, 2263, 588, 148, 900, 57 },
1419
  { 527, 2243, 588, 148, 900, 57 },
1420
  { 772, 2225, 588, 130, 1328, 66 },
1421
  { 992, 2211, 588, 116, 1776, 81 },
1422
  { 63, 1588, 588, 104, 2034, 87 },
1423
  { 340, 1576, 588, 104, 2034, 87 },
1424
  { 579, 1564, 588, 104, 2034, 87 },
1425
  { 808, 1552, 588, 104, 2034, 87 },
1426
  { 1028, 1540, 588, 104, 2034, 87 },
1427
  { 99, 1528, 2382, 104, 2034, 87 },
1428
};
1429
1430
extern const MCPhysReg ARMRegUnitRoots[][2] = {
1431
  { ARM::APSR },
1432
  { ARM::APSR_NZCV },
1433
  { ARM::CPSR },
1434
  { ARM::FPEXC },
1435
  { ARM::FPINST },
1436
  { ARM::FPSCR, ARM::FPSCR_NZCV },
1437
  { ARM::FPSID },
1438
  { ARM::ITSTATE },
1439
  { ARM::LR },
1440
  { ARM::PC },
1441
  { ARM::SP },
1442
  { ARM::SPSR },
1443
  { ARM::S0 },
1444
  { ARM::S1 },
1445
  { ARM::S2 },
1446
  { ARM::S3 },
1447
  { ARM::S4 },
1448
  { ARM::S5 },
1449
  { ARM::S6 },
1450
  { ARM::S7 },
1451
  { ARM::S8 },
1452
  { ARM::S9 },
1453
  { ARM::S10 },
1454
  { ARM::S11 },
1455
  { ARM::S12 },
1456
  { ARM::S13 },
1457
  { ARM::S14 },
1458
  { ARM::S15 },
1459
  { ARM::S16 },
1460
  { ARM::S17 },
1461
  { ARM::S18 },
1462
  { ARM::S19 },
1463
  { ARM::S20 },
1464
  { ARM::S21 },
1465
  { ARM::S22 },
1466
  { ARM::S23 },
1467
  { ARM::S24 },
1468
  { ARM::S25 },
1469
  { ARM::S26 },
1470
  { ARM::S27 },
1471
  { ARM::S28 },
1472
  { ARM::S29 },
1473
  { ARM::S30 },
1474
  { ARM::S31 },
1475
  { ARM::D16 },
1476
  { ARM::D17 },
1477
  { ARM::D18 },
1478
  { ARM::D19 },
1479
  { ARM::D20 },
1480
  { ARM::D21 },
1481
  { ARM::D22 },
1482
  { ARM::D23 },
1483
  { ARM::D24 },
1484
  { ARM::D25 },
1485
  { ARM::D26 },
1486
  { ARM::D27 },
1487
  { ARM::D28 },
1488
  { ARM::D29 },
1489
  { ARM::D30 },
1490
  { ARM::D31 },
1491
  { ARM::FPINST2 },
1492
  { ARM::MVFR0 },
1493
  { ARM::MVFR1 },
1494
  { ARM::MVFR2 },
1495
  { ARM::R0 },
1496
  { ARM::R1 },
1497
  { ARM::R2 },
1498
  { ARM::R3 },
1499
  { ARM::R4 },
1500
  { ARM::R5 },
1501
  { ARM::R6 },
1502
  { ARM::R7 },
1503
  { ARM::R8 },
1504
  { ARM::R9 },
1505
  { ARM::R10 },
1506
  { ARM::R11 },
1507
  { ARM::R12 },
1508
};
1509
1510
namespace {     // Register classes...
1511
  // SPR Register Class...
1512
  const MCPhysReg SPR[] = {
1513
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, 
1514
  };
1515
1516
  // SPR Bit set.
1517
  const uint8_t SPRBits[] = {
1518
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
1519
  };
1520
1521
  // GPR Register Class...
1522
  const MCPhysReg GPR[] = {
1523
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
1524
  };
1525
1526
  // GPR Bit set.
1527
  const uint8_t GPRBits[] = {
1528
    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1529
  };
1530
1531
  // GPRwithAPSR Register Class...
1532
  const MCPhysReg GPRwithAPSR[] = {
1533
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV, 
1534
  };
1535
1536
  // GPRwithAPSR Bit set.
1537
  const uint8_t GPRwithAPSRBits[] = {
1538
    0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1539
  };
1540
1541
  // SPR_8 Register Class...
1542
  const MCPhysReg SPR_8[] = {
1543
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, 
1544
  };
1545
1546
  // SPR_8 Bit set.
1547
  const uint8_t SPR_8Bits[] = {
1548
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
1549
  };
1550
1551
  // GPRnopc Register Class...
1552
  const MCPhysReg GPRnopc[] = {
1553
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
1554
  };
1555
1556
  // GPRnopc Bit set.
1557
  const uint8_t GPRnopcBits[] = {
1558
    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1559
  };
1560
1561
  // rGPR Register Class...
1562
  const MCPhysReg rGPR[] = {
1563
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
1564
  };
1565
1566
  // rGPR Bit set.
1567
  const uint8_t rGPRBits[] = {
1568
    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1569
  };
1570
1571
  // tGPRwithpc Register Class...
1572
  const MCPhysReg tGPRwithpc[] = {
1573
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC, 
1574
  };
1575
1576
  // tGPRwithpc Bit set.
1577
  const uint8_t tGPRwithpcBits[] = {
1578
    0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1579
  };
1580
1581
  // hGPR Register Class...
1582
  const MCPhysReg hGPR[] = {
1583
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
1584
  };
1585
1586
  // hGPR Bit set.
1587
  const uint8_t hGPRBits[] = {
1588
    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
1589
  };
1590
1591
  // tGPR Register Class...
1592
  const MCPhysReg tGPR[] = {
1593
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, 
1594
  };
1595
1596
  // tGPR Bit set.
1597
  const uint8_t tGPRBits[] = {
1598
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1599
  };
1600
1601
  // GPRnopc_and_hGPR Register Class...
1602
  const MCPhysReg GPRnopc_and_hGPR[] = {
1603
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
1604
  };
1605
1606
  // GPRnopc_and_hGPR Bit set.
1607
  const uint8_t GPRnopc_and_hGPRBits[] = {
1608
    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
1609
  };
1610
1611
  // hGPR_and_rGPR Register Class...
1612
  const MCPhysReg hGPR_and_rGPR[] = {
1613
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
1614
  };
1615
1616
  // hGPR_and_rGPR Bit set.
1617
  const uint8_t hGPR_and_rGPRBits[] = {
1618
    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
1619
  };
1620
1621
  // tcGPR Register Class...
1622
  const MCPhysReg tcGPR[] = {
1623
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, 
1624
  };
1625
1626
  // tcGPR Bit set.
1627
  const uint8_t tcGPRBits[] = {
1628
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40, 
1629
  };
1630
1631
  // tGPR_and_tcGPR Register Class...
1632
  const MCPhysReg tGPR_and_tcGPR[] = {
1633
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, 
1634
  };
1635
1636
  // tGPR_and_tcGPR Bit set.
1637
  const uint8_t tGPR_and_tcGPRBits[] = {
1638
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
1639
  };
1640
1641
  // CCR Register Class...
1642
  const MCPhysReg CCR[] = {
1643
    ARM::CPSR, 
1644
  };
1645
1646
  // CCR Bit set.
1647
  const uint8_t CCRBits[] = {
1648
    0x08, 
1649
  };
1650
1651
  // GPRsp Register Class...
1652
  const MCPhysReg GPRsp[] = {
1653
    ARM::SP, 
1654
  };
1655
1656
  // GPRsp Bit set.
1657
  const uint8_t GPRspBits[] = {
1658
    0x00, 0x10, 
1659
  };
1660
1661
  // hGPR_and_tGPRwithpc Register Class...
1662
  const MCPhysReg hGPR_and_tGPRwithpc[] = {
1663
    ARM::PC, 
1664
  };
1665
1666
  // hGPR_and_tGPRwithpc Bit set.
1667
  const uint8_t hGPR_and_tGPRwithpcBits[] = {
1668
    0x00, 0x08, 
1669
  };
1670
1671
  // hGPR_and_tcGPR Register Class...
1672
  const MCPhysReg hGPR_and_tcGPR[] = {
1673
    ARM::R12, 
1674
  };
1675
1676
  // hGPR_and_tcGPR Bit set.
1677
  const uint8_t hGPR_and_tcGPRBits[] = {
1678
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
1679
  };
1680
1681
  // DPR Register Class...
1682
  const MCPhysReg DPR[] = {
1683
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 
1684
  };
1685
1686
  // DPR Bit set.
1687
  const uint8_t DPRBits[] = {
1688
    0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
1689
  };
1690
1691
  // DPR_VFP2 Register Class...
1692
  const MCPhysReg DPR_VFP2[] = {
1693
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, 
1694
  };
1695
1696
  // DPR_VFP2 Bit set.
1697
  const uint8_t DPR_VFP2Bits[] = {
1698
    0x00, 0xc0, 0xff, 0x3f, 
1699
  };
1700
1701
  // DPR_8 Register Class...
1702
  const MCPhysReg DPR_8[] = {
1703
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, 
1704
  };
1705
1706
  // DPR_8 Bit set.
1707
  const uint8_t DPR_8Bits[] = {
1708
    0x00, 0xc0, 0x3f, 
1709
  };
1710
1711
  // GPRPair Register Class...
1712
  const MCPhysReg GPRPair[] = {
1713
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
1714
  };
1715
1716
  // GPRPair Bit set.
1717
  const uint8_t GPRPairBits[] = {
1718
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 
1719
  };
1720
1721
  // GPRPair_with_gsub_1_in_rGPR Register Class...
1722
  const MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = {
1723
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, 
1724
  };
1725
1726
  // GPRPair_with_gsub_1_in_rGPR Bit set.
1727
  const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = {
1728
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 
1729
  };
1730
1731
  // GPRPair_with_gsub_0_in_tGPR Register Class...
1732
  const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
1733
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 
1734
  };
1735
1736
  // GPRPair_with_gsub_0_in_tGPR Bit set.
1737
  const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
1738
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
1739
  };
1740
1741
  // GPRPair_with_gsub_0_in_hGPR Register Class...
1742
  const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
1743
    ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
1744
  };
1745
1746
  // GPRPair_with_gsub_0_in_hGPR Bit set.
1747
  const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
1748
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 
1749
  };
1750
1751
  // GPRPair_with_gsub_0_in_tcGPR Register Class...
1752
  const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
1753
    ARM::R0_R1, ARM::R2_R3, ARM::R12_SP, 
1754
  };
1755
1756
  // GPRPair_with_gsub_0_in_tcGPR Bit set.
1757
  const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
1758
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 
1759
  };
1760
1761
  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class...
1762
  const MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = {
1763
    ARM::R8_R9, ARM::R10_R11, 
1764
  };
1765
1766
  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set.
1767
  const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = {
1768
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 
1769
  };
1770
1771
  // GPRPair_with_gsub_1_in_tcGPR Register Class...
1772
  const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
1773
    ARM::R0_R1, ARM::R2_R3, 
1774
  };
1775
1776
  // GPRPair_with_gsub_1_in_tcGPR Bit set.
1777
  const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
1778
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 
1779
  };
1780
1781
  // GPRPair_with_gsub_1_in_GPRsp Register Class...
1782
  const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
1783
    ARM::R12_SP, 
1784
  };
1785
1786
  // GPRPair_with_gsub_1_in_GPRsp Bit set.
1787
  const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
1788
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
1789
  };
1790
1791
  // DPairSpc Register Class...
1792
  const MCPhysReg DPairSpc[] = {
1793
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31, 
1794
  };
1795
1796
  // DPairSpc Bit set.
1797
  const uint8_t DPairSpcBits[] = {
1798
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 
1799
  };
1800
1801
  // DPairSpc_with_ssub_0 Register Class...
1802
  const MCPhysReg DPairSpc_with_ssub_0[] = {
1803
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 
1804
  };
1805
1806
  // DPairSpc_with_ssub_0 Bit set.
1807
  const uint8_t DPairSpc_with_ssub_0Bits[] = {
1808
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
1809
  };
1810
1811
  // DPairSpc_with_ssub_4 Register Class...
1812
  const MCPhysReg DPairSpc_with_ssub_4[] = {
1813
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, 
1814
  };
1815
1816
  // DPairSpc_with_ssub_4 Bit set.
1817
  const uint8_t DPairSpc_with_ssub_4Bits[] = {
1818
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 
1819
  };
1820
1821
  // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
1822
  const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
1823
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 
1824
  };
1825
1826
  // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
1827
  const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
1828
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
1829
  };
1830
1831
  // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
1832
  const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
1833
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, 
1834
  };
1835
1836
  // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
1837
  const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
1838
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 
1839
  };
1840
1841
  // DPair Register Class...
1842
  const MCPhysReg DPair[] = {
1843
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15, 
1844
  };
1845
1846
  // DPair Bit set.
1847
  const uint8_t DPairBits[] = {
1848
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
1849
  };
1850
1851
  // DPair_with_ssub_0 Register Class...
1852
  const MCPhysReg DPair_with_ssub_0[] = {
1853
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, 
1854
  };
1855
1856
  // DPair_with_ssub_0 Bit set.
1857
  const uint8_t DPair_with_ssub_0Bits[] = {
1858
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
1859
  };
1860
1861
  // QPR Register Class...
1862
  const MCPhysReg QPR[] = {
1863
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 
1864
  };
1865
1866
  // QPR Bit set.
1867
  const uint8_t QPRBits[] = {
1868
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
1869
  };
1870
1871
  // DPair_with_ssub_2 Register Class...
1872
  const MCPhysReg DPair_with_ssub_2[] = {
1873
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, 
1874
  };
1875
1876
  // DPair_with_ssub_2 Bit set.
1877
  const uint8_t DPair_with_ssub_2Bits[] = {
1878
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
1879
  };
1880
1881
  // DPair_with_dsub_0_in_DPR_8 Register Class...
1882
  const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
1883
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, 
1884
  };
1885
1886
  // DPair_with_dsub_0_in_DPR_8 Bit set.
1887
  const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
1888
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
1889
  };
1890
1891
  // QPR_VFP2 Register Class...
1892
  const MCPhysReg QPR_VFP2[] = {
1893
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 
1894
  };
1895
1896
  // QPR_VFP2 Bit set.
1897
  const uint8_t QPR_VFP2Bits[] = {
1898
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1899
  };
1900
1901
  // DPair_with_dsub_1_in_DPR_8 Register Class...
1902
  const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
1903
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, 
1904
  };
1905
1906
  // DPair_with_dsub_1_in_DPR_8 Bit set.
1907
  const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
1908
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
1909
  };
1910
1911
  // QPR_8 Register Class...
1912
  const MCPhysReg QPR_8[] = {
1913
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 
1914
  };
1915
1916
  // QPR_8 Bit set.
1917
  const uint8_t QPR_8Bits[] = {
1918
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
1919
  };
1920
1921
  // DTriple Register Class...
1922
  const MCPhysReg DTriple[] = {
1923
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31, 
1924
  };
1925
1926
  // DTriple Bit set.
1927
  const uint8_t DTripleBits[] = {
1928
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, 
1929
  };
1930
1931
  // DTripleSpc Register Class...
1932
  const MCPhysReg DTripleSpc[] = {
1933
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
1934
  };
1935
1936
  // DTripleSpc Bit set.
1937
  const uint8_t DTripleSpcBits[] = {
1938
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
1939
  };
1940
1941
  // DTripleSpc_with_ssub_0 Register Class...
1942
  const MCPhysReg DTripleSpc_with_ssub_0[] = {
1943
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
1944
  };
1945
1946
  // DTripleSpc_with_ssub_0 Bit set.
1947
  const uint8_t DTripleSpc_with_ssub_0Bits[] = {
1948
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
1949
  };
1950
1951
  // DTriple_with_ssub_0 Register Class...
1952
  const MCPhysReg DTriple_with_ssub_0[] = {
1953
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, 
1954
  };
1955
1956
  // DTriple_with_ssub_0 Bit set.
1957
  const uint8_t DTriple_with_ssub_0Bits[] = {
1958
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
1959
  };
1960
1961
  // DTriple_with_qsub_0_in_QPR Register Class...
1962
  const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
1963
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30, 
1964
  };
1965
1966
  // DTriple_with_qsub_0_in_QPR Bit set.
1967
  const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
1968
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, 
1969
  };
1970
1971
  // DTriple_with_ssub_2 Register Class...
1972
  const MCPhysReg DTriple_with_ssub_2[] = {
1973
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, 
1974
  };
1975
1976
  // DTriple_with_ssub_2 Bit set.
1977
  const uint8_t DTriple_with_ssub_2Bits[] = {
1978
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 
1979
  };
1980
1981
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1982
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1983
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31, 
1984
  };
1985
1986
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1987
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1988
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a, 
1989
  };
1990
1991
  // DTripleSpc_with_ssub_4 Register Class...
1992
  const MCPhysReg DTripleSpc_with_ssub_4[] = {
1993
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
1994
  };
1995
1996
  // DTripleSpc_with_ssub_4 Bit set.
1997
  const uint8_t DTripleSpc_with_ssub_4Bits[] = {
1998
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
1999
  };
2000
2001
  // DTriple_with_ssub_4 Register Class...
2002
  const MCPhysReg DTriple_with_ssub_4[] = {
2003
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, 
2004
  };
2005
2006
  // DTriple_with_ssub_4 Bit set.
2007
  const uint8_t DTriple_with_ssub_4Bits[] = {
2008
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, 
2009
  };
2010
2011
  // DTripleSpc_with_ssub_8 Register Class...
2012
  const MCPhysReg DTripleSpc_with_ssub_8[] = {
2013
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
2014
  };
2015
2016
  // DTripleSpc_with_ssub_8 Bit set.
2017
  const uint8_t DTripleSpc_with_ssub_8Bits[] = {
2018
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
2019
  };
2020
2021
  // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
2022
  const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
2023
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
2024
  };
2025
2026
  // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
2027
  const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
2028
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2029
  };
2030
2031
  // DTriple_with_dsub_0_in_DPR_8 Register Class...
2032
  const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
2033
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, 
2034
  };
2035
2036
  // DTriple_with_dsub_0_in_DPR_8 Bit set.
2037
  const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
2038
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 
2039
  };
2040
2041
  // DTriple_with_qsub_0_in_QPR_VFP2 Register Class...
2042
  const MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = {
2043
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, 
2044
  };
2045
2046
  // DTriple_with_qsub_0_in_QPR_VFP2 Bit set.
2047
  const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = {
2048
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 
2049
  };
2050
2051
  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2052
  const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2053
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, 
2054
  };
2055
2056
  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2057
  const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2058
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 
2059
  };
2060
2061
  // DTriple_with_dsub_1_in_DPR_8 Register Class...
2062
  const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
2063
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, 
2064
  };
2065
2066
  // DTriple_with_dsub_1_in_DPR_8 Bit set.
2067
  const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
2068
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
2069
  };
2070
2071
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
2072
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
2073
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, 
2074
  };
2075
2076
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
2077
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
2078
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, 
2079
  };
2080
2081
  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Register Class...
2082
  const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR[] = {
2083
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, 
2084
  };
2085
2086
  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Bit set.
2087
  const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits[] = {
2088
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 
2089
  };
2090
2091
  // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
2092
  const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
2093
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
2094
  };
2095
2096
  // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
2097
  const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
2098
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
2099
  };
2100
2101
  // DTriple_with_dsub_2_in_DPR_8 Register Class...
2102
  const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
2103
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, 
2104
  };
2105
2106
  // DTriple_with_dsub_2_in_DPR_8 Bit set.
2107
  const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
2108
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 
2109
  };
2110
2111
  // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
2112
  const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
2113
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
2114
  };
2115
2116
  // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
2117
  const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
2118
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
2119
  };
2120
2121
  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2122
  const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2123
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, 
2124
  };
2125
2126
  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2127
  const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2128
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 
2129
  };
2130
2131
  // DTriple_with_qsub_0_in_QPR_8 Register Class...
2132
  const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
2133
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, 
2134
  };
2135
2136
  // DTriple_with_qsub_0_in_QPR_8 Bit set.
2137
  const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
2138
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 
2139
  };
2140
2141
  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class...
2142
  const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = {
2143
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, 
2144
  };
2145
2146
  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set.
2147
  const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = {
2148
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 
2149
  };
2150
2151
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
2152
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2153
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, 
2154
  };
2155
2156
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
2157
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
2158
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 
2159
  };
2160
2161
  // DQuadSpc Register Class...
2162
  const MCPhysReg DQuadSpc[] = {
2163
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
2164
  };
2165
2166
  // DQuadSpc Bit set.
2167
  const uint8_t DQuadSpcBits[] = {
2168
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
2169
  };
2170
2171
  // DQuadSpc_with_ssub_0 Register Class...
2172
  const MCPhysReg DQuadSpc_with_ssub_0[] = {
2173
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
2174
  };
2175
2176
  // DQuadSpc_with_ssub_0 Bit set.
2177
  const uint8_t DQuadSpc_with_ssub_0Bits[] = {
2178
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
2179
  };
2180
2181
  // DQuadSpc_with_ssub_4 Register Class...
2182
  const MCPhysReg DQuadSpc_with_ssub_4[] = {
2183
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
2184
  };
2185
2186
  // DQuadSpc_with_ssub_4 Bit set.
2187
  const uint8_t DQuadSpc_with_ssub_4Bits[] = {
2188
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
2189
  };
2190
2191
  // DQuadSpc_with_ssub_8 Register Class...
2192
  const MCPhysReg DQuadSpc_with_ssub_8[] = {
2193
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
2194
  };
2195
2196
  // DQuadSpc_with_ssub_8 Bit set.
2197
  const uint8_t DQuadSpc_with_ssub_8Bits[] = {
2198
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
2199
  };
2200
2201
  // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
2202
  const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
2203
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
2204
  };
2205
2206
  // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
2207
  const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
2208
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2209
  };
2210
2211
  // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
2212
  const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
2213
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
2214
  };
2215
2216
  // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
2217
  const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
2218
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
2219
  };
2220
2221
  // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
2222
  const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
2223
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
2224
  };
2225
2226
  // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
2227
  const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
2228
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
2229
  };
2230
2231
  // DQuad Register Class...
2232
  const MCPhysReg DQuad[] = {
2233
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15, 
2234
  };
2235
2236
  // DQuad Bit set.
2237
  const uint8_t DQuadBits[] = {
2238
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
2239
  };
2240
2241
  // DQuad_with_ssub_0 Register Class...
2242
  const MCPhysReg DQuad_with_ssub_0[] = {
2243
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, 
2244
  };
2245
2246
  // DQuad_with_ssub_0 Bit set.
2247
  const uint8_t DQuad_with_ssub_0Bits[] = {
2248
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
2249
  };
2250
2251
  // DQuad_with_ssub_2 Register Class...
2252
  const MCPhysReg DQuad_with_ssub_2[] = {
2253
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, 
2254
  };
2255
2256
  // DQuad_with_ssub_2 Bit set.
2257
  const uint8_t DQuad_with_ssub_2Bits[] = {
2258
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
2259
  };
2260
2261
  // QQPR Register Class...
2262
  const MCPhysReg QQPR[] = {
2263
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, 
2264
  };
2265
2266
  // QQPR Bit set.
2267
  const uint8_t QQPRBits[] = {
2268
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2269
  };
2270
2271
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2272
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2273
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30, 
2274
  };
2275
2276
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2277
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2278
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
2279
  };
2280
2281
  // DQuad_with_ssub_4 Register Class...
2282
  const MCPhysReg DQuad_with_ssub_4[] = {
2283
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, 
2284
  };
2285
2286
  // DQuad_with_ssub_4 Bit set.
2287
  const uint8_t DQuad_with_ssub_4Bits[] = {
2288
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
2289
  };
2290
2291
  // DQuad_with_ssub_6 Register Class...
2292
  const MCPhysReg DQuad_with_ssub_6[] = {
2293
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, 
2294
  };
2295
2296
  // DQuad_with_ssub_6 Bit set.
2297
  const uint8_t DQuad_with_ssub_6Bits[] = {
2298
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
2299
  };
2300
2301
  // DQuad_with_dsub_0_in_DPR_8 Register Class...
2302
  const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
2303
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, 
2304
  };
2305
2306
  // DQuad_with_dsub_0_in_DPR_8 Bit set.
2307
  const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
2308
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
2309
  };
2310
2311
  // DQuad_with_qsub_0_in_QPR_VFP2 Register Class...
2312
  const MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = {
2313
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, 
2314
  };
2315
2316
  // DQuad_with_qsub_0_in_QPR_VFP2 Bit set.
2317
  const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = {
2318
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2319
  };
2320
2321
  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2322
  const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2323
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, 
2324
  };
2325
2326
  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2327
  const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2328
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
2329
  };
2330
2331
  // DQuad_with_dsub_1_in_DPR_8 Register Class...
2332
  const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
2333
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, 
2334
  };
2335
2336
  // DQuad_with_dsub_1_in_DPR_8 Bit set.
2337
  const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
2338
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
2339
  };
2340
2341
  // DQuad_with_qsub_1_in_QPR_VFP2 Register Class...
2342
  const MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = {
2343
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, 
2344
  };
2345
2346
  // DQuad_with_qsub_1_in_QPR_VFP2 Bit set.
2347
  const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = {
2348
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
2349
  };
2350
2351
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
2352
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
2353
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, 
2354
  };
2355
2356
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
2357
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
2358
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
2359
  };
2360
2361
  // DQuad_with_dsub_2_in_DPR_8 Register Class...
2362
  const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
2363
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, 
2364
  };
2365
2366
  // DQuad_with_dsub_2_in_DPR_8 Bit set.
2367
  const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
2368
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
2369
  };
2370
2371
  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2372
  const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2373
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, 
2374
  };
2375
2376
  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2377
  const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2378
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
2379
  };
2380
2381
  // DQuad_with_dsub_3_in_DPR_8 Register Class...
2382
  const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
2383
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, 
2384
  };
2385
2386
  // DQuad_with_dsub_3_in_DPR_8 Bit set.
2387
  const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
2388
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
2389
  };
2390
2391
  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2392
  const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2393
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, 
2394
  };
2395
2396
  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2397
  const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2398
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
2399
  };
2400
2401
  // DQuad_with_qsub_0_in_QPR_8 Register Class...
2402
  const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
2403
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 
2404
  };
2405
2406
  // DQuad_with_qsub_0_in_QPR_8 Bit set.
2407
  const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
2408
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
2409
  };
2410
2411
  // DQuad_with_qsub_1_in_QPR_8 Register Class...
2412
  const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
2413
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, 
2414
  };
2415
2416
  // DQuad_with_qsub_1_in_QPR_8 Bit set.
2417
  const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
2418
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 
2419
  };
2420
2421
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
2422
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2423
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, 
2424
  };
2425
2426
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
2427
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
2428
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
2429
  };
2430
2431
  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2432
  const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2433
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, 
2434
  };
2435
2436
  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2437
  const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2438
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
2439
  };
2440
2441
  // QQQQPR Register Class...
2442
  const MCPhysReg QQQQPR[] = {
2443
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, 
2444
  };
2445
2446
  // QQQQPR Bit set.
2447
  const uint8_t QQQQPRBits[] = {
2448
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 
2449
  };
2450
2451
  // QQQQPR_with_ssub_0 Register Class...
2452
  const MCPhysReg QQQQPR_with_ssub_0[] = {
2453
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, 
2454
  };
2455
2456
  // QQQQPR_with_ssub_0 Bit set.
2457
  const uint8_t QQQQPR_with_ssub_0Bits[] = {
2458
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
2459
  };
2460
2461
  // QQQQPR_with_ssub_4 Register Class...
2462
  const MCPhysReg QQQQPR_with_ssub_4[] = {
2463
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, 
2464
  };
2465
2466
  // QQQQPR_with_ssub_4 Bit set.
2467
  const uint8_t QQQQPR_with_ssub_4Bits[] = {
2468
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
2469
  };
2470
2471
  // QQQQPR_with_ssub_8 Register Class...
2472
  const MCPhysReg QQQQPR_with_ssub_8[] = {
2473
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, 
2474
  };
2475
2476
  // QQQQPR_with_ssub_8 Bit set.
2477
  const uint8_t QQQQPR_with_ssub_8Bits[] = {
2478
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 
2479
  };
2480
2481
  // QQQQPR_with_ssub_12 Register Class...
2482
  const MCPhysReg QQQQPR_with_ssub_12[] = {
2483
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, 
2484
  };
2485
2486
  // QQQQPR_with_ssub_12 Bit set.
2487
  const uint8_t QQQQPR_with_ssub_12Bits[] = {
2488
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 
2489
  };
2490
2491
  // QQQQPR_with_dsub_0_in_DPR_8 Register Class...
2492
  const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = {
2493
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, 
2494
  };
2495
2496
  // QQQQPR_with_dsub_0_in_DPR_8 Bit set.
2497
  const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = {
2498
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
2499
  };
2500
2501
  // QQQQPR_with_dsub_2_in_DPR_8 Register Class...
2502
  const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = {
2503
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 
2504
  };
2505
2506
  // QQQQPR_with_dsub_2_in_DPR_8 Bit set.
2507
  const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = {
2508
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
2509
  };
2510
2511
  // QQQQPR_with_dsub_4_in_DPR_8 Register Class...
2512
  const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = {
2513
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, 
2514
  };
2515
2516
  // QQQQPR_with_dsub_4_in_DPR_8 Bit set.
2517
  const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = {
2518
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
2519
  };
2520
2521
  // QQQQPR_with_dsub_6_in_DPR_8 Register Class...
2522
  const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = {
2523
    ARM::Q0_Q1_Q2_Q3, 
2524
  };
2525
2526
  // QQQQPR_with_dsub_6_in_DPR_8 Bit set.
2527
  const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = {
2528
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
2529
  };
2530
2531
} // end anonymous namespace
2532
2533
extern const char ARMRegClassStrings[] = {
2534
  /* 0 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2535
  /* 19 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2536
  /* 40 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2537
  /* 63 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2538
  /* 84 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2539
  /* 102 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2540
  /* 122 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2541
  /* 140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '1', '2', 0,
2542
  /* 160 */ 'D', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2543
  /* 169 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2544
  /* 199 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2545
  /* 231 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2546
  /* 261 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2547
  /* 312 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2548
  /* 365 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2549
  /* 383 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2550
  /* 403 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2551
  /* 421 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2552
  /* 440 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2553
  /* 461 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2554
  /* 484 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2555
  /* 505 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2556
  /* 523 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2557
  /* 543 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', 0,
2558
  /* 561 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2559
  /* 589 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2560
  /* 619 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2561
  /* 651 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2562
  /* 681 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2563
  /* 708 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2564
  /* 737 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2565
  /* 764 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2566
  /* 791 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2567
  /* 820 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2568
  /* 847 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2569
  /* 875 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2570
  /* 905 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2571
  /* 937 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2572
  /* 967 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2573
  /* 994 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2574
  /* 1023 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2575
  /* 1050 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2576
  /* 1078 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2577
  /* 1108 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2578
  /* 1140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '6', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2579
  /* 1168 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2580
  /* 1195 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2581
  /* 1224 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2582
  /* 1251 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2583
  /* 1299 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2584
  /* 1349 */ 'S', 'P', 'R', '_', '8', 0,
2585
  /* 1355 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2586
  /* 1374 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2587
  /* 1395 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2588
  /* 1418 */ 'C', 'C', 'R', 0,
2589
  /* 1422 */ 'D', 'P', 'R', 0,
2590
  /* 1426 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
2591
  /* 1441 */ 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
2592
  /* 1456 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
2593
  /* 1485 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
2594
  /* 1514 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', '_', 'a', 'n', 'd', '_', 'h', 'G', 'P', 'R', 0,
2595
  /* 1531 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', 0,
2596
  /* 1559 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 'r', 'G', 'P', 'R', 0,
2597
  /* 1596 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'r', 'G', 'P', 'R', 0,
2598
  /* 1624 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'G', 'P', 'R', 0,
2599
  /* 1652 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', 0,
2600
  /* 1659 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2601
  /* 1710 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2602
  /* 1770 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2603
  /* 1838 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2604
  /* 1906 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2605
  /* 1983 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2606
  /* 2060 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2607
  /* 2132 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2608
  /* 2213 */ 'S', 'P', 'R', 0,
2609
  /* 2217 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 0,
2610
  /* 2229 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', 0,
2611
  /* 2238 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', 0,
2612
  /* 2249 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', 0,
2613
  /* 2258 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'w', 'i', 't', 'h', 'p', 'c', 0,
2614
  /* 2278 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', 0,
2615
  /* 2286 */ 'D', 'Q', 'u', 'a', 'd', 0,
2616
  /* 2292 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 0,
2617
  /* 2300 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'G', 'P', 'R', 's', 'p', 0,
2618
  /* 2329 */ 'D', 'P', 'a', 'i', 'r', 0,
2619
  /* 2335 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 0,
2620
};
2621
2622
extern const MCRegisterClass ARMMCRegisterClasses[] = {
2623
  { SPR, SPRBits, 2213, 32, sizeof(SPRBits), ARM::SPRRegClassID, 4, 1, true },
2624
  { GPR, GPRBits, 1437, 16, sizeof(GPRBits), ARM::GPRRegClassID, 4, 1, true },
2625
  { GPRwithAPSR, GPRwithAPSRBits, 2217, 16, sizeof(GPRwithAPSRBits), ARM::GPRwithAPSRRegClassID, 4, 1, true },
2626
  { SPR_8, SPR_8Bits, 1349, 16, sizeof(SPR_8Bits), ARM::SPR_8RegClassID, 4, 1, true },
2627
  { GPRnopc, GPRnopcBits, 2278, 15, sizeof(GPRnopcBits), ARM::GPRnopcRegClassID, 4, 1, true },
2628
  { rGPR, rGPRBits, 1591, 14, sizeof(rGPRBits), ARM::rGPRRegClassID, 4, 1, true },
2629
  { tGPRwithpc, tGPRwithpcBits, 2267, 9, sizeof(tGPRwithpcBits), ARM::tGPRwithpcRegClassID, 4, 1, true },
2630
  { hGPR, hGPRBits, 1526, 8, sizeof(hGPRBits), ARM::hGPRRegClassID, 4, 1, true },
2631
  { tGPR, tGPRBits, 1647, 8, sizeof(tGPRBits), ARM::tGPRRegClassID, 4, 1, true },
2632
  { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 1514, 7, sizeof(GPRnopc_and_hGPRBits), ARM::GPRnopc_and_hGPRRegClassID, 4, 1, true },
2633
  { hGPR_and_rGPR, hGPR_and_rGPRBits, 1582, 6, sizeof(hGPR_and_rGPRBits), ARM::hGPR_and_rGPRRegClassID, 4, 1, true },
2634
  { tcGPR, tcGPRBits, 1435, 5, sizeof(tcGPRBits), ARM::tcGPRRegClassID, 4, 1, true },
2635
  { tGPR_and_tcGPR, tGPR_and_tcGPRBits, 1441, 4, sizeof(tGPR_and_tcGPRBits), ARM::tGPR_and_tcGPRRegClassID, 4, 1, true },
2636
  { CCR, CCRBits, 1418, 1, sizeof(CCRBits), ARM::CCRRegClassID, 4, -1, false },
2637
  { GPRsp, GPRspBits, 2323, 1, sizeof(GPRspBits), ARM::GPRspRegClassID, 4, 1, true },
2638
  { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, 2258, 1, sizeof(hGPR_and_tGPRwithpcBits), ARM::hGPR_and_tGPRwithpcRegClassID, 4, 1, true },
2639
  { hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1426, 1, sizeof(hGPR_and_tcGPRBits), ARM::hGPR_and_tcGPRRegClassID, 4, 1, true },
2640
  { DPR, DPRBits, 1422, 32, sizeof(DPRBits), ARM::DPRRegClassID, 8, 1, true },
2641
  { DPR_VFP2, DPR_VFP2Bits, 160, 16, sizeof(DPR_VFP2Bits), ARM::DPR_VFP2RegClassID, 8, 1, true },
2642
  { DPR_8, DPR_8Bits, 583, 8, sizeof(DPR_8Bits), ARM::DPR_8RegClassID, 8, 1, true },
2643
  { GPRPair, GPRPairBits, 2335, 7, sizeof(GPRPairBits), ARM::GPRPairRegClassID, 8, 1, true },
2644
  { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, 1596, 6, sizeof(GPRPair_with_gsub_1_in_rGPRBits), ARM::GPRPair_with_gsub_1_in_rGPRRegClassID, 8, 1, true },
2645
  { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 1624, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, 8, 1, true },
2646
  { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 1531, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, 8, 1, true },
2647
  { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 1456, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID, 8, 1, true },
2648
  { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, 1559, 2, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits), ARM::GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID, 8, 1, true },
2649
  { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 1485, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM::GPRPair_with_gsub_1_in_tcGPRRegClassID, 8, 1, true },
2650
  { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 2300, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM::GPRPair_with_gsub_1_in_GPRspRegClassID, 8, 1, true },
2651
  { DPairSpc, DPairSpcBits, 2249, 30, sizeof(DPairSpcBits), ARM::DPairSpcRegClassID, 16, 1, true },
2652
  { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 63, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM::DPairSpc_with_ssub_0RegClassID, 16, 1, true },
2653
  { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, 484, 14, sizeof(DPairSpc_with_ssub_4Bits), ARM::DPairSpc_with_ssub_4RegClassID, 16, 1, true },
2654
  { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 651, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID, 16, 1, true },
2655
  { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 937, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID, 16, 1, true },
2656
  { DPair, DPairBits, 2329, 31, sizeof(DPairBits), ARM::DPairRegClassID, 16, 1, true },
2657
  { DPair_with_ssub_0, DPair_with_ssub_0Bits, 122, 16, sizeof(DPair_with_ssub_0Bits), ARM::DPair_with_ssub_0RegClassID, 16, 1, true },
2658
  { QPR, QPRBits, 1655, 16, sizeof(QPRBits), ARM::QPRRegClassID, 16, 1, true },
2659
  { DPair_with_ssub_2, DPair_with_ssub_2Bits, 403, 15, sizeof(DPair_with_ssub_2Bits), ARM::DPair_with_ssub_2RegClassID, 16, 1, true },
2660
  { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 737, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM::DPair_with_dsub_0_in_DPR_8RegClassID, 16, 1, true },
2661
  { QPR_VFP2, QPR_VFP2Bits, 190, 8, sizeof(QPR_VFP2Bits), ARM::QPR_VFP2RegClassID, 16, 1, true },
2662
  { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 820, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM::DPair_with_dsub_1_in_DPR_8RegClassID, 16, 1, true },
2663
  { QPR_8, QPR_8Bits, 1189, 4, sizeof(QPR_8Bits), ARM::QPR_8RegClassID, 16, 1, true },
2664
  { DTriple, DTripleBits, 2292, 30, sizeof(DTripleBits), ARM::DTripleRegClassID, 24, 1, true },
2665
  { DTripleSpc, DTripleSpcBits, 2238, 28, sizeof(DTripleSpcBits), ARM::DTripleSpcRegClassID, 24, 1, true },
2666
  { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 40, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM::DTripleSpc_with_ssub_0RegClassID, 24, 1, true },
2667
  { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 102, 16, sizeof(DTriple_with_ssub_0Bits), ARM::DTriple_with_ssub_0RegClassID, 24, 1, true },
2668
  { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 1683, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_qsub_0_in_QPRRegClassID, 24, 1, true },
2669
  { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 383, 15, sizeof(DTriple_with_ssub_2Bits), ARM::DTriple_with_ssub_2RegClassID, 24, 1, true },
2670
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2084, 15, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 24, 1, true },
2671
  { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, 461, 14, sizeof(DTripleSpc_with_ssub_4Bits), ARM::DTripleSpc_with_ssub_4RegClassID, 24, 1, true },
2672
  { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, 523, 14, sizeof(DTriple_with_ssub_4Bits), ARM::DTriple_with_ssub_4RegClassID, 24, 1, true },
2673
  { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, 1395, 12, sizeof(DTripleSpc_with_ssub_8Bits), ARM::DTripleSpc_with_ssub_8RegClassID, 24, 1, true },
2674
  { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 619, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 24, 1, true },
2675
  { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 708, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, 24, 1, true },
2676
  { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, 199, 8, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits), ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClassID, 24, 1, true },
2677
  { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2060, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 24, 1, true },
2678
  { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 791, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, 24, 1, true },
2679
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 312, 7, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 24, 1, true },
2680
  { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits, 1659, 7, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 1, true },
2681
  { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 905, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 24, 1, true },
2682
  { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 994, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, 24, 1, true },
2683
  { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 1108, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 24, 1, true },
2684
  { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2132, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 24, 1, true },
2685
  { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 1195, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM::DTriple_with_qsub_0_in_QPR_8RegClassID, 24, 1, true },
2686
  { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, 1710, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 1, true },
2687
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1299, 3, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 24, 1, true },
2688
  { DQuadSpc, DQuadSpcBits, 2229, 28, sizeof(DQuadSpcBits), ARM::DQuadSpcRegClassID, 32, 1, true },
2689
  { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 19, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM::DQuadSpc_with_ssub_0RegClassID, 32, 1, true },
2690
  { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, 440, 14, sizeof(DQuadSpc_with_ssub_4Bits), ARM::DQuadSpc_with_ssub_4RegClassID, 32, 1, true },
2691
  { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, 1374, 12, sizeof(DQuadSpc_with_ssub_8Bits), ARM::DQuadSpc_with_ssub_8RegClassID, 32, 1, true },
2692
  { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 589, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 32, 1, true },
2693
  { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 875, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 32, 1, true },
2694
  { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 1078, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 32, 1, true },
2695
  { DQuad, DQuadBits, 2286, 29, sizeof(DQuadBits), ARM::DQuadRegClassID, 32, 1, true },
2696
  { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 84, 16, sizeof(DQuad_with_ssub_0Bits), ARM::DQuad_with_ssub_0RegClassID, 32, 1, true },
2697
  { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 365, 15, sizeof(DQuad_with_ssub_2Bits), ARM::DQuad_with_ssub_2RegClassID, 32, 1, true },
2698
  { QQPR, QQPRBits, 1654, 15, sizeof(QQPRBits), ARM::QQPRRegClassID, 32, 1, true },
2699
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1792, 14, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
2700
  { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, 505, 14, sizeof(DQuad_with_ssub_4Bits), ARM::DQuad_with_ssub_4RegClassID, 32, 1, true },
2701
  { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, 543, 13, sizeof(DQuad_with_ssub_6Bits), ARM::DQuad_with_ssub_6RegClassID, 32, 1, true },
2702
  { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 681, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, 32, 1, true },
2703
  { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, 169, 8, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClassID, 32, 1, true },
2704
  { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1770, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
2705
  { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 764, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, 32, 1, true },
2706
  { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, 231, 7, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID, 32, 1, true },
2707
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 261, 7, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 32, 1, true },
2708
  { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 967, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, 32, 1, true },
2709
  { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1838, 6, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
2710
  { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 1023, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, 32, 1, true },
2711
  { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1906, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
2712
  { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 1168, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM::DQuad_with_qsub_0_in_QPR_8RegClassID, 32, 1, true },
2713
  { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 1224, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM::DQuad_with_qsub_1_in_QPR_8RegClassID, 32, 1, true },
2714
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1251, 3, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 32, 1, true },
2715
  { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1983, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
2716
  { QQQQPR, QQQQPRBits, 1652, 13, sizeof(QQQQPRBits), ARM::QQQQPRRegClassID, 64, 1, true },
2717
  { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 0, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM::QQQQPR_with_ssub_0RegClassID, 64, 1, true },
2718
  { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, 421, 7, sizeof(QQQQPR_with_ssub_4Bits), ARM::QQQQPR_with_ssub_4RegClassID, 64, 1, true },
2719
  { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, 1355, 6, sizeof(QQQQPR_with_ssub_8Bits), ARM::QQQQPR_with_ssub_8RegClassID, 64, 1, true },
2720
  { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, 140, 5, sizeof(QQQQPR_with_ssub_12Bits), ARM::QQQQPR_with_ssub_12RegClassID, 64, 1, true },
2721
  { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 561, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID, 64, 1, true },
2722
  { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 847, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID, 64, 1, true },
2723
  { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 1050, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID, 64, 1, true },
2724
  { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 1140, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID, 64, 1, true },
2725
};
2726
2727
// ARM Dwarf<->LLVM register mappings.
2728
extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
2729
  { 0U, ARM::R0 },
2730
  { 1U, ARM::R1 },
2731
  { 2U, ARM::R2 },
2732
  { 3U, ARM::R3 },
2733
  { 4U, ARM::R4 },
2734
  { 5U, ARM::R5 },
2735
  { 6U, ARM::R6 },
2736
  { 7U, ARM::R7 },
2737
  { 8U, ARM::R8 },
2738
  { 9U, ARM::R9 },
2739
  { 10U, ARM::R10 },
2740
  { 11U, ARM::R11 },
2741
  { 12U, ARM::R12 },
2742
  { 13U, ARM::SP },
2743
  { 14U, ARM::LR },
2744
  { 15U, ARM::PC },
2745
  { 256U, ARM::D0 },
2746
  { 257U, ARM::D1 },
2747
  { 258U, ARM::D2 },
2748
  { 259U, ARM::D3 },
2749
  { 260U, ARM::D4 },
2750
  { 261U, ARM::D5 },
2751
  { 262U, ARM::D6 },
2752
  { 263U, ARM::D7 },
2753
  { 264U, ARM::D8 },
2754
  { 265U, ARM::D9 },
2755
  { 266U, ARM::D10 },
2756
  { 267U, ARM::D11 },
2757
  { 268U, ARM::D12 },
2758
  { 269U, ARM::D13 },
2759
  { 270U, ARM::D14 },
2760
  { 271U, ARM::D15 },
2761
  { 272U, ARM::D16 },
2762
  { 273U, ARM::D17 },
2763
  { 274U, ARM::D18 },
2764
  { 275U, ARM::D19 },
2765
  { 276U, ARM::D20 },
2766
  { 277U, ARM::D21 },
2767
  { 278U, ARM::D22 },
2768
  { 279U, ARM::D23 },
2769
  { 280U, ARM::D24 },
2770
  { 281U, ARM::D25 },
2771
  { 282U, ARM::D26 },
2772
  { 283U, ARM::D27 },
2773
  { 284U, ARM::D28 },
2774
  { 285U, ARM::D29 },
2775
  { 286U, ARM::D30 },
2776
  { 287U, ARM::D31 },
2777
};
2778
extern const unsigned ARMDwarfFlavour0Dwarf2LSize = array_lengthof(ARMDwarfFlavour0Dwarf2L);
2779
2780
extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
2781
  { 0U, ARM::R0 },
2782
  { 1U, ARM::R1 },
2783
  { 2U, ARM::R2 },
2784
  { 3U, ARM::R3 },
2785
  { 4U, ARM::R4 },
2786
  { 5U, ARM::R5 },
2787
  { 6U, ARM::R6 },
2788
  { 7U, ARM::R7 },
2789
  { 8U, ARM::R8 },
2790
  { 9U, ARM::R9 },
2791
  { 10U, ARM::R10 },
2792
  { 11U, ARM::R11 },
2793
  { 12U, ARM::R12 },
2794
  { 13U, ARM::SP },
2795
  { 14U, ARM::LR },
2796
  { 15U, ARM::PC },
2797
  { 256U, ARM::D0 },
2798
  { 257U, ARM::D1 },
2799
  { 258U, ARM::D2 },
2800
  { 259U, ARM::D3 },
2801
  { 260U, ARM::D4 },
2802
  { 261U, ARM::D5 },
2803
  { 262U, ARM::D6 },
2804
  { 263U, ARM::D7 },
2805
  { 264U, ARM::D8 },
2806
  { 265U, ARM::D9 },
2807
  { 266U, ARM::D10 },
2808
  { 267U, ARM::D11 },
2809
  { 268U, ARM::D12 },
2810
  { 269U, ARM::D13 },
2811
  { 270U, ARM::D14 },
2812
  { 271U, ARM::D15 },
2813
  { 272U, ARM::D16 },
2814
  { 273U, ARM::D17 },
2815
  { 274U, ARM::D18 },
2816
  { 275U, ARM::D19 },
2817
  { 276U, ARM::D20 },
2818
  { 277U, ARM::D21 },
2819
  { 278U, ARM::D22 },
2820
  { 279U, ARM::D23 },
2821
  { 280U, ARM::D24 },
2822
  { 281U, ARM::D25 },
2823
  { 282U, ARM::D26 },
2824
  { 283U, ARM::D27 },
2825
  { 284U, ARM::D28 },
2826
  { 285U, ARM::D29 },
2827
  { 286U, ARM::D30 },
2828
  { 287U, ARM::D31 },
2829
};
2830
extern const unsigned ARMEHFlavour0Dwarf2LSize = array_lengthof(ARMEHFlavour0Dwarf2L);
2831
2832
extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
2833
  { ARM::LR, 14U },
2834
  { ARM::PC, 15U },
2835
  { ARM::SP, 13U },
2836
  { ARM::D0, 256U },
2837
  { ARM::D1, 257U },
2838
  { ARM::D2, 258U },
2839
  { ARM::D3, 259U },
2840
  { ARM::D4, 260U },
2841
  { ARM::D5, 261U },
2842
  { ARM::D6, 262U },
2843
  { ARM::D7, 263U },
2844
  { ARM::D8, 264U },
2845
  { ARM::D9, 265U },
2846
  { ARM::D10, 266U },
2847
  { ARM::D11, 267U },
2848
  { ARM::D12, 268U },
2849
  { ARM::D13, 269U },
2850
  { ARM::D14, 270U },
2851
  { ARM::D15, 271U },
2852
  { ARM::D16, 272U },
2853
  { ARM::D17, 273U },
2854
  { ARM::D18, 274U },
2855
  { ARM::D19, 275U },
2856
  { ARM::D20, 276U },
2857
  { ARM::D21, 277U },
2858
  { ARM::D22, 278U },
2859
  { ARM::D23, 279U },
2860
  { ARM::D24, 280U },
2861
  { ARM::D25, 281U },
2862
  { ARM::D26, 282U },
2863
  { ARM::D27, 283U },
2864
  { ARM::D28, 284U },
2865
  { ARM::D29, 285U },
2866
  { ARM::D30, 286U },
2867
  { ARM::D31, 287U },
2868
  { ARM::R0, 0U },
2869
  { ARM::R1, 1U },
2870
  { ARM::R2, 2U },
2871
  { ARM::R3, 3U },
2872
  { ARM::R4, 4U },
2873
  { ARM::R5, 5U },
2874
  { ARM::R6, 6U },
2875
  { ARM::R7, 7U },
2876
  { ARM::R8, 8U },
2877
  { ARM::R9, 9U },
2878
  { ARM::R10, 10U },
2879
  { ARM::R11, 11U },
2880
  { ARM::R12, 12U },
2881
};
2882
extern const unsigned ARMDwarfFlavour0L2DwarfSize = array_lengthof(ARMDwarfFlavour0L2Dwarf);
2883
2884
extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
2885
  { ARM::LR, 14U },
2886
  { ARM::PC, 15U },
2887
  { ARM::SP, 13U },
2888
  { ARM::D0, 256U },
2889
  { ARM::D1, 257U },
2890
  { ARM::D2, 258U },
2891
  { ARM::D3, 259U },
2892
  { ARM::D4, 260U },
2893
  { ARM::D5, 261U },
2894
  { ARM::D6, 262U },
2895
  { ARM::D7, 263U },
2896
  { ARM::D8, 264U },
2897
  { ARM::D9, 265U },
2898
  { ARM::D10, 266U },
2899
  { ARM::D11, 267U },
2900
  { ARM::D12, 268U },
2901
  { ARM::D13, 269U },
2902
  { ARM::D14, 270U },
2903
  { ARM::D15, 271U },
2904
  { ARM::D16, 272U },
2905
  { ARM::D17, 273U },
2906
  { ARM::D18, 274U },
2907
  { ARM::D19, 275U },
2908
  { ARM::D20, 276U },
2909
  { ARM::D21, 277U },
2910
  { ARM::D22, 278U },
2911
  { ARM::D23, 279U },
2912
  { ARM::D24, 280U },
2913
  { ARM::D25, 281U },
2914
  { ARM::D26, 282U },
2915
  { ARM::D27, 283U },
2916
  { ARM::D28, 284U },
2917
  { ARM::D29, 285U },
2918
  { ARM::D30, 286U },
2919
  { ARM::D31, 287U },
2920
  { ARM::R0, 0U },
2921
  { ARM::R1, 1U },
2922
  { ARM::R2, 2U },
2923
  { ARM::R3, 3U },
2924
  { ARM::R4, 4U },
2925
  { ARM::R5, 5U },
2926
  { ARM::R6, 6U },
2927
  { ARM::R7, 7U },
2928
  { ARM::R8, 8U },
2929
  { ARM::R9, 9U },
2930
  { ARM::R10, 10U },
2931
  { ARM::R11, 11U },
2932
  { ARM::R12, 12U },
2933
};
2934
extern const unsigned ARMEHFlavour0L2DwarfSize = array_lengthof(ARMEHFlavour0L2Dwarf);
2935
2936
extern const uint16_t ARMRegEncodingTable[] = {
2937
  0,
2938
  1,
2939
  15,
2940
  0,
2941
  8,
2942
  9,
2943
  3,
2944
  3,
2945
  0,
2946
  4,
2947
  14,
2948
  15,
2949
  13,
2950
  2,
2951
  0,
2952
  1,
2953
  2,
2954
  3,
2955
  4,
2956
  5,
2957
  6,
2958
  7,
2959
  8,
2960
  9,
2961
  10,
2962
  11,
2963
  12,
2964
  13,
2965
  14,
2966
  15,
2967
  16,
2968
  17,
2969
  18,
2970
  19,
2971
  20,
2972
  21,
2973
  22,
2974
  23,
2975
  24,
2976
  25,
2977
  26,
2978
  27,
2979
  28,
2980
  29,
2981
  30,
2982
  31,
2983
  10,
2984
  7,
2985
  6,
2986
  5,
2987
  0,
2988
  1,
2989
  2,
2990
  3,
2991
  4,
2992
  5,
2993
  6,
2994
  7,
2995
  8,
2996
  9,
2997
  10,
2998
  11,
2999
  12,
3000
  13,
3001
  14,
3002
  15,
3003
  0,
3004
  1,
3005
  2,
3006
  3,
3007
  4,
3008
  5,
3009
  6,
3010
  7,
3011
  8,
3012
  9,
3013
  10,
3014
  11,
3015
  12,
3016
  0,
3017
  1,
3018
  2,
3019
  3,
3020
  4,
3021
  5,
3022
  6,
3023
  7,
3024
  8,
3025
  9,
3026
  10,
3027
  11,
3028
  12,
3029
  13,
3030
  14,
3031
  15,
3032
  16,
3033
  17,
3034
  18,
3035
  19,
3036
  20,
3037
  21,
3038
  22,
3039
  23,
3040
  24,
3041
  25,
3042
  26,
3043
  27,
3044
  28,
3045
  29,
3046
  30,
3047
  31,
3048
  0,
3049
  1,
3050
  2,
3051
  3,
3052
  4,
3053
  5,
3054
  6,
3055
  7,
3056
  8,
3057
  9,
3058
  10,
3059
  11,
3060
  12,
3061
  13,
3062
  14,
3063
  15,
3064
  16,
3065
  17,
3066
  18,
3067
  19,
3068
  20,
3069
  21,
3070
  22,
3071
  23,
3072
  24,
3073
  25,
3074
  26,
3075
  27,
3076
  28,
3077
  29,
3078
  0,
3079
  1,
3080
  2,
3081
  3,
3082
  4,
3083
  5,
3084
  6,
3085
  7,
3086
  8,
3087
  9,
3088
  10,
3089
  11,
3090
  12,
3091
  13,
3092
  14,
3093
  0,
3094
  1,
3095
  2,
3096
  3,
3097
  4,
3098
  5,
3099
  6,
3100
  7,
3101
  8,
3102
  9,
3103
  10,
3104
  11,
3105
  12,
3106
  12,
3107
  0,
3108
  2,
3109
  4,
3110
  6,
3111
  8,
3112
  10,
3113
  0,
3114
  1,
3115
  2,
3116
  3,
3117
  4,
3118
  5,
3119
  6,
3120
  7,
3121
  8,
3122
  9,
3123
  10,
3124
  11,
3125
  12,
3126
  13,
3127
  14,
3128
  15,
3129
  16,
3130
  17,
3131
  18,
3132
  19,
3133
  20,
3134
  21,
3135
  22,
3136
  23,
3137
  24,
3138
  25,
3139
  26,
3140
  27,
3141
  28,
3142
  29,
3143
  0,
3144
  1,
3145
  2,
3146
  3,
3147
  4,
3148
  5,
3149
  6,
3150
  7,
3151
  8,
3152
  9,
3153
  10,
3154
  11,
3155
  12,
3156
  13,
3157
  14,
3158
  15,
3159
  16,
3160
  17,
3161
  18,
3162
  19,
3163
  20,
3164
  21,
3165
  22,
3166
  23,
3167
  24,
3168
  25,
3169
  26,
3170
  27,
3171
  0,
3172
  1,
3173
  2,
3174
  3,
3175
  4,
3176
  5,
3177
  6,
3178
  7,
3179
  8,
3180
  9,
3181
  10,
3182
  11,
3183
  12,
3184
  13,
3185
  14,
3186
  15,
3187
  16,
3188
  17,
3189
  18,
3190
  19,
3191
  20,
3192
  21,
3193
  22,
3194
  23,
3195
  24,
3196
  25,
3197
  1,
3198
  3,
3199
  5,
3200
  7,
3201
  9,
3202
  11,
3203
  13,
3204
  15,
3205
  17,
3206
  19,
3207
  21,
3208
  23,
3209
  25,
3210
  27,
3211
  29,
3212
  1,
3213
  3,
3214
  5,
3215
  7,
3216
  9,
3217
  11,
3218
  13,
3219
  15,
3220
  17,
3221
  19,
3222
  21,
3223
  23,
3224
  25,
3225
  27,
3226
};
3227
6.90k
static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3228
6.90k
  RI->InitMCRegisterInfo(ARMRegDesc, 289, RA, PC, ARMMCRegisterClasses, 102, ARMRegUnitRoots, 77, ARMRegDiffLists, ARMLaneMaskLists, ARMRegStrings, ARMRegClassStrings, ARMSubRegIdxLists, 57,
3229
6.90k
ARMSubRegIdxRanges, ARMRegEncodingTable);
3230
6.90k
3231
6.90k
  switch (DwarfFlavour) {
3232
0
  default:
3233
0
    llvm_unreachable("Unknown DWARF flavour");
3234
6.90k
  case 0:
3235
6.90k
    RI->mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
3236
6.90k
    break;
3237
6.90k
  }
3238
6.90k
  switch (EHFlavour) {
3239
0
  default:
3240
0
    llvm_unreachable("Unknown DWARF flavour");
3241
6.90k
  case 0:
3242
6.90k
    RI->mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
3243
6.90k
    break;
3244
6.90k
  }
3245
6.90k
  switch (DwarfFlavour) {
3246
0
  default:
3247
0
    llvm_unreachable("Unknown DWARF flavour");
3248
6.90k
  case 0:
3249
6.90k
    RI->mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false);
3250
6.90k
    break;
3251
6.90k
  }
3252
6.90k
  switch (EHFlavour) {
3253
0
  default:
3254
0
    llvm_unreachable("Unknown DWARF flavour");
3255
6.90k
  case 0:
3256
6.90k
    RI->mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true);
3257
6.90k
    break;
3258
6.90k
  }
3259
6.90k
}
3260
3261
} // end namespace llvm
3262
3263
#endif // GET_REGINFO_MC_DESC
3264
3265
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3266
|*                                                                            *|
3267
|* Register Information Header Fragment                                       *|
3268
|*                                                                            *|
3269
|* Automatically generated file, do not edit!                                 *|
3270
|*                                                                            *|
3271
\*===----------------------------------------------------------------------===*/
3272
3273
3274
#ifdef GET_REGINFO_HEADER
3275
#undef GET_REGINFO_HEADER
3276
3277
#include "llvm/Target/TargetRegisterInfo.h"
3278
3279
namespace llvm {
3280
3281
class ARMFrameLowering;
3282
3283
struct ARMGenRegisterInfo : public TargetRegisterInfo {
3284
  explicit ARMGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3285
      unsigned PC = 0, unsigned HwMode = 0);
3286
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3287
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3288
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3289
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3290
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3291
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
3292
  unsigned getNumRegPressureSets() const override;
3293
  const char *getRegPressureSetName(unsigned Idx) const override;
3294
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3295
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3296
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3297
  ArrayRef<const char *> getRegMaskNames() const override;
3298
  ArrayRef<const uint32_t *> getRegMasks() const override;
3299
  /// Devirtualized TargetFrameLowering.
3300
  static const ARMFrameLowering *getFrameLowering(
3301
      const MachineFunction &MF);
3302
};
3303
3304
namespace ARM { // Register classes
3305
  extern const TargetRegisterClass SPRRegClass;
3306
  extern const TargetRegisterClass GPRRegClass;
3307
  extern const TargetRegisterClass GPRwithAPSRRegClass;
3308
  extern const TargetRegisterClass SPR_8RegClass;
3309
  extern const TargetRegisterClass GPRnopcRegClass;
3310
  extern const TargetRegisterClass rGPRRegClass;
3311
  extern const TargetRegisterClass tGPRwithpcRegClass;
3312
  extern const TargetRegisterClass hGPRRegClass;
3313
  extern const TargetRegisterClass tGPRRegClass;
3314
  extern const TargetRegisterClass GPRnopc_and_hGPRRegClass;
3315
  extern const TargetRegisterClass hGPR_and_rGPRRegClass;
3316
  extern const TargetRegisterClass tcGPRRegClass;
3317
  extern const TargetRegisterClass tGPR_and_tcGPRRegClass;
3318
  extern const TargetRegisterClass CCRRegClass;
3319
  extern const TargetRegisterClass GPRspRegClass;
3320
  extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass;
3321
  extern const TargetRegisterClass hGPR_and_tcGPRRegClass;
3322
  extern const TargetRegisterClass DPRRegClass;
3323
  extern const TargetRegisterClass DPR_VFP2RegClass;
3324
  extern const TargetRegisterClass DPR_8RegClass;
3325
  extern const TargetRegisterClass GPRPairRegClass;
3326
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_rGPRRegClass;
3327
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass;
3328
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass;
3329
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass;
3330
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass;
3331
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass;
3332
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass;
3333
  extern const TargetRegisterClass DPairSpcRegClass;
3334
  extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass;
3335
  extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass;
3336
  extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass;
3337
  extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass;
3338
  extern const TargetRegisterClass DPairRegClass;
3339
  extern const TargetRegisterClass DPair_with_ssub_0RegClass;
3340
  extern const TargetRegisterClass QPRRegClass;
3341
  extern const TargetRegisterClass DPair_with_ssub_2RegClass;
3342
  extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass;
3343
  extern const TargetRegisterClass QPR_VFP2RegClass;
3344
  extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass;
3345
  extern const TargetRegisterClass QPR_8RegClass;
3346
  extern const TargetRegisterClass DTripleRegClass;
3347
  extern const TargetRegisterClass DTripleSpcRegClass;
3348
  extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass;
3349
  extern const TargetRegisterClass DTriple_with_ssub_0RegClass;
3350
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass;
3351
  extern const TargetRegisterClass DTriple_with_ssub_2RegClass;
3352
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3353
  extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass;
3354
  extern const TargetRegisterClass DTriple_with_ssub_4RegClass;
3355
  extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass;
3356
  extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass;
3357
  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass;
3358
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_VFP2RegClass;
3359
  extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3360
  extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass;
3361
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
3362
  extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass;
3363
  extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass;
3364
  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass;
3365
  extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass;
3366
  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3367
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass;
3368
  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass;
3369
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
3370
  extern const TargetRegisterClass DQuadSpcRegClass;
3371
  extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass;
3372
  extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass;
3373
  extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass;
3374
  extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass;
3375
  extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass;
3376
  extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass;
3377
  extern const TargetRegisterClass DQuadRegClass;
3378
  extern const TargetRegisterClass DQuad_with_ssub_0RegClass;
3379
  extern const TargetRegisterClass DQuad_with_ssub_2RegClass;
3380
  extern const TargetRegisterClass QQPRRegClass;
3381
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3382
  extern const TargetRegisterClass DQuad_with_ssub_4RegClass;
3383
  extern const TargetRegisterClass DQuad_with_ssub_6RegClass;
3384
  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass;
3385
  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_VFP2RegClass;
3386
  extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3387
  extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass;
3388
  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_VFP2RegClass;
3389
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
3390
  extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass;
3391
  extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3392
  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass;
3393
  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3394
  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass;
3395
  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass;
3396
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
3397
  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3398
  extern const TargetRegisterClass QQQQPRRegClass;
3399
  extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass;
3400
  extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass;
3401
  extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass;
3402
  extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass;
3403
  extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass;
3404
  extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass;
3405
  extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass;
3406
  extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass;
3407
} // end namespace ARM
3408
3409
} // end namespace llvm
3410
3411
#endif // GET_REGINFO_HEADER
3412
3413
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3414
|*                                                                            *|
3415
|* Target Register and Register Classes Information                           *|
3416
|*                                                                            *|
3417
|* Automatically generated file, do not edit!                                 *|
3418
|*                                                                            *|
3419
\*===----------------------------------------------------------------------===*/
3420
3421
3422
#ifdef GET_REGINFO_TARGET_DESC
3423
#undef GET_REGINFO_TARGET_DESC
3424
3425
namespace llvm {
3426
3427
extern const MCRegisterClass ARMMCRegisterClasses[];
3428
3429
static const MVT::SimpleValueType VTLists[] = {
3430
  /* 0 */ MVT::i32, MVT::Other,
3431
  /* 2 */ MVT::f32, MVT::Other,
3432
  /* 4 */ MVT::v2i64, MVT::Other,
3433
  /* 6 */ MVT::v4i64, MVT::Other,
3434
  /* 8 */ MVT::v8i64, MVT::Other,
3435
  /* 10 */ MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::v4f16, MVT::Other,
3436
  /* 18 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
3437
  /* 26 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other,
3438
  /* 33 */ MVT::Untyped, MVT::Other,
3439
};
3440
3441
static const char *const SubRegIndexNameTable[] = { "dsub_0", "dsub_1", "dsub_2", "dsub_3", "dsub_4", "dsub_5", "dsub_6", "dsub_7", "gsub_0", "gsub_1", "qqsub_0", "qqsub_1", "qsub_0", "qsub_1", "qsub_2", "qsub_3", "ssub_0", "ssub_1", "ssub_2", "ssub_3", "ssub_4", "ssub_5", "ssub_6", "ssub_7", "ssub_8", "ssub_9", "ssub_10", "ssub_11", "ssub_12", "ssub_13", "dsub_7_then_ssub_0", "dsub_7_then_ssub_1", "ssub_0_ssub_1_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5", "ssub_2_ssub_3_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_6_ssub_7_dsub_5", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5", "ssub_6_ssub_7_dsub_5_dsub_7", "ssub_6_ssub_7_ssub_8_ssub_9", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "ssub_8_ssub_9_ssub_12_ssub_13", "ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "dsub_5_dsub_7", "dsub_5_ssub_12_ssub_13_dsub_7", "dsub_5_ssub_12_ssub_13", "ssub_4_ssub_5_ssub_6_ssub_7_qsub_2", "" };
3442
3443
3444
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3445
  LaneBitmask::getAll(),
3446
  LaneBitmask(0x0000000C), // dsub_0
3447
  LaneBitmask(0x00000030), // dsub_1
3448
  LaneBitmask(0x000000C0), // dsub_2
3449
  LaneBitmask(0x00000300), // dsub_3
3450
  LaneBitmask(0x00000C00), // dsub_4
3451
  LaneBitmask(0x00003000), // dsub_5
3452
  LaneBitmask(0x0000C000), // dsub_6
3453
  LaneBitmask(0x00030000), // dsub_7
3454
  LaneBitmask(0x00000001), // gsub_0
3455
  LaneBitmask(0x00000002), // gsub_1
3456
  LaneBitmask(0x000003FC), // qqsub_0
3457
  LaneBitmask(0x0003FC00), // qqsub_1
3458
  LaneBitmask(0x0000003C), // qsub_0
3459
  LaneBitmask(0x000003C0), // qsub_1
3460
  LaneBitmask(0x00003C00), // qsub_2
3461
  LaneBitmask(0x0003C000), // qsub_3
3462
  LaneBitmask(0x00000004), // ssub_0
3463
  LaneBitmask(0x00000008), // ssub_1
3464
  LaneBitmask(0x00000010), // ssub_2
3465
  LaneBitmask(0x00000020), // ssub_3
3466
  LaneBitmask(0x00000040), // ssub_4
3467
  LaneBitmask(0x00000080), // ssub_5
3468
  LaneBitmask(0x00000100), // ssub_6
3469
  LaneBitmask(0x00000200), // ssub_7
3470
  LaneBitmask(0x00000400), // ssub_8
3471
  LaneBitmask(0x00000800), // ssub_9
3472
  LaneBitmask(0x00001000), // ssub_10
3473
  LaneBitmask(0x00002000), // ssub_11
3474
  LaneBitmask(0x00004000), // ssub_12
3475
  LaneBitmask(0x00008000), // ssub_13
3476
  LaneBitmask(0x00010000), // dsub_7_then_ssub_0
3477
  LaneBitmask(0x00020000), // dsub_7_then_ssub_1
3478
  LaneBitmask(0x000000CC), // ssub_0_ssub_1_ssub_4_ssub_5
3479
  LaneBitmask(0x000000FC), // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3480
  LaneBitmask(0x00000330), // ssub_2_ssub_3_ssub_6_ssub_7
3481
  LaneBitmask(0x000003F0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3482
  LaneBitmask(0x000000F0), // ssub_2_ssub_3_ssub_4_ssub_5
3483
  LaneBitmask(0x00000CCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
3484
  LaneBitmask(0x0000CCCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3485
  LaneBitmask(0x00003330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
3486
  LaneBitmask(0x00033330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
3487
  LaneBitmask(0x00000FF0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3488
  LaneBitmask(0x00000CC0), // ssub_4_ssub_5_ssub_8_ssub_9
3489
  LaneBitmask(0x00000FC0), // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3490
  LaneBitmask(0x0000CCC0), // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3491
  LaneBitmask(0x00003300), // ssub_6_ssub_7_dsub_5
3492
  LaneBitmask(0x00003F00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
3493
  LaneBitmask(0x00033300), // ssub_6_ssub_7_dsub_5_dsub_7
3494
  LaneBitmask(0x00000F00), // ssub_6_ssub_7_ssub_8_ssub_9
3495
  LaneBitmask(0x0000FF00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3496
  LaneBitmask(0x0000CC00), // ssub_8_ssub_9_ssub_12_ssub_13
3497
  LaneBitmask(0x0000FC00), // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3498
  LaneBitmask(0x00033000), // dsub_5_dsub_7
3499
  LaneBitmask(0x0003F000), // dsub_5_ssub_12_ssub_13_dsub_7
3500
  LaneBitmask(0x0000F000), // dsub_5_ssub_12_ssub_13
3501
  LaneBitmask(0x00003FC0), // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
3502
 };
3503
3504
3505
3506
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3507
  // Mode = 0 (Default)
3508
  { 32, 32, 32, VTLists+2 },    // SPR
3509
  { 32, 32, 32, VTLists+0 },    // GPR
3510
  { 32, 32, 32, VTLists+0 },    // GPRwithAPSR
3511
  { 32, 32, 32, VTLists+2 },    // SPR_8
3512
  { 32, 32, 32, VTLists+0 },    // GPRnopc
3513
  { 32, 32, 32, VTLists+0 },    // rGPR
3514
  { 32, 32, 32, VTLists+0 },    // tGPRwithpc
3515
  { 32, 32, 32, VTLists+0 },    // hGPR
3516
  { 32, 32, 32, VTLists+0 },    // tGPR
3517
  { 32, 32, 32, VTLists+0 },    // GPRnopc_and_hGPR
3518
  { 32, 32, 32, VTLists+0 },    // hGPR_and_rGPR
3519
  { 32, 32, 32, VTLists+0 },    // tcGPR
3520
  { 32, 32, 32, VTLists+0 },    // tGPR_and_tcGPR
3521
  { 32, 32, 32, VTLists+0 },    // CCR
3522
  { 32, 32, 32, VTLists+0 },    // GPRsp
3523
  { 32, 32, 32, VTLists+0 },    // hGPR_and_tGPRwithpc
3524
  { 32, 32, 32, VTLists+0 },    // hGPR_and_tcGPR
3525
  { 64, 64, 64, VTLists+10 },    // DPR
3526
  { 64, 64, 64, VTLists+10 },    // DPR_VFP2
3527
  { 64, 64, 64, VTLists+10 },    // DPR_8
3528
  { 64, 64, 64, VTLists+33 },    // GPRPair
3529
  { 64, 64, 64, VTLists+33 },    // GPRPair_with_gsub_1_in_rGPR
3530
  { 64, 64, 64, VTLists+33 },    // GPRPair_with_gsub_0_in_tGPR
3531
  { 64, 64, 64, VTLists+33 },    // GPRPair_with_gsub_0_in_hGPR
3532
  { 64, 64, 64, VTLists+33 },    // GPRPair_with_gsub_0_in_tcGPR
3533
  { 64, 64, 64, VTLists+33 },    // GPRPair_with_gsub_1_in_hGPR_and_rGPR
3534
  { 64, 64, 64, VTLists+33 },    // GPRPair_with_gsub_1_in_tcGPR
3535
  { 64, 64, 64, VTLists+33 },    // GPRPair_with_gsub_1_in_GPRsp
3536
  { 128, 128, 64, VTLists+4 },    // DPairSpc
3537
  { 128, 128, 64, VTLists+4 },    // DPairSpc_with_ssub_0
3538
  { 128, 128, 64, VTLists+4 },    // DPairSpc_with_ssub_4
3539
  { 128, 128, 64, VTLists+4 },    // DPairSpc_with_dsub_0_in_DPR_8
3540
  { 128, 128, 64, VTLists+4 },    // DPairSpc_with_dsub_2_in_DPR_8
3541
  { 128, 128, 128, VTLists+26 },    // DPair
3542
  { 128, 128, 128, VTLists+26 },    // DPair_with_ssub_0
3543
  { 128, 128, 128, VTLists+18 },    // QPR
3544
  { 128, 128, 128, VTLists+26 },    // DPair_with_ssub_2
3545
  { 128, 128, 128, VTLists+26 },    // DPair_with_dsub_0_in_DPR_8
3546
  { 128, 128, 128, VTLists+26 },    // QPR_VFP2
3547
  { 128, 128, 128, VTLists+26 },    // DPair_with_dsub_1_in_DPR_8
3548
  { 128, 128, 128, VTLists+26 },    // QPR_8
3549
  { 192, 192, 64, VTLists+33 },    // DTriple
3550
  { 192, 192, 64, VTLists+33 },    // DTripleSpc
3551
  { 192, 192, 64, VTLists+33 },    // DTripleSpc_with_ssub_0
3552
  { 192, 192, 64, VTLists+33 },    // DTriple_with_ssub_0
3553
  { 192, 192, 64, VTLists+33 },    // DTriple_with_qsub_0_in_QPR
3554
  { 192, 192, 64, VTLists+33 },    // DTriple_with_ssub_2
3555
  { 192, 192, 64, VTLists+33 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3556
  { 192, 192, 64, VTLists+33 },    // DTripleSpc_with_ssub_4
3557
  { 192, 192, 64, VTLists+33 },    // DTriple_with_ssub_4
3558
  { 192, 192, 64, VTLists+33 },    // DTripleSpc_with_ssub_8
3559
  { 192, 192, 64, VTLists+33 },    // DTripleSpc_with_dsub_0_in_DPR_8
3560
  { 192, 192, 64, VTLists+33 },    // DTriple_with_dsub_0_in_DPR_8
3561
  { 192, 192, 64, VTLists+33 },    // DTriple_with_qsub_0_in_QPR_VFP2
3562
  { 192, 192, 64, VTLists+33 },    // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3563
  { 192, 192, 64, VTLists+33 },    // DTriple_with_dsub_1_in_DPR_8
3564
  { 192, 192, 64, VTLists+33 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
3565
  { 192, 192, 64, VTLists+33 },    // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
3566
  { 192, 192, 64, VTLists+33 },    // DTripleSpc_with_dsub_2_in_DPR_8
3567
  { 192, 192, 64, VTLists+33 },    // DTriple_with_dsub_2_in_DPR_8
3568
  { 192, 192, 64, VTLists+33 },    // DTripleSpc_with_dsub_4_in_DPR_8
3569
  { 192, 192, 64, VTLists+33 },    // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3570
  { 192, 192, 64, VTLists+33 },    // DTriple_with_qsub_0_in_QPR_8
3571
  { 192, 192, 64, VTLists+33 },    // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
3572
  { 192, 192, 64, VTLists+33 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
3573
  { 256, 256, 64, VTLists+6 },    // DQuadSpc
3574
  { 256, 256, 64, VTLists+6 },    // DQuadSpc_with_ssub_0
3575
  { 256, 256, 64, VTLists+6 },    // DQuadSpc_with_ssub_4
3576
  { 256, 256, 64, VTLists+6 },    // DQuadSpc_with_ssub_8
3577
  { 256, 256, 64, VTLists+6 },    // DQuadSpc_with_dsub_0_in_DPR_8
3578
  { 256, 256, 64, VTLists+6 },    // DQuadSpc_with_dsub_2_in_DPR_8
3579
  { 256, 256, 64, VTLists+6 },    // DQuadSpc_with_dsub_4_in_DPR_8
3580
  { 256, 256, 256, VTLists+6 },    // DQuad
3581
  { 256, 256, 256, VTLists+6 },    // DQuad_with_ssub_0
3582
  { 256, 256, 256, VTLists+6 },    // DQuad_with_ssub_2
3583
  { 256, 256, 256, VTLists+6 },    // QQPR
3584
  { 256, 256, 256, VTLists+6 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3585
  { 256, 256, 256, VTLists+6 },    // DQuad_with_ssub_4
3586
  { 256, 256, 256, VTLists+6 },    // DQuad_with_ssub_6
3587
  { 256, 256, 256, VTLists+6 },    // DQuad_with_dsub_0_in_DPR_8
3588
  { 256, 256, 256, VTLists+6 },    // DQuad_with_qsub_0_in_QPR_VFP2
3589
  { 256, 256, 256, VTLists+6 },    // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3590
  { 256, 256, 256, VTLists+6 },    // DQuad_with_dsub_1_in_DPR_8
3591
  { 256, 256, 256, VTLists+6 },    // DQuad_with_qsub_1_in_QPR_VFP2
3592
  { 256, 256, 256, VTLists+6 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
3593
  { 256, 256, 256, VTLists+6 },    // DQuad_with_dsub_2_in_DPR_8
3594
  { 256, 256, 256, VTLists+6 },    // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3595
  { 256, 256, 256, VTLists+6 },    // DQuad_with_dsub_3_in_DPR_8
3596
  { 256, 256, 256, VTLists+6 },    // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3597
  { 256, 256, 256, VTLists+6 },    // DQuad_with_qsub_0_in_QPR_8
3598
  { 256, 256, 256, VTLists+6 },    // DQuad_with_qsub_1_in_QPR_8
3599
  { 256, 256, 256, VTLists+6 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
3600
  { 256, 256, 256, VTLists+6 },    // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3601
  { 512, 512, 256, VTLists+8 },    // QQQQPR
3602
  { 512, 512, 256, VTLists+8 },    // QQQQPR_with_ssub_0
3603
  { 512, 512, 256, VTLists+8 },    // QQQQPR_with_ssub_4
3604
  { 512, 512, 256, VTLists+8 },    // QQQQPR_with_ssub_8
3605
  { 512, 512, 256, VTLists+8 },    // QQQQPR_with_ssub_12
3606
  { 512, 512, 256, VTLists+8 },    // QQQQPR_with_dsub_0_in_DPR_8
3607
  { 512, 512, 256, VTLists+8 },    // QQQQPR_with_dsub_2_in_DPR_8
3608
  { 512, 512, 256, VTLists+8 },    // QQQQPR_with_dsub_4_in_DPR_8
3609
  { 512, 512, 256, VTLists+8 },    // QQQQPR_with_dsub_6_in_DPR_8
3610
};
3611
3612
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
3613
3614
static const uint32_t SPRSubClassMask[] = {
3615
  0x00000009, 0x00000000, 0x00000000, 0x00000000, 
3616
  0xe00c0000, 0xffff59f5, 0xdfffe6fd, 0x0000003f, // ssub_0
3617
  0xe00c0000, 0xffff59f5, 0xdfffe6fd, 0x0000003f, // ssub_1
3618
  0x00000000, 0xebb241f0, 0xdffde401, 0x0000003f, // ssub_2
3619
  0x00000000, 0xebb241f0, 0xdffde401, 0x0000003f, // ssub_3
3620
  0xc0000000, 0xff9f0001, 0x9ffce0f9, 0x0000003f, // ssub_4
3621
  0xc0000000, 0xff9f0001, 0x9ffce0f9, 0x0000003f, // ssub_5
3622
  0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // ssub_6
3623
  0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // ssub_7
3624
  0x00000000, 0x140c0000, 0x000000f0, 0x0000003f, // ssub_8
3625
  0x00000000, 0x140c0000, 0x000000f0, 0x0000003f, // ssub_9
3626
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_10
3627
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_11
3628
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_12
3629
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_13
3630
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_7_then_ssub_0
3631
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_7_then_ssub_1
3632
};
3633
3634
static const uint32_t GPRSubClassMask[] = {
3635
  0x0001dff2, 0x00000000, 0x00000000, 0x00000000, 
3636
  0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3637
  0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3638
};
3639
3640
static const uint32_t GPRwithAPSRSubClassMask[] = {
3641
  0x00015f34, 0x00000000, 0x00000000, 0x00000000, 
3642
  0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3643
  0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3644
};
3645
3646
static const uint32_t SPR_8SubClassMask[] = {
3647
  0x00000008, 0x00000000, 0x00000000, 0x00000000, 
3648
  0x80080000, 0xfc9801a1, 0x1fa480e1, 0x0000003c, // ssub_0
3649
  0x80080000, 0xfc9801a1, 0x1fa480e1, 0x0000003c, // ssub_1
3650
  0x00000000, 0xc8800180, 0x1ea40001, 0x0000003c, // ssub_2
3651
  0x00000000, 0xc8800180, 0x1ea40001, 0x0000003c, // ssub_3
3652
  0x00000000, 0x9c000001, 0x1ca000c1, 0x00000038, // ssub_4
3653
  0x00000000, 0x9c000001, 0x1ca000c1, 0x00000038, // ssub_5
3654
  0x00000000, 0x00000000, 0x14800000, 0x00000038, // ssub_6
3655
  0x00000000, 0x00000000, 0x14800000, 0x00000038, // ssub_7
3656
  0x00000000, 0x10000000, 0x00000080, 0x00000030, // ssub_8
3657
  0x00000000, 0x10000000, 0x00000080, 0x00000030, // ssub_9
3658
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_10
3659
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_11
3660
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_12
3661
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_13
3662
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_7_then_ssub_0
3663
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_7_then_ssub_1
3664
};
3665
3666
static const uint32_t GPRnopcSubClassMask[] = {
3667
  0x00015f30, 0x00000000, 0x00000000, 0x00000000, 
3668
  0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3669
  0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3670
};
3671
3672
static const uint32_t rGPRSubClassMask[] = {
3673
  0x00011d20, 0x00000000, 0x00000000, 0x00000000, 
3674
  0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3675
  0x06600000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3676
};
3677
3678
static const uint32_t tGPRwithpcSubClassMask[] = {
3679
  0x00009140, 0x00000000, 0x00000000, 0x00000000, 
3680
  0x04400000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3681
  0x04400000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3682
};
3683
3684
static const uint32_t hGPRSubClassMask[] = {
3685
  0x0001c680, 0x00000000, 0x00000000, 0x00000000, 
3686
  0x0a800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3687
  0x0a800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3688
};
3689
3690
static const uint32_t tGPRSubClassMask[] = {
3691
  0x00001100, 0x00000000, 0x00000000, 0x00000000, 
3692
  0x04400000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3693
  0x04400000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3694
};
3695
3696
static const uint32_t GPRnopc_and_hGPRSubClassMask[] = {
3697
  0x00014600, 0x00000000, 0x00000000, 0x00000000, 
3698
  0x0a800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3699
  0x0a800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3700
};
3701
3702
static const uint32_t hGPR_and_rGPRSubClassMask[] = {
3703
  0x00010400, 0x00000000, 0x00000000, 0x00000000, 
3704
  0x0a800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3705
  0x02000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3706
};
3707
3708
static const uint32_t tcGPRSubClassMask[] = {
3709
  0x00011800, 0x00000000, 0x00000000, 0x00000000, 
3710
  0x0d000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3711
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3712
};
3713
3714
static const uint32_t tGPR_and_tcGPRSubClassMask[] = {
3715
  0x00001000, 0x00000000, 0x00000000, 0x00000000, 
3716
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3717
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3718
};
3719
3720
static const uint32_t CCRSubClassMask[] = {
3721
  0x00002000, 0x00000000, 0x00000000, 0x00000000, 
3722
};
3723
3724
static const uint32_t GPRspSubClassMask[] = {
3725
  0x00004000, 0x00000000, 0x00000000, 0x00000000, 
3726
  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3727
};
3728
3729
static const uint32_t hGPR_and_tGPRwithpcSubClassMask[] = {
3730
  0x00008000, 0x00000000, 0x00000000, 0x00000000, 
3731
};
3732
3733
static const uint32_t hGPR_and_tcGPRSubClassMask[] = {
3734
  0x00010000, 0x00000000, 0x00000000, 0x00000000, 
3735
  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3736
};
3737
3738
static const uint32_t DPRSubClassMask[] = {
3739
  0x000e0000, 0x00000000, 0x00000000, 0x00000000, 
3740
  0xf0000000, 0xffffffff, 0xffffffff, 0x0000003f, // dsub_0
3741
  0x00000000, 0xebf2f3fe, 0xffffff01, 0x0000003f, // dsub_1
3742
  0xf0000000, 0xfffffe01, 0xffffffff, 0x0000003f, // dsub_2
3743
  0x00000000, 0x00000000, 0xffffff00, 0x0000003f, // dsub_3
3744
  0x00000000, 0x140d0c00, 0xe00000fe, 0x0000003f, // dsub_4
3745
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_5
3746
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_6
3747
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_7
3748
};
3749
3750
static const uint32_t DPR_VFP2SubClassMask[] = {
3751
  0x000c0000, 0x00000000, 0x00000000, 0x00000000, 
3752
  0xe0000000, 0xffff59f5, 0xdfffe6fd, 0x0000003f, // dsub_0
3753
  0x00000000, 0xebb241f0, 0xdffde401, 0x0000003f, // dsub_1
3754
  0xc0000000, 0xff9f0001, 0x9ffce0f9, 0x0000003f, // dsub_2
3755
  0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // dsub_3
3756
  0x00000000, 0x140c0000, 0x000000f0, 0x0000003f, // dsub_4
3757
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // dsub_5
3758
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_6
3759
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_7
3760
};
3761
3762
static const uint32_t DPR_8SubClassMask[] = {
3763
  0x00080000, 0x00000000, 0x00000000, 0x00000000, 
3764
  0x80000000, 0xfc9801a1, 0x1fa480e1, 0x0000003c, // dsub_0
3765
  0x00000000, 0xc8800180, 0x1ea40001, 0x0000003c, // dsub_1
3766
  0x00000000, 0x9c000001, 0x1ca000c1, 0x00000038, // dsub_2
3767
  0x00000000, 0x00000000, 0x14800000, 0x00000038, // dsub_3
3768
  0x00000000, 0x10000000, 0x00000080, 0x00000030, // dsub_4
3769
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // dsub_5
3770
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_6
3771
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_7
3772
};
3773
3774
static const uint32_t GPRPairSubClassMask[] = {
3775
  0x0ff00000, 0x00000000, 0x00000000, 0x00000000, 
3776
};
3777
3778
static const uint32_t GPRPair_with_gsub_1_in_rGPRSubClassMask[] = {
3779
  0x06600000, 0x00000000, 0x00000000, 0x00000000, 
3780
};
3781
3782
static const uint32_t GPRPair_with_gsub_0_in_tGPRSubClassMask[] = {
3783
  0x04400000, 0x00000000, 0x00000000, 0x00000000, 
3784
};
3785
3786
static const uint32_t GPRPair_with_gsub_0_in_hGPRSubClassMask[] = {
3787
  0x0a800000, 0x00000000, 0x00000000, 0x00000000, 
3788
};
3789
3790
static const uint32_t GPRPair_with_gsub_0_in_tcGPRSubClassMask[] = {
3791
  0x0d000000, 0x00000000, 0x00000000, 0x00000000, 
3792
};
3793
3794
static const uint32_t GPRPair_with_gsub_1_in_hGPR_and_rGPRSubClassMask[] = {
3795
  0x02000000, 0x00000000, 0x00000000, 0x00000000, 
3796
};
3797
3798
static const uint32_t GPRPair_with_gsub_1_in_tcGPRSubClassMask[] = {
3799
  0x04000000, 0x00000000, 0x00000000, 0x00000000, 
3800
};
3801
3802
static const uint32_t GPRPair_with_gsub_1_in_GPRspSubClassMask[] = {
3803
  0x08000000, 0x00000000, 0x00000000, 0x00000000, 
3804
};
3805
3806
static const uint32_t DPairSpcSubClassMask[] = {
3807
  0xf0000000, 0x00000001, 0x00000000, 0x00000000, 
3808
  0x00000000, 0xfffffe00, 0xffffffff, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5
3809
  0x00000000, 0x00000000, 0xffffff00, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7
3810
  0x00000000, 0x140d0c00, 0xe00000fe, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9
3811
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_dsub_5
3812
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_8_ssub_9_ssub_12_ssub_13
3813
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_5_dsub_7
3814
};
3815
3816
static const uint32_t DPairSpc_with_ssub_0SubClassMask[] = {
3817
  0xe0000000, 0x00000001, 0x00000000, 0x00000000, 
3818
  0x00000000, 0xffff5800, 0xdfffe6fd, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5
3819
  0x00000000, 0x00000000, 0xdffde400, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7
3820
  0x00000000, 0x140d0000, 0x800000f8, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9
3821
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_dsub_5
3822
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_8_ssub_9_ssub_12_ssub_13
3823
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // dsub_5_dsub_7
3824
};
3825
3826
static const uint32_t DPairSpc_with_ssub_4SubClassMask[] = {
3827
  0xc0000000, 0x00000001, 0x00000000, 0x00000000, 
3828
  0x00000000, 0xff9f0000, 0x9ffce0f9, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5
3829
  0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7
3830
  0x00000000, 0x140c0000, 0x000000f0, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9
3831
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_dsub_5
3832
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_8_ssub_9_ssub_12_ssub_13
3833
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_5_dsub_7
3834
};
3835
3836
static const uint32_t DPairSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
3837
  0x80000000, 0x00000001, 0x00000000, 0x00000000, 
3838
  0x00000000, 0xfc980000, 0x1fa480e1, 0x0000003c, // ssub_0_ssub_1_ssub_4_ssub_5
3839
  0x00000000, 0x00000000, 0x1ea40000, 0x0000003c, // ssub_2_ssub_3_ssub_6_ssub_7
3840
  0x00000000, 0x14000000, 0x000000c0, 0x00000038, // ssub_4_ssub_5_ssub_8_ssub_9
3841
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_dsub_5
3842
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_8_ssub_9_ssub_12_ssub_13
3843
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // dsub_5_dsub_7
3844
};
3845
3846
static const uint32_t DPairSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
3847
  0x00000000, 0x00000001, 0x00000000, 0x00000000, 
3848
  0x00000000, 0x9c000000, 0x1ca000c1, 0x00000038, // ssub_0_ssub_1_ssub_4_ssub_5
3849
  0x00000000, 0x00000000, 0x14800000, 0x00000038, // ssub_2_ssub_3_ssub_6_ssub_7
3850
  0x00000000, 0x10000000, 0x00000080, 0x00000030, // ssub_4_ssub_5_ssub_8_ssub_9
3851
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_dsub_5
3852
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_8_ssub_9_ssub_12_ssub_13
3853
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_5_dsub_7
3854
};
3855
3856
static const uint32_t DPairSubClassMask[] = {
3857
  0x00000000, 0x000001fe, 0x00000000, 0x00000000, 
3858
  0x00000000, 0xebf2f200, 0xffffff01, 0x0000003f, // qsub_0
3859
  0x00000000, 0x00000000, 0xffffff00, 0x0000003f, // qsub_1
3860
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qsub_2
3861
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qsub_3
3862
  0x00000000, 0xebf2f200, 0xffffff01, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5
3863
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9
3864
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_5_ssub_12_ssub_13
3865
};
3866
3867
static const uint32_t DPair_with_ssub_0SubClassMask[] = {
3868
  0x00000000, 0x000001f4, 0x00000000, 0x00000000, 
3869
  0x00000000, 0xebf25000, 0xdfffe601, 0x0000003f, // qsub_0
3870
  0x00000000, 0x00000000, 0x9ffce000, 0x0000003f, // qsub_1
3871
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qsub_2
3872
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qsub_3
3873
  0x00000000, 0xebb24000, 0xdffde401, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5
3874
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9
3875
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // dsub_5_ssub_12_ssub_13
3876
};
3877
3878
static const uint32_t QPRSubClassMask[] = {
3879
  0x00000000, 0x00000148, 0x00000000, 0x00000000, 
3880
  0x00000000, 0xc2202000, 0xe6090800, 0x0000003f, // qsub_0
3881
  0x00000000, 0x00000000, 0xe6090800, 0x0000003f, // qsub_1
3882
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qsub_2
3883
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qsub_3
3884
  0x00000000, 0x21408000, 0x19521001, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3885
};
3886
3887
static const uint32_t DPair_with_ssub_2SubClassMask[] = {
3888
  0x00000000, 0x000001f0, 0x00000000, 0x00000000, 
3889
  0x00000000, 0xebb24000, 0xdffde401, 0x0000003f, // qsub_0
3890
  0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // qsub_1
3891
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qsub_2
3892
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qsub_3
3893
  0x00000000, 0xeb920000, 0x9ffce001, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5
3894
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9
3895
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_5_ssub_12_ssub_13
3896
};
3897
3898
static const uint32_t DPair_with_dsub_0_in_DPR_8SubClassMask[] = {
3899
  0x00000000, 0x000001a0, 0x00000000, 0x00000000, 
3900
  0x00000000, 0xe8900000, 0x1fa48001, 0x0000003c, // qsub_0
3901
  0x00000000, 0x00000000, 0x1ca00000, 0x00000038, // qsub_1
3902
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // qsub_2
3903
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // qsub_3
3904
  0x00000000, 0xc8800000, 0x1ea40001, 0x0000003c, // ssub_2_ssub_3_ssub_4_ssub_5
3905
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_ssub_8_ssub_9
3906
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // dsub_5_ssub_12_ssub_13
3907
};
3908
3909
static const uint32_t QPR_VFP2SubClassMask[] = {
3910
  0x00000000, 0x00000140, 0x00000000, 0x00000000, 
3911
  0x00000000, 0xc2200000, 0xc6090000, 0x0000003f, // qsub_0
3912
  0x00000000, 0x00000000, 0x86080000, 0x0000003f, // qsub_1
3913
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qsub_2
3914
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qsub_3
3915
  0x00000000, 0x21000000, 0x19500001, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3916
};
3917
3918
static const uint32_t DPair_with_dsub_1_in_DPR_8SubClassMask[] = {
3919
  0x00000000, 0x00000180, 0x00000000, 0x00000000, 
3920
  0x00000000, 0xc8800000, 0x1ea40001, 0x0000003c, // qsub_0
3921
  0x00000000, 0x00000000, 0x14800000, 0x00000038, // qsub_1
3922
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // qsub_2
3923
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // qsub_3
3924
  0x00000000, 0x88000000, 0x1ca00001, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5
3925
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9
3926
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_5_ssub_12_ssub_13
3927
};
3928
3929
static const uint32_t QPR_8SubClassMask[] = {
3930
  0x00000000, 0x00000100, 0x00000000, 0x00000000, 
3931
  0x00000000, 0xc0000000, 0x06000000, 0x0000003c, // qsub_0
3932
  0x00000000, 0x00000000, 0x04000000, 0x00000038, // qsub_1
3933
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // qsub_2
3934
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // qsub_3
3935
  0x00000000, 0x00000000, 0x18000001, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3936
};
3937
3938
static const uint32_t DTripleSubClassMask[] = {
3939
  0x00000000, 0xebf2f200, 0x00000001, 0x00000000, 
3940
  0x00000000, 0x00000000, 0xffffff00, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3941
  0x00000000, 0x00000000, 0xffffff00, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3942
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3943
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
3944
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3945
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_5_ssub_12_ssub_13_dsub_7
3946
};
3947
3948
static const uint32_t DTripleSpcSubClassMask[] = {
3949
  0x00000000, 0x140d0c00, 0x000000fe, 0x00000000, 
3950
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
3951
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
3952
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3953
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
3954
};
3955
3956
static const uint32_t DTripleSpc_with_ssub_0SubClassMask[] = {
3957
  0x00000000, 0x140d0800, 0x000000fc, 0x00000000, 
3958
  0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
3959
  0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
3960
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3961
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
3962
};
3963
3964
static const uint32_t DTriple_with_ssub_0SubClassMask[] = {
3965
  0x00000000, 0xebf25000, 0x00000001, 0x00000000, 
3966
  0x00000000, 0x00000000, 0xdfffe600, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3967
  0x00000000, 0x00000000, 0xdffde400, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3968
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3969
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
3970
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3971
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // dsub_5_ssub_12_ssub_13_dsub_7
3972
};
3973
3974
static const uint32_t DTriple_with_qsub_0_in_QPRSubClassMask[] = {
3975
  0x00000000, 0xc2202000, 0x00000000, 0x00000000, 
3976
  0x00000000, 0x00000000, 0xe6090800, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3977
  0x00000000, 0x00000000, 0x19521000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3978
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3979
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3980
};
3981
3982
static const uint32_t DTriple_with_ssub_2SubClassMask[] = {
3983
  0x00000000, 0xebb24000, 0x00000001, 0x00000000, 
3984
  0x00000000, 0x00000000, 0xdffde400, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3985
  0x00000000, 0x00000000, 0x9ffce000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3986
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3987
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
3988
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3989
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_5_ssub_12_ssub_13_dsub_7
3990
};
3991
3992
static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
3993
  0x00000000, 0x21408000, 0x00000001, 0x00000000, 
3994
  0x00000000, 0x00000000, 0x19521000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3995
  0x00000000, 0x00000000, 0xe6090800, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3996
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
3997
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_5_ssub_12_ssub_13_dsub_7
3998
};
3999
4000
static const uint32_t DTripleSpc_with_ssub_4SubClassMask[] = {
4001
  0x00000000, 0x140d0000, 0x000000f8, 0x00000000, 
4002
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4003
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4004
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4005
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
4006
};
4007
4008
static const uint32_t DTriple_with_ssub_4SubClassMask[] = {
4009
  0x00000000, 0xeb920000, 0x00000001, 0x00000000, 
4010
  0x00000000, 0x00000000, 0x9ffce000, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4011
  0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4012
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4013
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4014
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4015
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_5_ssub_12_ssub_13_dsub_7
4016
};
4017
4018
static const uint32_t DTripleSpc_with_ssub_8SubClassMask[] = {
4019
  0x00000000, 0x140c0000, 0x000000f0, 0x00000000, 
4020
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4021
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4022
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4023
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_6_ssub_7_dsub_5_dsub_7
4024
};
4025
4026
static const uint32_t DTripleSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
4027
  0x00000000, 0x14080000, 0x000000e0, 0x00000000, 
4028
  0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4029
  0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4030
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4031
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_dsub_5_dsub_7
4032
};
4033
4034
static const uint32_t DTriple_with_dsub_0_in_DPR_8SubClassMask[] = {
4035
  0x00000000, 0xe8900000, 0x00000001, 0x00000000, 
4036
  0x00000000, 0x00000000, 0x1fa48000, 0x0000003c, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4037
  0x00000000, 0x00000000, 0x1ea40000, 0x0000003c, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4038
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4039
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4040
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4041
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // dsub_5_ssub_12_ssub_13_dsub_7
4042
};
4043
4044
static const uint32_t DTriple_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
4045
  0x00000000, 0xc2200000, 0x00000000, 0x00000000, 
4046
  0x00000000, 0x00000000, 0xc6090000, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4047
  0x00000000, 0x00000000, 0x19500000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4048
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4049
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4050
};
4051
4052
static const uint32_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4053
  0x00000000, 0x21400000, 0x00000001, 0x00000000, 
4054
  0x00000000, 0x00000000, 0x19520000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4055
  0x00000000, 0x00000000, 0xc6090000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4056
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4057
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // dsub_5_ssub_12_ssub_13_dsub_7
4058
};
4059
4060
static const uint32_t DTriple_with_dsub_1_in_DPR_8SubClassMask[] = {
4061
  0x00000000, 0xc8800000, 0x00000001, 0x00000000, 
4062
  0x00000000, 0x00000000, 0x1ea40000, 0x0000003c, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4063
  0x00000000, 0x00000000, 0x1ca00000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4064
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4065
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4066
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4067
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_5_ssub_12_ssub_13_dsub_7
4068
};
4069
4070
static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
4071
  0x00000000, 0x21000000, 0x00000001, 0x00000000, 
4072
  0x00000000, 0x00000000, 0x19500000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4073
  0x00000000, 0x00000000, 0x86080000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4074
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4075
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_5_ssub_12_ssub_13_dsub_7
4076
};
4077
4078
static const uint32_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
4079
  0x00000000, 0xc2000000, 0x00000000, 0x00000000, 
4080
  0x00000000, 0x00000000, 0x86080000, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4081
  0x00000000, 0x00000000, 0x19400000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4082
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4083
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4084
};
4085
4086
static const uint32_t DTripleSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
4087
  0x00000000, 0x14000000, 0x000000c0, 0x00000000, 
4088
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4089
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4090
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4091
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_dsub_5_dsub_7
4092
};
4093
4094
static const uint32_t DTriple_with_dsub_2_in_DPR_8SubClassMask[] = {
4095
  0x00000000, 0x88000000, 0x00000001, 0x00000000, 
4096
  0x00000000, 0x00000000, 0x1ca00000, 0x00000038, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4097
  0x00000000, 0x00000000, 0x14800000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4098
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4099
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4100
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4101
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_5_ssub_12_ssub_13_dsub_7
4102
};
4103
4104
static const uint32_t DTripleSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
4105
  0x00000000, 0x10000000, 0x00000080, 0x00000000, 
4106
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4107
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4108
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4109
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_6_ssub_7_dsub_5_dsub_7
4110
};
4111
4112
static const uint32_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4113
  0x00000000, 0x20000000, 0x00000001, 0x00000000, 
4114
  0x00000000, 0x00000000, 0x19000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4115
  0x00000000, 0x00000000, 0x06000000, 0x0000003c, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4116
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4117
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // dsub_5_ssub_12_ssub_13_dsub_7
4118
};
4119
4120
static const uint32_t DTriple_with_qsub_0_in_QPR_8SubClassMask[] = {
4121
  0x00000000, 0xc0000000, 0x00000000, 0x00000000, 
4122
  0x00000000, 0x00000000, 0x06000000, 0x0000003c, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4123
  0x00000000, 0x00000000, 0x18000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4124
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4125
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4126
};
4127
4128
static const uint32_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
4129
  0x00000000, 0x80000000, 0x00000000, 0x00000000, 
4130
  0x00000000, 0x00000000, 0x04000000, 0x00000038, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4131
  0x00000000, 0x00000000, 0x10000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4132
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4133
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4134
};
4135
4136
static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
4137
  0x00000000, 0x00000000, 0x00000001, 0x00000000, 
4138
  0x00000000, 0x00000000, 0x18000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4139
  0x00000000, 0x00000000, 0x04000000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4140
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4141
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_5_ssub_12_ssub_13_dsub_7
4142
};
4143
4144
static const uint32_t DQuadSpcSubClassMask[] = {
4145
  0x00000000, 0x00000000, 0x000000fe, 0x00000000, 
4146
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4147
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4148
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4149
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
4150
};
4151
4152
static const uint32_t DQuadSpc_with_ssub_0SubClassMask[] = {
4153
  0x00000000, 0x00000000, 0x000000fc, 0x00000000, 
4154
  0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4155
  0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4156
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4157
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
4158
};
4159
4160
static const uint32_t DQuadSpc_with_ssub_4SubClassMask[] = {
4161
  0x00000000, 0x00000000, 0x000000f8, 0x00000000, 
4162
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4163
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4164
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4165
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
4166
};
4167
4168
static const uint32_t DQuadSpc_with_ssub_8SubClassMask[] = {
4169
  0x00000000, 0x00000000, 0x000000f0, 0x00000000, 
4170
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4171
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4172
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4173
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_6_ssub_7_dsub_5_dsub_7
4174
};
4175
4176
static const uint32_t DQuadSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
4177
  0x00000000, 0x00000000, 0x000000e0, 0x00000000, 
4178
  0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4179
  0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4180
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4181
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_dsub_5_dsub_7
4182
};
4183
4184
static const uint32_t DQuadSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
4185
  0x00000000, 0x00000000, 0x000000c0, 0x00000000, 
4186
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4187
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4188
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4189
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_dsub_5_dsub_7
4190
};
4191
4192
static const uint32_t DQuadSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
4193
  0x00000000, 0x00000000, 0x00000080, 0x00000000, 
4194
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4195
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4196
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4197
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_6_ssub_7_dsub_5_dsub_7
4198
};
4199
4200
static const uint32_t DQuadSubClassMask[] = {
4201
  0x00000000, 0x00000000, 0x1fffff00, 0x00000000, 
4202
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qqsub_0
4203
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qqsub_1
4204
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4205
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4206
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4207
};
4208
4209
static const uint32_t DQuad_with_ssub_0SubClassMask[] = {
4210
  0x00000000, 0x00000000, 0x1fffe600, 0x00000000, 
4211
  0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // qqsub_0
4212
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qqsub_1
4213
  0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4214
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4215
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4216
};
4217
4218
static const uint32_t DQuad_with_ssub_2SubClassMask[] = {
4219
  0x00000000, 0x00000000, 0x1ffde400, 0x00000000, 
4220
  0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // qqsub_0
4221
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qqsub_1
4222
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4223
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4224
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4225
};
4226
4227
static const uint32_t QQPRSubClassMask[] = {
4228
  0x00000000, 0x00000000, 0x06090800, 0x00000000, 
4229
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qqsub_0
4230
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qqsub_1
4231
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4232
};
4233
4234
static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4235
  0x00000000, 0x00000000, 0x19521000, 0x00000000, 
4236
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4237
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4238
};
4239
4240
static const uint32_t DQuad_with_ssub_4SubClassMask[] = {
4241
  0x00000000, 0x00000000, 0x1ffce000, 0x00000000, 
4242
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // qqsub_0
4243
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qqsub_1
4244
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4245
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4246
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4247
};
4248
4249
static const uint32_t DQuad_with_ssub_6SubClassMask[] = {
4250
  0x00000000, 0x00000000, 0x1fecc000, 0x00000000, 
4251
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // qqsub_0
4252
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qqsub_1
4253
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4254
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4255
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4256
};
4257
4258
static const uint32_t DQuad_with_dsub_0_in_DPR_8SubClassMask[] = {
4259
  0x00000000, 0x00000000, 0x1fa48000, 0x00000000, 
4260
  0x00000000, 0x00000000, 0x00000000, 0x0000003c, // qqsub_0
4261
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // qqsub_1
4262
  0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4263
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4264
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4265
};
4266
4267
static const uint32_t DQuad_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
4268
  0x00000000, 0x00000000, 0x06090000, 0x00000000, 
4269
  0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // qqsub_0
4270
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qqsub_1
4271
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4272
};
4273
4274
static const uint32_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4275
  0x00000000, 0x00000000, 0x19520000, 0x00000000, 
4276
  0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4277
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4278
};
4279
4280
static const uint32_t DQuad_with_dsub_1_in_DPR_8SubClassMask[] = {
4281
  0x00000000, 0x00000000, 0x1ea40000, 0x00000000, 
4282
  0x00000000, 0x00000000, 0x00000000, 0x0000003c, // qqsub_0
4283
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // qqsub_1
4284
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4285
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4286
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4287
};
4288
4289
static const uint32_t DQuad_with_qsub_1_in_QPR_VFP2SubClassMask[] = {
4290
  0x00000000, 0x00000000, 0x06080000, 0x00000000, 
4291
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // qqsub_0
4292
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qqsub_1
4293
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4294
};
4295
4296
static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
4297
  0x00000000, 0x00000000, 0x19500000, 0x00000000, 
4298
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4299
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4300
};
4301
4302
static const uint32_t DQuad_with_dsub_2_in_DPR_8SubClassMask[] = {
4303
  0x00000000, 0x00000000, 0x1ca00000, 0x00000000, 
4304
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // qqsub_0
4305
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // qqsub_1
4306
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4307
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4308
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4309
};
4310
4311
static const uint32_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4312
  0x00000000, 0x00000000, 0x19400000, 0x00000000, 
4313
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4314
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4315
};
4316
4317
static const uint32_t DQuad_with_dsub_3_in_DPR_8SubClassMask[] = {
4318
  0x00000000, 0x00000000, 0x14800000, 0x00000000, 
4319
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // qqsub_0
4320
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // qqsub_1
4321
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4322
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4323
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4324
};
4325
4326
static const uint32_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4327
  0x00000000, 0x00000000, 0x19000000, 0x00000000, 
4328
  0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4329
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4330
};
4331
4332
static const uint32_t DQuad_with_qsub_0_in_QPR_8SubClassMask[] = {
4333
  0x00000000, 0x00000000, 0x06000000, 0x00000000, 
4334
  0x00000000, 0x00000000, 0x00000000, 0x0000003c, // qqsub_0
4335
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // qqsub_1
4336
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4337
};
4338
4339
static const uint32_t DQuad_with_qsub_1_in_QPR_8SubClassMask[] = {
4340
  0x00000000, 0x00000000, 0x04000000, 0x00000000, 
4341
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // qqsub_0
4342
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // qqsub_1
4343
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4344
};
4345
4346
static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
4347
  0x00000000, 0x00000000, 0x18000000, 0x00000000, 
4348
  0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4349
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4350
};
4351
4352
static const uint32_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4353
  0x00000000, 0x00000000, 0x10000000, 0x00000000, 
4354
  0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4355
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4356
};
4357
4358
static const uint32_t QQQQPRSubClassMask[] = {
4359
  0x00000000, 0x00000000, 0xe0000000, 0x0000003f, 
4360
};
4361
4362
static const uint32_t QQQQPR_with_ssub_0SubClassMask[] = {
4363
  0x00000000, 0x00000000, 0xc0000000, 0x0000003f, 
4364
};
4365
4366
static const uint32_t QQQQPR_with_ssub_4SubClassMask[] = {
4367
  0x00000000, 0x00000000, 0x80000000, 0x0000003f, 
4368
};
4369
4370
static const uint32_t QQQQPR_with_ssub_8SubClassMask[] = {
4371
  0x00000000, 0x00000000, 0x00000000, 0x0000003f, 
4372
};
4373
4374
static const uint32_t QQQQPR_with_ssub_12SubClassMask[] = {
4375
  0x00000000, 0x00000000, 0x00000000, 0x0000003e, 
4376
};
4377
4378
static const uint32_t QQQQPR_with_dsub_0_in_DPR_8SubClassMask[] = {
4379
  0x00000000, 0x00000000, 0x00000000, 0x0000003c, 
4380
};
4381
4382
static const uint32_t QQQQPR_with_dsub_2_in_DPR_8SubClassMask[] = {
4383
  0x00000000, 0x00000000, 0x00000000, 0x00000038, 
4384
};
4385
4386
static const uint32_t QQQQPR_with_dsub_4_in_DPR_8SubClassMask[] = {
4387
  0x00000000, 0x00000000, 0x00000000, 0x00000030, 
4388
};
4389
4390
static const uint32_t QQQQPR_with_dsub_6_in_DPR_8SubClassMask[] = {
4391
  0x00000000, 0x00000000, 0x00000000, 0x00000020, 
4392
};
4393
4394
static const uint16_t SuperRegIdxSeqs[] = {
4395
  /* 0 */ 1, 2, 3, 4, 5, 6, 7, 8, 0,
4396
  /* 9 */ 9, 0,
4397
  /* 11 */ 9, 10, 0,
4398
  /* 14 */ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0,
4399
  /* 31 */ 13, 14, 15, 16, 37, 0,
4400
  /* 37 */ 38, 40, 45, 48, 0,
4401
  /* 42 */ 42, 50, 0,
4402
  /* 45 */ 34, 36, 44, 52, 0,
4403
  /* 50 */ 33, 35, 43, 46, 51, 53, 0,
4404
  /* 57 */ 34, 36, 47, 54, 0,
4405
  /* 62 */ 34, 36, 44, 47, 52, 54, 0,
4406
  /* 69 */ 13, 14, 15, 16, 37, 49, 55, 0,
4407
  /* 77 */ 11, 12, 56, 0,
4408
  /* 81 */ 11, 12, 42, 50, 56, 0,
4409
};
4410
4411
static const TargetRegisterClass *const SPR_8Superclasses[] = {
4412
  &ARM::SPRRegClass,
4413
  nullptr
4414
};
4415
4416
static const TargetRegisterClass *const GPRnopcSuperclasses[] = {
4417
  &ARM::GPRRegClass,
4418
  &ARM::GPRwithAPSRRegClass,
4419
  nullptr
4420
};
4421
4422
static const TargetRegisterClass *const rGPRSuperclasses[] = {
4423
  &ARM::GPRRegClass,
4424
  &ARM::GPRwithAPSRRegClass,
4425
  &ARM::GPRnopcRegClass,
4426
  nullptr
4427
};
4428
4429
static const TargetRegisterClass *const tGPRwithpcSuperclasses[] = {
4430
  &ARM::GPRRegClass,
4431
  nullptr
4432
};
4433
4434
static const TargetRegisterClass *const hGPRSuperclasses[] = {
4435
  &ARM::GPRRegClass,
4436
  nullptr
4437
};
4438
4439
static const TargetRegisterClass *const tGPRSuperclasses[] = {
4440
  &ARM::GPRRegClass,
4441
  &ARM::GPRwithAPSRRegClass,
4442
  &ARM::GPRnopcRegClass,
4443
  &ARM::rGPRRegClass,
4444
  &ARM::tGPRwithpcRegClass,
4445
  nullptr
4446
};
4447
4448
static const TargetRegisterClass *const GPRnopc_and_hGPRSuperclasses[] = {
4449
  &ARM::GPRRegClass,
4450
  &ARM::GPRwithAPSRRegClass,
4451
  &ARM::GPRnopcRegClass,
4452
  &ARM::hGPRRegClass,
4453
  nullptr
4454
};
4455
4456
static const TargetRegisterClass *const hGPR_and_rGPRSuperclasses[] = {
4457
  &ARM::GPRRegClass,
4458
  &ARM::GPRwithAPSRRegClass,
4459
  &ARM::GPRnopcRegClass,
4460
  &ARM::rGPRRegClass,
4461
  &ARM::hGPRRegClass,
4462
  &ARM::GPRnopc_and_hGPRRegClass,
4463
  nullptr
4464
};
4465
4466
static const TargetRegisterClass *const tcGPRSuperclasses[] = {
4467
  &ARM::GPRRegClass,
4468
  &ARM::GPRwithAPSRRegClass,
4469
  &ARM::GPRnopcRegClass,
4470
  &ARM::rGPRRegClass,
4471
  nullptr
4472
};
4473
4474
static const TargetRegisterClass *const tGPR_and_tcGPRSuperclasses[] = {
4475
  &ARM::GPRRegClass,
4476
  &ARM::GPRwithAPSRRegClass,
4477
  &ARM::GPRnopcRegClass,
4478
  &ARM::rGPRRegClass,
4479
  &ARM::tGPRwithpcRegClass,
4480
  &ARM::tGPRRegClass,
4481
  &ARM::tcGPRRegClass,
4482
  nullptr
4483
};
4484
4485
static const TargetRegisterClass *const GPRspSuperclasses[] = {
4486
  &ARM::GPRRegClass,
4487
  &ARM::GPRwithAPSRRegClass,
4488
  &ARM::GPRnopcRegClass,
4489
  &ARM::hGPRRegClass,
4490
  &ARM::GPRnopc_and_hGPRRegClass,
4491
  nullptr
4492
};
4493
4494
static const TargetRegisterClass *const hGPR_and_tGPRwithpcSuperclasses[] = {
4495
  &ARM::GPRRegClass,
4496
  &ARM::tGPRwithpcRegClass,
4497
  &ARM::hGPRRegClass,
4498
  nullptr
4499
};
4500
4501
static const TargetRegisterClass *const hGPR_and_tcGPRSuperclasses[] = {
4502
  &ARM::GPRRegClass,
4503
  &ARM::GPRwithAPSRRegClass,
4504
  &ARM::GPRnopcRegClass,
4505
  &ARM::rGPRRegClass,
4506
  &ARM::hGPRRegClass,
4507
  &ARM::GPRnopc_and_hGPRRegClass,
4508
  &ARM::hGPR_and_rGPRRegClass,
4509
  &ARM::tcGPRRegClass,
4510
  nullptr
4511
};
4512
4513
static const TargetRegisterClass *const DPR_VFP2Superclasses[] = {
4514
  &ARM::DPRRegClass,
4515
  nullptr
4516
};
4517
4518
static const TargetRegisterClass *const DPR_8Superclasses[] = {
4519
  &ARM::DPRRegClass,
4520
  &ARM::DPR_VFP2RegClass,
4521
  nullptr
4522
};
4523
4524
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_rGPRSuperclasses[] = {
4525
  &ARM::GPRPairRegClass,
4526
  nullptr
4527
};
4528
4529
static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tGPRSuperclasses[] = {
4530
  &ARM::GPRPairRegClass,
4531
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4532
  nullptr
4533
};
4534
4535
static const TargetRegisterClass *const GPRPair_with_gsub_0_in_hGPRSuperclasses[] = {
4536
  &ARM::GPRPairRegClass,
4537
  nullptr
4538
};
4539
4540
static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tcGPRSuperclasses[] = {
4541
  &ARM::GPRPairRegClass,
4542
  nullptr
4543
};
4544
4545
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_hGPR_and_rGPRSuperclasses[] = {
4546
  &ARM::GPRPairRegClass,
4547
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4548
  &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
4549
  nullptr
4550
};
4551
4552
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_tcGPRSuperclasses[] = {
4553
  &ARM::GPRPairRegClass,
4554
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4555
  &ARM::GPRPair_with_gsub_0_in_tGPRRegClass,
4556
  &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
4557
  nullptr
4558
};
4559
4560
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_GPRspSuperclasses[] = {
4561
  &ARM::GPRPairRegClass,
4562
  &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
4563
  &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
4564
  nullptr
4565
};
4566
4567
static const TargetRegisterClass *const DPairSpc_with_ssub_0Superclasses[] = {
4568
  &ARM::DPairSpcRegClass,
4569
  nullptr
4570
};
4571
4572
static const TargetRegisterClass *const DPairSpc_with_ssub_4Superclasses[] = {
4573
  &ARM::DPairSpcRegClass,
4574
  &ARM::DPairSpc_with_ssub_0RegClass,
4575
  nullptr
4576
};
4577
4578
static const TargetRegisterClass *const DPairSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4579
  &ARM::DPairSpcRegClass,
4580
  &ARM::DPairSpc_with_ssub_0RegClass,
4581
  &ARM::DPairSpc_with_ssub_4RegClass,
4582
  nullptr
4583
};
4584
4585
static const TargetRegisterClass *const DPairSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4586
  &ARM::DPairSpcRegClass,
4587
  &ARM::DPairSpc_with_ssub_0RegClass,
4588
  &ARM::DPairSpc_with_ssub_4RegClass,
4589
  &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass,
4590
  nullptr
4591
};
4592
4593
static const TargetRegisterClass *const DPair_with_ssub_0Superclasses[] = {
4594
  &ARM::DPairRegClass,
4595
  nullptr
4596
};
4597
4598
static const TargetRegisterClass *const QPRSuperclasses[] = {
4599
  &ARM::DPairRegClass,
4600
  nullptr
4601
};
4602
4603
static const TargetRegisterClass *const DPair_with_ssub_2Superclasses[] = {
4604
  &ARM::DPairRegClass,
4605
  &ARM::DPair_with_ssub_0RegClass,
4606
  nullptr
4607
};
4608
4609
static const TargetRegisterClass *const DPair_with_dsub_0_in_DPR_8Superclasses[] = {
4610
  &ARM::DPairRegClass,
4611
  &ARM::DPair_with_ssub_0RegClass,
4612
  &ARM::DPair_with_ssub_2RegClass,
4613
  nullptr
4614
};
4615
4616
static const TargetRegisterClass *const QPR_VFP2Superclasses[] = {
4617
  &ARM::DPairRegClass,
4618
  &ARM::DPair_with_ssub_0RegClass,
4619
  &ARM::QPRRegClass,
4620
  &ARM::DPair_with_ssub_2RegClass,
4621
  nullptr
4622
};
4623
4624
static const TargetRegisterClass *const DPair_with_dsub_1_in_DPR_8Superclasses[] = {
4625
  &ARM::DPairRegClass,
4626
  &ARM::DPair_with_ssub_0RegClass,
4627
  &ARM::DPair_with_ssub_2RegClass,
4628
  &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
4629
  nullptr
4630
};
4631
4632
static const TargetRegisterClass *const QPR_8Superclasses[] = {
4633
  &ARM::DPairRegClass,
4634
  &ARM::DPair_with_ssub_0RegClass,
4635
  &ARM::QPRRegClass,
4636
  &ARM::DPair_with_ssub_2RegClass,
4637
  &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
4638
  &ARM::QPR_VFP2RegClass,
4639
  &ARM::DPair_with_dsub_1_in_DPR_8RegClass,
4640
  nullptr
4641
};
4642
4643
static const TargetRegisterClass *const DTripleSpc_with_ssub_0Superclasses[] = {
4644
  &ARM::DTripleSpcRegClass,
4645
  nullptr
4646
};
4647
4648
static const TargetRegisterClass *const DTriple_with_ssub_0Superclasses[] = {
4649
  &ARM::DTripleRegClass,
4650
  nullptr
4651
};
4652
4653
static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4654
  &ARM::DTripleRegClass,
4655
  nullptr
4656
};
4657
4658
static const TargetRegisterClass *const DTriple_with_ssub_2Superclasses[] = {
4659
  &ARM::DTripleRegClass,
4660
  &ARM::DTriple_with_ssub_0RegClass,
4661
  nullptr
4662
};
4663
4664
static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4665
  &ARM::DTripleRegClass,
4666
  nullptr
4667
};
4668
4669
static const TargetRegisterClass *const DTripleSpc_with_ssub_4Superclasses[] = {
4670
  &ARM::DTripleSpcRegClass,
4671
  &ARM::DTripleSpc_with_ssub_0RegClass,
4672
  nullptr
4673
};
4674
4675
static const TargetRegisterClass *const DTriple_with_ssub_4Superclasses[] = {
4676
  &ARM::DTripleRegClass,
4677
  &ARM::DTriple_with_ssub_0RegClass,
4678
  &ARM::DTriple_with_ssub_2RegClass,
4679
  nullptr
4680
};
4681
4682
static const TargetRegisterClass *const DTripleSpc_with_ssub_8Superclasses[] = {
4683
  &ARM::DTripleSpcRegClass,
4684
  &ARM::DTripleSpc_with_ssub_0RegClass,
4685
  &ARM::DTripleSpc_with_ssub_4RegClass,
4686
  nullptr
4687
};
4688
4689
static const TargetRegisterClass *const DTripleSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4690
  &ARM::DTripleSpcRegClass,
4691
  &ARM::DTripleSpc_with_ssub_0RegClass,
4692
  &ARM::DTripleSpc_with_ssub_4RegClass,
4693
  &ARM::DTripleSpc_with_ssub_8RegClass,
4694
  nullptr
4695
};
4696
4697
static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8Superclasses[] = {
4698
  &ARM::DTripleRegClass,
4699
  &ARM::DTriple_with_ssub_0RegClass,
4700
  &ARM::DTriple_with_ssub_2RegClass,
4701
  &ARM::DTriple_with_ssub_4RegClass,
4702
  nullptr
4703
};
4704
4705
static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_VFP2Superclasses[] = {
4706
  &ARM::DTripleRegClass,
4707
  &ARM::DTriple_with_ssub_0RegClass,
4708
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4709
  &ARM::DTriple_with_ssub_2RegClass,
4710
  nullptr
4711
};
4712
4713
static const TargetRegisterClass *const DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4714
  &ARM::DTripleRegClass,
4715
  &ARM::DTriple_with_ssub_0RegClass,
4716
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4717
  nullptr
4718
};
4719
4720
static const TargetRegisterClass *const DTriple_with_dsub_1_in_DPR_8Superclasses[] = {
4721
  &ARM::DTripleRegClass,
4722
  &ARM::DTriple_with_ssub_0RegClass,
4723
  &ARM::DTriple_with_ssub_2RegClass,
4724
  &ARM::DTriple_with_ssub_4RegClass,
4725
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4726
  nullptr
4727
};
4728
4729
static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
4730
  &ARM::DTripleRegClass,
4731
  &ARM::DTriple_with_ssub_0RegClass,
4732
  &ARM::DTriple_with_ssub_2RegClass,
4733
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4734
  &ARM::DTriple_with_ssub_4RegClass,
4735
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4736
  nullptr
4737
};
4738
4739
static const TargetRegisterClass *const DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4740
  &ARM::DTripleRegClass,
4741
  &ARM::DTriple_with_ssub_0RegClass,
4742
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4743
  &ARM::DTriple_with_ssub_2RegClass,
4744
  &ARM::DTriple_with_ssub_4RegClass,
4745
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4746
  nullptr
4747
};
4748
4749
static const TargetRegisterClass *const DTripleSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4750
  &ARM::DTripleSpcRegClass,
4751
  &ARM::DTripleSpc_with_ssub_0RegClass,
4752
  &ARM::DTripleSpc_with_ssub_4RegClass,
4753
  &ARM::DTripleSpc_with_ssub_8RegClass,
4754
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4755
  nullptr
4756
};
4757
4758
static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8Superclasses[] = {
4759
  &ARM::DTripleRegClass,
4760
  &ARM::DTriple_with_ssub_0RegClass,
4761
  &ARM::DTriple_with_ssub_2RegClass,
4762
  &ARM::DTriple_with_ssub_4RegClass,
4763
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4764
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4765
  nullptr
4766
};
4767
4768
static const TargetRegisterClass *const DTripleSpc_with_dsub_4_in_DPR_8Superclasses[] = {
4769
  &ARM::DTripleSpcRegClass,
4770
  &ARM::DTripleSpc_with_ssub_0RegClass,
4771
  &ARM::DTripleSpc_with_ssub_4RegClass,
4772
  &ARM::DTripleSpc_with_ssub_8RegClass,
4773
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4774
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4775
  nullptr
4776
};
4777
4778
static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4779
  &ARM::DTripleRegClass,
4780
  &ARM::DTriple_with_ssub_0RegClass,
4781
  &ARM::DTriple_with_ssub_2RegClass,
4782
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4783
  &ARM::DTriple_with_ssub_4RegClass,
4784
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4785
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4786
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
4787
  nullptr
4788
};
4789
4790
static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_8Superclasses[] = {
4791
  &ARM::DTripleRegClass,
4792
  &ARM::DTriple_with_ssub_0RegClass,
4793
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4794
  &ARM::DTriple_with_ssub_2RegClass,
4795
  &ARM::DTriple_with_ssub_4RegClass,
4796
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4797
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4798
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4799
  &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
4800
  nullptr
4801
};
4802
4803
static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4804
  &ARM::DTripleRegClass,
4805
  &ARM::DTriple_with_ssub_0RegClass,
4806
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4807
  &ARM::DTriple_with_ssub_2RegClass,
4808
  &ARM::DTriple_with_ssub_4RegClass,
4809
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4810
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4811
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4812
  &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
4813
  &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
4814
  &ARM::DTriple_with_qsub_0_in_QPR_8RegClass,
4815
  nullptr
4816
};
4817
4818
static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
4819
  &ARM::DTripleRegClass,
4820
  &ARM::DTriple_with_ssub_0RegClass,
4821
  &ARM::DTriple_with_ssub_2RegClass,
4822
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4823
  &ARM::DTriple_with_ssub_4RegClass,
4824
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4825
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4826
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4827
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
4828
  &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
4829
  &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4830
  nullptr
4831
};
4832
4833
static const TargetRegisterClass *const DQuadSpcSuperclasses[] = {
4834
  &ARM::DTripleSpcRegClass,
4835
  nullptr
4836
};
4837
4838
static const TargetRegisterClass *const DQuadSpc_with_ssub_0Superclasses[] = {
4839
  &ARM::DTripleSpcRegClass,
4840
  &ARM::DTripleSpc_with_ssub_0RegClass,
4841
  &ARM::DQuadSpcRegClass,
4842
  nullptr
4843
};
4844
4845
static const TargetRegisterClass *const DQuadSpc_with_ssub_4Superclasses[] = {
4846
  &ARM::DTripleSpcRegClass,
4847
  &ARM::DTripleSpc_with_ssub_0RegClass,
4848
  &ARM::DTripleSpc_with_ssub_4RegClass,
4849
  &ARM::DQuadSpcRegClass,
4850
  &ARM::DQuadSpc_with_ssub_0RegClass,
4851
  nullptr
4852
};
4853
4854
static const TargetRegisterClass *const DQuadSpc_with_ssub_8Superclasses[] = {
4855
  &ARM::DTripleSpcRegClass,
4856
  &ARM::DTripleSpc_with_ssub_0RegClass,
4857
  &ARM::DTripleSpc_with_ssub_4RegClass,
4858
  &ARM::DTripleSpc_with_ssub_8RegClass,
4859
  &ARM::DQuadSpcRegClass,
4860
  &ARM::DQuadSpc_with_ssub_0RegClass,
4861
  &ARM::DQuadSpc_with_ssub_4RegClass,
4862
  nullptr
4863
};
4864
4865
static const TargetRegisterClass *const DQuadSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4866
  &ARM::DTripleSpcRegClass,
4867
  &ARM::DTripleSpc_with_ssub_0RegClass,
4868
  &ARM::DTripleSpc_with_ssub_4RegClass,
4869
  &ARM::DTripleSpc_with_ssub_8RegClass,
4870
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4871
  &ARM::DQuadSpcRegClass,
4872
  &ARM::DQuadSpc_with_ssub_0RegClass,
4873
  &ARM::DQuadSpc_with_ssub_4RegClass,
4874
  &ARM::DQuadSpc_with_ssub_8RegClass,
4875
  nullptr
4876
};
4877
4878
static const TargetRegisterClass *const DQuadSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4879
  &ARM::DTripleSpcRegClass,
4880
  &ARM::DTripleSpc_with_ssub_0RegClass,
4881
  &ARM::DTripleSpc_with_ssub_4RegClass,
4882
  &ARM::DTripleSpc_with_ssub_8RegClass,
4883
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4884
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4885
  &ARM::DQuadSpcRegClass,
4886
  &ARM::DQuadSpc_with_ssub_0RegClass,
4887
  &ARM::DQuadSpc_with_ssub_4RegClass,
4888
  &ARM::DQuadSpc_with_ssub_8RegClass,
4889
  &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
4890
  nullptr
4891
};
4892
4893
static const TargetRegisterClass *const DQuadSpc_with_dsub_4_in_DPR_8Superclasses[] = {
4894
  &ARM::DTripleSpcRegClass,
4895
  &ARM::DTripleSpc_with_ssub_0RegClass,
4896
  &ARM::DTripleSpc_with_ssub_4RegClass,
4897
  &ARM::DTripleSpc_with_ssub_8RegClass,
4898
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4899
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4900
  &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass,
4901
  &ARM::DQuadSpcRegClass,
4902
  &ARM::DQuadSpc_with_ssub_0RegClass,
4903
  &ARM::DQuadSpc_with_ssub_4RegClass,
4904
  &ARM::DQuadSpc_with_ssub_8RegClass,
4905
  &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
4906
  &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass,
4907
  nullptr
4908
};
4909
4910
static const TargetRegisterClass *const DQuad_with_ssub_0Superclasses[] = {
4911
  &ARM::DQuadRegClass,
4912
  nullptr
4913
};
4914
4915
static const TargetRegisterClass *const DQuad_with_ssub_2Superclasses[] = {
4916
  &ARM::DQuadRegClass,
4917
  &ARM::DQuad_with_ssub_0RegClass,
4918
  nullptr
4919
};
4920
4921
static const TargetRegisterClass *const QQPRSuperclasses[] = {
4922
  &ARM::DQuadRegClass,
4923
  nullptr
4924
};
4925
4926
static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4927
  &ARM::DQuadRegClass,
4928
  nullptr
4929
};
4930
4931
static const TargetRegisterClass *const DQuad_with_ssub_4Superclasses[] = {
4932
  &ARM::DQuadRegClass,
4933
  &ARM::DQuad_with_ssub_0RegClass,
4934
  &ARM::DQuad_with_ssub_2RegClass,
4935
  nullptr
4936
};
4937
4938
static const TargetRegisterClass *const DQuad_with_ssub_6Superclasses[] = {
4939
  &ARM::DQuadRegClass,
4940
  &ARM::DQuad_with_ssub_0RegClass,
4941
  &ARM::DQuad_with_ssub_2RegClass,
4942
  &ARM::DQuad_with_ssub_4RegClass,
4943
  nullptr
4944
};
4945
4946
static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8Superclasses[] = {
4947
  &ARM::DQuadRegClass,
4948
  &ARM::DQuad_with_ssub_0RegClass,
4949
  &ARM::DQuad_with_ssub_2RegClass,
4950
  &ARM::DQuad_with_ssub_4RegClass,
4951
  &ARM::DQuad_with_ssub_6RegClass,
4952
  nullptr
4953
};
4954
4955
static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_VFP2Superclasses[] = {
4956
  &ARM::DQuadRegClass,
4957
  &ARM::DQuad_with_ssub_0RegClass,
4958
  &ARM::DQuad_with_ssub_2RegClass,
4959
  &ARM::QQPRRegClass,
4960
  nullptr
4961
};
4962
4963
static const TargetRegisterClass *const DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4964
  &ARM::DQuadRegClass,
4965
  &ARM::DQuad_with_ssub_0RegClass,
4966
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4967
  nullptr
4968
};
4969
4970
static const TargetRegisterClass *const DQuad_with_dsub_1_in_DPR_8Superclasses[] = {
4971
  &ARM::DQuadRegClass,
4972
  &ARM::DQuad_with_ssub_0RegClass,
4973
  &ARM::DQuad_with_ssub_2RegClass,
4974
  &ARM::DQuad_with_ssub_4RegClass,
4975
  &ARM::DQuad_with_ssub_6RegClass,
4976
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
4977
  nullptr
4978
};
4979
4980
static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_VFP2Superclasses[] = {
4981
  &ARM::DQuadRegClass,
4982
  &ARM::DQuad_with_ssub_0RegClass,
4983
  &ARM::DQuad_with_ssub_2RegClass,
4984
  &ARM::QQPRRegClass,
4985
  &ARM::DQuad_with_ssub_4RegClass,
4986
  &ARM::DQuad_with_ssub_6RegClass,
4987
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
4988
  nullptr
4989
};
4990
4991
static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
4992
  &ARM::DQuadRegClass,
4993
  &ARM::DQuad_with_ssub_0RegClass,
4994
  &ARM::DQuad_with_ssub_2RegClass,
4995
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4996
  &ARM::DQuad_with_ssub_4RegClass,
4997
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4998
  nullptr
4999
};
5000
5001
static const TargetRegisterClass *const DQuad_with_dsub_2_in_DPR_8Superclasses[] = {
5002
  &ARM::DQuadRegClass,
5003
  &ARM::DQuad_with_ssub_0RegClass,
5004
  &ARM::DQuad_with_ssub_2RegClass,
5005
  &ARM::DQuad_with_ssub_4RegClass,
5006
  &ARM::DQuad_with_ssub_6RegClass,
5007
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5008
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5009
  nullptr
5010
};
5011
5012
static const TargetRegisterClass *const DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5013
  &ARM::DQuadRegClass,
5014
  &ARM::DQuad_with_ssub_0RegClass,
5015
  &ARM::DQuad_with_ssub_2RegClass,
5016
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5017
  &ARM::DQuad_with_ssub_4RegClass,
5018
  &ARM::DQuad_with_ssub_6RegClass,
5019
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5020
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5021
  nullptr
5022
};
5023
5024
static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8Superclasses[] = {
5025
  &ARM::DQuadRegClass,
5026
  &ARM::DQuad_with_ssub_0RegClass,
5027
  &ARM::DQuad_with_ssub_2RegClass,
5028
  &ARM::DQuad_with_ssub_4RegClass,
5029
  &ARM::DQuad_with_ssub_6RegClass,
5030
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5031
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5032
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5033
  nullptr
5034
};
5035
5036
static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5037
  &ARM::DQuadRegClass,
5038
  &ARM::DQuad_with_ssub_0RegClass,
5039
  &ARM::DQuad_with_ssub_2RegClass,
5040
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5041
  &ARM::DQuad_with_ssub_4RegClass,
5042
  &ARM::DQuad_with_ssub_6RegClass,
5043
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5044
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5045
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5046
  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5047
  nullptr
5048
};
5049
5050
static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_8Superclasses[] = {
5051
  &ARM::DQuadRegClass,
5052
  &ARM::DQuad_with_ssub_0RegClass,
5053
  &ARM::DQuad_with_ssub_2RegClass,
5054
  &ARM::QQPRRegClass,
5055
  &ARM::DQuad_with_ssub_4RegClass,
5056
  &ARM::DQuad_with_ssub_6RegClass,
5057
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5058
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
5059
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5060
  &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
5061
  nullptr
5062
};
5063
5064
static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_8Superclasses[] = {
5065
  &ARM::DQuadRegClass,
5066
  &ARM::DQuad_with_ssub_0RegClass,
5067
  &ARM::DQuad_with_ssub_2RegClass,
5068
  &ARM::QQPRRegClass,
5069
  &ARM::DQuad_with_ssub_4RegClass,
5070
  &ARM::DQuad_with_ssub_6RegClass,
5071
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5072
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
5073
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5074
  &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
5075
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5076
  &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
5077
  &ARM::DQuad_with_qsub_0_in_QPR_8RegClass,
5078
  nullptr
5079
};
5080
5081
static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
5082
  &ARM::DQuadRegClass,
5083
  &ARM::DQuad_with_ssub_0RegClass,
5084
  &ARM::DQuad_with_ssub_2RegClass,
5085
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5086
  &ARM::DQuad_with_ssub_4RegClass,
5087
  &ARM::DQuad_with_ssub_6RegClass,
5088
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5089
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5090
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5091
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5092
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5093
  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5094
  &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5095
  nullptr
5096
};
5097
5098
static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5099
  &ARM::DQuadRegClass,
5100
  &ARM::DQuad_with_ssub_0RegClass,
5101
  &ARM::DQuad_with_ssub_2RegClass,
5102
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5103
  &ARM::DQuad_with_ssub_4RegClass,
5104
  &ARM::DQuad_with_ssub_6RegClass,
5105
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5106
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5107
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5108
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5109
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5110
  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5111
  &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
5112
  &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5113
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
5114
  nullptr
5115
};
5116
5117
static const TargetRegisterClass *const QQQQPR_with_ssub_0Superclasses[] = {
5118
  &ARM::QQQQPRRegClass,
5119
  nullptr
5120
};
5121
5122
static const TargetRegisterClass *const QQQQPR_with_ssub_4Superclasses[] = {
5123
  &ARM::QQQQPRRegClass,
5124
  &ARM::QQQQPR_with_ssub_0RegClass,
5125
  nullptr
5126
};
5127
5128
static const TargetRegisterClass *const QQQQPR_with_ssub_8Superclasses[] = {
5129
  &ARM::QQQQPRRegClass,
5130
  &ARM::QQQQPR_with_ssub_0RegClass,
5131
  &ARM::QQQQPR_with_ssub_4RegClass,
5132
  nullptr
5133
};
5134
5135
static const TargetRegisterClass *const QQQQPR_with_ssub_12Superclasses[] = {
5136
  &ARM::QQQQPRRegClass,
5137
  &ARM::QQQQPR_with_ssub_0RegClass,
5138
  &ARM::QQQQPR_with_ssub_4RegClass,
5139
  &ARM::QQQQPR_with_ssub_8RegClass,
5140
  nullptr
5141
};
5142
5143
static const TargetRegisterClass *const QQQQPR_with_dsub_0_in_DPR_8Superclasses[] = {
5144
  &ARM::QQQQPRRegClass,
5145
  &ARM::QQQQPR_with_ssub_0RegClass,
5146
  &ARM::QQQQPR_with_ssub_4RegClass,
5147
  &ARM::QQQQPR_with_ssub_8RegClass,
5148
  &ARM::QQQQPR_with_ssub_12RegClass,
5149
  nullptr
5150
};
5151
5152
static const TargetRegisterClass *const QQQQPR_with_dsub_2_in_DPR_8Superclasses[] = {
5153
  &ARM::QQQQPRRegClass,
5154
  &ARM::QQQQPR_with_ssub_0RegClass,
5155
  &ARM::QQQQPR_with_ssub_4RegClass,
5156
  &ARM::QQQQPR_with_ssub_8RegClass,
5157
  &ARM::QQQQPR_with_ssub_12RegClass,
5158
  &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
5159
  nullptr
5160
};
5161
5162
static const TargetRegisterClass *const QQQQPR_with_dsub_4_in_DPR_8Superclasses[] = {
5163
  &ARM::QQQQPRRegClass,
5164
  &ARM::QQQQPR_with_ssub_0RegClass,
5165
  &ARM::QQQQPR_with_ssub_4RegClass,
5166
  &ARM::QQQQPR_with_ssub_8RegClass,
5167
  &ARM::QQQQPR_with_ssub_12RegClass,
5168
  &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
5169
  &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
5170
  nullptr
5171
};
5172
5173
static const TargetRegisterClass *const QQQQPR_with_dsub_6_in_DPR_8Superclasses[] = {
5174
  &ARM::QQQQPRRegClass,
5175
  &ARM::QQQQPR_with_ssub_0RegClass,
5176
  &ARM::QQQQPR_with_ssub_4RegClass,
5177
  &ARM::QQQQPR_with_ssub_8RegClass,
5178
  &ARM::QQQQPR_with_ssub_12RegClass,
5179
  &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
5180
  &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
5181
  &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass,
5182
  nullptr
5183
};
5184
5185
5186
764
static inline unsigned SPRAltOrderSelect(const MachineFunction &MF) {
5187
764
    return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
5188
764
  }
5189
5190
764
static ArrayRef<MCPhysReg> SPRGetRawAllocationOrder(const MachineFunction &MF) {
5191
764
  static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 };
5192
764
  static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 };
5193
764
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::SPRRegClassID];
5194
764
  const ArrayRef<MCPhysReg> Order[] = {
5195
764
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5196
764
    makeArrayRef(AltOrder1),
5197
764
    makeArrayRef(AltOrder2)
5198
764
  };
5199
764
  const unsigned Select = SPRAltOrderSelect(MF);
5200
764
  assert(Select < 3);
5201
764
  return Order[Select];
5202
764
}
5203
5204
6.97k
static inline unsigned GPRAltOrderSelect(const MachineFunction &MF) {
5205
6.97k
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5206
6.97k
  }
5207
5208
6.97k
static ArrayRef<MCPhysReg> GPRGetRawAllocationOrder(const MachineFunction &MF) {
5209
6.97k
  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC };
5210
6.97k
  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5211
6.97k
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRRegClassID];
5212
6.97k
  const ArrayRef<MCPhysReg> Order[] = {
5213
6.97k
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5214
6.97k
    makeArrayRef(AltOrder1),
5215
6.97k
    makeArrayRef(AltOrder2)
5216
6.97k
  };
5217
6.97k
  const unsigned Select = GPRAltOrderSelect(MF);
5218
6.97k
  assert(Select < 3);
5219
6.97k
  return Order[Select];
5220
6.97k
}
5221
5222
0
static inline unsigned GPRwithAPSRAltOrderSelect(const MachineFunction &MF) {
5223
0
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5224
0
  }
5225
5226
0
static ArrayRef<MCPhysReg> GPRwithAPSRGetRawAllocationOrder(const MachineFunction &MF) {
5227
0
  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5228
0
  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5229
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithAPSRRegClassID];
5230
0
  const ArrayRef<MCPhysReg> Order[] = {
5231
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5232
0
    makeArrayRef(AltOrder1),
5233
0
    makeArrayRef(AltOrder2)
5234
0
  };
5235
0
  const unsigned Select = GPRwithAPSRAltOrderSelect(MF);
5236
0
  assert(Select < 3);
5237
0
  return Order[Select];
5238
0
}
5239
5240
2.12k
static inline unsigned GPRnopcAltOrderSelect(const MachineFunction &MF) {
5241
2.12k
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5242
2.12k
  }
5243
5244
2.12k
static ArrayRef<MCPhysReg> GPRnopcGetRawAllocationOrder(const MachineFunction &MF) {
5245
2.12k
  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5246
2.12k
  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5247
2.12k
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRnopcRegClassID];
5248
2.12k
  const ArrayRef<MCPhysReg> Order[] = {
5249
2.12k
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5250
2.12k
    makeArrayRef(AltOrder1),
5251
2.12k
    makeArrayRef(AltOrder2)
5252
2.12k
  };
5253
2.12k
  const unsigned Select = GPRnopcAltOrderSelect(MF);
5254
2.12k
  assert(Select < 3);
5255
2.12k
  return Order[Select];
5256
2.12k
}
5257
5258
3.13k
static inline unsigned rGPRAltOrderSelect(const MachineFunction &MF) {
5259
3.13k
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5260
3.13k
  }
5261
5262
3.13k
static ArrayRef<MCPhysReg> rGPRGetRawAllocationOrder(const MachineFunction &MF) {
5263
3.13k
  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12 };
5264
3.13k
  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5265
3.13k
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::rGPRRegClassID];
5266
3.13k
  const ArrayRef<MCPhysReg> Order[] = {
5267
3.13k
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5268
3.13k
    makeArrayRef(AltOrder1),
5269
3.13k
    makeArrayRef(AltOrder2)
5270
3.13k
  };
5271
3.13k
  const unsigned Select = rGPRAltOrderSelect(MF);
5272
3.13k
  assert(Select < 3);
5273
3.13k
  return Order[Select];
5274
3.13k
}
5275
5276
38
static inline unsigned tcGPRAltOrderSelect(const MachineFunction &MF) {
5277
38
      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5278
38
  }
5279
5280
38
static ArrayRef<MCPhysReg> tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
5281
38
  static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
5282
38
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tcGPRRegClassID];
5283
38
  const ArrayRef<MCPhysReg> Order[] = {
5284
38
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5285
38
    makeArrayRef(AltOrder1)
5286
38
  };
5287
38
  const unsigned Select = tcGPRAltOrderSelect(MF);
5288
38
  assert(Select < 2);
5289
38
  return Order[Select];
5290
38
}
5291
5292
0
static inline unsigned tGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) {
5293
0
      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5294
0
  }
5295
5296
0
static ArrayRef<MCPhysReg> tGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
5297
0
  static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
5298
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tcGPRRegClassID];
5299
0
  const ArrayRef<MCPhysReg> Order[] = {
5300
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5301
0
    makeArrayRef(AltOrder1)
5302
0
  };
5303
0
  const unsigned Select = tGPR_and_tcGPRAltOrderSelect(MF);
5304
0
  assert(Select < 2);
5305
0
  return Order[Select];
5306
0
}
5307
5308
0
static inline unsigned hGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) {
5309
0
      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5310
0
  }
5311
5312
0
static ArrayRef<MCPhysReg> hGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
5313
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::hGPR_and_tcGPRRegClassID];
5314
0
  const ArrayRef<MCPhysReg> Order[] = {
5315
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5316
0
    ArrayRef<MCPhysReg>()
5317
0
  };
5318
0
  const unsigned Select = hGPR_and_tcGPRAltOrderSelect(MF);
5319
0
  assert(Select < 2);
5320
0
  return Order[Select];
5321
0
}
5322
5323
1.13k
static inline unsigned DPRAltOrderSelect(const MachineFunction &MF) {
5324
1.13k
    return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
5325
1.13k
  }
5326
5327
1.13k
static ArrayRef<MCPhysReg> DPRGetRawAllocationOrder(const MachineFunction &MF) {
5328
1.13k
  static const MCPhysReg AltOrder1[] = { ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
5329
1.13k
  static const MCPhysReg AltOrder2[] = { ARM::D16, ARM::D18, ARM::D20, ARM::D22, ARM::D24, ARM::D26, ARM::D28, ARM::D30, ARM::D0, ARM::D2, ARM::D4, ARM::D6, ARM::D8, ARM::D10, ARM::D12, ARM::D14, ARM::D17, ARM::D19, ARM::D21, ARM::D23, ARM::D25, ARM::D27, ARM::D29, ARM::D31, ARM::D1, ARM::D3, ARM::D5, ARM::D7, ARM::D9, ARM::D11, ARM::D13, ARM::D15 };
5330
1.13k
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPRRegClassID];
5331
1.13k
  const ArrayRef<MCPhysReg> Order[] = {
5332
1.13k
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5333
1.13k
    makeArrayRef(AltOrder1),
5334
1.13k
    makeArrayRef(AltOrder2)
5335
1.13k
  };
5336
1.13k
  const unsigned Select = DPRAltOrderSelect(MF);
5337
1.13k
  assert(Select < 3);
5338
1.13k
  return Order[Select];
5339
1.13k
}
5340
5341
211
static inline unsigned DPairAltOrderSelect(const MachineFunction &MF) { return 1; }
5342
5343
211
static ArrayRef<MCPhysReg> DPairGetRawAllocationOrder(const MachineFunction &MF) {
5344
211
  static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D17_D18, ARM::D19_D20, ARM::D21_D22, ARM::D23_D24, ARM::D25_D26, ARM::D27_D28, ARM::D29_D30, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
5345
211
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPairRegClassID];
5346
211
  const ArrayRef<MCPhysReg> Order[] = {
5347
211
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5348
211
    makeArrayRef(AltOrder1)
5349
211
  };
5350
211
  const unsigned Select = DPairAltOrderSelect(MF);
5351
211
  assert(Select < 2);
5352
211
  return Order[Select];
5353
211
}
5354
5355
171
static inline unsigned DPair_with_ssub_0AltOrderSelect(const MachineFunction &MF) { return 1; }
5356
5357
171
static ArrayRef<MCPhysReg> DPair_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) {
5358
171
  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
5359
171
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_0RegClassID];
5360
171
  const ArrayRef<MCPhysReg> Order[] = {
5361
171
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5362
171
    makeArrayRef(AltOrder1)
5363
171
  };
5364
171
  const unsigned Select = DPair_with_ssub_0AltOrderSelect(MF);
5365
171
  assert(Select < 2);
5366
171
  return Order[Select];
5367
171
}
5368
5369
403
static inline unsigned QPRAltOrderSelect(const MachineFunction &MF) { return 1; }
5370
5371
403
static ArrayRef<MCPhysReg> QPRGetRawAllocationOrder(const MachineFunction &MF) {
5372
403
  static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 };
5373
403
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QPRRegClassID];
5374
403
  const ArrayRef<MCPhysReg> Order[] = {
5375
403
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5376
403
    makeArrayRef(AltOrder1)
5377
403
  };
5378
403
  const unsigned Select = QPRAltOrderSelect(MF);
5379
403
  assert(Select < 2);
5380
403
  return Order[Select];
5381
403
}
5382
5383
0
static inline unsigned DPair_with_ssub_2AltOrderSelect(const MachineFunction &MF) { return 1; }
5384
5385
0
static ArrayRef<MCPhysReg> DPair_with_ssub_2GetRawAllocationOrder(const MachineFunction &MF) {
5386
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14 };
5387
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_2RegClassID];
5388
0
  const ArrayRef<MCPhysReg> Order[] = {
5389
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5390
0
    makeArrayRef(AltOrder1)
5391
0
  };
5392
0
  const unsigned Select = DPair_with_ssub_2AltOrderSelect(MF);
5393
0
  assert(Select < 2);
5394
0
  return Order[Select];
5395
0
}
5396
5397
6
static inline unsigned DPair_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5398
5399
6
static ArrayRef<MCPhysReg> DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5400
6
  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8 };
5401
6
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_0_in_DPR_8RegClassID];
5402
6
  const ArrayRef<MCPhysReg> Order[] = {
5403
6
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5404
6
    makeArrayRef(AltOrder1)
5405
6
  };
5406
6
  const unsigned Select = DPair_with_dsub_0_in_DPR_8AltOrderSelect(MF);
5407
6
  assert(Select < 2);
5408
6
  return Order[Select];
5409
6
}
5410
5411
0
static inline unsigned DPair_with_dsub_1_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5412
5413
0
static ArrayRef<MCPhysReg> DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5414
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6 };
5415
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_1_in_DPR_8RegClassID];
5416
0
  const ArrayRef<MCPhysReg> Order[] = {
5417
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5418
0
    makeArrayRef(AltOrder1)
5419
0
  };
5420
0
  const unsigned Select = DPair_with_dsub_1_in_DPR_8AltOrderSelect(MF);
5421
0
  assert(Select < 2);
5422
0
  return Order[Select];
5423
0
}
5424
5425
38
static inline unsigned QQPRAltOrderSelect(const MachineFunction &MF) { return 1; }
5426
5427
38
static ArrayRef<MCPhysReg> QQPRGetRawAllocationOrder(const MachineFunction &MF) {
5428
38
  static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 };
5429
38
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQPRRegClassID];
5430
38
  const ArrayRef<MCPhysReg> Order[] = {
5431
38
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5432
38
    makeArrayRef(AltOrder1)
5433
38
  };
5434
38
  const unsigned Select = QQPRAltOrderSelect(MF);
5435
38
  assert(Select < 2);
5436
38
  return Order[Select];
5437
38
}
5438
5439
0
static inline unsigned DQuad_with_qsub_0_in_QPR_VFP2AltOrderSelect(const MachineFunction &MF) { return 1; }
5440
5441
0
static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_QPR_VFP2GetRawAllocationOrder(const MachineFunction &MF) {
5442
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 };
5443
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClassID];
5444
0
  const ArrayRef<MCPhysReg> Order[] = {
5445
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5446
0
    makeArrayRef(AltOrder1)
5447
0
  };
5448
0
  const unsigned Select = DQuad_with_qsub_0_in_QPR_VFP2AltOrderSelect(MF);
5449
0
  assert(Select < 2);
5450
0
  return Order[Select];
5451
0
}
5452
5453
0
static inline unsigned DQuad_with_qsub_1_in_QPR_VFP2AltOrderSelect(const MachineFunction &MF) { return 1; }
5454
5455
0
static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_QPR_VFP2GetRawAllocationOrder(const MachineFunction &MF) {
5456
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 };
5457
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID];
5458
0
  const ArrayRef<MCPhysReg> Order[] = {
5459
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5460
0
    makeArrayRef(AltOrder1)
5461
0
  };
5462
0
  const unsigned Select = DQuad_with_qsub_1_in_QPR_VFP2AltOrderSelect(MF);
5463
0
  assert(Select < 2);
5464
0
  return Order[Select];
5465
0
}
5466
5467
0
static inline unsigned DQuad_with_qsub_0_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5468
5469
0
static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5470
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4 };
5471
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_QPR_8RegClassID];
5472
0
  const ArrayRef<MCPhysReg> Order[] = {
5473
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5474
0
    makeArrayRef(AltOrder1)
5475
0
  };
5476
0
  const unsigned Select = DQuad_with_qsub_0_in_QPR_8AltOrderSelect(MF);
5477
0
  assert(Select < 2);
5478
0
  return Order[Select];
5479
0
}
5480
5481
0
static inline unsigned DQuad_with_qsub_1_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5482
5483
0
static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5484
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3 };
5485
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_QPR_8RegClassID];
5486
0
  const ArrayRef<MCPhysReg> Order[] = {
5487
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5488
0
    makeArrayRef(AltOrder1)
5489
0
  };
5490
0
  const unsigned Select = DQuad_with_qsub_1_in_QPR_8AltOrderSelect(MF);
5491
0
  assert(Select < 2);
5492
0
  return Order[Select];
5493
0
}
5494
5495
193
static inline unsigned QQQQPRAltOrderSelect(const MachineFunction &MF) { return 1; }
5496
5497
193
static ArrayRef<MCPhysReg> QQQQPRGetRawAllocationOrder(const MachineFunction &MF) {
5498
193
  static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 };
5499
193
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPRRegClassID];
5500
193
  const ArrayRef<MCPhysReg> Order[] = {
5501
193
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5502
193
    makeArrayRef(AltOrder1)
5503
193
  };
5504
193
  const unsigned Select = QQQQPRAltOrderSelect(MF);
5505
193
  assert(Select < 2);
5506
193
  return Order[Select];
5507
193
}
5508
5509
162
static inline unsigned QQQQPR_with_ssub_0AltOrderSelect(const MachineFunction &MF) { return 1; }
5510
5511
162
static ArrayRef<MCPhysReg> QQQQPR_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) {
5512
162
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 };
5513
162
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_0RegClassID];
5514
162
  const ArrayRef<MCPhysReg> Order[] = {
5515
162
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5516
162
    makeArrayRef(AltOrder1)
5517
162
  };
5518
162
  const unsigned Select = QQQQPR_with_ssub_0AltOrderSelect(MF);
5519
162
  assert(Select < 2);
5520
162
  return Order[Select];
5521
162
}
5522
5523
0
static inline unsigned QQQQPR_with_ssub_4AltOrderSelect(const MachineFunction &MF) { return 1; }
5524
5525
0
static ArrayRef<MCPhysReg> QQQQPR_with_ssub_4GetRawAllocationOrder(const MachineFunction &MF) {
5526
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9 };
5527
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_4RegClassID];
5528
0
  const ArrayRef<MCPhysReg> Order[] = {
5529
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5530
0
    makeArrayRef(AltOrder1)
5531
0
  };
5532
0
  const unsigned Select = QQQQPR_with_ssub_4AltOrderSelect(MF);
5533
0
  assert(Select < 2);
5534
0
  return Order[Select];
5535
0
}
5536
5537
0
static inline unsigned QQQQPR_with_ssub_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5538
5539
0
static ArrayRef<MCPhysReg> QQQQPR_with_ssub_8GetRawAllocationOrder(const MachineFunction &MF) {
5540
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8 };
5541
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_8RegClassID];
5542
0
  const ArrayRef<MCPhysReg> Order[] = {
5543
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5544
0
    makeArrayRef(AltOrder1)
5545
0
  };
5546
0
  const unsigned Select = QQQQPR_with_ssub_8AltOrderSelect(MF);
5547
0
  assert(Select < 2);
5548
0
  return Order[Select];
5549
0
}
5550
5551
3
static inline unsigned QQQQPR_with_ssub_12AltOrderSelect(const MachineFunction &MF) { return 1; }
5552
5553
3
static ArrayRef<MCPhysReg> QQQQPR_with_ssub_12GetRawAllocationOrder(const MachineFunction &MF) {
5554
3
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 };
5555
3
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_12RegClassID];
5556
3
  const ArrayRef<MCPhysReg> Order[] = {
5557
3
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5558
3
    makeArrayRef(AltOrder1)
5559
3
  };
5560
3
  const unsigned Select = QQQQPR_with_ssub_12AltOrderSelect(MF);
5561
3
  assert(Select < 2);
5562
3
  return Order[Select];
5563
3
}
5564
5565
0
static inline unsigned QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5566
5567
0
static ArrayRef<MCPhysReg> QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5568
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6 };
5569
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID];
5570
0
  const ArrayRef<MCPhysReg> Order[] = {
5571
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5572
0
    makeArrayRef(AltOrder1)
5573
0
  };
5574
0
  const unsigned Select = QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(MF);
5575
0
  assert(Select < 2);
5576
0
  return Order[Select];
5577
0
}
5578
5579
0
static inline unsigned QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5580
5581
0
static ArrayRef<MCPhysReg> QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5582
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5 };
5583
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID];
5584
0
  const ArrayRef<MCPhysReg> Order[] = {
5585
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5586
0
    makeArrayRef(AltOrder1)
5587
0
  };
5588
0
  const unsigned Select = QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(MF);
5589
0
  assert(Select < 2);
5590
0
  return Order[Select];
5591
0
}
5592
5593
0
static inline unsigned QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5594
5595
0
static ArrayRef<MCPhysReg> QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5596
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4 };
5597
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID];
5598
0
  const ArrayRef<MCPhysReg> Order[] = {
5599
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5600
0
    makeArrayRef(AltOrder1)
5601
0
  };
5602
0
  const unsigned Select = QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(MF);
5603
0
  assert(Select < 2);
5604
0
  return Order[Select];
5605
0
}
5606
5607
0
static inline unsigned QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5608
5609
0
static ArrayRef<MCPhysReg> QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5610
0
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3 };
5611
0
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID];
5612
0
  const ArrayRef<MCPhysReg> Order[] = {
5613
0
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5614
0
    makeArrayRef(AltOrder1)
5615
0
  };
5616
0
  const unsigned Select = QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(MF);
5617
0
  assert(Select < 2);
5618
0
  return Order[Select];
5619
0
}
5620
5621
namespace ARM {   // Register class instances
5622
  extern const TargetRegisterClass SPRRegClass = {
5623
    &ARMMCRegisterClasses[SPRRegClassID],
5624
    SPRSubClassMask,
5625
    SuperRegIdxSeqs + 14,
5626
    LaneBitmask(0x00000001),
5627
    0,
5628
    false, /* HasDisjunctSubRegs */
5629
    false, /* CoveredBySubRegs */
5630
    NullRegClasses,
5631
    SPRGetRawAllocationOrder
5632
  };
5633
5634
  extern const TargetRegisterClass GPRRegClass = {
5635
    &ARMMCRegisterClasses[GPRRegClassID],
5636
    GPRSubClassMask,
5637
    SuperRegIdxSeqs + 11,
5638
    LaneBitmask(0x00000001),
5639
    0,
5640
    false, /* HasDisjunctSubRegs */
5641
    true, /* CoveredBySubRegs */
5642
    NullRegClasses,
5643
    GPRGetRawAllocationOrder
5644
  };
5645
5646
  extern const TargetRegisterClass GPRwithAPSRRegClass = {
5647
    &ARMMCRegisterClasses[GPRwithAPSRRegClassID],
5648
    GPRwithAPSRSubClassMask,
5649
    SuperRegIdxSeqs + 11,
5650
    LaneBitmask(0x00000001),
5651
    0,
5652
    false, /* HasDisjunctSubRegs */
5653
    true, /* CoveredBySubRegs */
5654
    NullRegClasses,
5655
    GPRwithAPSRGetRawAllocationOrder
5656
  };
5657
5658
  extern const TargetRegisterClass SPR_8RegClass = {
5659
    &ARMMCRegisterClasses[SPR_8RegClassID],
5660
    SPR_8SubClassMask,
5661
    SuperRegIdxSeqs + 14,
5662
    LaneBitmask(0x00000001),
5663
    0,
5664
    false, /* HasDisjunctSubRegs */
5665
    false, /* CoveredBySubRegs */
5666
    SPR_8Superclasses,
5667
    nullptr
5668
  };
5669
5670
  extern const TargetRegisterClass GPRnopcRegClass = {
5671
    &ARMMCRegisterClasses[GPRnopcRegClassID],
5672
    GPRnopcSubClassMask,
5673
    SuperRegIdxSeqs + 11,
5674
    LaneBitmask(0x00000001),
5675
    0,
5676
    false, /* HasDisjunctSubRegs */
5677
    true, /* CoveredBySubRegs */
5678
    GPRnopcSuperclasses,
5679
    GPRnopcGetRawAllocationOrder
5680
  };
5681
5682
  extern const TargetRegisterClass rGPRRegClass = {
5683
    &ARMMCRegisterClasses[rGPRRegClassID],
5684
    rGPRSubClassMask,
5685
    SuperRegIdxSeqs + 11,
5686
    LaneBitmask(0x00000001),
5687
    0,
5688
    false, /* HasDisjunctSubRegs */
5689
    true, /* CoveredBySubRegs */
5690
    rGPRSuperclasses,
5691
    rGPRGetRawAllocationOrder
5692
  };
5693
5694
  extern const TargetRegisterClass tGPRwithpcRegClass = {
5695
    &ARMMCRegisterClasses[tGPRwithpcRegClassID],
5696
    tGPRwithpcSubClassMask,
5697
    SuperRegIdxSeqs + 11,
5698
    LaneBitmask(0x00000001),
5699
    0,
5700
    false, /* HasDisjunctSubRegs */
5701
    true, /* CoveredBySubRegs */
5702
    tGPRwithpcSuperclasses,
5703
    nullptr
5704
  };
5705
5706
  extern const TargetRegisterClass hGPRRegClass = {
5707
    &ARMMCRegisterClasses[hGPRRegClassID],
5708
    hGPRSubClassMask,
5709
    SuperRegIdxSeqs + 11,
5710
    LaneBitmask(0x00000001),
5711
    0,
5712
    false, /* HasDisjunctSubRegs */
5713
    true, /* CoveredBySubRegs */
5714
    hGPRSuperclasses,
5715
    nullptr
5716
  };
5717
5718
  extern const TargetRegisterClass tGPRRegClass = {
5719
    &ARMMCRegisterClasses[tGPRRegClassID],
5720
    tGPRSubClassMask,
5721
    SuperRegIdxSeqs + 11,
5722
    LaneBitmask(0x00000001),
5723
    0,
5724
    false, /* HasDisjunctSubRegs */
5725
    true, /* CoveredBySubRegs */
5726
    tGPRSuperclasses,
5727
    nullptr
5728
  };
5729
5730
  extern const TargetRegisterClass GPRnopc_and_hGPRRegClass = {
5731
    &ARMMCRegisterClasses[GPRnopc_and_hGPRRegClassID],
5732
    GPRnopc_and_hGPRSubClassMask,
5733
    SuperRegIdxSeqs + 11,
5734
    LaneBitmask(0x00000001),
5735
    0,
5736
    false, /* HasDisjunctSubRegs */
5737
    true, /* CoveredBySubRegs */
5738
    GPRnopc_and_hGPRSuperclasses,
5739
    nullptr
5740
  };
5741
5742
  extern const TargetRegisterClass hGPR_and_rGPRRegClass = {
5743
    &ARMMCRegisterClasses[hGPR_and_rGPRRegClassID],
5744
    hGPR_and_rGPRSubClassMask,
5745
    SuperRegIdxSeqs + 11,
5746
    LaneBitmask(0x00000001),
5747
    0,
5748
    false, /* HasDisjunctSubRegs */
5749
    true, /* CoveredBySubRegs */
5750
    hGPR_and_rGPRSuperclasses,
5751
    nullptr
5752
  };
5753
5754
  extern const TargetRegisterClass tcGPRRegClass = {
5755
    &ARMMCRegisterClasses[tcGPRRegClassID],
5756
    tcGPRSubClassMask,
5757
    SuperRegIdxSeqs + 11,
5758
    LaneBitmask(0x00000001),
5759
    0,
5760
    false, /* HasDisjunctSubRegs */
5761
    true, /* CoveredBySubRegs */
5762
    tcGPRSuperclasses,
5763
    tcGPRGetRawAllocationOrder
5764
  };
5765
5766
  extern const TargetRegisterClass tGPR_and_tcGPRRegClass = {
5767
    &ARMMCRegisterClasses[tGPR_and_tcGPRRegClassID],
5768
    tGPR_and_tcGPRSubClassMask,
5769
    SuperRegIdxSeqs + 11,
5770
    LaneBitmask(0x00000001),
5771
    0,
5772
    false, /* HasDisjunctSubRegs */
5773
    true, /* CoveredBySubRegs */
5774
    tGPR_and_tcGPRSuperclasses,
5775
    tGPR_and_tcGPRGetRawAllocationOrder
5776
  };
5777
5778
  extern const TargetRegisterClass CCRRegClass = {
5779
    &ARMMCRegisterClasses[CCRRegClassID],
5780
    CCRSubClassMask,
5781
    SuperRegIdxSeqs + 8,
5782
    LaneBitmask(0x00000001),
5783
    0,
5784
    false, /* HasDisjunctSubRegs */
5785
    true, /* CoveredBySubRegs */
5786
    NullRegClasses,
5787
    nullptr
5788
  };
5789
5790
  extern const TargetRegisterClass GPRspRegClass = {
5791
    &ARMMCRegisterClasses[GPRspRegClassID],
5792
    GPRspSubClassMask,
5793
    SuperRegIdxSeqs + 12,
5794
    LaneBitmask(0x00000001),
5795
    0,
5796
    false, /* HasDisjunctSubRegs */
5797
    true, /* CoveredBySubRegs */
5798
    GPRspSuperclasses,
5799
    nullptr
5800
  };
5801
5802
  extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass = {
5803
    &ARMMCRegisterClasses[hGPR_and_tGPRwithpcRegClassID],
5804
    hGPR_and_tGPRwithpcSubClassMask,
5805
    SuperRegIdxSeqs + 8,
5806
    LaneBitmask(0x00000001),
5807
    0,
5808
    false, /* HasDisjunctSubRegs */
5809
    true, /* CoveredBySubRegs */
5810
    hGPR_and_tGPRwithpcSuperclasses,
5811
    nullptr
5812
  };
5813
5814
  extern const TargetRegisterClass hGPR_and_tcGPRRegClass = {
5815
    &ARMMCRegisterClasses[hGPR_and_tcGPRRegClassID],
5816
    hGPR_and_tcGPRSubClassMask,
5817
    SuperRegIdxSeqs + 9,
5818
    LaneBitmask(0x00000001),
5819
    0,
5820
    false, /* HasDisjunctSubRegs */
5821
    true, /* CoveredBySubRegs */
5822
    hGPR_and_tcGPRSuperclasses,
5823
    hGPR_and_tcGPRGetRawAllocationOrder
5824
  };
5825
5826
  extern const TargetRegisterClass DPRRegClass = {
5827
    &ARMMCRegisterClasses[DPRRegClassID],
5828
    DPRSubClassMask,
5829
    SuperRegIdxSeqs + 0,
5830
    LaneBitmask(0x0000000C),
5831
    0,
5832
    true, /* HasDisjunctSubRegs */
5833
    false, /* CoveredBySubRegs */
5834
    NullRegClasses,
5835
    DPRGetRawAllocationOrder
5836
  };
5837
5838
  extern const TargetRegisterClass DPR_VFP2RegClass = {
5839
    &ARMMCRegisterClasses[DPR_VFP2RegClassID],
5840
    DPR_VFP2SubClassMask,
5841
    SuperRegIdxSeqs + 0,
5842
    LaneBitmask(0x0000000C),
5843
    0,
5844
    true, /* HasDisjunctSubRegs */
5845
    true, /* CoveredBySubRegs */
5846
    DPR_VFP2Superclasses,
5847
    nullptr
5848
  };
5849
5850
  extern const TargetRegisterClass DPR_8RegClass = {
5851
    &ARMMCRegisterClasses[DPR_8RegClassID],
5852
    DPR_8SubClassMask,
5853
    SuperRegIdxSeqs + 0,
5854
    LaneBitmask(0x0000000C),
5855
    0,
5856
    true, /* HasDisjunctSubRegs */
5857
    true, /* CoveredBySubRegs */
5858
    DPR_8Superclasses,
5859
    nullptr
5860
  };
5861
5862
  extern const TargetRegisterClass GPRPairRegClass = {
5863
    &ARMMCRegisterClasses[GPRPairRegClassID],
5864
    GPRPairSubClassMask,
5865
    SuperRegIdxSeqs + 8,
5866
    LaneBitmask(0x00000003),
5867
    0,
5868
    true, /* HasDisjunctSubRegs */
5869
    true, /* CoveredBySubRegs */
5870
    NullRegClasses,
5871
    nullptr
5872
  };
5873
5874
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_rGPRRegClass = {
5875
    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_rGPRRegClassID],
5876
    GPRPair_with_gsub_1_in_rGPRSubClassMask,
5877
    SuperRegIdxSeqs + 8,
5878
    LaneBitmask(0x00000003),
5879
    0,
5880
    true, /* HasDisjunctSubRegs */
5881
    true, /* CoveredBySubRegs */
5882
    GPRPair_with_gsub_1_in_rGPRSuperclasses,
5883
    nullptr
5884
  };
5885
5886
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass = {
5887
    &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tGPRRegClassID],
5888
    GPRPair_with_gsub_0_in_tGPRSubClassMask,
5889
    SuperRegIdxSeqs + 8,
5890
    LaneBitmask(0x00000003),
5891
    0,
5892
    true, /* HasDisjunctSubRegs */
5893
    true, /* CoveredBySubRegs */
5894
    GPRPair_with_gsub_0_in_tGPRSuperclasses,
5895
    nullptr
5896
  };
5897
5898
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass = {
5899
    &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_hGPRRegClassID],
5900
    GPRPair_with_gsub_0_in_hGPRSubClassMask,
5901
    SuperRegIdxSeqs + 8,
5902
    LaneBitmask(0x00000003),
5903
    0,
5904
    true, /* HasDisjunctSubRegs */
5905
    true, /* CoveredBySubRegs */
5906
    GPRPair_with_gsub_0_in_hGPRSuperclasses,
5907
    nullptr
5908
  };
5909
5910
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass = {
5911
    &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tcGPRRegClassID],
5912
    GPRPair_with_gsub_0_in_tcGPRSubClassMask,
5913
    SuperRegIdxSeqs + 8,
5914
    LaneBitmask(0x00000003),
5915
    0,
5916
    true, /* HasDisjunctSubRegs */
5917
    true, /* CoveredBySubRegs */
5918
    GPRPair_with_gsub_0_in_tcGPRSuperclasses,
5919
    nullptr
5920
  };
5921
5922
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass = {
5923
    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID],
5924
    GPRPair_with_gsub_1_in_hGPR_and_rGPRSubClassMask,
5925
    SuperRegIdxSeqs + 8,
5926
    LaneBitmask(0x00000003),
5927
    0,
5928
    true, /* HasDisjunctSubRegs */
5929
    true, /* CoveredBySubRegs */
5930
    GPRPair_with_gsub_1_in_hGPR_and_rGPRSuperclasses,
5931
    nullptr
5932
  };
5933
5934
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass = {
5935
    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_tcGPRRegClassID],
5936
    GPRPair_with_gsub_1_in_tcGPRSubClassMask,
5937
    SuperRegIdxSeqs + 8,
5938
    LaneBitmask(0x00000003),
5939
    0,
5940
    true, /* HasDisjunctSubRegs */
5941
    true, /* CoveredBySubRegs */
5942
    GPRPair_with_gsub_1_in_tcGPRSuperclasses,
5943
    nullptr
5944
  };
5945
5946
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass = {
5947
    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_GPRspRegClassID],
5948
    GPRPair_with_gsub_1_in_GPRspSubClassMask,
5949
    SuperRegIdxSeqs + 8,
5950
    LaneBitmask(0x00000003),
5951
    0,
5952
    true, /* HasDisjunctSubRegs */
5953
    true, /* CoveredBySubRegs */
5954
    GPRPair_with_gsub_1_in_GPRspSuperclasses,
5955
    nullptr
5956
  };
5957
5958
  extern const TargetRegisterClass DPairSpcRegClass = {
5959
    &ARMMCRegisterClasses[DPairSpcRegClassID],
5960
    DPairSpcSubClassMask,
5961
    SuperRegIdxSeqs + 50,
5962
    LaneBitmask(0x000000CC),
5963
    0,
5964
    true, /* HasDisjunctSubRegs */
5965
    true, /* CoveredBySubRegs */
5966
    NullRegClasses,
5967
    nullptr
5968
  };
5969
5970
  extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass = {
5971
    &ARMMCRegisterClasses[DPairSpc_with_ssub_0RegClassID],
5972
    DPairSpc_with_ssub_0SubClassMask,
5973
    SuperRegIdxSeqs + 50,
5974
    LaneBitmask(0x000000CC),
5975
    0,
5976
    true, /* HasDisjunctSubRegs */
5977
    true, /* CoveredBySubRegs */
5978
    DPairSpc_with_ssub_0Superclasses,
5979
    nullptr
5980
  };
5981
5982
  extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass = {
5983
    &ARMMCRegisterClasses[DPairSpc_with_ssub_4RegClassID],
5984
    DPairSpc_with_ssub_4SubClassMask,
5985
    SuperRegIdxSeqs + 50,
5986
    LaneBitmask(0x000000CC),
5987
    0,
5988
    true, /* HasDisjunctSubRegs */
5989
    true, /* CoveredBySubRegs */
5990
    DPairSpc_with_ssub_4Superclasses,
5991
    nullptr
5992
  };
5993
5994
  extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass = {
5995
    &ARMMCRegisterClasses[DPairSpc_with_dsub_0_in_DPR_8RegClassID],
5996
    DPairSpc_with_dsub_0_in_DPR_8SubClassMask,
5997
    SuperRegIdxSeqs + 50,
5998
    LaneBitmask(0x000000CC),
5999
    0,
6000
    true, /* HasDisjunctSubRegs */
6001
    true, /* CoveredBySubRegs */
6002
    DPairSpc_with_dsub_0_in_DPR_8Superclasses,
6003
    nullptr
6004
  };
6005
6006
  extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass = {
6007
    &ARMMCRegisterClasses[DPairSpc_with_dsub_2_in_DPR_8RegClassID],
6008
    DPairSpc_with_dsub_2_in_DPR_8SubClassMask,
6009
    SuperRegIdxSeqs + 50,
6010
    LaneBitmask(0x000000CC),
6011
    0,
6012
    true, /* HasDisjunctSubRegs */
6013
    true, /* CoveredBySubRegs */
6014
    DPairSpc_with_dsub_2_in_DPR_8Superclasses,
6015
    nullptr
6016
  };
6017
6018
  extern const TargetRegisterClass DPairRegClass = {
6019
    &ARMMCRegisterClasses[DPairRegClassID],
6020
    DPairSubClassMask,
6021
    SuperRegIdxSeqs + 69,
6022
    LaneBitmask(0x0000003C),
6023
    0,
6024
    true, /* HasDisjunctSubRegs */
6025
    true, /* CoveredBySubRegs */
6026
    NullRegClasses,
6027
    DPairGetRawAllocationOrder
6028
  };
6029
6030
  extern const TargetRegisterClass DPair_with_ssub_0RegClass = {
6031
    &ARMMCRegisterClasses[DPair_with_ssub_0RegClassID],
6032
    DPair_with_ssub_0SubClassMask,
6033
    SuperRegIdxSeqs + 69,
6034
    LaneBitmask(0x0000003C),
6035
    0,
6036
    true, /* HasDisjunctSubRegs */
6037
    true, /* CoveredBySubRegs */
6038
    DPair_with_ssub_0Superclasses,
6039
    DPair_with_ssub_0GetRawAllocationOrder
6040
  };
6041
6042
  extern const TargetRegisterClass QPRRegClass = {
6043
    &ARMMCRegisterClasses[QPRRegClassID],
6044
    QPRSubClassMask,
6045
    SuperRegIdxSeqs + 31,
6046
    LaneBitmask(0x0000003C),
6047
    0,
6048
    true, /* HasDisjunctSubRegs */
6049
    true, /* CoveredBySubRegs */
6050
    QPRSuperclasses,
6051
    QPRGetRawAllocationOrder
6052
  };
6053
6054
  extern const TargetRegisterClass DPair_with_ssub_2RegClass = {
6055
    &ARMMCRegisterClasses[DPair_with_ssub_2RegClassID],
6056
    DPair_with_ssub_2SubClassMask,
6057
    SuperRegIdxSeqs + 69,
6058
    LaneBitmask(0x0000003C),
6059
    0,
6060
    true, /* HasDisjunctSubRegs */
6061
    true, /* CoveredBySubRegs */
6062
    DPair_with_ssub_2Superclasses,
6063
    DPair_with_ssub_2GetRawAllocationOrder
6064
  };
6065
6066
  extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass = {
6067
    &ARMMCRegisterClasses[DPair_with_dsub_0_in_DPR_8RegClassID],
6068
    DPair_with_dsub_0_in_DPR_8SubClassMask,
6069
    SuperRegIdxSeqs + 69,
6070
    LaneBitmask(0x0000003C),
6071
    0,
6072
    true, /* HasDisjunctSubRegs */
6073
    true, /* CoveredBySubRegs */
6074
    DPair_with_dsub_0_in_DPR_8Superclasses,
6075
    DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder
6076
  };
6077
6078
  extern const TargetRegisterClass QPR_VFP2RegClass = {
6079
    &ARMMCRegisterClasses[QPR_VFP2RegClassID],
6080
    QPR_VFP2SubClassMask,
6081
    SuperRegIdxSeqs + 31,
6082
    LaneBitmask(0x0000003C),
6083
    0,
6084
    true, /* HasDisjunctSubRegs */
6085
    true, /* CoveredBySubRegs */
6086
    QPR_VFP2Superclasses,
6087
    nullptr
6088
  };
6089
6090
  extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass = {
6091
    &ARMMCRegisterClasses[DPair_with_dsub_1_in_DPR_8RegClassID],
6092
    DPair_with_dsub_1_in_DPR_8SubClassMask,
6093
    SuperRegIdxSeqs + 69,
6094
    LaneBitmask(0x0000003C),
6095
    0,
6096
    true, /* HasDisjunctSubRegs */
6097
    true, /* CoveredBySubRegs */
6098
    DPair_with_dsub_1_in_DPR_8Superclasses,
6099
    DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder
6100
  };
6101
6102
  extern const TargetRegisterClass QPR_8RegClass = {
6103
    &ARMMCRegisterClasses[QPR_8RegClassID],
6104
    QPR_8SubClassMask,
6105
    SuperRegIdxSeqs + 31,
6106
    LaneBitmask(0x0000003C),
6107
    0,
6108
    true, /* HasDisjunctSubRegs */
6109
    true, /* CoveredBySubRegs */
6110
    QPR_8Superclasses,
6111
    nullptr
6112
  };
6113
6114
  extern const TargetRegisterClass DTripleRegClass = {
6115
    &ARMMCRegisterClasses[DTripleRegClassID],
6116
    DTripleSubClassMask,
6117
    SuperRegIdxSeqs + 62,
6118
    LaneBitmask(0x000000FC),
6119
    0,
6120
    true, /* HasDisjunctSubRegs */
6121
    true, /* CoveredBySubRegs */
6122
    NullRegClasses,
6123
    nullptr
6124
  };
6125
6126
  extern const TargetRegisterClass DTripleSpcRegClass = {
6127
    &ARMMCRegisterClasses[DTripleSpcRegClassID],
6128
    DTripleSpcSubClassMask,
6129
    SuperRegIdxSeqs + 37,
6130
    LaneBitmask(0x00000CCC),
6131
    0,
6132
    true, /* HasDisjunctSubRegs */
6133
    true, /* CoveredBySubRegs */
6134
    NullRegClasses,
6135
    nullptr
6136
  };
6137
6138
  extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass = {
6139
    &ARMMCRegisterClasses[DTripleSpc_with_ssub_0RegClassID],
6140
    DTripleSpc_with_ssub_0SubClassMask,
6141
    SuperRegIdxSeqs + 37,
6142
    LaneBitmask(0x00000CCC),
6143
    0,
6144
    true, /* HasDisjunctSubRegs */
6145
    true, /* CoveredBySubRegs */
6146
    DTripleSpc_with_ssub_0Superclasses,
6147
    nullptr
6148
  };
6149
6150
  extern const TargetRegisterClass DTriple_with_ssub_0RegClass = {
6151
    &ARMMCRegisterClasses[DTriple_with_ssub_0RegClassID],
6152
    DTriple_with_ssub_0SubClassMask,
6153
    SuperRegIdxSeqs + 62,
6154
    LaneBitmask(0x000000FC),
6155
    0,
6156
    true, /* HasDisjunctSubRegs */
6157
    true, /* CoveredBySubRegs */
6158
    DTriple_with_ssub_0Superclasses,
6159
    nullptr
6160
  };
6161
6162
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass = {
6163
    &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPRRegClassID],
6164
    DTriple_with_qsub_0_in_QPRSubClassMask,
6165
    SuperRegIdxSeqs + 45,
6166
    LaneBitmask(0x000000FC),
6167
    0,
6168
    true, /* HasDisjunctSubRegs */
6169
    true, /* CoveredBySubRegs */
6170
    DTriple_with_qsub_0_in_QPRSuperclasses,
6171
    nullptr
6172
  };
6173
6174
  extern const TargetRegisterClass DTriple_with_ssub_2RegClass = {
6175
    &ARMMCRegisterClasses[DTriple_with_ssub_2RegClassID],
6176
    DTriple_with_ssub_2SubClassMask,
6177
    SuperRegIdxSeqs + 62,
6178
    LaneBitmask(0x000000FC),
6179
    0,
6180
    true, /* HasDisjunctSubRegs */
6181
    true, /* CoveredBySubRegs */
6182
    DTriple_with_ssub_2Superclasses,
6183
    nullptr
6184
  };
6185
6186
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6187
    &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6188
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6189
    SuperRegIdxSeqs + 57,
6190
    LaneBitmask(0x000000FC),
6191
    0,
6192
    true, /* HasDisjunctSubRegs */
6193
    true, /* CoveredBySubRegs */
6194
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6195
    nullptr
6196
  };
6197
6198
  extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass = {
6199
    &ARMMCRegisterClasses[DTripleSpc_with_ssub_4RegClassID],
6200
    DTripleSpc_with_ssub_4SubClassMask,
6201
    SuperRegIdxSeqs + 37,
6202
    LaneBitmask(0x00000CCC),
6203
    0,
6204
    true, /* HasDisjunctSubRegs */
6205
    true, /* CoveredBySubRegs */
6206
    DTripleSpc_with_ssub_4Superclasses,
6207
    nullptr
6208
  };
6209
6210
  extern const TargetRegisterClass DTriple_with_ssub_4RegClass = {
6211
    &ARMMCRegisterClasses[DTriple_with_ssub_4RegClassID],
6212
    DTriple_with_ssub_4SubClassMask,
6213
    SuperRegIdxSeqs + 62,
6214
    LaneBitmask(0x000000FC),
6215
    0,
6216
    true, /* HasDisjunctSubRegs */
6217
    true, /* CoveredBySubRegs */
6218
    DTriple_with_ssub_4Superclasses,
6219
    nullptr
6220
  };
6221
6222
  extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass = {
6223
    &ARMMCRegisterClasses[DTripleSpc_with_ssub_8RegClassID],
6224
    DTripleSpc_with_ssub_8SubClassMask,
6225
    SuperRegIdxSeqs + 37,
6226
    LaneBitmask(0x00000CCC),
6227
    0,
6228
    true, /* HasDisjunctSubRegs */
6229
    true, /* CoveredBySubRegs */
6230
    DTripleSpc_with_ssub_8Superclasses,
6231
    nullptr
6232
  };
6233
6234
  extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass = {
6235
    &ARMMCRegisterClasses[DTripleSpc_with_dsub_0_in_DPR_8RegClassID],
6236
    DTripleSpc_with_dsub_0_in_DPR_8SubClassMask,
6237
    SuperRegIdxSeqs + 37,
6238
    LaneBitmask(0x00000CCC),
6239
    0,
6240
    true, /* HasDisjunctSubRegs */
6241
    true, /* CoveredBySubRegs */
6242
    DTripleSpc_with_dsub_0_in_DPR_8Superclasses,
6243
    nullptr
6244
  };
6245
6246
  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass = {
6247
    &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8RegClassID],
6248
    DTriple_with_dsub_0_in_DPR_8SubClassMask,
6249
    SuperRegIdxSeqs + 62,
6250
    LaneBitmask(0x000000FC),
6251
    0,
6252
    true, /* HasDisjunctSubRegs */
6253
    true, /* CoveredBySubRegs */
6254
    DTriple_with_dsub_0_in_DPR_8Superclasses,
6255
    nullptr
6256
  };
6257
6258
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_VFP2RegClass = {
6259
    &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPR_VFP2RegClassID],
6260
    DTriple_with_qsub_0_in_QPR_VFP2SubClassMask,
6261
    SuperRegIdxSeqs + 45,
6262
    LaneBitmask(0x000000FC),
6263
    0,
6264
    true, /* HasDisjunctSubRegs */
6265
    true, /* CoveredBySubRegs */
6266
    DTriple_with_qsub_0_in_QPR_VFP2Superclasses,
6267
    nullptr
6268
  };
6269
6270
  extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6271
    &ARMMCRegisterClasses[DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6272
    DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6273
    SuperRegIdxSeqs + 57,
6274
    LaneBitmask(0x000000FC),
6275
    0,
6276
    true, /* HasDisjunctSubRegs */
6277
    true, /* CoveredBySubRegs */
6278
    DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6279
    nullptr
6280
  };
6281
6282
  extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass = {
6283
    &ARMMCRegisterClasses[DTriple_with_dsub_1_in_DPR_8RegClassID],
6284
    DTriple_with_dsub_1_in_DPR_8SubClassMask,
6285
    SuperRegIdxSeqs + 62,
6286
    LaneBitmask(0x000000FC),
6287
    0,
6288
    true, /* HasDisjunctSubRegs */
6289
    true, /* CoveredBySubRegs */
6290
    DTriple_with_dsub_1_in_DPR_8Superclasses,
6291
    nullptr
6292
  };
6293
6294
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass = {
6295
    &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID],
6296
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask,
6297
    SuperRegIdxSeqs + 57,
6298
    LaneBitmask(0x000000FC),
6299
    0,
6300
    true, /* HasDisjunctSubRegs */
6301
    true, /* CoveredBySubRegs */
6302
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses,
6303
    nullptr
6304
  };
6305
6306
  extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass = {
6307
    &ARMMCRegisterClasses[DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID],
6308
    DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSubClassMask,
6309
    SuperRegIdxSeqs + 45,
6310
    LaneBitmask(0x000000FC),
6311
    0,
6312
    true, /* HasDisjunctSubRegs */
6313
    true, /* CoveredBySubRegs */
6314
    DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSuperclasses,
6315
    nullptr
6316
  };
6317
6318
  extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass = {
6319
    &ARMMCRegisterClasses[DTripleSpc_with_dsub_2_in_DPR_8RegClassID],
6320
    DTripleSpc_with_dsub_2_in_DPR_8SubClassMask,
6321
    SuperRegIdxSeqs + 37,
6322
    LaneBitmask(0x00000CCC),
6323
    0,
6324
    true, /* HasDisjunctSubRegs */
6325
    true, /* CoveredBySubRegs */
6326
    DTripleSpc_with_dsub_2_in_DPR_8Superclasses,
6327
    nullptr
6328
  };
6329
6330
  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass = {
6331
    &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8RegClassID],
6332
    DTriple_with_dsub_2_in_DPR_8SubClassMask,
6333
    SuperRegIdxSeqs + 62,
6334
    LaneBitmask(0x000000FC),
6335
    0,
6336
    true, /* HasDisjunctSubRegs */
6337
    true, /* CoveredBySubRegs */
6338
    DTriple_with_dsub_2_in_DPR_8Superclasses,
6339
    nullptr
6340
  };
6341
6342
  extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass = {
6343
    &ARMMCRegisterClasses[DTripleSpc_with_dsub_4_in_DPR_8RegClassID],
6344
    DTripleSpc_with_dsub_4_in_DPR_8SubClassMask,
6345
    SuperRegIdxSeqs + 37,
6346
    LaneBitmask(0x00000CCC),
6347
    0,
6348
    true, /* HasDisjunctSubRegs */
6349
    true, /* CoveredBySubRegs */
6350
    DTripleSpc_with_dsub_4_in_DPR_8Superclasses,
6351
    nullptr
6352
  };
6353
6354
  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6355
    &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6356
    DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6357
    SuperRegIdxSeqs + 57,
6358
    LaneBitmask(0x000000FC),
6359
    0,
6360
    true, /* HasDisjunctSubRegs */
6361
    true, /* CoveredBySubRegs */
6362
    DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6363
    nullptr
6364
  };
6365
6366
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass = {
6367
    &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPR_8RegClassID],
6368
    DTriple_with_qsub_0_in_QPR_8SubClassMask,
6369
    SuperRegIdxSeqs + 45,
6370
    LaneBitmask(0x000000FC),
6371
    0,
6372
    true, /* HasDisjunctSubRegs */
6373
    true, /* CoveredBySubRegs */
6374
    DTriple_with_qsub_0_in_QPR_8Superclasses,
6375
    nullptr
6376
  };
6377
6378
  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass = {
6379
    &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID],
6380
    DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSubClassMask,
6381
    SuperRegIdxSeqs + 45,
6382
    LaneBitmask(0x000000FC),
6383
    0,
6384
    true, /* HasDisjunctSubRegs */
6385
    true, /* CoveredBySubRegs */
6386
    DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSuperclasses,
6387
    nullptr
6388
  };
6389
6390
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = {
6391
    &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID],
6392
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask,
6393
    SuperRegIdxSeqs + 57,
6394
    LaneBitmask(0x000000FC),
6395
    0,
6396
    true, /* HasDisjunctSubRegs */
6397
    true, /* CoveredBySubRegs */
6398
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses,
6399
    nullptr
6400
  };
6401
6402
  extern const TargetRegisterClass DQuadSpcRegClass = {
6403
    &ARMMCRegisterClasses[DQuadSpcRegClassID],
6404
    DQuadSpcSubClassMask,
6405
    SuperRegIdxSeqs + 37,
6406
    LaneBitmask(0x00000CCC),
6407
    0,
6408
    true, /* HasDisjunctSubRegs */
6409
    true, /* CoveredBySubRegs */
6410
    DQuadSpcSuperclasses,
6411
    nullptr
6412
  };
6413
6414
  extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass = {
6415
    &ARMMCRegisterClasses[DQuadSpc_with_ssub_0RegClassID],
6416
    DQuadSpc_with_ssub_0SubClassMask,
6417
    SuperRegIdxSeqs + 37,
6418
    LaneBitmask(0x00000CCC),
6419
    0,
6420
    true, /* HasDisjunctSubRegs */
6421
    true, /* CoveredBySubRegs */
6422
    DQuadSpc_with_ssub_0Superclasses,
6423
    nullptr
6424
  };
6425
6426
  extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass = {
6427
    &ARMMCRegisterClasses[DQuadSpc_with_ssub_4RegClassID],
6428
    DQuadSpc_with_ssub_4SubClassMask,
6429
    SuperRegIdxSeqs + 37,
6430
    LaneBitmask(0x00000CCC),
6431
    0,
6432
    true, /* HasDisjunctSubRegs */
6433
    true, /* CoveredBySubRegs */
6434
    DQuadSpc_with_ssub_4Superclasses,
6435
    nullptr
6436
  };
6437
6438
  extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass = {
6439
    &ARMMCRegisterClasses[DQuadSpc_with_ssub_8RegClassID],
6440
    DQuadSpc_with_ssub_8SubClassMask,
6441
    SuperRegIdxSeqs + 37,
6442
    LaneBitmask(0x00000CCC),
6443
    0,
6444
    true, /* HasDisjunctSubRegs */
6445
    true, /* CoveredBySubRegs */
6446
    DQuadSpc_with_ssub_8Superclasses,
6447
    nullptr
6448
  };
6449
6450
  extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass = {
6451
    &ARMMCRegisterClasses[DQuadSpc_with_dsub_0_in_DPR_8RegClassID],
6452
    DQuadSpc_with_dsub_0_in_DPR_8SubClassMask,
6453
    SuperRegIdxSeqs + 37,
6454
    LaneBitmask(0x00000CCC),
6455
    0,
6456
    true, /* HasDisjunctSubRegs */
6457
    true, /* CoveredBySubRegs */
6458
    DQuadSpc_with_dsub_0_in_DPR_8Superclasses,
6459
    nullptr
6460
  };
6461
6462
  extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass = {
6463
    &ARMMCRegisterClasses[DQuadSpc_with_dsub_2_in_DPR_8RegClassID],
6464
    DQuadSpc_with_dsub_2_in_DPR_8SubClassMask,
6465
    SuperRegIdxSeqs + 37,
6466
    LaneBitmask(0x00000CCC),
6467
    0,
6468
    true, /* HasDisjunctSubRegs */
6469
    true, /* CoveredBySubRegs */
6470
    DQuadSpc_with_dsub_2_in_DPR_8Superclasses,
6471
    nullptr
6472
  };
6473
6474
  extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass = {
6475
    &ARMMCRegisterClasses[DQuadSpc_with_dsub_4_in_DPR_8RegClassID],
6476
    DQuadSpc_with_dsub_4_in_DPR_8SubClassMask,
6477
    SuperRegIdxSeqs + 37,
6478
    LaneBitmask(0x00000CCC),
6479
    0,
6480
    true, /* HasDisjunctSubRegs */
6481
    true, /* CoveredBySubRegs */
6482
    DQuadSpc_with_dsub_4_in_DPR_8Superclasses,
6483
    nullptr
6484
  };
6485
6486
  extern const TargetRegisterClass DQuadRegClass = {
6487
    &ARMMCRegisterClasses[DQuadRegClassID],
6488
    DQuadSubClassMask,
6489
    SuperRegIdxSeqs + 81,
6490
    LaneBitmask(0x000003FC),
6491
    0,
6492
    true, /* HasDisjunctSubRegs */
6493
    true, /* CoveredBySubRegs */
6494
    NullRegClasses,
6495
    nullptr
6496
  };
6497
6498
  extern const TargetRegisterClass DQuad_with_ssub_0RegClass = {
6499
    &ARMMCRegisterClasses[DQuad_with_ssub_0RegClassID],
6500
    DQuad_with_ssub_0SubClassMask,
6501
    SuperRegIdxSeqs + 81,
6502
    LaneBitmask(0x000003FC),
6503
    0,
6504
    true, /* HasDisjunctSubRegs */
6505
    true, /* CoveredBySubRegs */
6506
    DQuad_with_ssub_0Superclasses,
6507
    nullptr
6508
  };
6509
6510
  extern const TargetRegisterClass DQuad_with_ssub_2RegClass = {
6511
    &ARMMCRegisterClasses[DQuad_with_ssub_2RegClassID],
6512
    DQuad_with_ssub_2SubClassMask,
6513
    SuperRegIdxSeqs + 81,
6514
    LaneBitmask(0x000003FC),
6515
    0,
6516
    true, /* HasDisjunctSubRegs */
6517
    true, /* CoveredBySubRegs */
6518
    DQuad_with_ssub_2Superclasses,
6519
    nullptr
6520
  };
6521
6522
  extern const TargetRegisterClass QQPRRegClass = {
6523
    &ARMMCRegisterClasses[QQPRRegClassID],
6524
    QQPRSubClassMask,
6525
    SuperRegIdxSeqs + 77,
6526
    LaneBitmask(0x000003FC),
6527
    0,
6528
    true, /* HasDisjunctSubRegs */
6529
    true, /* CoveredBySubRegs */
6530
    QQPRSuperclasses,
6531
    QQPRGetRawAllocationOrder
6532
  };
6533
6534
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6535
    &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6536
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6537
    SuperRegIdxSeqs + 42,
6538
    LaneBitmask(0x000003FC),
6539
    0,
6540
    true, /* HasDisjunctSubRegs */
6541
    true, /* CoveredBySubRegs */
6542
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6543
    nullptr
6544
  };
6545
6546
  extern const TargetRegisterClass DQuad_with_ssub_4RegClass = {
6547
    &ARMMCRegisterClasses[DQuad_with_ssub_4RegClassID],
6548
    DQuad_with_ssub_4SubClassMask,
6549
    SuperRegIdxSeqs + 81,
6550
    LaneBitmask(0x000003FC),
6551
    0,
6552
    true, /* HasDisjunctSubRegs */
6553
    true, /* CoveredBySubRegs */
6554
    DQuad_with_ssub_4Superclasses,
6555
    nullptr
6556
  };
6557
6558
  extern const TargetRegisterClass DQuad_with_ssub_6RegClass = {
6559
    &ARMMCRegisterClasses[DQuad_with_ssub_6RegClassID],
6560
    DQuad_with_ssub_6SubClassMask,
6561
    SuperRegIdxSeqs + 81,
6562
    LaneBitmask(0x000003FC),
6563
    0,
6564
    true, /* HasDisjunctSubRegs */
6565
    true, /* CoveredBySubRegs */
6566
    DQuad_with_ssub_6Superclasses,
6567
    nullptr
6568
  };
6569
6570
  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass = {
6571
    &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8RegClassID],
6572
    DQuad_with_dsub_0_in_DPR_8SubClassMask,
6573
    SuperRegIdxSeqs + 81,
6574
    LaneBitmask(0x000003FC),
6575
    0,
6576
    true, /* HasDisjunctSubRegs */
6577
    true, /* CoveredBySubRegs */
6578
    DQuad_with_dsub_0_in_DPR_8Superclasses,
6579
    nullptr
6580
  };
6581
6582
  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_VFP2RegClass = {
6583
    &ARMMCRegisterClasses[DQuad_with_qsub_0_in_QPR_VFP2RegClassID],
6584
    DQuad_with_qsub_0_in_QPR_VFP2SubClassMask,
6585
    SuperRegIdxSeqs + 77,
6586
    LaneBitmask(0x000003FC),
6587
    0,
6588
    true, /* HasDisjunctSubRegs */
6589
    true, /* CoveredBySubRegs */
6590
    DQuad_with_qsub_0_in_QPR_VFP2Superclasses,
6591
    DQuad_with_qsub_0_in_QPR_VFP2GetRawAllocationOrder
6592
  };
6593
6594
  extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6595
    &ARMMCRegisterClasses[DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6596
    DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6597
    SuperRegIdxSeqs + 42,
6598
    LaneBitmask(0x000003FC),
6599
    0,
6600
    true, /* HasDisjunctSubRegs */
6601
    true, /* CoveredBySubRegs */
6602
    DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6603
    nullptr
6604
  };
6605
6606
  extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass = {
6607
    &ARMMCRegisterClasses[DQuad_with_dsub_1_in_DPR_8RegClassID],
6608
    DQuad_with_dsub_1_in_DPR_8SubClassMask,
6609
    SuperRegIdxSeqs + 81,
6610
    LaneBitmask(0x000003FC),
6611
    0,
6612
    true, /* HasDisjunctSubRegs */
6613
    true, /* CoveredBySubRegs */
6614
    DQuad_with_dsub_1_in_DPR_8Superclasses,
6615
    nullptr
6616
  };
6617
6618
  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_VFP2RegClass = {
6619
    &ARMMCRegisterClasses[DQuad_with_qsub_1_in_QPR_VFP2RegClassID],
6620
    DQuad_with_qsub_1_in_QPR_VFP2SubClassMask,
6621
    SuperRegIdxSeqs + 77,
6622
    LaneBitmask(0x000003FC),
6623
    0,
6624
    true, /* HasDisjunctSubRegs */
6625
    true, /* CoveredBySubRegs */
6626
    DQuad_with_qsub_1_in_QPR_VFP2Superclasses,
6627
    DQuad_with_qsub_1_in_QPR_VFP2GetRawAllocationOrder
6628
  };
6629
6630
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass = {
6631
    &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID],
6632
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask,
6633
    SuperRegIdxSeqs + 42,
6634
    LaneBitmask(0x000003FC),
6635
    0,
6636
    true, /* HasDisjunctSubRegs */
6637
    true, /* CoveredBySubRegs */
6638
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses,
6639
    nullptr
6640
  };
6641
6642
  extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass = {
6643
    &ARMMCRegisterClasses[DQuad_with_dsub_2_in_DPR_8RegClassID],
6644
    DQuad_with_dsub_2_in_DPR_8SubClassMask,
6645
    SuperRegIdxSeqs + 81,
6646
    LaneBitmask(0x000003FC),
6647
    0,
6648
    true, /* HasDisjunctSubRegs */
6649
    true, /* CoveredBySubRegs */
6650
    DQuad_with_dsub_2_in_DPR_8Superclasses,
6651
    nullptr
6652
  };
6653
6654
  extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6655
    &ARMMCRegisterClasses[DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6656
    DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6657
    SuperRegIdxSeqs + 42,
6658
    LaneBitmask(0x000003FC),
6659
    0,
6660
    true, /* HasDisjunctSubRegs */
6661
    true, /* CoveredBySubRegs */
6662
    DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6663
    nullptr
6664
  };
6665
6666
  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass = {
6667
    &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8RegClassID],
6668
    DQuad_with_dsub_3_in_DPR_8SubClassMask,
6669
    SuperRegIdxSeqs + 81,
6670
    LaneBitmask(0x000003FC),
6671
    0,
6672
    true, /* HasDisjunctSubRegs */
6673
    true, /* CoveredBySubRegs */
6674
    DQuad_with_dsub_3_in_DPR_8Superclasses,
6675
    nullptr
6676
  };
6677
6678
  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6679
    &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6680
    DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6681
    SuperRegIdxSeqs + 42,
6682
    LaneBitmask(0x000003FC),
6683
    0,
6684
    true, /* HasDisjunctSubRegs */
6685
    true, /* CoveredBySubRegs */
6686
    DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6687
    nullptr
6688
  };
6689
6690
  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass = {
6691
    &ARMMCRegisterClasses[DQuad_with_qsub_0_in_QPR_8RegClassID],
6692
    DQuad_with_qsub_0_in_QPR_8SubClassMask,
6693
    SuperRegIdxSeqs + 77,
6694
    LaneBitmask(0x000003FC),
6695
    0,
6696
    true, /* HasDisjunctSubRegs */
6697
    true, /* CoveredBySubRegs */
6698
    DQuad_with_qsub_0_in_QPR_8Superclasses,
6699
    DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder
6700
  };
6701
6702
  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass = {
6703
    &ARMMCRegisterClasses[DQuad_with_qsub_1_in_QPR_8RegClassID],
6704
    DQuad_with_qsub_1_in_QPR_8SubClassMask,
6705
    SuperRegIdxSeqs + 77,
6706
    LaneBitmask(0x000003FC),
6707
    0,
6708
    true, /* HasDisjunctSubRegs */
6709
    true, /* CoveredBySubRegs */
6710
    DQuad_with_qsub_1_in_QPR_8Superclasses,
6711
    DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder
6712
  };
6713
6714
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = {
6715
    &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID],
6716
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask,
6717
    SuperRegIdxSeqs + 42,
6718
    LaneBitmask(0x000003FC),
6719
    0,
6720
    true, /* HasDisjunctSubRegs */
6721
    true, /* CoveredBySubRegs */
6722
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses,
6723
    nullptr
6724
  };
6725
6726
  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6727
    &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6728
    DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6729
    SuperRegIdxSeqs + 42,
6730
    LaneBitmask(0x000003FC),
6731
    0,
6732
    true, /* HasDisjunctSubRegs */
6733
    true, /* CoveredBySubRegs */
6734
    DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6735
    nullptr
6736
  };
6737
6738
  extern const TargetRegisterClass QQQQPRRegClass = {
6739
    &ARMMCRegisterClasses[QQQQPRRegClassID],
6740
    QQQQPRSubClassMask,
6741
    SuperRegIdxSeqs + 8,
6742
    LaneBitmask(0x0003FFFC),
6743
    0,
6744
    true, /* HasDisjunctSubRegs */
6745
    true, /* CoveredBySubRegs */
6746
    NullRegClasses,
6747
    QQQQPRGetRawAllocationOrder
6748
  };
6749
6750
  extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass = {
6751
    &ARMMCRegisterClasses[QQQQPR_with_ssub_0RegClassID],
6752
    QQQQPR_with_ssub_0SubClassMask,
6753
    SuperRegIdxSeqs + 8,
6754
    LaneBitmask(0x0003FFFC),
6755
    0,
6756
    true, /* HasDisjunctSubRegs */
6757
    true, /* CoveredBySubRegs */
6758
    QQQQPR_with_ssub_0Superclasses,
6759
    QQQQPR_with_ssub_0GetRawAllocationOrder
6760
  };
6761
6762
  extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass = {
6763
    &ARMMCRegisterClasses[QQQQPR_with_ssub_4RegClassID],
6764
    QQQQPR_with_ssub_4SubClassMask,
6765
    SuperRegIdxSeqs + 8,
6766
    LaneBitmask(0x0003FFFC),
6767
    0,
6768
    true, /* HasDisjunctSubRegs */
6769
    true, /* CoveredBySubRegs */
6770
    QQQQPR_with_ssub_4Superclasses,
6771
    QQQQPR_with_ssub_4GetRawAllocationOrder
6772
  };
6773
6774
  extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass = {
6775
    &ARMMCRegisterClasses[QQQQPR_with_ssub_8RegClassID],
6776
    QQQQPR_with_ssub_8SubClassMask,
6777
    SuperRegIdxSeqs + 8,
6778
    LaneBitmask(0x0003FFFC),
6779
    0,
6780
    true, /* HasDisjunctSubRegs */
6781
    true, /* CoveredBySubRegs */
6782
    QQQQPR_with_ssub_8Superclasses,
6783
    QQQQPR_with_ssub_8GetRawAllocationOrder
6784
  };
6785
6786
  extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass = {
6787
    &ARMMCRegisterClasses[QQQQPR_with_ssub_12RegClassID],
6788
    QQQQPR_with_ssub_12SubClassMask,
6789
    SuperRegIdxSeqs + 8,
6790
    LaneBitmask(0x0003FFFC),
6791
    0,
6792
    true, /* HasDisjunctSubRegs */
6793
    true, /* CoveredBySubRegs */
6794
    QQQQPR_with_ssub_12Superclasses,
6795
    QQQQPR_with_ssub_12GetRawAllocationOrder
6796
  };
6797
6798
  extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass = {
6799
    &ARMMCRegisterClasses[QQQQPR_with_dsub_0_in_DPR_8RegClassID],
6800
    QQQQPR_with_dsub_0_in_DPR_8SubClassMask,
6801
    SuperRegIdxSeqs + 8,
6802
    LaneBitmask(0x0003FFFC),
6803
    0,
6804
    true, /* HasDisjunctSubRegs */
6805
    true, /* CoveredBySubRegs */
6806
    QQQQPR_with_dsub_0_in_DPR_8Superclasses,
6807
    QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder
6808
  };
6809
6810
  extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass = {
6811
    &ARMMCRegisterClasses[QQQQPR_with_dsub_2_in_DPR_8RegClassID],
6812
    QQQQPR_with_dsub_2_in_DPR_8SubClassMask,
6813
    SuperRegIdxSeqs + 8,
6814
    LaneBitmask(0x0003FFFC),
6815
    0,
6816
    true, /* HasDisjunctSubRegs */
6817
    true, /* CoveredBySubRegs */
6818
    QQQQPR_with_dsub_2_in_DPR_8Superclasses,
6819
    QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder
6820
  };
6821
6822
  extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass = {
6823
    &ARMMCRegisterClasses[QQQQPR_with_dsub_4_in_DPR_8RegClassID],
6824
    QQQQPR_with_dsub_4_in_DPR_8SubClassMask,
6825
    SuperRegIdxSeqs + 8,
6826
    LaneBitmask(0x0003FFFC),
6827
    0,
6828
    true, /* HasDisjunctSubRegs */
6829
    true, /* CoveredBySubRegs */
6830
    QQQQPR_with_dsub_4_in_DPR_8Superclasses,
6831
    QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder
6832
  };
6833
6834
  extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass = {
6835
    &ARMMCRegisterClasses[QQQQPR_with_dsub_6_in_DPR_8RegClassID],
6836
    QQQQPR_with_dsub_6_in_DPR_8SubClassMask,
6837
    SuperRegIdxSeqs + 8,
6838
    LaneBitmask(0x0003FFFC),
6839
    0,
6840
    true, /* HasDisjunctSubRegs */
6841
    true, /* CoveredBySubRegs */
6842
    QQQQPR_with_dsub_6_in_DPR_8Superclasses,
6843
    QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder
6844
  };
6845
6846
} // end namespace ARM
6847
6848
namespace {
6849
  const TargetRegisterClass* const RegisterClasses[] = {
6850
    &ARM::SPRRegClass,
6851
    &ARM::GPRRegClass,
6852
    &ARM::GPRwithAPSRRegClass,
6853
    &ARM::SPR_8RegClass,
6854
    &ARM::GPRnopcRegClass,
6855
    &ARM::rGPRRegClass,
6856
    &ARM::tGPRwithpcRegClass,
6857
    &ARM::hGPRRegClass,
6858
    &ARM::tGPRRegClass,
6859
    &ARM::GPRnopc_and_hGPRRegClass,
6860
    &ARM::hGPR_and_rGPRRegClass,
6861
    &ARM::tcGPRRegClass,
6862
    &ARM::tGPR_and_tcGPRRegClass,
6863
    &ARM::CCRRegClass,
6864
    &ARM::GPRspRegClass,
6865
    &ARM::hGPR_and_tGPRwithpcRegClass,
6866
    &ARM::hGPR_and_tcGPRRegClass,
6867
    &ARM::DPRRegClass,
6868
    &ARM::DPR_VFP2RegClass,
6869
    &ARM::DPR_8RegClass,
6870
    &ARM::GPRPairRegClass,
6871
    &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
6872
    &ARM::GPRPair_with_gsub_0_in_tGPRRegClass,
6873
    &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
6874
    &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
6875
    &ARM::GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass,
6876
    &ARM::GPRPair_with_gsub_1_in_tcGPRRegClass,
6877
    &ARM::GPRPair_with_gsub_1_in_GPRspRegClass,
6878
    &ARM::DPairSpcRegClass,
6879
    &ARM::DPairSpc_with_ssub_0RegClass,
6880
    &ARM::DPairSpc_with_ssub_4RegClass,
6881
    &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass,
6882
    &ARM::DPairSpc_with_dsub_2_in_DPR_8RegClass,
6883
    &ARM::DPairRegClass,
6884
    &ARM::DPair_with_ssub_0RegClass,
6885
    &ARM::QPRRegClass,
6886
    &ARM::DPair_with_ssub_2RegClass,
6887
    &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
6888
    &ARM::QPR_VFP2RegClass,
6889
    &ARM::DPair_with_dsub_1_in_DPR_8RegClass,
6890
    &ARM::QPR_8RegClass,
6891
    &ARM::DTripleRegClass,
6892
    &ARM::DTripleSpcRegClass,
6893
    &ARM::DTripleSpc_with_ssub_0RegClass,
6894
    &ARM::DTriple_with_ssub_0RegClass,
6895
    &ARM::DTriple_with_qsub_0_in_QPRRegClass,
6896
    &ARM::DTriple_with_ssub_2RegClass,
6897
    &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
6898
    &ARM::DTripleSpc_with_ssub_4RegClass,
6899
    &ARM::DTriple_with_ssub_4RegClass,
6900
    &ARM::DTripleSpc_with_ssub_8RegClass,
6901
    &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
6902
    &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
6903
    &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
6904
    &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
6905
    &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
6906
    &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
6907
    &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
6908
    &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
6909
    &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
6910
    &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass,
6911
    &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
6912
    &ARM::DTriple_with_qsub_0_in_QPR_8RegClass,
6913
    &ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass,
6914
    &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
6915
    &ARM::DQuadSpcRegClass,
6916
    &ARM::DQuadSpc_with_ssub_0RegClass,
6917
    &ARM::DQuadSpc_with_ssub_4RegClass,
6918
    &ARM::DQuadSpc_with_ssub_8RegClass,
6919
    &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
6920
    &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass,
6921
    &ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClass,
6922
    &ARM::DQuadRegClass,
6923
    &ARM::DQuad_with_ssub_0RegClass,
6924
    &ARM::DQuad_with_ssub_2RegClass,
6925
    &ARM::QQPRRegClass,
6926
    &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
6927
    &ARM::DQuad_with_ssub_4RegClass,
6928
    &ARM::DQuad_with_ssub_6RegClass,
6929
    &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
6930
    &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
6931
    &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
6932
    &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
6933
    &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
6934
    &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
6935
    &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
6936
    &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
6937
    &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
6938
    &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
6939
    &ARM::DQuad_with_qsub_0_in_QPR_8RegClass,
6940
    &ARM::DQuad_with_qsub_1_in_QPR_8RegClass,
6941
    &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
6942
    &ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
6943
    &ARM::QQQQPRRegClass,
6944
    &ARM::QQQQPR_with_ssub_0RegClass,
6945
    &ARM::QQQQPR_with_ssub_4RegClass,
6946
    &ARM::QQQQPR_with_ssub_8RegClass,
6947
    &ARM::QQQQPR_with_ssub_12RegClass,
6948
    &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
6949
    &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
6950
    &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass,
6951
    &ARM::QQQQPR_with_dsub_6_in_DPR_8RegClass,
6952
  };
6953
} // end anonymous namespace
6954
6955
static const TargetRegisterInfoDesc ARMRegInfoDesc[] = { // Extra Descriptors
6956
  { 0, false },
6957
  { 0, false },
6958
  { 0, true },
6959
  { 0, false },
6960
  { 0, false },
6961
  { 0, false },
6962
  { 0, false },
6963
  { 0, false },
6964
  { 0, false },
6965
  { 0, false },
6966
  { 1, true },
6967
  { 1, true },
6968
  { 1, true },
6969
  { 0, false },
6970
  { 0, true },
6971
  { 0, true },
6972
  { 0, true },
6973
  { 0, true },
6974
  { 0, true },
6975
  { 0, true },
6976
  { 0, true },
6977
  { 0, true },
6978
  { 0, true },
6979
  { 0, true },
6980
  { 0, true },
6981
  { 0, true },
6982
  { 0, true },
6983
  { 0, true },
6984
  { 0, true },
6985
  { 0, true },
6986
  { 0, true },
6987
  { 0, true },
6988
  { 0, true },
6989
  { 0, true },
6990
  { 0, true },
6991
  { 0, true },
6992
  { 0, true },
6993
  { 0, true },
6994
  { 0, true },
6995
  { 0, true },
6996
  { 0, true },
6997
  { 0, true },
6998
  { 0, true },
6999
  { 0, true },
7000
  { 0, true },
7001
  { 0, true },
7002
  { 0, false },
7003
  { 0, false },
7004
  { 0, false },
7005
  { 0, false },
7006
  { 0, true },
7007
  { 0, true },
7008
  { 0, true },
7009
  { 0, true },
7010
  { 0, true },
7011
  { 0, true },
7012
  { 0, true },
7013
  { 0, true },
7014
  { 0, true },
7015
  { 0, true },
7016
  { 0, true },
7017
  { 0, true },
7018
  { 0, true },
7019
  { 0, true },
7020
  { 0, true },
7021
  { 0, true },
7022
  { 0, true },
7023
  { 0, true },
7024
  { 0, true },
7025
  { 0, true },
7026
  { 0, true },
7027
  { 0, true },
7028
  { 0, true },
7029
  { 0, true },
7030
  { 1, true },
7031
  { 1, true },
7032
  { 1, true },
7033
  { 1, true },
7034
  { 1, true },
7035
  { 0, true },
7036
  { 0, true },
7037
  { 0, true },
7038
  { 0, true },
7039
  { 0, true },
7040
  { 0, true },
7041
  { 0, true },
7042
  { 0, true },
7043
  { 0, true },
7044
  { 0, true },
7045
  { 0, true },
7046
  { 0, true },
7047
  { 0, true },
7048
  { 0, true },
7049
  { 0, true },
7050
  { 0, true },
7051
  { 0, true },
7052
  { 0, true },
7053
  { 0, true },
7054
  { 0, true },
7055
  { 0, true },
7056
  { 0, true },
7057
  { 0, true },
7058
  { 0, true },
7059
  { 0, true },
7060
  { 0, true },
7061
  { 0, true },
7062
  { 0, true },
7063
  { 0, true },
7064
  { 0, true },
7065
  { 0, true },
7066
  { 0, true },
7067
  { 0, true },
7068
  { 0, true },
7069
  { 0, true },
7070
  { 0, true },
7071
  { 0, true },
7072
  { 0, true },
7073
  { 0, true },
7074
  { 0, true },
7075
  { 0, true },
7076
  { 0, true },
7077
  { 0, true },
7078
  { 0, true },
7079
  { 0, true },
7080
  { 0, true },
7081
  { 0, true },
7082
  { 0, true },
7083
  { 0, true },
7084
  { 0, true },
7085
  { 0, true },
7086
  { 0, true },
7087
  { 0, true },
7088
  { 0, true },
7089
  { 0, true },
7090
  { 0, true },
7091
  { 0, true },
7092
  { 0, true },
7093
  { 0, true },
7094
  { 0, true },
7095
  { 0, true },
7096
  { 0, true },
7097
  { 0, true },
7098
  { 0, true },
7099
  { 0, true },
7100
  { 0, true },
7101
  { 0, true },
7102
  { 0, true },
7103
  { 0, true },
7104
  { 0, true },
7105
  { 0, true },
7106
  { 0, true },
7107
  { 0, true },
7108
  { 0, true },
7109
  { 0, true },
7110
  { 0, true },
7111
  { 0, true },
7112
  { 0, true },
7113
  { 0, true },
7114
  { 0, true },
7115
  { 0, true },
7116
  { 0, true },
7117
  { 0, true },
7118
  { 0, true },
7119
  { 0, true },
7120
  { 0, true },
7121
  { 0, true },
7122
  { 0, true },
7123
  { 0, true },
7124
  { 0, true },
7125
  { 1, true },
7126
  { 0, true },
7127
  { 0, true },
7128
  { 0, true },
7129
  { 0, true },
7130
  { 1, true },
7131
  { 1, true },
7132
  { 0, true },
7133
  { 0, true },
7134
  { 0, true },
7135
  { 0, true },
7136
  { 0, true },
7137
  { 0, true },
7138
  { 0, true },
7139
  { 0, true },
7140
  { 0, true },
7141
  { 0, true },
7142
  { 0, true },
7143
  { 0, true },
7144
  { 0, true },
7145
  { 0, true },
7146
  { 0, true },
7147
  { 0, true },
7148
  { 0, true },
7149
  { 0, true },
7150
  { 0, true },
7151
  { 0, true },
7152
  { 0, true },
7153
  { 0, true },
7154
  { 0, true },
7155
  { 0, true },
7156
  { 0, true },
7157
  { 0, true },
7158
  { 0, true },
7159
  { 0, true },
7160
  { 0, true },
7161
  { 0, true },
7162
  { 0, true },
7163
  { 0, true },
7164
  { 0, true },
7165
  { 0, true },
7166
  { 0, true },
7167
  { 0, true },
7168
  { 0, true },
7169
  { 0, true },
7170
  { 0, true },
7171
  { 0, true },
7172
  { 0, true },
7173
  { 0, true },
7174
  { 0, true },
7175
  { 0, true },
7176
  { 0, true },
7177
  { 0, true },
7178
  { 0, true },
7179
  { 0, true },
7180
  { 0, true },
7181
  { 0, true },
7182
  { 0, true },
7183
  { 0, true },
7184
  { 0, true },
7185
  { 0, true },
7186
  { 0, true },
7187
  { 0, true },
7188
  { 0, true },
7189
  { 0, true },
7190
  { 0, false },
7191
  { 0, false },
7192
  { 0, false },
7193
  { 0, false },
7194
  { 0, false },
7195
  { 0, false },
7196
  { 0, false },
7197
  { 0, false },
7198
  { 0, false },
7199
  { 0, false },
7200
  { 0, false },
7201
  { 0, false },
7202
  { 0, false },
7203
  { 0, false },
7204
  { 0, false },
7205
  { 0, false },
7206
  { 0, false },
7207
  { 0, false },
7208
  { 0, false },
7209
  { 0, false },
7210
  { 0, false },
7211
  { 0, false },
7212
  { 0, false },
7213
  { 0, false },
7214
  { 0, false },
7215
  { 0, false },
7216
  { 0, true },
7217
  { 0, true },
7218
  { 0, true },
7219
  { 0, true },
7220
  { 0, true },
7221
  { 0, true },
7222
  { 0, true },
7223
  { 0, true },
7224
  { 0, true },
7225
  { 0, true },
7226
  { 0, true },
7227
  { 0, true },
7228
  { 0, true },
7229
  { 0, true },
7230
  { 0, true },
7231
  { 0, true },
7232
  { 0, true },
7233
  { 0, true },
7234
  { 0, true },
7235
  { 0, true },
7236
  { 0, true },
7237
  { 0, true },
7238
  { 0, true },
7239
  { 0, true },
7240
  { 0, true },
7241
  { 0, true },
7242
  { 0, true },
7243
  { 0, true },
7244
  { 0, true },
7245
};
7246
2.30k
unsigned ARMGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
7247
2.30k
  static const uint8_t RowMap[56] = {
7248
2.30k
    0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 4, 0, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 5, 5, 5, 2, 
7249
2.30k
  };
7250
2.30k
  static const uint8_t Rows[8][56] = {
7251
2.30k
    { 1, 2, 3, 4, 5, 0, 7, 0, 0, 0, 0, 0, 13, 14, 0, 0, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 0, 0, 29, 30, 0, 0, 33, 34, 35, 36, 37, 38, 0, 0, 0, 0, 43, 0, 45, 0, 0, 0, 0, 0, 51, 0, 0, 0, 0, 0, },
7252
2.30k
    { 2, 3, 4, 5, 6, 0, 8, 0, 0, 0, 0, 0, 37, 49, 0, 0, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 0, 0, 31, 32, 0, 0, 35, 36, 43, 44, 14, 40, 0, 0, 0, 0, 46, 0, 48, 0, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, },
7253
2.30k
    { 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 14, 15, 0, 0, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 0, 0, 0, 0, 0, 0, 43, 44, 46, 47, 49, 0, 0, 0, 0, 0, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7254
2.30k
    { 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 49, 55, 0, 0, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 46, 47, 51, 52, 15, 0, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7255
2.30k
    { 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 15, 16, 0, 0, 25, 26, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 51, 52, 53, 54, 55, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7256
2.30k
    { 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 55, 0, 0, 0, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 53, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7257
2.30k
    { 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7258
2.30k
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7259
2.30k
  };
7260
2.30k
7261
2.30k
  --IdxA; assert(IdxA < 56);
7262
2.30k
  --IdxB; assert(IdxB < 56);
7263
2.30k
  return Rows[RowMap[IdxA]][IdxB];
7264
2.30k
}
7265
7266
  struct MaskRolOp {
7267
    LaneBitmask Mask;
7268
    uint8_t  RotateLeft;
7269
  };
7270
  static const MaskRolOp LaneMaskComposeSequences[] = {
7271
    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
7272
    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
7273
    { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
7274
    { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
7275
    { LaneBitmask(0xFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
7276
    { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
7277
    { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
7278
    { LaneBitmask(0xFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
7279
    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 16
7280
    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 18
7281
    { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 20
7282
    { LaneBitmask(0xFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 22
7283
    { LaneBitmask(0xFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 24
7284
    { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 26
7285
    { LaneBitmask(0xFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 28
7286
    { LaneBitmask(0xFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 },   // Sequence 30
7287
    { LaneBitmask(0xFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 },   // Sequence 32
7288
    { LaneBitmask(0xFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 }  // Sequence 34
7289
  };
7290
  static const MaskRolOp *const CompositeSequences[] = {
7291
    &LaneMaskComposeSequences[0], // to dsub_0
7292
    &LaneMaskComposeSequences[2], // to dsub_1
7293
    &LaneMaskComposeSequences[4], // to dsub_2
7294
    &LaneMaskComposeSequences[6], // to dsub_3
7295
    &LaneMaskComposeSequences[8], // to dsub_4
7296
    &LaneMaskComposeSequences[10], // to dsub_5
7297
    &LaneMaskComposeSequences[12], // to dsub_6
7298
    &LaneMaskComposeSequences[14], // to dsub_7
7299
    &LaneMaskComposeSequences[0], // to gsub_0
7300
    &LaneMaskComposeSequences[16], // to gsub_1
7301
    &LaneMaskComposeSequences[0], // to qqsub_0
7302
    &LaneMaskComposeSequences[8], // to qqsub_1
7303
    &LaneMaskComposeSequences[0], // to qsub_0
7304
    &LaneMaskComposeSequences[4], // to qsub_1
7305
    &LaneMaskComposeSequences[8], // to qsub_2
7306
    &LaneMaskComposeSequences[12], // to qsub_3
7307
    &LaneMaskComposeSequences[2], // to ssub_0
7308
    &LaneMaskComposeSequences[18], // to ssub_1
7309
    &LaneMaskComposeSequences[4], // to ssub_2
7310
    &LaneMaskComposeSequences[20], // to ssub_3
7311
    &LaneMaskComposeSequences[6], // to ssub_4
7312
    &LaneMaskComposeSequences[22], // to ssub_5
7313
    &LaneMaskComposeSequences[8], // to ssub_6
7314
    &LaneMaskComposeSequences[24], // to ssub_7
7315
    &LaneMaskComposeSequences[10], // to ssub_8
7316
    &LaneMaskComposeSequences[26], // to ssub_9
7317
    &LaneMaskComposeSequences[12], // to ssub_10
7318
    &LaneMaskComposeSequences[28], // to ssub_11
7319
    &LaneMaskComposeSequences[14], // to ssub_12
7320
    &LaneMaskComposeSequences[30], // to ssub_13
7321
    &LaneMaskComposeSequences[32], // to dsub_7_then_ssub_0
7322
    &LaneMaskComposeSequences[34], // to dsub_7_then_ssub_1
7323
    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5
7324
    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7325
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7
7326
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7327
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5
7328
    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7329
    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7330
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7331
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7332
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7333
    &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9
7334
    &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7335
    &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7336
    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5
7337
    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7338
    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5_dsub_7
7339
    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9
7340
    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7341
    &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_ssub_12_ssub_13
7342
    &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7343
    &LaneMaskComposeSequences[10], // to dsub_5_dsub_7
7344
    &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13_dsub_7
7345
    &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13
7346
    &LaneMaskComposeSequences[4] // to ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7347
  };
7348
7349
0
LaneBitmask ARMGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
7350
0
  --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
7351
0
  LaneBitmask Result;
7352
0
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; 
Ops->Mask.any()0
;
++Ops0
) {
7353
0
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
7354
0
    if (unsigned S = Ops->RotateLeft)
7355
0
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
7356
0
    else
7357
0
      Result |= LaneBitmask(M);
7358
0
  }
7359
0
  return Result;
7360
0
}
7361
7362
0
LaneBitmask ARMGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
7363
0
  LaneMask &= getSubRegIndexLaneMask(IdxA);
7364
0
  --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
7365
0
  LaneBitmask Result;
7366
0
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; 
Ops->Mask.any()0
;
++Ops0
) {
7367
0
    LaneBitmask::Type M = LaneMask.getAsInteger();
7368
0
    if (unsigned S = Ops->RotateLeft)
7369
0
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
7370
0
    else
7371
0
      Result |= LaneBitmask(M);
7372
0
  }
7373
0
  return Result;
7374
0
}
7375
7376
11.5k
const TargetRegisterClass *ARMGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
7377
11.5k
  static const uint8_t Table[102][56] = {
7378
11.5k
    { // SPR
7379
11.5k
      0,  // dsub_0
7380
11.5k
      0,  // dsub_1
7381
11.5k
      0,  // dsub_2
7382
11.5k
      0,  // dsub_3
7383
11.5k
      0,  // dsub_4
7384
11.5k
      0,  // dsub_5
7385
11.5k
      0,  // dsub_6
7386
11.5k
      0,  // dsub_7
7387
11.5k
      0,  // gsub_0
7388
11.5k
      0,  // gsub_1
7389
11.5k
      0,  // qqsub_0
7390
11.5k
      0,  // qqsub_1
7391
11.5k
      0,  // qsub_0
7392
11.5k
      0,  // qsub_1
7393
11.5k
      0,  // qsub_2
7394
11.5k
      0,  // qsub_3
7395
11.5k
      0,  // ssub_0
7396
11.5k
      0,  // ssub_1
7397
11.5k
      0,  // ssub_2
7398
11.5k
      0,  // ssub_3
7399
11.5k
      0,  // ssub_4
7400
11.5k
      0,  // ssub_5
7401
11.5k
      0,  // ssub_6
7402
11.5k
      0,  // ssub_7
7403
11.5k
      0,  // ssub_8
7404
11.5k
      0,  // ssub_9
7405
11.5k
      0,  // ssub_10
7406
11.5k
      0,  // ssub_11
7407
11.5k
      0,  // ssub_12
7408
11.5k
      0,  // ssub_13
7409
11.5k
      0,  // dsub_7_then_ssub_0
7410
11.5k
      0,  // dsub_7_then_ssub_1
7411
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
7412
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7413
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
7414
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7415
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
7416
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7417
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7418
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7419
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7420
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7421
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
7422
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7423
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7424
11.5k
      0,  // ssub_6_ssub_7_dsub_5
7425
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7426
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
7427
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
7428
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7429
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
7430
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7431
11.5k
      0,  // dsub_5_dsub_7
7432
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
7433
11.5k
      0,  // dsub_5_ssub_12_ssub_13
7434
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7435
11.5k
    },
7436
11.5k
    { // GPR
7437
11.5k
      0,  // dsub_0
7438
11.5k
      0,  // dsub_1
7439
11.5k
      0,  // dsub_2
7440
11.5k
      0,  // dsub_3
7441
11.5k
      0,  // dsub_4
7442
11.5k
      0,  // dsub_5
7443
11.5k
      0,  // dsub_6
7444
11.5k
      0,  // dsub_7
7445
11.5k
      0,  // gsub_0
7446
11.5k
      0,  // gsub_1
7447
11.5k
      0,  // qqsub_0
7448
11.5k
      0,  // qqsub_1
7449
11.5k
      0,  // qsub_0
7450
11.5k
      0,  // qsub_1
7451
11.5k
      0,  // qsub_2
7452
11.5k
      0,  // qsub_3
7453
11.5k
      0,  // ssub_0
7454
11.5k
      0,  // ssub_1
7455
11.5k
      0,  // ssub_2
7456
11.5k
      0,  // ssub_3
7457
11.5k
      0,  // ssub_4
7458
11.5k
      0,  // ssub_5
7459
11.5k
      0,  // ssub_6
7460
11.5k
      0,  // ssub_7
7461
11.5k
      0,  // ssub_8
7462
11.5k
      0,  // ssub_9
7463
11.5k
      0,  // ssub_10
7464
11.5k
      0,  // ssub_11
7465
11.5k
      0,  // ssub_12
7466
11.5k
      0,  // ssub_13
7467
11.5k
      0,  // dsub_7_then_ssub_0
7468
11.5k
      0,  // dsub_7_then_ssub_1
7469
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
7470
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7471
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
7472
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7473
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
7474
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7475
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7476
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7477
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7478
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7479
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
7480
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7481
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7482
11.5k
      0,  // ssub_6_ssub_7_dsub_5
7483
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7484
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
7485
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
7486
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7487
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
7488
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7489
11.5k
      0,  // dsub_5_dsub_7
7490
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
7491
11.5k
      0,  // dsub_5_ssub_12_ssub_13
7492
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7493
11.5k
    },
7494
11.5k
    { // GPRwithAPSR
7495
11.5k
      0,  // dsub_0
7496
11.5k
      0,  // dsub_1
7497
11.5k
      0,  // dsub_2
7498
11.5k
      0,  // dsub_3
7499
11.5k
      0,  // dsub_4
7500
11.5k
      0,  // dsub_5
7501
11.5k
      0,  // dsub_6
7502
11.5k
      0,  // dsub_7
7503
11.5k
      0,  // gsub_0
7504
11.5k
      0,  // gsub_1
7505
11.5k
      0,  // qqsub_0
7506
11.5k
      0,  // qqsub_1
7507
11.5k
      0,  // qsub_0
7508
11.5k
      0,  // qsub_1
7509
11.5k
      0,  // qsub_2
7510
11.5k
      0,  // qsub_3
7511
11.5k
      0,  // ssub_0
7512
11.5k
      0,  // ssub_1
7513
11.5k
      0,  // ssub_2
7514
11.5k
      0,  // ssub_3
7515
11.5k
      0,  // ssub_4
7516
11.5k
      0,  // ssub_5
7517
11.5k
      0,  // ssub_6
7518
11.5k
      0,  // ssub_7
7519
11.5k
      0,  // ssub_8
7520
11.5k
      0,  // ssub_9
7521
11.5k
      0,  // ssub_10
7522
11.5k
      0,  // ssub_11
7523
11.5k
      0,  // ssub_12
7524
11.5k
      0,  // ssub_13
7525
11.5k
      0,  // dsub_7_then_ssub_0
7526
11.5k
      0,  // dsub_7_then_ssub_1
7527
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
7528
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7529
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
7530
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7531
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
7532
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7533
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7534
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7535
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7536
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7537
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
7538
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7539
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7540
11.5k
      0,  // ssub_6_ssub_7_dsub_5
7541
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7542
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
7543
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
7544
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7545
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
7546
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7547
11.5k
      0,  // dsub_5_dsub_7
7548
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
7549
11.5k
      0,  // dsub_5_ssub_12_ssub_13
7550
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7551
11.5k
    },
7552
11.5k
    { // SPR_8
7553
11.5k
      0,  // dsub_0
7554
11.5k
      0,  // dsub_1
7555
11.5k
      0,  // dsub_2
7556
11.5k
      0,  // dsub_3
7557
11.5k
      0,  // dsub_4
7558
11.5k
      0,  // dsub_5
7559
11.5k
      0,  // dsub_6
7560
11.5k
      0,  // dsub_7
7561
11.5k
      0,  // gsub_0
7562
11.5k
      0,  // gsub_1
7563
11.5k
      0,  // qqsub_0
7564
11.5k
      0,  // qqsub_1
7565
11.5k
      0,  // qsub_0
7566
11.5k
      0,  // qsub_1
7567
11.5k
      0,  // qsub_2
7568
11.5k
      0,  // qsub_3
7569
11.5k
      0,  // ssub_0
7570
11.5k
      0,  // ssub_1
7571
11.5k
      0,  // ssub_2
7572
11.5k
      0,  // ssub_3
7573
11.5k
      0,  // ssub_4
7574
11.5k
      0,  // ssub_5
7575
11.5k
      0,  // ssub_6
7576
11.5k
      0,  // ssub_7
7577
11.5k
      0,  // ssub_8
7578
11.5k
      0,  // ssub_9
7579
11.5k
      0,  // ssub_10
7580
11.5k
      0,  // ssub_11
7581
11.5k
      0,  // ssub_12
7582
11.5k
      0,  // ssub_13
7583
11.5k
      0,  // dsub_7_then_ssub_0
7584
11.5k
      0,  // dsub_7_then_ssub_1
7585
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
7586
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7587
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
7588
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7589
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
7590
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7591
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7592
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7593
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7594
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7595
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
7596
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7597
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7598
11.5k
      0,  // ssub_6_ssub_7_dsub_5
7599
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7600
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
7601
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
7602
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7603
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
7604
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7605
11.5k
      0,  // dsub_5_dsub_7
7606
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
7607
11.5k
      0,  // dsub_5_ssub_12_ssub_13
7608
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7609
11.5k
    },
7610
11.5k
    { // GPRnopc
7611
11.5k
      0,  // dsub_0
7612
11.5k
      0,  // dsub_1
7613
11.5k
      0,  // dsub_2
7614
11.5k
      0,  // dsub_3
7615
11.5k
      0,  // dsub_4
7616
11.5k
      0,  // dsub_5
7617
11.5k
      0,  // dsub_6
7618
11.5k
      0,  // dsub_7
7619
11.5k
      0,  // gsub_0
7620
11.5k
      0,  // gsub_1
7621
11.5k
      0,  // qqsub_0
7622
11.5k
      0,  // qqsub_1
7623
11.5k
      0,  // qsub_0
7624
11.5k
      0,  // qsub_1
7625
11.5k
      0,  // qsub_2
7626
11.5k
      0,  // qsub_3
7627
11.5k
      0,  // ssub_0
7628
11.5k
      0,  // ssub_1
7629
11.5k
      0,  // ssub_2
7630
11.5k
      0,  // ssub_3
7631
11.5k
      0,  // ssub_4
7632
11.5k
      0,  // ssub_5
7633
11.5k
      0,  // ssub_6
7634
11.5k
      0,  // ssub_7
7635
11.5k
      0,  // ssub_8
7636
11.5k
      0,  // ssub_9
7637
11.5k
      0,  // ssub_10
7638
11.5k
      0,  // ssub_11
7639
11.5k
      0,  // ssub_12
7640
11.5k
      0,  // ssub_13
7641
11.5k
      0,  // dsub_7_then_ssub_0
7642
11.5k
      0,  // dsub_7_then_ssub_1
7643
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
7644
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7645
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
7646
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7647
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
7648
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7649
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7650
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7651
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7652
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7653
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
7654
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7655
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7656
11.5k
      0,  // ssub_6_ssub_7_dsub_5
7657
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7658
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
7659
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
7660
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7661
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
7662
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7663
11.5k
      0,  // dsub_5_dsub_7
7664
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
7665
11.5k
      0,  // dsub_5_ssub_12_ssub_13
7666
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7667
11.5k
    },
7668
11.5k
    { // rGPR
7669
11.5k
      0,  // dsub_0
7670
11.5k
      0,  // dsub_1
7671
11.5k
      0,  // dsub_2
7672
11.5k
      0,  // dsub_3
7673
11.5k
      0,  // dsub_4
7674
11.5k
      0,  // dsub_5
7675
11.5k
      0,  // dsub_6
7676
11.5k
      0,  // dsub_7
7677
11.5k
      0,  // gsub_0
7678
11.5k
      0,  // gsub_1
7679
11.5k
      0,  // qqsub_0
7680
11.5k
      0,  // qqsub_1
7681
11.5k
      0,  // qsub_0
7682
11.5k
      0,  // qsub_1
7683
11.5k
      0,  // qsub_2
7684
11.5k
      0,  // qsub_3
7685
11.5k
      0,  // ssub_0
7686
11.5k
      0,  // ssub_1
7687
11.5k
      0,  // ssub_2
7688
11.5k
      0,  // ssub_3
7689
11.5k
      0,  // ssub_4
7690
11.5k
      0,  // ssub_5
7691
11.5k
      0,  // ssub_6
7692
11.5k
      0,  // ssub_7
7693
11.5k
      0,  // ssub_8
7694
11.5k
      0,  // ssub_9
7695
11.5k
      0,  // ssub_10
7696
11.5k
      0,  // ssub_11
7697
11.5k
      0,  // ssub_12
7698
11.5k
      0,  // ssub_13
7699
11.5k
      0,  // dsub_7_then_ssub_0
7700
11.5k
      0,  // dsub_7_then_ssub_1
7701
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
7702
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7703
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
7704
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7705
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
7706
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7707
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7708
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7709
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7710
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7711
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
7712
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7713
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7714
11.5k
      0,  // ssub_6_ssub_7_dsub_5
7715
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7716
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
7717
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
7718
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7719
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
7720
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7721
11.5k
      0,  // dsub_5_dsub_7
7722
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
7723
11.5k
      0,  // dsub_5_ssub_12_ssub_13
7724
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7725
11.5k
    },
7726
11.5k
    { // tGPRwithpc
7727
11.5k
      0,  // dsub_0
7728
11.5k
      0,  // dsub_1
7729
11.5k
      0,  // dsub_2
7730
11.5k
      0,  // dsub_3
7731
11.5k
      0,  // dsub_4
7732
11.5k
      0,  // dsub_5
7733
11.5k
      0,  // dsub_6
7734
11.5k
      0,  // dsub_7
7735
11.5k
      0,  // gsub_0
7736
11.5k
      0,  // gsub_1
7737
11.5k
      0,  // qqsub_0
7738
11.5k
      0,  // qqsub_1
7739
11.5k
      0,  // qsub_0
7740
11.5k
      0,  // qsub_1
7741
11.5k
      0,  // qsub_2
7742
11.5k
      0,  // qsub_3
7743
11.5k
      0,  // ssub_0
7744
11.5k
      0,  // ssub_1
7745
11.5k
      0,  // ssub_2
7746
11.5k
      0,  // ssub_3
7747
11.5k
      0,  // ssub_4
7748
11.5k
      0,  // ssub_5
7749
11.5k
      0,  // ssub_6
7750
11.5k
      0,  // ssub_7
7751
11.5k
      0,  // ssub_8
7752
11.5k
      0,  // ssub_9
7753
11.5k
      0,  // ssub_10
7754
11.5k
      0,  // ssub_11
7755
11.5k
      0,  // ssub_12
7756
11.5k
      0,  // ssub_13
7757
11.5k
      0,  // dsub_7_then_ssub_0
7758
11.5k
      0,  // dsub_7_then_ssub_1
7759
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
7760
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7761
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
7762
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7763
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
7764
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7765
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7766
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7767
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7768
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7769
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
7770
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7771
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7772
11.5k
      0,  // ssub_6_ssub_7_dsub_5
7773
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7774
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
7775
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
7776
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7777
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
7778
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7779
11.5k
      0,  // dsub_5_dsub_7
7780
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
7781
11.5k
      0,  // dsub_5_ssub_12_ssub_13
7782
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7783
11.5k
    },
7784
11.5k
    { // hGPR
7785
11.5k
      0,  // dsub_0
7786
11.5k
      0,  // dsub_1
7787
11.5k
      0,  // dsub_2
7788
11.5k
      0,  // dsub_3
7789
11.5k
      0,  // dsub_4
7790
11.5k
      0,  // dsub_5
7791
11.5k
      0,  // dsub_6
7792
11.5k
      0,  // dsub_7
7793
11.5k
      0,  // gsub_0
7794
11.5k
      0,  // gsub_1
7795
11.5k
      0,  // qqsub_0
7796
11.5k
      0,  // qqsub_1
7797
11.5k
      0,  // qsub_0
7798
11.5k
      0,  // qsub_1
7799
11.5k
      0,  // qsub_2
7800
11.5k
      0,  // qsub_3
7801
11.5k
      0,  // ssub_0
7802
11.5k
      0,  // ssub_1
7803
11.5k
      0,  // ssub_2
7804
11.5k
      0,  // ssub_3
7805
11.5k
      0,  // ssub_4
7806
11.5k
      0,  // ssub_5
7807
11.5k
      0,  // ssub_6
7808
11.5k
      0,  // ssub_7
7809
11.5k
      0,  // ssub_8
7810
11.5k
      0,  // ssub_9
7811
11.5k
      0,  // ssub_10
7812
11.5k
      0,  // ssub_11
7813
11.5k
      0,  // ssub_12
7814
11.5k
      0,  // ssub_13
7815
11.5k
      0,  // dsub_7_then_ssub_0
7816
11.5k
      0,  // dsub_7_then_ssub_1
7817
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
7818
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7819
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
7820
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7821
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
7822
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7823
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7824
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7825
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7826
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7827
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
7828
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7829
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7830
11.5k
      0,  // ssub_6_ssub_7_dsub_5
7831
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7832
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
7833
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
7834
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7835
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
7836
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7837
11.5k
      0,  // dsub_5_dsub_7
7838
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
7839
11.5k
      0,  // dsub_5_ssub_12_ssub_13
7840
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7841
11.5k
    },
7842
11.5k
    { // tGPR
7843
11.5k
      0,  // dsub_0
7844
11.5k
      0,  // dsub_1
7845
11.5k
      0,  // dsub_2
7846
11.5k
      0,  // dsub_3
7847
11.5k
      0,  // dsub_4
7848
11.5k
      0,  // dsub_5
7849
11.5k
      0,  // dsub_6
7850
11.5k
      0,  // dsub_7
7851
11.5k
      0,  // gsub_0
7852
11.5k
      0,  // gsub_1
7853
11.5k
      0,  // qqsub_0
7854
11.5k
      0,  // qqsub_1
7855
11.5k
      0,  // qsub_0
7856
11.5k
      0,  // qsub_1
7857
11.5k
      0,  // qsub_2
7858
11.5k
      0,  // qsub_3
7859
11.5k
      0,  // ssub_0
7860
11.5k
      0,  // ssub_1
7861
11.5k
      0,  // ssub_2
7862
11.5k
      0,  // ssub_3
7863
11.5k
      0,  // ssub_4
7864
11.5k
      0,  // ssub_5
7865
11.5k
      0,  // ssub_6
7866
11.5k
      0,  // ssub_7
7867
11.5k
      0,  // ssub_8
7868
11.5k
      0,  // ssub_9
7869
11.5k
      0,  // ssub_10
7870
11.5k
      0,  // ssub_11
7871
11.5k
      0,  // ssub_12
7872
11.5k
      0,  // ssub_13
7873
11.5k
      0,  // dsub_7_then_ssub_0
7874
11.5k
      0,  // dsub_7_then_ssub_1
7875
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
7876
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7877
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
7878
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7879
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
7880
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7881
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7882
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7883
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7884
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7885
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
7886
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7887
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7888
11.5k
      0,  // ssub_6_ssub_7_dsub_5
7889
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7890
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
7891
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
7892
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7893
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
7894
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7895
11.5k
      0,  // dsub_5_dsub_7
7896
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
7897
11.5k
      0,  // dsub_5_ssub_12_ssub_13
7898
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7899
11.5k
    },
7900
11.5k
    { // GPRnopc_and_hGPR
7901
11.5k
      0,  // dsub_0
7902
11.5k
      0,  // dsub_1
7903
11.5k
      0,  // dsub_2
7904
11.5k
      0,  // dsub_3
7905
11.5k
      0,  // dsub_4
7906
11.5k
      0,  // dsub_5
7907
11.5k
      0,  // dsub_6
7908
11.5k
      0,  // dsub_7
7909
11.5k
      0,  // gsub_0
7910
11.5k
      0,  // gsub_1
7911
11.5k
      0,  // qqsub_0
7912
11.5k
      0,  // qqsub_1
7913
11.5k
      0,  // qsub_0
7914
11.5k
      0,  // qsub_1
7915
11.5k
      0,  // qsub_2
7916
11.5k
      0,  // qsub_3
7917
11.5k
      0,  // ssub_0
7918
11.5k
      0,  // ssub_1
7919
11.5k
      0,  // ssub_2
7920
11.5k
      0,  // ssub_3
7921
11.5k
      0,  // ssub_4
7922
11.5k
      0,  // ssub_5
7923
11.5k
      0,  // ssub_6
7924
11.5k
      0,  // ssub_7
7925
11.5k
      0,  // ssub_8
7926
11.5k
      0,  // ssub_9
7927
11.5k
      0,  // ssub_10
7928
11.5k
      0,  // ssub_11
7929
11.5k
      0,  // ssub_12
7930
11.5k
      0,  // ssub_13
7931
11.5k
      0,  // dsub_7_then_ssub_0
7932
11.5k
      0,  // dsub_7_then_ssub_1
7933
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
7934
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7935
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
7936
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7937
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
7938
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7939
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7940
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7941
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7942
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7943
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
7944
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7945
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7946
11.5k
      0,  // ssub_6_ssub_7_dsub_5
7947
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7948
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
7949
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
7950
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7951
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
7952
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7953
11.5k
      0,  // dsub_5_dsub_7
7954
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
7955
11.5k
      0,  // dsub_5_ssub_12_ssub_13
7956
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7957
11.5k
    },
7958
11.5k
    { // hGPR_and_rGPR
7959
11.5k
      0,  // dsub_0
7960
11.5k
      0,  // dsub_1
7961
11.5k
      0,  // dsub_2
7962
11.5k
      0,  // dsub_3
7963
11.5k
      0,  // dsub_4
7964
11.5k
      0,  // dsub_5
7965
11.5k
      0,  // dsub_6
7966
11.5k
      0,  // dsub_7
7967
11.5k
      0,  // gsub_0
7968
11.5k
      0,  // gsub_1
7969
11.5k
      0,  // qqsub_0
7970
11.5k
      0,  // qqsub_1
7971
11.5k
      0,  // qsub_0
7972
11.5k
      0,  // qsub_1
7973
11.5k
      0,  // qsub_2
7974
11.5k
      0,  // qsub_3
7975
11.5k
      0,  // ssub_0
7976
11.5k
      0,  // ssub_1
7977
11.5k
      0,  // ssub_2
7978
11.5k
      0,  // ssub_3
7979
11.5k
      0,  // ssub_4
7980
11.5k
      0,  // ssub_5
7981
11.5k
      0,  // ssub_6
7982
11.5k
      0,  // ssub_7
7983
11.5k
      0,  // ssub_8
7984
11.5k
      0,  // ssub_9
7985
11.5k
      0,  // ssub_10
7986
11.5k
      0,  // ssub_11
7987
11.5k
      0,  // ssub_12
7988
11.5k
      0,  // ssub_13
7989
11.5k
      0,  // dsub_7_then_ssub_0
7990
11.5k
      0,  // dsub_7_then_ssub_1
7991
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
7992
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7993
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
7994
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7995
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
7996
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7997
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7998
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7999
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8000
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8001
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8002
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8003
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8004
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8005
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8006
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8007
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8008
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8009
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8010
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8011
11.5k
      0,  // dsub_5_dsub_7
8012
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8013
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8014
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8015
11.5k
    },
8016
11.5k
    { // tcGPR
8017
11.5k
      0,  // dsub_0
8018
11.5k
      0,  // dsub_1
8019
11.5k
      0,  // dsub_2
8020
11.5k
      0,  // dsub_3
8021
11.5k
      0,  // dsub_4
8022
11.5k
      0,  // dsub_5
8023
11.5k
      0,  // dsub_6
8024
11.5k
      0,  // dsub_7
8025
11.5k
      0,  // gsub_0
8026
11.5k
      0,  // gsub_1
8027
11.5k
      0,  // qqsub_0
8028
11.5k
      0,  // qqsub_1
8029
11.5k
      0,  // qsub_0
8030
11.5k
      0,  // qsub_1
8031
11.5k
      0,  // qsub_2
8032
11.5k
      0,  // qsub_3
8033
11.5k
      0,  // ssub_0
8034
11.5k
      0,  // ssub_1
8035
11.5k
      0,  // ssub_2
8036
11.5k
      0,  // ssub_3
8037
11.5k
      0,  // ssub_4
8038
11.5k
      0,  // ssub_5
8039
11.5k
      0,  // ssub_6
8040
11.5k
      0,  // ssub_7
8041
11.5k
      0,  // ssub_8
8042
11.5k
      0,  // ssub_9
8043
11.5k
      0,  // ssub_10
8044
11.5k
      0,  // ssub_11
8045
11.5k
      0,  // ssub_12
8046
11.5k
      0,  // ssub_13
8047
11.5k
      0,  // dsub_7_then_ssub_0
8048
11.5k
      0,  // dsub_7_then_ssub_1
8049
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8050
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8051
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8052
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8053
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8054
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8055
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8056
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8057
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8058
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8059
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8060
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8061
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8062
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8063
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8064
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8065
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8066
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8067
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8068
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8069
11.5k
      0,  // dsub_5_dsub_7
8070
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8071
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8072
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8073
11.5k
    },
8074
11.5k
    { // tGPR_and_tcGPR
8075
11.5k
      0,  // dsub_0
8076
11.5k
      0,  // dsub_1
8077
11.5k
      0,  // dsub_2
8078
11.5k
      0,  // dsub_3
8079
11.5k
      0,  // dsub_4
8080
11.5k
      0,  // dsub_5
8081
11.5k
      0,  // dsub_6
8082
11.5k
      0,  // dsub_7
8083
11.5k
      0,  // gsub_0
8084
11.5k
      0,  // gsub_1
8085
11.5k
      0,  // qqsub_0
8086
11.5k
      0,  // qqsub_1
8087
11.5k
      0,  // qsub_0
8088
11.5k
      0,  // qsub_1
8089
11.5k
      0,  // qsub_2
8090
11.5k
      0,  // qsub_3
8091
11.5k
      0,  // ssub_0
8092
11.5k
      0,  // ssub_1
8093
11.5k
      0,  // ssub_2
8094
11.5k
      0,  // ssub_3
8095
11.5k
      0,  // ssub_4
8096
11.5k
      0,  // ssub_5
8097
11.5k
      0,  // ssub_6
8098
11.5k
      0,  // ssub_7
8099
11.5k
      0,  // ssub_8
8100
11.5k
      0,  // ssub_9
8101
11.5k
      0,  // ssub_10
8102
11.5k
      0,  // ssub_11
8103
11.5k
      0,  // ssub_12
8104
11.5k
      0,  // ssub_13
8105
11.5k
      0,  // dsub_7_then_ssub_0
8106
11.5k
      0,  // dsub_7_then_ssub_1
8107
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8108
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8109
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8110
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8111
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8112
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8113
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8114
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8115
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8116
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8117
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8118
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8119
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8120
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8121
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8122
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8123
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8124
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8125
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8126
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8127
11.5k
      0,  // dsub_5_dsub_7
8128
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8129
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8130
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8131
11.5k
    },
8132
11.5k
    { // CCR
8133
11.5k
      0,  // dsub_0
8134
11.5k
      0,  // dsub_1
8135
11.5k
      0,  // dsub_2
8136
11.5k
      0,  // dsub_3
8137
11.5k
      0,  // dsub_4
8138
11.5k
      0,  // dsub_5
8139
11.5k
      0,  // dsub_6
8140
11.5k
      0,  // dsub_7
8141
11.5k
      0,  // gsub_0
8142
11.5k
      0,  // gsub_1
8143
11.5k
      0,  // qqsub_0
8144
11.5k
      0,  // qqsub_1
8145
11.5k
      0,  // qsub_0
8146
11.5k
      0,  // qsub_1
8147
11.5k
      0,  // qsub_2
8148
11.5k
      0,  // qsub_3
8149
11.5k
      0,  // ssub_0
8150
11.5k
      0,  // ssub_1
8151
11.5k
      0,  // ssub_2
8152
11.5k
      0,  // ssub_3
8153
11.5k
      0,  // ssub_4
8154
11.5k
      0,  // ssub_5
8155
11.5k
      0,  // ssub_6
8156
11.5k
      0,  // ssub_7
8157
11.5k
      0,  // ssub_8
8158
11.5k
      0,  // ssub_9
8159
11.5k
      0,  // ssub_10
8160
11.5k
      0,  // ssub_11
8161
11.5k
      0,  // ssub_12
8162
11.5k
      0,  // ssub_13
8163
11.5k
      0,  // dsub_7_then_ssub_0
8164
11.5k
      0,  // dsub_7_then_ssub_1
8165
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8166
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8167
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8168
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8169
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8170
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8171
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8172
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8173
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8174
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8175
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8176
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8177
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8178
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8179
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8180
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8181
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8182
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8183
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8184
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8185
11.5k
      0,  // dsub_5_dsub_7
8186
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8187
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8188
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8189
11.5k
    },
8190
11.5k
    { // GPRsp
8191
11.5k
      0,  // dsub_0
8192
11.5k
      0,  // dsub_1
8193
11.5k
      0,  // dsub_2
8194
11.5k
      0,  // dsub_3
8195
11.5k
      0,  // dsub_4
8196
11.5k
      0,  // dsub_5
8197
11.5k
      0,  // dsub_6
8198
11.5k
      0,  // dsub_7
8199
11.5k
      0,  // gsub_0
8200
11.5k
      0,  // gsub_1
8201
11.5k
      0,  // qqsub_0
8202
11.5k
      0,  // qqsub_1
8203
11.5k
      0,  // qsub_0
8204
11.5k
      0,  // qsub_1
8205
11.5k
      0,  // qsub_2
8206
11.5k
      0,  // qsub_3
8207
11.5k
      0,  // ssub_0
8208
11.5k
      0,  // ssub_1
8209
11.5k
      0,  // ssub_2
8210
11.5k
      0,  // ssub_3
8211
11.5k
      0,  // ssub_4
8212
11.5k
      0,  // ssub_5
8213
11.5k
      0,  // ssub_6
8214
11.5k
      0,  // ssub_7
8215
11.5k
      0,  // ssub_8
8216
11.5k
      0,  // ssub_9
8217
11.5k
      0,  // ssub_10
8218
11.5k
      0,  // ssub_11
8219
11.5k
      0,  // ssub_12
8220
11.5k
      0,  // ssub_13
8221
11.5k
      0,  // dsub_7_then_ssub_0
8222
11.5k
      0,  // dsub_7_then_ssub_1
8223
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8224
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8225
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8226
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8227
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8228
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8229
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8230
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8231
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8232
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8233
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8234
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8235
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8236
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8237
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8238
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8239
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8240
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8241
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8242
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8243
11.5k
      0,  // dsub_5_dsub_7
8244
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8245
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8246
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8247
11.5k
    },
8248
11.5k
    { // hGPR_and_tGPRwithpc
8249
11.5k
      0,  // dsub_0
8250
11.5k
      0,  // dsub_1
8251
11.5k
      0,  // dsub_2
8252
11.5k
      0,  // dsub_3
8253
11.5k
      0,  // dsub_4
8254
11.5k
      0,  // dsub_5
8255
11.5k
      0,  // dsub_6
8256
11.5k
      0,  // dsub_7
8257
11.5k
      0,  // gsub_0
8258
11.5k
      0,  // gsub_1
8259
11.5k
      0,  // qqsub_0
8260
11.5k
      0,  // qqsub_1
8261
11.5k
      0,  // qsub_0
8262
11.5k
      0,  // qsub_1
8263
11.5k
      0,  // qsub_2
8264
11.5k
      0,  // qsub_3
8265
11.5k
      0,  // ssub_0
8266
11.5k
      0,  // ssub_1
8267
11.5k
      0,  // ssub_2
8268
11.5k
      0,  // ssub_3
8269
11.5k
      0,  // ssub_4
8270
11.5k
      0,  // ssub_5
8271
11.5k
      0,  // ssub_6
8272
11.5k
      0,  // ssub_7
8273
11.5k
      0,  // ssub_8
8274
11.5k
      0,  // ssub_9
8275
11.5k
      0,  // ssub_10
8276
11.5k
      0,  // ssub_11
8277
11.5k
      0,  // ssub_12
8278
11.5k
      0,  // ssub_13
8279
11.5k
      0,  // dsub_7_then_ssub_0
8280
11.5k
      0,  // dsub_7_then_ssub_1
8281
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8282
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8283
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8284
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8285
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8286
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8287
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8288
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8289
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8290
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8291
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8292
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8293
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8294
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8295
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8296
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8297
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8298
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8299
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8300
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8301
11.5k
      0,  // dsub_5_dsub_7
8302
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8303
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8304
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8305
11.5k
    },
8306
11.5k
    { // hGPR_and_tcGPR
8307
11.5k
      0,  // dsub_0
8308
11.5k
      0,  // dsub_1
8309
11.5k
      0,  // dsub_2
8310
11.5k
      0,  // dsub_3
8311
11.5k
      0,  // dsub_4
8312
11.5k
      0,  // dsub_5
8313
11.5k
      0,  // dsub_6
8314
11.5k
      0,  // dsub_7
8315
11.5k
      0,  // gsub_0
8316
11.5k
      0,  // gsub_1
8317
11.5k
      0,  // qqsub_0
8318
11.5k
      0,  // qqsub_1
8319
11.5k
      0,  // qsub_0
8320
11.5k
      0,  // qsub_1
8321
11.5k
      0,  // qsub_2
8322
11.5k
      0,  // qsub_3
8323
11.5k
      0,  // ssub_0
8324
11.5k
      0,  // ssub_1
8325
11.5k
      0,  // ssub_2
8326
11.5k
      0,  // ssub_3
8327
11.5k
      0,  // ssub_4
8328
11.5k
      0,  // ssub_5
8329
11.5k
      0,  // ssub_6
8330
11.5k
      0,  // ssub_7
8331
11.5k
      0,  // ssub_8
8332
11.5k
      0,  // ssub_9
8333
11.5k
      0,  // ssub_10
8334
11.5k
      0,  // ssub_11
8335
11.5k
      0,  // ssub_12
8336
11.5k
      0,  // ssub_13
8337
11.5k
      0,  // dsub_7_then_ssub_0
8338
11.5k
      0,  // dsub_7_then_ssub_1
8339
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8340
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8341
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8342
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8343
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8344
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8345
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8346
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8347
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8348
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8349
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8350
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8351
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8352
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8353
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8354
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8355
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8356
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8357
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8358
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8359
11.5k
      0,  // dsub_5_dsub_7
8360
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8361
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8362
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8363
11.5k
    },
8364
11.5k
    { // DPR
8365
11.5k
      0,  // dsub_0
8366
11.5k
      0,  // dsub_1
8367
11.5k
      0,  // dsub_2
8368
11.5k
      0,  // dsub_3
8369
11.5k
      0,  // dsub_4
8370
11.5k
      0,  // dsub_5
8371
11.5k
      0,  // dsub_6
8372
11.5k
      0,  // dsub_7
8373
11.5k
      0,  // gsub_0
8374
11.5k
      0,  // gsub_1
8375
11.5k
      0,  // qqsub_0
8376
11.5k
      0,  // qqsub_1
8377
11.5k
      0,  // qsub_0
8378
11.5k
      0,  // qsub_1
8379
11.5k
      0,  // qsub_2
8380
11.5k
      0,  // qsub_3
8381
11.5k
      19, // ssub_0 -> DPR_VFP2
8382
11.5k
      19, // ssub_1 -> DPR_VFP2
8383
11.5k
      0,  // ssub_2
8384
11.5k
      0,  // ssub_3
8385
11.5k
      0,  // ssub_4
8386
11.5k
      0,  // ssub_5
8387
11.5k
      0,  // ssub_6
8388
11.5k
      0,  // ssub_7
8389
11.5k
      0,  // ssub_8
8390
11.5k
      0,  // ssub_9
8391
11.5k
      0,  // ssub_10
8392
11.5k
      0,  // ssub_11
8393
11.5k
      0,  // ssub_12
8394
11.5k
      0,  // ssub_13
8395
11.5k
      0,  // dsub_7_then_ssub_0
8396
11.5k
      0,  // dsub_7_then_ssub_1
8397
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8398
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8399
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8400
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8401
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8402
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8403
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8404
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8405
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8406
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8407
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8408
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8409
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8410
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8411
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8412
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8413
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8414
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8415
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8416
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8417
11.5k
      0,  // dsub_5_dsub_7
8418
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8419
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8420
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8421
11.5k
    },
8422
11.5k
    { // DPR_VFP2
8423
11.5k
      0,  // dsub_0
8424
11.5k
      0,  // dsub_1
8425
11.5k
      0,  // dsub_2
8426
11.5k
      0,  // dsub_3
8427
11.5k
      0,  // dsub_4
8428
11.5k
      0,  // dsub_5
8429
11.5k
      0,  // dsub_6
8430
11.5k
      0,  // dsub_7
8431
11.5k
      0,  // gsub_0
8432
11.5k
      0,  // gsub_1
8433
11.5k
      0,  // qqsub_0
8434
11.5k
      0,  // qqsub_1
8435
11.5k
      0,  // qsub_0
8436
11.5k
      0,  // qsub_1
8437
11.5k
      0,  // qsub_2
8438
11.5k
      0,  // qsub_3
8439
11.5k
      19, // ssub_0 -> DPR_VFP2
8440
11.5k
      19, // ssub_1 -> DPR_VFP2
8441
11.5k
      0,  // ssub_2
8442
11.5k
      0,  // ssub_3
8443
11.5k
      0,  // ssub_4
8444
11.5k
      0,  // ssub_5
8445
11.5k
      0,  // ssub_6
8446
11.5k
      0,  // ssub_7
8447
11.5k
      0,  // ssub_8
8448
11.5k
      0,  // ssub_9
8449
11.5k
      0,  // ssub_10
8450
11.5k
      0,  // ssub_11
8451
11.5k
      0,  // ssub_12
8452
11.5k
      0,  // ssub_13
8453
11.5k
      0,  // dsub_7_then_ssub_0
8454
11.5k
      0,  // dsub_7_then_ssub_1
8455
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8456
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8457
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8458
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8459
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8460
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8461
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8462
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8463
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8464
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8465
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8466
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8467
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8468
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8469
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8470
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8471
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8472
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8473
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8474
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8475
11.5k
      0,  // dsub_5_dsub_7
8476
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8477
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8478
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8479
11.5k
    },
8480
11.5k
    { // DPR_8
8481
11.5k
      0,  // dsub_0
8482
11.5k
      0,  // dsub_1
8483
11.5k
      0,  // dsub_2
8484
11.5k
      0,  // dsub_3
8485
11.5k
      0,  // dsub_4
8486
11.5k
      0,  // dsub_5
8487
11.5k
      0,  // dsub_6
8488
11.5k
      0,  // dsub_7
8489
11.5k
      0,  // gsub_0
8490
11.5k
      0,  // gsub_1
8491
11.5k
      0,  // qqsub_0
8492
11.5k
      0,  // qqsub_1
8493
11.5k
      0,  // qsub_0
8494
11.5k
      0,  // qsub_1
8495
11.5k
      0,  // qsub_2
8496
11.5k
      0,  // qsub_3
8497
11.5k
      20, // ssub_0 -> DPR_8
8498
11.5k
      20, // ssub_1 -> DPR_8
8499
11.5k
      0,  // ssub_2
8500
11.5k
      0,  // ssub_3
8501
11.5k
      0,  // ssub_4
8502
11.5k
      0,  // ssub_5
8503
11.5k
      0,  // ssub_6
8504
11.5k
      0,  // ssub_7
8505
11.5k
      0,  // ssub_8
8506
11.5k
      0,  // ssub_9
8507
11.5k
      0,  // ssub_10
8508
11.5k
      0,  // ssub_11
8509
11.5k
      0,  // ssub_12
8510
11.5k
      0,  // ssub_13
8511
11.5k
      0,  // dsub_7_then_ssub_0
8512
11.5k
      0,  // dsub_7_then_ssub_1
8513
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8514
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8515
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8516
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8517
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8518
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8519
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8520
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8521
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8522
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8523
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8524
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8525
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8526
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8527
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8528
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8529
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8530
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8531
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8532
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8533
11.5k
      0,  // dsub_5_dsub_7
8534
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8535
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8536
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8537
11.5k
    },
8538
11.5k
    { // GPRPair
8539
11.5k
      0,  // dsub_0
8540
11.5k
      0,  // dsub_1
8541
11.5k
      0,  // dsub_2
8542
11.5k
      0,  // dsub_3
8543
11.5k
      0,  // dsub_4
8544
11.5k
      0,  // dsub_5
8545
11.5k
      0,  // dsub_6
8546
11.5k
      0,  // dsub_7
8547
11.5k
      21, // gsub_0 -> GPRPair
8548
11.5k
      21, // gsub_1 -> GPRPair
8549
11.5k
      0,  // qqsub_0
8550
11.5k
      0,  // qqsub_1
8551
11.5k
      0,  // qsub_0
8552
11.5k
      0,  // qsub_1
8553
11.5k
      0,  // qsub_2
8554
11.5k
      0,  // qsub_3
8555
11.5k
      0,  // ssub_0
8556
11.5k
      0,  // ssub_1
8557
11.5k
      0,  // ssub_2
8558
11.5k
      0,  // ssub_3
8559
11.5k
      0,  // ssub_4
8560
11.5k
      0,  // ssub_5
8561
11.5k
      0,  // ssub_6
8562
11.5k
      0,  // ssub_7
8563
11.5k
      0,  // ssub_8
8564
11.5k
      0,  // ssub_9
8565
11.5k
      0,  // ssub_10
8566
11.5k
      0,  // ssub_11
8567
11.5k
      0,  // ssub_12
8568
11.5k
      0,  // ssub_13
8569
11.5k
      0,  // dsub_7_then_ssub_0
8570
11.5k
      0,  // dsub_7_then_ssub_1
8571
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8572
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8573
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8574
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8575
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8576
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8577
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8578
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8579
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8580
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8581
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8582
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8583
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8584
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8585
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8586
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8587
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8588
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8589
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8590
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8591
11.5k
      0,  // dsub_5_dsub_7
8592
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8593
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8594
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8595
11.5k
    },
8596
11.5k
    { // GPRPair_with_gsub_1_in_rGPR
8597
11.5k
      0,  // dsub_0
8598
11.5k
      0,  // dsub_1
8599
11.5k
      0,  // dsub_2
8600
11.5k
      0,  // dsub_3
8601
11.5k
      0,  // dsub_4
8602
11.5k
      0,  // dsub_5
8603
11.5k
      0,  // dsub_6
8604
11.5k
      0,  // dsub_7
8605
11.5k
      22, // gsub_0 -> GPRPair_with_gsub_1_in_rGPR
8606
11.5k
      22, // gsub_1 -> GPRPair_with_gsub_1_in_rGPR
8607
11.5k
      0,  // qqsub_0
8608
11.5k
      0,  // qqsub_1
8609
11.5k
      0,  // qsub_0
8610
11.5k
      0,  // qsub_1
8611
11.5k
      0,  // qsub_2
8612
11.5k
      0,  // qsub_3
8613
11.5k
      0,  // ssub_0
8614
11.5k
      0,  // ssub_1
8615
11.5k
      0,  // ssub_2
8616
11.5k
      0,  // ssub_3
8617
11.5k
      0,  // ssub_4
8618
11.5k
      0,  // ssub_5
8619
11.5k
      0,  // ssub_6
8620
11.5k
      0,  // ssub_7
8621
11.5k
      0,  // ssub_8
8622
11.5k
      0,  // ssub_9
8623
11.5k
      0,  // ssub_10
8624
11.5k
      0,  // ssub_11
8625
11.5k
      0,  // ssub_12
8626
11.5k
      0,  // ssub_13
8627
11.5k
      0,  // dsub_7_then_ssub_0
8628
11.5k
      0,  // dsub_7_then_ssub_1
8629
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8630
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8631
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8632
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8633
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8634
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8635
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8636
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8637
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8638
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8639
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8640
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8641
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8642
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8643
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8644
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8645
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8646
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8647
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8648
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8649
11.5k
      0,  // dsub_5_dsub_7
8650
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8651
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8652
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8653
11.5k
    },
8654
11.5k
    { // GPRPair_with_gsub_0_in_tGPR
8655
11.5k
      0,  // dsub_0
8656
11.5k
      0,  // dsub_1
8657
11.5k
      0,  // dsub_2
8658
11.5k
      0,  // dsub_3
8659
11.5k
      0,  // dsub_4
8660
11.5k
      0,  // dsub_5
8661
11.5k
      0,  // dsub_6
8662
11.5k
      0,  // dsub_7
8663
11.5k
      23, // gsub_0 -> GPRPair_with_gsub_0_in_tGPR
8664
11.5k
      23, // gsub_1 -> GPRPair_with_gsub_0_in_tGPR
8665
11.5k
      0,  // qqsub_0
8666
11.5k
      0,  // qqsub_1
8667
11.5k
      0,  // qsub_0
8668
11.5k
      0,  // qsub_1
8669
11.5k
      0,  // qsub_2
8670
11.5k
      0,  // qsub_3
8671
11.5k
      0,  // ssub_0
8672
11.5k
      0,  // ssub_1
8673
11.5k
      0,  // ssub_2
8674
11.5k
      0,  // ssub_3
8675
11.5k
      0,  // ssub_4
8676
11.5k
      0,  // ssub_5
8677
11.5k
      0,  // ssub_6
8678
11.5k
      0,  // ssub_7
8679
11.5k
      0,  // ssub_8
8680
11.5k
      0,  // ssub_9
8681
11.5k
      0,  // ssub_10
8682
11.5k
      0,  // ssub_11
8683
11.5k
      0,  // ssub_12
8684
11.5k
      0,  // ssub_13
8685
11.5k
      0,  // dsub_7_then_ssub_0
8686
11.5k
      0,  // dsub_7_then_ssub_1
8687
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8688
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8689
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8690
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8691
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8692
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8693
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8694
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8695
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8696
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8697
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8698
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8699
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8700
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8701
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8702
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8703
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8704
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8705
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8706
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8707
11.5k
      0,  // dsub_5_dsub_7
8708
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8709
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8710
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8711
11.5k
    },
8712
11.5k
    { // GPRPair_with_gsub_0_in_hGPR
8713
11.5k
      0,  // dsub_0
8714
11.5k
      0,  // dsub_1
8715
11.5k
      0,  // dsub_2
8716
11.5k
      0,  // dsub_3
8717
11.5k
      0,  // dsub_4
8718
11.5k
      0,  // dsub_5
8719
11.5k
      0,  // dsub_6
8720
11.5k
      0,  // dsub_7
8721
11.5k
      24, // gsub_0 -> GPRPair_with_gsub_0_in_hGPR
8722
11.5k
      24, // gsub_1 -> GPRPair_with_gsub_0_in_hGPR
8723
11.5k
      0,  // qqsub_0
8724
11.5k
      0,  // qqsub_1
8725
11.5k
      0,  // qsub_0
8726
11.5k
      0,  // qsub_1
8727
11.5k
      0,  // qsub_2
8728
11.5k
      0,  // qsub_3
8729
11.5k
      0,  // ssub_0
8730
11.5k
      0,  // ssub_1
8731
11.5k
      0,  // ssub_2
8732
11.5k
      0,  // ssub_3
8733
11.5k
      0,  // ssub_4
8734
11.5k
      0,  // ssub_5
8735
11.5k
      0,  // ssub_6
8736
11.5k
      0,  // ssub_7
8737
11.5k
      0,  // ssub_8
8738
11.5k
      0,  // ssub_9
8739
11.5k
      0,  // ssub_10
8740
11.5k
      0,  // ssub_11
8741
11.5k
      0,  // ssub_12
8742
11.5k
      0,  // ssub_13
8743
11.5k
      0,  // dsub_7_then_ssub_0
8744
11.5k
      0,  // dsub_7_then_ssub_1
8745
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8746
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8747
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8748
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8749
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8750
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8751
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8752
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8753
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8754
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8755
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8756
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8757
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8758
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8759
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8760
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8761
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8762
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8763
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8764
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8765
11.5k
      0,  // dsub_5_dsub_7
8766
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8767
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8768
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8769
11.5k
    },
8770
11.5k
    { // GPRPair_with_gsub_0_in_tcGPR
8771
11.5k
      0,  // dsub_0
8772
11.5k
      0,  // dsub_1
8773
11.5k
      0,  // dsub_2
8774
11.5k
      0,  // dsub_3
8775
11.5k
      0,  // dsub_4
8776
11.5k
      0,  // dsub_5
8777
11.5k
      0,  // dsub_6
8778
11.5k
      0,  // dsub_7
8779
11.5k
      25, // gsub_0 -> GPRPair_with_gsub_0_in_tcGPR
8780
11.5k
      25, // gsub_1 -> GPRPair_with_gsub_0_in_tcGPR
8781
11.5k
      0,  // qqsub_0
8782
11.5k
      0,  // qqsub_1
8783
11.5k
      0,  // qsub_0
8784
11.5k
      0,  // qsub_1
8785
11.5k
      0,  // qsub_2
8786
11.5k
      0,  // qsub_3
8787
11.5k
      0,  // ssub_0
8788
11.5k
      0,  // ssub_1
8789
11.5k
      0,  // ssub_2
8790
11.5k
      0,  // ssub_3
8791
11.5k
      0,  // ssub_4
8792
11.5k
      0,  // ssub_5
8793
11.5k
      0,  // ssub_6
8794
11.5k
      0,  // ssub_7
8795
11.5k
      0,  // ssub_8
8796
11.5k
      0,  // ssub_9
8797
11.5k
      0,  // ssub_10
8798
11.5k
      0,  // ssub_11
8799
11.5k
      0,  // ssub_12
8800
11.5k
      0,  // ssub_13
8801
11.5k
      0,  // dsub_7_then_ssub_0
8802
11.5k
      0,  // dsub_7_then_ssub_1
8803
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8804
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8805
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8806
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8807
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8808
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8809
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8810
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8811
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8812
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8813
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8814
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8815
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8816
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8817
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8818
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8819
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8820
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8821
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8822
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8823
11.5k
      0,  // dsub_5_dsub_7
8824
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8825
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8826
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8827
11.5k
    },
8828
11.5k
    { // GPRPair_with_gsub_1_in_hGPR_and_rGPR
8829
11.5k
      0,  // dsub_0
8830
11.5k
      0,  // dsub_1
8831
11.5k
      0,  // dsub_2
8832
11.5k
      0,  // dsub_3
8833
11.5k
      0,  // dsub_4
8834
11.5k
      0,  // dsub_5
8835
11.5k
      0,  // dsub_6
8836
11.5k
      0,  // dsub_7
8837
11.5k
      26, // gsub_0 -> GPRPair_with_gsub_1_in_hGPR_and_rGPR
8838
11.5k
      26, // gsub_1 -> GPRPair_with_gsub_1_in_hGPR_and_rGPR
8839
11.5k
      0,  // qqsub_0
8840
11.5k
      0,  // qqsub_1
8841
11.5k
      0,  // qsub_0
8842
11.5k
      0,  // qsub_1
8843
11.5k
      0,  // qsub_2
8844
11.5k
      0,  // qsub_3
8845
11.5k
      0,  // ssub_0
8846
11.5k
      0,  // ssub_1
8847
11.5k
      0,  // ssub_2
8848
11.5k
      0,  // ssub_3
8849
11.5k
      0,  // ssub_4
8850
11.5k
      0,  // ssub_5
8851
11.5k
      0,  // ssub_6
8852
11.5k
      0,  // ssub_7
8853
11.5k
      0,  // ssub_8
8854
11.5k
      0,  // ssub_9
8855
11.5k
      0,  // ssub_10
8856
11.5k
      0,  // ssub_11
8857
11.5k
      0,  // ssub_12
8858
11.5k
      0,  // ssub_13
8859
11.5k
      0,  // dsub_7_then_ssub_0
8860
11.5k
      0,  // dsub_7_then_ssub_1
8861
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8862
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8863
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8864
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8865
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8866
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8867
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8868
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8869
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8870
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8871
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8872
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8873
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8874
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8875
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8876
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8877
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8878
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8879
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8880
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8881
11.5k
      0,  // dsub_5_dsub_7
8882
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8883
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8884
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8885
11.5k
    },
8886
11.5k
    { // GPRPair_with_gsub_1_in_tcGPR
8887
11.5k
      0,  // dsub_0
8888
11.5k
      0,  // dsub_1
8889
11.5k
      0,  // dsub_2
8890
11.5k
      0,  // dsub_3
8891
11.5k
      0,  // dsub_4
8892
11.5k
      0,  // dsub_5
8893
11.5k
      0,  // dsub_6
8894
11.5k
      0,  // dsub_7
8895
11.5k
      27, // gsub_0 -> GPRPair_with_gsub_1_in_tcGPR
8896
11.5k
      27, // gsub_1 -> GPRPair_with_gsub_1_in_tcGPR
8897
11.5k
      0,  // qqsub_0
8898
11.5k
      0,  // qqsub_1
8899
11.5k
      0,  // qsub_0
8900
11.5k
      0,  // qsub_1
8901
11.5k
      0,  // qsub_2
8902
11.5k
      0,  // qsub_3
8903
11.5k
      0,  // ssub_0
8904
11.5k
      0,  // ssub_1
8905
11.5k
      0,  // ssub_2
8906
11.5k
      0,  // ssub_3
8907
11.5k
      0,  // ssub_4
8908
11.5k
      0,  // ssub_5
8909
11.5k
      0,  // ssub_6
8910
11.5k
      0,  // ssub_7
8911
11.5k
      0,  // ssub_8
8912
11.5k
      0,  // ssub_9
8913
11.5k
      0,  // ssub_10
8914
11.5k
      0,  // ssub_11
8915
11.5k
      0,  // ssub_12
8916
11.5k
      0,  // ssub_13
8917
11.5k
      0,  // dsub_7_then_ssub_0
8918
11.5k
      0,  // dsub_7_then_ssub_1
8919
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8920
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8921
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8922
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8923
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8924
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8925
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8926
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8927
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8928
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8929
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8930
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8931
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8932
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8933
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8934
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8935
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8936
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8937
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8938
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8939
11.5k
      0,  // dsub_5_dsub_7
8940
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8941
11.5k
      0,  // dsub_5_ssub_12_ssub_13
8942
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8943
11.5k
    },
8944
11.5k
    { // GPRPair_with_gsub_1_in_GPRsp
8945
11.5k
      0,  // dsub_0
8946
11.5k
      0,  // dsub_1
8947
11.5k
      0,  // dsub_2
8948
11.5k
      0,  // dsub_3
8949
11.5k
      0,  // dsub_4
8950
11.5k
      0,  // dsub_5
8951
11.5k
      0,  // dsub_6
8952
11.5k
      0,  // dsub_7
8953
11.5k
      28, // gsub_0 -> GPRPair_with_gsub_1_in_GPRsp
8954
11.5k
      28, // gsub_1 -> GPRPair_with_gsub_1_in_GPRsp
8955
11.5k
      0,  // qqsub_0
8956
11.5k
      0,  // qqsub_1
8957
11.5k
      0,  // qsub_0
8958
11.5k
      0,  // qsub_1
8959
11.5k
      0,  // qsub_2
8960
11.5k
      0,  // qsub_3
8961
11.5k
      0,  // ssub_0
8962
11.5k
      0,  // ssub_1
8963
11.5k
      0,  // ssub_2
8964
11.5k
      0,  // ssub_3
8965
11.5k
      0,  // ssub_4
8966
11.5k
      0,  // ssub_5
8967
11.5k
      0,  // ssub_6
8968
11.5k
      0,  // ssub_7
8969
11.5k
      0,  // ssub_8
8970
11.5k
      0,  // ssub_9
8971
11.5k
      0,  // ssub_10
8972
11.5k
      0,  // ssub_11
8973
11.5k
      0,  // ssub_12
8974
11.5k
      0,  // ssub_13
8975
11.5k
      0,  // dsub_7_then_ssub_0
8976
11.5k
      0,  // dsub_7_then_ssub_1
8977
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
8978
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8979
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
8980
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8981
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
8982
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8983
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8984
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8985
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8986
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8987
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
8988
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8989
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8990
11.5k
      0,  // ssub_6_ssub_7_dsub_5
8991
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8992
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
8993
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
8994
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8995
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
8996
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8997
11.5k
      0,  // dsub_5_dsub_7
8998
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
8999
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9000
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9001
11.5k
    },
9002
11.5k
    { // DPairSpc
9003
11.5k
      29, // dsub_0 -> DPairSpc
9004
11.5k
      0,  // dsub_1
9005
11.5k
      29, // dsub_2 -> DPairSpc
9006
11.5k
      0,  // dsub_3
9007
11.5k
      0,  // dsub_4
9008
11.5k
      0,  // dsub_5
9009
11.5k
      0,  // dsub_6
9010
11.5k
      0,  // dsub_7
9011
11.5k
      0,  // gsub_0
9012
11.5k
      0,  // gsub_1
9013
11.5k
      0,  // qqsub_0
9014
11.5k
      0,  // qqsub_1
9015
11.5k
      0,  // qsub_0
9016
11.5k
      0,  // qsub_1
9017
11.5k
      0,  // qsub_2
9018
11.5k
      0,  // qsub_3
9019
11.5k
      30, // ssub_0 -> DPairSpc_with_ssub_0
9020
11.5k
      30, // ssub_1 -> DPairSpc_with_ssub_0
9021
11.5k
      0,  // ssub_2
9022
11.5k
      0,  // ssub_3
9023
11.5k
      31, // ssub_4 -> DPairSpc_with_ssub_4
9024
11.5k
      31, // ssub_5 -> DPairSpc_with_ssub_4
9025
11.5k
      0,  // ssub_6
9026
11.5k
      0,  // ssub_7
9027
11.5k
      0,  // ssub_8
9028
11.5k
      0,  // ssub_9
9029
11.5k
      0,  // ssub_10
9030
11.5k
      0,  // ssub_11
9031
11.5k
      0,  // ssub_12
9032
11.5k
      0,  // ssub_13
9033
11.5k
      0,  // dsub_7_then_ssub_0
9034
11.5k
      0,  // dsub_7_then_ssub_1
9035
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9036
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9037
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9038
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9039
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9040
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9041
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9042
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9043
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9044
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9045
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9046
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9047
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9048
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9049
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9050
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9051
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9052
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9053
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9054
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9055
11.5k
      0,  // dsub_5_dsub_7
9056
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9057
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9058
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9059
11.5k
    },
9060
11.5k
    { // DPairSpc_with_ssub_0
9061
11.5k
      30, // dsub_0 -> DPairSpc_with_ssub_0
9062
11.5k
      0,  // dsub_1
9063
11.5k
      30, // dsub_2 -> DPairSpc_with_ssub_0
9064
11.5k
      0,  // dsub_3
9065
11.5k
      0,  // dsub_4
9066
11.5k
      0,  // dsub_5
9067
11.5k
      0,  // dsub_6
9068
11.5k
      0,  // dsub_7
9069
11.5k
      0,  // gsub_0
9070
11.5k
      0,  // gsub_1
9071
11.5k
      0,  // qqsub_0
9072
11.5k
      0,  // qqsub_1
9073
11.5k
      0,  // qsub_0
9074
11.5k
      0,  // qsub_1
9075
11.5k
      0,  // qsub_2
9076
11.5k
      0,  // qsub_3
9077
11.5k
      30, // ssub_0 -> DPairSpc_with_ssub_0
9078
11.5k
      30, // ssub_1 -> DPairSpc_with_ssub_0
9079
11.5k
      0,  // ssub_2
9080
11.5k
      0,  // ssub_3
9081
11.5k
      31, // ssub_4 -> DPairSpc_with_ssub_4
9082
11.5k
      31, // ssub_5 -> DPairSpc_with_ssub_4
9083
11.5k
      0,  // ssub_6
9084
11.5k
      0,  // ssub_7
9085
11.5k
      0,  // ssub_8
9086
11.5k
      0,  // ssub_9
9087
11.5k
      0,  // ssub_10
9088
11.5k
      0,  // ssub_11
9089
11.5k
      0,  // ssub_12
9090
11.5k
      0,  // ssub_13
9091
11.5k
      0,  // dsub_7_then_ssub_0
9092
11.5k
      0,  // dsub_7_then_ssub_1
9093
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9094
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9095
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9096
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9097
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9098
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9099
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9100
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9101
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9102
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9103
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9104
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9105
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9106
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9107
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9108
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9109
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9110
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9111
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9112
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9113
11.5k
      0,  // dsub_5_dsub_7
9114
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9115
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9116
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9117
11.5k
    },
9118
11.5k
    { // DPairSpc_with_ssub_4
9119
11.5k
      31, // dsub_0 -> DPairSpc_with_ssub_4
9120
11.5k
      0,  // dsub_1
9121
11.5k
      31, // dsub_2 -> DPairSpc_with_ssub_4
9122
11.5k
      0,  // dsub_3
9123
11.5k
      0,  // dsub_4
9124
11.5k
      0,  // dsub_5
9125
11.5k
      0,  // dsub_6
9126
11.5k
      0,  // dsub_7
9127
11.5k
      0,  // gsub_0
9128
11.5k
      0,  // gsub_1
9129
11.5k
      0,  // qqsub_0
9130
11.5k
      0,  // qqsub_1
9131
11.5k
      0,  // qsub_0
9132
11.5k
      0,  // qsub_1
9133
11.5k
      0,  // qsub_2
9134
11.5k
      0,  // qsub_3
9135
11.5k
      31, // ssub_0 -> DPairSpc_with_ssub_4
9136
11.5k
      31, // ssub_1 -> DPairSpc_with_ssub_4
9137
11.5k
      0,  // ssub_2
9138
11.5k
      0,  // ssub_3
9139
11.5k
      31, // ssub_4 -> DPairSpc_with_ssub_4
9140
11.5k
      31, // ssub_5 -> DPairSpc_with_ssub_4
9141
11.5k
      0,  // ssub_6
9142
11.5k
      0,  // ssub_7
9143
11.5k
      0,  // ssub_8
9144
11.5k
      0,  // ssub_9
9145
11.5k
      0,  // ssub_10
9146
11.5k
      0,  // ssub_11
9147
11.5k
      0,  // ssub_12
9148
11.5k
      0,  // ssub_13
9149
11.5k
      0,  // dsub_7_then_ssub_0
9150
11.5k
      0,  // dsub_7_then_ssub_1
9151
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9152
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9153
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9154
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9155
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9156
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9157
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9158
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9159
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9160
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9161
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9162
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9163
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9164
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9165
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9166
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9167
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9168
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9169
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9170
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9171
11.5k
      0,  // dsub_5_dsub_7
9172
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9173
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9174
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9175
11.5k
    },
9176
11.5k
    { // DPairSpc_with_dsub_0_in_DPR_8
9177
11.5k
      32, // dsub_0 -> DPairSpc_with_dsub_0_in_DPR_8
9178
11.5k
      0,  // dsub_1
9179
11.5k
      32, // dsub_2 -> DPairSpc_with_dsub_0_in_DPR_8
9180
11.5k
      0,  // dsub_3
9181
11.5k
      0,  // dsub_4
9182
11.5k
      0,  // dsub_5
9183
11.5k
      0,  // dsub_6
9184
11.5k
      0,  // dsub_7
9185
11.5k
      0,  // gsub_0
9186
11.5k
      0,  // gsub_1
9187
11.5k
      0,  // qqsub_0
9188
11.5k
      0,  // qqsub_1
9189
11.5k
      0,  // qsub_0
9190
11.5k
      0,  // qsub_1
9191
11.5k
      0,  // qsub_2
9192
11.5k
      0,  // qsub_3
9193
11.5k
      32, // ssub_0 -> DPairSpc_with_dsub_0_in_DPR_8
9194
11.5k
      32, // ssub_1 -> DPairSpc_with_dsub_0_in_DPR_8
9195
11.5k
      0,  // ssub_2
9196
11.5k
      0,  // ssub_3
9197
11.5k
      32, // ssub_4 -> DPairSpc_with_dsub_0_in_DPR_8
9198
11.5k
      32, // ssub_5 -> DPairSpc_with_dsub_0_in_DPR_8
9199
11.5k
      0,  // ssub_6
9200
11.5k
      0,  // ssub_7
9201
11.5k
      0,  // ssub_8
9202
11.5k
      0,  // ssub_9
9203
11.5k
      0,  // ssub_10
9204
11.5k
      0,  // ssub_11
9205
11.5k
      0,  // ssub_12
9206
11.5k
      0,  // ssub_13
9207
11.5k
      0,  // dsub_7_then_ssub_0
9208
11.5k
      0,  // dsub_7_then_ssub_1
9209
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9210
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9211
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9212
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9213
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9214
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9215
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9216
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9217
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9218
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9219
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9220
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9221
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9222
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9223
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9224
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9225
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9226
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9227
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9228
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9229
11.5k
      0,  // dsub_5_dsub_7
9230
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9231
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9232
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9233
11.5k
    },
9234
11.5k
    { // DPairSpc_with_dsub_2_in_DPR_8
9235
11.5k
      33, // dsub_0 -> DPairSpc_with_dsub_2_in_DPR_8
9236
11.5k
      0,  // dsub_1
9237
11.5k
      33, // dsub_2 -> DPairSpc_with_dsub_2_in_DPR_8
9238
11.5k
      0,  // dsub_3
9239
11.5k
      0,  // dsub_4
9240
11.5k
      0,  // dsub_5
9241
11.5k
      0,  // dsub_6
9242
11.5k
      0,  // dsub_7
9243
11.5k
      0,  // gsub_0
9244
11.5k
      0,  // gsub_1
9245
11.5k
      0,  // qqsub_0
9246
11.5k
      0,  // qqsub_1
9247
11.5k
      0,  // qsub_0
9248
11.5k
      0,  // qsub_1
9249
11.5k
      0,  // qsub_2
9250
11.5k
      0,  // qsub_3
9251
11.5k
      33, // ssub_0 -> DPairSpc_with_dsub_2_in_DPR_8
9252
11.5k
      33, // ssub_1 -> DPairSpc_with_dsub_2_in_DPR_8
9253
11.5k
      0,  // ssub_2
9254
11.5k
      0,  // ssub_3
9255
11.5k
      33, // ssub_4 -> DPairSpc_with_dsub_2_in_DPR_8
9256
11.5k
      33, // ssub_5 -> DPairSpc_with_dsub_2_in_DPR_8
9257
11.5k
      0,  // ssub_6
9258
11.5k
      0,  // ssub_7
9259
11.5k
      0,  // ssub_8
9260
11.5k
      0,  // ssub_9
9261
11.5k
      0,  // ssub_10
9262
11.5k
      0,  // ssub_11
9263
11.5k
      0,  // ssub_12
9264
11.5k
      0,  // ssub_13
9265
11.5k
      0,  // dsub_7_then_ssub_0
9266
11.5k
      0,  // dsub_7_then_ssub_1
9267
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9268
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9269
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9270
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9271
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9272
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9273
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9274
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9275
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9276
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9277
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9278
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9279
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9280
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9281
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9282
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9283
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9284
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9285
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9286
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9287
11.5k
      0,  // dsub_5_dsub_7
9288
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9289
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9290
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9291
11.5k
    },
9292
11.5k
    { // DPair
9293
11.5k
      34, // dsub_0 -> DPair
9294
11.5k
      34, // dsub_1 -> DPair
9295
11.5k
      0,  // dsub_2
9296
11.5k
      0,  // dsub_3
9297
11.5k
      0,  // dsub_4
9298
11.5k
      0,  // dsub_5
9299
11.5k
      0,  // dsub_6
9300
11.5k
      0,  // dsub_7
9301
11.5k
      0,  // gsub_0
9302
11.5k
      0,  // gsub_1
9303
11.5k
      0,  // qqsub_0
9304
11.5k
      0,  // qqsub_1
9305
11.5k
      0,  // qsub_0
9306
11.5k
      0,  // qsub_1
9307
11.5k
      0,  // qsub_2
9308
11.5k
      0,  // qsub_3
9309
11.5k
      35, // ssub_0 -> DPair_with_ssub_0
9310
11.5k
      35, // ssub_1 -> DPair_with_ssub_0
9311
11.5k
      37, // ssub_2 -> DPair_with_ssub_2
9312
11.5k
      37, // ssub_3 -> DPair_with_ssub_2
9313
11.5k
      0,  // ssub_4
9314
11.5k
      0,  // ssub_5
9315
11.5k
      0,  // ssub_6
9316
11.5k
      0,  // ssub_7
9317
11.5k
      0,  // ssub_8
9318
11.5k
      0,  // ssub_9
9319
11.5k
      0,  // ssub_10
9320
11.5k
      0,  // ssub_11
9321
11.5k
      0,  // ssub_12
9322
11.5k
      0,  // ssub_13
9323
11.5k
      0,  // dsub_7_then_ssub_0
9324
11.5k
      0,  // dsub_7_then_ssub_1
9325
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9326
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9327
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9328
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9329
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9330
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9331
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9332
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9333
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9334
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9335
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9336
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9337
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9338
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9339
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9340
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9341
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9342
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9343
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9344
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9345
11.5k
      0,  // dsub_5_dsub_7
9346
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9347
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9348
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9349
11.5k
    },
9350
11.5k
    { // DPair_with_ssub_0
9351
11.5k
      35, // dsub_0 -> DPair_with_ssub_0
9352
11.5k
      35, // dsub_1 -> DPair_with_ssub_0
9353
11.5k
      0,  // dsub_2
9354
11.5k
      0,  // dsub_3
9355
11.5k
      0,  // dsub_4
9356
11.5k
      0,  // dsub_5
9357
11.5k
      0,  // dsub_6
9358
11.5k
      0,  // dsub_7
9359
11.5k
      0,  // gsub_0
9360
11.5k
      0,  // gsub_1
9361
11.5k
      0,  // qqsub_0
9362
11.5k
      0,  // qqsub_1
9363
11.5k
      0,  // qsub_0
9364
11.5k
      0,  // qsub_1
9365
11.5k
      0,  // qsub_2
9366
11.5k
      0,  // qsub_3
9367
11.5k
      35, // ssub_0 -> DPair_with_ssub_0
9368
11.5k
      35, // ssub_1 -> DPair_with_ssub_0
9369
11.5k
      37, // ssub_2 -> DPair_with_ssub_2
9370
11.5k
      37, // ssub_3 -> DPair_with_ssub_2
9371
11.5k
      0,  // ssub_4
9372
11.5k
      0,  // ssub_5
9373
11.5k
      0,  // ssub_6
9374
11.5k
      0,  // ssub_7
9375
11.5k
      0,  // ssub_8
9376
11.5k
      0,  // ssub_9
9377
11.5k
      0,  // ssub_10
9378
11.5k
      0,  // ssub_11
9379
11.5k
      0,  // ssub_12
9380
11.5k
      0,  // ssub_13
9381
11.5k
      0,  // dsub_7_then_ssub_0
9382
11.5k
      0,  // dsub_7_then_ssub_1
9383
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9384
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9385
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9386
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9387
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9388
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9389
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9390
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9391
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9392
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9393
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9394
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9395
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9396
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9397
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9398
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9399
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9400
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9401
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9402
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9403
11.5k
      0,  // dsub_5_dsub_7
9404
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9405
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9406
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9407
11.5k
    },
9408
11.5k
    { // QPR
9409
11.5k
      36, // dsub_0 -> QPR
9410
11.5k
      36, // dsub_1 -> QPR
9411
11.5k
      0,  // dsub_2
9412
11.5k
      0,  // dsub_3
9413
11.5k
      0,  // dsub_4
9414
11.5k
      0,  // dsub_5
9415
11.5k
      0,  // dsub_6
9416
11.5k
      0,  // dsub_7
9417
11.5k
      0,  // gsub_0
9418
11.5k
      0,  // gsub_1
9419
11.5k
      0,  // qqsub_0
9420
11.5k
      0,  // qqsub_1
9421
11.5k
      0,  // qsub_0
9422
11.5k
      0,  // qsub_1
9423
11.5k
      0,  // qsub_2
9424
11.5k
      0,  // qsub_3
9425
11.5k
      39, // ssub_0 -> QPR_VFP2
9426
11.5k
      39, // ssub_1 -> QPR_VFP2
9427
11.5k
      39, // ssub_2 -> QPR_VFP2
9428
11.5k
      39, // ssub_3 -> QPR_VFP2
9429
11.5k
      0,  // ssub_4
9430
11.5k
      0,  // ssub_5
9431
11.5k
      0,  // ssub_6
9432
11.5k
      0,  // ssub_7
9433
11.5k
      0,  // ssub_8
9434
11.5k
      0,  // ssub_9
9435
11.5k
      0,  // ssub_10
9436
11.5k
      0,  // ssub_11
9437
11.5k
      0,  // ssub_12
9438
11.5k
      0,  // ssub_13
9439
11.5k
      0,  // dsub_7_then_ssub_0
9440
11.5k
      0,  // dsub_7_then_ssub_1
9441
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9442
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9443
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9444
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9445
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9446
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9447
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9448
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9449
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9450
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9451
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9452
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9453
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9454
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9455
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9456
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9457
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9458
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9459
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9460
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9461
11.5k
      0,  // dsub_5_dsub_7
9462
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9463
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9464
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9465
11.5k
    },
9466
11.5k
    { // DPair_with_ssub_2
9467
11.5k
      37, // dsub_0 -> DPair_with_ssub_2
9468
11.5k
      37, // dsub_1 -> DPair_with_ssub_2
9469
11.5k
      0,  // dsub_2
9470
11.5k
      0,  // dsub_3
9471
11.5k
      0,  // dsub_4
9472
11.5k
      0,  // dsub_5
9473
11.5k
      0,  // dsub_6
9474
11.5k
      0,  // dsub_7
9475
11.5k
      0,  // gsub_0
9476
11.5k
      0,  // gsub_1
9477
11.5k
      0,  // qqsub_0
9478
11.5k
      0,  // qqsub_1
9479
11.5k
      0,  // qsub_0
9480
11.5k
      0,  // qsub_1
9481
11.5k
      0,  // qsub_2
9482
11.5k
      0,  // qsub_3
9483
11.5k
      37, // ssub_0 -> DPair_with_ssub_2
9484
11.5k
      37, // ssub_1 -> DPair_with_ssub_2
9485
11.5k
      37, // ssub_2 -> DPair_with_ssub_2
9486
11.5k
      37, // ssub_3 -> DPair_with_ssub_2
9487
11.5k
      0,  // ssub_4
9488
11.5k
      0,  // ssub_5
9489
11.5k
      0,  // ssub_6
9490
11.5k
      0,  // ssub_7
9491
11.5k
      0,  // ssub_8
9492
11.5k
      0,  // ssub_9
9493
11.5k
      0,  // ssub_10
9494
11.5k
      0,  // ssub_11
9495
11.5k
      0,  // ssub_12
9496
11.5k
      0,  // ssub_13
9497
11.5k
      0,  // dsub_7_then_ssub_0
9498
11.5k
      0,  // dsub_7_then_ssub_1
9499
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9500
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9501
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9502
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9503
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9504
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9505
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9506
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9507
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9508
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9509
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9510
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9511
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9512
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9513
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9514
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9515
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9516
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9517
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9518
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9519
11.5k
      0,  // dsub_5_dsub_7
9520
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9521
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9522
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9523
11.5k
    },
9524
11.5k
    { // DPair_with_dsub_0_in_DPR_8
9525
11.5k
      38, // dsub_0 -> DPair_with_dsub_0_in_DPR_8
9526
11.5k
      38, // dsub_1 -> DPair_with_dsub_0_in_DPR_8
9527
11.5k
      0,  // dsub_2
9528
11.5k
      0,  // dsub_3
9529
11.5k
      0,  // dsub_4
9530
11.5k
      0,  // dsub_5
9531
11.5k
      0,  // dsub_6
9532
11.5k
      0,  // dsub_7
9533
11.5k
      0,  // gsub_0
9534
11.5k
      0,  // gsub_1
9535
11.5k
      0,  // qqsub_0
9536
11.5k
      0,  // qqsub_1
9537
11.5k
      0,  // qsub_0
9538
11.5k
      0,  // qsub_1
9539
11.5k
      0,  // qsub_2
9540
11.5k
      0,  // qsub_3
9541
11.5k
      38, // ssub_0 -> DPair_with_dsub_0_in_DPR_8
9542
11.5k
      38, // ssub_1 -> DPair_with_dsub_0_in_DPR_8
9543
11.5k
      38, // ssub_2 -> DPair_with_dsub_0_in_DPR_8
9544
11.5k
      38, // ssub_3 -> DPair_with_dsub_0_in_DPR_8
9545
11.5k
      0,  // ssub_4
9546
11.5k
      0,  // ssub_5
9547
11.5k
      0,  // ssub_6
9548
11.5k
      0,  // ssub_7
9549
11.5k
      0,  // ssub_8
9550
11.5k
      0,  // ssub_9
9551
11.5k
      0,  // ssub_10
9552
11.5k
      0,  // ssub_11
9553
11.5k
      0,  // ssub_12
9554
11.5k
      0,  // ssub_13
9555
11.5k
      0,  // dsub_7_then_ssub_0
9556
11.5k
      0,  // dsub_7_then_ssub_1
9557
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9558
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9559
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9560
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9561
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9562
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9563
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9564
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9565
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9566
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9567
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9568
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9569
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9570
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9571
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9572
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9573
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9574
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9575
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9576
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9577
11.5k
      0,  // dsub_5_dsub_7
9578
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9579
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9580
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9581
11.5k
    },
9582
11.5k
    { // QPR_VFP2
9583
11.5k
      39, // dsub_0 -> QPR_VFP2
9584
11.5k
      39, // dsub_1 -> QPR_VFP2
9585
11.5k
      0,  // dsub_2
9586
11.5k
      0,  // dsub_3
9587
11.5k
      0,  // dsub_4
9588
11.5k
      0,  // dsub_5
9589
11.5k
      0,  // dsub_6
9590
11.5k
      0,  // dsub_7
9591
11.5k
      0,  // gsub_0
9592
11.5k
      0,  // gsub_1
9593
11.5k
      0,  // qqsub_0
9594
11.5k
      0,  // qqsub_1
9595
11.5k
      0,  // qsub_0
9596
11.5k
      0,  // qsub_1
9597
11.5k
      0,  // qsub_2
9598
11.5k
      0,  // qsub_3
9599
11.5k
      39, // ssub_0 -> QPR_VFP2
9600
11.5k
      39, // ssub_1 -> QPR_VFP2
9601
11.5k
      39, // ssub_2 -> QPR_VFP2
9602
11.5k
      39, // ssub_3 -> QPR_VFP2
9603
11.5k
      0,  // ssub_4
9604
11.5k
      0,  // ssub_5
9605
11.5k
      0,  // ssub_6
9606
11.5k
      0,  // ssub_7
9607
11.5k
      0,  // ssub_8
9608
11.5k
      0,  // ssub_9
9609
11.5k
      0,  // ssub_10
9610
11.5k
      0,  // ssub_11
9611
11.5k
      0,  // ssub_12
9612
11.5k
      0,  // ssub_13
9613
11.5k
      0,  // dsub_7_then_ssub_0
9614
11.5k
      0,  // dsub_7_then_ssub_1
9615
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9616
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9617
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9618
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9619
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9620
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9621
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9622
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9623
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9624
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9625
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9626
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9627
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9628
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9629
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9630
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9631
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9632
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9633
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9634
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9635
11.5k
      0,  // dsub_5_dsub_7
9636
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9637
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9638
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9639
11.5k
    },
9640
11.5k
    { // DPair_with_dsub_1_in_DPR_8
9641
11.5k
      40, // dsub_0 -> DPair_with_dsub_1_in_DPR_8
9642
11.5k
      40, // dsub_1 -> DPair_with_dsub_1_in_DPR_8
9643
11.5k
      0,  // dsub_2
9644
11.5k
      0,  // dsub_3
9645
11.5k
      0,  // dsub_4
9646
11.5k
      0,  // dsub_5
9647
11.5k
      0,  // dsub_6
9648
11.5k
      0,  // dsub_7
9649
11.5k
      0,  // gsub_0
9650
11.5k
      0,  // gsub_1
9651
11.5k
      0,  // qqsub_0
9652
11.5k
      0,  // qqsub_1
9653
11.5k
      0,  // qsub_0
9654
11.5k
      0,  // qsub_1
9655
11.5k
      0,  // qsub_2
9656
11.5k
      0,  // qsub_3
9657
11.5k
      40, // ssub_0 -> DPair_with_dsub_1_in_DPR_8
9658
11.5k
      40, // ssub_1 -> DPair_with_dsub_1_in_DPR_8
9659
11.5k
      40, // ssub_2 -> DPair_with_dsub_1_in_DPR_8
9660
11.5k
      40, // ssub_3 -> DPair_with_dsub_1_in_DPR_8
9661
11.5k
      0,  // ssub_4
9662
11.5k
      0,  // ssub_5
9663
11.5k
      0,  // ssub_6
9664
11.5k
      0,  // ssub_7
9665
11.5k
      0,  // ssub_8
9666
11.5k
      0,  // ssub_9
9667
11.5k
      0,  // ssub_10
9668
11.5k
      0,  // ssub_11
9669
11.5k
      0,  // ssub_12
9670
11.5k
      0,  // ssub_13
9671
11.5k
      0,  // dsub_7_then_ssub_0
9672
11.5k
      0,  // dsub_7_then_ssub_1
9673
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9674
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9675
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9676
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9677
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9678
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9679
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9680
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9681
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9682
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9683
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9684
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9685
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9686
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9687
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9688
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9689
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9690
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9691
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9692
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9693
11.5k
      0,  // dsub_5_dsub_7
9694
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9695
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9696
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9697
11.5k
    },
9698
11.5k
    { // QPR_8
9699
11.5k
      41, // dsub_0 -> QPR_8
9700
11.5k
      41, // dsub_1 -> QPR_8
9701
11.5k
      0,  // dsub_2
9702
11.5k
      0,  // dsub_3
9703
11.5k
      0,  // dsub_4
9704
11.5k
      0,  // dsub_5
9705
11.5k
      0,  // dsub_6
9706
11.5k
      0,  // dsub_7
9707
11.5k
      0,  // gsub_0
9708
11.5k
      0,  // gsub_1
9709
11.5k
      0,  // qqsub_0
9710
11.5k
      0,  // qqsub_1
9711
11.5k
      0,  // qsub_0
9712
11.5k
      0,  // qsub_1
9713
11.5k
      0,  // qsub_2
9714
11.5k
      0,  // qsub_3
9715
11.5k
      41, // ssub_0 -> QPR_8
9716
11.5k
      41, // ssub_1 -> QPR_8
9717
11.5k
      41, // ssub_2 -> QPR_8
9718
11.5k
      41, // ssub_3 -> QPR_8
9719
11.5k
      0,  // ssub_4
9720
11.5k
      0,  // ssub_5
9721
11.5k
      0,  // ssub_6
9722
11.5k
      0,  // ssub_7
9723
11.5k
      0,  // ssub_8
9724
11.5k
      0,  // ssub_9
9725
11.5k
      0,  // ssub_10
9726
11.5k
      0,  // ssub_11
9727
11.5k
      0,  // ssub_12
9728
11.5k
      0,  // ssub_13
9729
11.5k
      0,  // dsub_7_then_ssub_0
9730
11.5k
      0,  // dsub_7_then_ssub_1
9731
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5
9732
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9733
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9734
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9735
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9736
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9737
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9738
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9739
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9740
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9741
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9742
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9743
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9744
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9745
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9746
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9747
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9748
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9749
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9750
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9751
11.5k
      0,  // dsub_5_dsub_7
9752
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9753
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9754
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9755
11.5k
    },
9756
11.5k
    { // DTriple
9757
11.5k
      42, // dsub_0 -> DTriple
9758
11.5k
      42, // dsub_1 -> DTriple
9759
11.5k
      42, // dsub_2 -> DTriple
9760
11.5k
      0,  // dsub_3
9761
11.5k
      0,  // dsub_4
9762
11.5k
      0,  // dsub_5
9763
11.5k
      0,  // dsub_6
9764
11.5k
      0,  // dsub_7
9765
11.5k
      0,  // gsub_0
9766
11.5k
      0,  // gsub_1
9767
11.5k
      0,  // qqsub_0
9768
11.5k
      0,  // qqsub_1
9769
11.5k
      42, // qsub_0 -> DTriple
9770
11.5k
      0,  // qsub_1
9771
11.5k
      0,  // qsub_2
9772
11.5k
      0,  // qsub_3
9773
11.5k
      45, // ssub_0 -> DTriple_with_ssub_0
9774
11.5k
      45, // ssub_1 -> DTriple_with_ssub_0
9775
11.5k
      47, // ssub_2 -> DTriple_with_ssub_2
9776
11.5k
      47, // ssub_3 -> DTriple_with_ssub_2
9777
11.5k
      50, // ssub_4 -> DTriple_with_ssub_4
9778
11.5k
      50, // ssub_5 -> DTriple_with_ssub_4
9779
11.5k
      0,  // ssub_6
9780
11.5k
      0,  // ssub_7
9781
11.5k
      0,  // ssub_8
9782
11.5k
      0,  // ssub_9
9783
11.5k
      0,  // ssub_10
9784
11.5k
      0,  // ssub_11
9785
11.5k
      0,  // ssub_12
9786
11.5k
      0,  // ssub_13
9787
11.5k
      0,  // dsub_7_then_ssub_0
9788
11.5k
      0,  // dsub_7_then_ssub_1
9789
11.5k
      42, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple
9790
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9791
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9792
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9793
11.5k
      42, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple
9794
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9795
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9796
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9797
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9798
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9799
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9800
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9801
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9802
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9803
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9804
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9805
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9806
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9807
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9808
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9809
11.5k
      0,  // dsub_5_dsub_7
9810
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9811
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9812
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9813
11.5k
    },
9814
11.5k
    { // DTripleSpc
9815
11.5k
      43, // dsub_0 -> DTripleSpc
9816
11.5k
      0,  // dsub_1
9817
11.5k
      43, // dsub_2 -> DTripleSpc
9818
11.5k
      0,  // dsub_3
9819
11.5k
      43, // dsub_4 -> DTripleSpc
9820
11.5k
      0,  // dsub_5
9821
11.5k
      0,  // dsub_6
9822
11.5k
      0,  // dsub_7
9823
11.5k
      0,  // gsub_0
9824
11.5k
      0,  // gsub_1
9825
11.5k
      0,  // qqsub_0
9826
11.5k
      0,  // qqsub_1
9827
11.5k
      0,  // qsub_0
9828
11.5k
      0,  // qsub_1
9829
11.5k
      0,  // qsub_2
9830
11.5k
      0,  // qsub_3
9831
11.5k
      44, // ssub_0 -> DTripleSpc_with_ssub_0
9832
11.5k
      44, // ssub_1 -> DTripleSpc_with_ssub_0
9833
11.5k
      0,  // ssub_2
9834
11.5k
      0,  // ssub_3
9835
11.5k
      49, // ssub_4 -> DTripleSpc_with_ssub_4
9836
11.5k
      49, // ssub_5 -> DTripleSpc_with_ssub_4
9837
11.5k
      0,  // ssub_6
9838
11.5k
      0,  // ssub_7
9839
11.5k
      51, // ssub_8 -> DTripleSpc_with_ssub_8
9840
11.5k
      51, // ssub_9 -> DTripleSpc_with_ssub_8
9841
11.5k
      0,  // ssub_10
9842
11.5k
      0,  // ssub_11
9843
11.5k
      0,  // ssub_12
9844
11.5k
      0,  // ssub_13
9845
11.5k
      0,  // dsub_7_then_ssub_0
9846
11.5k
      0,  // dsub_7_then_ssub_1
9847
11.5k
      43, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc
9848
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9849
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9850
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9851
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9852
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9853
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9854
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9855
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9856
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9857
11.5k
      43, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc
9858
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9859
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9860
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9861
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9862
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9863
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9864
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9865
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9866
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9867
11.5k
      0,  // dsub_5_dsub_7
9868
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9869
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9870
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9871
11.5k
    },
9872
11.5k
    { // DTripleSpc_with_ssub_0
9873
11.5k
      44, // dsub_0 -> DTripleSpc_with_ssub_0
9874
11.5k
      0,  // dsub_1
9875
11.5k
      44, // dsub_2 -> DTripleSpc_with_ssub_0
9876
11.5k
      0,  // dsub_3
9877
11.5k
      44, // dsub_4 -> DTripleSpc_with_ssub_0
9878
11.5k
      0,  // dsub_5
9879
11.5k
      0,  // dsub_6
9880
11.5k
      0,  // dsub_7
9881
11.5k
      0,  // gsub_0
9882
11.5k
      0,  // gsub_1
9883
11.5k
      0,  // qqsub_0
9884
11.5k
      0,  // qqsub_1
9885
11.5k
      0,  // qsub_0
9886
11.5k
      0,  // qsub_1
9887
11.5k
      0,  // qsub_2
9888
11.5k
      0,  // qsub_3
9889
11.5k
      44, // ssub_0 -> DTripleSpc_with_ssub_0
9890
11.5k
      44, // ssub_1 -> DTripleSpc_with_ssub_0
9891
11.5k
      0,  // ssub_2
9892
11.5k
      0,  // ssub_3
9893
11.5k
      49, // ssub_4 -> DTripleSpc_with_ssub_4
9894
11.5k
      49, // ssub_5 -> DTripleSpc_with_ssub_4
9895
11.5k
      0,  // ssub_6
9896
11.5k
      0,  // ssub_7
9897
11.5k
      51, // ssub_8 -> DTripleSpc_with_ssub_8
9898
11.5k
      51, // ssub_9 -> DTripleSpc_with_ssub_8
9899
11.5k
      0,  // ssub_10
9900
11.5k
      0,  // ssub_11
9901
11.5k
      0,  // ssub_12
9902
11.5k
      0,  // ssub_13
9903
11.5k
      0,  // dsub_7_then_ssub_0
9904
11.5k
      0,  // dsub_7_then_ssub_1
9905
11.5k
      44, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_0
9906
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9907
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9908
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9909
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
9910
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9911
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9912
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9913
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9914
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9915
11.5k
      44, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_0
9916
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9917
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9918
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9919
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9920
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9921
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9922
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9923
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9924
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9925
11.5k
      0,  // dsub_5_dsub_7
9926
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9927
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9928
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9929
11.5k
    },
9930
11.5k
    { // DTriple_with_ssub_0
9931
11.5k
      45, // dsub_0 -> DTriple_with_ssub_0
9932
11.5k
      45, // dsub_1 -> DTriple_with_ssub_0
9933
11.5k
      45, // dsub_2 -> DTriple_with_ssub_0
9934
11.5k
      0,  // dsub_3
9935
11.5k
      0,  // dsub_4
9936
11.5k
      0,  // dsub_5
9937
11.5k
      0,  // dsub_6
9938
11.5k
      0,  // dsub_7
9939
11.5k
      0,  // gsub_0
9940
11.5k
      0,  // gsub_1
9941
11.5k
      0,  // qqsub_0
9942
11.5k
      0,  // qqsub_1
9943
11.5k
      45, // qsub_0 -> DTriple_with_ssub_0
9944
11.5k
      0,  // qsub_1
9945
11.5k
      0,  // qsub_2
9946
11.5k
      0,  // qsub_3
9947
11.5k
      45, // ssub_0 -> DTriple_with_ssub_0
9948
11.5k
      45, // ssub_1 -> DTriple_with_ssub_0
9949
11.5k
      47, // ssub_2 -> DTriple_with_ssub_2
9950
11.5k
      47, // ssub_3 -> DTriple_with_ssub_2
9951
11.5k
      50, // ssub_4 -> DTriple_with_ssub_4
9952
11.5k
      50, // ssub_5 -> DTriple_with_ssub_4
9953
11.5k
      0,  // ssub_6
9954
11.5k
      0,  // ssub_7
9955
11.5k
      0,  // ssub_8
9956
11.5k
      0,  // ssub_9
9957
11.5k
      0,  // ssub_10
9958
11.5k
      0,  // ssub_11
9959
11.5k
      0,  // ssub_12
9960
11.5k
      0,  // ssub_13
9961
11.5k
      0,  // dsub_7_then_ssub_0
9962
11.5k
      0,  // dsub_7_then_ssub_1
9963
11.5k
      45, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0
9964
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9965
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
9966
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9967
11.5k
      45, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0
9968
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9969
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9970
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9971
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9972
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9973
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
9974
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9975
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9976
11.5k
      0,  // ssub_6_ssub_7_dsub_5
9977
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9978
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
9979
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
9980
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9981
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
9982
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9983
11.5k
      0,  // dsub_5_dsub_7
9984
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
9985
11.5k
      0,  // dsub_5_ssub_12_ssub_13
9986
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9987
11.5k
    },
9988
11.5k
    { // DTriple_with_qsub_0_in_QPR
9989
11.5k
      46, // dsub_0 -> DTriple_with_qsub_0_in_QPR
9990
11.5k
      46, // dsub_1 -> DTriple_with_qsub_0_in_QPR
9991
11.5k
      46, // dsub_2 -> DTriple_with_qsub_0_in_QPR
9992
11.5k
      0,  // dsub_3
9993
11.5k
      0,  // dsub_4
9994
11.5k
      0,  // dsub_5
9995
11.5k
      0,  // dsub_6
9996
11.5k
      0,  // dsub_7
9997
11.5k
      0,  // gsub_0
9998
11.5k
      0,  // gsub_1
9999
11.5k
      0,  // qqsub_0
10000
11.5k
      0,  // qqsub_1
10001
11.5k
      46, // qsub_0 -> DTriple_with_qsub_0_in_QPR
10002
11.5k
      0,  // qsub_1
10003
11.5k
      0,  // qsub_2
10004
11.5k
      0,  // qsub_3
10005
11.5k
      54, // ssub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
10006
11.5k
      54, // ssub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
10007
11.5k
      54, // ssub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
10008
11.5k
      54, // ssub_3 -> DTriple_with_qsub_0_in_QPR_VFP2
10009
11.5k
      58, // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10010
11.5k
      58, // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10011
11.5k
      0,  // ssub_6
10012
11.5k
      0,  // ssub_7
10013
11.5k
      0,  // ssub_8
10014
11.5k
      0,  // ssub_9
10015
11.5k
      0,  // ssub_10
10016
11.5k
      0,  // ssub_11
10017
11.5k
      0,  // ssub_12
10018
11.5k
      0,  // ssub_13
10019
11.5k
      0,  // dsub_7_then_ssub_0
10020
11.5k
      0,  // dsub_7_then_ssub_1
10021
11.5k
      46, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR
10022
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10023
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10024
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10025
11.5k
      46, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR
10026
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10027
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10028
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10029
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10030
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10031
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10032
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10033
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10034
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10035
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10036
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10037
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10038
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10039
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10040
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10041
11.5k
      0,  // dsub_5_dsub_7
10042
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10043
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10044
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10045
11.5k
    },
10046
11.5k
    { // DTriple_with_ssub_2
10047
11.5k
      47, // dsub_0 -> DTriple_with_ssub_2
10048
11.5k
      47, // dsub_1 -> DTriple_with_ssub_2
10049
11.5k
      47, // dsub_2 -> DTriple_with_ssub_2
10050
11.5k
      0,  // dsub_3
10051
11.5k
      0,  // dsub_4
10052
11.5k
      0,  // dsub_5
10053
11.5k
      0,  // dsub_6
10054
11.5k
      0,  // dsub_7
10055
11.5k
      0,  // gsub_0
10056
11.5k
      0,  // gsub_1
10057
11.5k
      0,  // qqsub_0
10058
11.5k
      0,  // qqsub_1
10059
11.5k
      47, // qsub_0 -> DTriple_with_ssub_2
10060
11.5k
      0,  // qsub_1
10061
11.5k
      0,  // qsub_2
10062
11.5k
      0,  // qsub_3
10063
11.5k
      47, // ssub_0 -> DTriple_with_ssub_2
10064
11.5k
      47, // ssub_1 -> DTriple_with_ssub_2
10065
11.5k
      47, // ssub_2 -> DTriple_with_ssub_2
10066
11.5k
      47, // ssub_3 -> DTriple_with_ssub_2
10067
11.5k
      50, // ssub_4 -> DTriple_with_ssub_4
10068
11.5k
      50, // ssub_5 -> DTriple_with_ssub_4
10069
11.5k
      0,  // ssub_6
10070
11.5k
      0,  // ssub_7
10071
11.5k
      0,  // ssub_8
10072
11.5k
      0,  // ssub_9
10073
11.5k
      0,  // ssub_10
10074
11.5k
      0,  // ssub_11
10075
11.5k
      0,  // ssub_12
10076
11.5k
      0,  // ssub_13
10077
11.5k
      0,  // dsub_7_then_ssub_0
10078
11.5k
      0,  // dsub_7_then_ssub_1
10079
11.5k
      47, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2
10080
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10081
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10082
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10083
11.5k
      47, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2
10084
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10085
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10086
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10087
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10088
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10089
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10090
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10091
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10092
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10093
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10094
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10095
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10096
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10097
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10098
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10099
11.5k
      0,  // dsub_5_dsub_7
10100
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10101
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10102
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10103
11.5k
    },
10104
11.5k
    { // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10105
11.5k
      48, // dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10106
11.5k
      48, // dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10107
11.5k
      48, // dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10108
11.5k
      0,  // dsub_3
10109
11.5k
      0,  // dsub_4
10110
11.5k
      0,  // dsub_5
10111
11.5k
      0,  // dsub_6
10112
11.5k
      0,  // dsub_7
10113
11.5k
      0,  // gsub_0
10114
11.5k
      0,  // gsub_1
10115
11.5k
      0,  // qqsub_0
10116
11.5k
      0,  // qqsub_1
10117
11.5k
      48, // qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10118
11.5k
      0,  // qsub_1
10119
11.5k
      0,  // qsub_2
10120
11.5k
      0,  // qsub_3
10121
11.5k
      55, // ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10122
11.5k
      55, // ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10123
11.5k
      57, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10124
11.5k
      57, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10125
11.5k
      57, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10126
11.5k
      57, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10127
11.5k
      0,  // ssub_6
10128
11.5k
      0,  // ssub_7
10129
11.5k
      0,  // ssub_8
10130
11.5k
      0,  // ssub_9
10131
11.5k
      0,  // ssub_10
10132
11.5k
      0,  // ssub_11
10133
11.5k
      0,  // ssub_12
10134
11.5k
      0,  // ssub_13
10135
11.5k
      0,  // dsub_7_then_ssub_0
10136
11.5k
      0,  // dsub_7_then_ssub_1
10137
11.5k
      48, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10138
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10139
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10140
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10141
11.5k
      48, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10142
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10143
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10144
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10145
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10146
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10147
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10148
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10149
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10150
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10151
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10152
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10153
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10154
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10155
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10156
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10157
11.5k
      0,  // dsub_5_dsub_7
10158
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10159
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10160
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10161
11.5k
    },
10162
11.5k
    { // DTripleSpc_with_ssub_4
10163
11.5k
      49, // dsub_0 -> DTripleSpc_with_ssub_4
10164
11.5k
      0,  // dsub_1
10165
11.5k
      49, // dsub_2 -> DTripleSpc_with_ssub_4
10166
11.5k
      0,  // dsub_3
10167
11.5k
      49, // dsub_4 -> DTripleSpc_with_ssub_4
10168
11.5k
      0,  // dsub_5
10169
11.5k
      0,  // dsub_6
10170
11.5k
      0,  // dsub_7
10171
11.5k
      0,  // gsub_0
10172
11.5k
      0,  // gsub_1
10173
11.5k
      0,  // qqsub_0
10174
11.5k
      0,  // qqsub_1
10175
11.5k
      0,  // qsub_0
10176
11.5k
      0,  // qsub_1
10177
11.5k
      0,  // qsub_2
10178
11.5k
      0,  // qsub_3
10179
11.5k
      49, // ssub_0 -> DTripleSpc_with_ssub_4
10180
11.5k
      49, // ssub_1 -> DTripleSpc_with_ssub_4
10181
11.5k
      0,  // ssub_2
10182
11.5k
      0,  // ssub_3
10183
11.5k
      49, // ssub_4 -> DTripleSpc_with_ssub_4
10184
11.5k
      49, // ssub_5 -> DTripleSpc_with_ssub_4
10185
11.5k
      0,  // ssub_6
10186
11.5k
      0,  // ssub_7
10187
11.5k
      51, // ssub_8 -> DTripleSpc_with_ssub_8
10188
11.5k
      51, // ssub_9 -> DTripleSpc_with_ssub_8
10189
11.5k
      0,  // ssub_10
10190
11.5k
      0,  // ssub_11
10191
11.5k
      0,  // ssub_12
10192
11.5k
      0,  // ssub_13
10193
11.5k
      0,  // dsub_7_then_ssub_0
10194
11.5k
      0,  // dsub_7_then_ssub_1
10195
11.5k
      49, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_4
10196
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10197
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10198
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10199
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
10200
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10201
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10202
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10203
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10204
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10205
11.5k
      49, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_4
10206
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10207
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10208
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10209
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10210
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10211
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10212
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10213
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10214
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10215
11.5k
      0,  // dsub_5_dsub_7
10216
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10217
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10218
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10219
11.5k
    },
10220
11.5k
    { // DTriple_with_ssub_4
10221
11.5k
      50, // dsub_0 -> DTriple_with_ssub_4
10222
11.5k
      50, // dsub_1 -> DTriple_with_ssub_4
10223
11.5k
      50, // dsub_2 -> DTriple_with_ssub_4
10224
11.5k
      0,  // dsub_3
10225
11.5k
      0,  // dsub_4
10226
11.5k
      0,  // dsub_5
10227
11.5k
      0,  // dsub_6
10228
11.5k
      0,  // dsub_7
10229
11.5k
      0,  // gsub_0
10230
11.5k
      0,  // gsub_1
10231
11.5k
      0,  // qqsub_0
10232
11.5k
      0,  // qqsub_1
10233
11.5k
      50, // qsub_0 -> DTriple_with_ssub_4
10234
11.5k
      0,  // qsub_1
10235
11.5k
      0,  // qsub_2
10236
11.5k
      0,  // qsub_3
10237
11.5k
      50, // ssub_0 -> DTriple_with_ssub_4
10238
11.5k
      50, // ssub_1 -> DTriple_with_ssub_4
10239
11.5k
      50, // ssub_2 -> DTriple_with_ssub_4
10240
11.5k
      50, // ssub_3 -> DTriple_with_ssub_4
10241
11.5k
      50, // ssub_4 -> DTriple_with_ssub_4
10242
11.5k
      50, // ssub_5 -> DTriple_with_ssub_4
10243
11.5k
      0,  // ssub_6
10244
11.5k
      0,  // ssub_7
10245
11.5k
      0,  // ssub_8
10246
11.5k
      0,  // ssub_9
10247
11.5k
      0,  // ssub_10
10248
11.5k
      0,  // ssub_11
10249
11.5k
      0,  // ssub_12
10250
11.5k
      0,  // ssub_13
10251
11.5k
      0,  // dsub_7_then_ssub_0
10252
11.5k
      0,  // dsub_7_then_ssub_1
10253
11.5k
      50, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4
10254
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10255
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10256
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10257
11.5k
      50, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4
10258
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10259
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10260
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10261
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10262
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10263
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10264
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10265
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10266
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10267
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10268
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10269
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10270
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10271
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10272
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10273
11.5k
      0,  // dsub_5_dsub_7
10274
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10275
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10276
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10277
11.5k
    },
10278
11.5k
    { // DTripleSpc_with_ssub_8
10279
11.5k
      51, // dsub_0 -> DTripleSpc_with_ssub_8
10280
11.5k
      0,  // dsub_1
10281
11.5k
      51, // dsub_2 -> DTripleSpc_with_ssub_8
10282
11.5k
      0,  // dsub_3
10283
11.5k
      51, // dsub_4 -> DTripleSpc_with_ssub_8
10284
11.5k
      0,  // dsub_5
10285
11.5k
      0,  // dsub_6
10286
11.5k
      0,  // dsub_7
10287
11.5k
      0,  // gsub_0
10288
11.5k
      0,  // gsub_1
10289
11.5k
      0,  // qqsub_0
10290
11.5k
      0,  // qqsub_1
10291
11.5k
      0,  // qsub_0
10292
11.5k
      0,  // qsub_1
10293
11.5k
      0,  // qsub_2
10294
11.5k
      0,  // qsub_3
10295
11.5k
      51, // ssub_0 -> DTripleSpc_with_ssub_8
10296
11.5k
      51, // ssub_1 -> DTripleSpc_with_ssub_8
10297
11.5k
      0,  // ssub_2
10298
11.5k
      0,  // ssub_3
10299
11.5k
      51, // ssub_4 -> DTripleSpc_with_ssub_8
10300
11.5k
      51, // ssub_5 -> DTripleSpc_with_ssub_8
10301
11.5k
      0,  // ssub_6
10302
11.5k
      0,  // ssub_7
10303
11.5k
      51, // ssub_8 -> DTripleSpc_with_ssub_8
10304
11.5k
      51, // ssub_9 -> DTripleSpc_with_ssub_8
10305
11.5k
      0,  // ssub_10
10306
11.5k
      0,  // ssub_11
10307
11.5k
      0,  // ssub_12
10308
11.5k
      0,  // ssub_13
10309
11.5k
      0,  // dsub_7_then_ssub_0
10310
11.5k
      0,  // dsub_7_then_ssub_1
10311
11.5k
      51, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_8
10312
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10313
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10314
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10315
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
10316
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10317
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10318
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10319
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10320
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10321
11.5k
      51, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_8
10322
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10323
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10324
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10325
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10326
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10327
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10328
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10329
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10330
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10331
11.5k
      0,  // dsub_5_dsub_7
10332
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10333
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10334
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10335
11.5k
    },
10336
11.5k
    { // DTripleSpc_with_dsub_0_in_DPR_8
10337
11.5k
      52, // dsub_0 -> DTripleSpc_with_dsub_0_in_DPR_8
10338
11.5k
      0,  // dsub_1
10339
11.5k
      52, // dsub_2 -> DTripleSpc_with_dsub_0_in_DPR_8
10340
11.5k
      0,  // dsub_3
10341
11.5k
      52, // dsub_4 -> DTripleSpc_with_dsub_0_in_DPR_8
10342
11.5k
      0,  // dsub_5
10343
11.5k
      0,  // dsub_6
10344
11.5k
      0,  // dsub_7
10345
11.5k
      0,  // gsub_0
10346
11.5k
      0,  // gsub_1
10347
11.5k
      0,  // qqsub_0
10348
11.5k
      0,  // qqsub_1
10349
11.5k
      0,  // qsub_0
10350
11.5k
      0,  // qsub_1
10351
11.5k
      0,  // qsub_2
10352
11.5k
      0,  // qsub_3
10353
11.5k
      52, // ssub_0 -> DTripleSpc_with_dsub_0_in_DPR_8
10354
11.5k
      52, // ssub_1 -> DTripleSpc_with_dsub_0_in_DPR_8
10355
11.5k
      0,  // ssub_2
10356
11.5k
      0,  // ssub_3
10357
11.5k
      52, // ssub_4 -> DTripleSpc_with_dsub_0_in_DPR_8
10358
11.5k
      52, // ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8
10359
11.5k
      0,  // ssub_6
10360
11.5k
      0,  // ssub_7
10361
11.5k
      52, // ssub_8 -> DTripleSpc_with_dsub_0_in_DPR_8
10362
11.5k
      52, // ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8
10363
11.5k
      0,  // ssub_10
10364
11.5k
      0,  // ssub_11
10365
11.5k
      0,  // ssub_12
10366
11.5k
      0,  // ssub_13
10367
11.5k
      0,  // dsub_7_then_ssub_0
10368
11.5k
      0,  // dsub_7_then_ssub_1
10369
11.5k
      52, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8
10370
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10371
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10372
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10373
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
10374
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10375
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10376
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10377
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10378
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10379
11.5k
      52, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8
10380
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10381
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10382
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10383
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10384
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10385
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10386
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10387
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10388
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10389
11.5k
      0,  // dsub_5_dsub_7
10390
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10391
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10392
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10393
11.5k
    },
10394
11.5k
    { // DTriple_with_dsub_0_in_DPR_8
10395
11.5k
      53, // dsub_0 -> DTriple_with_dsub_0_in_DPR_8
10396
11.5k
      53, // dsub_1 -> DTriple_with_dsub_0_in_DPR_8
10397
11.5k
      53, // dsub_2 -> DTriple_with_dsub_0_in_DPR_8
10398
11.5k
      0,  // dsub_3
10399
11.5k
      0,  // dsub_4
10400
11.5k
      0,  // dsub_5
10401
11.5k
      0,  // dsub_6
10402
11.5k
      0,  // dsub_7
10403
11.5k
      0,  // gsub_0
10404
11.5k
      0,  // gsub_1
10405
11.5k
      0,  // qqsub_0
10406
11.5k
      0,  // qqsub_1
10407
11.5k
      53, // qsub_0 -> DTriple_with_dsub_0_in_DPR_8
10408
11.5k
      0,  // qsub_1
10409
11.5k
      0,  // qsub_2
10410
11.5k
      0,  // qsub_3
10411
11.5k
      53, // ssub_0 -> DTriple_with_dsub_0_in_DPR_8
10412
11.5k
      53, // ssub_1 -> DTriple_with_dsub_0_in_DPR_8
10413
11.5k
      53, // ssub_2 -> DTriple_with_dsub_0_in_DPR_8
10414
11.5k
      53, // ssub_3 -> DTriple_with_dsub_0_in_DPR_8
10415
11.5k
      53, // ssub_4 -> DTriple_with_dsub_0_in_DPR_8
10416
11.5k
      53, // ssub_5 -> DTriple_with_dsub_0_in_DPR_8
10417
11.5k
      0,  // ssub_6
10418
11.5k
      0,  // ssub_7
10419
11.5k
      0,  // ssub_8
10420
11.5k
      0,  // ssub_9
10421
11.5k
      0,  // ssub_10
10422
11.5k
      0,  // ssub_11
10423
11.5k
      0,  // ssub_12
10424
11.5k
      0,  // ssub_13
10425
11.5k
      0,  // dsub_7_then_ssub_0
10426
11.5k
      0,  // dsub_7_then_ssub_1
10427
11.5k
      53, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8
10428
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10429
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10430
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10431
11.5k
      53, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8
10432
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10433
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10434
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10435
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10436
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10437
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10438
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10439
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10440
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10441
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10442
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10443
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10444
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10445
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10446
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10447
11.5k
      0,  // dsub_5_dsub_7
10448
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10449
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10450
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10451
11.5k
    },
10452
11.5k
    { // DTriple_with_qsub_0_in_QPR_VFP2
10453
11.5k
      54, // dsub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
10454
11.5k
      54, // dsub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
10455
11.5k
      54, // dsub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
10456
11.5k
      0,  // dsub_3
10457
11.5k
      0,  // dsub_4
10458
11.5k
      0,  // dsub_5
10459
11.5k
      0,  // dsub_6
10460
11.5k
      0,  // dsub_7
10461
11.5k
      0,  // gsub_0
10462
11.5k
      0,  // gsub_1
10463
11.5k
      0,  // qqsub_0
10464
11.5k
      0,  // qqsub_1
10465
11.5k
      54, // qsub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
10466
11.5k
      0,  // qsub_1
10467
11.5k
      0,  // qsub_2
10468
11.5k
      0,  // qsub_3
10469
11.5k
      54, // ssub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
10470
11.5k
      54, // ssub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
10471
11.5k
      54, // ssub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
10472
11.5k
      54, // ssub_3 -> DTriple_with_qsub_0_in_QPR_VFP2
10473
11.5k
      58, // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10474
11.5k
      58, // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10475
11.5k
      0,  // ssub_6
10476
11.5k
      0,  // ssub_7
10477
11.5k
      0,  // ssub_8
10478
11.5k
      0,  // ssub_9
10479
11.5k
      0,  // ssub_10
10480
11.5k
      0,  // ssub_11
10481
11.5k
      0,  // ssub_12
10482
11.5k
      0,  // ssub_13
10483
11.5k
      0,  // dsub_7_then_ssub_0
10484
11.5k
      0,  // dsub_7_then_ssub_1
10485
11.5k
      54, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_VFP2
10486
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10487
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10488
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10489
11.5k
      54, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_VFP2
10490
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10491
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10492
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10493
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10494
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10495
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10496
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10497
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10498
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10499
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10500
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10501
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10502
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10503
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10504
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10505
11.5k
      0,  // dsub_5_dsub_7
10506
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10507
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10508
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10509
11.5k
    },
10510
11.5k
    { // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10511
11.5k
      55, // dsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10512
11.5k
      55, // dsub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10513
11.5k
      55, // dsub_2 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10514
11.5k
      0,  // dsub_3
10515
11.5k
      0,  // dsub_4
10516
11.5k
      0,  // dsub_5
10517
11.5k
      0,  // dsub_6
10518
11.5k
      0,  // dsub_7
10519
11.5k
      0,  // gsub_0
10520
11.5k
      0,  // gsub_1
10521
11.5k
      0,  // qqsub_0
10522
11.5k
      0,  // qqsub_1
10523
11.5k
      55, // qsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10524
11.5k
      0,  // qsub_1
10525
11.5k
      0,  // qsub_2
10526
11.5k
      0,  // qsub_3
10527
11.5k
      55, // ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10528
11.5k
      55, // ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10529
11.5k
      57, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10530
11.5k
      57, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10531
11.5k
      57, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10532
11.5k
      57, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10533
11.5k
      0,  // ssub_6
10534
11.5k
      0,  // ssub_7
10535
11.5k
      0,  // ssub_8
10536
11.5k
      0,  // ssub_9
10537
11.5k
      0,  // ssub_10
10538
11.5k
      0,  // ssub_11
10539
11.5k
      0,  // ssub_12
10540
11.5k
      0,  // ssub_13
10541
11.5k
      0,  // dsub_7_then_ssub_0
10542
11.5k
      0,  // dsub_7_then_ssub_1
10543
11.5k
      55, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10544
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10545
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10546
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10547
11.5k
      55, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10548
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10549
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10550
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10551
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10552
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10553
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10554
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10555
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10556
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10557
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10558
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10559
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10560
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10561
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10562
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10563
11.5k
      0,  // dsub_5_dsub_7
10564
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10565
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10566
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10567
11.5k
    },
10568
11.5k
    { // DTriple_with_dsub_1_in_DPR_8
10569
11.5k
      56, // dsub_0 -> DTriple_with_dsub_1_in_DPR_8
10570
11.5k
      56, // dsub_1 -> DTriple_with_dsub_1_in_DPR_8
10571
11.5k
      56, // dsub_2 -> DTriple_with_dsub_1_in_DPR_8
10572
11.5k
      0,  // dsub_3
10573
11.5k
      0,  // dsub_4
10574
11.5k
      0,  // dsub_5
10575
11.5k
      0,  // dsub_6
10576
11.5k
      0,  // dsub_7
10577
11.5k
      0,  // gsub_0
10578
11.5k
      0,  // gsub_1
10579
11.5k
      0,  // qqsub_0
10580
11.5k
      0,  // qqsub_1
10581
11.5k
      56, // qsub_0 -> DTriple_with_dsub_1_in_DPR_8
10582
11.5k
      0,  // qsub_1
10583
11.5k
      0,  // qsub_2
10584
11.5k
      0,  // qsub_3
10585
11.5k
      56, // ssub_0 -> DTriple_with_dsub_1_in_DPR_8
10586
11.5k
      56, // ssub_1 -> DTriple_with_dsub_1_in_DPR_8
10587
11.5k
      56, // ssub_2 -> DTriple_with_dsub_1_in_DPR_8
10588
11.5k
      56, // ssub_3 -> DTriple_with_dsub_1_in_DPR_8
10589
11.5k
      56, // ssub_4 -> DTriple_with_dsub_1_in_DPR_8
10590
11.5k
      56, // ssub_5 -> DTriple_with_dsub_1_in_DPR_8
10591
11.5k
      0,  // ssub_6
10592
11.5k
      0,  // ssub_7
10593
11.5k
      0,  // ssub_8
10594
11.5k
      0,  // ssub_9
10595
11.5k
      0,  // ssub_10
10596
11.5k
      0,  // ssub_11
10597
11.5k
      0,  // ssub_12
10598
11.5k
      0,  // ssub_13
10599
11.5k
      0,  // dsub_7_then_ssub_0
10600
11.5k
      0,  // dsub_7_then_ssub_1
10601
11.5k
      56, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8
10602
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10603
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10604
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10605
11.5k
      56, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8
10606
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10607
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10608
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10609
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10610
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10611
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10612
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10613
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10614
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10615
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10616
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10617
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10618
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10619
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10620
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10621
11.5k
      0,  // dsub_5_dsub_7
10622
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10623
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10624
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10625
11.5k
    },
10626
11.5k
    { // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10627
11.5k
      57, // dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10628
11.5k
      57, // dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10629
11.5k
      57, // dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10630
11.5k
      0,  // dsub_3
10631
11.5k
      0,  // dsub_4
10632
11.5k
      0,  // dsub_5
10633
11.5k
      0,  // dsub_6
10634
11.5k
      0,  // dsub_7
10635
11.5k
      0,  // gsub_0
10636
11.5k
      0,  // gsub_1
10637
11.5k
      0,  // qqsub_0
10638
11.5k
      0,  // qqsub_1
10639
11.5k
      57, // qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10640
11.5k
      0,  // qsub_1
10641
11.5k
      0,  // qsub_2
10642
11.5k
      0,  // qsub_3
10643
11.5k
      57, // ssub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10644
11.5k
      57, // ssub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10645
11.5k
      57, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10646
11.5k
      57, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10647
11.5k
      57, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10648
11.5k
      57, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10649
11.5k
      0,  // ssub_6
10650
11.5k
      0,  // ssub_7
10651
11.5k
      0,  // ssub_8
10652
11.5k
      0,  // ssub_9
10653
11.5k
      0,  // ssub_10
10654
11.5k
      0,  // ssub_11
10655
11.5k
      0,  // ssub_12
10656
11.5k
      0,  // ssub_13
10657
11.5k
      0,  // dsub_7_then_ssub_0
10658
11.5k
      0,  // dsub_7_then_ssub_1
10659
11.5k
      57, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10660
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10661
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10662
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10663
11.5k
      57, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10664
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10665
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10666
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10667
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10668
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10669
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10670
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10671
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10672
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10673
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10674
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10675
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10676
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10677
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10678
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10679
11.5k
      0,  // dsub_5_dsub_7
10680
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10681
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10682
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10683
11.5k
    },
10684
11.5k
    { // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10685
11.5k
      58, // dsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10686
11.5k
      58, // dsub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10687
11.5k
      58, // dsub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10688
11.5k
      0,  // dsub_3
10689
11.5k
      0,  // dsub_4
10690
11.5k
      0,  // dsub_5
10691
11.5k
      0,  // dsub_6
10692
11.5k
      0,  // dsub_7
10693
11.5k
      0,  // gsub_0
10694
11.5k
      0,  // gsub_1
10695
11.5k
      0,  // qqsub_0
10696
11.5k
      0,  // qqsub_1
10697
11.5k
      58, // qsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10698
11.5k
      0,  // qsub_1
10699
11.5k
      0,  // qsub_2
10700
11.5k
      0,  // qsub_3
10701
11.5k
      58, // ssub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10702
11.5k
      58, // ssub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10703
11.5k
      58, // ssub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10704
11.5k
      58, // ssub_3 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10705
11.5k
      58, // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10706
11.5k
      58, // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10707
11.5k
      0,  // ssub_6
10708
11.5k
      0,  // ssub_7
10709
11.5k
      0,  // ssub_8
10710
11.5k
      0,  // ssub_9
10711
11.5k
      0,  // ssub_10
10712
11.5k
      0,  // ssub_11
10713
11.5k
      0,  // ssub_12
10714
11.5k
      0,  // ssub_13
10715
11.5k
      0,  // dsub_7_then_ssub_0
10716
11.5k
      0,  // dsub_7_then_ssub_1
10717
11.5k
      58, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10718
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10719
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10720
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10721
11.5k
      58, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10722
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10723
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10724
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10725
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10726
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10727
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10728
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10729
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10730
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10731
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10732
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10733
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10734
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10735
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10736
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10737
11.5k
      0,  // dsub_5_dsub_7
10738
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10739
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10740
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10741
11.5k
    },
10742
11.5k
    { // DTripleSpc_with_dsub_2_in_DPR_8
10743
11.5k
      59, // dsub_0 -> DTripleSpc_with_dsub_2_in_DPR_8
10744
11.5k
      0,  // dsub_1
10745
11.5k
      59, // dsub_2 -> DTripleSpc_with_dsub_2_in_DPR_8
10746
11.5k
      0,  // dsub_3
10747
11.5k
      59, // dsub_4 -> DTripleSpc_with_dsub_2_in_DPR_8
10748
11.5k
      0,  // dsub_5
10749
11.5k
      0,  // dsub_6
10750
11.5k
      0,  // dsub_7
10751
11.5k
      0,  // gsub_0
10752
11.5k
      0,  // gsub_1
10753
11.5k
      0,  // qqsub_0
10754
11.5k
      0,  // qqsub_1
10755
11.5k
      0,  // qsub_0
10756
11.5k
      0,  // qsub_1
10757
11.5k
      0,  // qsub_2
10758
11.5k
      0,  // qsub_3
10759
11.5k
      59, // ssub_0 -> DTripleSpc_with_dsub_2_in_DPR_8
10760
11.5k
      59, // ssub_1 -> DTripleSpc_with_dsub_2_in_DPR_8
10761
11.5k
      0,  // ssub_2
10762
11.5k
      0,  // ssub_3
10763
11.5k
      59, // ssub_4 -> DTripleSpc_with_dsub_2_in_DPR_8
10764
11.5k
      59, // ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8
10765
11.5k
      0,  // ssub_6
10766
11.5k
      0,  // ssub_7
10767
11.5k
      59, // ssub_8 -> DTripleSpc_with_dsub_2_in_DPR_8
10768
11.5k
      59, // ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8
10769
11.5k
      0,  // ssub_10
10770
11.5k
      0,  // ssub_11
10771
11.5k
      0,  // ssub_12
10772
11.5k
      0,  // ssub_13
10773
11.5k
      0,  // dsub_7_then_ssub_0
10774
11.5k
      0,  // dsub_7_then_ssub_1
10775
11.5k
      59, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8
10776
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10777
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10778
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10779
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
10780
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10781
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10782
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10783
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10784
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10785
11.5k
      59, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8
10786
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10787
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10788
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10789
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10790
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10791
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10792
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10793
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10794
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10795
11.5k
      0,  // dsub_5_dsub_7
10796
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10797
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10798
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10799
11.5k
    },
10800
11.5k
    { // DTriple_with_dsub_2_in_DPR_8
10801
11.5k
      60, // dsub_0 -> DTriple_with_dsub_2_in_DPR_8
10802
11.5k
      60, // dsub_1 -> DTriple_with_dsub_2_in_DPR_8
10803
11.5k
      60, // dsub_2 -> DTriple_with_dsub_2_in_DPR_8
10804
11.5k
      0,  // dsub_3
10805
11.5k
      0,  // dsub_4
10806
11.5k
      0,  // dsub_5
10807
11.5k
      0,  // dsub_6
10808
11.5k
      0,  // dsub_7
10809
11.5k
      0,  // gsub_0
10810
11.5k
      0,  // gsub_1
10811
11.5k
      0,  // qqsub_0
10812
11.5k
      0,  // qqsub_1
10813
11.5k
      60, // qsub_0 -> DTriple_with_dsub_2_in_DPR_8
10814
11.5k
      0,  // qsub_1
10815
11.5k
      0,  // qsub_2
10816
11.5k
      0,  // qsub_3
10817
11.5k
      60, // ssub_0 -> DTriple_with_dsub_2_in_DPR_8
10818
11.5k
      60, // ssub_1 -> DTriple_with_dsub_2_in_DPR_8
10819
11.5k
      60, // ssub_2 -> DTriple_with_dsub_2_in_DPR_8
10820
11.5k
      60, // ssub_3 -> DTriple_with_dsub_2_in_DPR_8
10821
11.5k
      60, // ssub_4 -> DTriple_with_dsub_2_in_DPR_8
10822
11.5k
      60, // ssub_5 -> DTriple_with_dsub_2_in_DPR_8
10823
11.5k
      0,  // ssub_6
10824
11.5k
      0,  // ssub_7
10825
11.5k
      0,  // ssub_8
10826
11.5k
      0,  // ssub_9
10827
11.5k
      0,  // ssub_10
10828
11.5k
      0,  // ssub_11
10829
11.5k
      0,  // ssub_12
10830
11.5k
      0,  // ssub_13
10831
11.5k
      0,  // dsub_7_then_ssub_0
10832
11.5k
      0,  // dsub_7_then_ssub_1
10833
11.5k
      60, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8
10834
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10835
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10836
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10837
11.5k
      60, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8
10838
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10839
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10840
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10841
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10842
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10843
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10844
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10845
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10846
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10847
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10848
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10849
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10850
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10851
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10852
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10853
11.5k
      0,  // dsub_5_dsub_7
10854
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10855
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10856
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10857
11.5k
    },
10858
11.5k
    { // DTripleSpc_with_dsub_4_in_DPR_8
10859
11.5k
      61, // dsub_0 -> DTripleSpc_with_dsub_4_in_DPR_8
10860
11.5k
      0,  // dsub_1
10861
11.5k
      61, // dsub_2 -> DTripleSpc_with_dsub_4_in_DPR_8
10862
11.5k
      0,  // dsub_3
10863
11.5k
      61, // dsub_4 -> DTripleSpc_with_dsub_4_in_DPR_8
10864
11.5k
      0,  // dsub_5
10865
11.5k
      0,  // dsub_6
10866
11.5k
      0,  // dsub_7
10867
11.5k
      0,  // gsub_0
10868
11.5k
      0,  // gsub_1
10869
11.5k
      0,  // qqsub_0
10870
11.5k
      0,  // qqsub_1
10871
11.5k
      0,  // qsub_0
10872
11.5k
      0,  // qsub_1
10873
11.5k
      0,  // qsub_2
10874
11.5k
      0,  // qsub_3
10875
11.5k
      61, // ssub_0 -> DTripleSpc_with_dsub_4_in_DPR_8
10876
11.5k
      61, // ssub_1 -> DTripleSpc_with_dsub_4_in_DPR_8
10877
11.5k
      0,  // ssub_2
10878
11.5k
      0,  // ssub_3
10879
11.5k
      61, // ssub_4 -> DTripleSpc_with_dsub_4_in_DPR_8
10880
11.5k
      61, // ssub_5 -> DTripleSpc_with_dsub_4_in_DPR_8
10881
11.5k
      0,  // ssub_6
10882
11.5k
      0,  // ssub_7
10883
11.5k
      61, // ssub_8 -> DTripleSpc_with_dsub_4_in_DPR_8
10884
11.5k
      61, // ssub_9 -> DTripleSpc_with_dsub_4_in_DPR_8
10885
11.5k
      0,  // ssub_10
10886
11.5k
      0,  // ssub_11
10887
11.5k
      0,  // ssub_12
10888
11.5k
      0,  // ssub_13
10889
11.5k
      0,  // dsub_7_then_ssub_0
10890
11.5k
      0,  // dsub_7_then_ssub_1
10891
11.5k
      61, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_4_in_DPR_8
10892
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10893
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10894
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10895
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
10896
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10897
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10898
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10899
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10900
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10901
11.5k
      61, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_4_in_DPR_8
10902
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10903
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10904
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10905
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10906
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10907
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10908
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10909
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10910
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10911
11.5k
      0,  // dsub_5_dsub_7
10912
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10913
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10914
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10915
11.5k
    },
10916
11.5k
    { // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10917
11.5k
      62, // dsub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10918
11.5k
      62, // dsub_1 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10919
11.5k
      62, // dsub_2 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10920
11.5k
      0,  // dsub_3
10921
11.5k
      0,  // dsub_4
10922
11.5k
      0,  // dsub_5
10923
11.5k
      0,  // dsub_6
10924
11.5k
      0,  // dsub_7
10925
11.5k
      0,  // gsub_0
10926
11.5k
      0,  // gsub_1
10927
11.5k
      0,  // qqsub_0
10928
11.5k
      0,  // qqsub_1
10929
11.5k
      62, // qsub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10930
11.5k
      0,  // qsub_1
10931
11.5k
      0,  // qsub_2
10932
11.5k
      0,  // qsub_3
10933
11.5k
      62, // ssub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10934
11.5k
      62, // ssub_1 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10935
11.5k
      62, // ssub_2 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10936
11.5k
      62, // ssub_3 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10937
11.5k
      62, // ssub_4 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10938
11.5k
      62, // ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10939
11.5k
      0,  // ssub_6
10940
11.5k
      0,  // ssub_7
10941
11.5k
      0,  // ssub_8
10942
11.5k
      0,  // ssub_9
10943
11.5k
      0,  // ssub_10
10944
11.5k
      0,  // ssub_11
10945
11.5k
      0,  // ssub_12
10946
11.5k
      0,  // ssub_13
10947
11.5k
      0,  // dsub_7_then_ssub_0
10948
11.5k
      0,  // dsub_7_then_ssub_1
10949
11.5k
      62, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10950
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10951
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
10952
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10953
11.5k
      62, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10954
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10955
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10956
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10957
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10958
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10959
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
10960
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10961
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10962
11.5k
      0,  // ssub_6_ssub_7_dsub_5
10963
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10964
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
10965
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
10966
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10967
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
10968
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10969
11.5k
      0,  // dsub_5_dsub_7
10970
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
10971
11.5k
      0,  // dsub_5_ssub_12_ssub_13
10972
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10973
11.5k
    },
10974
11.5k
    { // DTriple_with_qsub_0_in_QPR_8
10975
11.5k
      63, // dsub_0 -> DTriple_with_qsub_0_in_QPR_8
10976
11.5k
      63, // dsub_1 -> DTriple_with_qsub_0_in_QPR_8
10977
11.5k
      63, // dsub_2 -> DTriple_with_qsub_0_in_QPR_8
10978
11.5k
      0,  // dsub_3
10979
11.5k
      0,  // dsub_4
10980
11.5k
      0,  // dsub_5
10981
11.5k
      0,  // dsub_6
10982
11.5k
      0,  // dsub_7
10983
11.5k
      0,  // gsub_0
10984
11.5k
      0,  // gsub_1
10985
11.5k
      0,  // qqsub_0
10986
11.5k
      0,  // qqsub_1
10987
11.5k
      63, // qsub_0 -> DTriple_with_qsub_0_in_QPR_8
10988
11.5k
      0,  // qsub_1
10989
11.5k
      0,  // qsub_2
10990
11.5k
      0,  // qsub_3
10991
11.5k
      63, // ssub_0 -> DTriple_with_qsub_0_in_QPR_8
10992
11.5k
      63, // ssub_1 -> DTriple_with_qsub_0_in_QPR_8
10993
11.5k
      63, // ssub_2 -> DTriple_with_qsub_0_in_QPR_8
10994
11.5k
      63, // ssub_3 -> DTriple_with_qsub_0_in_QPR_8
10995
11.5k
      63, // ssub_4 -> DTriple_with_qsub_0_in_QPR_8
10996
11.5k
      63, // ssub_5 -> DTriple_with_qsub_0_in_QPR_8
10997
11.5k
      0,  // ssub_6
10998
11.5k
      0,  // ssub_7
10999
11.5k
      0,  // ssub_8
11000
11.5k
      0,  // ssub_9
11001
11.5k
      0,  // ssub_10
11002
11.5k
      0,  // ssub_11
11003
11.5k
      0,  // ssub_12
11004
11.5k
      0,  // ssub_13
11005
11.5k
      0,  // dsub_7_then_ssub_0
11006
11.5k
      0,  // dsub_7_then_ssub_1
11007
11.5k
      63, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_8
11008
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11009
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
11010
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11011
11.5k
      63, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_8
11012
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11013
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11014
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11015
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11016
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11017
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
11018
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11019
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11020
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11021
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11022
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11023
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11024
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11025
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11026
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11027
11.5k
      0,  // dsub_5_dsub_7
11028
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11029
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11030
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11031
11.5k
    },
11032
11.5k
    { // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11033
11.5k
      64, // dsub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11034
11.5k
      64, // dsub_1 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11035
11.5k
      64, // dsub_2 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11036
11.5k
      0,  // dsub_3
11037
11.5k
      0,  // dsub_4
11038
11.5k
      0,  // dsub_5
11039
11.5k
      0,  // dsub_6
11040
11.5k
      0,  // dsub_7
11041
11.5k
      0,  // gsub_0
11042
11.5k
      0,  // gsub_1
11043
11.5k
      0,  // qqsub_0
11044
11.5k
      0,  // qqsub_1
11045
11.5k
      64, // qsub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11046
11.5k
      0,  // qsub_1
11047
11.5k
      0,  // qsub_2
11048
11.5k
      0,  // qsub_3
11049
11.5k
      64, // ssub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11050
11.5k
      64, // ssub_1 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11051
11.5k
      64, // ssub_2 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11052
11.5k
      64, // ssub_3 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11053
11.5k
      64, // ssub_4 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11054
11.5k
      64, // ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11055
11.5k
      0,  // ssub_6
11056
11.5k
      0,  // ssub_7
11057
11.5k
      0,  // ssub_8
11058
11.5k
      0,  // ssub_9
11059
11.5k
      0,  // ssub_10
11060
11.5k
      0,  // ssub_11
11061
11.5k
      0,  // ssub_12
11062
11.5k
      0,  // ssub_13
11063
11.5k
      0,  // dsub_7_then_ssub_0
11064
11.5k
      0,  // dsub_7_then_ssub_1
11065
11.5k
      64, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11066
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11067
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
11068
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11069
11.5k
      64, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11070
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11071
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11072
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11073
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11074
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11075
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
11076
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11077
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11078
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11079
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11080
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11081
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11082
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11083
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11084
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11085
11.5k
      0,  // dsub_5_dsub_7
11086
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11087
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11088
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11089
11.5k
    },
11090
11.5k
    { // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11091
11.5k
      65, // dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11092
11.5k
      65, // dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11093
11.5k
      65, // dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11094
11.5k
      0,  // dsub_3
11095
11.5k
      0,  // dsub_4
11096
11.5k
      0,  // dsub_5
11097
11.5k
      0,  // dsub_6
11098
11.5k
      0,  // dsub_7
11099
11.5k
      0,  // gsub_0
11100
11.5k
      0,  // gsub_1
11101
11.5k
      0,  // qqsub_0
11102
11.5k
      0,  // qqsub_1
11103
11.5k
      65, // qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11104
11.5k
      0,  // qsub_1
11105
11.5k
      0,  // qsub_2
11106
11.5k
      0,  // qsub_3
11107
11.5k
      65, // ssub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11108
11.5k
      65, // ssub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11109
11.5k
      65, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11110
11.5k
      65, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11111
11.5k
      65, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11112
11.5k
      65, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11113
11.5k
      0,  // ssub_6
11114
11.5k
      0,  // ssub_7
11115
11.5k
      0,  // ssub_8
11116
11.5k
      0,  // ssub_9
11117
11.5k
      0,  // ssub_10
11118
11.5k
      0,  // ssub_11
11119
11.5k
      0,  // ssub_12
11120
11.5k
      0,  // ssub_13
11121
11.5k
      0,  // dsub_7_then_ssub_0
11122
11.5k
      0,  // dsub_7_then_ssub_1
11123
11.5k
      65, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11124
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11125
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
11126
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11127
11.5k
      65, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11128
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11129
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11130
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11131
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11132
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11133
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
11134
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11135
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11136
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11137
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11138
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11139
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11140
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11141
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11142
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11143
11.5k
      0,  // dsub_5_dsub_7
11144
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11145
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11146
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11147
11.5k
    },
11148
11.5k
    { // DQuadSpc
11149
11.5k
      66, // dsub_0 -> DQuadSpc
11150
11.5k
      0,  // dsub_1
11151
11.5k
      66, // dsub_2 -> DQuadSpc
11152
11.5k
      0,  // dsub_3
11153
11.5k
      66, // dsub_4 -> DQuadSpc
11154
11.5k
      0,  // dsub_5
11155
11.5k
      0,  // dsub_6
11156
11.5k
      0,  // dsub_7
11157
11.5k
      0,  // gsub_0
11158
11.5k
      0,  // gsub_1
11159
11.5k
      0,  // qqsub_0
11160
11.5k
      0,  // qqsub_1
11161
11.5k
      0,  // qsub_0
11162
11.5k
      0,  // qsub_1
11163
11.5k
      0,  // qsub_2
11164
11.5k
      0,  // qsub_3
11165
11.5k
      67, // ssub_0 -> DQuadSpc_with_ssub_0
11166
11.5k
      67, // ssub_1 -> DQuadSpc_with_ssub_0
11167
11.5k
      0,  // ssub_2
11168
11.5k
      0,  // ssub_3
11169
11.5k
      68, // ssub_4 -> DQuadSpc_with_ssub_4
11170
11.5k
      68, // ssub_5 -> DQuadSpc_with_ssub_4
11171
11.5k
      0,  // ssub_6
11172
11.5k
      0,  // ssub_7
11173
11.5k
      69, // ssub_8 -> DQuadSpc_with_ssub_8
11174
11.5k
      69, // ssub_9 -> DQuadSpc_with_ssub_8
11175
11.5k
      0,  // ssub_10
11176
11.5k
      0,  // ssub_11
11177
11.5k
      0,  // ssub_12
11178
11.5k
      0,  // ssub_13
11179
11.5k
      0,  // dsub_7_then_ssub_0
11180
11.5k
      0,  // dsub_7_then_ssub_1
11181
11.5k
      66, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc
11182
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11183
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
11184
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11185
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
11186
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11187
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11188
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11189
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11190
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11191
11.5k
      66, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc
11192
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11193
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11194
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11195
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11196
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11197
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11198
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11199
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11200
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11201
11.5k
      0,  // dsub_5_dsub_7
11202
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11203
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11204
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11205
11.5k
    },
11206
11.5k
    { // DQuadSpc_with_ssub_0
11207
11.5k
      67, // dsub_0 -> DQuadSpc_with_ssub_0
11208
11.5k
      0,  // dsub_1
11209
11.5k
      67, // dsub_2 -> DQuadSpc_with_ssub_0
11210
11.5k
      0,  // dsub_3
11211
11.5k
      67, // dsub_4 -> DQuadSpc_with_ssub_0
11212
11.5k
      0,  // dsub_5
11213
11.5k
      0,  // dsub_6
11214
11.5k
      0,  // dsub_7
11215
11.5k
      0,  // gsub_0
11216
11.5k
      0,  // gsub_1
11217
11.5k
      0,  // qqsub_0
11218
11.5k
      0,  // qqsub_1
11219
11.5k
      0,  // qsub_0
11220
11.5k
      0,  // qsub_1
11221
11.5k
      0,  // qsub_2
11222
11.5k
      0,  // qsub_3
11223
11.5k
      67, // ssub_0 -> DQuadSpc_with_ssub_0
11224
11.5k
      67, // ssub_1 -> DQuadSpc_with_ssub_0
11225
11.5k
      0,  // ssub_2
11226
11.5k
      0,  // ssub_3
11227
11.5k
      68, // ssub_4 -> DQuadSpc_with_ssub_4
11228
11.5k
      68, // ssub_5 -> DQuadSpc_with_ssub_4
11229
11.5k
      0,  // ssub_6
11230
11.5k
      0,  // ssub_7
11231
11.5k
      69, // ssub_8 -> DQuadSpc_with_ssub_8
11232
11.5k
      69, // ssub_9 -> DQuadSpc_with_ssub_8
11233
11.5k
      0,  // ssub_10
11234
11.5k
      0,  // ssub_11
11235
11.5k
      0,  // ssub_12
11236
11.5k
      0,  // ssub_13
11237
11.5k
      0,  // dsub_7_then_ssub_0
11238
11.5k
      0,  // dsub_7_then_ssub_1
11239
11.5k
      67, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_0
11240
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11241
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
11242
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11243
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
11244
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11245
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11246
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11247
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11248
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11249
11.5k
      67, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_0
11250
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11251
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11252
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11253
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11254
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11255
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11256
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11257
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11258
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11259
11.5k
      0,  // dsub_5_dsub_7
11260
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11261
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11262
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11263
11.5k
    },
11264
11.5k
    { // DQuadSpc_with_ssub_4
11265
11.5k
      68, // dsub_0 -> DQuadSpc_with_ssub_4
11266
11.5k
      0,  // dsub_1
11267
11.5k
      68, // dsub_2 -> DQuadSpc_with_ssub_4
11268
11.5k
      0,  // dsub_3
11269
11.5k
      68, // dsub_4 -> DQuadSpc_with_ssub_4
11270
11.5k
      0,  // dsub_5
11271
11.5k
      0,  // dsub_6
11272
11.5k
      0,  // dsub_7
11273
11.5k
      0,  // gsub_0
11274
11.5k
      0,  // gsub_1
11275
11.5k
      0,  // qqsub_0
11276
11.5k
      0,  // qqsub_1
11277
11.5k
      0,  // qsub_0
11278
11.5k
      0,  // qsub_1
11279
11.5k
      0,  // qsub_2
11280
11.5k
      0,  // qsub_3
11281
11.5k
      68, // ssub_0 -> DQuadSpc_with_ssub_4
11282
11.5k
      68, // ssub_1 -> DQuadSpc_with_ssub_4
11283
11.5k
      0,  // ssub_2
11284
11.5k
      0,  // ssub_3
11285
11.5k
      68, // ssub_4 -> DQuadSpc_with_ssub_4
11286
11.5k
      68, // ssub_5 -> DQuadSpc_with_ssub_4
11287
11.5k
      0,  // ssub_6
11288
11.5k
      0,  // ssub_7
11289
11.5k
      69, // ssub_8 -> DQuadSpc_with_ssub_8
11290
11.5k
      69, // ssub_9 -> DQuadSpc_with_ssub_8
11291
11.5k
      0,  // ssub_10
11292
11.5k
      0,  // ssub_11
11293
11.5k
      0,  // ssub_12
11294
11.5k
      0,  // ssub_13
11295
11.5k
      0,  // dsub_7_then_ssub_0
11296
11.5k
      0,  // dsub_7_then_ssub_1
11297
11.5k
      68, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_4
11298
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11299
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
11300
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11301
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
11302
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11303
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11304
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11305
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11306
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11307
11.5k
      68, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_4
11308
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11309
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11310
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11311
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11312
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11313
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11314
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11315
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11316
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11317
11.5k
      0,  // dsub_5_dsub_7
11318
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11319
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11320
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11321
11.5k
    },
11322
11.5k
    { // DQuadSpc_with_ssub_8
11323
11.5k
      69, // dsub_0 -> DQuadSpc_with_ssub_8
11324
11.5k
      0,  // dsub_1
11325
11.5k
      69, // dsub_2 -> DQuadSpc_with_ssub_8
11326
11.5k
      0,  // dsub_3
11327
11.5k
      69, // dsub_4 -> DQuadSpc_with_ssub_8
11328
11.5k
      0,  // dsub_5
11329
11.5k
      0,  // dsub_6
11330
11.5k
      0,  // dsub_7
11331
11.5k
      0,  // gsub_0
11332
11.5k
      0,  // gsub_1
11333
11.5k
      0,  // qqsub_0
11334
11.5k
      0,  // qqsub_1
11335
11.5k
      0,  // qsub_0
11336
11.5k
      0,  // qsub_1
11337
11.5k
      0,  // qsub_2
11338
11.5k
      0,  // qsub_3
11339
11.5k
      69, // ssub_0 -> DQuadSpc_with_ssub_8
11340
11.5k
      69, // ssub_1 -> DQuadSpc_with_ssub_8
11341
11.5k
      0,  // ssub_2
11342
11.5k
      0,  // ssub_3
11343
11.5k
      69, // ssub_4 -> DQuadSpc_with_ssub_8
11344
11.5k
      69, // ssub_5 -> DQuadSpc_with_ssub_8
11345
11.5k
      0,  // ssub_6
11346
11.5k
      0,  // ssub_7
11347
11.5k
      69, // ssub_8 -> DQuadSpc_with_ssub_8
11348
11.5k
      69, // ssub_9 -> DQuadSpc_with_ssub_8
11349
11.5k
      0,  // ssub_10
11350
11.5k
      0,  // ssub_11
11351
11.5k
      0,  // ssub_12
11352
11.5k
      0,  // ssub_13
11353
11.5k
      0,  // dsub_7_then_ssub_0
11354
11.5k
      0,  // dsub_7_then_ssub_1
11355
11.5k
      69, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_8
11356
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11357
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
11358
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11359
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
11360
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11361
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11362
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11363
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11364
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11365
11.5k
      69, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_8
11366
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11367
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11368
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11369
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11370
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11371
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11372
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11373
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11374
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11375
11.5k
      0,  // dsub_5_dsub_7
11376
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11377
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11378
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11379
11.5k
    },
11380
11.5k
    { // DQuadSpc_with_dsub_0_in_DPR_8
11381
11.5k
      70, // dsub_0 -> DQuadSpc_with_dsub_0_in_DPR_8
11382
11.5k
      0,  // dsub_1
11383
11.5k
      70, // dsub_2 -> DQuadSpc_with_dsub_0_in_DPR_8
11384
11.5k
      0,  // dsub_3
11385
11.5k
      70, // dsub_4 -> DQuadSpc_with_dsub_0_in_DPR_8
11386
11.5k
      0,  // dsub_5
11387
11.5k
      0,  // dsub_6
11388
11.5k
      0,  // dsub_7
11389
11.5k
      0,  // gsub_0
11390
11.5k
      0,  // gsub_1
11391
11.5k
      0,  // qqsub_0
11392
11.5k
      0,  // qqsub_1
11393
11.5k
      0,  // qsub_0
11394
11.5k
      0,  // qsub_1
11395
11.5k
      0,  // qsub_2
11396
11.5k
      0,  // qsub_3
11397
11.5k
      70, // ssub_0 -> DQuadSpc_with_dsub_0_in_DPR_8
11398
11.5k
      70, // ssub_1 -> DQuadSpc_with_dsub_0_in_DPR_8
11399
11.5k
      0,  // ssub_2
11400
11.5k
      0,  // ssub_3
11401
11.5k
      70, // ssub_4 -> DQuadSpc_with_dsub_0_in_DPR_8
11402
11.5k
      70, // ssub_5 -> DQuadSpc_with_dsub_0_in_DPR_8
11403
11.5k
      0,  // ssub_6
11404
11.5k
      0,  // ssub_7
11405
11.5k
      70, // ssub_8 -> DQuadSpc_with_dsub_0_in_DPR_8
11406
11.5k
      70, // ssub_9 -> DQuadSpc_with_dsub_0_in_DPR_8
11407
11.5k
      0,  // ssub_10
11408
11.5k
      0,  // ssub_11
11409
11.5k
      0,  // ssub_12
11410
11.5k
      0,  // ssub_13
11411
11.5k
      0,  // dsub_7_then_ssub_0
11412
11.5k
      0,  // dsub_7_then_ssub_1
11413
11.5k
      70, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_0_in_DPR_8
11414
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11415
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
11416
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11417
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
11418
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11419
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11420
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11421
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11422
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11423
11.5k
      70, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_0_in_DPR_8
11424
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11425
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11426
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11427
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11428
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11429
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11430
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11431
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11432
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11433
11.5k
      0,  // dsub_5_dsub_7
11434
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11435
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11436
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11437
11.5k
    },
11438
11.5k
    { // DQuadSpc_with_dsub_2_in_DPR_8
11439
11.5k
      71, // dsub_0 -> DQuadSpc_with_dsub_2_in_DPR_8
11440
11.5k
      0,  // dsub_1
11441
11.5k
      71, // dsub_2 -> DQuadSpc_with_dsub_2_in_DPR_8
11442
11.5k
      0,  // dsub_3
11443
11.5k
      71, // dsub_4 -> DQuadSpc_with_dsub_2_in_DPR_8
11444
11.5k
      0,  // dsub_5
11445
11.5k
      0,  // dsub_6
11446
11.5k
      0,  // dsub_7
11447
11.5k
      0,  // gsub_0
11448
11.5k
      0,  // gsub_1
11449
11.5k
      0,  // qqsub_0
11450
11.5k
      0,  // qqsub_1
11451
11.5k
      0,  // qsub_0
11452
11.5k
      0,  // qsub_1
11453
11.5k
      0,  // qsub_2
11454
11.5k
      0,  // qsub_3
11455
11.5k
      71, // ssub_0 -> DQuadSpc_with_dsub_2_in_DPR_8
11456
11.5k
      71, // ssub_1 -> DQuadSpc_with_dsub_2_in_DPR_8
11457
11.5k
      0,  // ssub_2
11458
11.5k
      0,  // ssub_3
11459
11.5k
      71, // ssub_4 -> DQuadSpc_with_dsub_2_in_DPR_8
11460
11.5k
      71, // ssub_5 -> DQuadSpc_with_dsub_2_in_DPR_8
11461
11.5k
      0,  // ssub_6
11462
11.5k
      0,  // ssub_7
11463
11.5k
      71, // ssub_8 -> DQuadSpc_with_dsub_2_in_DPR_8
11464
11.5k
      71, // ssub_9 -> DQuadSpc_with_dsub_2_in_DPR_8
11465
11.5k
      0,  // ssub_10
11466
11.5k
      0,  // ssub_11
11467
11.5k
      0,  // ssub_12
11468
11.5k
      0,  // ssub_13
11469
11.5k
      0,  // dsub_7_then_ssub_0
11470
11.5k
      0,  // dsub_7_then_ssub_1
11471
11.5k
      71, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_2_in_DPR_8
11472
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11473
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
11474
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11475
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
11476
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11477
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11478
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11479
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11480
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11481
11.5k
      71, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_2_in_DPR_8
11482
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11483
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11484
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11485
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11486
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11487
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11488
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11489
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11490
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11491
11.5k
      0,  // dsub_5_dsub_7
11492
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11493
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11494
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11495
11.5k
    },
11496
11.5k
    { // DQuadSpc_with_dsub_4_in_DPR_8
11497
11.5k
      72, // dsub_0 -> DQuadSpc_with_dsub_4_in_DPR_8
11498
11.5k
      0,  // dsub_1
11499
11.5k
      72, // dsub_2 -> DQuadSpc_with_dsub_4_in_DPR_8
11500
11.5k
      0,  // dsub_3
11501
11.5k
      72, // dsub_4 -> DQuadSpc_with_dsub_4_in_DPR_8
11502
11.5k
      0,  // dsub_5
11503
11.5k
      0,  // dsub_6
11504
11.5k
      0,  // dsub_7
11505
11.5k
      0,  // gsub_0
11506
11.5k
      0,  // gsub_1
11507
11.5k
      0,  // qqsub_0
11508
11.5k
      0,  // qqsub_1
11509
11.5k
      0,  // qsub_0
11510
11.5k
      0,  // qsub_1
11511
11.5k
      0,  // qsub_2
11512
11.5k
      0,  // qsub_3
11513
11.5k
      72, // ssub_0 -> DQuadSpc_with_dsub_4_in_DPR_8
11514
11.5k
      72, // ssub_1 -> DQuadSpc_with_dsub_4_in_DPR_8
11515
11.5k
      0,  // ssub_2
11516
11.5k
      0,  // ssub_3
11517
11.5k
      72, // ssub_4 -> DQuadSpc_with_dsub_4_in_DPR_8
11518
11.5k
      72, // ssub_5 -> DQuadSpc_with_dsub_4_in_DPR_8
11519
11.5k
      0,  // ssub_6
11520
11.5k
      0,  // ssub_7
11521
11.5k
      72, // ssub_8 -> DQuadSpc_with_dsub_4_in_DPR_8
11522
11.5k
      72, // ssub_9 -> DQuadSpc_with_dsub_4_in_DPR_8
11523
11.5k
      0,  // ssub_10
11524
11.5k
      0,  // ssub_11
11525
11.5k
      0,  // ssub_12
11526
11.5k
      0,  // ssub_13
11527
11.5k
      0,  // dsub_7_then_ssub_0
11528
11.5k
      0,  // dsub_7_then_ssub_1
11529
11.5k
      72, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_4_in_DPR_8
11530
11.5k
      0,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11531
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7
11532
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11533
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5
11534
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11535
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11536
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11537
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11538
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11539
11.5k
      72, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_4_in_DPR_8
11540
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11541
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11542
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11543
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11544
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11545
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11546
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11547
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11548
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11549
11.5k
      0,  // dsub_5_dsub_7
11550
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11551
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11552
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11553
11.5k
    },
11554
11.5k
    { // DQuad
11555
11.5k
      73, // dsub_0 -> DQuad
11556
11.5k
      73, // dsub_1 -> DQuad
11557
11.5k
      73, // dsub_2 -> DQuad
11558
11.5k
      73, // dsub_3 -> DQuad
11559
11.5k
      0,  // dsub_4
11560
11.5k
      0,  // dsub_5
11561
11.5k
      0,  // dsub_6
11562
11.5k
      0,  // dsub_7
11563
11.5k
      0,  // gsub_0
11564
11.5k
      0,  // gsub_1
11565
11.5k
      0,  // qqsub_0
11566
11.5k
      0,  // qqsub_1
11567
11.5k
      73, // qsub_0 -> DQuad
11568
11.5k
      73, // qsub_1 -> DQuad
11569
11.5k
      0,  // qsub_2
11570
11.5k
      0,  // qsub_3
11571
11.5k
      74, // ssub_0 -> DQuad_with_ssub_0
11572
11.5k
      74, // ssub_1 -> DQuad_with_ssub_0
11573
11.5k
      75, // ssub_2 -> DQuad_with_ssub_2
11574
11.5k
      75, // ssub_3 -> DQuad_with_ssub_2
11575
11.5k
      78, // ssub_4 -> DQuad_with_ssub_4
11576
11.5k
      78, // ssub_5 -> DQuad_with_ssub_4
11577
11.5k
      79, // ssub_6 -> DQuad_with_ssub_6
11578
11.5k
      79, // ssub_7 -> DQuad_with_ssub_6
11579
11.5k
      0,  // ssub_8
11580
11.5k
      0,  // ssub_9
11581
11.5k
      0,  // ssub_10
11582
11.5k
      0,  // ssub_11
11583
11.5k
      0,  // ssub_12
11584
11.5k
      0,  // ssub_13
11585
11.5k
      0,  // dsub_7_then_ssub_0
11586
11.5k
      0,  // dsub_7_then_ssub_1
11587
11.5k
      73, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad
11588
11.5k
      73, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad
11589
11.5k
      73, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad
11590
11.5k
      73, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad
11591
11.5k
      73, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad
11592
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11593
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11594
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11595
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11596
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11597
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
11598
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11599
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11600
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11601
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11602
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11603
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11604
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11605
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11606
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11607
11.5k
      0,  // dsub_5_dsub_7
11608
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11609
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11610
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11611
11.5k
    },
11612
11.5k
    { // DQuad_with_ssub_0
11613
11.5k
      74, // dsub_0 -> DQuad_with_ssub_0
11614
11.5k
      74, // dsub_1 -> DQuad_with_ssub_0
11615
11.5k
      74, // dsub_2 -> DQuad_with_ssub_0
11616
11.5k
      74, // dsub_3 -> DQuad_with_ssub_0
11617
11.5k
      0,  // dsub_4
11618
11.5k
      0,  // dsub_5
11619
11.5k
      0,  // dsub_6
11620
11.5k
      0,  // dsub_7
11621
11.5k
      0,  // gsub_0
11622
11.5k
      0,  // gsub_1
11623
11.5k
      0,  // qqsub_0
11624
11.5k
      0,  // qqsub_1
11625
11.5k
      74, // qsub_0 -> DQuad_with_ssub_0
11626
11.5k
      74, // qsub_1 -> DQuad_with_ssub_0
11627
11.5k
      0,  // qsub_2
11628
11.5k
      0,  // qsub_3
11629
11.5k
      74, // ssub_0 -> DQuad_with_ssub_0
11630
11.5k
      74, // ssub_1 -> DQuad_with_ssub_0
11631
11.5k
      75, // ssub_2 -> DQuad_with_ssub_2
11632
11.5k
      75, // ssub_3 -> DQuad_with_ssub_2
11633
11.5k
      78, // ssub_4 -> DQuad_with_ssub_4
11634
11.5k
      78, // ssub_5 -> DQuad_with_ssub_4
11635
11.5k
      79, // ssub_6 -> DQuad_with_ssub_6
11636
11.5k
      79, // ssub_7 -> DQuad_with_ssub_6
11637
11.5k
      0,  // ssub_8
11638
11.5k
      0,  // ssub_9
11639
11.5k
      0,  // ssub_10
11640
11.5k
      0,  // ssub_11
11641
11.5k
      0,  // ssub_12
11642
11.5k
      0,  // ssub_13
11643
11.5k
      0,  // dsub_7_then_ssub_0
11644
11.5k
      0,  // dsub_7_then_ssub_1
11645
11.5k
      74, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_0
11646
11.5k
      74, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0
11647
11.5k
      74, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_0
11648
11.5k
      74, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_0
11649
11.5k
      74, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0
11650
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11651
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11652
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11653
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11654
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11655
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
11656
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11657
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11658
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11659
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11660
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11661
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11662
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11663
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11664
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11665
11.5k
      0,  // dsub_5_dsub_7
11666
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11667
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11668
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11669
11.5k
    },
11670
11.5k
    { // DQuad_with_ssub_2
11671
11.5k
      75, // dsub_0 -> DQuad_with_ssub_2
11672
11.5k
      75, // dsub_1 -> DQuad_with_ssub_2
11673
11.5k
      75, // dsub_2 -> DQuad_with_ssub_2
11674
11.5k
      75, // dsub_3 -> DQuad_with_ssub_2
11675
11.5k
      0,  // dsub_4
11676
11.5k
      0,  // dsub_5
11677
11.5k
      0,  // dsub_6
11678
11.5k
      0,  // dsub_7
11679
11.5k
      0,  // gsub_0
11680
11.5k
      0,  // gsub_1
11681
11.5k
      0,  // qqsub_0
11682
11.5k
      0,  // qqsub_1
11683
11.5k
      75, // qsub_0 -> DQuad_with_ssub_2
11684
11.5k
      75, // qsub_1 -> DQuad_with_ssub_2
11685
11.5k
      0,  // qsub_2
11686
11.5k
      0,  // qsub_3
11687
11.5k
      75, // ssub_0 -> DQuad_with_ssub_2
11688
11.5k
      75, // ssub_1 -> DQuad_with_ssub_2
11689
11.5k
      75, // ssub_2 -> DQuad_with_ssub_2
11690
11.5k
      75, // ssub_3 -> DQuad_with_ssub_2
11691
11.5k
      78, // ssub_4 -> DQuad_with_ssub_4
11692
11.5k
      78, // ssub_5 -> DQuad_with_ssub_4
11693
11.5k
      79, // ssub_6 -> DQuad_with_ssub_6
11694
11.5k
      79, // ssub_7 -> DQuad_with_ssub_6
11695
11.5k
      0,  // ssub_8
11696
11.5k
      0,  // ssub_9
11697
11.5k
      0,  // ssub_10
11698
11.5k
      0,  // ssub_11
11699
11.5k
      0,  // ssub_12
11700
11.5k
      0,  // ssub_13
11701
11.5k
      0,  // dsub_7_then_ssub_0
11702
11.5k
      0,  // dsub_7_then_ssub_1
11703
11.5k
      75, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2
11704
11.5k
      75, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2
11705
11.5k
      75, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2
11706
11.5k
      75, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2
11707
11.5k
      75, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2
11708
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11709
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11710
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11711
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11712
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11713
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
11714
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11715
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11716
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11717
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11718
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11719
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11720
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11721
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11722
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11723
11.5k
      0,  // dsub_5_dsub_7
11724
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11725
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11726
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11727
11.5k
    },
11728
11.5k
    { // QQPR
11729
11.5k
      76, // dsub_0 -> QQPR
11730
11.5k
      76, // dsub_1 -> QQPR
11731
11.5k
      76, // dsub_2 -> QQPR
11732
11.5k
      76, // dsub_3 -> QQPR
11733
11.5k
      0,  // dsub_4
11734
11.5k
      0,  // dsub_5
11735
11.5k
      0,  // dsub_6
11736
11.5k
      0,  // dsub_7
11737
11.5k
      0,  // gsub_0
11738
11.5k
      0,  // gsub_1
11739
11.5k
      0,  // qqsub_0
11740
11.5k
      0,  // qqsub_1
11741
11.5k
      76, // qsub_0 -> QQPR
11742
11.5k
      76, // qsub_1 -> QQPR
11743
11.5k
      0,  // qsub_2
11744
11.5k
      0,  // qsub_3
11745
11.5k
      81, // ssub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
11746
11.5k
      81, // ssub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
11747
11.5k
      81, // ssub_2 -> DQuad_with_qsub_0_in_QPR_VFP2
11748
11.5k
      81, // ssub_3 -> DQuad_with_qsub_0_in_QPR_VFP2
11749
11.5k
      84, // ssub_4 -> DQuad_with_qsub_1_in_QPR_VFP2
11750
11.5k
      84, // ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
11751
11.5k
      84, // ssub_6 -> DQuad_with_qsub_1_in_QPR_VFP2
11752
11.5k
      84, // ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
11753
11.5k
      0,  // ssub_8
11754
11.5k
      0,  // ssub_9
11755
11.5k
      0,  // ssub_10
11756
11.5k
      0,  // ssub_11
11757
11.5k
      0,  // ssub_12
11758
11.5k
      0,  // ssub_13
11759
11.5k
      0,  // dsub_7_then_ssub_0
11760
11.5k
      0,  // dsub_7_then_ssub_1
11761
11.5k
      76, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQPR
11762
11.5k
      76, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQPR
11763
11.5k
      76, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQPR
11764
11.5k
      76, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQPR
11765
11.5k
      76, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQPR
11766
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11767
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11768
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11769
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11770
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11771
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
11772
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11773
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11774
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11775
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11776
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11777
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11778
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11779
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11780
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11781
11.5k
      0,  // dsub_5_dsub_7
11782
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11783
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11784
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11785
11.5k
    },
11786
11.5k
    { // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11787
11.5k
      77, // dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11788
11.5k
      77, // dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11789
11.5k
      77, // dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11790
11.5k
      77, // dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11791
11.5k
      0,  // dsub_4
11792
11.5k
      0,  // dsub_5
11793
11.5k
      0,  // dsub_6
11794
11.5k
      0,  // dsub_7
11795
11.5k
      0,  // gsub_0
11796
11.5k
      0,  // gsub_1
11797
11.5k
      0,  // qqsub_0
11798
11.5k
      0,  // qqsub_1
11799
11.5k
      77, // qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11800
11.5k
      77, // qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11801
11.5k
      0,  // qsub_2
11802
11.5k
      0,  // qsub_3
11803
11.5k
      82, // ssub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11804
11.5k
      82, // ssub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11805
11.5k
      85, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
11806
11.5k
      85, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
11807
11.5k
      85, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
11808
11.5k
      85, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
11809
11.5k
      87, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11810
11.5k
      87, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11811
11.5k
      0,  // ssub_8
11812
11.5k
      0,  // ssub_9
11813
11.5k
      0,  // ssub_10
11814
11.5k
      0,  // ssub_11
11815
11.5k
      0,  // ssub_12
11816
11.5k
      0,  // ssub_13
11817
11.5k
      0,  // dsub_7_then_ssub_0
11818
11.5k
      0,  // dsub_7_then_ssub_1
11819
11.5k
      77, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11820
11.5k
      77, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11821
11.5k
      77, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11822
11.5k
      77, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11823
11.5k
      77, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11824
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11825
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11826
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11827
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11828
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11829
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
11830
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11831
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11832
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11833
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11834
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11835
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11836
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11837
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11838
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11839
11.5k
      0,  // dsub_5_dsub_7
11840
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11841
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11842
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11843
11.5k
    },
11844
11.5k
    { // DQuad_with_ssub_4
11845
11.5k
      78, // dsub_0 -> DQuad_with_ssub_4
11846
11.5k
      78, // dsub_1 -> DQuad_with_ssub_4
11847
11.5k
      78, // dsub_2 -> DQuad_with_ssub_4
11848
11.5k
      78, // dsub_3 -> DQuad_with_ssub_4
11849
11.5k
      0,  // dsub_4
11850
11.5k
      0,  // dsub_5
11851
11.5k
      0,  // dsub_6
11852
11.5k
      0,  // dsub_7
11853
11.5k
      0,  // gsub_0
11854
11.5k
      0,  // gsub_1
11855
11.5k
      0,  // qqsub_0
11856
11.5k
      0,  // qqsub_1
11857
11.5k
      78, // qsub_0 -> DQuad_with_ssub_4
11858
11.5k
      78, // qsub_1 -> DQuad_with_ssub_4
11859
11.5k
      0,  // qsub_2
11860
11.5k
      0,  // qsub_3
11861
11.5k
      78, // ssub_0 -> DQuad_with_ssub_4
11862
11.5k
      78, // ssub_1 -> DQuad_with_ssub_4
11863
11.5k
      78, // ssub_2 -> DQuad_with_ssub_4
11864
11.5k
      78, // ssub_3 -> DQuad_with_ssub_4
11865
11.5k
      78, // ssub_4 -> DQuad_with_ssub_4
11866
11.5k
      78, // ssub_5 -> DQuad_with_ssub_4
11867
11.5k
      79, // ssub_6 -> DQuad_with_ssub_6
11868
11.5k
      79, // ssub_7 -> DQuad_with_ssub_6
11869
11.5k
      0,  // ssub_8
11870
11.5k
      0,  // ssub_9
11871
11.5k
      0,  // ssub_10
11872
11.5k
      0,  // ssub_11
11873
11.5k
      0,  // ssub_12
11874
11.5k
      0,  // ssub_13
11875
11.5k
      0,  // dsub_7_then_ssub_0
11876
11.5k
      0,  // dsub_7_then_ssub_1
11877
11.5k
      78, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_4
11878
11.5k
      78, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_4
11879
11.5k
      78, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_4
11880
11.5k
      78, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_4
11881
11.5k
      78, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_4
11882
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11883
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11884
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11885
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11886
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11887
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
11888
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11889
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11890
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11891
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11892
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11893
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11894
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11895
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11896
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11897
11.5k
      0,  // dsub_5_dsub_7
11898
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11899
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11900
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11901
11.5k
    },
11902
11.5k
    { // DQuad_with_ssub_6
11903
11.5k
      79, // dsub_0 -> DQuad_with_ssub_6
11904
11.5k
      79, // dsub_1 -> DQuad_with_ssub_6
11905
11.5k
      79, // dsub_2 -> DQuad_with_ssub_6
11906
11.5k
      79, // dsub_3 -> DQuad_with_ssub_6
11907
11.5k
      0,  // dsub_4
11908
11.5k
      0,  // dsub_5
11909
11.5k
      0,  // dsub_6
11910
11.5k
      0,  // dsub_7
11911
11.5k
      0,  // gsub_0
11912
11.5k
      0,  // gsub_1
11913
11.5k
      0,  // qqsub_0
11914
11.5k
      0,  // qqsub_1
11915
11.5k
      79, // qsub_0 -> DQuad_with_ssub_6
11916
11.5k
      79, // qsub_1 -> DQuad_with_ssub_6
11917
11.5k
      0,  // qsub_2
11918
11.5k
      0,  // qsub_3
11919
11.5k
      79, // ssub_0 -> DQuad_with_ssub_6
11920
11.5k
      79, // ssub_1 -> DQuad_with_ssub_6
11921
11.5k
      79, // ssub_2 -> DQuad_with_ssub_6
11922
11.5k
      79, // ssub_3 -> DQuad_with_ssub_6
11923
11.5k
      79, // ssub_4 -> DQuad_with_ssub_6
11924
11.5k
      79, // ssub_5 -> DQuad_with_ssub_6
11925
11.5k
      79, // ssub_6 -> DQuad_with_ssub_6
11926
11.5k
      79, // ssub_7 -> DQuad_with_ssub_6
11927
11.5k
      0,  // ssub_8
11928
11.5k
      0,  // ssub_9
11929
11.5k
      0,  // ssub_10
11930
11.5k
      0,  // ssub_11
11931
11.5k
      0,  // ssub_12
11932
11.5k
      0,  // ssub_13
11933
11.5k
      0,  // dsub_7_then_ssub_0
11934
11.5k
      0,  // dsub_7_then_ssub_1
11935
11.5k
      79, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_6
11936
11.5k
      79, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6
11937
11.5k
      79, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_6
11938
11.5k
      79, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_6
11939
11.5k
      79, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6
11940
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11941
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11942
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11943
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11944
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11945
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
11946
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11947
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11948
11.5k
      0,  // ssub_6_ssub_7_dsub_5
11949
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11950
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
11951
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
11952
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11953
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
11954
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11955
11.5k
      0,  // dsub_5_dsub_7
11956
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
11957
11.5k
      0,  // dsub_5_ssub_12_ssub_13
11958
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11959
11.5k
    },
11960
11.5k
    { // DQuad_with_dsub_0_in_DPR_8
11961
11.5k
      80, // dsub_0 -> DQuad_with_dsub_0_in_DPR_8
11962
11.5k
      80, // dsub_1 -> DQuad_with_dsub_0_in_DPR_8
11963
11.5k
      80, // dsub_2 -> DQuad_with_dsub_0_in_DPR_8
11964
11.5k
      80, // dsub_3 -> DQuad_with_dsub_0_in_DPR_8
11965
11.5k
      0,  // dsub_4
11966
11.5k
      0,  // dsub_5
11967
11.5k
      0,  // dsub_6
11968
11.5k
      0,  // dsub_7
11969
11.5k
      0,  // gsub_0
11970
11.5k
      0,  // gsub_1
11971
11.5k
      0,  // qqsub_0
11972
11.5k
      0,  // qqsub_1
11973
11.5k
      80, // qsub_0 -> DQuad_with_dsub_0_in_DPR_8
11974
11.5k
      80, // qsub_1 -> DQuad_with_dsub_0_in_DPR_8
11975
11.5k
      0,  // qsub_2
11976
11.5k
      0,  // qsub_3
11977
11.5k
      80, // ssub_0 -> DQuad_with_dsub_0_in_DPR_8
11978
11.5k
      80, // ssub_1 -> DQuad_with_dsub_0_in_DPR_8
11979
11.5k
      80, // ssub_2 -> DQuad_with_dsub_0_in_DPR_8
11980
11.5k
      80, // ssub_3 -> DQuad_with_dsub_0_in_DPR_8
11981
11.5k
      80, // ssub_4 -> DQuad_with_dsub_0_in_DPR_8
11982
11.5k
      80, // ssub_5 -> DQuad_with_dsub_0_in_DPR_8
11983
11.5k
      80, // ssub_6 -> DQuad_with_dsub_0_in_DPR_8
11984
11.5k
      80, // ssub_7 -> DQuad_with_dsub_0_in_DPR_8
11985
11.5k
      0,  // ssub_8
11986
11.5k
      0,  // ssub_9
11987
11.5k
      0,  // ssub_10
11988
11.5k
      0,  // ssub_11
11989
11.5k
      0,  // ssub_12
11990
11.5k
      0,  // ssub_13
11991
11.5k
      0,  // dsub_7_then_ssub_0
11992
11.5k
      0,  // dsub_7_then_ssub_1
11993
11.5k
      80, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8
11994
11.5k
      80, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8
11995
11.5k
      80, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8
11996
11.5k
      80, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8
11997
11.5k
      80, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8
11998
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11999
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12000
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12001
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12002
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12003
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12004
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12005
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12006
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12007
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12008
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12009
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12010
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12011
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12012
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12013
11.5k
      0,  // dsub_5_dsub_7
12014
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12015
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12016
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12017
11.5k
    },
12018
11.5k
    { // DQuad_with_qsub_0_in_QPR_VFP2
12019
11.5k
      81, // dsub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
12020
11.5k
      81, // dsub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
12021
11.5k
      81, // dsub_2 -> DQuad_with_qsub_0_in_QPR_VFP2
12022
11.5k
      81, // dsub_3 -> DQuad_with_qsub_0_in_QPR_VFP2
12023
11.5k
      0,  // dsub_4
12024
11.5k
      0,  // dsub_5
12025
11.5k
      0,  // dsub_6
12026
11.5k
      0,  // dsub_7
12027
11.5k
      0,  // gsub_0
12028
11.5k
      0,  // gsub_1
12029
11.5k
      0,  // qqsub_0
12030
11.5k
      0,  // qqsub_1
12031
11.5k
      81, // qsub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
12032
11.5k
      81, // qsub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
12033
11.5k
      0,  // qsub_2
12034
11.5k
      0,  // qsub_3
12035
11.5k
      81, // ssub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
12036
11.5k
      81, // ssub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
12037
11.5k
      81, // ssub_2 -> DQuad_with_qsub_0_in_QPR_VFP2
12038
11.5k
      81, // ssub_3 -> DQuad_with_qsub_0_in_QPR_VFP2
12039
11.5k
      84, // ssub_4 -> DQuad_with_qsub_1_in_QPR_VFP2
12040
11.5k
      84, // ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
12041
11.5k
      84, // ssub_6 -> DQuad_with_qsub_1_in_QPR_VFP2
12042
11.5k
      84, // ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
12043
11.5k
      0,  // ssub_8
12044
11.5k
      0,  // ssub_9
12045
11.5k
      0,  // ssub_10
12046
11.5k
      0,  // ssub_11
12047
11.5k
      0,  // ssub_12
12048
11.5k
      0,  // ssub_13
12049
11.5k
      0,  // dsub_7_then_ssub_0
12050
11.5k
      0,  // dsub_7_then_ssub_1
12051
11.5k
      81, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_VFP2
12052
11.5k
      81, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_VFP2
12053
11.5k
      81, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_VFP2
12054
11.5k
      81, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_VFP2
12055
11.5k
      81, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_VFP2
12056
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12057
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12058
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12059
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12060
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12061
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12062
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12063
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12064
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12065
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12066
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12067
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12068
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12069
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12070
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12071
11.5k
      0,  // dsub_5_dsub_7
12072
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12073
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12074
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12075
11.5k
    },
12076
11.5k
    { // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12077
11.5k
      82, // dsub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12078
11.5k
      82, // dsub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12079
11.5k
      82, // dsub_2 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12080
11.5k
      82, // dsub_3 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12081
11.5k
      0,  // dsub_4
12082
11.5k
      0,  // dsub_5
12083
11.5k
      0,  // dsub_6
12084
11.5k
      0,  // dsub_7
12085
11.5k
      0,  // gsub_0
12086
11.5k
      0,  // gsub_1
12087
11.5k
      0,  // qqsub_0
12088
11.5k
      0,  // qqsub_1
12089
11.5k
      82, // qsub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12090
11.5k
      82, // qsub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12091
11.5k
      0,  // qsub_2
12092
11.5k
      0,  // qsub_3
12093
11.5k
      82, // ssub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12094
11.5k
      82, // ssub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12095
11.5k
      85, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12096
11.5k
      85, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12097
11.5k
      85, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12098
11.5k
      85, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12099
11.5k
      87, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12100
11.5k
      87, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12101
11.5k
      0,  // ssub_8
12102
11.5k
      0,  // ssub_9
12103
11.5k
      0,  // ssub_10
12104
11.5k
      0,  // ssub_11
12105
11.5k
      0,  // ssub_12
12106
11.5k
      0,  // ssub_13
12107
11.5k
      0,  // dsub_7_then_ssub_0
12108
11.5k
      0,  // dsub_7_then_ssub_1
12109
11.5k
      82, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12110
11.5k
      82, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12111
11.5k
      82, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12112
11.5k
      82, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12113
11.5k
      82, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12114
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12115
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12116
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12117
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12118
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12119
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12120
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12121
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12122
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12123
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12124
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12125
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12126
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12127
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12128
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12129
11.5k
      0,  // dsub_5_dsub_7
12130
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12131
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12132
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12133
11.5k
    },
12134
11.5k
    { // DQuad_with_dsub_1_in_DPR_8
12135
11.5k
      83, // dsub_0 -> DQuad_with_dsub_1_in_DPR_8
12136
11.5k
      83, // dsub_1 -> DQuad_with_dsub_1_in_DPR_8
12137
11.5k
      83, // dsub_2 -> DQuad_with_dsub_1_in_DPR_8
12138
11.5k
      83, // dsub_3 -> DQuad_with_dsub_1_in_DPR_8
12139
11.5k
      0,  // dsub_4
12140
11.5k
      0,  // dsub_5
12141
11.5k
      0,  // dsub_6
12142
11.5k
      0,  // dsub_7
12143
11.5k
      0,  // gsub_0
12144
11.5k
      0,  // gsub_1
12145
11.5k
      0,  // qqsub_0
12146
11.5k
      0,  // qqsub_1
12147
11.5k
      83, // qsub_0 -> DQuad_with_dsub_1_in_DPR_8
12148
11.5k
      83, // qsub_1 -> DQuad_with_dsub_1_in_DPR_8
12149
11.5k
      0,  // qsub_2
12150
11.5k
      0,  // qsub_3
12151
11.5k
      83, // ssub_0 -> DQuad_with_dsub_1_in_DPR_8
12152
11.5k
      83, // ssub_1 -> DQuad_with_dsub_1_in_DPR_8
12153
11.5k
      83, // ssub_2 -> DQuad_with_dsub_1_in_DPR_8
12154
11.5k
      83, // ssub_3 -> DQuad_with_dsub_1_in_DPR_8
12155
11.5k
      83, // ssub_4 -> DQuad_with_dsub_1_in_DPR_8
12156
11.5k
      83, // ssub_5 -> DQuad_with_dsub_1_in_DPR_8
12157
11.5k
      83, // ssub_6 -> DQuad_with_dsub_1_in_DPR_8
12158
11.5k
      83, // ssub_7 -> DQuad_with_dsub_1_in_DPR_8
12159
11.5k
      0,  // ssub_8
12160
11.5k
      0,  // ssub_9
12161
11.5k
      0,  // ssub_10
12162
11.5k
      0,  // ssub_11
12163
11.5k
      0,  // ssub_12
12164
11.5k
      0,  // ssub_13
12165
11.5k
      0,  // dsub_7_then_ssub_0
12166
11.5k
      0,  // dsub_7_then_ssub_1
12167
11.5k
      83, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8
12168
11.5k
      83, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8
12169
11.5k
      83, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_1_in_DPR_8
12170
11.5k
      83, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_1_in_DPR_8
12171
11.5k
      83, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8
12172
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12173
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12174
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12175
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12176
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12177
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12178
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12179
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12180
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12181
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12182
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12183
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12184
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12185
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12186
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12187
11.5k
      0,  // dsub_5_dsub_7
12188
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12189
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12190
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12191
11.5k
    },
12192
11.5k
    { // DQuad_with_qsub_1_in_QPR_VFP2
12193
11.5k
      84, // dsub_0 -> DQuad_with_qsub_1_in_QPR_VFP2
12194
11.5k
      84, // dsub_1 -> DQuad_with_qsub_1_in_QPR_VFP2
12195
11.5k
      84, // dsub_2 -> DQuad_with_qsub_1_in_QPR_VFP2
12196
11.5k
      84, // dsub_3 -> DQuad_with_qsub_1_in_QPR_VFP2
12197
11.5k
      0,  // dsub_4
12198
11.5k
      0,  // dsub_5
12199
11.5k
      0,  // dsub_6
12200
11.5k
      0,  // dsub_7
12201
11.5k
      0,  // gsub_0
12202
11.5k
      0,  // gsub_1
12203
11.5k
      0,  // qqsub_0
12204
11.5k
      0,  // qqsub_1
12205
11.5k
      84, // qsub_0 -> DQuad_with_qsub_1_in_QPR_VFP2
12206
11.5k
      84, // qsub_1 -> DQuad_with_qsub_1_in_QPR_VFP2
12207
11.5k
      0,  // qsub_2
12208
11.5k
      0,  // qsub_3
12209
11.5k
      84, // ssub_0 -> DQuad_with_qsub_1_in_QPR_VFP2
12210
11.5k
      84, // ssub_1 -> DQuad_with_qsub_1_in_QPR_VFP2
12211
11.5k
      84, // ssub_2 -> DQuad_with_qsub_1_in_QPR_VFP2
12212
11.5k
      84, // ssub_3 -> DQuad_with_qsub_1_in_QPR_VFP2
12213
11.5k
      84, // ssub_4 -> DQuad_with_qsub_1_in_QPR_VFP2
12214
11.5k
      84, // ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
12215
11.5k
      84, // ssub_6 -> DQuad_with_qsub_1_in_QPR_VFP2
12216
11.5k
      84, // ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
12217
11.5k
      0,  // ssub_8
12218
11.5k
      0,  // ssub_9
12219
11.5k
      0,  // ssub_10
12220
11.5k
      0,  // ssub_11
12221
11.5k
      0,  // ssub_12
12222
11.5k
      0,  // ssub_13
12223
11.5k
      0,  // dsub_7_then_ssub_0
12224
11.5k
      0,  // dsub_7_then_ssub_1
12225
11.5k
      84, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
12226
11.5k
      84, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
12227
11.5k
      84, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
12228
11.5k
      84, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
12229
11.5k
      84, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
12230
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12231
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12232
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12233
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12234
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12235
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12236
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12237
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12238
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12239
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12240
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12241
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12242
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12243
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12244
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12245
11.5k
      0,  // dsub_5_dsub_7
12246
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12247
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12248
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12249
11.5k
    },
12250
11.5k
    { // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12251
11.5k
      85, // dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12252
11.5k
      85, // dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12253
11.5k
      85, // dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12254
11.5k
      85, // dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12255
11.5k
      0,  // dsub_4
12256
11.5k
      0,  // dsub_5
12257
11.5k
      0,  // dsub_6
12258
11.5k
      0,  // dsub_7
12259
11.5k
      0,  // gsub_0
12260
11.5k
      0,  // gsub_1
12261
11.5k
      0,  // qqsub_0
12262
11.5k
      0,  // qqsub_1
12263
11.5k
      85, // qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12264
11.5k
      85, // qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12265
11.5k
      0,  // qsub_2
12266
11.5k
      0,  // qsub_3
12267
11.5k
      85, // ssub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12268
11.5k
      85, // ssub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12269
11.5k
      85, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12270
11.5k
      85, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12271
11.5k
      85, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12272
11.5k
      85, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12273
11.5k
      87, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12274
11.5k
      87, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12275
11.5k
      0,  // ssub_8
12276
11.5k
      0,  // ssub_9
12277
11.5k
      0,  // ssub_10
12278
11.5k
      0,  // ssub_11
12279
11.5k
      0,  // ssub_12
12280
11.5k
      0,  // ssub_13
12281
11.5k
      0,  // dsub_7_then_ssub_0
12282
11.5k
      0,  // dsub_7_then_ssub_1
12283
11.5k
      85, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12284
11.5k
      85, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12285
11.5k
      85, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12286
11.5k
      85, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12287
11.5k
      85, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12288
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12289
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12290
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12291
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12292
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12293
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12294
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12295
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12296
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12297
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12298
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12299
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12300
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12301
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12302
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12303
11.5k
      0,  // dsub_5_dsub_7
12304
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12305
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12306
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12307
11.5k
    },
12308
11.5k
    { // DQuad_with_dsub_2_in_DPR_8
12309
11.5k
      86, // dsub_0 -> DQuad_with_dsub_2_in_DPR_8
12310
11.5k
      86, // dsub_1 -> DQuad_with_dsub_2_in_DPR_8
12311
11.5k
      86, // dsub_2 -> DQuad_with_dsub_2_in_DPR_8
12312
11.5k
      86, // dsub_3 -> DQuad_with_dsub_2_in_DPR_8
12313
11.5k
      0,  // dsub_4
12314
11.5k
      0,  // dsub_5
12315
11.5k
      0,  // dsub_6
12316
11.5k
      0,  // dsub_7
12317
11.5k
      0,  // gsub_0
12318
11.5k
      0,  // gsub_1
12319
11.5k
      0,  // qqsub_0
12320
11.5k
      0,  // qqsub_1
12321
11.5k
      86, // qsub_0 -> DQuad_with_dsub_2_in_DPR_8
12322
11.5k
      86, // qsub_1 -> DQuad_with_dsub_2_in_DPR_8
12323
11.5k
      0,  // qsub_2
12324
11.5k
      0,  // qsub_3
12325
11.5k
      86, // ssub_0 -> DQuad_with_dsub_2_in_DPR_8
12326
11.5k
      86, // ssub_1 -> DQuad_with_dsub_2_in_DPR_8
12327
11.5k
      86, // ssub_2 -> DQuad_with_dsub_2_in_DPR_8
12328
11.5k
      86, // ssub_3 -> DQuad_with_dsub_2_in_DPR_8
12329
11.5k
      86, // ssub_4 -> DQuad_with_dsub_2_in_DPR_8
12330
11.5k
      86, // ssub_5 -> DQuad_with_dsub_2_in_DPR_8
12331
11.5k
      86, // ssub_6 -> DQuad_with_dsub_2_in_DPR_8
12332
11.5k
      86, // ssub_7 -> DQuad_with_dsub_2_in_DPR_8
12333
11.5k
      0,  // ssub_8
12334
11.5k
      0,  // ssub_9
12335
11.5k
      0,  // ssub_10
12336
11.5k
      0,  // ssub_11
12337
11.5k
      0,  // ssub_12
12338
11.5k
      0,  // ssub_13
12339
11.5k
      0,  // dsub_7_then_ssub_0
12340
11.5k
      0,  // dsub_7_then_ssub_1
12341
11.5k
      86, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8
12342
11.5k
      86, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8
12343
11.5k
      86, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_2_in_DPR_8
12344
11.5k
      86, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_2_in_DPR_8
12345
11.5k
      86, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8
12346
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12347
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12348
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12349
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12350
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12351
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12352
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12353
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12354
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12355
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12356
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12357
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12358
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12359
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12360
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12361
11.5k
      0,  // dsub_5_dsub_7
12362
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12363
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12364
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12365
11.5k
    },
12366
11.5k
    { // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12367
11.5k
      87, // dsub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12368
11.5k
      87, // dsub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12369
11.5k
      87, // dsub_2 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12370
11.5k
      87, // dsub_3 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12371
11.5k
      0,  // dsub_4
12372
11.5k
      0,  // dsub_5
12373
11.5k
      0,  // dsub_6
12374
11.5k
      0,  // dsub_7
12375
11.5k
      0,  // gsub_0
12376
11.5k
      0,  // gsub_1
12377
11.5k
      0,  // qqsub_0
12378
11.5k
      0,  // qqsub_1
12379
11.5k
      87, // qsub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12380
11.5k
      87, // qsub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12381
11.5k
      0,  // qsub_2
12382
11.5k
      0,  // qsub_3
12383
11.5k
      87, // ssub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12384
11.5k
      87, // ssub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12385
11.5k
      87, // ssub_2 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12386
11.5k
      87, // ssub_3 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12387
11.5k
      87, // ssub_4 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12388
11.5k
      87, // ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12389
11.5k
      87, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12390
11.5k
      87, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12391
11.5k
      0,  // ssub_8
12392
11.5k
      0,  // ssub_9
12393
11.5k
      0,  // ssub_10
12394
11.5k
      0,  // ssub_11
12395
11.5k
      0,  // ssub_12
12396
11.5k
      0,  // ssub_13
12397
11.5k
      0,  // dsub_7_then_ssub_0
12398
11.5k
      0,  // dsub_7_then_ssub_1
12399
11.5k
      87, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12400
11.5k
      87, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12401
11.5k
      87, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12402
11.5k
      87, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12403
11.5k
      87, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12404
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12405
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12406
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12407
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12408
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12409
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12410
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12411
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12412
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12413
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12414
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12415
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12416
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12417
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12418
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12419
11.5k
      0,  // dsub_5_dsub_7
12420
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12421
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12422
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12423
11.5k
    },
12424
11.5k
    { // DQuad_with_dsub_3_in_DPR_8
12425
11.5k
      88, // dsub_0 -> DQuad_with_dsub_3_in_DPR_8
12426
11.5k
      88, // dsub_1 -> DQuad_with_dsub_3_in_DPR_8
12427
11.5k
      88, // dsub_2 -> DQuad_with_dsub_3_in_DPR_8
12428
11.5k
      88, // dsub_3 -> DQuad_with_dsub_3_in_DPR_8
12429
11.5k
      0,  // dsub_4
12430
11.5k
      0,  // dsub_5
12431
11.5k
      0,  // dsub_6
12432
11.5k
      0,  // dsub_7
12433
11.5k
      0,  // gsub_0
12434
11.5k
      0,  // gsub_1
12435
11.5k
      0,  // qqsub_0
12436
11.5k
      0,  // qqsub_1
12437
11.5k
      88, // qsub_0 -> DQuad_with_dsub_3_in_DPR_8
12438
11.5k
      88, // qsub_1 -> DQuad_with_dsub_3_in_DPR_8
12439
11.5k
      0,  // qsub_2
12440
11.5k
      0,  // qsub_3
12441
11.5k
      88, // ssub_0 -> DQuad_with_dsub_3_in_DPR_8
12442
11.5k
      88, // ssub_1 -> DQuad_with_dsub_3_in_DPR_8
12443
11.5k
      88, // ssub_2 -> DQuad_with_dsub_3_in_DPR_8
12444
11.5k
      88, // ssub_3 -> DQuad_with_dsub_3_in_DPR_8
12445
11.5k
      88, // ssub_4 -> DQuad_with_dsub_3_in_DPR_8
12446
11.5k
      88, // ssub_5 -> DQuad_with_dsub_3_in_DPR_8
12447
11.5k
      88, // ssub_6 -> DQuad_with_dsub_3_in_DPR_8
12448
11.5k
      88, // ssub_7 -> DQuad_with_dsub_3_in_DPR_8
12449
11.5k
      0,  // ssub_8
12450
11.5k
      0,  // ssub_9
12451
11.5k
      0,  // ssub_10
12452
11.5k
      0,  // ssub_11
12453
11.5k
      0,  // ssub_12
12454
11.5k
      0,  // ssub_13
12455
11.5k
      0,  // dsub_7_then_ssub_0
12456
11.5k
      0,  // dsub_7_then_ssub_1
12457
11.5k
      88, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8
12458
11.5k
      88, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8
12459
11.5k
      88, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8
12460
11.5k
      88, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8
12461
11.5k
      88, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8
12462
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12463
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12464
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12465
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12466
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12467
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12468
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12469
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12470
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12471
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12472
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12473
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12474
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12475
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12476
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12477
11.5k
      0,  // dsub_5_dsub_7
12478
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12479
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12480
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12481
11.5k
    },
12482
11.5k
    { // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12483
11.5k
      89, // dsub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12484
11.5k
      89, // dsub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12485
11.5k
      89, // dsub_2 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12486
11.5k
      89, // dsub_3 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12487
11.5k
      0,  // dsub_4
12488
11.5k
      0,  // dsub_5
12489
11.5k
      0,  // dsub_6
12490
11.5k
      0,  // dsub_7
12491
11.5k
      0,  // gsub_0
12492
11.5k
      0,  // gsub_1
12493
11.5k
      0,  // qqsub_0
12494
11.5k
      0,  // qqsub_1
12495
11.5k
      89, // qsub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12496
11.5k
      89, // qsub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12497
11.5k
      0,  // qsub_2
12498
11.5k
      0,  // qsub_3
12499
11.5k
      89, // ssub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12500
11.5k
      89, // ssub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12501
11.5k
      89, // ssub_2 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12502
11.5k
      89, // ssub_3 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12503
11.5k
      89, // ssub_4 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12504
11.5k
      89, // ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12505
11.5k
      89, // ssub_6 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12506
11.5k
      89, // ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12507
11.5k
      0,  // ssub_8
12508
11.5k
      0,  // ssub_9
12509
11.5k
      0,  // ssub_10
12510
11.5k
      0,  // ssub_11
12511
11.5k
      0,  // ssub_12
12512
11.5k
      0,  // ssub_13
12513
11.5k
      0,  // dsub_7_then_ssub_0
12514
11.5k
      0,  // dsub_7_then_ssub_1
12515
11.5k
      89, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12516
11.5k
      89, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12517
11.5k
      89, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12518
11.5k
      89, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12519
11.5k
      89, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12520
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12521
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12522
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12523
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12524
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12525
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12526
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12527
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12528
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12529
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12530
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12531
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12532
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12533
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12534
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12535
11.5k
      0,  // dsub_5_dsub_7
12536
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12537
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12538
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12539
11.5k
    },
12540
11.5k
    { // DQuad_with_qsub_0_in_QPR_8
12541
11.5k
      90, // dsub_0 -> DQuad_with_qsub_0_in_QPR_8
12542
11.5k
      90, // dsub_1 -> DQuad_with_qsub_0_in_QPR_8
12543
11.5k
      90, // dsub_2 -> DQuad_with_qsub_0_in_QPR_8
12544
11.5k
      90, // dsub_3 -> DQuad_with_qsub_0_in_QPR_8
12545
11.5k
      0,  // dsub_4
12546
11.5k
      0,  // dsub_5
12547
11.5k
      0,  // dsub_6
12548
11.5k
      0,  // dsub_7
12549
11.5k
      0,  // gsub_0
12550
11.5k
      0,  // gsub_1
12551
11.5k
      0,  // qqsub_0
12552
11.5k
      0,  // qqsub_1
12553
11.5k
      90, // qsub_0 -> DQuad_with_qsub_0_in_QPR_8
12554
11.5k
      90, // qsub_1 -> DQuad_with_qsub_0_in_QPR_8
12555
11.5k
      0,  // qsub_2
12556
11.5k
      0,  // qsub_3
12557
11.5k
      90, // ssub_0 -> DQuad_with_qsub_0_in_QPR_8
12558
11.5k
      90, // ssub_1 -> DQuad_with_qsub_0_in_QPR_8
12559
11.5k
      90, // ssub_2 -> DQuad_with_qsub_0_in_QPR_8
12560
11.5k
      90, // ssub_3 -> DQuad_with_qsub_0_in_QPR_8
12561
11.5k
      90, // ssub_4 -> DQuad_with_qsub_0_in_QPR_8
12562
11.5k
      90, // ssub_5 -> DQuad_with_qsub_0_in_QPR_8
12563
11.5k
      90, // ssub_6 -> DQuad_with_qsub_0_in_QPR_8
12564
11.5k
      90, // ssub_7 -> DQuad_with_qsub_0_in_QPR_8
12565
11.5k
      0,  // ssub_8
12566
11.5k
      0,  // ssub_9
12567
11.5k
      0,  // ssub_10
12568
11.5k
      0,  // ssub_11
12569
11.5k
      0,  // ssub_12
12570
11.5k
      0,  // ssub_13
12571
11.5k
      0,  // dsub_7_then_ssub_0
12572
11.5k
      0,  // dsub_7_then_ssub_1
12573
11.5k
      90, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8
12574
11.5k
      90, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8
12575
11.5k
      90, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_8
12576
11.5k
      90, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_8
12577
11.5k
      90, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8
12578
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12579
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12580
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12581
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12582
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12583
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12584
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12585
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12586
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12587
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12588
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12589
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12590
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12591
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12592
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12593
11.5k
      0,  // dsub_5_dsub_7
12594
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12595
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12596
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12597
11.5k
    },
12598
11.5k
    { // DQuad_with_qsub_1_in_QPR_8
12599
11.5k
      91, // dsub_0 -> DQuad_with_qsub_1_in_QPR_8
12600
11.5k
      91, // dsub_1 -> DQuad_with_qsub_1_in_QPR_8
12601
11.5k
      91, // dsub_2 -> DQuad_with_qsub_1_in_QPR_8
12602
11.5k
      91, // dsub_3 -> DQuad_with_qsub_1_in_QPR_8
12603
11.5k
      0,  // dsub_4
12604
11.5k
      0,  // dsub_5
12605
11.5k
      0,  // dsub_6
12606
11.5k
      0,  // dsub_7
12607
11.5k
      0,  // gsub_0
12608
11.5k
      0,  // gsub_1
12609
11.5k
      0,  // qqsub_0
12610
11.5k
      0,  // qqsub_1
12611
11.5k
      91, // qsub_0 -> DQuad_with_qsub_1_in_QPR_8
12612
11.5k
      91, // qsub_1 -> DQuad_with_qsub_1_in_QPR_8
12613
11.5k
      0,  // qsub_2
12614
11.5k
      0,  // qsub_3
12615
11.5k
      91, // ssub_0 -> DQuad_with_qsub_1_in_QPR_8
12616
11.5k
      91, // ssub_1 -> DQuad_with_qsub_1_in_QPR_8
12617
11.5k
      91, // ssub_2 -> DQuad_with_qsub_1_in_QPR_8
12618
11.5k
      91, // ssub_3 -> DQuad_with_qsub_1_in_QPR_8
12619
11.5k
      91, // ssub_4 -> DQuad_with_qsub_1_in_QPR_8
12620
11.5k
      91, // ssub_5 -> DQuad_with_qsub_1_in_QPR_8
12621
11.5k
      91, // ssub_6 -> DQuad_with_qsub_1_in_QPR_8
12622
11.5k
      91, // ssub_7 -> DQuad_with_qsub_1_in_QPR_8
12623
11.5k
      0,  // ssub_8
12624
11.5k
      0,  // ssub_9
12625
11.5k
      0,  // ssub_10
12626
11.5k
      0,  // ssub_11
12627
11.5k
      0,  // ssub_12
12628
11.5k
      0,  // ssub_13
12629
11.5k
      0,  // dsub_7_then_ssub_0
12630
11.5k
      0,  // dsub_7_then_ssub_1
12631
11.5k
      91, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8
12632
11.5k
      91, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8
12633
11.5k
      91, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_8
12634
11.5k
      91, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_8
12635
11.5k
      91, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8
12636
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12637
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12638
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12639
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12640
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12641
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12642
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12643
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12644
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12645
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12646
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12647
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12648
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12649
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12650
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12651
11.5k
      0,  // dsub_5_dsub_7
12652
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12653
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12654
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12655
11.5k
    },
12656
11.5k
    { // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12657
11.5k
      92, // dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12658
11.5k
      92, // dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12659
11.5k
      92, // dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12660
11.5k
      92, // dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12661
11.5k
      0,  // dsub_4
12662
11.5k
      0,  // dsub_5
12663
11.5k
      0,  // dsub_6
12664
11.5k
      0,  // dsub_7
12665
11.5k
      0,  // gsub_0
12666
11.5k
      0,  // gsub_1
12667
11.5k
      0,  // qqsub_0
12668
11.5k
      0,  // qqsub_1
12669
11.5k
      92, // qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12670
11.5k
      92, // qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12671
11.5k
      0,  // qsub_2
12672
11.5k
      0,  // qsub_3
12673
11.5k
      92, // ssub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12674
11.5k
      92, // ssub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12675
11.5k
      92, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12676
11.5k
      92, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12677
11.5k
      92, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12678
11.5k
      92, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12679
11.5k
      92, // ssub_6 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12680
11.5k
      92, // ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12681
11.5k
      0,  // ssub_8
12682
11.5k
      0,  // ssub_9
12683
11.5k
      0,  // ssub_10
12684
11.5k
      0,  // ssub_11
12685
11.5k
      0,  // ssub_12
12686
11.5k
      0,  // ssub_13
12687
11.5k
      0,  // dsub_7_then_ssub_0
12688
11.5k
      0,  // dsub_7_then_ssub_1
12689
11.5k
      92, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12690
11.5k
      92, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12691
11.5k
      92, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12692
11.5k
      92, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12693
11.5k
      92, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12694
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12695
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12696
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12697
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12698
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12699
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12700
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12701
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12702
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12703
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12704
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12705
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12706
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12707
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12708
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12709
11.5k
      0,  // dsub_5_dsub_7
12710
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12711
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12712
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12713
11.5k
    },
12714
11.5k
    { // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12715
11.5k
      93, // dsub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12716
11.5k
      93, // dsub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12717
11.5k
      93, // dsub_2 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12718
11.5k
      93, // dsub_3 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12719
11.5k
      0,  // dsub_4
12720
11.5k
      0,  // dsub_5
12721
11.5k
      0,  // dsub_6
12722
11.5k
      0,  // dsub_7
12723
11.5k
      0,  // gsub_0
12724
11.5k
      0,  // gsub_1
12725
11.5k
      0,  // qqsub_0
12726
11.5k
      0,  // qqsub_1
12727
11.5k
      93, // qsub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12728
11.5k
      93, // qsub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12729
11.5k
      0,  // qsub_2
12730
11.5k
      0,  // qsub_3
12731
11.5k
      93, // ssub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12732
11.5k
      93, // ssub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12733
11.5k
      93, // ssub_2 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12734
11.5k
      93, // ssub_3 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12735
11.5k
      93, // ssub_4 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12736
11.5k
      93, // ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12737
11.5k
      93, // ssub_6 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12738
11.5k
      93, // ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12739
11.5k
      0,  // ssub_8
12740
11.5k
      0,  // ssub_9
12741
11.5k
      0,  // ssub_10
12742
11.5k
      0,  // ssub_11
12743
11.5k
      0,  // ssub_12
12744
11.5k
      0,  // ssub_13
12745
11.5k
      0,  // dsub_7_then_ssub_0
12746
11.5k
      0,  // dsub_7_then_ssub_1
12747
11.5k
      93, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12748
11.5k
      93, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12749
11.5k
      93, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12750
11.5k
      93, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12751
11.5k
      93, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12752
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12753
11.5k
      0,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12754
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12755
11.5k
      0,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12756
11.5k
      0,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12757
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9
12758
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12759
11.5k
      0,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12760
11.5k
      0,  // ssub_6_ssub_7_dsub_5
12761
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12762
11.5k
      0,  // ssub_6_ssub_7_dsub_5_dsub_7
12763
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9
12764
11.5k
      0,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12765
11.5k
      0,  // ssub_8_ssub_9_ssub_12_ssub_13
12766
11.5k
      0,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12767
11.5k
      0,  // dsub_5_dsub_7
12768
11.5k
      0,  // dsub_5_ssub_12_ssub_13_dsub_7
12769
11.5k
      0,  // dsub_5_ssub_12_ssub_13
12770
11.5k
      0,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12771
11.5k
    },
12772
11.5k
    { // QQQQPR
12773
11.5k
      94, // dsub_0 -> QQQQPR
12774
11.5k
      94, // dsub_1 -> QQQQPR
12775
11.5k
      94, // dsub_2 -> QQQQPR
12776
11.5k
      94, // dsub_3 -> QQQQPR
12777
11.5k
      94, // dsub_4 -> QQQQPR
12778
11.5k
      94, // dsub_5 -> QQQQPR
12779
11.5k
      94, // dsub_6 -> QQQQPR
12780
11.5k
      94, // dsub_7 -> QQQQPR
12781
11.5k
      0,  // gsub_0
12782
11.5k
      0,  // gsub_1
12783
11.5k
      94, // qqsub_0 -> QQQQPR
12784
11.5k
      94, // qqsub_1 -> QQQQPR
12785
11.5k
      94, // qsub_0 -> QQQQPR
12786
11.5k
      94, // qsub_1 -> QQQQPR
12787
11.5k
      94, // qsub_2 -> QQQQPR
12788
11.5k
      94, // qsub_3 -> QQQQPR
12789
11.5k
      95, // ssub_0 -> QQQQPR_with_ssub_0
12790
11.5k
      95, // ssub_1 -> QQQQPR_with_ssub_0
12791
11.5k
      95, // ssub_2 -> QQQQPR_with_ssub_0
12792
11.5k
      95, // ssub_3 -> QQQQPR_with_ssub_0
12793
11.5k
      96, // ssub_4 -> QQQQPR_with_ssub_4
12794
11.5k
      96, // ssub_5 -> QQQQPR_with_ssub_4
12795
11.5k
      96, // ssub_6 -> QQQQPR_with_ssub_4
12796
11.5k
      96, // ssub_7 -> QQQQPR_with_ssub_4
12797
11.5k
      97, // ssub_8 -> QQQQPR_with_ssub_8
12798
11.5k
      97, // ssub_9 -> QQQQPR_with_ssub_8
12799
11.5k
      97, // ssub_10 -> QQQQPR_with_ssub_8
12800
11.5k
      97, // ssub_11 -> QQQQPR_with_ssub_8
12801
11.5k
      98, // ssub_12 -> QQQQPR_with_ssub_12
12802
11.5k
      98, // ssub_13 -> QQQQPR_with_ssub_12
12803
11.5k
      98, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
12804
11.5k
      98, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
12805
11.5k
      94, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR
12806
11.5k
      94, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR
12807
11.5k
      94, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR
12808
11.5k
      94, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR
12809
11.5k
      94, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR
12810
11.5k
      94, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR
12811
11.5k
      94, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR
12812
11.5k
      94, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR
12813
11.5k
      94, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR
12814
11.5k
      94, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR
12815
11.5k
      94, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR
12816
11.5k
      94, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR
12817
11.5k
      94, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR
12818
11.5k
      94, // ssub_6_ssub_7_dsub_5 -> QQQQPR
12819
11.5k
      94, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR
12820
11.5k
      94, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR
12821
11.5k
      94, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR
12822
11.5k
      94, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR
12823
11.5k
      94, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR
12824
11.5k
      94, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR
12825
11.5k
      94, // dsub_5_dsub_7 -> QQQQPR
12826
11.5k
      94, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR
12827
11.5k
      94, // dsub_5_ssub_12_ssub_13 -> QQQQPR
12828
11.5k
      94, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR
12829
11.5k
    },
12830
11.5k
    { // QQQQPR_with_ssub_0
12831
11.5k
      95, // dsub_0 -> QQQQPR_with_ssub_0
12832
11.5k
      95, // dsub_1 -> QQQQPR_with_ssub_0
12833
11.5k
      95, // dsub_2 -> QQQQPR_with_ssub_0
12834
11.5k
      95, // dsub_3 -> QQQQPR_with_ssub_0
12835
11.5k
      95, // dsub_4 -> QQQQPR_with_ssub_0
12836
11.5k
      95, // dsub_5 -> QQQQPR_with_ssub_0
12837
11.5k
      95, // dsub_6 -> QQQQPR_with_ssub_0
12838
11.5k
      95, // dsub_7 -> QQQQPR_with_ssub_0
12839
11.5k
      0,  // gsub_0
12840
11.5k
      0,  // gsub_1
12841
11.5k
      95, // qqsub_0 -> QQQQPR_with_ssub_0
12842
11.5k
      95, // qqsub_1 -> QQQQPR_with_ssub_0
12843
11.5k
      95, // qsub_0 -> QQQQPR_with_ssub_0
12844
11.5k
      95, // qsub_1 -> QQQQPR_with_ssub_0
12845
11.5k
      95, // qsub_2 -> QQQQPR_with_ssub_0
12846
11.5k
      95, // qsub_3 -> QQQQPR_with_ssub_0
12847
11.5k
      95, // ssub_0 -> QQQQPR_with_ssub_0
12848
11.5k
      95, // ssub_1 -> QQQQPR_with_ssub_0
12849
11.5k
      95, // ssub_2 -> QQQQPR_with_ssub_0
12850
11.5k
      95, // ssub_3 -> QQQQPR_with_ssub_0
12851
11.5k
      96, // ssub_4 -> QQQQPR_with_ssub_4
12852
11.5k
      96, // ssub_5 -> QQQQPR_with_ssub_4
12853
11.5k
      96, // ssub_6 -> QQQQPR_with_ssub_4
12854
11.5k
      96, // ssub_7 -> QQQQPR_with_ssub_4
12855
11.5k
      97, // ssub_8 -> QQQQPR_with_ssub_8
12856
11.5k
      97, // ssub_9 -> QQQQPR_with_ssub_8
12857
11.5k
      97, // ssub_10 -> QQQQPR_with_ssub_8
12858
11.5k
      97, // ssub_11 -> QQQQPR_with_ssub_8
12859
11.5k
      98, // ssub_12 -> QQQQPR_with_ssub_12
12860
11.5k
      98, // ssub_13 -> QQQQPR_with_ssub_12
12861
11.5k
      98, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
12862
11.5k
      98, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
12863
11.5k
      95, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_0
12864
11.5k
      95, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_0
12865
11.5k
      95, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_0
12866
11.5k
      95, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_0
12867
11.5k
      95, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_0
12868
11.5k
      95, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
12869
11.5k
      95, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
12870
11.5k
      95, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_0
12871
11.5k
      95, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_0
12872
11.5k
      95, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
12873
11.5k
      95, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
12874
11.5k
      95, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
12875
11.5k
      95, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
12876
11.5k
      95, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_0
12877
11.5k
      95, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_0
12878
11.5k
      95, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_0
12879
11.5k
      95, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
12880
11.5k
      95, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
12881
11.5k
      95, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
12882
11.5k
      95, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
12883
11.5k
      95, // dsub_5_dsub_7 -> QQQQPR_with_ssub_0
12884
11.5k
      95, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_0
12885
11.5k
      95, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
12886
11.5k
      95, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_0
12887
11.5k
    },
12888
11.5k
    { // QQQQPR_with_ssub_4
12889
11.5k
      96, // dsub_0 -> QQQQPR_with_ssub_4
12890
11.5k
      96, // dsub_1 -> QQQQPR_with_ssub_4
12891
11.5k
      96, // dsub_2 -> QQQQPR_with_ssub_4
12892
11.5k
      96, // dsub_3 -> QQQQPR_with_ssub_4
12893
11.5k
      96, // dsub_4 -> QQQQPR_with_ssub_4
12894
11.5k
      96, // dsub_5 -> QQQQPR_with_ssub_4
12895
11.5k
      96, // dsub_6 -> QQQQPR_with_ssub_4
12896
11.5k
      96, // dsub_7 -> QQQQPR_with_ssub_4
12897
11.5k
      0,  // gsub_0
12898
11.5k
      0,  // gsub_1
12899
11.5k
      96, // qqsub_0 -> QQQQPR_with_ssub_4
12900
11.5k
      96, // qqsub_1 -> QQQQPR_with_ssub_4
12901
11.5k
      96, // qsub_0 -> QQQQPR_with_ssub_4
12902
11.5k
      96, // qsub_1 -> QQQQPR_with_ssub_4
12903
11.5k
      96, // qsub_2 -> QQQQPR_with_ssub_4
12904
11.5k
      96, // qsub_3 -> QQQQPR_with_ssub_4
12905
11.5k
      96, // ssub_0 -> QQQQPR_with_ssub_4
12906
11.5k
      96, // ssub_1 -> QQQQPR_with_ssub_4
12907
11.5k
      96, // ssub_2 -> QQQQPR_with_ssub_4
12908
11.5k
      96, // ssub_3 -> QQQQPR_with_ssub_4
12909
11.5k
      96, // ssub_4 -> QQQQPR_with_ssub_4
12910
11.5k
      96, // ssub_5 -> QQQQPR_with_ssub_4
12911
11.5k
      96, // ssub_6 -> QQQQPR_with_ssub_4
12912
11.5k
      96, // ssub_7 -> QQQQPR_with_ssub_4
12913
11.5k
      97, // ssub_8 -> QQQQPR_with_ssub_8
12914
11.5k
      97, // ssub_9 -> QQQQPR_with_ssub_8
12915
11.5k
      97, // ssub_10 -> QQQQPR_with_ssub_8
12916
11.5k
      97, // ssub_11 -> QQQQPR_with_ssub_8
12917
11.5k
      98, // ssub_12 -> QQQQPR_with_ssub_12
12918
11.5k
      98, // ssub_13 -> QQQQPR_with_ssub_12
12919
11.5k
      98, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
12920
11.5k
      98, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
12921
11.5k
      96, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_4
12922
11.5k
      96, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_4
12923
11.5k
      96, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_4
12924
11.5k
      96, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_4
12925
11.5k
      96, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_4
12926
11.5k
      96, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
12927
11.5k
      96, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
12928
11.5k
      96, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_4
12929
11.5k
      96, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_4
12930
11.5k
      96, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
12931
11.5k
      96, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
12932
11.5k
      96, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
12933
11.5k
      96, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
12934
11.5k
      96, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_4
12935
11.5k
      96, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_4
12936
11.5k
      96, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_4
12937
11.5k
      96, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
12938
11.5k
      96, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
12939
11.5k
      96, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
12940
11.5k
      96, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
12941
11.5k
      96, // dsub_5_dsub_7 -> QQQQPR_with_ssub_4
12942
11.5k
      96, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_4
12943
11.5k
      96, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
12944
11.5k
      96, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_4
12945
11.5k
    },
12946
11.5k
    { // QQQQPR_with_ssub_8
12947
11.5k
      97, // dsub_0 -> QQQQPR_with_ssub_8
12948
11.5k
      97, // dsub_1 -> QQQQPR_with_ssub_8
12949
11.5k
      97, // dsub_2 -> QQQQPR_with_ssub_8
12950
11.5k
      97, // dsub_3 -> QQQQPR_with_ssub_8
12951
11.5k
      97, // dsub_4 -> QQQQPR_with_ssub_8
12952
11.5k
      97, // dsub_5 -> QQQQPR_with_ssub_8
12953
11.5k
      97, // dsub_6 -> QQQQPR_with_ssub_8
12954
11.5k
      97, // dsub_7 -> QQQQPR_with_ssub_8
12955
11.5k
      0,  // gsub_0
12956
11.5k
      0,  // gsub_1
12957
11.5k
      97, // qqsub_0 -> QQQQPR_with_ssub_8
12958
11.5k
      97, // qqsub_1 -> QQQQPR_with_ssub_8
12959
11.5k
      97, // qsub_0 -> QQQQPR_with_ssub_8
12960
11.5k
      97, // qsub_1 -> QQQQPR_with_ssub_8
12961
11.5k
      97, // qsub_2 -> QQQQPR_with_ssub_8
12962
11.5k
      97, // qsub_3 -> QQQQPR_with_ssub_8
12963
11.5k
      97, // ssub_0 -> QQQQPR_with_ssub_8
12964
11.5k
      97, // ssub_1 -> QQQQPR_with_ssub_8
12965
11.5k
      97, // ssub_2 -> QQQQPR_with_ssub_8
12966
11.5k
      97, // ssub_3 -> QQQQPR_with_ssub_8
12967
11.5k
      97, // ssub_4 -> QQQQPR_with_ssub_8
12968
11.5k
      97, // ssub_5 -> QQQQPR_with_ssub_8
12969
11.5k
      97, // ssub_6 -> QQQQPR_with_ssub_8
12970
11.5k
      97, // ssub_7 -> QQQQPR_with_ssub_8
12971
11.5k
      97, // ssub_8 -> QQQQPR_with_ssub_8
12972
11.5k
      97, // ssub_9 -> QQQQPR_with_ssub_8
12973
11.5k
      97, // ssub_10 -> QQQQPR_with_ssub_8
12974
11.5k
      97, // ssub_11 -> QQQQPR_with_ssub_8
12975
11.5k
      98, // ssub_12 -> QQQQPR_with_ssub_12
12976
11.5k
      98, // ssub_13 -> QQQQPR_with_ssub_12
12977
11.5k
      98, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
12978
11.5k
      98, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
12979
11.5k
      97, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_8
12980
11.5k
      97, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_8
12981
11.5k
      97, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_8
12982
11.5k
      97, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_8
12983
11.5k
      97, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_8
12984
11.5k
      97, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
12985
11.5k
      97, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
12986
11.5k
      97, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_8
12987
11.5k
      97, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_8
12988
11.5k
      97, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
12989
11.5k
      97, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
12990
11.5k
      97, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
12991
11.5k
      97, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
12992
11.5k
      97, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_8
12993
11.5k
      97, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_8
12994
11.5k
      97, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_8
12995
11.5k
      97, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
12996
11.5k
      97, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
12997
11.5k
      97, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
12998
11.5k
      97, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
12999
11.5k
      97, // dsub_5_dsub_7 -> QQQQPR_with_ssub_8
13000
11.5k
      97, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_8
13001
11.5k
      97, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
13002
11.5k
      97, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_8
13003
11.5k
    },
13004
11.5k
    { // QQQQPR_with_ssub_12
13005
11.5k
      98, // dsub_0 -> QQQQPR_with_ssub_12
13006
11.5k
      98, // dsub_1 -> QQQQPR_with_ssub_12
13007
11.5k
      98, // dsub_2 -> QQQQPR_with_ssub_12
13008
11.5k
      98, // dsub_3 -> QQQQPR_with_ssub_12
13009
11.5k
      98, // dsub_4 -> QQQQPR_with_ssub_12
13010
11.5k
      98, // dsub_5 -> QQQQPR_with_ssub_12
13011
11.5k
      98, // dsub_6 -> QQQQPR_with_ssub_12
13012
11.5k
      98, // dsub_7 -> QQQQPR_with_ssub_12
13013
11.5k
      0,  // gsub_0
13014
11.5k
      0,  // gsub_1
13015
11.5k
      98, // qqsub_0 -> QQQQPR_with_ssub_12
13016
11.5k
      98, // qqsub_1 -> QQQQPR_with_ssub_12
13017
11.5k
      98, // qsub_0 -> QQQQPR_with_ssub_12
13018
11.5k
      98, // qsub_1 -> QQQQPR_with_ssub_12
13019
11.5k
      98, // qsub_2 -> QQQQPR_with_ssub_12
13020
11.5k
      98, // qsub_3 -> QQQQPR_with_ssub_12
13021
11.5k
      98, // ssub_0 -> QQQQPR_with_ssub_12
13022
11.5k
      98, // ssub_1 -> QQQQPR_with_ssub_12
13023
11.5k
      98, // ssub_2 -> QQQQPR_with_ssub_12
13024
11.5k
      98, // ssub_3 -> QQQQPR_with_ssub_12
13025
11.5k
      98, // ssub_4 -> QQQQPR_with_ssub_12
13026
11.5k
      98, // ssub_5 -> QQQQPR_with_ssub_12
13027
11.5k
      98, // ssub_6 -> QQQQPR_with_ssub_12
13028
11.5k
      98, // ssub_7 -> QQQQPR_with_ssub_12
13029
11.5k
      98, // ssub_8 -> QQQQPR_with_ssub_12
13030
11.5k
      98, // ssub_9 -> QQQQPR_with_ssub_12
13031
11.5k
      98, // ssub_10 -> QQQQPR_with_ssub_12
13032
11.5k
      98, // ssub_11 -> QQQQPR_with_ssub_12
13033
11.5k
      98, // ssub_12 -> QQQQPR_with_ssub_12
13034
11.5k
      98, // ssub_13 -> QQQQPR_with_ssub_12
13035
11.5k
      98, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
13036
11.5k
      98, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
13037
11.5k
      98, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_12
13038
11.5k
      98, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_12
13039
11.5k
      98, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_12
13040
11.5k
      98, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_12
13041
11.5k
      98, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_12
13042
11.5k
      98, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
13043
11.5k
      98, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13044
11.5k
      98, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_12
13045
11.5k
      98, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_12
13046
11.5k
      98, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
13047
11.5k
      98, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
13048
11.5k
      98, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
13049
11.5k
      98, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13050
11.5k
      98, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_12
13051
11.5k
      98, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_12
13052
11.5k
      98, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_12
13053
11.5k
      98, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
13054
11.5k
      98, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13055
11.5k
      98, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13056
11.5k
      98, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13057
11.5k
      98, // dsub_5_dsub_7 -> QQQQPR_with_ssub_12
13058
11.5k
      98, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_12
13059
11.5k
      98, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13060
11.5k
      98, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_12
13061
11.5k
    },
13062
11.5k
    { // QQQQPR_with_dsub_0_in_DPR_8
13063
11.5k
      99, // dsub_0 -> QQQQPR_with_dsub_0_in_DPR_8
13064
11.5k
      99, // dsub_1 -> QQQQPR_with_dsub_0_in_DPR_8
13065
11.5k
      99, // dsub_2 -> QQQQPR_with_dsub_0_in_DPR_8
13066
11.5k
      99, // dsub_3 -> QQQQPR_with_dsub_0_in_DPR_8
13067
11.5k
      99, // dsub_4 -> QQQQPR_with_dsub_0_in_DPR_8
13068
11.5k
      99, // dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13069
11.5k
      99, // dsub_6 -> QQQQPR_with_dsub_0_in_DPR_8
13070
11.5k
      99, // dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13071
11.5k
      0,  // gsub_0
13072
11.5k
      0,  // gsub_1
13073
11.5k
      99, // qqsub_0 -> QQQQPR_with_dsub_0_in_DPR_8
13074
11.5k
      99, // qqsub_1 -> QQQQPR_with_dsub_0_in_DPR_8
13075
11.5k
      99, // qsub_0 -> QQQQPR_with_dsub_0_in_DPR_8
13076
11.5k
      99, // qsub_1 -> QQQQPR_with_dsub_0_in_DPR_8
13077
11.5k
      99, // qsub_2 -> QQQQPR_with_dsub_0_in_DPR_8
13078
11.5k
      99, // qsub_3 -> QQQQPR_with_dsub_0_in_DPR_8
13079
11.5k
      99, // ssub_0 -> QQQQPR_with_dsub_0_in_DPR_8
13080
11.5k
      99, // ssub_1 -> QQQQPR_with_dsub_0_in_DPR_8
13081
11.5k
      99, // ssub_2 -> QQQQPR_with_dsub_0_in_DPR_8
13082
11.5k
      99, // ssub_3 -> QQQQPR_with_dsub_0_in_DPR_8
13083
11.5k
      99, // ssub_4 -> QQQQPR_with_dsub_0_in_DPR_8
13084
11.5k
      99, // ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13085
11.5k
      99, // ssub_6 -> QQQQPR_with_dsub_0_in_DPR_8
13086
11.5k
      99, // ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13087
11.5k
      99, // ssub_8 -> QQQQPR_with_dsub_0_in_DPR_8
13088
11.5k
      99, // ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13089
11.5k
      99, // ssub_10 -> QQQQPR_with_dsub_0_in_DPR_8
13090
11.5k
      99, // ssub_11 -> QQQQPR_with_dsub_0_in_DPR_8
13091
11.5k
      99, // ssub_12 -> QQQQPR_with_dsub_0_in_DPR_8
13092
11.5k
      99, // ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13093
11.5k
      99, // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_0_in_DPR_8
13094
11.5k
      99, // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_0_in_DPR_8
13095
11.5k
      99, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13096
11.5k
      99, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13097
11.5k
      99, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13098
11.5k
      99, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13099
11.5k
      99, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13100
11.5k
      99, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13101
11.5k
      99, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13102
11.5k
      99, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13103
11.5k
      99, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13104
11.5k
      99, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13105
11.5k
      99, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13106
11.5k
      99, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13107
11.5k
      99, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13108
11.5k
      99, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13109
11.5k
      99, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13110
11.5k
      99, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13111
11.5k
      99, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13112
11.5k
      99, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13113
11.5k
      99, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13114
11.5k
      99, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13115
11.5k
      99, // dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13116
11.5k
      99, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13117
11.5k
      99, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13118
11.5k
      99, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_0_in_DPR_8
13119
11.5k
    },
13120
11.5k
    { // QQQQPR_with_dsub_2_in_DPR_8
13121
11.5k
      100,  // dsub_0 -> QQQQPR_with_dsub_2_in_DPR_8
13122
11.5k
      100,  // dsub_1 -> QQQQPR_with_dsub_2_in_DPR_8
13123
11.5k
      100,  // dsub_2 -> QQQQPR_with_dsub_2_in_DPR_8
13124
11.5k
      100,  // dsub_3 -> QQQQPR_with_dsub_2_in_DPR_8
13125
11.5k
      100,  // dsub_4 -> QQQQPR_with_dsub_2_in_DPR_8
13126
11.5k
      100,  // dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13127
11.5k
      100,  // dsub_6 -> QQQQPR_with_dsub_2_in_DPR_8
13128
11.5k
      100,  // dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13129
11.5k
      0,  // gsub_0
13130
11.5k
      0,  // gsub_1
13131
11.5k
      100,  // qqsub_0 -> QQQQPR_with_dsub_2_in_DPR_8
13132
11.5k
      100,  // qqsub_1 -> QQQQPR_with_dsub_2_in_DPR_8
13133
11.5k
      100,  // qsub_0 -> QQQQPR_with_dsub_2_in_DPR_8
13134
11.5k
      100,  // qsub_1 -> QQQQPR_with_dsub_2_in_DPR_8
13135
11.5k
      100,  // qsub_2 -> QQQQPR_with_dsub_2_in_DPR_8
13136
11.5k
      100,  // qsub_3 -> QQQQPR_with_dsub_2_in_DPR_8
13137
11.5k
      100,  // ssub_0 -> QQQQPR_with_dsub_2_in_DPR_8
13138
11.5k
      100,  // ssub_1 -> QQQQPR_with_dsub_2_in_DPR_8
13139
11.5k
      100,  // ssub_2 -> QQQQPR_with_dsub_2_in_DPR_8
13140
11.5k
      100,  // ssub_3 -> QQQQPR_with_dsub_2_in_DPR_8
13141
11.5k
      100,  // ssub_4 -> QQQQPR_with_dsub_2_in_DPR_8
13142
11.5k
      100,  // ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13143
11.5k
      100,  // ssub_6 -> QQQQPR_with_dsub_2_in_DPR_8
13144
11.5k
      100,  // ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13145
11.5k
      100,  // ssub_8 -> QQQQPR_with_dsub_2_in_DPR_8
13146
11.5k
      100,  // ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13147
11.5k
      100,  // ssub_10 -> QQQQPR_with_dsub_2_in_DPR_8
13148
11.5k
      100,  // ssub_11 -> QQQQPR_with_dsub_2_in_DPR_8
13149
11.5k
      100,  // ssub_12 -> QQQQPR_with_dsub_2_in_DPR_8
13150
11.5k
      100,  // ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13151
11.5k
      100,  // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_2_in_DPR_8
13152
11.5k
      100,  // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_2_in_DPR_8
13153
11.5k
      100,  // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13154
11.5k
      100,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13155
11.5k
      100,  // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13156
11.5k
      100,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13157
11.5k
      100,  // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13158
11.5k
      100,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13159
11.5k
      100,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13160
11.5k
      100,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13161
11.5k
      100,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13162
11.5k
      100,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13163
11.5k
      100,  // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13164
11.5k
      100,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13165
11.5k
      100,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13166
11.5k
      100,  // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13167
11.5k
      100,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13168
11.5k
      100,  // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13169
11.5k
      100,  // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13170
11.5k
      100,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13171
11.5k
      100,  // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13172
11.5k
      100,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13173
11.5k
      100,  // dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13174
11.5k
      100,  // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13175
11.5k
      100,  // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13176
11.5k
      100,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_2_in_DPR_8
13177
11.5k
    },
13178
11.5k
    { // QQQQPR_with_dsub_4_in_DPR_8
13179
11.5k
      101,  // dsub_0 -> QQQQPR_with_dsub_4_in_DPR_8
13180
11.5k
      101,  // dsub_1 -> QQQQPR_with_dsub_4_in_DPR_8
13181
11.5k
      101,  // dsub_2 -> QQQQPR_with_dsub_4_in_DPR_8
13182
11.5k
      101,  // dsub_3 -> QQQQPR_with_dsub_4_in_DPR_8
13183
11.5k
      101,  // dsub_4 -> QQQQPR_with_dsub_4_in_DPR_8
13184
11.5k
      101,  // dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13185
11.5k
      101,  // dsub_6 -> QQQQPR_with_dsub_4_in_DPR_8
13186
11.5k
      101,  // dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13187
11.5k
      0,  // gsub_0
13188
11.5k
      0,  // gsub_1
13189
11.5k
      101,  // qqsub_0 -> QQQQPR_with_dsub_4_in_DPR_8
13190
11.5k
      101,  // qqsub_1 -> QQQQPR_with_dsub_4_in_DPR_8
13191
11.5k
      101,  // qsub_0 -> QQQQPR_with_dsub_4_in_DPR_8
13192
11.5k
      101,  // qsub_1 -> QQQQPR_with_dsub_4_in_DPR_8
13193
11.5k
      101,  // qsub_2 -> QQQQPR_with_dsub_4_in_DPR_8
13194
11.5k
      101,  // qsub_3 -> QQQQPR_with_dsub_4_in_DPR_8
13195
11.5k
      101,  // ssub_0 -> QQQQPR_with_dsub_4_in_DPR_8
13196
11.5k
      101,  // ssub_1 -> QQQQPR_with_dsub_4_in_DPR_8
13197
11.5k
      101,  // ssub_2 -> QQQQPR_with_dsub_4_in_DPR_8
13198
11.5k
      101,  // ssub_3 -> QQQQPR_with_dsub_4_in_DPR_8
13199
11.5k
      101,  // ssub_4 -> QQQQPR_with_dsub_4_in_DPR_8
13200
11.5k
      101,  // ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13201
11.5k
      101,  // ssub_6 -> QQQQPR_with_dsub_4_in_DPR_8
13202
11.5k
      101,  // ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13203
11.5k
      101,  // ssub_8 -> QQQQPR_with_dsub_4_in_DPR_8
13204
11.5k
      101,  // ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13205
11.5k
      101,  // ssub_10 -> QQQQPR_with_dsub_4_in_DPR_8
13206
11.5k
      101,  // ssub_11 -> QQQQPR_with_dsub_4_in_DPR_8
13207
11.5k
      101,  // ssub_12 -> QQQQPR_with_dsub_4_in_DPR_8
13208
11.5k
      101,  // ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13209
11.5k
      101,  // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_4_in_DPR_8
13210
11.5k
      101,  // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_4_in_DPR_8
13211
11.5k
      101,  // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13212
11.5k
      101,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13213
11.5k
      101,  // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13214
11.5k
      101,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13215
11.5k
      101,  // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13216
11.5k
      101,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13217
11.5k
      101,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13218
11.5k
      101,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13219
11.5k
      101,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13220
11.5k
      101,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13221
11.5k
      101,  // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13222
11.5k
      101,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13223
11.5k
      101,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13224
11.5k
      101,  // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13225
11.5k
      101,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13226
11.5k
      101,  // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13227
11.5k
      101,  // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13228
11.5k
      101,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13229
11.5k
      101,  // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13230
11.5k
      101,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13231
11.5k
      101,  // dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13232
11.5k
      101,  // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13233
11.5k
      101,  // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13234
11.5k
      101,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_4_in_DPR_8
13235
11.5k
    },
13236
11.5k
    { // QQQQPR_with_dsub_6_in_DPR_8
13237
11.5k
      102,  // dsub_0 -> QQQQPR_with_dsub_6_in_DPR_8
13238
11.5k
      102,  // dsub_1 -> QQQQPR_with_dsub_6_in_DPR_8
13239
11.5k
      102,  // dsub_2 -> QQQQPR_with_dsub_6_in_DPR_8
13240
11.5k
      102,  // dsub_3 -> QQQQPR_with_dsub_6_in_DPR_8
13241
11.5k
      102,  // dsub_4 -> QQQQPR_with_dsub_6_in_DPR_8
13242
11.5k
      102,  // dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13243
11.5k
      102,  // dsub_6 -> QQQQPR_with_dsub_6_in_DPR_8
13244
11.5k
      102,  // dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13245
11.5k
      0,  // gsub_0
13246
11.5k
      0,  // gsub_1
13247
11.5k
      102,  // qqsub_0 -> QQQQPR_with_dsub_6_in_DPR_8
13248
11.5k
      102,  // qqsub_1 -> QQQQPR_with_dsub_6_in_DPR_8
13249
11.5k
      102,  // qsub_0 -> QQQQPR_with_dsub_6_in_DPR_8
13250
11.5k
      102,  // qsub_1 -> QQQQPR_with_dsub_6_in_DPR_8
13251
11.5k
      102,  // qsub_2 -> QQQQPR_with_dsub_6_in_DPR_8
13252
11.5k
      102,  // qsub_3 -> QQQQPR_with_dsub_6_in_DPR_8
13253
11.5k
      102,  // ssub_0 -> QQQQPR_with_dsub_6_in_DPR_8
13254
11.5k
      102,  // ssub_1 -> QQQQPR_with_dsub_6_in_DPR_8
13255
11.5k
      102,  // ssub_2 -> QQQQPR_with_dsub_6_in_DPR_8
13256
11.5k
      102,  // ssub_3 -> QQQQPR_with_dsub_6_in_DPR_8
13257
11.5k
      102,  // ssub_4 -> QQQQPR_with_dsub_6_in_DPR_8
13258
11.5k
      102,  // ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13259
11.5k
      102,  // ssub_6 -> QQQQPR_with_dsub_6_in_DPR_8
13260
11.5k
      102,  // ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13261
11.5k
      102,  // ssub_8 -> QQQQPR_with_dsub_6_in_DPR_8
13262
11.5k
      102,  // ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13263
11.5k
      102,  // ssub_10 -> QQQQPR_with_dsub_6_in_DPR_8
13264
11.5k
      102,  // ssub_11 -> QQQQPR_with_dsub_6_in_DPR_8
13265
11.5k
      102,  // ssub_12 -> QQQQPR_with_dsub_6_in_DPR_8
13266
11.5k
      102,  // ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13267
11.5k
      102,  // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_6_in_DPR_8
13268
11.5k
      102,  // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_6_in_DPR_8
13269
11.5k
      102,  // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13270
11.5k
      102,  // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13271
11.5k
      102,  // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13272
11.5k
      102,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13273
11.5k
      102,  // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13274
11.5k
      102,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13275
11.5k
      102,  // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13276
11.5k
      102,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13277
11.5k
      102,  // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13278
11.5k
      102,  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13279
11.5k
      102,  // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13280
11.5k
      102,  // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13281
11.5k
      102,  // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13282
11.5k
      102,  // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13283
11.5k
      102,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13284
11.5k
      102,  // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13285
11.5k
      102,  // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13286
11.5k
      102,  // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13287
11.5k
      102,  // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13288
11.5k
      102,  // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13289
11.5k
      102,  // dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13290
11.5k
      102,  // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13291
11.5k
      102,  // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13292
11.5k
      102,  // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_6_in_DPR_8
13293
11.5k
    },
13294
11.5k
  };
13295
11.5k
  assert(RC && "Missing regclass");
13296
11.5k
  if (
!Idx11.5k
)
return RC0
;
13297
11.5k
  --Idx;
13298
11.5k
  assert(Idx < 56 && "Bad subreg");
13299
11.5k
  unsigned TV = Table[RC->getID()][Idx];
13300
11.5k
  return TV ? 
getRegClass(TV - 1)11.5k
:
nullptr0
;
13301
11.5k
}
13302
13303
/// Get the weight in units of pressure for this register class.
13304
const RegClassWeight &ARMGenRegisterInfo::
13305
347k
getRegClassWeight(const TargetRegisterClass *RC) const {
13306
347k
  static const RegClassWeight RCWeightTable[] = {
13307
347k
    {1, 32},    // SPR
13308
347k
    {1, 16},    // GPR
13309
347k
    {1, 16},    // GPRwithAPSR
13310
347k
    {1, 16},    // SPR_8
13311
347k
    {1, 15},    // GPRnopc
13312
347k
    {1, 14},    // rGPR
13313
347k
    {1, 9},   // tGPRwithpc
13314
347k
    {1, 8},   // hGPR
13315
347k
    {1, 8},   // tGPR
13316
347k
    {1, 7},   // GPRnopc_and_hGPR
13317
347k
    {1, 6},   // hGPR_and_rGPR
13318
347k
    {1, 5},   // tcGPR
13319
347k
    {1, 4},   // tGPR_and_tcGPR
13320
347k
    {0, 0},   // CCR
13321
347k
    {1, 1},   // GPRsp
13322
347k
    {1, 1},   // hGPR_and_tGPRwithpc
13323
347k
    {1, 1},   // hGPR_and_tcGPR
13324
347k
    {2, 64},    // DPR
13325
347k
    {2, 32},    // DPR_VFP2
13326
347k
    {2, 16},    // DPR_8
13327
347k
    {2, 14},    // GPRPair
13328
347k
    {2, 12},    // GPRPair_with_gsub_1_in_rGPR
13329
347k
    {2, 8},   // GPRPair_with_gsub_0_in_tGPR
13330
347k
    {2, 6},   // GPRPair_with_gsub_0_in_hGPR
13331
347k
    {2, 6},   // GPRPair_with_gsub_0_in_tcGPR
13332
347k
    {2, 4},   // GPRPair_with_gsub_1_in_hGPR_and_rGPR
13333
347k
    {2, 4},   // GPRPair_with_gsub_1_in_tcGPR
13334
347k
    {2, 2},   // GPRPair_with_gsub_1_in_GPRsp
13335
347k
    {4, 64},    // DPairSpc
13336
347k
    {4, 36},    // DPairSpc_with_ssub_0
13337
347k
    {4, 32},    // DPairSpc_with_ssub_4
13338
347k
    {4, 20},    // DPairSpc_with_dsub_0_in_DPR_8
13339
347k
    {4, 16},    // DPairSpc_with_dsub_2_in_DPR_8
13340
347k
    {4, 64},    // DPair
13341
347k
    {4, 34},    // DPair_with_ssub_0
13342
347k
    {4, 64},    // QPR
13343
347k
    {4, 32},    // DPair_with_ssub_2
13344
347k
    {4, 18},    // DPair_with_dsub_0_in_DPR_8
13345
347k
    {4, 32},    // QPR_VFP2
13346
347k
    {4, 16},    // DPair_with_dsub_1_in_DPR_8
13347
347k
    {4, 16},    // QPR_8
13348
347k
    {6, 64},    // DTriple
13349
347k
    {6, 64},    // DTripleSpc
13350
347k
    {6, 40},    // DTripleSpc_with_ssub_0
13351
347k
    {6, 36},    // DTriple_with_ssub_0
13352
347k
    {6, 62},    // DTriple_with_qsub_0_in_QPR
13353
347k
    {6, 34},    // DTriple_with_ssub_2
13354
347k
    {6, 62},    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13355
347k
    {6, 36},    // DTripleSpc_with_ssub_4
13356
347k
    {6, 32},    // DTriple_with_ssub_4
13357
347k
    {6, 32},    // DTripleSpc_with_ssub_8
13358
347k
    {6, 24},    // DTripleSpc_with_dsub_0_in_DPR_8
13359
347k
    {6, 20},    // DTriple_with_dsub_0_in_DPR_8
13360
347k
    {6, 34},    // DTriple_with_qsub_0_in_QPR_VFP2
13361
347k
    {6, 34},    // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13362
347k
    {6, 18},    // DTriple_with_dsub_1_in_DPR_8
13363
347k
    {6, 30},    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
13364
347k
    {6, 30},    // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
13365
347k
    {6, 20},    // DTripleSpc_with_dsub_2_in_DPR_8
13366
347k
    {6, 16},    // DTriple_with_dsub_2_in_DPR_8
13367
347k
    {6, 16},    // DTripleSpc_with_dsub_4_in_DPR_8
13368
347k
    {6, 18},    // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13369
347k
    {6, 18},    // DTriple_with_qsub_0_in_QPR_8
13370
347k
    {6, 14},    // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
13371
347k
    {6, 14},    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
13372
347k
    {6, 64},    // DQuadSpc
13373
347k
    {6, 40},    // DQuadSpc_with_ssub_0
13374
347k
    {6, 36},    // DQuadSpc_with_ssub_4
13375
347k
    {6, 32},    // DQuadSpc_with_ssub_8
13376
347k
    {6, 24},    // DQuadSpc_with_dsub_0_in_DPR_8
13377
347k
    {6, 20},    // DQuadSpc_with_dsub_2_in_DPR_8
13378
347k
    {6, 16},    // DQuadSpc_with_dsub_4_in_DPR_8
13379
347k
    {8, 64},    // DQuad
13380
347k
    {8, 38},    // DQuad_with_ssub_0
13381
347k
    {8, 36},    // DQuad_with_ssub_2
13382
347k
    {8, 64},    // QQPR
13383
347k
    {8, 60},    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13384
347k
    {8, 34},    // DQuad_with_ssub_4
13385
347k
    {8, 32},    // DQuad_with_ssub_6
13386
347k
    {8, 22},    // DQuad_with_dsub_0_in_DPR_8
13387
347k
    {8, 36},    // DQuad_with_qsub_0_in_QPR_VFP2
13388
347k
    {8, 36},    // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13389
347k
    {8, 20},    // DQuad_with_dsub_1_in_DPR_8
13390
347k
    {8, 32},    // DQuad_with_qsub_1_in_QPR_VFP2
13391
347k
    {8, 32},    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
13392
347k
    {8, 18},    // DQuad_with_dsub_2_in_DPR_8
13393
347k
    {8, 28},    // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13394
347k
    {8, 16},    // DQuad_with_dsub_3_in_DPR_8
13395
347k
    {8, 20},    // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13396
347k
    {8, 20},    // DQuad_with_qsub_0_in_QPR_8
13397
347k
    {8, 16},    // DQuad_with_qsub_1_in_QPR_8
13398
347k
    {8, 16},    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
13399
347k
    {8, 12},    // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13400
347k
    {16, 64},   // QQQQPR
13401
347k
    {16, 44},   // QQQQPR_with_ssub_0
13402
347k
    {16, 40},   // QQQQPR_with_ssub_4
13403
347k
    {16, 36},   // QQQQPR_with_ssub_8
13404
347k
    {16, 32},   // QQQQPR_with_ssub_12
13405
347k
    {16, 28},   // QQQQPR_with_dsub_0_in_DPR_8
13406
347k
    {16, 24},   // QQQQPR_with_dsub_2_in_DPR_8
13407
347k
    {16, 20},   // QQQQPR_with_dsub_4_in_DPR_8
13408
347k
    {16, 16},   // QQQQPR_with_dsub_6_in_DPR_8
13409
347k
  };
13410
347k
  return RCWeightTable[RC->getID()];
13411
347k
}
13412
13413
/// Get the weight in units of pressure for this register unit.
13414
unsigned ARMGenRegisterInfo::
13415
21.7k
getRegUnitWeight(unsigned RegUnit) const {
13416
21.7k
  assert(RegUnit < 77 && "invalid register unit");
13417
21.7k
  static const uint8_t RUWeightTable[] = {
13418
21.7k
    0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
13419
21.7k
  return RUWeightTable[RegUnit];
13420
21.7k
}
13421
13422
13423
// Get the number of dimensions of register pressure.
13424
45.9k
unsigned ARMGenRegisterInfo::getNumRegPressureSets() const {
13425
45.9k
  return 21;
13426
45.9k
}
13427
13428
// Get the name of this register unit pressure set.
13429
const char *ARMGenRegisterInfo::
13430
0
getRegPressureSetName(unsigned Idx) const {
13431
0
  static const char *const PressureNameTable[] = {
13432
0
    "hGPR_and_tGPRwithpc",
13433
0
    "GPRsp",
13434
0
    "tcGPR",
13435
0
    "hGPR",
13436
0
    "tGPR",
13437
0
    "hGPR+tcGPR",
13438
0
    "GPR",
13439
0
    "DQuad_with_dsub_0_in_DPR_8",
13440
0
    "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2",
13441
0
    "SPR",
13442
0
    "DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
13443
0
    "DPair_with_ssub_0",
13444
0
    "DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
13445
0
    "DPairSpc_with_ssub_0",
13446
0
    "DQuad_with_ssub_0",
13447
0
    "DTripleSpc_with_ssub_0",
13448
0
    "QQQQPR_with_ssub_0",
13449
0
    "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
13450
0
    "DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
13451
0
    "DTriple_with_qsub_0_in_QPR",
13452
0
    "DPR",
13453
0
  };
13454
0
  return PressureNameTable[Idx];
13455
0
}
13456
13457
// Get the register unit pressure limit for this dimension.
13458
// This limit must be adjusted dynamically for reserved registers.
13459
unsigned ARMGenRegisterInfo::
13460
339k
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
13461
339k
  static const uint8_t PressureLimitTable[] = {
13462
339k
    1,    // 0: hGPR_and_tGPRwithpc
13463
339k
    2,    // 1: GPRsp
13464
339k
    6,    // 2: tcGPR
13465
339k
    8,    // 3: hGPR
13466
339k
    11,   // 4: tGPR
13467
339k
    12,   // 5: hGPR+tcGPR
13468
339k
    17,   // 6: GPR
13469
339k
    24,   // 7: DQuad_with_dsub_0_in_DPR_8
13470
339k
    32,   // 8: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
13471
339k
    32,   // 9: SPR
13472
339k
    34,   // 10: DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13473
339k
    34,   // 11: DPair_with_ssub_0
13474
339k
    36,   // 12: DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13475
339k
    36,   // 13: DPairSpc_with_ssub_0
13476
339k
    38,   // 14: DQuad_with_ssub_0
13477
339k
    40,   // 15: DTripleSpc_with_ssub_0
13478
339k
    44,   // 16: QQQQPR_with_ssub_0
13479
339k
    60,   // 17: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13480
339k
    62,   // 18: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13481
339k
    62,   // 19: DTriple_with_qsub_0_in_QPR
13482
339k
    64,   // 20: DPR
13483
339k
  };
13484
339k
  return PressureLimitTable[Idx];
13485
339k
}
13486
13487
/// Table of pressure sets per register class or unit.
13488
static const int RCSetsTable[] = {
13489
  /* 0 */ 4, 6, -1,
13490
  /* 3 */ 3, 5, 6, -1,
13491
  /* 7 */ 2, 4, 5, 6, -1,
13492
  /* 12 */ 0, 3, 4, 5, 6, -1,
13493
  /* 18 */ 1, 2, 3, 4, 5, 6, -1,
13494
  /* 25 */ 18, 20, -1,
13495
  /* 28 */ 7, 9, 11, 13, 14, 15, 16, 19, 20, -1,
13496
  /* 38 */ 12, 14, 15, 16, 17, 18, 19, 20, -1,
13497
  /* 47 */ 10, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1,
13498
  /* 58 */ 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1,
13499
  /* 71 */ 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1,
13500
};
13501
13502
/// Get the dimensions of register pressure impacted by this register class.
13503
/// Returns a -1 terminated array of pressure set IDs
13504
const int* ARMGenRegisterInfo::
13505
829k
getRegClassPressureSets(const TargetRegisterClass *RC) const {
13506
829k
  static const uint8_t RCSetStartTable[] = {
13507
829k
    29,1,1,28,1,1,0,3,0,3,3,7,7,2,18,12,18,26,29,28,1,1,0,3,7,3,7,18,26,31,29,28,28,26,30,26,29,28,29,28,28,26,26,33,31,35,30,25,31,29,29,28,28,30,47,28,72,29,28,28,28,71,28,28,71,26,33,31,29,28,28,28,26,32,31,26,42,30,29,28,31,38,28,29,58,28,72,28,71,28,28,71,71,26,34,33,31,29,29,28,28,28,};
13508
829k
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
13509
829k
}
13510
13511
/// Get the dimensions of register pressure impacted by this register unit.
13512
/// Returns a -1 terminated array of pressure set IDs
13513
const int* ARMGenRegisterInfo::
13514
21.7k
getRegUnitPressureSets(unsigned RegUnit) const {
13515
21.7k
  assert(RegUnit < 77 && "invalid register unit");
13516
21.7k
  static const uint8_t RUSetStartTable[] = {
13517
21.7k
    2,1,2,2,2,2,2,2,3,12,18,2,28,28,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,72,72,72,72,72,72,72,72,58,47,38,40,41,41,42,42,42,42,42,42,42,42,42,25,2,2,2,2,7,7,7,7,0,0,0,0,3,3,3,3,18,};
13518
21.7k
  return &RCSetsTable[RUSetStartTable[RegUnit]];
13519
21.7k
}
13520
13521
extern const MCRegisterDesc ARMRegDesc[];
13522
extern const MCPhysReg ARMRegDiffLists[];
13523
extern const LaneBitmask ARMLaneMaskLists[];
13524
extern const char ARMRegStrings[];
13525
extern const char ARMRegClassStrings[];
13526
extern const MCPhysReg ARMRegUnitRoots[][2];
13527
extern const uint16_t ARMSubRegIdxLists[];
13528
extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[];
13529
extern const uint16_t ARMRegEncodingTable[];
13530
// ARM Dwarf<->LLVM register mappings.
13531
extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[];
13532
extern const unsigned ARMDwarfFlavour0Dwarf2LSize;
13533
13534
extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[];
13535
extern const unsigned ARMEHFlavour0Dwarf2LSize;
13536
13537
extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[];
13538
extern const unsigned ARMDwarfFlavour0L2DwarfSize;
13539
13540
extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[];
13541
extern const unsigned ARMEHFlavour0L2DwarfSize;
13542
13543
ARMGenRegisterInfo::
13544
ARMGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
13545
      unsigned PC, unsigned HwMode)
13546
  : TargetRegisterInfo(ARMRegInfoDesc, RegisterClasses, RegisterClasses+102,
13547
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
13548
6.10k
             LaneBitmask(0xFFFFFFFF), RegClassInfos, HwMode) {
13549
6.10k
  InitMCRegisterInfo(ARMRegDesc, 289, RA, PC,
13550
6.10k
                     ARMMCRegisterClasses, 102,
13551
6.10k
                     ARMRegUnitRoots,
13552
6.10k
                     77,
13553
6.10k
                     ARMRegDiffLists,
13554
6.10k
                     ARMLaneMaskLists,
13555
6.10k
                     ARMRegStrings,
13556
6.10k
                     ARMRegClassStrings,
13557
6.10k
                     ARMSubRegIdxLists,
13558
6.10k
                     57,
13559
6.10k
                     ARMSubRegIdxRanges,
13560
6.10k
                     ARMRegEncodingTable);
13561
6.10k
13562
6.10k
  switch (DwarfFlavour) {
13563
0
  default:
13564
0
    llvm_unreachable("Unknown DWARF flavour");
13565
6.10k
  case 0:
13566
6.10k
    mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
13567
6.10k
    break;
13568
6.10k
  }
13569
6.10k
  switch (EHFlavour) {
13570
0
  default:
13571
0
    llvm_unreachable("Unknown DWARF flavour");
13572
6.10k
  case 0:
13573
6.10k
    mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
13574
6.10k
    break;
13575
6.10k
  }
13576
6.10k
  switch (DwarfFlavour) {
13577
0
  default:
13578
0
    llvm_unreachable("Unknown DWARF flavour");
13579
6.10k
  case 0:
13580
6.10k
    mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false);
13581
6.10k
    break;
13582
6.10k
  }
13583
6.10k
  switch (EHFlavour) {
13584
0
  default:
13585
0
    llvm_unreachable("Unknown DWARF flavour");
13586
6.10k
  case 0:
13587
6.10k
    mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true);
13588
6.10k
    break;
13589
6.10k
  }
13590
6.10k
}
13591
13592
static const MCPhysReg CSR_AAPCS_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13593
static const uint32_t CSR_AAPCS_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003fc0, 0x1f807fff, 0x000e0000, 0x3f00f001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13594
static const MCPhysReg CSR_AAPCS_SplitPush_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13595
static const uint32_t CSR_AAPCS_SplitPush_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003fc0, 0x1f807fff, 0x000e0000, 0x3f00f001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13596
static const MCPhysReg CSR_AAPCS_SplitPush_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13597
static const uint32_t CSR_AAPCS_SplitPush_SwiftError_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003bc0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13598
static const MCPhysReg CSR_AAPCS_SwiftError_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13599
static const uint32_t CSR_AAPCS_SwiftError_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003bc0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13600
static const MCPhysReg CSR_AAPCS_ThisReturn_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
13601
static const uint32_t CSR_AAPCS_ThisReturn_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003fc4, 0x1f807fff, 0x000e0000, 0x3f00f001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13602
static const MCPhysReg CSR_FIQ_SaveList[] = { ARM::LR, ARM::R11, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
13603
static const uint32_t CSR_FIQ_RegMask[] = { 0x00000400, 0x00000000, 0x000023fc, 0x00000000, 0x00000000, 0x00003c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13604
static const MCPhysReg CSR_FPRegs_SaveList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 0 };
13605
static const uint32_t CSR_FPRegs_RegMask[] = { 0xffffc000, 0xfffc3fff, 0xffff8003, 0xffffffff, 0xffffffff, 0xffff01ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
13606
static const MCPhysReg CSR_GenericInt_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
13607
static const uint32_t CSR_GenericInt_RegMask[] = { 0x00000400, 0x00000000, 0x00007ffc, 0x00000000, 0x00000000, 0x0000fc00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13608
static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
13609
static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13610
static const MCPhysReg CSR_iOS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13611
static const uint32_t CSR_iOS_RegMask[] = { 0x3fc00400, 0x03c00000, 0x800037c0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13612
static const MCPhysReg CSR_iOS_CXX_TLS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R12, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
13613
static const uint32_t CSR_iOS_CXX_TLS_RegMask[] = { 0xffffc400, 0xfffc3fff, 0xfffffffb, 0xffffffff, 0xffffffff, 0xfffff9ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
13614
static const MCPhysReg CSR_iOS_CXX_TLS_PE_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R7, ARM::R5, ARM::R4, 0 };
13615
static const uint32_t CSR_iOS_CXX_TLS_PE_RegMask[] = { 0x00000400, 0x00000000, 0x000062c0, 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13616
static const MCPhysReg CSR_iOS_CXX_TLS_ViaCopy_SaveList[] = { ARM::R6, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
13617
static const uint32_t CSR_iOS_CXX_TLS_ViaCopy_RegMask[] = { 0xffffc000, 0xfffc3fff, 0xffff9d3b, 0xffffffff, 0xffffffff, 0xffff49ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
13618
static const MCPhysReg CSR_iOS_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13619
static const uint32_t CSR_iOS_SwiftError_RegMask[] = { 0x3fc00400, 0x03c00000, 0x800033c0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13620
static const MCPhysReg CSR_iOS_TLSCall_SaveList[] = { ARM::LR, ARM::SP, ARM::R11, ARM::R10, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
13621
static const uint32_t CSR_iOS_TLSCall_RegMask[] = { 0xffffd400, 0xfffc3fff, 0xffffb7fb, 0xffffffff, 0xffffffff, 0xffffb9ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
13622
static const MCPhysReg CSR_iOS_ThisReturn_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
13623
static const uint32_t CSR_iOS_ThisReturn_RegMask[] = { 0x3fc00400, 0x03c00000, 0x800037c4, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13624
13625
13626
497
ArrayRef<const uint32_t *> ARMGenRegisterInfo::getRegMasks() const {
13627
497
  static const uint32_t *const Masks[] = {
13628
497
    CSR_AAPCS_RegMask,
13629
497
    CSR_AAPCS_SplitPush_RegMask,
13630
497
    CSR_AAPCS_SplitPush_SwiftError_RegMask,
13631
497
    CSR_AAPCS_SwiftError_RegMask,
13632
497
    CSR_AAPCS_ThisReturn_RegMask,
13633
497
    CSR_FIQ_RegMask,
13634
497
    CSR_FPRegs_RegMask,
13635
497
    CSR_GenericInt_RegMask,
13636
497
    CSR_NoRegs_RegMask,
13637
497
    CSR_iOS_RegMask,
13638
497
    CSR_iOS_CXX_TLS_RegMask,
13639
497
    CSR_iOS_CXX_TLS_PE_RegMask,
13640
497
    CSR_iOS_CXX_TLS_ViaCopy_RegMask,
13641
497
    CSR_iOS_SwiftError_RegMask,
13642
497
    CSR_iOS_TLSCall_RegMask,
13643
497
    CSR_iOS_ThisReturn_RegMask,
13644
497
  };
13645
497
  return makeArrayRef(Masks);
13646
497
}
13647
13648
155
ArrayRef<const char *> ARMGenRegisterInfo::getRegMaskNames() const {
13649
155
  static const char *const Names[] = {
13650
155
    "CSR_AAPCS",
13651
155
    "CSR_AAPCS_SplitPush",
13652
155
    "CSR_AAPCS_SplitPush_SwiftError",
13653
155
    "CSR_AAPCS_SwiftError",
13654
155
    "CSR_AAPCS_ThisReturn",
13655
155
    "CSR_FIQ",
13656
155
    "CSR_FPRegs",
13657
155
    "CSR_GenericInt",
13658
155
    "CSR_NoRegs",
13659
155
    "CSR_iOS",
13660
155
    "CSR_iOS_CXX_TLS",
13661
155
    "CSR_iOS_CXX_TLS_PE",
13662
155
    "CSR_iOS_CXX_TLS_ViaCopy",
13663
155
    "CSR_iOS_SwiftError",
13664
155
    "CSR_iOS_TLSCall",
13665
155
    "CSR_iOS_ThisReturn",
13666
155
  };
13667
155
  return makeArrayRef(Names);
13668
155
}
13669
13670
const ARMFrameLowering *
13671
3.75M
ARMGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
13672
3.75M
  return static_cast<const ARMFrameLowering *>(
13673
3.75M
      MF.getSubtarget().getFrameLowering());
13674
3.75M
}
13675
13676
} // end namespace llvm
13677
13678
#endif // GET_REGINFO_TARGET_DESC
13679