/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/clang-build/lib/Target/BPF/BPFGenRegisterInfo.inc
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1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Target Register Enum Values *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | |
10 | | #ifdef GET_REGINFO_ENUM |
11 | | #undef GET_REGINFO_ENUM |
12 | | |
13 | | namespace llvm { |
14 | | |
15 | | class MCRegisterClass; |
16 | | extern const MCRegisterClass BPFMCRegisterClasses[]; |
17 | | |
18 | | namespace BPF { |
19 | | enum { |
20 | | NoRegister, |
21 | | R0 = 1, |
22 | | R1 = 2, |
23 | | R2 = 3, |
24 | | R3 = 4, |
25 | | R4 = 5, |
26 | | R5 = 6, |
27 | | R6 = 7, |
28 | | R7 = 8, |
29 | | R8 = 9, |
30 | | R9 = 10, |
31 | | R10 = 11, |
32 | | R11 = 12, |
33 | | W0 = 13, |
34 | | W1 = 14, |
35 | | W2 = 15, |
36 | | W3 = 16, |
37 | | W4 = 17, |
38 | | W5 = 18, |
39 | | W6 = 19, |
40 | | W7 = 20, |
41 | | W8 = 21, |
42 | | W9 = 22, |
43 | | W10 = 23, |
44 | | W11 = 24, |
45 | | NUM_TARGET_REGS // 25 |
46 | | }; |
47 | | } // end namespace BPF |
48 | | |
49 | | // Register classes |
50 | | |
51 | | namespace BPF { |
52 | | enum { |
53 | | GPR32RegClassID = 0, |
54 | | GPRRegClassID = 1, |
55 | | |
56 | | }; |
57 | | } // end namespace BPF |
58 | | |
59 | | |
60 | | // Subregister indices |
61 | | |
62 | | namespace BPF { |
63 | | enum { |
64 | | NoSubRegister, |
65 | | sub_32, // 1 |
66 | | NUM_TARGET_SUBREGS |
67 | | }; |
68 | | } // end namespace BPF |
69 | | |
70 | | } // end namespace llvm |
71 | | |
72 | | #endif // GET_REGINFO_ENUM |
73 | | |
74 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
75 | | |* *| |
76 | | |* MC Register Information *| |
77 | | |* *| |
78 | | |* Automatically generated file, do not edit! *| |
79 | | |* *| |
80 | | \*===----------------------------------------------------------------------===*/ |
81 | | |
82 | | |
83 | | #ifdef GET_REGINFO_MC_DESC |
84 | | #undef GET_REGINFO_MC_DESC |
85 | | |
86 | | namespace llvm { |
87 | | |
88 | | extern const MCPhysReg BPFRegDiffLists[] = { |
89 | | /* 0 */ 12, 0, |
90 | | /* 2 */ 65523, 0, |
91 | | /* 4 */ 65524, 0, |
92 | | /* 6 */ 65535, 0, |
93 | | }; |
94 | | |
95 | | extern const LaneBitmask BPFLaneMaskLists[] = { |
96 | | /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(), |
97 | | /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(), |
98 | | }; |
99 | | |
100 | | extern const uint16_t BPFSubRegIdxLists[] = { |
101 | | /* 0 */ 1, 0, |
102 | | }; |
103 | | |
104 | | extern const MCRegisterInfo::SubRegCoveredBits BPFSubRegIdxRanges[] = { |
105 | | { 65535, 65535 }, |
106 | | { 0, 32 }, // sub_32 |
107 | | }; |
108 | | |
109 | | extern const char BPFRegStrings[] = { |
110 | | /* 0 */ 'R', '1', '0', 0, |
111 | | /* 4 */ 'W', '1', '0', 0, |
112 | | /* 8 */ 'R', '0', 0, |
113 | | /* 11 */ 'W', '0', 0, |
114 | | /* 14 */ 'R', '1', '1', 0, |
115 | | /* 18 */ 'W', '1', '1', 0, |
116 | | /* 22 */ 'R', '1', 0, |
117 | | /* 25 */ 'W', '1', 0, |
118 | | /* 28 */ 'R', '2', 0, |
119 | | /* 31 */ 'W', '2', 0, |
120 | | /* 34 */ 'R', '3', 0, |
121 | | /* 37 */ 'W', '3', 0, |
122 | | /* 40 */ 'R', '4', 0, |
123 | | /* 43 */ 'W', '4', 0, |
124 | | /* 46 */ 'R', '5', 0, |
125 | | /* 49 */ 'W', '5', 0, |
126 | | /* 52 */ 'R', '6', 0, |
127 | | /* 55 */ 'W', '6', 0, |
128 | | /* 58 */ 'R', '7', 0, |
129 | | /* 61 */ 'W', '7', 0, |
130 | | /* 64 */ 'R', '8', 0, |
131 | | /* 67 */ 'W', '8', 0, |
132 | | /* 70 */ 'R', '9', 0, |
133 | | /* 73 */ 'W', '9', 0, |
134 | | }; |
135 | | |
136 | | extern const MCRegisterDesc BPFRegDesc[] = { // Descriptors |
137 | | { 3, 0, 0, 0, 0, 0 }, |
138 | | { 8, 0, 1, 0, 97, 2 }, |
139 | | { 22, 0, 1, 0, 97, 2 }, |
140 | | { 28, 0, 1, 0, 97, 2 }, |
141 | | { 34, 0, 1, 0, 97, 2 }, |
142 | | { 40, 0, 1, 0, 97, 2 }, |
143 | | { 46, 0, 1, 0, 97, 2 }, |
144 | | { 52, 0, 1, 0, 97, 2 }, |
145 | | { 58, 0, 1, 0, 97, 2 }, |
146 | | { 64, 0, 1, 0, 97, 2 }, |
147 | | { 70, 0, 1, 0, 97, 2 }, |
148 | | { 0, 0, 1, 0, 97, 2 }, |
149 | | { 14, 0, 1, 0, 97, 2 }, |
150 | | { 11, 1, 4, 1, 33, 0 }, |
151 | | { 25, 1, 4, 1, 33, 0 }, |
152 | | { 31, 1, 4, 1, 33, 0 }, |
153 | | { 37, 1, 4, 1, 33, 0 }, |
154 | | { 43, 1, 4, 1, 33, 0 }, |
155 | | { 49, 1, 4, 1, 33, 0 }, |
156 | | { 55, 1, 4, 1, 33, 0 }, |
157 | | { 61, 1, 4, 1, 33, 0 }, |
158 | | { 67, 1, 4, 1, 33, 0 }, |
159 | | { 73, 1, 4, 1, 33, 0 }, |
160 | | { 4, 1, 4, 1, 33, 0 }, |
161 | | { 18, 1, 4, 1, 33, 0 }, |
162 | | }; |
163 | | |
164 | | extern const MCPhysReg BPFRegUnitRoots[][2] = { |
165 | | { BPF::W0 }, |
166 | | { BPF::W1 }, |
167 | | { BPF::W2 }, |
168 | | { BPF::W3 }, |
169 | | { BPF::W4 }, |
170 | | { BPF::W5 }, |
171 | | { BPF::W6 }, |
172 | | { BPF::W7 }, |
173 | | { BPF::W8 }, |
174 | | { BPF::W9 }, |
175 | | { BPF::W10 }, |
176 | | { BPF::W11 }, |
177 | | }; |
178 | | |
179 | | namespace { // Register classes... |
180 | | // GPR32 Register Class... |
181 | | const MCPhysReg GPR32[] = { |
182 | | BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5, BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W0, BPF::W11, BPF::W10, |
183 | | }; |
184 | | |
185 | | // GPR32 Bit set. |
186 | | const uint8_t GPR32Bits[] = { |
187 | | 0x00, 0xe0, 0xff, 0x01, |
188 | | }; |
189 | | |
190 | | // GPR Register Class... |
191 | | const MCPhysReg GPR[] = { |
192 | | BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R0, BPF::R11, BPF::R10, |
193 | | }; |
194 | | |
195 | | // GPR Bit set. |
196 | | const uint8_t GPRBits[] = { |
197 | | 0xfe, 0x1f, |
198 | | }; |
199 | | |
200 | | } // end anonymous namespace |
201 | | |
202 | | extern const char BPFRegClassStrings[] = { |
203 | | /* 0 */ 'G', 'P', 'R', '3', '2', 0, |
204 | | /* 6 */ 'G', 'P', 'R', 0, |
205 | | }; |
206 | | |
207 | | extern const MCRegisterClass BPFMCRegisterClasses[] = { |
208 | | { GPR32, GPR32Bits, 0, 12, sizeof(GPR32Bits), BPF::GPR32RegClassID, 4, 1, true }, |
209 | | { GPR, GPRBits, 6, 12, sizeof(GPRBits), BPF::GPRRegClassID, 8, 1, true }, |
210 | | }; |
211 | | |
212 | | // BPF Dwarf<->LLVM register mappings. |
213 | | extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[] = { |
214 | | { 0U, BPF::W0 }, |
215 | | { 1U, BPF::W1 }, |
216 | | { 2U, BPF::W2 }, |
217 | | { 3U, BPF::W3 }, |
218 | | { 4U, BPF::W4 }, |
219 | | { 5U, BPF::W5 }, |
220 | | { 6U, BPF::W6 }, |
221 | | { 7U, BPF::W7 }, |
222 | | { 8U, BPF::W8 }, |
223 | | { 9U, BPF::W9 }, |
224 | | { 10U, BPF::W10 }, |
225 | | { 11U, BPF::W11 }, |
226 | | }; |
227 | | extern const unsigned BPFDwarfFlavour0Dwarf2LSize = array_lengthof(BPFDwarfFlavour0Dwarf2L); |
228 | | |
229 | | extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[] = { |
230 | | { 0U, BPF::W0 }, |
231 | | { 1U, BPF::W1 }, |
232 | | { 2U, BPF::W2 }, |
233 | | { 3U, BPF::W3 }, |
234 | | { 4U, BPF::W4 }, |
235 | | { 5U, BPF::W5 }, |
236 | | { 6U, BPF::W6 }, |
237 | | { 7U, BPF::W7 }, |
238 | | { 8U, BPF::W8 }, |
239 | | { 9U, BPF::W9 }, |
240 | | { 10U, BPF::W10 }, |
241 | | { 11U, BPF::W11 }, |
242 | | }; |
243 | | extern const unsigned BPFEHFlavour0Dwarf2LSize = array_lengthof(BPFEHFlavour0Dwarf2L); |
244 | | |
245 | | extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[] = { |
246 | | { BPF::R0, 0U }, |
247 | | { BPF::R1, 1U }, |
248 | | { BPF::R2, 2U }, |
249 | | { BPF::R3, 3U }, |
250 | | { BPF::R4, 4U }, |
251 | | { BPF::R5, 5U }, |
252 | | { BPF::R6, 6U }, |
253 | | { BPF::R7, 7U }, |
254 | | { BPF::R8, 8U }, |
255 | | { BPF::R9, 9U }, |
256 | | { BPF::R10, 10U }, |
257 | | { BPF::R11, 11U }, |
258 | | { BPF::W0, 0U }, |
259 | | { BPF::W1, 1U }, |
260 | | { BPF::W2, 2U }, |
261 | | { BPF::W3, 3U }, |
262 | | { BPF::W4, 4U }, |
263 | | { BPF::W5, 5U }, |
264 | | { BPF::W6, 6U }, |
265 | | { BPF::W7, 7U }, |
266 | | { BPF::W8, 8U }, |
267 | | { BPF::W9, 9U }, |
268 | | { BPF::W10, 10U }, |
269 | | { BPF::W11, 11U }, |
270 | | }; |
271 | | extern const unsigned BPFDwarfFlavour0L2DwarfSize = array_lengthof(BPFDwarfFlavour0L2Dwarf); |
272 | | |
273 | | extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[] = { |
274 | | { BPF::R0, 0U }, |
275 | | { BPF::R1, 1U }, |
276 | | { BPF::R2, 2U }, |
277 | | { BPF::R3, 3U }, |
278 | | { BPF::R4, 4U }, |
279 | | { BPF::R5, 5U }, |
280 | | { BPF::R6, 6U }, |
281 | | { BPF::R7, 7U }, |
282 | | { BPF::R8, 8U }, |
283 | | { BPF::R9, 9U }, |
284 | | { BPF::R10, 10U }, |
285 | | { BPF::R11, 11U }, |
286 | | { BPF::W0, 0U }, |
287 | | { BPF::W1, 1U }, |
288 | | { BPF::W2, 2U }, |
289 | | { BPF::W3, 3U }, |
290 | | { BPF::W4, 4U }, |
291 | | { BPF::W5, 5U }, |
292 | | { BPF::W6, 6U }, |
293 | | { BPF::W7, 7U }, |
294 | | { BPF::W8, 8U }, |
295 | | { BPF::W9, 9U }, |
296 | | { BPF::W10, 10U }, |
297 | | { BPF::W11, 11U }, |
298 | | }; |
299 | | extern const unsigned BPFEHFlavour0L2DwarfSize = array_lengthof(BPFEHFlavour0L2Dwarf); |
300 | | |
301 | | extern const uint16_t BPFRegEncodingTable[] = { |
302 | | 0, |
303 | | 0, |
304 | | 1, |
305 | | 2, |
306 | | 3, |
307 | | 4, |
308 | | 5, |
309 | | 6, |
310 | | 7, |
311 | | 8, |
312 | | 9, |
313 | | 10, |
314 | | 11, |
315 | | 0, |
316 | | 1, |
317 | | 2, |
318 | | 3, |
319 | | 4, |
320 | | 5, |
321 | | 6, |
322 | | 7, |
323 | | 8, |
324 | | 9, |
325 | | 10, |
326 | | 11, |
327 | | }; |
328 | 61 | static inline void InitBPFMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
329 | 61 | RI->InitMCRegisterInfo(BPFRegDesc, 25, RA, PC, BPFMCRegisterClasses, 2, BPFRegUnitRoots, 12, BPFRegDiffLists, BPFLaneMaskLists, BPFRegStrings, BPFRegClassStrings, BPFSubRegIdxLists, 2, |
330 | 61 | BPFSubRegIdxRanges, BPFRegEncodingTable); |
331 | 61 | |
332 | 61 | switch (DwarfFlavour) { |
333 | 0 | default: |
334 | 0 | llvm_unreachable("Unknown DWARF flavour"); |
335 | 61 | case 0: |
336 | 61 | RI->mapDwarfRegsToLLVMRegs(BPFDwarfFlavour0Dwarf2L, BPFDwarfFlavour0Dwarf2LSize, false); |
337 | 61 | break; |
338 | 61 | } |
339 | 61 | switch (EHFlavour) { |
340 | 0 | default: |
341 | 0 | llvm_unreachable("Unknown DWARF flavour"); |
342 | 61 | case 0: |
343 | 61 | RI->mapDwarfRegsToLLVMRegs(BPFEHFlavour0Dwarf2L, BPFEHFlavour0Dwarf2LSize, true); |
344 | 61 | break; |
345 | 61 | } |
346 | 61 | switch (DwarfFlavour) { |
347 | 0 | default: |
348 | 0 | llvm_unreachable("Unknown DWARF flavour"); |
349 | 61 | case 0: |
350 | 61 | RI->mapLLVMRegsToDwarfRegs(BPFDwarfFlavour0L2Dwarf, BPFDwarfFlavour0L2DwarfSize, false); |
351 | 61 | break; |
352 | 61 | } |
353 | 61 | switch (EHFlavour) { |
354 | 0 | default: |
355 | 0 | llvm_unreachable("Unknown DWARF flavour"); |
356 | 61 | case 0: |
357 | 61 | RI->mapLLVMRegsToDwarfRegs(BPFEHFlavour0L2Dwarf, BPFEHFlavour0L2DwarfSize, true); |
358 | 61 | break; |
359 | 61 | } |
360 | 61 | } |
361 | | |
362 | | } // end namespace llvm |
363 | | |
364 | | #endif // GET_REGINFO_MC_DESC |
365 | | |
366 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
367 | | |* *| |
368 | | |* Register Information Header Fragment *| |
369 | | |* *| |
370 | | |* Automatically generated file, do not edit! *| |
371 | | |* *| |
372 | | \*===----------------------------------------------------------------------===*/ |
373 | | |
374 | | |
375 | | #ifdef GET_REGINFO_HEADER |
376 | | #undef GET_REGINFO_HEADER |
377 | | |
378 | | #include "llvm/Target/TargetRegisterInfo.h" |
379 | | |
380 | | namespace llvm { |
381 | | |
382 | | class BPFFrameLowering; |
383 | | |
384 | | struct BPFGenRegisterInfo : public TargetRegisterInfo { |
385 | | explicit BPFGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, |
386 | | unsigned PC = 0, unsigned HwMode = 0); |
387 | | unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; |
388 | | LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
389 | | LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
390 | | const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override; |
391 | | const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; |
392 | | unsigned getRegUnitWeight(unsigned RegUnit) const override; |
393 | | unsigned getNumRegPressureSets() const override; |
394 | | const char *getRegPressureSetName(unsigned Idx) const override; |
395 | | unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; |
396 | | const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; |
397 | | const int *getRegUnitPressureSets(unsigned RegUnit) const override; |
398 | | ArrayRef<const char *> getRegMaskNames() const override; |
399 | | ArrayRef<const uint32_t *> getRegMasks() const override; |
400 | | /// Devirtualized TargetFrameLowering. |
401 | | static const BPFFrameLowering *getFrameLowering( |
402 | | const MachineFunction &MF); |
403 | | }; |
404 | | |
405 | | namespace BPF { // Register classes |
406 | | extern const TargetRegisterClass GPR32RegClass; |
407 | | extern const TargetRegisterClass GPRRegClass; |
408 | | } // end namespace BPF |
409 | | |
410 | | } // end namespace llvm |
411 | | |
412 | | #endif // GET_REGINFO_HEADER |
413 | | |
414 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
415 | | |* *| |
416 | | |* Target Register and Register Classes Information *| |
417 | | |* *| |
418 | | |* Automatically generated file, do not edit! *| |
419 | | |* *| |
420 | | \*===----------------------------------------------------------------------===*/ |
421 | | |
422 | | |
423 | | #ifdef GET_REGINFO_TARGET_DESC |
424 | | #undef GET_REGINFO_TARGET_DESC |
425 | | |
426 | | namespace llvm { |
427 | | |
428 | | extern const MCRegisterClass BPFMCRegisterClasses[]; |
429 | | |
430 | | static const MVT::SimpleValueType VTLists[] = { |
431 | | /* 0 */ MVT::i32, MVT::Other, |
432 | | /* 2 */ MVT::i64, MVT::Other, |
433 | | }; |
434 | | |
435 | | static const char *const SubRegIndexNameTable[] = { "sub_32", "" }; |
436 | | |
437 | | |
438 | | static const LaneBitmask SubRegIndexLaneMaskTable[] = { |
439 | | LaneBitmask::getAll(), |
440 | | LaneBitmask(0x00000001), // sub_32 |
441 | | }; |
442 | | |
443 | | |
444 | | |
445 | | static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { |
446 | | // Mode = 0 (Default) |
447 | | { 32, 32, 32, VTLists+0 }, // GPR32 |
448 | | { 64, 64, 64, VTLists+2 }, // GPR |
449 | | }; |
450 | | |
451 | | static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; |
452 | | |
453 | | static const uint32_t GPR32SubClassMask[] = { |
454 | | 0x00000001, |
455 | | 0x00000002, // sub_32 |
456 | | }; |
457 | | |
458 | | static const uint32_t GPRSubClassMask[] = { |
459 | | 0x00000002, |
460 | | }; |
461 | | |
462 | | static const uint16_t SuperRegIdxSeqs[] = { |
463 | | /* 0 */ 1, 0, |
464 | | }; |
465 | | |
466 | | |
467 | | namespace BPF { // Register class instances |
468 | | extern const TargetRegisterClass GPR32RegClass = { |
469 | | &BPFMCRegisterClasses[GPR32RegClassID], |
470 | | GPR32SubClassMask, |
471 | | SuperRegIdxSeqs + 0, |
472 | | LaneBitmask(0x00000001), |
473 | | 0, |
474 | | false, /* HasDisjunctSubRegs */ |
475 | | false, /* CoveredBySubRegs */ |
476 | | NullRegClasses, |
477 | | nullptr |
478 | | }; |
479 | | |
480 | | extern const TargetRegisterClass GPRRegClass = { |
481 | | &BPFMCRegisterClasses[GPRRegClassID], |
482 | | GPRSubClassMask, |
483 | | SuperRegIdxSeqs + 1, |
484 | | LaneBitmask(0x00000001), |
485 | | 0, |
486 | | false, /* HasDisjunctSubRegs */ |
487 | | false, /* CoveredBySubRegs */ |
488 | | NullRegClasses, |
489 | | nullptr |
490 | | }; |
491 | | |
492 | | } // end namespace BPF |
493 | | |
494 | | namespace { |
495 | | const TargetRegisterClass* const RegisterClasses[] = { |
496 | | &BPF::GPR32RegClass, |
497 | | &BPF::GPRRegClass, |
498 | | }; |
499 | | } // end anonymous namespace |
500 | | |
501 | | static const TargetRegisterInfoDesc BPFRegInfoDesc[] = { // Extra Descriptors |
502 | | { 0, false }, |
503 | | { 0, true }, |
504 | | { 0, true }, |
505 | | { 0, true }, |
506 | | { 0, true }, |
507 | | { 0, true }, |
508 | | { 0, true }, |
509 | | { 0, true }, |
510 | | { 0, true }, |
511 | | { 0, true }, |
512 | | { 0, true }, |
513 | | { 0, true }, |
514 | | { 0, true }, |
515 | | { 0, true }, |
516 | | { 0, true }, |
517 | | { 0, true }, |
518 | | { 0, true }, |
519 | | { 0, true }, |
520 | | { 0, true }, |
521 | | { 0, true }, |
522 | | { 0, true }, |
523 | | { 0, true }, |
524 | | { 0, true }, |
525 | | { 0, true }, |
526 | | { 0, true }, |
527 | | }; |
528 | 0 | unsigned BPFGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { |
529 | 0 | static const uint8_t Rows[1][1] = { |
530 | 0 | { 0, }, |
531 | 0 | }; |
532 | 0 |
|
533 | 0 | --IdxA; assert(IdxA < 1); |
534 | 0 | --IdxB; assert(IdxB < 1); |
535 | 0 | return Rows[0][IdxB]; |
536 | 0 | } |
537 | | |
538 | | struct MaskRolOp { |
539 | | LaneBitmask Mask; |
540 | | uint8_t RotateLeft; |
541 | | }; |
542 | | static const MaskRolOp LaneMaskComposeSequences[] = { |
543 | | { LaneBitmask(0xFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0 |
544 | | }; |
545 | | static const MaskRolOp *const CompositeSequences[] = { |
546 | | &LaneMaskComposeSequences[0] // to sub_32 |
547 | | }; |
548 | | |
549 | 0 | LaneBitmask BPFGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
550 | 0 | --IdxA; assert(IdxA < 1 && "Subregister index out of bounds"); |
551 | 0 | LaneBitmask Result; |
552 | 0 | for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any()0 ; ++Ops0 ) { |
553 | 0 | LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); |
554 | 0 | if (unsigned S = Ops->RotateLeft) |
555 | 0 | Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); |
556 | 0 | else |
557 | 0 | Result |= LaneBitmask(M); |
558 | 0 | } |
559 | 0 | return Result; |
560 | 0 | } |
561 | | |
562 | 0 | LaneBitmask BPFGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
563 | 0 | LaneMask &= getSubRegIndexLaneMask(IdxA); |
564 | 0 | --IdxA; assert(IdxA < 1 && "Subregister index out of bounds"); |
565 | 0 | LaneBitmask Result; |
566 | 0 | for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any()0 ; ++Ops0 ) { |
567 | 0 | LaneBitmask::Type M = LaneMask.getAsInteger(); |
568 | 0 | if (unsigned S = Ops->RotateLeft) |
569 | 0 | Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); |
570 | 0 | else |
571 | 0 | Result |= LaneBitmask(M); |
572 | 0 | } |
573 | 0 | return Result; |
574 | 0 | } |
575 | | |
576 | 0 | const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { |
577 | 0 | static const uint8_t Table[2][1] = { |
578 | 0 | { // GPR32 |
579 | 0 | 0, // sub_32 |
580 | 0 | }, |
581 | 0 | { // GPR |
582 | 0 | 2, // sub_32 -> GPR |
583 | 0 | }, |
584 | 0 | }; |
585 | 0 | assert(RC && "Missing regclass"); |
586 | 0 | if (!Idx0 ) return RC0 ; |
587 | 0 | --Idx; |
588 | 0 | assert(Idx < 1 && "Bad subreg"); |
589 | 0 | unsigned TV = Table[RC->getID()][Idx]; |
590 | 0 | return TV ? getRegClass(TV - 1)0 : nullptr0 ; |
591 | 0 | } |
592 | | |
593 | | /// Get the weight in units of pressure for this register class. |
594 | | const RegClassWeight &BPFGenRegisterInfo:: |
595 | 145 | getRegClassWeight(const TargetRegisterClass *RC) const { |
596 | 145 | static const RegClassWeight RCWeightTable[] = { |
597 | 145 | {1, 12}, // GPR32 |
598 | 145 | {1, 12}, // GPR |
599 | 145 | }; |
600 | 145 | return RCWeightTable[RC->getID()]; |
601 | 145 | } |
602 | | |
603 | | /// Get the weight in units of pressure for this register unit. |
604 | | unsigned BPFGenRegisterInfo:: |
605 | 0 | getRegUnitWeight(unsigned RegUnit) const { |
606 | 0 | assert(RegUnit < 12 && "invalid register unit"); |
607 | 0 | // All register units have unit weight. |
608 | 0 | return 1; |
609 | 0 | } |
610 | | |
611 | | |
612 | | // Get the number of dimensions of register pressure. |
613 | 339 | unsigned BPFGenRegisterInfo::getNumRegPressureSets() const { |
614 | 339 | return 1; |
615 | 339 | } |
616 | | |
617 | | // Get the name of this register unit pressure set. |
618 | | const char *BPFGenRegisterInfo:: |
619 | 0 | getRegPressureSetName(unsigned Idx) const { |
620 | 0 | static const char *const PressureNameTable[] = { |
621 | 0 | "GPR32", |
622 | 0 | }; |
623 | 0 | return PressureNameTable[Idx]; |
624 | 0 | } |
625 | | |
626 | | // Get the register unit pressure limit for this dimension. |
627 | | // This limit must be adjusted dynamically for reserved registers. |
628 | | unsigned BPFGenRegisterInfo:: |
629 | 147 | getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { |
630 | 147 | static const uint8_t PressureLimitTable[] = { |
631 | 147 | 12, // 0: GPR32 |
632 | 147 | }; |
633 | 147 | return PressureLimitTable[Idx]; |
634 | 147 | } |
635 | | |
636 | | /// Table of pressure sets per register class or unit. |
637 | | static const int RCSetsTable[] = { |
638 | | /* 0 */ 0, -1, |
639 | | }; |
640 | | |
641 | | /// Get the dimensions of register pressure impacted by this register class. |
642 | | /// Returns a -1 terminated array of pressure set IDs |
643 | | const int* BPFGenRegisterInfo:: |
644 | 120 | getRegClassPressureSets(const TargetRegisterClass *RC) const { |
645 | 120 | static const uint8_t RCSetStartTable[] = { |
646 | 120 | 0,0,}; |
647 | 120 | return &RCSetsTable[RCSetStartTable[RC->getID()]]; |
648 | 120 | } |
649 | | |
650 | | /// Get the dimensions of register pressure impacted by this register unit. |
651 | | /// Returns a -1 terminated array of pressure set IDs |
652 | | const int* BPFGenRegisterInfo:: |
653 | 0 | getRegUnitPressureSets(unsigned RegUnit) const { |
654 | 0 | assert(RegUnit < 12 && "invalid register unit"); |
655 | 0 | static const uint8_t RUSetStartTable[] = { |
656 | 0 | 0,0,0,0,0,0,0,0,0,0,0,0,}; |
657 | 0 | return &RCSetsTable[RUSetStartTable[RegUnit]]; |
658 | 0 | } |
659 | | |
660 | | extern const MCRegisterDesc BPFRegDesc[]; |
661 | | extern const MCPhysReg BPFRegDiffLists[]; |
662 | | extern const LaneBitmask BPFLaneMaskLists[]; |
663 | | extern const char BPFRegStrings[]; |
664 | | extern const char BPFRegClassStrings[]; |
665 | | extern const MCPhysReg BPFRegUnitRoots[][2]; |
666 | | extern const uint16_t BPFSubRegIdxLists[]; |
667 | | extern const MCRegisterInfo::SubRegCoveredBits BPFSubRegIdxRanges[]; |
668 | | extern const uint16_t BPFRegEncodingTable[]; |
669 | | // BPF Dwarf<->LLVM register mappings. |
670 | | extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[]; |
671 | | extern const unsigned BPFDwarfFlavour0Dwarf2LSize; |
672 | | |
673 | | extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[]; |
674 | | extern const unsigned BPFEHFlavour0Dwarf2LSize; |
675 | | |
676 | | extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[]; |
677 | | extern const unsigned BPFDwarfFlavour0L2DwarfSize; |
678 | | |
679 | | extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[]; |
680 | | extern const unsigned BPFEHFlavour0L2DwarfSize; |
681 | | |
682 | | BPFGenRegisterInfo:: |
683 | | BPFGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, |
684 | | unsigned PC, unsigned HwMode) |
685 | | : TargetRegisterInfo(BPFRegInfoDesc, RegisterClasses, RegisterClasses+2, |
686 | | SubRegIndexNameTable, SubRegIndexLaneMaskTable, |
687 | 51 | LaneBitmask(0xFFFFFFFE), RegClassInfos, HwMode) { |
688 | 51 | InitMCRegisterInfo(BPFRegDesc, 25, RA, PC, |
689 | 51 | BPFMCRegisterClasses, 2, |
690 | 51 | BPFRegUnitRoots, |
691 | 51 | 12, |
692 | 51 | BPFRegDiffLists, |
693 | 51 | BPFLaneMaskLists, |
694 | 51 | BPFRegStrings, |
695 | 51 | BPFRegClassStrings, |
696 | 51 | BPFSubRegIdxLists, |
697 | 51 | 2, |
698 | 51 | BPFSubRegIdxRanges, |
699 | 51 | BPFRegEncodingTable); |
700 | 51 | |
701 | 51 | switch (DwarfFlavour) { |
702 | 0 | default: |
703 | 0 | llvm_unreachable("Unknown DWARF flavour"); |
704 | 51 | case 0: |
705 | 51 | mapDwarfRegsToLLVMRegs(BPFDwarfFlavour0Dwarf2L, BPFDwarfFlavour0Dwarf2LSize, false); |
706 | 51 | break; |
707 | 51 | } |
708 | 51 | switch (EHFlavour) { |
709 | 0 | default: |
710 | 0 | llvm_unreachable("Unknown DWARF flavour"); |
711 | 51 | case 0: |
712 | 51 | mapDwarfRegsToLLVMRegs(BPFEHFlavour0Dwarf2L, BPFEHFlavour0Dwarf2LSize, true); |
713 | 51 | break; |
714 | 51 | } |
715 | 51 | switch (DwarfFlavour) { |
716 | 0 | default: |
717 | 0 | llvm_unreachable("Unknown DWARF flavour"); |
718 | 51 | case 0: |
719 | 51 | mapLLVMRegsToDwarfRegs(BPFDwarfFlavour0L2Dwarf, BPFDwarfFlavour0L2DwarfSize, false); |
720 | 51 | break; |
721 | 51 | } |
722 | 51 | switch (EHFlavour) { |
723 | 0 | default: |
724 | 0 | llvm_unreachable("Unknown DWARF flavour"); |
725 | 51 | case 0: |
726 | 51 | mapLLVMRegsToDwarfRegs(BPFEHFlavour0L2Dwarf, BPFEHFlavour0L2DwarfSize, true); |
727 | 51 | break; |
728 | 51 | } |
729 | 51 | } |
730 | | |
731 | | static const MCPhysReg CSR_SaveList[] = { BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 }; |
732 | | static const uint32_t CSR_RegMask[] = { 0x00f80f80, }; |
733 | | |
734 | | |
735 | 0 | ArrayRef<const uint32_t *> BPFGenRegisterInfo::getRegMasks() const { |
736 | 0 | static const uint32_t *const Masks[] = { |
737 | 0 | CSR_RegMask, |
738 | 0 | }; |
739 | 0 | return makeArrayRef(Masks); |
740 | 0 | } |
741 | | |
742 | 0 | ArrayRef<const char *> BPFGenRegisterInfo::getRegMaskNames() const { |
743 | 0 | static const char *const Names[] = { |
744 | 0 | "CSR", |
745 | 0 | }; |
746 | 0 | return makeArrayRef(Names); |
747 | 0 | } |
748 | | |
749 | | const BPFFrameLowering * |
750 | 0 | BPFGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { |
751 | 0 | return static_cast<const BPFFrameLowering *>( |
752 | 0 | MF.getSubtarget().getFrameLowering()); |
753 | 0 | } |
754 | | |
755 | | } // end namespace llvm |
756 | | |
757 | | #endif // GET_REGINFO_TARGET_DESC |
758 | | |