Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/clang-build/lib/Target/X86/X86GenCallingConv.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Calling Convention Implementation Fragment                                 *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
10
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
11
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
12
static bool CC_X86(unsigned ValNo, MVT ValVT,
13
                   MVT LocVT, CCValAssign::LocInfo LocInfo,
14
                   ISD::ArgFlagsTy ArgFlags, CCState &State);
15
static bool CC_X86_32(unsigned ValNo, MVT ValVT,
16
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
17
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
18
static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
19
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
20
                        ISD::ArgFlagsTy ArgFlags, CCState &State);
21
static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
22
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
23
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
24
static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
25
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
26
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
27
static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
28
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
29
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
30
static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
31
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
32
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
33
static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
34
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
35
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
36
static bool CC_X86_32_Intr(unsigned ValNo, MVT ValVT,
37
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
38
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
39
static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
40
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
41
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
42
static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
43
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
44
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
45
static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
46
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
47
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
48
static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
49
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
50
                                      ISD::ArgFlagsTy ArgFlags, CCState &State);
51
static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
52
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
53
                                     ISD::ArgFlagsTy ArgFlags, CCState &State);
54
static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
55
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
56
                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
57
static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
58
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
59
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
60
static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
61
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
62
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
63
static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
64
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
65
                                      ISD::ArgFlagsTy ArgFlags, CCState &State);
66
static bool CC_X86_64(unsigned ValNo, MVT ValVT,
67
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
68
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
69
static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
70
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
71
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
72
static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
73
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
74
                        ISD::ArgFlagsTy ArgFlags, CCState &State);
75
static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
76
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
77
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
78
static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
79
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
80
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
81
static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
82
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
83
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
84
static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
85
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
86
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
87
static bool CC_X86_64_Intr(unsigned ValNo, MVT ValVT,
88
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
89
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
90
static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
91
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
92
                                ISD::ArgFlagsTy ArgFlags, CCState &State);
93
static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
94
                                  MVT LocVT, CCValAssign::LocInfo LocInfo,
95
                                  ISD::ArgFlagsTy ArgFlags, CCState &State);
96
static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
97
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
98
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
99
static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
100
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
101
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
102
static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
103
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
104
                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
105
static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
106
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
107
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
108
static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
109
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
110
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
111
static bool RetCC_X86(unsigned ValNo, MVT ValVT,
112
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
113
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
114
static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
115
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
116
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
117
static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
118
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
119
                         ISD::ArgFlagsTy ArgFlags, CCState &State);
120
static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
121
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
122
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
123
static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
124
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
125
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
126
static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
127
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
128
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
129
static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
130
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
131
                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
132
static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
133
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
134
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
135
static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
136
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
137
                         ISD::ArgFlagsTy ArgFlags, CCState &State);
138
static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
139
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
140
                                ISD::ArgFlagsTy ArgFlags, CCState &State);
141
static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
142
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
143
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
144
static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
145
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
146
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
147
static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
148
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
149
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
150
static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
151
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
152
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
153
static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
154
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
155
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
156
static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
157
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
158
                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
159
static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
160
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
161
                                     ISD::ArgFlagsTy ArgFlags, CCState &State);
162
static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
163
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
164
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
165
static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
166
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
167
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
168
169
170
static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
171
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
172
182
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
173
182
174
182
  if (
LocVT == MVT::i32182
) {
175
18
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()18
) {
176
2
      static const MCPhysReg RegList1[] = {
177
2
        X86::ECX, X86::EDX, X86::R8D, X86::R9D
178
2
      };
179
2
      if (unsigned 
Reg2
= State.AllocateReg(RegList1)) {
180
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
181
2
        return false;
182
2
      }
183
2
    }
184
18
  }
185
182
186
180
  
if (180
LocVT == MVT::i64180
) {
187
12
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()12
) {
188
6
      static const MCPhysReg RegList2[] = {
189
6
        X86::RCX, X86::RDX, X86::R8, X86::R9
190
6
      };
191
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList2)) {
192
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
193
6
        return false;
194
6
      }
195
6
    }
196
12
  }
197
180
198
174
  
if (174
LocVT == MVT::i32174
) {
199
16
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()16
) {
200
2
      static const MCPhysReg RegList3[] = {
201
2
        X86::EDI, X86::ESI, X86::EDX, X86::ECX
202
2
      };
203
2
      if (unsigned 
Reg2
= State.AllocateReg(RegList3)) {
204
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
205
2
        return false;
206
2
      }
207
2
    }
208
16
  }
209
174
210
172
  
if (172
LocVT == MVT::i64172
) {
211
6
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()6
) {
212
6
      static const MCPhysReg RegList4[] = {
213
6
        X86::RDI, X86::RSI, X86::RDX, X86::RCX
214
6
      };
215
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList4)) {
216
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
217
6
        return false;
218
6
      }
219
6
    }
220
6
  }
221
172
222
166
  
if (166
LocVT == MVT::i32166
) {
223
14
    unsigned Offset5 = State.AllocateStack(4, 4);
224
14
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
225
14
    return false;
226
14
  }
227
166
228
152
  
if (152
LocVT == MVT::f32 ||
229
152
      LocVT == MVT::f64 ||
230
152
      LocVT == MVT::v4i32 ||
231
152
      LocVT == MVT::v2i64 ||
232
152
      LocVT == MVT::v4f32 ||
233
152
      
LocVT == MVT::v2f6480
) {
234
72
    static const MCPhysReg RegList6[] = {
235
72
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
236
72
    };
237
72
    if (unsigned 
Reg72
= State.AllocateReg(RegList6)) {
238
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
239
60
      return false;
240
60
    }
241
72
  }
242
152
243
92
  
if (92
LocVT == MVT::v8f32 ||
244
60
      LocVT == MVT::v4f64 ||
245
60
      LocVT == MVT::v8i32 ||
246
92
      
LocVT == MVT::v4i6460
) {
247
32
    static const MCPhysReg RegList7[] = {
248
32
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
249
32
    };
250
32
    if (unsigned 
Reg32
= State.AllocateReg(RegList7)) {
251
32
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
252
32
      return false;
253
32
    }
254
32
  }
255
92
256
60
  
if (60
LocVT == MVT::v16f32 ||
257
32
      LocVT == MVT::v8f64 ||
258
32
      LocVT == MVT::v16i32 ||
259
60
      
LocVT == MVT::v8i6424
) {
260
36
    static const MCPhysReg RegList8[] = {
261
36
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
262
36
    };
263
36
    if (unsigned 
Reg36
= State.AllocateReg(RegList8)) {
264
36
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
265
36
      return false;
266
36
    }
267
36
  }
268
60
269
24
  
if (24
LocVT == MVT::v16i1 ||
270
24
      
LocVT == MVT::v8i112
) {
271
12
    if (unsigned 
Reg12
= State.AllocateReg(X86::K1)) {
272
12
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
273
12
      return false;
274
12
    }
275
12
  }
276
24
277
12
  
if (12
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()12
) {
278
4
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
279
4
      return false;
280
4
  }
281
12
282
8
  
if (8
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()8
) {
283
4
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
284
4
      return false;
285
4
  }
286
8
287
4
  
if (4
!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)4
)
288
4
    return false;
289
4
290
0
  return true;  // CC didn't match.
291
182
}
Unexecuted instantiation: X86CallLowering.cpp:CC_Intel_OCL_BI(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_Intel_OCL_BI(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_Intel_OCL_BI(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
172
182
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
173
182
174
182
  if (
LocVT == MVT::i32182
) {
175
18
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()18
) {
176
2
      static const MCPhysReg RegList1[] = {
177
2
        X86::ECX, X86::EDX, X86::R8D, X86::R9D
178
2
      };
179
2
      if (unsigned 
Reg2
= State.AllocateReg(RegList1)) {
180
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
181
2
        return false;
182
2
      }
183
2
    }
184
18
  }
185
182
186
180
  
if (180
LocVT == MVT::i64180
) {
187
12
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()12
) {
188
6
      static const MCPhysReg RegList2[] = {
189
6
        X86::RCX, X86::RDX, X86::R8, X86::R9
190
6
      };
191
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList2)) {
192
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
193
6
        return false;
194
6
      }
195
6
    }
196
12
  }
197
180
198
174
  
if (174
LocVT == MVT::i32174
) {
199
16
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()16
) {
200
2
      static const MCPhysReg RegList3[] = {
201
2
        X86::EDI, X86::ESI, X86::EDX, X86::ECX
202
2
      };
203
2
      if (unsigned 
Reg2
= State.AllocateReg(RegList3)) {
204
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
205
2
        return false;
206
2
      }
207
2
    }
208
16
  }
209
174
210
172
  
if (172
LocVT == MVT::i64172
) {
211
6
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()6
) {
212
6
      static const MCPhysReg RegList4[] = {
213
6
        X86::RDI, X86::RSI, X86::RDX, X86::RCX
214
6
      };
215
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList4)) {
216
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
217
6
        return false;
218
6
      }
219
6
    }
220
6
  }
221
172
222
166
  
if (166
LocVT == MVT::i32166
) {
223
14
    unsigned Offset5 = State.AllocateStack(4, 4);
224
14
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
225
14
    return false;
226
14
  }
227
166
228
152
  
if (152
LocVT == MVT::f32 ||
229
152
      LocVT == MVT::f64 ||
230
152
      LocVT == MVT::v4i32 ||
231
152
      LocVT == MVT::v2i64 ||
232
152
      LocVT == MVT::v4f32 ||
233
152
      
LocVT == MVT::v2f6480
) {
234
72
    static const MCPhysReg RegList6[] = {
235
72
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
236
72
    };
237
72
    if (unsigned 
Reg72
= State.AllocateReg(RegList6)) {
238
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
239
60
      return false;
240
60
    }
241
72
  }
242
152
243
92
  
if (92
LocVT == MVT::v8f32 ||
244
60
      LocVT == MVT::v4f64 ||
245
60
      LocVT == MVT::v8i32 ||
246
92
      
LocVT == MVT::v4i6460
) {
247
32
    static const MCPhysReg RegList7[] = {
248
32
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
249
32
    };
250
32
    if (unsigned 
Reg32
= State.AllocateReg(RegList7)) {
251
32
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
252
32
      return false;
253
32
    }
254
32
  }
255
92
256
60
  
if (60
LocVT == MVT::v16f32 ||
257
32
      LocVT == MVT::v8f64 ||
258
32
      LocVT == MVT::v16i32 ||
259
60
      
LocVT == MVT::v8i6424
) {
260
36
    static const MCPhysReg RegList8[] = {
261
36
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
262
36
    };
263
36
    if (unsigned 
Reg36
= State.AllocateReg(RegList8)) {
264
36
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
265
36
      return false;
266
36
    }
267
36
  }
268
60
269
24
  
if (24
LocVT == MVT::v16i1 ||
270
24
      
LocVT == MVT::v8i112
) {
271
12
    if (unsigned 
Reg12
= State.AllocateReg(X86::K1)) {
272
12
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
273
12
      return false;
274
12
    }
275
12
  }
276
24
277
12
  
if (12
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()12
) {
278
4
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
279
4
      return false;
280
4
  }
281
12
282
8
  
if (8
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()8
) {
283
4
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
284
4
      return false;
285
4
  }
286
8
287
4
  
if (4
!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)4
)
288
4
    return false;
289
4
290
0
  return true;  // CC didn't match.
291
182
}
292
293
294
static bool CC_X86(unsigned ValNo, MVT ValVT,
295
                   MVT LocVT, CCValAssign::LocInfo LocInfo,
296
212k
                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
297
212k
298
212k
  if (
State.getCallingConv() == CallingConv::Intel_OCL_BI212k
) {
299
182
    if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
300
182
      return false;
301
182
  }
302
212k
303
211k
  
if (211k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()211k
) {
304
154k
    if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
305
153k
      return false;
306
154k
  }
307
211k
308
57.9k
  
if (57.9k
!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)57.9k
)
309
57.9k
    return false;
310
57.9k
311
18.4E
  return true;  // CC didn't match.
312
212k
}
X86FastISel.cpp:CC_X86(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
296
908
                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
297
908
298
908
  if (
State.getCallingConv() == CallingConv::Intel_OCL_BI908
) {
299
0
    if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
300
0
      return false;
301
0
  }
302
908
303
908
  
if (908
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()908
) {
304
751
    if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
305
751
      return false;
306
751
  }
307
908
308
157
  
if (157
!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)157
)
309
157
    return false;
310
157
311
0
  return true;  // CC didn't match.
312
908
}
X86CallLowering.cpp:CC_X86(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
296
776
                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
297
776
298
776
  if (
State.getCallingConv() == CallingConv::Intel_OCL_BI776
) {
299
0
    if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
300
0
      return false;
301
0
  }
302
776
303
776
  
if (776
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()776
) {
304
584
    if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
305
584
      return false;
306
584
  }
307
776
308
192
  
if (192
!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)192
)
309
192
    return false;
310
192
311
0
  return true;  // CC didn't match.
312
776
}
X86ISelLowering.cpp:CC_X86(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
296
210k
                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
297
210k
298
210k
  if (
State.getCallingConv() == CallingConv::Intel_OCL_BI210k
) {
299
182
    if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
300
182
      return false;
301
182
  }
302
210k
303
210k
  
if (210k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()210k
) {
304
152k
    if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
305
152k
      return false;
306
152k
  }
307
210k
308
57.6k
  
if (57.6k
!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)57.6k
)
309
57.6k
    return false;
310
57.6k
311
18.4E
  return true;  // CC didn't match.
312
210k
}
313
314
315
static bool CC_X86_32(unsigned ValNo, MVT ValVT,
316
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
317
57.9k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
318
57.9k
319
57.9k
  if (
State.getCallingConv() == CallingConv::X86_INTR57.9k
) {
320
15
    if (!CC_X86_32_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
321
15
      return false;
322
15
  }
323
57.9k
324
57.9k
  
if (57.9k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()57.9k
) {
325
125
    if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
326
125
      return false;
327
125
  }
328
57.9k
329
57.8k
  
if (57.8k
State.getCallingConv() == CallingConv::X86_FastCall57.8k
) {
330
174
    if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
331
174
      return false;
332
174
  }
333
57.8k
334
57.6k
  
if (57.6k
State.getCallingConv() == CallingConv::X86_VectorCall57.6k
) {
335
240
    if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
336
240
      return false;
337
240
  }
338
57.6k
339
57.4k
  
if (57.4k
State.getCallingConv() == CallingConv::X86_ThisCall57.4k
) {
340
362
    if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
341
362
      return false;
342
362
  }
343
57.4k
344
57.0k
  
if (57.0k
State.getCallingConv() == CallingConv::Fast57.0k
) {
345
759
    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
346
759
      return false;
347
759
  }
348
57.0k
349
56.2k
  
if (56.2k
State.getCallingConv() == CallingConv::GHC56.2k
) {
350
20
    if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
351
20
      return false;
352
20
  }
353
56.2k
354
56.2k
  
if (56.2k
State.getCallingConv() == CallingConv::HiPE56.2k
) {
355
42
    if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
356
42
      return false;
357
42
  }
358
56.2k
359
56.2k
  
if (56.2k
State.getCallingConv() == CallingConv::X86_RegCall56.2k
) {
360
200
    if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
361
200
      return false;
362
200
  }
363
56.2k
364
56.0k
  
if (56.0k
!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)56.0k
)
365
56.0k
    return false;
366
56.0k
367
0
  return true;  // CC didn't match.
368
57.9k
}
X86ISelLowering.cpp:CC_X86_32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
317
57.6k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
318
57.6k
319
57.6k
  if (
State.getCallingConv() == CallingConv::X86_INTR57.6k
) {
320
15
    if (!CC_X86_32_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
321
15
      return false;
322
15
  }
323
57.6k
324
57.6k
  
if (57.6k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()57.6k
) {
325
125
    if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
326
125
      return false;
327
125
  }
328
57.6k
329
57.4k
  
if (57.4k
State.getCallingConv() == CallingConv::X86_FastCall57.4k
) {
330
174
    if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
331
174
      return false;
332
174
  }
333
57.4k
334
57.3k
  
if (57.3k
State.getCallingConv() == CallingConv::X86_VectorCall57.3k
) {
335
240
    if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
336
240
      return false;
337
240
  }
338
57.3k
339
57.0k
  
if (57.0k
State.getCallingConv() == CallingConv::X86_ThisCall57.0k
) {
340
334
    if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
341
334
      return false;
342
334
  }
343
57.0k
344
56.7k
  
if (56.7k
State.getCallingConv() == CallingConv::Fast56.7k
) {
345
755
    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
346
755
      return false;
347
755
  }
348
56.7k
349
55.9k
  
if (55.9k
State.getCallingConv() == CallingConv::GHC55.9k
) {
350
20
    if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
351
20
      return false;
352
20
  }
353
55.9k
354
55.9k
  
if (55.9k
State.getCallingConv() == CallingConv::HiPE55.9k
) {
355
42
    if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
356
42
      return false;
357
42
  }
358
55.9k
359
55.9k
  
if (55.9k
State.getCallingConv() == CallingConv::X86_RegCall55.9k
) {
360
200
    if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
361
200
      return false;
362
200
  }
363
55.9k
364
55.7k
  
if (55.7k
!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)55.7k
)
365
55.7k
    return false;
366
55.7k
367
0
  return true;  // CC didn't match.
368
57.6k
}
X86FastISel.cpp:CC_X86_32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
317
157
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
318
157
319
157
  if (
State.getCallingConv() == CallingConv::X86_INTR157
) {
320
0
    if (!CC_X86_32_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
321
0
      return false;
322
0
  }
323
157
324
157
  
if (157
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()157
) {
325
0
    if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
326
0
      return false;
327
0
  }
328
157
329
157
  
if (157
State.getCallingConv() == CallingConv::X86_FastCall157
) {
330
0
    if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
331
0
      return false;
332
0
  }
333
157
334
157
  
if (157
State.getCallingConv() == CallingConv::X86_VectorCall157
) {
335
0
    if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
336
0
      return false;
337
0
  }
338
157
339
157
  
if (157
State.getCallingConv() == CallingConv::X86_ThisCall157
) {
340
28
    if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
341
28
      return false;
342
28
  }
343
157
344
129
  
if (129
State.getCallingConv() == CallingConv::Fast129
) {
345
4
    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
346
4
      return false;
347
4
  }
348
129
349
125
  
if (125
State.getCallingConv() == CallingConv::GHC125
) {
350
0
    if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
351
0
      return false;
352
0
  }
353
125
354
125
  
if (125
State.getCallingConv() == CallingConv::HiPE125
) {
355
0
    if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
356
0
      return false;
357
0
  }
358
125
359
125
  
if (125
State.getCallingConv() == CallingConv::X86_RegCall125
) {
360
0
    if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
361
0
      return false;
362
0
  }
363
125
364
125
  
if (125
!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)125
)
365
125
    return false;
366
125
367
0
  return true;  // CC didn't match.
368
157
}
X86CallLowering.cpp:CC_X86_32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
317
192
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
318
192
319
192
  if (
State.getCallingConv() == CallingConv::X86_INTR192
) {
320
0
    if (!CC_X86_32_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
321
0
      return false;
322
0
  }
323
192
324
192
  
if (192
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()192
) {
325
0
    if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
326
0
      return false;
327
0
  }
328
192
329
192
  
if (192
State.getCallingConv() == CallingConv::X86_FastCall192
) {
330
0
    if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
331
0
      return false;
332
0
  }
333
192
334
192
  
if (192
State.getCallingConv() == CallingConv::X86_VectorCall192
) {
335
0
    if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
336
0
      return false;
337
0
  }
338
192
339
192
  
if (192
State.getCallingConv() == CallingConv::X86_ThisCall192
) {
340
0
    if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
341
0
      return false;
342
0
  }
343
192
344
192
  
if (192
State.getCallingConv() == CallingConv::Fast192
) {
345
0
    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
346
0
      return false;
347
0
  }
348
192
349
192
  
if (192
State.getCallingConv() == CallingConv::GHC192
) {
350
0
    if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
351
0
      return false;
352
0
  }
353
192
354
192
  
if (192
State.getCallingConv() == CallingConv::HiPE192
) {
355
0
    if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
356
0
      return false;
357
0
  }
358
192
359
192
  
if (192
State.getCallingConv() == CallingConv::X86_RegCall192
) {
360
0
    if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
361
0
      return false;
362
0
  }
363
192
364
192
  
if (192
!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)192
)
365
192
    return false;
366
192
367
0
  return true;  // CC didn't match.
368
192
}
369
370
371
static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
372
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
373
56.0k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
374
56.0k
375
56.0k
  if (LocVT == MVT::i1 ||
376
56.0k
      LocVT == MVT::i8 ||
377
53.8k
      LocVT == MVT::i16 ||
378
56.0k
      
LocVT == MVT::v1i153.0k
) {
379
3.00k
    LocVT = MVT::i32;
380
3.00k
    if (ArgFlags.isSExt())
381
87
        LocInfo = CCValAssign::SExt;
382
2.92k
    else 
if (2.92k
ArgFlags.isZExt()2.92k
)
383
669
        LocInfo = CCValAssign::ZExt;
384
2.92k
    else
385
2.25k
        LocInfo = CCValAssign::AExt;
386
3.00k
  }
387
56.0k
388
56.0k
  if (
ArgFlags.isNest()56.0k
) {
389
8
    if (unsigned 
Reg8
= State.AllocateReg(X86::ECX)) {
390
8
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
391
8
      return false;
392
8
    }
393
8
  }
394
56.0k
395
56.0k
  
if (56.0k
!State.isVarArg()56.0k
) {
396
53.0k
    if (
ArgFlags.isInReg()53.0k
) {
397
228
      if (
LocVT == MVT::i32228
) {
398
204
        static const MCPhysReg RegList1[] = {
399
204
          X86::EAX, X86::EDX, X86::ECX
400
204
        };
401
204
        if (unsigned 
Reg204
= State.AllocateReg(RegList1)) {
402
204
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
403
204
          return false;
404
204
        }
405
204
      }
406
228
    }
407
53.0k
  }
408
56.0k
409
55.8k
  
if (55.8k
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)55.8k
)
410
55.8k
    return false;
411
55.8k
412
0
  return true;  // CC didn't match.
413
56.0k
}
X86ISelLowering.cpp:CC_X86_32_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
373
55.7k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
374
55.7k
375
55.7k
  if (LocVT == MVT::i1 ||
376
55.7k
      LocVT == MVT::i8 ||
377
53.5k
      LocVT == MVT::i16 ||
378
55.7k
      
LocVT == MVT::v1i152.7k
) {
379
2.97k
    LocVT = MVT::i32;
380
2.97k
    if (ArgFlags.isSExt())
381
85
        LocInfo = CCValAssign::SExt;
382
2.89k
    else 
if (2.89k
ArgFlags.isZExt()2.89k
)
383
667
        LocInfo = CCValAssign::ZExt;
384
2.89k
    else
385
2.22k
        LocInfo = CCValAssign::AExt;
386
2.97k
  }
387
55.7k
388
55.7k
  if (
ArgFlags.isNest()55.7k
) {
389
8
    if (unsigned 
Reg8
= State.AllocateReg(X86::ECX)) {
390
8
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
391
8
      return false;
392
8
    }
393
8
  }
394
55.7k
395
55.7k
  
if (55.7k
!State.isVarArg()55.7k
) {
396
52.7k
    if (
ArgFlags.isInReg()52.7k
) {
397
219
      if (
LocVT == MVT::i32219
) {
398
195
        static const MCPhysReg RegList1[] = {
399
195
          X86::EAX, X86::EDX, X86::ECX
400
195
        };
401
195
        if (unsigned 
Reg195
= State.AllocateReg(RegList1)) {
402
195
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
403
195
          return false;
404
195
        }
405
195
      }
406
219
    }
407
52.7k
  }
408
55.7k
409
55.5k
  
if (55.5k
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)55.5k
)
410
55.5k
    return false;
411
55.5k
412
0
  return true;  // CC didn't match.
413
55.7k
}
X86FastISel.cpp:CC_X86_32_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
373
125
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
374
125
375
125
  if (LocVT == MVT::i1 ||
376
125
      LocVT == MVT::i8 ||
377
123
      LocVT == MVT::i16 ||
378
125
      
LocVT == MVT::v1i1123
) {
379
2
    LocVT = MVT::i32;
380
2
    if (ArgFlags.isSExt())
381
0
        LocInfo = CCValAssign::SExt;
382
2
    else 
if (2
ArgFlags.isZExt()2
)
383
0
        LocInfo = CCValAssign::ZExt;
384
2
    else
385
2
        LocInfo = CCValAssign::AExt;
386
2
  }
387
125
388
125
  if (
ArgFlags.isNest()125
) {
389
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::ECX)) {
390
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
391
0
      return false;
392
0
    }
393
0
  }
394
125
395
125
  
if (125
!State.isVarArg()125
) {
396
115
    if (
ArgFlags.isInReg()115
) {
397
9
      if (
LocVT == MVT::i329
) {
398
9
        static const MCPhysReg RegList1[] = {
399
9
          X86::EAX, X86::EDX, X86::ECX
400
9
        };
401
9
        if (unsigned 
Reg9
= State.AllocateReg(RegList1)) {
402
9
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
403
9
          return false;
404
9
        }
405
9
      }
406
9
    }
407
115
  }
408
125
409
116
  
if (116
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)116
)
410
116
    return false;
411
116
412
0
  return true;  // CC didn't match.
413
125
}
X86CallLowering.cpp:CC_X86_32_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
373
192
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
374
192
375
192
  if (LocVT == MVT::i1 ||
376
190
      LocVT == MVT::i8 ||
377
169
      LocVT == MVT::i16 ||
378
192
      
LocVT == MVT::v1i1162
) {
379
30
    LocVT = MVT::i32;
380
30
    if (ArgFlags.isSExt())
381
2
        LocInfo = CCValAssign::SExt;
382
28
    else 
if (28
ArgFlags.isZExt()28
)
383
2
        LocInfo = CCValAssign::ZExt;
384
28
    else
385
26
        LocInfo = CCValAssign::AExt;
386
30
  }
387
192
388
192
  if (
ArgFlags.isNest()192
) {
389
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::ECX)) {
390
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
391
0
      return false;
392
0
    }
393
0
  }
394
192
395
192
  
if (192
!State.isVarArg()192
) {
396
192
    if (
ArgFlags.isInReg()192
) {
397
0
      if (
LocVT == MVT::i320
) {
398
0
        static const MCPhysReg RegList1[] = {
399
0
          X86::EAX, X86::EDX, X86::ECX
400
0
        };
401
0
        if (unsigned 
Reg0
= State.AllocateReg(RegList1)) {
402
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
403
0
          return false;
404
0
        }
405
0
      }
406
0
    }
407
192
  }
408
192
409
192
  
if (192
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)192
)
410
192
    return false;
411
192
412
0
  return true;  // CC didn't match.
413
192
}
414
415
416
static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
417
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
418
56.3k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
419
56.3k
420
56.3k
  if (
ArgFlags.isByVal()56.3k
) {
421
149
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
422
149
    return false;
423
149
  }
424
56.3k
425
56.2k
  
if (56.2k
!State.isVarArg()56.2k
) {
426
53.2k
    if (
ArgFlags.isInReg()53.2k
) {
427
45
      if (LocVT == MVT::f32 ||
428
45
          
LocVT == MVT::f6441
) {
429
8
        if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()8
) {
430
0
          static const MCPhysReg RegList1[] = {
431
0
            X86::XMM0, X86::XMM1, X86::XMM2
432
0
          };
433
0
          if (unsigned 
Reg0
= State.AllocateReg(RegList1)) {
434
0
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
435
0
            return false;
436
0
          }
437
0
        }
438
8
      }
439
45
    }
440
53.2k
  }
441
56.2k
442
56.2k
  
if (56.2k
!State.isVarArg()56.2k
) {
443
53.2k
    if (
LocVT == MVT::x86mmx53.2k
) {
444
219
      static const MCPhysReg RegList2[] = {
445
219
        X86::MM0, X86::MM1, X86::MM2
446
219
      };
447
219
      if (unsigned 
Reg219
= State.AllocateReg(RegList2)) {
448
219
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
449
219
        return false;
450
219
      }
451
219
    }
452
53.2k
  }
453
56.2k
454
56.0k
  
if (56.0k
LocVT == MVT::i32 ||
455
56.0k
      
LocVT == MVT::f329.62k
) {
456
47.5k
    unsigned Offset3 = State.AllocateStack(4, 4);
457
47.5k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
458
47.5k
    return false;
459
47.5k
  }
460
56.0k
461
8.47k
  
if (8.47k
LocVT == MVT::f648.47k
) {
462
832
    unsigned Offset4 = State.AllocateStack(8, 4);
463
832
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
464
832
    return false;
465
832
  }
466
8.47k
467
7.64k
  
if (7.64k
LocVT == MVT::f807.64k
) {
468
226
    unsigned Offset5 = State.AllocateStack(
469
226
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4);
470
226
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
471
226
    return false;
472
226
  }
473
7.64k
474
7.41k
  
if (7.41k
LocVT == MVT::v2i17.41k
) {
475
7
    LocVT = MVT::v2i64;
476
7
    if (ArgFlags.isSExt())
477
0
        LocInfo = CCValAssign::SExt;
478
7
    else 
if (7
ArgFlags.isZExt()7
)
479
0
        LocInfo = CCValAssign::ZExt;
480
7
    else
481
7
        LocInfo = CCValAssign::AExt;
482
7
  }
483
7.41k
484
7.41k
  if (
LocVT == MVT::v4i17.41k
) {
485
7
    LocVT = MVT::v4i32;
486
7
    if (ArgFlags.isSExt())
487
0
        LocInfo = CCValAssign::SExt;
488
7
    else 
if (7
ArgFlags.isZExt()7
)
489
0
        LocInfo = CCValAssign::ZExt;
490
7
    else
491
7
        LocInfo = CCValAssign::AExt;
492
7
  }
493
7.41k
494
7.41k
  if (
LocVT == MVT::v8i17.41k
) {
495
11
    LocVT = MVT::v8i16;
496
11
    if (ArgFlags.isSExt())
497
0
        LocInfo = CCValAssign::SExt;
498
11
    else 
if (11
ArgFlags.isZExt()11
)
499
0
        LocInfo = CCValAssign::ZExt;
500
11
    else
501
11
        LocInfo = CCValAssign::AExt;
502
11
  }
503
7.41k
504
7.41k
  if (
LocVT == MVT::v16i17.41k
) {
505
25
    LocVT = MVT::v16i8;
506
25
    if (ArgFlags.isSExt())
507
0
        LocInfo = CCValAssign::SExt;
508
25
    else 
if (25
ArgFlags.isZExt()25
)
509
0
        LocInfo = CCValAssign::ZExt;
510
25
    else
511
25
        LocInfo = CCValAssign::AExt;
512
25
  }
513
7.41k
514
7.41k
  if (
LocVT == MVT::v32i17.41k
) {
515
3
    LocVT = MVT::v32i8;
516
3
    if (ArgFlags.isSExt())
517
0
        LocInfo = CCValAssign::SExt;
518
3
    else 
if (3
ArgFlags.isZExt()3
)
519
0
        LocInfo = CCValAssign::ZExt;
520
3
    else
521
3
        LocInfo = CCValAssign::AExt;
522
3
  }
523
7.41k
524
7.41k
  if (
LocVT == MVT::v64i17.41k
) {
525
0
    LocVT = MVT::v64i8;
526
0
    if (ArgFlags.isSExt())
527
0
        LocInfo = CCValAssign::SExt;
528
0
    else 
if (0
ArgFlags.isZExt()0
)
529
0
        LocInfo = CCValAssign::ZExt;
530
0
    else
531
0
        LocInfo = CCValAssign::AExt;
532
0
  }
533
7.41k
534
7.41k
  if (
LocVT == MVT::x86mmx7.41k
) {
535
0
    unsigned Offset6 = State.AllocateStack(8, 4);
536
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
537
0
    return false;
538
0
  }
539
7.41k
540
7.41k
  
if (7.41k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()7.41k
) {
541
2.14k
    if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
542
2.14k
      return false;
543
2.14k
  }
544
7.41k
545
5.27k
  
if (5.27k
!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)5.27k
)
546
5.27k
    return false;
547
5.27k
548
0
  return true;  // CC didn't match.
549
56.3k
}
X86CallLowering.cpp:CC_X86_32_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
418
192
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
419
192
420
192
  if (
ArgFlags.isByVal()192
) {
421
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
422
0
    return false;
423
0
  }
424
192
425
192
  
if (192
!State.isVarArg()192
) {
426
192
    if (
ArgFlags.isInReg()192
) {
427
0
      if (LocVT == MVT::f32 ||
428
0
          
LocVT == MVT::f640
) {
429
0
        if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()0
) {
430
0
          static const MCPhysReg RegList1[] = {
431
0
            X86::XMM0, X86::XMM1, X86::XMM2
432
0
          };
433
0
          if (unsigned 
Reg0
= State.AllocateReg(RegList1)) {
434
0
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
435
0
            return false;
436
0
          }
437
0
        }
438
0
      }
439
0
    }
440
192
  }
441
192
442
192
  
if (192
!State.isVarArg()192
) {
443
192
    if (
LocVT == MVT::x86mmx192
) {
444
0
      static const MCPhysReg RegList2[] = {
445
0
        X86::MM0, X86::MM1, X86::MM2
446
0
      };
447
0
      if (unsigned 
Reg0
= State.AllocateReg(RegList2)) {
448
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
449
0
        return false;
450
0
      }
451
0
    }
452
192
  }
453
192
454
192
  
if (192
LocVT == MVT::i32 ||
455
192
      
LocVT == MVT::f3230
) {
456
166
    unsigned Offset3 = State.AllocateStack(4, 4);
457
166
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
458
166
    return false;
459
166
  }
460
192
461
26
  
if (26
LocVT == MVT::f6426
) {
462
4
    unsigned Offset4 = State.AllocateStack(8, 4);
463
4
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
464
4
    return false;
465
4
  }
466
26
467
22
  
if (22
LocVT == MVT::f8022
) {
468
0
    unsigned Offset5 = State.AllocateStack(
469
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4);
470
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
471
0
    return false;
472
0
  }
473
22
474
22
  
if (22
LocVT == MVT::v2i122
) {
475
0
    LocVT = MVT::v2i64;
476
0
    if (ArgFlags.isSExt())
477
0
        LocInfo = CCValAssign::SExt;
478
0
    else 
if (0
ArgFlags.isZExt()0
)
479
0
        LocInfo = CCValAssign::ZExt;
480
0
    else
481
0
        LocInfo = CCValAssign::AExt;
482
0
  }
483
22
484
22
  if (
LocVT == MVT::v4i122
) {
485
0
    LocVT = MVT::v4i32;
486
0
    if (ArgFlags.isSExt())
487
0
        LocInfo = CCValAssign::SExt;
488
0
    else 
if (0
ArgFlags.isZExt()0
)
489
0
        LocInfo = CCValAssign::ZExt;
490
0
    else
491
0
        LocInfo = CCValAssign::AExt;
492
0
  }
493
22
494
22
  if (
LocVT == MVT::v8i122
) {
495
0
    LocVT = MVT::v8i16;
496
0
    if (ArgFlags.isSExt())
497
0
        LocInfo = CCValAssign::SExt;
498
0
    else 
if (0
ArgFlags.isZExt()0
)
499
0
        LocInfo = CCValAssign::ZExt;
500
0
    else
501
0
        LocInfo = CCValAssign::AExt;
502
0
  }
503
22
504
22
  if (
LocVT == MVT::v16i122
) {
505
0
    LocVT = MVT::v16i8;
506
0
    if (ArgFlags.isSExt())
507
0
        LocInfo = CCValAssign::SExt;
508
0
    else 
if (0
ArgFlags.isZExt()0
)
509
0
        LocInfo = CCValAssign::ZExt;
510
0
    else
511
0
        LocInfo = CCValAssign::AExt;
512
0
  }
513
22
514
22
  if (
LocVT == MVT::v32i122
) {
515
0
    LocVT = MVT::v32i8;
516
0
    if (ArgFlags.isSExt())
517
0
        LocInfo = CCValAssign::SExt;
518
0
    else 
if (0
ArgFlags.isZExt()0
)
519
0
        LocInfo = CCValAssign::ZExt;
520
0
    else
521
0
        LocInfo = CCValAssign::AExt;
522
0
  }
523
22
524
22
  if (
LocVT == MVT::v64i122
) {
525
0
    LocVT = MVT::v64i8;
526
0
    if (ArgFlags.isSExt())
527
0
        LocInfo = CCValAssign::SExt;
528
0
    else 
if (0
ArgFlags.isZExt()0
)
529
0
        LocInfo = CCValAssign::ZExt;
530
0
    else
531
0
        LocInfo = CCValAssign::AExt;
532
0
  }
533
22
534
22
  if (
LocVT == MVT::x86mmx22
) {
535
0
    unsigned Offset6 = State.AllocateStack(8, 4);
536
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
537
0
    return false;
538
0
  }
539
22
540
22
  
if (22
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()22
) {
541
0
    if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
542
0
      return false;
543
0
  }
544
22
545
22
  
if (22
!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)22
)
546
22
    return false;
547
22
548
0
  return true;  // CC didn't match.
549
192
}
X86ISelLowering.cpp:CC_X86_32_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
418
56.0k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
419
56.0k
420
56.0k
  if (
ArgFlags.isByVal()56.0k
) {
421
145
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
422
145
    return false;
423
145
  }
424
56.0k
425
55.9k
  
if (55.9k
!State.isVarArg()55.9k
) {
426
52.9k
    if (
ArgFlags.isInReg()52.9k
) {
427
45
      if (LocVT == MVT::f32 ||
428
45
          
LocVT == MVT::f6441
) {
429
8
        if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()8
) {
430
0
          static const MCPhysReg RegList1[] = {
431
0
            X86::XMM0, X86::XMM1, X86::XMM2
432
0
          };
433
0
          if (unsigned 
Reg0
= State.AllocateReg(RegList1)) {
434
0
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
435
0
            return false;
436
0
          }
437
0
        }
438
8
      }
439
45
    }
440
52.9k
  }
441
55.9k
442
55.9k
  
if (55.9k
!State.isVarArg()55.9k
) {
443
52.9k
    if (
LocVT == MVT::x86mmx52.9k
) {
444
219
      static const MCPhysReg RegList2[] = {
445
219
        X86::MM0, X86::MM1, X86::MM2
446
219
      };
447
219
      if (unsigned 
Reg219
= State.AllocateReg(RegList2)) {
448
219
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
449
219
        return false;
450
219
      }
451
219
    }
452
52.9k
  }
453
55.9k
454
55.7k
  
if (55.7k
LocVT == MVT::i32 ||
455
55.7k
      
LocVT == MVT::f329.58k
) {
456
47.2k
    unsigned Offset3 = State.AllocateStack(4, 4);
457
47.2k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
458
47.2k
    return false;
459
47.2k
  }
460
55.7k
461
8.44k
  
if (8.44k
LocVT == MVT::f648.44k
) {
462
828
    unsigned Offset4 = State.AllocateStack(8, 4);
463
828
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
464
828
    return false;
465
828
  }
466
8.44k
467
7.61k
  
if (7.61k
LocVT == MVT::f807.61k
) {
468
226
    unsigned Offset5 = State.AllocateStack(
469
226
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4);
470
226
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
471
226
    return false;
472
226
  }
473
7.61k
474
7.39k
  
if (7.39k
LocVT == MVT::v2i17.39k
) {
475
7
    LocVT = MVT::v2i64;
476
7
    if (ArgFlags.isSExt())
477
0
        LocInfo = CCValAssign::SExt;
478
7
    else 
if (7
ArgFlags.isZExt()7
)
479
0
        LocInfo = CCValAssign::ZExt;
480
7
    else
481
7
        LocInfo = CCValAssign::AExt;
482
7
  }
483
7.39k
484
7.39k
  if (
LocVT == MVT::v4i17.39k
) {
485
7
    LocVT = MVT::v4i32;
486
7
    if (ArgFlags.isSExt())
487
0
        LocInfo = CCValAssign::SExt;
488
7
    else 
if (7
ArgFlags.isZExt()7
)
489
0
        LocInfo = CCValAssign::ZExt;
490
7
    else
491
7
        LocInfo = CCValAssign::AExt;
492
7
  }
493
7.39k
494
7.39k
  if (
LocVT == MVT::v8i17.39k
) {
495
11
    LocVT = MVT::v8i16;
496
11
    if (ArgFlags.isSExt())
497
0
        LocInfo = CCValAssign::SExt;
498
11
    else 
if (11
ArgFlags.isZExt()11
)
499
0
        LocInfo = CCValAssign::ZExt;
500
11
    else
501
11
        LocInfo = CCValAssign::AExt;
502
11
  }
503
7.39k
504
7.39k
  if (
LocVT == MVT::v16i17.39k
) {
505
25
    LocVT = MVT::v16i8;
506
25
    if (ArgFlags.isSExt())
507
0
        LocInfo = CCValAssign::SExt;
508
25
    else 
if (25
ArgFlags.isZExt()25
)
509
0
        LocInfo = CCValAssign::ZExt;
510
25
    else
511
25
        LocInfo = CCValAssign::AExt;
512
25
  }
513
7.39k
514
7.39k
  if (
LocVT == MVT::v32i17.39k
) {
515
3
    LocVT = MVT::v32i8;
516
3
    if (ArgFlags.isSExt())
517
0
        LocInfo = CCValAssign::SExt;
518
3
    else 
if (3
ArgFlags.isZExt()3
)
519
0
        LocInfo = CCValAssign::ZExt;
520
3
    else
521
3
        LocInfo = CCValAssign::AExt;
522
3
  }
523
7.39k
524
7.39k
  if (
LocVT == MVT::v64i17.39k
) {
525
0
    LocVT = MVT::v64i8;
526
0
    if (ArgFlags.isSExt())
527
0
        LocInfo = CCValAssign::SExt;
528
0
    else 
if (0
ArgFlags.isZExt()0
)
529
0
        LocInfo = CCValAssign::ZExt;
530
0
    else
531
0
        LocInfo = CCValAssign::AExt;
532
0
  }
533
7.39k
534
7.39k
  if (
LocVT == MVT::x86mmx7.39k
) {
535
0
    unsigned Offset6 = State.AllocateStack(8, 4);
536
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
537
0
    return false;
538
0
  }
539
7.39k
540
7.39k
  
if (7.39k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()7.39k
) {
541
2.13k
    if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
542
2.13k
      return false;
543
2.13k
  }
544
7.39k
545
5.25k
  
if (5.25k
!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)5.25k
)
546
5.25k
    return false;
547
5.25k
548
0
  return true;  // CC didn't match.
549
56.0k
}
X86FastISel.cpp:CC_X86_32_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
418
124
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
419
124
420
124
  if (
ArgFlags.isByVal()124
) {
421
4
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
422
4
    return false;
423
4
  }
424
124
425
120
  
if (120
!State.isVarArg()120
) {
426
112
    if (
ArgFlags.isInReg()112
) {
427
0
      if (LocVT == MVT::f32 ||
428
0
          
LocVT == MVT::f640
) {
429
0
        if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()0
) {
430
0
          static const MCPhysReg RegList1[] = {
431
0
            X86::XMM0, X86::XMM1, X86::XMM2
432
0
          };
433
0
          if (unsigned 
Reg0
= State.AllocateReg(RegList1)) {
434
0
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
435
0
            return false;
436
0
          }
437
0
        }
438
0
      }
439
0
    }
440
112
  }
441
120
442
120
  
if (120
!State.isVarArg()120
) {
443
112
    if (
LocVT == MVT::x86mmx112
) {
444
0
      static const MCPhysReg RegList2[] = {
445
0
        X86::MM0, X86::MM1, X86::MM2
446
0
      };
447
0
      if (unsigned 
Reg0
= State.AllocateReg(RegList2)) {
448
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
449
0
        return false;
450
0
      }
451
0
    }
452
112
  }
453
120
454
120
  
if (120
LocVT == MVT::i32 ||
455
120
      
LocVT == MVT::f325
) {
456
115
    unsigned Offset3 = State.AllocateStack(4, 4);
457
115
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
458
115
    return false;
459
115
  }
460
120
461
5
  
if (5
LocVT == MVT::f645
) {
462
0
    unsigned Offset4 = State.AllocateStack(8, 4);
463
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
464
0
    return false;
465
0
  }
466
5
467
5
  
if (5
LocVT == MVT::f805
) {
468
0
    unsigned Offset5 = State.AllocateStack(
469
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4);
470
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
471
0
    return false;
472
0
  }
473
5
474
5
  
if (5
LocVT == MVT::v2i15
) {
475
0
    LocVT = MVT::v2i64;
476
0
    if (ArgFlags.isSExt())
477
0
        LocInfo = CCValAssign::SExt;
478
0
    else 
if (0
ArgFlags.isZExt()0
)
479
0
        LocInfo = CCValAssign::ZExt;
480
0
    else
481
0
        LocInfo = CCValAssign::AExt;
482
0
  }
483
5
484
5
  if (
LocVT == MVT::v4i15
) {
485
0
    LocVT = MVT::v4i32;
486
0
    if (ArgFlags.isSExt())
487
0
        LocInfo = CCValAssign::SExt;
488
0
    else 
if (0
ArgFlags.isZExt()0
)
489
0
        LocInfo = CCValAssign::ZExt;
490
0
    else
491
0
        LocInfo = CCValAssign::AExt;
492
0
  }
493
5
494
5
  if (
LocVT == MVT::v8i15
) {
495
0
    LocVT = MVT::v8i16;
496
0
    if (ArgFlags.isSExt())
497
0
        LocInfo = CCValAssign::SExt;
498
0
    else 
if (0
ArgFlags.isZExt()0
)
499
0
        LocInfo = CCValAssign::ZExt;
500
0
    else
501
0
        LocInfo = CCValAssign::AExt;
502
0
  }
503
5
504
5
  if (
LocVT == MVT::v16i15
) {
505
0
    LocVT = MVT::v16i8;
506
0
    if (ArgFlags.isSExt())
507
0
        LocInfo = CCValAssign::SExt;
508
0
    else 
if (0
ArgFlags.isZExt()0
)
509
0
        LocInfo = CCValAssign::ZExt;
510
0
    else
511
0
        LocInfo = CCValAssign::AExt;
512
0
  }
513
5
514
5
  if (
LocVT == MVT::v32i15
) {
515
0
    LocVT = MVT::v32i8;
516
0
    if (ArgFlags.isSExt())
517
0
        LocInfo = CCValAssign::SExt;
518
0
    else 
if (0
ArgFlags.isZExt()0
)
519
0
        LocInfo = CCValAssign::ZExt;
520
0
    else
521
0
        LocInfo = CCValAssign::AExt;
522
0
  }
523
5
524
5
  if (
LocVT == MVT::v64i15
) {
525
0
    LocVT = MVT::v64i8;
526
0
    if (ArgFlags.isSExt())
527
0
        LocInfo = CCValAssign::SExt;
528
0
    else 
if (0
ArgFlags.isZExt()0
)
529
0
        LocInfo = CCValAssign::ZExt;
530
0
    else
531
0
        LocInfo = CCValAssign::AExt;
532
0
  }
533
5
534
5
  if (
LocVT == MVT::x86mmx5
) {
535
0
    unsigned Offset6 = State.AllocateStack(8, 4);
536
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
537
0
    return false;
538
0
  }
539
5
540
5
  
if (5
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()5
) {
541
5
    if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
542
5
      return false;
543
5
  }
544
5
545
0
  
if (0
!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)0
)
546
0
    return false;
547
0
548
0
  return true;  // CC didn't match.
549
124
}
550
551
552
static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
553
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
554
759
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
555
759
556
759
  if (
ArgFlags.isByVal()759
) {
557
7
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
558
7
    return false;
559
7
  }
560
759
561
752
  
if (752
LocVT == MVT::i1 ||
562
752
      LocVT == MVT::i8 ||
563
651
      LocVT == MVT::i16 ||
564
752
      
LocVT == MVT::v1i1650
) {
565
102
    LocVT = MVT::i32;
566
102
    if (ArgFlags.isSExt())
567
5
        LocInfo = CCValAssign::SExt;
568
97
    else 
if (97
ArgFlags.isZExt()97
)
569
95
        LocInfo = CCValAssign::ZExt;
570
97
    else
571
2
        LocInfo = CCValAssign::AExt;
572
102
  }
573
752
574
752
  if (
ArgFlags.isNest()752
) {
575
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::EAX)) {
576
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
577
0
      return false;
578
0
    }
579
0
  }
580
752
581
752
  
if (752
LocVT == MVT::i32752
) {
582
725
    static const MCPhysReg RegList1[] = {
583
725
      X86::ECX, X86::EDX
584
725
    };
585
725
    if (unsigned 
Reg725
= State.AllocateReg(RegList1)) {
586
404
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
587
404
      return false;
588
404
    }
589
725
  }
590
752
591
348
  
if (348
!State.isVarArg()348
) {
592
348
    if (LocVT == MVT::f32 ||
593
348
        
LocVT == MVT::f64344
) {
594
18
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()18
) {
595
8
        static const MCPhysReg RegList2[] = {
596
8
          X86::XMM0, X86::XMM1, X86::XMM2
597
8
        };
598
8
        if (unsigned 
Reg8
= State.AllocateReg(RegList2)) {
599
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
600
6
          return false;
601
6
        }
602
8
      }
603
18
    }
604
348
  }
605
348
606
342
  
if (342
LocVT == MVT::f64342
) {
607
9
    unsigned Offset3 = State.AllocateStack(8, 8);
608
9
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
609
9
    return false;
610
9
  }
611
342
612
333
  
if (333
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)333
)
613
333
    return false;
614
333
615
0
  return true;  // CC didn't match.
616
759
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86FastISel.cpp:CC_X86_32_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
554
4
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
555
4
556
4
  if (
ArgFlags.isByVal()4
) {
557
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
558
0
    return false;
559
0
  }
560
4
561
4
  
if (4
LocVT == MVT::i1 ||
562
4
      LocVT == MVT::i8 ||
563
4
      LocVT == MVT::i16 ||
564
4
      
LocVT == MVT::v1i14
) {
565
0
    LocVT = MVT::i32;
566
0
    if (ArgFlags.isSExt())
567
0
        LocInfo = CCValAssign::SExt;
568
0
    else 
if (0
ArgFlags.isZExt()0
)
569
0
        LocInfo = CCValAssign::ZExt;
570
0
    else
571
0
        LocInfo = CCValAssign::AExt;
572
0
  }
573
4
574
4
  if (
ArgFlags.isNest()4
) {
575
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::EAX)) {
576
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
577
0
      return false;
578
0
    }
579
0
  }
580
4
581
4
  
if (4
LocVT == MVT::i324
) {
582
4
    static const MCPhysReg RegList1[] = {
583
4
      X86::ECX, X86::EDX
584
4
    };
585
4
    if (unsigned 
Reg4
= State.AllocateReg(RegList1)) {
586
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
587
4
      return false;
588
4
    }
589
4
  }
590
4
591
0
  
if (0
!State.isVarArg()0
) {
592
0
    if (LocVT == MVT::f32 ||
593
0
        
LocVT == MVT::f640
) {
594
0
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()0
) {
595
0
        static const MCPhysReg RegList2[] = {
596
0
          X86::XMM0, X86::XMM1, X86::XMM2
597
0
        };
598
0
        if (unsigned 
Reg0
= State.AllocateReg(RegList2)) {
599
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
600
0
          return false;
601
0
        }
602
0
      }
603
0
    }
604
0
  }
605
0
606
0
  
if (0
LocVT == MVT::f640
) {
607
0
    unsigned Offset3 = State.AllocateStack(8, 8);
608
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
609
0
    return false;
610
0
  }
611
0
612
0
  
if (0
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)0
)
613
0
    return false;
614
0
615
0
  return true;  // CC didn't match.
616
4
}
X86ISelLowering.cpp:CC_X86_32_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
554
755
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
555
755
556
755
  if (
ArgFlags.isByVal()755
) {
557
7
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
558
7
    return false;
559
7
  }
560
755
561
748
  
if (748
LocVT == MVT::i1 ||
562
748
      LocVT == MVT::i8 ||
563
647
      LocVT == MVT::i16 ||
564
748
      
LocVT == MVT::v1i1646
) {
565
102
    LocVT = MVT::i32;
566
102
    if (ArgFlags.isSExt())
567
5
        LocInfo = CCValAssign::SExt;
568
97
    else 
if (97
ArgFlags.isZExt()97
)
569
95
        LocInfo = CCValAssign::ZExt;
570
97
    else
571
2
        LocInfo = CCValAssign::AExt;
572
102
  }
573
748
574
748
  if (
ArgFlags.isNest()748
) {
575
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::EAX)) {
576
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
577
0
      return false;
578
0
    }
579
0
  }
580
748
581
748
  
if (748
LocVT == MVT::i32748
) {
582
721
    static const MCPhysReg RegList1[] = {
583
721
      X86::ECX, X86::EDX
584
721
    };
585
721
    if (unsigned 
Reg721
= State.AllocateReg(RegList1)) {
586
400
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
587
400
      return false;
588
400
    }
589
721
  }
590
748
591
348
  
if (348
!State.isVarArg()348
) {
592
348
    if (LocVT == MVT::f32 ||
593
348
        
LocVT == MVT::f64344
) {
594
18
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()18
) {
595
8
        static const MCPhysReg RegList2[] = {
596
8
          X86::XMM0, X86::XMM1, X86::XMM2
597
8
        };
598
8
        if (unsigned 
Reg8
= State.AllocateReg(RegList2)) {
599
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
600
6
          return false;
601
6
        }
602
8
      }
603
18
    }
604
348
  }
605
348
606
342
  
if (342
LocVT == MVT::f64342
) {
607
9
    unsigned Offset3 = State.AllocateStack(8, 8);
608
9
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
609
9
    return false;
610
9
  }
611
342
612
333
  
if (333
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)333
)
613
333
    return false;
614
333
615
0
  return true;  // CC didn't match.
616
755
}
617
618
619
static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
620
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
621
232
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
622
232
623
232
  if (LocVT == MVT::i1 ||
624
232
      LocVT == MVT::i8 ||
625
228
      LocVT == MVT::i16 ||
626
232
      
LocVT == MVT::v1i1226
) {
627
6
    LocVT = MVT::i32;
628
6
    if (ArgFlags.isSExt())
629
0
        LocInfo = CCValAssign::SExt;
630
6
    else 
if (6
ArgFlags.isZExt()6
)
631
0
        LocInfo = CCValAssign::ZExt;
632
6
    else
633
6
        LocInfo = CCValAssign::AExt;
634
6
  }
635
232
636
232
  if (
ArgFlags.isNest()232
) {
637
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::EAX)) {
638
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
639
0
      return false;
640
0
    }
641
0
  }
642
232
643
232
  
if (232
ArgFlags.isInReg()232
) {
644
176
    if (
LocVT == MVT::i32176
) {
645
161
      static const MCPhysReg RegList1[] = {
646
161
        X86::ECX, X86::EDX
647
161
      };
648
161
      if (unsigned 
Reg161
= State.AllocateReg(RegList1)) {
649
155
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
650
155
        return false;
651
155
      }
652
161
    }
653
176
  }
654
232
655
77
  
if (77
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)77
)
656
77
    return false;
657
77
658
0
  return true;  // CC didn't match.
659
232
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_FastCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_FastCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_32_FastCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
621
232
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
622
232
623
232
  if (LocVT == MVT::i1 ||
624
232
      LocVT == MVT::i8 ||
625
228
      LocVT == MVT::i16 ||
626
232
      
LocVT == MVT::v1i1226
) {
627
6
    LocVT = MVT::i32;
628
6
    if (ArgFlags.isSExt())
629
0
        LocInfo = CCValAssign::SExt;
630
6
    else 
if (6
ArgFlags.isZExt()6
)
631
0
        LocInfo = CCValAssign::ZExt;
632
6
    else
633
6
        LocInfo = CCValAssign::AExt;
634
6
  }
635
232
636
232
  if (
ArgFlags.isNest()232
) {
637
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::EAX)) {
638
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
639
0
      return false;
640
0
    }
641
0
  }
642
232
643
232
  
if (232
ArgFlags.isInReg()232
) {
644
176
    if (
LocVT == MVT::i32176
) {
645
161
      static const MCPhysReg RegList1[] = {
646
161
        X86::ECX, X86::EDX
647
161
      };
648
161
      if (unsigned 
Reg161
= State.AllocateReg(RegList1)) {
649
155
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
650
155
        return false;
651
155
      }
652
161
    }
653
176
  }
654
232
655
77
  
if (77
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)77
)
656
77
    return false;
657
77
658
0
  return true;  // CC didn't match.
659
232
}
660
661
662
static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
663
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
664
20
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
665
20
666
20
  if (LocVT == MVT::i8 ||
667
20
      
LocVT == MVT::i1620
) {
668
0
    LocVT = MVT::i32;
669
0
    if (ArgFlags.isSExt())
670
0
        LocInfo = CCValAssign::SExt;
671
0
    else 
if (0
ArgFlags.isZExt()0
)
672
0
        LocInfo = CCValAssign::ZExt;
673
0
    else
674
0
        LocInfo = CCValAssign::AExt;
675
0
  }
676
20
677
20
  if (
LocVT == MVT::i3220
) {
678
20
    static const MCPhysReg RegList1[] = {
679
20
      X86::EBX, X86::EBP, X86::EDI, X86::ESI
680
20
    };
681
20
    if (unsigned 
Reg20
= State.AllocateReg(RegList1)) {
682
20
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
683
20
      return false;
684
20
    }
685
20
  }
686
20
687
0
  return true;  // CC didn't match.
688
20
}
X86ISelLowering.cpp:CC_X86_32_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
664
20
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
665
20
666
20
  if (LocVT == MVT::i8 ||
667
20
      
LocVT == MVT::i1620
) {
668
0
    LocVT = MVT::i32;
669
0
    if (ArgFlags.isSExt())
670
0
        LocInfo = CCValAssign::SExt;
671
0
    else 
if (0
ArgFlags.isZExt()0
)
672
0
        LocInfo = CCValAssign::ZExt;
673
0
    else
674
0
        LocInfo = CCValAssign::AExt;
675
0
  }
676
20
677
20
  if (
LocVT == MVT::i3220
) {
678
20
    static const MCPhysReg RegList1[] = {
679
20
      X86::EBX, X86::EBP, X86::EDI, X86::ESI
680
20
    };
681
20
    if (unsigned 
Reg20
= State.AllocateReg(RegList1)) {
682
20
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
683
20
      return false;
684
20
    }
685
20
  }
686
20
687
0
  return true;  // CC didn't match.
688
20
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
689
690
691
static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
692
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
693
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
694
42
695
42
  if (LocVT == MVT::i8 ||
696
42
      
LocVT == MVT::i1642
) {
697
0
    LocVT = MVT::i32;
698
0
    if (ArgFlags.isSExt())
699
0
        LocInfo = CCValAssign::SExt;
700
0
    else 
if (0
ArgFlags.isZExt()0
)
701
0
        LocInfo = CCValAssign::ZExt;
702
0
    else
703
0
        LocInfo = CCValAssign::AExt;
704
0
  }
705
42
706
42
  if (
LocVT == MVT::i3242
) {
707
42
    static const MCPhysReg RegList1[] = {
708
42
      X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
709
42
    };
710
42
    if (unsigned 
Reg42
= State.AllocateReg(RegList1)) {
711
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
712
41
      return false;
713
41
    }
714
42
  }
715
42
716
1
  
if (1
LocVT == MVT::i32 ||
717
1
      
LocVT == MVT::f320
) {
718
1
    unsigned Offset2 = State.AllocateStack(4, 4);
719
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
720
1
    return false;
721
1
  }
722
1
723
0
  return true;  // CC didn't match.
724
42
}
X86ISelLowering.cpp:CC_X86_32_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
693
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
694
42
695
42
  if (LocVT == MVT::i8 ||
696
42
      
LocVT == MVT::i1642
) {
697
0
    LocVT = MVT::i32;
698
0
    if (ArgFlags.isSExt())
699
0
        LocInfo = CCValAssign::SExt;
700
0
    else 
if (0
ArgFlags.isZExt()0
)
701
0
        LocInfo = CCValAssign::ZExt;
702
0
    else
703
0
        LocInfo = CCValAssign::AExt;
704
0
  }
705
42
706
42
  if (
LocVT == MVT::i3242
) {
707
42
    static const MCPhysReg RegList1[] = {
708
42
      X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
709
42
    };
710
42
    if (unsigned 
Reg42
= State.AllocateReg(RegList1)) {
711
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
712
41
      return false;
713
41
    }
714
42
  }
715
42
716
1
  
if (1
LocVT == MVT::i32 ||
717
1
      
LocVT == MVT::f320
) {
718
1
    unsigned Offset2 = State.AllocateStack(4, 4);
719
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
720
1
    return false;
721
1
  }
722
1
723
0
  return true;  // CC didn't match.
724
42
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
725
726
727
static bool CC_X86_32_Intr(unsigned ValNo, MVT ValVT,
728
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
729
15
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
730
15
731
15
  unsigned Offset1 = State.AllocateStack(4, 4);
732
15
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
733
15
  return false;
734
15
735
0
  return true;  // CC didn't match.
736
15
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_32_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
729
15
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
730
15
731
15
  unsigned Offset1 = State.AllocateStack(4, 4);
732
15
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
733
15
  return false;
734
15
735
0
  return true;  // CC didn't match.
736
15
}
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
737
738
739
static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
740
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
741
125
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
742
125
743
125
  if (
ArgFlags.isByVal()125
) {
744
1
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
745
1
    return false;
746
1
  }
747
125
748
124
  
if (124
LocVT == MVT::i1 ||
749
124
      LocVT == MVT::i8 ||
750
115
      LocVT == MVT::i16 ||
751
124
      
LocVT == MVT::v1i1109
) {
752
15
    LocVT = MVT::i32;
753
15
    if (ArgFlags.isSExt())
754
0
        LocInfo = CCValAssign::SExt;
755
15
    else 
if (15
ArgFlags.isZExt()15
)
756
3
        LocInfo = CCValAssign::ZExt;
757
15
    else
758
12
        LocInfo = CCValAssign::AExt;
759
15
  }
760
124
761
124
  if (
!State.isVarArg()124
) {
762
123
    if (
LocVT == MVT::i32123
) {
763
122
      if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
764
119
            return false;
765
122
    }
766
123
  }
767
124
768
5
  
if (5
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)5
)
769
5
    return false;
770
5
771
0
  return true;  // CC didn't match.
772
125
}
X86ISelLowering.cpp:CC_X86_32_MCU(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
741
125
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
742
125
743
125
  if (
ArgFlags.isByVal()125
) {
744
1
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
745
1
    return false;
746
1
  }
747
125
748
124
  
if (124
LocVT == MVT::i1 ||
749
124
      LocVT == MVT::i8 ||
750
115
      LocVT == MVT::i16 ||
751
124
      
LocVT == MVT::v1i1109
) {
752
15
    LocVT = MVT::i32;
753
15
    if (ArgFlags.isSExt())
754
0
        LocInfo = CCValAssign::SExt;
755
15
    else 
if (15
ArgFlags.isZExt()15
)
756
3
        LocInfo = CCValAssign::ZExt;
757
15
    else
758
12
        LocInfo = CCValAssign::AExt;
759
15
  }
760
124
761
124
  if (
!State.isVarArg()124
) {
762
123
    if (
LocVT == MVT::i32123
) {
763
122
      if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
764
119
            return false;
765
122
    }
766
123
  }
767
124
768
5
  
if (5
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)5
)
769
5
    return false;
770
5
771
0
  return true;  // CC didn't match.
772
125
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_MCU(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_MCU(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
773
774
775
static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
776
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
777
200
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
778
200
779
200
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()200
) {
780
0
    if (
ArgFlags.isByVal()0
) {
781
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
782
0
      return false;
783
0
    }
784
0
  }
785
200
786
200
  
if (200
ArgFlags.isByVal()200
) {
787
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
788
0
    return false;
789
0
  }
790
200
791
200
  
if (200
LocVT == MVT::i1 ||
792
200
      LocVT == MVT::i8 ||
793
189
      LocVT == MVT::i16 ||
794
200
      
LocVT == MVT::v1i1185
) {
795
15
    LocVT = MVT::i32;
796
15
    if (ArgFlags.isSExt())
797
2
        LocInfo = CCValAssign::SExt;
798
13
    else 
if (13
ArgFlags.isZExt()13
)
799
0
        LocInfo = CCValAssign::ZExt;
800
13
    else
801
13
        LocInfo = CCValAssign::AExt;
802
15
  }
803
200
804
200
  if (LocVT == MVT::v8i1 ||
805
194
      LocVT == MVT::v16i1 ||
806
200
      
LocVT == MVT::v32i1188
) {
807
18
    LocVT = MVT::i32;
808
18
    if (ArgFlags.isSExt())
809
0
        LocInfo = CCValAssign::SExt;
810
18
    else 
if (18
ArgFlags.isZExt()18
)
811
0
        LocInfo = CCValAssign::ZExt;
812
18
    else
813
18
        LocInfo = CCValAssign::AExt;
814
18
  }
815
200
816
200
  if (
LocVT == MVT::i32200
) {
817
86
    static const MCPhysReg RegList1[] = {
818
86
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
819
86
    };
820
86
    if (unsigned 
Reg86
= State.AllocateReg(RegList1)) {
821
71
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
822
71
      return false;
823
71
    }
824
86
  }
825
200
826
129
  
if (129
LocVT == MVT::i64129
) {
827
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::RAX)) {
828
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
829
0
      return false;
830
0
    }
831
0
  }
832
129
833
129
  
if (129
LocVT == MVT::v64i1129
) {
834
26
    LocVT = MVT::i64;
835
26
    if (ArgFlags.isSExt())
836
0
        LocInfo = CCValAssign::SExt;
837
26
    else 
if (26
ArgFlags.isZExt()26
)
838
0
        LocInfo = CCValAssign::ZExt;
839
26
    else
840
26
        LocInfo = CCValAssign::AExt;
841
26
  }
842
129
843
129
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()129
) {
844
0
    if (
LocVT == MVT::i640
) {
845
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::RAX)) {
846
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
847
0
        return false;
848
0
      }
849
0
    }
850
0
  }
851
129
852
129
  
if (129
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()129
) {
853
129
    if (
LocVT == MVT::i64129
) {
854
26
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
855
4
            return false;
856
26
    }
857
129
  }
858
129
859
125
  
if (125
LocVT == MVT::f32 ||
860
120
      LocVT == MVT::f64 ||
861
125
      
LocVT == MVT::f128115
) {
862
10
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()10
) {
863
10
      static const MCPhysReg RegList2[] = {
864
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
865
10
      };
866
10
      if (unsigned 
Reg10
= State.AllocateReg(RegList2)) {
867
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
868
10
        return false;
869
10
      }
870
10
    }
871
10
  }
872
125
873
115
  
if (115
LocVT == MVT::f80115
) {
874
3
    if (unsigned 
Reg3
= State.AllocateReg(X86::FP0)) {
875
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
876
3
      return false;
877
3
    }
878
3
  }
879
115
880
112
  
if (112
LocVT == MVT::v16i8 ||
881
112
      LocVT == MVT::v8i16 ||
882
112
      LocVT == MVT::v4i32 ||
883
107
      LocVT == MVT::v2i64 ||
884
107
      LocVT == MVT::v4f32 ||
885
112
      
LocVT == MVT::v2f6471
) {
886
41
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()41
) {
887
41
      static const MCPhysReg RegList3[] = {
888
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
889
41
      };
890
41
      if (unsigned 
Reg41
= State.AllocateReg(RegList3)) {
891
21
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
892
21
        return false;
893
21
      }
894
41
    }
895
41
  }
896
112
897
91
  
if (91
LocVT == MVT::v32i8 ||
898
91
      LocVT == MVT::v16i16 ||
899
91
      LocVT == MVT::v8i32 ||
900
86
      LocVT == MVT::v4i64 ||
901
86
      LocVT == MVT::v8f32 ||
902
91
      
LocVT == MVT::v4f6486
) {
903
5
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()5
) {
904
5
      static const MCPhysReg RegList4[] = {
905
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
906
5
      };
907
5
      if (unsigned 
Reg5
= State.AllocateReg(RegList4)) {
908
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
909
5
        return false;
910
5
      }
911
5
    }
912
5
  }
913
91
914
86
  
if (86
LocVT == MVT::v64i8 ||
915
86
      LocVT == MVT::v32i16 ||
916
86
      LocVT == MVT::v16i32 ||
917
81
      LocVT == MVT::v8i64 ||
918
81
      LocVT == MVT::v16f32 ||
919
86
      
LocVT == MVT::v8f6457
) {
920
29
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()29
) {
921
29
      static const MCPhysReg RegList5[] = {
922
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
923
29
      };
924
29
      if (unsigned 
Reg29
= State.AllocateReg(RegList5)) {
925
19
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
926
19
        return false;
927
19
      }
928
29
    }
929
29
  }
930
86
931
67
  
if (67
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()67
) {
932
0
    if (LocVT == MVT::i32 ||
933
0
        LocVT == MVT::i64 ||
934
0
        LocVT == MVT::f32 ||
935
0
        
LocVT == MVT::f640
) {
936
0
      unsigned Offset6 = State.AllocateStack(8, 8);
937
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
938
0
      return false;
939
0
    }
940
0
  }
941
67
942
67
  
if (67
LocVT == MVT::i32 ||
943
67
      
LocVT == MVT::f3252
) {
944
15
    unsigned Offset7 = State.AllocateStack(4, 4);
945
15
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
946
15
    return false;
947
15
  }
948
67
949
52
  
if (52
LocVT == MVT::i64 ||
950
52
      
LocVT == MVT::f6430
) {
951
22
    unsigned Offset8 = State.AllocateStack(8, 4);
952
22
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
953
22
    return false;
954
22
  }
955
52
956
30
  
if (30
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()30
) {
957
0
    if (
LocVT == MVT::x86mmx0
) {
958
0
      unsigned Offset9 = State.AllocateStack(8, 8);
959
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
960
0
      return false;
961
0
    }
962
0
  }
963
30
964
30
  
if (30
LocVT == MVT::x86mmx30
) {
965
0
    unsigned Offset10 = State.AllocateStack(8, 4);
966
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
967
0
    return false;
968
0
  }
969
30
970
30
  
if (30
LocVT == MVT::f80 ||
971
30
      
LocVT == MVT::f12830
) {
972
0
    unsigned Offset11 = State.AllocateStack(
973
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
974
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
975
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
976
0
    return false;
977
0
  }
978
30
979
30
  
if (30
LocVT == MVT::v16i8 ||
980
30
      LocVT == MVT::v8i16 ||
981
30
      LocVT == MVT::v4i32 ||
982
30
      LocVT == MVT::v2i64 ||
983
30
      LocVT == MVT::v4f32 ||
984
30
      
LocVT == MVT::v2f6410
) {
985
20
    unsigned Offset12 = State.AllocateStack(16, 16);
986
20
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
987
20
    return false;
988
20
  }
989
30
990
10
  
if (10
LocVT == MVT::v32i8 ||
991
10
      LocVT == MVT::v16i16 ||
992
10
      LocVT == MVT::v8i32 ||
993
10
      LocVT == MVT::v4i64 ||
994
10
      LocVT == MVT::v8f32 ||
995
10
      
LocVT == MVT::v4f6410
) {
996
0
    unsigned Offset13 = State.AllocateStack(32, 32);
997
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
998
0
    return false;
999
0
  }
1000
10
1001
10
  
if (10
LocVT == MVT::v16i32 ||
1002
10
      LocVT == MVT::v8i64 ||
1003
10
      LocVT == MVT::v16f32 ||
1004
10
      
LocVT == MVT::v8f640
) {
1005
10
    unsigned Offset14 = State.AllocateStack(64, 64);
1006
10
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
1007
10
    return false;
1008
10
  }
1009
10
1010
0
  return true;  // CC didn't match.
1011
200
}
X86ISelLowering.cpp:CC_X86_32_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
777
200
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
778
200
779
200
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()200
) {
780
0
    if (
ArgFlags.isByVal()0
) {
781
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
782
0
      return false;
783
0
    }
784
0
  }
785
200
786
200
  
if (200
ArgFlags.isByVal()200
) {
787
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
788
0
    return false;
789
0
  }
790
200
791
200
  
if (200
LocVT == MVT::i1 ||
792
200
      LocVT == MVT::i8 ||
793
189
      LocVT == MVT::i16 ||
794
200
      
LocVT == MVT::v1i1185
) {
795
15
    LocVT = MVT::i32;
796
15
    if (ArgFlags.isSExt())
797
2
        LocInfo = CCValAssign::SExt;
798
13
    else 
if (13
ArgFlags.isZExt()13
)
799
0
        LocInfo = CCValAssign::ZExt;
800
13
    else
801
13
        LocInfo = CCValAssign::AExt;
802
15
  }
803
200
804
200
  if (LocVT == MVT::v8i1 ||
805
194
      LocVT == MVT::v16i1 ||
806
200
      
LocVT == MVT::v32i1188
) {
807
18
    LocVT = MVT::i32;
808
18
    if (ArgFlags.isSExt())
809
0
        LocInfo = CCValAssign::SExt;
810
18
    else 
if (18
ArgFlags.isZExt()18
)
811
0
        LocInfo = CCValAssign::ZExt;
812
18
    else
813
18
        LocInfo = CCValAssign::AExt;
814
18
  }
815
200
816
200
  if (
LocVT == MVT::i32200
) {
817
86
    static const MCPhysReg RegList1[] = {
818
86
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
819
86
    };
820
86
    if (unsigned 
Reg86
= State.AllocateReg(RegList1)) {
821
71
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
822
71
      return false;
823
71
    }
824
86
  }
825
200
826
129
  
if (129
LocVT == MVT::i64129
) {
827
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::RAX)) {
828
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
829
0
      return false;
830
0
    }
831
0
  }
832
129
833
129
  
if (129
LocVT == MVT::v64i1129
) {
834
26
    LocVT = MVT::i64;
835
26
    if (ArgFlags.isSExt())
836
0
        LocInfo = CCValAssign::SExt;
837
26
    else 
if (26
ArgFlags.isZExt()26
)
838
0
        LocInfo = CCValAssign::ZExt;
839
26
    else
840
26
        LocInfo = CCValAssign::AExt;
841
26
  }
842
129
843
129
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()129
) {
844
0
    if (
LocVT == MVT::i640
) {
845
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::RAX)) {
846
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
847
0
        return false;
848
0
      }
849
0
    }
850
0
  }
851
129
852
129
  
if (129
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()129
) {
853
129
    if (
LocVT == MVT::i64129
) {
854
26
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
855
4
            return false;
856
26
    }
857
129
  }
858
129
859
125
  
if (125
LocVT == MVT::f32 ||
860
120
      LocVT == MVT::f64 ||
861
125
      
LocVT == MVT::f128115
) {
862
10
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()10
) {
863
10
      static const MCPhysReg RegList2[] = {
864
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
865
10
      };
866
10
      if (unsigned 
Reg10
= State.AllocateReg(RegList2)) {
867
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
868
10
        return false;
869
10
      }
870
10
    }
871
10
  }
872
125
873
115
  
if (115
LocVT == MVT::f80115
) {
874
3
    if (unsigned 
Reg3
= State.AllocateReg(X86::FP0)) {
875
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
876
3
      return false;
877
3
    }
878
3
  }
879
115
880
112
  
if (112
LocVT == MVT::v16i8 ||
881
112
      LocVT == MVT::v8i16 ||
882
112
      LocVT == MVT::v4i32 ||
883
107
      LocVT == MVT::v2i64 ||
884
107
      LocVT == MVT::v4f32 ||
885
112
      
LocVT == MVT::v2f6471
) {
886
41
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()41
) {
887
41
      static const MCPhysReg RegList3[] = {
888
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
889
41
      };
890
41
      if (unsigned 
Reg41
= State.AllocateReg(RegList3)) {
891
21
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
892
21
        return false;
893
21
      }
894
41
    }
895
41
  }
896
112
897
91
  
if (91
LocVT == MVT::v32i8 ||
898
91
      LocVT == MVT::v16i16 ||
899
91
      LocVT == MVT::v8i32 ||
900
86
      LocVT == MVT::v4i64 ||
901
86
      LocVT == MVT::v8f32 ||
902
91
      
LocVT == MVT::v4f6486
) {
903
5
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()5
) {
904
5
      static const MCPhysReg RegList4[] = {
905
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
906
5
      };
907
5
      if (unsigned 
Reg5
= State.AllocateReg(RegList4)) {
908
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
909
5
        return false;
910
5
      }
911
5
    }
912
5
  }
913
91
914
86
  
if (86
LocVT == MVT::v64i8 ||
915
86
      LocVT == MVT::v32i16 ||
916
86
      LocVT == MVT::v16i32 ||
917
81
      LocVT == MVT::v8i64 ||
918
81
      LocVT == MVT::v16f32 ||
919
86
      
LocVT == MVT::v8f6457
) {
920
29
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()29
) {
921
29
      static const MCPhysReg RegList5[] = {
922
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
923
29
      };
924
29
      if (unsigned 
Reg29
= State.AllocateReg(RegList5)) {
925
19
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
926
19
        return false;
927
19
      }
928
29
    }
929
29
  }
930
86
931
67
  
if (67
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()67
) {
932
0
    if (LocVT == MVT::i32 ||
933
0
        LocVT == MVT::i64 ||
934
0
        LocVT == MVT::f32 ||
935
0
        
LocVT == MVT::f640
) {
936
0
      unsigned Offset6 = State.AllocateStack(8, 8);
937
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
938
0
      return false;
939
0
    }
940
0
  }
941
67
942
67
  
if (67
LocVT == MVT::i32 ||
943
67
      
LocVT == MVT::f3252
) {
944
15
    unsigned Offset7 = State.AllocateStack(4, 4);
945
15
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
946
15
    return false;
947
15
  }
948
67
949
52
  
if (52
LocVT == MVT::i64 ||
950
52
      
LocVT == MVT::f6430
) {
951
22
    unsigned Offset8 = State.AllocateStack(8, 4);
952
22
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
953
22
    return false;
954
22
  }
955
52
956
30
  
if (30
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()30
) {
957
0
    if (
LocVT == MVT::x86mmx0
) {
958
0
      unsigned Offset9 = State.AllocateStack(8, 8);
959
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
960
0
      return false;
961
0
    }
962
0
  }
963
30
964
30
  
if (30
LocVT == MVT::x86mmx30
) {
965
0
    unsigned Offset10 = State.AllocateStack(8, 4);
966
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
967
0
    return false;
968
0
  }
969
30
970
30
  
if (30
LocVT == MVT::f80 ||
971
30
      
LocVT == MVT::f12830
) {
972
0
    unsigned Offset11 = State.AllocateStack(
973
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
974
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
975
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
976
0
    return false;
977
0
  }
978
30
979
30
  
if (30
LocVT == MVT::v16i8 ||
980
30
      LocVT == MVT::v8i16 ||
981
30
      LocVT == MVT::v4i32 ||
982
30
      LocVT == MVT::v2i64 ||
983
30
      LocVT == MVT::v4f32 ||
984
30
      
LocVT == MVT::v2f6410
) {
985
20
    unsigned Offset12 = State.AllocateStack(16, 16);
986
20
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
987
20
    return false;
988
20
  }
989
30
990
10
  
if (10
LocVT == MVT::v32i8 ||
991
10
      LocVT == MVT::v16i16 ||
992
10
      LocVT == MVT::v8i32 ||
993
10
      LocVT == MVT::v4i64 ||
994
10
      LocVT == MVT::v8f32 ||
995
10
      
LocVT == MVT::v4f6410
) {
996
0
    unsigned Offset13 = State.AllocateStack(32, 32);
997
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
998
0
    return false;
999
0
  }
1000
10
1001
10
  
if (10
LocVT == MVT::v16i32 ||
1002
10
      LocVT == MVT::v8i64 ||
1003
10
      LocVT == MVT::v16f32 ||
1004
10
      
LocVT == MVT::v8f640
) {
1005
10
    unsigned Offset14 = State.AllocateStack(64, 64);
1006
10
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
1007
10
    return false;
1008
10
  }
1009
10
1010
0
  return true;  // CC didn't match.
1011
200
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
1012
1013
1014
static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
1015
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
1016
362
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
1017
362
1018
362
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()362
) {
1019
40
    if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1020
40
      return false;
1021
40
  }
1022
362
1023
322
  
if (322
!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)322
)
1024
322
    return false;
1025
322
1026
0
  return true;  // CC didn't match.
1027
362
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_ThisCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86FastISel.cpp:CC_X86_32_ThisCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1016
28
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
1017
28
1018
28
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()28
) {
1019
12
    if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1020
12
      return false;
1021
12
  }
1022
28
1023
16
  
if (16
!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)16
)
1024
16
    return false;
1025
16
1026
0
  return true;  // CC didn't match.
1027
28
}
X86ISelLowering.cpp:CC_X86_32_ThisCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1016
334
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
1017
334
1018
334
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()334
) {
1019
28
    if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1020
28
      return false;
1021
28
  }
1022
334
1023
306
  
if (306
!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)306
)
1024
306
    return false;
1025
306
1026
0
  return true;  // CC didn't match.
1027
334
}
1028
1029
1030
static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
1031
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1032
338
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1033
338
1034
338
  if (
LocVT == MVT::i32338
) {
1035
336
    if (unsigned 
Reg336
= State.AllocateReg(X86::ECX)) {
1036
180
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1037
180
      return false;
1038
180
    }
1039
336
  }
1040
338
1041
158
  
if (158
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)158
)
1042
158
    return false;
1043
158
1044
0
  return true;  // CC didn't match.
1045
338
}
X86FastISel.cpp:CC_X86_32_ThisCall_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1032
22
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1033
22
1034
22
  if (
LocVT == MVT::i3222
) {
1035
22
    if (unsigned 
Reg22
= State.AllocateReg(X86::ECX)) {
1036
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1037
14
      return false;
1038
14
    }
1039
22
  }
1040
22
1041
8
  
if (8
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)8
)
1042
8
    return false;
1043
8
1044
0
  return true;  // CC didn't match.
1045
22
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_ThisCall_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_32_ThisCall_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1032
316
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1033
316
1034
316
  if (
LocVT == MVT::i32316
) {
1035
314
    if (unsigned 
Reg314
= State.AllocateReg(X86::ECX)) {
1036
166
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1037
166
      return false;
1038
166
    }
1039
314
  }
1040
316
1041
150
  
if (150
!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)150
)
1042
150
    return false;
1043
150
1044
0
  return true;  // CC didn't match.
1045
316
}
1046
1047
1048
static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
1049
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
1050
40
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
1051
40
1052
40
  if (LocVT == MVT::i1 ||
1053
40
      LocVT == MVT::i8 ||
1054
40
      LocVT == MVT::i16 ||
1055
40
      
LocVT == MVT::v1i140
) {
1056
0
    LocVT = MVT::i32;
1057
0
    if (ArgFlags.isSExt())
1058
0
        LocInfo = CCValAssign::SExt;
1059
0
    else 
if (0
ArgFlags.isZExt()0
)
1060
0
        LocInfo = CCValAssign::ZExt;
1061
0
    else
1062
0
        LocInfo = CCValAssign::AExt;
1063
0
  }
1064
40
1065
40
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1066
40
    return false;
1067
40
1068
0
  return true;  // CC didn't match.
1069
40
}
X86ISelLowering.cpp:CC_X86_32_ThisCall_Mingw(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1050
28
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
1051
28
1052
28
  if (LocVT == MVT::i1 ||
1053
28
      LocVT == MVT::i8 ||
1054
28
      LocVT == MVT::i16 ||
1055
28
      
LocVT == MVT::v1i128
) {
1056
0
    LocVT = MVT::i32;
1057
0
    if (ArgFlags.isSExt())
1058
0
        LocInfo = CCValAssign::SExt;
1059
0
    else 
if (0
ArgFlags.isZExt()0
)
1060
0
        LocInfo = CCValAssign::ZExt;
1061
0
    else
1062
0
        LocInfo = CCValAssign::AExt;
1063
0
  }
1064
28
1065
28
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1066
28
    return false;
1067
28
1068
0
  return true;  // CC didn't match.
1069
28
}
X86FastISel.cpp:CC_X86_32_ThisCall_Mingw(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1050
12
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
1051
12
1052
12
  if (LocVT == MVT::i1 ||
1053
12
      LocVT == MVT::i8 ||
1054
12
      LocVT == MVT::i16 ||
1055
12
      
LocVT == MVT::v1i112
) {
1056
0
    LocVT = MVT::i32;
1057
0
    if (ArgFlags.isSExt())
1058
0
        LocInfo = CCValAssign::SExt;
1059
0
    else 
if (0
ArgFlags.isZExt()0
)
1060
0
        LocInfo = CCValAssign::ZExt;
1061
0
    else
1062
0
        LocInfo = CCValAssign::AExt;
1063
0
  }
1064
12
1065
12
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1066
12
    return false;
1067
12
1068
0
  return true;  // CC didn't match.
1069
12
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_ThisCall_Mingw(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
1070
1071
1072
static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
1073
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
1074
322
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
1075
322
1076
322
  if (LocVT == MVT::i1 ||
1077
322
      LocVT == MVT::i8 ||
1078
321
      LocVT == MVT::i16 ||
1079
322
      
LocVT == MVT::v1i1321
) {
1080
1
    LocVT = MVT::i32;
1081
1
    if (ArgFlags.isSExt())
1082
0
        LocInfo = CCValAssign::SExt;
1083
1
    else 
if (1
ArgFlags.isZExt()1
)
1084
0
        LocInfo = CCValAssign::ZExt;
1085
1
    else
1086
1
        LocInfo = CCValAssign::AExt;
1087
1
  }
1088
322
1089
322
  if (
ArgFlags.isSRet()322
) {
1090
24
    unsigned Offset1 = State.AllocateStack(4, 4);
1091
24
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1092
24
    return false;
1093
24
  }
1094
322
1095
298
  
if (298
!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)298
)
1096
298
    return false;
1097
298
1098
0
  return true;  // CC didn't match.
1099
322
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_ThisCall_Win(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86FastISel.cpp:CC_X86_32_ThisCall_Win(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1074
16
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
1075
16
1076
16
  if (LocVT == MVT::i1 ||
1077
16
      LocVT == MVT::i8 ||
1078
16
      LocVT == MVT::i16 ||
1079
16
      
LocVT == MVT::v1i116
) {
1080
0
    LocVT = MVT::i32;
1081
0
    if (ArgFlags.isSExt())
1082
0
        LocInfo = CCValAssign::SExt;
1083
0
    else 
if (0
ArgFlags.isZExt()0
)
1084
0
        LocInfo = CCValAssign::ZExt;
1085
0
    else
1086
0
        LocInfo = CCValAssign::AExt;
1087
0
  }
1088
16
1089
16
  if (
ArgFlags.isSRet()16
) {
1090
6
    unsigned Offset1 = State.AllocateStack(4, 4);
1091
6
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1092
6
    return false;
1093
6
  }
1094
16
1095
10
  
if (10
!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)10
)
1096
10
    return false;
1097
10
1098
0
  return true;  // CC didn't match.
1099
16
}
X86ISelLowering.cpp:CC_X86_32_ThisCall_Win(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1074
306
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
1075
306
1076
306
  if (LocVT == MVT::i1 ||
1077
306
      LocVT == MVT::i8 ||
1078
305
      LocVT == MVT::i16 ||
1079
306
      
LocVT == MVT::v1i1305
) {
1080
1
    LocVT = MVT::i32;
1081
1
    if (ArgFlags.isSExt())
1082
0
        LocInfo = CCValAssign::SExt;
1083
1
    else 
if (1
ArgFlags.isZExt()1
)
1084
0
        LocInfo = CCValAssign::ZExt;
1085
1
    else
1086
1
        LocInfo = CCValAssign::AExt;
1087
1
  }
1088
306
1089
306
  if (
ArgFlags.isSRet()306
) {
1090
18
    unsigned Offset1 = State.AllocateStack(4, 4);
1091
18
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1092
18
    return false;
1093
18
  }
1094
306
1095
288
  
if (288
!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)288
)
1096
288
    return false;
1097
288
1098
0
  return true;  // CC didn't match.
1099
306
}
1100
1101
1102
static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
1103
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
1104
175
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1105
175
1106
175
  if (LocVT == MVT::v16i8 ||
1107
173
      LocVT == MVT::v8i16 ||
1108
165
      LocVT == MVT::v4i32 ||
1109
149
      LocVT == MVT::v2i64 ||
1110
140
      LocVT == MVT::v4f32 ||
1111
175
      
LocVT == MVT::v2f6475
) {
1112
118
    unsigned Offset1 = State.AllocateStack(16, 16);
1113
118
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1114
118
    return false;
1115
118
  }
1116
175
1117
57
  
if (57
LocVT == MVT::v32i8 ||
1118
55
      LocVT == MVT::v16i16 ||
1119
53
      LocVT == MVT::v8i32 ||
1120
46
      LocVT == MVT::v4i64 ||
1121
43
      LocVT == MVT::v8f32 ||
1122
57
      
LocVT == MVT::v4f6425
) {
1123
42
    unsigned Offset2 = State.AllocateStack(32, 32);
1124
42
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1125
42
    return false;
1126
42
  }
1127
57
1128
15
  
if (15
LocVT == MVT::v64i8 ||
1129
13
      LocVT == MVT::v32i16 ||
1130
11
      LocVT == MVT::v16i32 ||
1131
10
      LocVT == MVT::v8i64 ||
1132
6
      LocVT == MVT::v16f32 ||
1133
15
      
LocVT == MVT::v8f645
) {
1134
15
    unsigned Offset3 = State.AllocateStack(64, 64);
1135
15
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1136
15
    return false;
1137
15
  }
1138
15
1139
0
  return true;  // CC didn't match.
1140
175
}
X86ISelLowering.cpp:CC_X86_32_Vector_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1104
171
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1105
171
1106
171
  if (LocVT == MVT::v16i8 ||
1107
169
      LocVT == MVT::v8i16 ||
1108
161
      LocVT == MVT::v4i32 ||
1109
148
      LocVT == MVT::v2i64 ||
1110
139
      LocVT == MVT::v4f32 ||
1111
171
      
LocVT == MVT::v2f6475
) {
1112
114
    unsigned Offset1 = State.AllocateStack(16, 16);
1113
114
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1114
114
    return false;
1115
114
  }
1116
171
1117
57
  
if (57
LocVT == MVT::v32i8 ||
1118
55
      LocVT == MVT::v16i16 ||
1119
53
      LocVT == MVT::v8i32 ||
1120
46
      LocVT == MVT::v4i64 ||
1121
43
      LocVT == MVT::v8f32 ||
1122
57
      
LocVT == MVT::v4f6425
) {
1123
42
    unsigned Offset2 = State.AllocateStack(32, 32);
1124
42
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1125
42
    return false;
1126
42
  }
1127
57
1128
15
  
if (15
LocVT == MVT::v64i8 ||
1129
13
      LocVT == MVT::v32i16 ||
1130
11
      LocVT == MVT::v16i32 ||
1131
10
      LocVT == MVT::v8i64 ||
1132
6
      LocVT == MVT::v16f32 ||
1133
15
      
LocVT == MVT::v8f645
) {
1134
15
    unsigned Offset3 = State.AllocateStack(64, 64);
1135
15
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1136
15
    return false;
1137
15
  }
1138
15
1139
0
  return true;  // CC didn't match.
1140
171
}
X86CallLowering.cpp:CC_X86_32_Vector_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1104
3
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1105
3
1106
3
  if (LocVT == MVT::v16i8 ||
1107
3
      LocVT == MVT::v8i16 ||
1108
3
      LocVT == MVT::v4i32 ||
1109
0
      LocVT == MVT::v2i64 ||
1110
0
      LocVT == MVT::v4f32 ||
1111
3
      
LocVT == MVT::v2f640
) {
1112
3
    unsigned Offset1 = State.AllocateStack(16, 16);
1113
3
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1114
3
    return false;
1115
3
  }
1116
3
1117
0
  
if (0
LocVT == MVT::v32i8 ||
1118
0
      LocVT == MVT::v16i16 ||
1119
0
      LocVT == MVT::v8i32 ||
1120
0
      LocVT == MVT::v4i64 ||
1121
0
      LocVT == MVT::v8f32 ||
1122
0
      
LocVT == MVT::v4f640
) {
1123
0
    unsigned Offset2 = State.AllocateStack(32, 32);
1124
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1125
0
    return false;
1126
0
  }
1127
0
1128
0
  
if (0
LocVT == MVT::v64i8 ||
1129
0
      LocVT == MVT::v32i16 ||
1130
0
      LocVT == MVT::v16i32 ||
1131
0
      LocVT == MVT::v8i64 ||
1132
0
      LocVT == MVT::v16f32 ||
1133
0
      
LocVT == MVT::v8f640
) {
1134
0
    unsigned Offset3 = State.AllocateStack(64, 64);
1135
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1136
0
    return false;
1137
0
  }
1138
0
1139
0
  return true;  // CC didn't match.
1140
3
}
X86FastISel.cpp:CC_X86_32_Vector_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1104
1
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1105
1
1106
1
  if (LocVT == MVT::v16i8 ||
1107
1
      LocVT == MVT::v8i16 ||
1108
1
      LocVT == MVT::v4i32 ||
1109
1
      LocVT == MVT::v2i64 ||
1110
1
      LocVT == MVT::v4f32 ||
1111
1
      
LocVT == MVT::v2f640
) {
1112
1
    unsigned Offset1 = State.AllocateStack(16, 16);
1113
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1114
1
    return false;
1115
1
  }
1116
1
1117
0
  
if (0
LocVT == MVT::v32i8 ||
1118
0
      LocVT == MVT::v16i16 ||
1119
0
      LocVT == MVT::v8i32 ||
1120
0
      LocVT == MVT::v4i64 ||
1121
0
      LocVT == MVT::v8f32 ||
1122
0
      
LocVT == MVT::v4f640
) {
1123
0
    unsigned Offset2 = State.AllocateStack(32, 32);
1124
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1125
0
    return false;
1126
0
  }
1127
0
1128
0
  
if (0
LocVT == MVT::v64i8 ||
1129
0
      LocVT == MVT::v32i16 ||
1130
0
      LocVT == MVT::v16i32 ||
1131
0
      LocVT == MVT::v8i64 ||
1132
0
      LocVT == MVT::v16f32 ||
1133
0
      
LocVT == MVT::v8f640
) {
1134
0
    unsigned Offset3 = State.AllocateStack(64, 64);
1135
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1136
0
    return false;
1137
0
  }
1138
0
1139
0
  return true;  // CC didn't match.
1140
1
}
1141
1142
1143
static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
1144
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
1145
2.14k
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1146
2.14k
1147
2.14k
  if (
!State.isVarArg()2.14k
) {
1148
2.14k
    if (LocVT == MVT::v16i8 ||
1149
1.90k
        LocVT == MVT::v8i16 ||
1150
1.69k
        LocVT == MVT::v4i32 ||
1151
1.44k
        LocVT == MVT::v2i64 ||
1152
1.27k
        LocVT == MVT::v4f32 ||
1153
2.14k
        
LocVT == MVT::v2f64866
) {
1154
1.54k
      static const MCPhysReg RegList1[] = {
1155
1.54k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1156
1.54k
      };
1157
1.54k
      if (unsigned 
Reg1.54k
= State.AllocateReg(RegList1)) {
1158
1.53k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1159
1.53k
        return false;
1160
1.53k
      }
1161
1.54k
    }
1162
2.14k
  }
1163
2.14k
1164
608
  
if (608
!State.isVarArg()608
) {
1165
608
    if (LocVT == MVT::v32i8 ||
1166
516
        LocVT == MVT::v16i16 ||
1167
380
        LocVT == MVT::v8i32 ||
1168
230
        LocVT == MVT::v4i64 ||
1169
168
        LocVT == MVT::v8f32 ||
1170
608
        
LocVT == MVT::v4f6479
) {
1171
587
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasFp256()587
) {
1172
587
        static const MCPhysReg RegList2[] = {
1173
587
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1174
587
        };
1175
587
        if (unsigned 
Reg587
= State.AllocateReg(RegList2)) {
1176
567
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1177
567
          return false;
1178
567
        }
1179
587
      }
1180
587
    }
1181
608
  }
1182
608
1183
41
  
if (41
!State.isVarArg()41
) {
1184
41
    if (LocVT == MVT::v64i8 ||
1185
41
        LocVT == MVT::v32i16 ||
1186
41
        LocVT == MVT::v16i32 ||
1187
35
        LocVT == MVT::v8i64 ||
1188
35
        LocVT == MVT::v16f32 ||
1189
41
        
LocVT == MVT::v8f6428
) {
1190
13
      static const MCPhysReg RegList3[] = {
1191
13
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1192
13
      };
1193
13
      if (unsigned 
Reg13
= State.AllocateReg(RegList3)) {
1194
13
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1195
13
        return false;
1196
13
      }
1197
13
    }
1198
41
  }
1199
41
1200
28
  
if (28
!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)28
)
1201
28
    return false;
1202
28
1203
0
  return true;  // CC didn't match.
1204
2.14k
}
X86ISelLowering.cpp:CC_X86_32_Vector_Darwin(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1145
2.13k
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1146
2.13k
1147
2.13k
  if (
!State.isVarArg()2.13k
) {
1148
2.13k
    if (LocVT == MVT::v16i8 ||
1149
1.90k
        LocVT == MVT::v8i16 ||
1150
1.69k
        LocVT == MVT::v4i32 ||
1151
1.43k
        LocVT == MVT::v2i64 ||
1152
1.27k
        LocVT == MVT::v4f32 ||
1153
2.13k
        
LocVT == MVT::v2f64866
) {
1154
1.53k
      static const MCPhysReg RegList1[] = {
1155
1.53k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1156
1.53k
      };
1157
1.53k
      if (unsigned 
Reg1.53k
= State.AllocateReg(RegList1)) {
1158
1.52k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1159
1.52k
        return false;
1160
1.52k
      }
1161
1.53k
    }
1162
2.13k
  }
1163
2.13k
1164
607
  
if (607
!State.isVarArg()607
) {
1165
607
    if (LocVT == MVT::v32i8 ||
1166
515
        LocVT == MVT::v16i16 ||
1167
379
        LocVT == MVT::v8i32 ||
1168
229
        LocVT == MVT::v4i64 ||
1169
167
        LocVT == MVT::v8f32 ||
1170
607
        
LocVT == MVT::v4f6478
) {
1171
587
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasFp256()587
) {
1172
587
        static const MCPhysReg RegList2[] = {
1173
587
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1174
587
        };
1175
587
        if (unsigned 
Reg587
= State.AllocateReg(RegList2)) {
1176
567
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1177
567
          return false;
1178
567
        }
1179
587
      }
1180
587
    }
1181
607
  }
1182
607
1183
40
  
if (40
!State.isVarArg()40
) {
1184
40
    if (LocVT == MVT::v64i8 ||
1185
40
        LocVT == MVT::v32i16 ||
1186
40
        LocVT == MVT::v16i32 ||
1187
34
        LocVT == MVT::v8i64 ||
1188
34
        LocVT == MVT::v16f32 ||
1189
40
        
LocVT == MVT::v8f6427
) {
1190
13
      static const MCPhysReg RegList3[] = {
1191
13
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1192
13
      };
1193
13
      if (unsigned 
Reg13
= State.AllocateReg(RegList3)) {
1194
13
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1195
13
        return false;
1196
13
      }
1197
13
    }
1198
40
  }
1199
40
1200
27
  
if (27
!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)27
)
1201
27
    return false;
1202
27
1203
0
  return true;  // CC didn't match.
1204
2.13k
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_Vector_Darwin(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86FastISel.cpp:CC_X86_32_Vector_Darwin(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1145
5
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1146
5
1147
5
  if (
!State.isVarArg()5
) {
1148
5
    if (LocVT == MVT::v16i8 ||
1149
5
        LocVT == MVT::v8i16 ||
1150
5
        LocVT == MVT::v4i32 ||
1151
5
        LocVT == MVT::v2i64 ||
1152
5
        LocVT == MVT::v4f32 ||
1153
5
        
LocVT == MVT::v2f640
) {
1154
5
      static const MCPhysReg RegList1[] = {
1155
5
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1156
5
      };
1157
5
      if (unsigned 
Reg5
= State.AllocateReg(RegList1)) {
1158
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1159
4
        return false;
1160
4
      }
1161
5
    }
1162
5
  }
1163
5
1164
1
  
if (1
!State.isVarArg()1
) {
1165
1
    if (LocVT == MVT::v32i8 ||
1166
1
        LocVT == MVT::v16i16 ||
1167
1
        LocVT == MVT::v8i32 ||
1168
1
        LocVT == MVT::v4i64 ||
1169
1
        LocVT == MVT::v8f32 ||
1170
1
        
LocVT == MVT::v4f641
) {
1171
0
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasFp256()0
) {
1172
0
        static const MCPhysReg RegList2[] = {
1173
0
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1174
0
        };
1175
0
        if (unsigned 
Reg0
= State.AllocateReg(RegList2)) {
1176
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1177
0
          return false;
1178
0
        }
1179
0
      }
1180
0
    }
1181
1
  }
1182
1
1183
1
  
if (1
!State.isVarArg()1
) {
1184
1
    if (LocVT == MVT::v64i8 ||
1185
1
        LocVT == MVT::v32i16 ||
1186
1
        LocVT == MVT::v16i32 ||
1187
1
        LocVT == MVT::v8i64 ||
1188
1
        LocVT == MVT::v16f32 ||
1189
1
        
LocVT == MVT::v8f641
) {
1190
0
      static const MCPhysReg RegList3[] = {
1191
0
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1192
0
      };
1193
0
      if (unsigned 
Reg0
= State.AllocateReg(RegList3)) {
1194
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1195
0
        return false;
1196
0
      }
1197
0
    }
1198
1
  }
1199
1
1200
1
  
if (1
!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)1
)
1201
1
    return false;
1202
1
1203
0
  return true;  // CC didn't match.
1204
5
}
1205
1206
1207
static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
1208
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1209
5.27k
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1210
5.27k
1211
5.27k
  if (
!State.isVarArg()5.27k
) {
1212
5.27k
    if (LocVT == MVT::v16i8 ||
1213
5.06k
        LocVT == MVT::v8i16 ||
1214
4.83k
        LocVT == MVT::v4i32 ||
1215
4.45k
        LocVT == MVT::v2i64 ||
1216
3.67k
        LocVT == MVT::v4f32 ||
1217
5.27k
        
LocVT == MVT::v2f643.04k
) {
1218
2.63k
      static const MCPhysReg RegList1[] = {
1219
2.63k
        X86::XMM0, X86::XMM1, X86::XMM2
1220
2.63k
      };
1221
2.63k
      if (unsigned 
Reg2.63k
= State.AllocateReg(RegList1)) {
1222
2.52k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1223
2.52k
        return false;
1224
2.52k
      }
1225
2.63k
    }
1226
5.27k
  }
1227
5.27k
1228
2.75k
  
if (2.75k
!State.isVarArg()2.75k
) {
1229
2.75k
    if (LocVT == MVT::v32i8 ||
1230
2.57k
        LocVT == MVT::v16i16 ||
1231
2.43k
        LocVT == MVT::v8i32 ||
1232
2.25k
        LocVT == MVT::v4i64 ||
1233
1.81k
        LocVT == MVT::v8f32 ||
1234
2.75k
        
LocVT == MVT::v4f641.45k
) {
1235
1.55k
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasFp256()1.55k
) {
1236
1.55k
        static const MCPhysReg RegList2[] = {
1237
1.55k
          X86::YMM0, X86::YMM1, X86::YMM2
1238
1.55k
        };
1239
1.55k
        if (unsigned 
Reg1.55k
= State.AllocateReg(RegList2)) {
1240
1.53k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1241
1.53k
          return false;
1242
1.53k
        }
1243
1.55k
      }
1244
1.55k
    }
1245
2.75k
  }
1246
2.75k
1247
1.22k
  
if (1.22k
!State.isVarArg()1.22k
) {
1248
1.21k
    if (LocVT == MVT::v64i8 ||
1249
1.12k
        LocVT == MVT::v32i16 ||
1250
877
        LocVT == MVT::v16i32 ||
1251
749
        LocVT == MVT::v8i64 ||
1252
473
        LocVT == MVT::v16f32 ||
1253
1.21k
        
LocVT == MVT::v8f64383
) {
1254
1.08k
      static const MCPhysReg RegList3[] = {
1255
1.08k
        X86::ZMM0, X86::ZMM1, X86::ZMM2
1256
1.08k
      };
1257
1.08k
      if (unsigned 
Reg1.08k
= State.AllocateReg(RegList3)) {
1258
1.07k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1259
1.07k
        return false;
1260
1.07k
      }
1261
1.08k
    }
1262
1.21k
  }
1263
1.22k
1264
147
  
if (147
!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)147
)
1265
147
    return false;
1266
147
1267
0
  return true;  // CC didn't match.
1268
5.27k
}
X86ISelLowering.cpp:CC_X86_32_Vector_Standard(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1209
5.25k
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1210
5.25k
1211
5.25k
  if (
!State.isVarArg()5.25k
) {
1212
5.25k
    if (LocVT == MVT::v16i8 ||
1213
5.03k
        LocVT == MVT::v8i16 ||
1214
4.80k
        LocVT == MVT::v4i32 ||
1215
4.45k
        LocVT == MVT::v2i64 ||
1216
3.67k
        LocVT == MVT::v4f32 ||
1217
5.25k
        
LocVT == MVT::v2f643.04k
) {
1218
2.61k
      static const MCPhysReg RegList1[] = {
1219
2.61k
        X86::XMM0, X86::XMM1, X86::XMM2
1220
2.61k
      };
1221
2.61k
      if (unsigned 
Reg2.61k
= State.AllocateReg(RegList1)) {
1222
2.50k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1223
2.50k
        return false;
1224
2.50k
      }
1225
2.61k
    }
1226
5.25k
  }
1227
5.25k
1228
2.75k
  
if (2.75k
!State.isVarArg()2.75k
) {
1229
2.74k
    if (LocVT == MVT::v32i8 ||
1230
2.57k
        LocVT == MVT::v16i16 ||
1231
2.43k
        LocVT == MVT::v8i32 ||
1232
2.25k
        LocVT == MVT::v4i64 ||
1233
1.81k
        LocVT == MVT::v8f32 ||
1234
2.74k
        
LocVT == MVT::v4f641.45k
) {
1235
1.55k
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasFp256()1.55k
) {
1236
1.55k
        static const MCPhysReg RegList2[] = {
1237
1.55k
          X86::YMM0, X86::YMM1, X86::YMM2
1238
1.55k
        };
1239
1.55k
        if (unsigned 
Reg1.55k
= State.AllocateReg(RegList2)) {
1240
1.53k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1241
1.53k
          return false;
1242
1.53k
        }
1243
1.55k
      }
1244
1.55k
    }
1245
2.74k
  }
1246
2.75k
1247
1.21k
  
if (1.21k
!State.isVarArg()1.21k
) {
1248
1.21k
    if (LocVT == MVT::v64i8 ||
1249
1.12k
        LocVT == MVT::v32i16 ||
1250
874
        LocVT == MVT::v16i32 ||
1251
746
        LocVT == MVT::v8i64 ||
1252
470
        LocVT == MVT::v16f32 ||
1253
1.21k
        
LocVT == MVT::v8f64380
) {
1254
1.08k
      static const MCPhysReg RegList3[] = {
1255
1.08k
        X86::ZMM0, X86::ZMM1, X86::ZMM2
1256
1.08k
      };
1257
1.08k
      if (unsigned 
Reg1.08k
= State.AllocateReg(RegList3)) {
1258
1.07k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1259
1.07k
        return false;
1260
1.07k
      }
1261
1.08k
    }
1262
1.21k
  }
1263
1.21k
1264
144
  
if (144
!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)144
)
1265
144
    return false;
1266
144
1267
0
  return true;  // CC didn't match.
1268
5.25k
}
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_Vector_Standard(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86CallLowering.cpp:CC_X86_32_Vector_Standard(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1209
22
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1210
22
1211
22
  if (
!State.isVarArg()22
) {
1212
22
    if (LocVT == MVT::v16i8 ||
1213
22
        LocVT == MVT::v8i16 ||
1214
22
        LocVT == MVT::v4i32 ||
1215
0
        LocVT == MVT::v2i64 ||
1216
0
        LocVT == MVT::v4f32 ||
1217
22
        
LocVT == MVT::v2f640
) {
1218
22
      static const MCPhysReg RegList1[] = {
1219
22
        X86::XMM0, X86::XMM1, X86::XMM2
1220
22
      };
1221
22
      if (unsigned 
Reg22
= State.AllocateReg(RegList1)) {
1222
19
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1223
19
        return false;
1224
19
      }
1225
22
    }
1226
22
  }
1227
22
1228
3
  
if (3
!State.isVarArg()3
) {
1229
3
    if (LocVT == MVT::v32i8 ||
1230
3
        LocVT == MVT::v16i16 ||
1231
3
        LocVT == MVT::v8i32 ||
1232
3
        LocVT == MVT::v4i64 ||
1233
3
        LocVT == MVT::v8f32 ||
1234
3
        
LocVT == MVT::v4f643
) {
1235
0
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasFp256()0
) {
1236
0
        static const MCPhysReg RegList2[] = {
1237
0
          X86::YMM0, X86::YMM1, X86::YMM2
1238
0
        };
1239
0
        if (unsigned 
Reg0
= State.AllocateReg(RegList2)) {
1240
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1241
0
          return false;
1242
0
        }
1243
0
      }
1244
0
    }
1245
3
  }
1246
3
1247
3
  
if (3
!State.isVarArg()3
) {
1248
3
    if (LocVT == MVT::v64i8 ||
1249
3
        LocVT == MVT::v32i16 ||
1250
3
        LocVT == MVT::v16i32 ||
1251
3
        LocVT == MVT::v8i64 ||
1252
3
        LocVT == MVT::v16f32 ||
1253
3
        
LocVT == MVT::v8f643
) {
1254
0
      static const MCPhysReg RegList3[] = {
1255
0
        X86::ZMM0, X86::ZMM1, X86::ZMM2
1256
0
      };
1257
0
      if (unsigned 
Reg0
= State.AllocateReg(RegList3)) {
1258
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1259
0
        return false;
1260
0
      }
1261
0
    }
1262
3
  }
1263
3
1264
3
  
if (3
!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)3
)
1265
3
    return false;
1266
3
1267
0
  return true;  // CC didn't match.
1268
22
}
1269
1270
1271
static bool CC_X86_64(unsigned ValNo, MVT ValVT,
1272
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1273
154k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1274
154k
1275
154k
  if (
State.getCallingConv() == CallingConv::GHC154k
) {
1276
62
    if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1277
62
      return false;
1278
62
  }
1279
154k
1280
154k
  
if (154k
State.getCallingConv() == CallingConv::HiPE154k
) {
1281
42
    if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1282
42
      return false;
1283
42
  }
1284
154k
1285
154k
  
if (154k
State.getCallingConv() == CallingConv::WebKit_JS154k
) {
1286
69
    if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1287
69
      return false;
1288
69
  }
1289
154k
1290
153k
  
if (153k
State.getCallingConv() == CallingConv::AnyReg153k
) {
1291
0
    if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1292
0
      return false;
1293
0
  }
1294
153k
1295
153k
  
if (153k
State.getCallingConv() == CallingConv::Win64153k
) {
1296
54
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1297
54
      return false;
1298
54
  }
1299
153k
1300
153k
  
if (153k
State.getCallingConv() == CallingConv::X86_64_SysV153k
) {
1301
22
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1302
22
      return false;
1303
22
  }
1304
153k
1305
153k
  
if (153k
State.getCallingConv() == CallingConv::X86_VectorCall153k
) {
1306
152
    if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1307
152
      return false;
1308
152
  }
1309
153k
1310
153k
  
if (153k
State.getCallingConv() == CallingConv::HHVM153k
) {
1311
112
    if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1312
112
      return false;
1313
112
  }
1314
153k
1315
153k
  
if (153k
State.getCallingConv() == CallingConv::HHVM_C153k
) {
1316
25
    if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1317
25
      return false;
1318
25
  }
1319
153k
1320
153k
  
if (153k
State.getCallingConv() == CallingConv::X86_RegCall153k
) {
1321
380
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()380
) {
1322
195
      if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1323
195
        return false;
1324
195
    }
1325
380
  }
1326
153k
1327
153k
  
if (153k
State.getCallingConv() == CallingConv::X86_RegCall153k
) {
1328
185
    if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1329
185
      return false;
1330
185
  }
1331
153k
1332
153k
  
if (153k
State.getCallingConv() == CallingConv::X86_INTR153k
) {
1333
19
    if (!CC_X86_64_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1334
19
      return false;
1335
19
  }
1336
153k
1337
153k
  
if (153k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()153k
) {
1338
2.05k
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1339
2.04k
      return false;
1340
2.05k
  }
1341
153k
1342
151k
  
if (151k
!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)151k
)
1343
150k
    return false;
1344
151k
1345
200
  return true;  // CC didn't match.
1346
154k
}
X86ISelLowering.cpp:CC_X86_64(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1273
152k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1274
152k
1275
152k
  if (
State.getCallingConv() == CallingConv::GHC152k
) {
1276
62
    if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1277
62
      return false;
1278
62
  }
1279
152k
1280
152k
  
if (152k
State.getCallingConv() == CallingConv::HiPE152k
) {
1281
42
    if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1282
42
      return false;
1283
42
  }
1284
152k
1285
152k
  
if (152k
State.getCallingConv() == CallingConv::WebKit_JS152k
) {
1286
49
    if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1287
49
      return false;
1288
49
  }
1289
152k
1290
152k
  
if (152k
State.getCallingConv() == CallingConv::AnyReg152k
) {
1291
0
    if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1292
0
      return false;
1293
0
  }
1294
152k
1295
152k
  
if (152k
State.getCallingConv() == CallingConv::Win64152k
) {
1296
54
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1297
54
      return false;
1298
54
  }
1299
152k
1300
152k
  
if (152k
State.getCallingConv() == CallingConv::X86_64_SysV152k
) {
1301
22
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1302
22
      return false;
1303
22
  }
1304
152k
1305
152k
  
if (152k
State.getCallingConv() == CallingConv::X86_VectorCall152k
) {
1306
152
    if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1307
152
      return false;
1308
152
  }
1309
152k
1310
152k
  
if (152k
State.getCallingConv() == CallingConv::HHVM152k
) {
1311
112
    if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1312
112
      return false;
1313
112
  }
1314
152k
1315
152k
  
if (152k
State.getCallingConv() == CallingConv::HHVM_C152k
) {
1316
25
    if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1317
25
      return false;
1318
25
  }
1319
152k
1320
152k
  
if (152k
State.getCallingConv() == CallingConv::X86_RegCall152k
) {
1321
380
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()380
) {
1322
195
      if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1323
195
        return false;
1324
195
    }
1325
380
  }
1326
152k
1327
152k
  
if (152k
State.getCallingConv() == CallingConv::X86_RegCall152k
) {
1328
185
    if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1329
185
      return false;
1330
185
  }
1331
152k
1332
151k
  
if (151k
State.getCallingConv() == CallingConv::X86_INTR151k
) {
1333
19
    if (!CC_X86_64_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1334
19
      return false;
1335
19
  }
1336
151k
1337
151k
  
if (151k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()151k
) {
1338
2.05k
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1339
2.04k
      return false;
1340
2.05k
  }
1341
151k
1342
149k
  
if (149k
!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)149k
)
1343
149k
    return false;
1344
149k
1345
200
  return true;  // CC didn't match.
1346
152k
}
X86CallLowering.cpp:CC_X86_64(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1273
584
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1274
584
1275
584
  if (
State.getCallingConv() == CallingConv::GHC584
) {
1276
0
    if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1277
0
      return false;
1278
0
  }
1279
584
1280
584
  
if (584
State.getCallingConv() == CallingConv::HiPE584
) {
1281
0
    if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1282
0
      return false;
1283
0
  }
1284
584
1285
584
  
if (584
State.getCallingConv() == CallingConv::WebKit_JS584
) {
1286
0
    if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1287
0
      return false;
1288
0
  }
1289
584
1290
584
  
if (584
State.getCallingConv() == CallingConv::AnyReg584
) {
1291
0
    if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1292
0
      return false;
1293
0
  }
1294
584
1295
584
  
if (584
State.getCallingConv() == CallingConv::Win64584
) {
1296
0
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1297
0
      return false;
1298
0
  }
1299
584
1300
584
  
if (584
State.getCallingConv() == CallingConv::X86_64_SysV584
) {
1301
0
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1302
0
      return false;
1303
0
  }
1304
584
1305
584
  
if (584
State.getCallingConv() == CallingConv::X86_VectorCall584
) {
1306
0
    if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1307
0
      return false;
1308
0
  }
1309
584
1310
584
  
if (584
State.getCallingConv() == CallingConv::HHVM584
) {
1311
0
    if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1312
0
      return false;
1313
0
  }
1314
584
1315
584
  
if (584
State.getCallingConv() == CallingConv::HHVM_C584
) {
1316
0
    if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1317
0
      return false;
1318
0
  }
1319
584
1320
584
  
if (584
State.getCallingConv() == CallingConv::X86_RegCall584
) {
1321
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()0
) {
1322
0
      if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1323
0
        return false;
1324
0
    }
1325
0
  }
1326
584
1327
584
  
if (584
State.getCallingConv() == CallingConv::X86_RegCall584
) {
1328
0
    if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1329
0
      return false;
1330
0
  }
1331
584
1332
584
  
if (584
State.getCallingConv() == CallingConv::X86_INTR584
) {
1333
0
    if (!CC_X86_64_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1334
0
      return false;
1335
0
  }
1336
584
1337
584
  
if (584
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()584
) {
1338
0
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1339
0
      return false;
1340
0
  }
1341
584
1342
584
  
if (584
!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)584
)
1343
584
    return false;
1344
584
1345
0
  return true;  // CC didn't match.
1346
584
}
X86FastISel.cpp:CC_X86_64(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1273
751
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1274
751
1275
751
  if (
State.getCallingConv() == CallingConv::GHC751
) {
1276
0
    if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1277
0
      return false;
1278
0
  }
1279
751
1280
751
  
if (751
State.getCallingConv() == CallingConv::HiPE751
) {
1281
0
    if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1282
0
      return false;
1283
0
  }
1284
751
1285
751
  
if (751
State.getCallingConv() == CallingConv::WebKit_JS751
) {
1286
20
    if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1287
20
      return false;
1288
20
  }
1289
751
1290
731
  
if (731
State.getCallingConv() == CallingConv::AnyReg731
) {
1291
0
    if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1292
0
      return false;
1293
0
  }
1294
731
1295
731
  
if (731
State.getCallingConv() == CallingConv::Win64731
) {
1296
0
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1297
0
      return false;
1298
0
  }
1299
731
1300
731
  
if (731
State.getCallingConv() == CallingConv::X86_64_SysV731
) {
1301
0
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1302
0
      return false;
1303
0
  }
1304
731
1305
731
  
if (731
State.getCallingConv() == CallingConv::X86_VectorCall731
) {
1306
0
    if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1307
0
      return false;
1308
0
  }
1309
731
1310
731
  
if (731
State.getCallingConv() == CallingConv::HHVM731
) {
1311
0
    if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1312
0
      return false;
1313
0
  }
1314
731
1315
731
  
if (731
State.getCallingConv() == CallingConv::HHVM_C731
) {
1316
0
    if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1317
0
      return false;
1318
0
  }
1319
731
1320
731
  
if (731
State.getCallingConv() == CallingConv::X86_RegCall731
) {
1321
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()0
) {
1322
0
      if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1323
0
        return false;
1324
0
    }
1325
0
  }
1326
731
1327
731
  
if (731
State.getCallingConv() == CallingConv::X86_RegCall731
) {
1328
0
    if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1329
0
      return false;
1330
0
  }
1331
731
1332
731
  
if (731
State.getCallingConv() == CallingConv::X86_INTR731
) {
1333
0
    if (!CC_X86_64_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1334
0
      return false;
1335
0
  }
1336
731
1337
731
  
if (731
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()731
) {
1338
4
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1339
4
      return false;
1340
4
  }
1341
731
1342
727
  
if (727
!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)727
)
1343
727
    return false;
1344
727
1345
0
  return true;  // CC didn't match.
1346
751
}
1347
1348
1349
static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
1350
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
1351
0
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1352
0
1353
0
  if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1354
0
    return false;
1355
0
1356
0
  return true;  // CC didn't match.
1357
0
}
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_AnyReg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86ISelLowering.cpp:CC_X86_64_AnyReg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_AnyReg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
1358
1359
1360
static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
1361
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
1362
151k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
1363
151k
1364
151k
  if (
ArgFlags.isByVal()151k
) {
1365
104
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1366
104
    return false;
1367
104
  }
1368
151k
1369
151k
  
if (151k
LocVT == MVT::i1 ||
1370
151k
      LocVT == MVT::i8 ||
1371
146k
      LocVT == MVT::i16 ||
1372
151k
      
LocVT == MVT::v1i1144k
) {
1373
6.85k
    LocVT = MVT::i32;
1374
6.85k
    if (ArgFlags.isSExt())
1375
163
        LocInfo = CCValAssign::SExt;
1376
6.69k
    else 
if (6.69k
ArgFlags.isZExt()6.69k
)
1377
2.20k
        LocInfo = CCValAssign::ZExt;
1378
6.69k
    else
1379
4.48k
        LocInfo = CCValAssign::AExt;
1380
6.85k
  }
1381
151k
1382
151k
  if (
ArgFlags.isNest()151k
) {
1383
11
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()11
) {
1384
2
      if (unsigned 
Reg2
= State.AllocateReg(X86::R10D)) {
1385
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1386
2
        return false;
1387
2
      }
1388
2
    }
1389
11
  }
1390
151k
1391
151k
  
if (151k
ArgFlags.isNest()151k
) {
1392
9
    if (unsigned 
Reg9
= State.AllocateReg(X86::R10)) {
1393
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1394
9
      return false;
1395
9
    }
1396
9
  }
1397
151k
1398
151k
  
if (151k
ArgFlags.isSwiftSelf()151k
) {
1399
40
    if (
LocVT == MVT::i6440
) {
1400
40
      if (unsigned 
Reg40
= State.AllocateReg(X86::R13)) {
1401
40
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1402
40
        return false;
1403
40
      }
1404
40
    }
1405
40
  }
1406
151k
1407
151k
  
if (151k
ArgFlags.isSwiftError()151k
) {
1408
74
    if (
LocVT == MVT::i6474
) {
1409
74
      if (unsigned 
Reg74
= State.AllocateReg(X86::R12)) {
1410
74
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1411
74
        return false;
1412
74
      }
1413
74
    }
1414
74
  }
1415
151k
1416
150k
  
if (150k
State.getCallingConv() == CallingConv::Swift150k
) {
1417
134
    if (
ArgFlags.isSRet()134
) {
1418
6
      if (
LocVT == MVT::i646
) {
1419
6
        if (unsigned 
Reg6
= State.AllocateReg(X86::RAX)) {
1420
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1421
6
          return false;
1422
6
        }
1423
6
      }
1424
6
    }
1425
134
  }
1426
150k
1427
150k
  
if (150k
LocVT == MVT::i32150k
) {
1428
19.4k
    static const MCPhysReg RegList1[] = {
1429
19.4k
      X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1430
19.4k
    };
1431
19.4k
    if (unsigned 
Reg19.4k
= State.AllocateReg(RegList1)) {
1432
18.3k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1433
18.3k
      return false;
1434
18.3k
    }
1435
19.4k
  }
1436
150k
1437
132k
  
if (132k
LocVT == MVT::i64132k
) {
1438
62.1k
    static const MCPhysReg RegList2[] = {
1439
62.1k
      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1440
62.1k
    };
1441
62.1k
    if (unsigned 
Reg62.1k
= State.AllocateReg(RegList2)) {
1442
61.0k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1443
61.0k
      return false;
1444
61.0k
    }
1445
62.1k
  }
1446
132k
1447
71.5k
  
if (71.5k
LocVT == MVT::x86mmx71.5k
) {
1448
209
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()209
) {
1449
12
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()12
) {
1450
12
        LocVT = MVT::v2i64;
1451
12
        if (ArgFlags.isSExt())
1452
0
                LocInfo = CCValAssign::SExt;
1453
12
        else 
if (12
ArgFlags.isZExt()12
)
1454
0
                LocInfo = CCValAssign::ZExt;
1455
12
        else
1456
12
                LocInfo = CCValAssign::AExt;
1457
12
      }
1458
12
    }
1459
209
  }
1460
71.5k
1461
71.5k
  if (
LocVT == MVT::v2i171.5k
) {
1462
32
    LocVT = MVT::v2i64;
1463
32
    if (ArgFlags.isSExt())
1464
0
        LocInfo = CCValAssign::SExt;
1465
32
    else 
if (32
ArgFlags.isZExt()32
)
1466
0
        LocInfo = CCValAssign::ZExt;
1467
32
    else
1468
32
        LocInfo = CCValAssign::AExt;
1469
32
  }
1470
71.5k
1471
71.5k
  if (
LocVT == MVT::v4i171.5k
) {
1472
49
    LocVT = MVT::v4i32;
1473
49
    if (ArgFlags.isSExt())
1474
0
        LocInfo = CCValAssign::SExt;
1475
49
    else 
if (49
ArgFlags.isZExt()49
)
1476
0
        LocInfo = CCValAssign::ZExt;
1477
49
    else
1478
49
        LocInfo = CCValAssign::AExt;
1479
49
  }
1480
71.5k
1481
71.5k
  if (
LocVT == MVT::v8i171.5k
) {
1482
94
    LocVT = MVT::v8i16;
1483
94
    if (ArgFlags.isSExt())
1484
0
        LocInfo = CCValAssign::SExt;
1485
94
    else 
if (94
ArgFlags.isZExt()94
)
1486
0
        LocInfo = CCValAssign::ZExt;
1487
94
    else
1488
94
        LocInfo = CCValAssign::AExt;
1489
94
  }
1490
71.5k
1491
71.5k
  if (
LocVT == MVT::v16i171.5k
) {
1492
124
    LocVT = MVT::v16i8;
1493
124
    if (ArgFlags.isSExt())
1494
0
        LocInfo = CCValAssign::SExt;
1495
124
    else 
if (124
ArgFlags.isZExt()124
)
1496
0
        LocInfo = CCValAssign::ZExt;
1497
124
    else
1498
124
        LocInfo = CCValAssign::AExt;
1499
124
  }
1500
71.5k
1501
71.5k
  if (
LocVT == MVT::v32i171.5k
) {
1502
24
    LocVT = MVT::v32i8;
1503
24
    if (ArgFlags.isSExt())
1504
0
        LocInfo = CCValAssign::SExt;
1505
24
    else 
if (24
ArgFlags.isZExt()24
)
1506
0
        LocInfo = CCValAssign::ZExt;
1507
24
    else
1508
24
        LocInfo = CCValAssign::AExt;
1509
24
  }
1510
71.5k
1511
71.5k
  if (
LocVT == MVT::v64i171.5k
) {
1512
5
    LocVT = MVT::v64i8;
1513
5
    if (ArgFlags.isSExt())
1514
0
        LocInfo = CCValAssign::SExt;
1515
5
    else 
if (5
ArgFlags.isZExt()5
)
1516
0
        LocInfo = CCValAssign::ZExt;
1517
5
    else
1518
5
        LocInfo = CCValAssign::AExt;
1519
5
  }
1520
71.5k
1521
71.5k
  if (LocVT == MVT::f32 ||
1522
69.1k
      LocVT == MVT::f64 ||
1523
66.6k
      LocVT == MVT::f128 ||
1524
66.2k
      LocVT == MVT::v16i8 ||
1525
61.5k
      LocVT == MVT::v8i16 ||
1526
55.6k
      LocVT == MVT::v4i32 ||
1527
48.1k
      LocVT == MVT::v2i64 ||
1528
40.4k
      LocVT == MVT::v4f32 ||
1529
71.5k
      
LocVT == MVT::v2f6434.1k
) {
1530
41.2k
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()41.2k
) {
1531
41.2k
      static const MCPhysReg RegList3[] = {
1532
41.2k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1533
41.2k
      };
1534
41.2k
      if (unsigned 
Reg41.2k
= State.AllocateReg(RegList3)) {
1535
39.5k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1536
39.5k
        return false;
1537
39.5k
      }
1538
41.2k
    }
1539
41.2k
  }
1540
71.5k
1541
32.0k
  
if (32.0k
!State.isVarArg()32.0k
) {
1542
31.7k
    if (LocVT == MVT::v32i8 ||
1543
29.0k
        LocVT == MVT::v16i16 ||
1544
25.6k
        LocVT == MVT::v8i32 ||
1545
22.4k
        LocVT == MVT::v4i64 ||
1546
18.8k
        LocVT == MVT::v8f32 ||
1547
31.7k
        
LocVT == MVT::v4f6415.3k
) {
1548
19.4k
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasFp256()19.4k
) {
1549
19.4k
        static const MCPhysReg RegList4[] = {
1550
19.4k
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1551
19.4k
        };
1552
19.4k
        if (unsigned 
Reg19.4k
= State.AllocateReg(RegList4)) {
1553
19.3k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1554
19.3k
          return false;
1555
19.3k
        }
1556
19.4k
      }
1557
19.4k
    }
1558
31.7k
  }
1559
32.0k
1560
12.6k
  
if (12.6k
!State.isVarArg()12.6k
) {
1561
12.3k
    if (LocVT == MVT::v64i8 ||
1562
11.9k
        LocVT == MVT::v32i16 ||
1563
11.2k
        LocVT == MVT::v16i32 ||
1564
9.46k
        LocVT == MVT::v8i64 ||
1565
7.23k
        LocVT == MVT::v16f32 ||
1566
12.3k
        
LocVT == MVT::v8f645.66k
) {
1567
8.11k
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()8.11k
) {
1568
8.11k
        static const MCPhysReg RegList5[] = {
1569
8.11k
          X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1570
8.11k
        };
1571
8.11k
        if (unsigned 
Reg8.11k
= State.AllocateReg(RegList5)) {
1572
8.11k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1573
8.11k
          return false;
1574
8.11k
        }
1575
8.11k
      }
1576
8.11k
    }
1577
12.3k
  }
1578
12.6k
1579
4.53k
  
if (4.53k
LocVT == MVT::i32 ||
1580
3.39k
      LocVT == MVT::i64 ||
1581
2.35k
      LocVT == MVT::f32 ||
1582
4.53k
      
LocVT == MVT::f642.29k
) {
1583
2.23k
    unsigned Offset6 = State.AllocateStack(8, 8);
1584
2.23k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1585
2.23k
    return false;
1586
2.23k
  }
1587
4.53k
1588
2.29k
  
if (2.29k
LocVT == MVT::f80 ||
1589
2.29k
      
LocVT == MVT::f1281.97k
) {
1590
447
    unsigned Offset7 = State.AllocateStack(
1591
447
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
1592
447
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
1593
447
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1594
447
    return false;
1595
447
  }
1596
2.29k
1597
1.85k
  
if (1.85k
LocVT == MVT::v16i8 ||
1598
1.80k
      LocVT == MVT::v8i16 ||
1599
1.78k
      LocVT == MVT::v4i32 ||
1600
1.71k
      LocVT == MVT::v2i64 ||
1601
374
      LocVT == MVT::v4f32 ||
1602
1.85k
      
LocVT == MVT::v2f64338
) {
1603
1.60k
    unsigned Offset8 = State.AllocateStack(16, 16);
1604
1.60k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1605
1.60k
    return false;
1606
1.60k
  }
1607
1.85k
1608
247
  
if (247
LocVT == MVT::v32i8 ||
1609
246
      LocVT == MVT::v16i16 ||
1610
246
      LocVT == MVT::v8i32 ||
1611
246
      LocVT == MVT::v4i64 ||
1612
222
      LocVT == MVT::v8f32 ||
1613
247
      
LocVT == MVT::v4f64217
) {
1614
45
    unsigned Offset9 = State.AllocateStack(32, 32);
1615
45
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1616
45
    return false;
1617
45
  }
1618
247
1619
202
  
if (202
LocVT == MVT::v16i32 ||
1620
201
      LocVT == MVT::v8i64 ||
1621
201
      LocVT == MVT::v16f32 ||
1622
202
      
LocVT == MVT::v8f64201
) {
1623
0
    unsigned Offset10 = State.AllocateStack(64, 64);
1624
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1625
0
    return false;
1626
0
  }
1627
202
1628
202
  return true;  // CC didn't match.
1629
151k
}
X86ISelLowering.cpp:CC_X86_64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1362
149k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
1363
149k
1364
149k
  if (
ArgFlags.isByVal()149k
) {
1365
94
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1366
94
    return false;
1367
94
  }
1368
149k
1369
149k
  
if (149k
LocVT == MVT::i1 ||
1370
149k
      LocVT == MVT::i8 ||
1371
144k
      LocVT == MVT::i16 ||
1372
149k
      
LocVT == MVT::v1i1143k
) {
1373
6.78k
    LocVT = MVT::i32;
1374
6.78k
    if (ArgFlags.isSExt())
1375
161
        LocInfo = CCValAssign::SExt;
1376
6.62k
    else 
if (6.62k
ArgFlags.isZExt()6.62k
)
1377
2.19k
        LocInfo = CCValAssign::ZExt;
1378
6.62k
    else
1379
4.43k
        LocInfo = CCValAssign::AExt;
1380
6.78k
  }
1381
149k
1382
149k
  if (
ArgFlags.isNest()149k
) {
1383
11
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()11
) {
1384
2
      if (unsigned 
Reg2
= State.AllocateReg(X86::R10D)) {
1385
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1386
2
        return false;
1387
2
      }
1388
2
    }
1389
11
  }
1390
149k
1391
149k
  
if (149k
ArgFlags.isNest()149k
) {
1392
9
    if (unsigned 
Reg9
= State.AllocateReg(X86::R10)) {
1393
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1394
9
      return false;
1395
9
    }
1396
9
  }
1397
149k
1398
149k
  
if (149k
ArgFlags.isSwiftSelf()149k
) {
1399
37
    if (
LocVT == MVT::i6437
) {
1400
37
      if (unsigned 
Reg37
= State.AllocateReg(X86::R13)) {
1401
37
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1402
37
        return false;
1403
37
      }
1404
37
    }
1405
37
  }
1406
149k
1407
149k
  
if (149k
ArgFlags.isSwiftError()149k
) {
1408
74
    if (
LocVT == MVT::i6474
) {
1409
74
      if (unsigned 
Reg74
= State.AllocateReg(X86::R12)) {
1410
74
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1411
74
        return false;
1412
74
      }
1413
74
    }
1414
74
  }
1415
149k
1416
149k
  
if (149k
State.getCallingConv() == CallingConv::Swift149k
) {
1417
131
    if (
ArgFlags.isSRet()131
) {
1418
6
      if (
LocVT == MVT::i646
) {
1419
6
        if (unsigned 
Reg6
= State.AllocateReg(X86::RAX)) {
1420
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1421
6
          return false;
1422
6
        }
1423
6
      }
1424
6
    }
1425
131
  }
1426
149k
1427
149k
  
if (149k
LocVT == MVT::i32149k
) {
1428
19.0k
    static const MCPhysReg RegList1[] = {
1429
19.0k
      X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1430
19.0k
    };
1431
19.0k
    if (unsigned 
Reg19.0k
= State.AllocateReg(RegList1)) {
1432
17.9k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1433
17.9k
      return false;
1434
17.9k
    }
1435
19.0k
  }
1436
149k
1437
131k
  
if (131k
LocVT == MVT::i64131k
) {
1438
61.5k
    static const MCPhysReg RegList2[] = {
1439
61.5k
      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1440
61.5k
    };
1441
61.5k
    if (unsigned 
Reg61.5k
= State.AllocateReg(RegList2)) {
1442
60.5k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1443
60.5k
      return false;
1444
60.5k
    }
1445
61.5k
  }
1446
131k
1447
71.2k
  
if (71.2k
LocVT == MVT::x86mmx71.2k
) {
1448
208
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()208
) {
1449
11
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()11
) {
1450
11
        LocVT = MVT::v2i64;
1451
11
        if (ArgFlags.isSExt())
1452
0
                LocInfo = CCValAssign::SExt;
1453
11
        else 
if (11
ArgFlags.isZExt()11
)
1454
0
                LocInfo = CCValAssign::ZExt;
1455
11
        else
1456
11
                LocInfo = CCValAssign::AExt;
1457
11
      }
1458
11
    }
1459
208
  }
1460
71.2k
1461
71.2k
  if (
LocVT == MVT::v2i171.2k
) {
1462
32
    LocVT = MVT::v2i64;
1463
32
    if (ArgFlags.isSExt())
1464
0
        LocInfo = CCValAssign::SExt;
1465
32
    else 
if (32
ArgFlags.isZExt()32
)
1466
0
        LocInfo = CCValAssign::ZExt;
1467
32
    else
1468
32
        LocInfo = CCValAssign::AExt;
1469
32
  }
1470
71.2k
1471
71.2k
  if (
LocVT == MVT::v4i171.2k
) {
1472
49
    LocVT = MVT::v4i32;
1473
49
    if (ArgFlags.isSExt())
1474
0
        LocInfo = CCValAssign::SExt;
1475
49
    else 
if (49
ArgFlags.isZExt()49
)
1476
0
        LocInfo = CCValAssign::ZExt;
1477
49
    else
1478
49
        LocInfo = CCValAssign::AExt;
1479
49
  }
1480
71.2k
1481
71.2k
  if (
LocVT == MVT::v8i171.2k
) {
1482
94
    LocVT = MVT::v8i16;
1483
94
    if (ArgFlags.isSExt())
1484
0
        LocInfo = CCValAssign::SExt;
1485
94
    else 
if (94
ArgFlags.isZExt()94
)
1486
0
        LocInfo = CCValAssign::ZExt;
1487
94
    else
1488
94
        LocInfo = CCValAssign::AExt;
1489
94
  }
1490
71.2k
1491
71.2k
  if (
LocVT == MVT::v16i171.2k
) {
1492
124
    LocVT = MVT::v16i8;
1493
124
    if (ArgFlags.isSExt())
1494
0
        LocInfo = CCValAssign::SExt;
1495
124
    else 
if (124
ArgFlags.isZExt()124
)
1496
0
        LocInfo = CCValAssign::ZExt;
1497
124
    else
1498
124
        LocInfo = CCValAssign::AExt;
1499
124
  }
1500
71.2k
1501
71.2k
  if (
LocVT == MVT::v32i171.2k
) {
1502
24
    LocVT = MVT::v32i8;
1503
24
    if (ArgFlags.isSExt())
1504
0
        LocInfo = CCValAssign::SExt;
1505
24
    else 
if (24
ArgFlags.isZExt()24
)
1506
0
        LocInfo = CCValAssign::ZExt;
1507
24
    else
1508
24
        LocInfo = CCValAssign::AExt;
1509
24
  }
1510
71.2k
1511
71.2k
  if (
LocVT == MVT::v64i171.2k
) {
1512
5
    LocVT = MVT::v64i8;
1513
5
    if (ArgFlags.isSExt())
1514
0
        LocInfo = CCValAssign::SExt;
1515
5
    else 
if (5
ArgFlags.isZExt()5
)
1516
0
        LocInfo = CCValAssign::ZExt;
1517
5
    else
1518
5
        LocInfo = CCValAssign::AExt;
1519
5
  }
1520
71.2k
1521
71.2k
  if (LocVT == MVT::f32 ||
1522
68.8k
      LocVT == MVT::f64 ||
1523
66.4k
      LocVT == MVT::f128 ||
1524
66.0k
      LocVT == MVT::v16i8 ||
1525
61.3k
      LocVT == MVT::v8i16 ||
1526
55.4k
      LocVT == MVT::v4i32 ||
1527
48.0k
      LocVT == MVT::v2i64 ||
1528
40.3k
      LocVT == MVT::v4f32 ||
1529
71.2k
      
LocVT == MVT::v2f6434.0k
) {
1530
41.1k
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()41.1k
) {
1531
41.1k
      static const MCPhysReg RegList3[] = {
1532
41.1k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1533
41.1k
      };
1534
41.1k
      if (unsigned 
Reg41.1k
= State.AllocateReg(RegList3)) {
1535
39.3k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1536
39.3k
        return false;
1537
39.3k
      }
1538
41.1k
    }
1539
41.1k
  }
1540
71.2k
1541
31.8k
  
if (31.8k
!State.isVarArg()31.8k
) {
1542
31.5k
    if (LocVT == MVT::v32i8 ||
1543
28.9k
        LocVT == MVT::v16i16 ||
1544
25.5k
        LocVT == MVT::v8i32 ||
1545
22.3k
        LocVT == MVT::v4i64 ||
1546
18.8k
        LocVT == MVT::v8f32 ||
1547
31.5k
        
LocVT == MVT::v4f6415.2k
) {
1548
19.3k
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasFp256()19.3k
) {
1549
19.3k
        static const MCPhysReg RegList4[] = {
1550
19.3k
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1551
19.3k
        };
1552
19.3k
        if (unsigned 
Reg19.3k
= State.AllocateReg(RegList4)) {
1553
19.3k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1554
19.3k
          return false;
1555
19.3k
        }
1556
19.3k
      }
1557
19.3k
    }
1558
31.5k
  }
1559
31.8k
1560
12.5k
  
if (12.5k
!State.isVarArg()12.5k
) {
1561
12.2k
    if (LocVT == MVT::v64i8 ||
1562
11.8k
        LocVT == MVT::v32i16 ||
1563
11.2k
        LocVT == MVT::v16i32 ||
1564
9.42k
        LocVT == MVT::v8i64 ||
1565
7.20k
        LocVT == MVT::v16f32 ||
1566
12.2k
        
LocVT == MVT::v8f645.62k
) {
1567
8.08k
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()8.08k
) {
1568
8.08k
        static const MCPhysReg RegList5[] = {
1569
8.08k
          X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1570
8.08k
        };
1571
8.08k
        if (unsigned 
Reg8.08k
= State.AllocateReg(RegList5)) {
1572
8.08k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1573
8.08k
          return false;
1574
8.08k
        }
1575
8.08k
      }
1576
8.08k
    }
1577
12.2k
  }
1578
12.5k
1579
4.49k
  
if (4.49k
LocVT == MVT::i32 ||
1580
3.37k
      LocVT == MVT::i64 ||
1581
2.35k
      LocVT == MVT::f32 ||
1582
4.49k
      
LocVT == MVT::f642.29k
) {
1583
2.20k
    unsigned Offset6 = State.AllocateStack(8, 8);
1584
2.20k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1585
2.20k
    return false;
1586
2.20k
  }
1587
4.49k
1588
2.29k
  
if (2.29k
LocVT == MVT::f80 ||
1589
2.29k
      
LocVT == MVT::f1281.97k
) {
1590
447
    unsigned Offset7 = State.AllocateStack(
1591
447
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
1592
447
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
1593
447
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1594
447
    return false;
1595
447
  }
1596
2.29k
1597
1.85k
  
if (1.85k
LocVT == MVT::v16i8 ||
1598
1.80k
      LocVT == MVT::v8i16 ||
1599
1.78k
      LocVT == MVT::v4i32 ||
1600
1.71k
      LocVT == MVT::v2i64 ||
1601
374
      LocVT == MVT::v4f32 ||
1602
1.85k
      
LocVT == MVT::v2f64338
) {
1603
1.60k
    unsigned Offset8 = State.AllocateStack(16, 16);
1604
1.60k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1605
1.60k
    return false;
1606
1.60k
  }
1607
1.85k
1608
247
  
if (247
LocVT == MVT::v32i8 ||
1609
246
      LocVT == MVT::v16i16 ||
1610
246
      LocVT == MVT::v8i32 ||
1611
246
      LocVT == MVT::v4i64 ||
1612
222
      LocVT == MVT::v8f32 ||
1613
247
      
LocVT == MVT::v4f64217
) {
1614
45
    unsigned Offset9 = State.AllocateStack(32, 32);
1615
45
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1616
45
    return false;
1617
45
  }
1618
247
1619
202
  
if (202
LocVT == MVT::v16i32 ||
1620
201
      LocVT == MVT::v8i64 ||
1621
201
      LocVT == MVT::v16f32 ||
1622
202
      
LocVT == MVT::v8f64201
) {
1623
0
    unsigned Offset10 = State.AllocateStack(64, 64);
1624
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1625
0
    return false;
1626
0
  }
1627
202
1628
202
  return true;  // CC didn't match.
1629
149k
}
X86CallLowering.cpp:CC_X86_64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1362
584
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
1363
584
1364
584
  if (
ArgFlags.isByVal()584
) {
1365
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1366
0
    return false;
1367
0
  }
1368
584
1369
584
  
if (584
LocVT == MVT::i1 ||
1370
582
      LocVT == MVT::i8 ||
1371
547
      LocVT == MVT::i16 ||
1372
584
      
LocVT == MVT::v1i1526
) {
1373
58
    LocVT = MVT::i32;
1374
58
    if (ArgFlags.isSExt())
1375
2
        LocInfo = CCValAssign::SExt;
1376
56
    else 
if (56
ArgFlags.isZExt()56
)
1377
2
        LocInfo = CCValAssign::ZExt;
1378
56
    else
1379
54
        LocInfo = CCValAssign::AExt;
1380
58
  }
1381
584
1382
584
  if (
ArgFlags.isNest()584
) {
1383
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()0
) {
1384
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::R10D)) {
1385
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1386
0
        return false;
1387
0
      }
1388
0
    }
1389
0
  }
1390
584
1391
584
  
if (584
ArgFlags.isNest()584
) {
1392
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::R10)) {
1393
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1394
0
      return false;
1395
0
    }
1396
0
  }
1397
584
1398
584
  
if (584
ArgFlags.isSwiftSelf()584
) {
1399
0
    if (
LocVT == MVT::i640
) {
1400
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::R13)) {
1401
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1402
0
        return false;
1403
0
      }
1404
0
    }
1405
0
  }
1406
584
1407
584
  
if (584
ArgFlags.isSwiftError()584
) {
1408
0
    if (
LocVT == MVT::i640
) {
1409
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::R12)) {
1410
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1411
0
        return false;
1412
0
      }
1413
0
    }
1414
0
  }
1415
584
1416
584
  
if (584
State.getCallingConv() == CallingConv::Swift584
) {
1417
0
    if (
ArgFlags.isSRet()0
) {
1418
0
      if (
LocVT == MVT::i640
) {
1419
0
        if (unsigned 
Reg0
= State.AllocateReg(X86::RAX)) {
1420
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1421
0
          return false;
1422
0
        }
1423
0
      }
1424
0
    }
1425
0
  }
1426
584
1427
584
  
if (584
LocVT == MVT::i32584
) {
1428
179
    static const MCPhysReg RegList1[] = {
1429
179
      X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1430
179
    };
1431
179
    if (unsigned 
Reg179
= State.AllocateReg(RegList1)) {
1432
171
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1433
171
      return false;
1434
171
    }
1435
179
  }
1436
584
1437
413
  
if (413
LocVT == MVT::i64413
) {
1438
138
    static const MCPhysReg RegList2[] = {
1439
138
      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1440
138
    };
1441
138
    if (unsigned 
Reg138
= State.AllocateReg(RegList2)) {
1442
134
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1443
134
      return false;
1444
134
    }
1445
138
  }
1446
413
1447
279
  
if (279
LocVT == MVT::x86mmx279
) {
1448
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()0
) {
1449
0
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()0
) {
1450
0
        LocVT = MVT::v2i64;
1451
0
        if (ArgFlags.isSExt())
1452
0
                LocInfo = CCValAssign::SExt;
1453
0
        else 
if (0
ArgFlags.isZExt()0
)
1454
0
                LocInfo = CCValAssign::ZExt;
1455
0
        else
1456
0
                LocInfo = CCValAssign::AExt;
1457
0
      }
1458
0
    }
1459
0
  }
1460
279
1461
279
  if (
LocVT == MVT::v2i1279
) {
1462
0
    LocVT = MVT::v2i64;
1463
0
    if (ArgFlags.isSExt())
1464
0
        LocInfo = CCValAssign::SExt;
1465
0
    else 
if (0
ArgFlags.isZExt()0
)
1466
0
        LocInfo = CCValAssign::ZExt;
1467
0
    else
1468
0
        LocInfo = CCValAssign::AExt;
1469
0
  }
1470
279
1471
279
  if (
LocVT == MVT::v4i1279
) {
1472
0
    LocVT = MVT::v4i32;
1473
0
    if (ArgFlags.isSExt())
1474
0
        LocInfo = CCValAssign::SExt;
1475
0
    else 
if (0
ArgFlags.isZExt()0
)
1476
0
        LocInfo = CCValAssign::ZExt;
1477
0
    else
1478
0
        LocInfo = CCValAssign::AExt;
1479
0
  }
1480
279
1481
279
  if (
LocVT == MVT::v8i1279
) {
1482
0
    LocVT = MVT::v8i16;
1483
0
    if (ArgFlags.isSExt())
1484
0
        LocInfo = CCValAssign::SExt;
1485
0
    else 
if (0
ArgFlags.isZExt()0
)
1486
0
        LocInfo = CCValAssign::ZExt;
1487
0
    else
1488
0
        LocInfo = CCValAssign::AExt;
1489
0
  }
1490
279
1491
279
  if (
LocVT == MVT::v16i1279
) {
1492
0
    LocVT = MVT::v16i8;
1493
0
    if (ArgFlags.isSExt())
1494
0
        LocInfo = CCValAssign::SExt;
1495
0
    else 
if (0
ArgFlags.isZExt()0
)
1496
0
        LocInfo = CCValAssign::ZExt;
1497
0
    else
1498
0
        LocInfo = CCValAssign::AExt;
1499
0
  }
1500
279
1501
279
  if (
LocVT == MVT::v32i1279
) {
1502
0
    LocVT = MVT::v32i8;
1503
0
    if (ArgFlags.isSExt())
1504
0
        LocInfo = CCValAssign::SExt;
1505
0
    else 
if (0
ArgFlags.isZExt()0
)
1506
0
        LocInfo = CCValAssign::ZExt;
1507
0
    else
1508
0
        LocInfo = CCValAssign::AExt;
1509
0
  }
1510
279
1511
279
  if (
LocVT == MVT::v64i1279
) {
1512
0
    LocVT = MVT::v64i8;
1513
0
    if (ArgFlags.isSExt())
1514
0
        LocInfo = CCValAssign::SExt;
1515
0
    else 
if (0
ArgFlags.isZExt()0
)
1516
0
        LocInfo = CCValAssign::ZExt;
1517
0
    else
1518
0
        LocInfo = CCValAssign::AExt;
1519
0
  }
1520
279
1521
279
  if (LocVT == MVT::f32 ||
1522
240
      LocVT == MVT::f64 ||
1523
208
      LocVT == MVT::f128 ||
1524
208
      LocVT == MVT::v16i8 ||
1525
200
      LocVT == MVT::v8i16 ||
1526
190
      LocVT == MVT::v4i32 ||
1527
138
      LocVT == MVT::v2i64 ||
1528
128
      LocVT == MVT::v4f32 ||
1529
279
      
LocVT == MVT::v2f64112
) {
1530
167
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()167
) {
1531
167
      static const MCPhysReg RegList3[] = {
1532
167
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1533
167
      };
1534
167
      if (unsigned 
Reg167
= State.AllocateReg(RegList3)) {
1535
167
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1536
167
        return false;
1537
167
      }
1538
167
    }
1539
167
  }
1540
279
1541
112
  
if (112
!State.isVarArg()112
) {
1542
112
    if (LocVT == MVT::v32i8 ||
1543
96
        LocVT == MVT::v16i16 ||
1544
78
        LocVT == MVT::v8i32 ||
1545
56
        LocVT == MVT::v4i64 ||
1546
38
        LocVT == MVT::v8f32 ||
1547
112
        
LocVT == MVT::v4f6438
) {
1548
74
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasFp256()74
) {
1549
74
        static const MCPhysReg RegList4[] = {
1550
74
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1551
74
        };
1552
74
        if (unsigned 
Reg74
= State.AllocateReg(RegList4)) {
1553
74
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1554
74
          return false;
1555
74
        }
1556
74
      }
1557
74
    }
1558
112
  }
1559
112
1560
38
  
if (38
!State.isVarArg()38
) {
1561
38
    if (LocVT == MVT::v64i8 ||
1562
34
        LocVT == MVT::v32i16 ||
1563
28
        LocVT == MVT::v16i32 ||
1564
18
        LocVT == MVT::v8i64 ||
1565
12
        LocVT == MVT::v16f32 ||
1566
38
        
LocVT == MVT::v8f6412
) {
1567
26
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()26
) {
1568
26
        static const MCPhysReg RegList5[] = {
1569
26
          X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1570
26
        };
1571
26
        if (unsigned 
Reg26
= State.AllocateReg(RegList5)) {
1572
26
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1573
26
          return false;
1574
26
        }
1575
26
      }
1576
26
    }
1577
38
  }
1578
38
1579
12
  
if (12
LocVT == MVT::i32 ||
1580
4
      LocVT == MVT::i64 ||
1581
0
      LocVT == MVT::f32 ||
1582
12
      
LocVT == MVT::f640
) {
1583
12
    unsigned Offset6 = State.AllocateStack(8, 8);
1584
12
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1585
12
    return false;
1586
12
  }
1587
12
1588
0
  
if (0
LocVT == MVT::f80 ||
1589
0
      
LocVT == MVT::f1280
) {
1590
0
    unsigned Offset7 = State.AllocateStack(
1591
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
1592
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
1593
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1594
0
    return false;
1595
0
  }
1596
0
1597
0
  
if (0
LocVT == MVT::v16i8 ||
1598
0
      LocVT == MVT::v8i16 ||
1599
0
      LocVT == MVT::v4i32 ||
1600
0
      LocVT == MVT::v2i64 ||
1601
0
      LocVT == MVT::v4f32 ||
1602
0
      
LocVT == MVT::v2f640
) {
1603
0
    unsigned Offset8 = State.AllocateStack(16, 16);
1604
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1605
0
    return false;
1606
0
  }
1607
0
1608
0
  
if (0
LocVT == MVT::v32i8 ||
1609
0
      LocVT == MVT::v16i16 ||
1610
0
      LocVT == MVT::v8i32 ||
1611
0
      LocVT == MVT::v4i64 ||
1612
0
      LocVT == MVT::v8f32 ||
1613
0
      
LocVT == MVT::v4f640
) {
1614
0
    unsigned Offset9 = State.AllocateStack(32, 32);
1615
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1616
0
    return false;
1617
0
  }
1618
0
1619
0
  
if (0
LocVT == MVT::v16i32 ||
1620
0
      LocVT == MVT::v8i64 ||
1621
0
      LocVT == MVT::v16f32 ||
1622
0
      
LocVT == MVT::v8f640
) {
1623
0
    unsigned Offset10 = State.AllocateStack(64, 64);
1624
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1625
0
    return false;
1626
0
  }
1627
0
1628
0
  return true;  // CC didn't match.
1629
584
}
X86FastISel.cpp:CC_X86_64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1362
727
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
1363
727
1364
727
  if (
ArgFlags.isByVal()727
) {
1365
10
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1366
10
    return false;
1367
10
  }
1368
727
1369
717
  
if (717
LocVT == MVT::i1 ||
1370
717
      LocVT == MVT::i8 ||
1371
713
      LocVT == MVT::i16 ||
1372
717
      
LocVT == MVT::v1i1706
) {
1373
11
    LocVT = MVT::i32;
1374
11
    if (ArgFlags.isSExt())
1375
0
        LocInfo = CCValAssign::SExt;
1376
11
    else 
if (11
ArgFlags.isZExt()11
)
1377
7
        LocInfo = CCValAssign::ZExt;
1378
11
    else
1379
4
        LocInfo = CCValAssign::AExt;
1380
11
  }
1381
717
1382
717
  if (
ArgFlags.isNest()717
) {
1383
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()0
) {
1384
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::R10D)) {
1385
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1386
0
        return false;
1387
0
      }
1388
0
    }
1389
0
  }
1390
717
1391
717
  
if (717
ArgFlags.isNest()717
) {
1392
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::R10)) {
1393
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1394
0
      return false;
1395
0
    }
1396
0
  }
1397
717
1398
717
  
if (717
ArgFlags.isSwiftSelf()717
) {
1399
3
    if (
LocVT == MVT::i643
) {
1400
3
      if (unsigned 
Reg3
= State.AllocateReg(X86::R13)) {
1401
3
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1402
3
        return false;
1403
3
      }
1404
3
    }
1405
3
  }
1406
717
1407
714
  
if (714
ArgFlags.isSwiftError()714
) {
1408
0
    if (
LocVT == MVT::i640
) {
1409
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::R12)) {
1410
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1411
0
        return false;
1412
0
      }
1413
0
    }
1414
0
  }
1415
714
1416
714
  
if (714
State.getCallingConv() == CallingConv::Swift714
) {
1417
3
    if (
ArgFlags.isSRet()3
) {
1418
0
      if (
LocVT == MVT::i640
) {
1419
0
        if (unsigned 
Reg0
= State.AllocateReg(X86::RAX)) {
1420
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1421
0
          return false;
1422
0
        }
1423
0
      }
1424
0
    }
1425
3
  }
1426
714
1427
714
  
if (714
LocVT == MVT::i32714
) {
1428
283
    static const MCPhysReg RegList1[] = {
1429
283
      X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1430
283
    };
1431
283
    if (unsigned 
Reg283
= State.AllocateReg(RegList1)) {
1432
274
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1433
274
      return false;
1434
274
    }
1435
283
  }
1436
714
1437
440
  
if (440
LocVT == MVT::i64440
) {
1438
416
    static const MCPhysReg RegList2[] = {
1439
416
      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1440
416
    };
1441
416
    if (unsigned 
Reg416
= State.AllocateReg(RegList2)) {
1442
404
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1443
404
      return false;
1444
404
    }
1445
416
  }
1446
440
1447
36
  
if (36
LocVT == MVT::x86mmx36
) {
1448
1
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()1
) {
1449
1
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()1
) {
1450
1
        LocVT = MVT::v2i64;
1451
1
        if (ArgFlags.isSExt())
1452
0
                LocInfo = CCValAssign::SExt;
1453
1
        else 
if (1
ArgFlags.isZExt()1
)
1454
0
                LocInfo = CCValAssign::ZExt;
1455
1
        else
1456
1
                LocInfo = CCValAssign::AExt;
1457
1
      }
1458
1
    }
1459
1
  }
1460
36
1461
36
  if (
LocVT == MVT::v2i136
) {
1462
0
    LocVT = MVT::v2i64;
1463
0
    if (ArgFlags.isSExt())
1464
0
        LocInfo = CCValAssign::SExt;
1465
0
    else 
if (0
ArgFlags.isZExt()0
)
1466
0
        LocInfo = CCValAssign::ZExt;
1467
0
    else
1468
0
        LocInfo = CCValAssign::AExt;
1469
0
  }
1470
36
1471
36
  if (
LocVT == MVT::v4i136
) {
1472
0
    LocVT = MVT::v4i32;
1473
0
    if (ArgFlags.isSExt())
1474
0
        LocInfo = CCValAssign::SExt;
1475
0
    else 
if (0
ArgFlags.isZExt()0
)
1476
0
        LocInfo = CCValAssign::ZExt;
1477
0
    else
1478
0
        LocInfo = CCValAssign::AExt;
1479
0
  }
1480
36
1481
36
  if (
LocVT == MVT::v8i136
) {
1482
0
    LocVT = MVT::v8i16;
1483
0
    if (ArgFlags.isSExt())
1484
0
        LocInfo = CCValAssign::SExt;
1485
0
    else 
if (0
ArgFlags.isZExt()0
)
1486
0
        LocInfo = CCValAssign::ZExt;
1487
0
    else
1488
0
        LocInfo = CCValAssign::AExt;
1489
0
  }
1490
36
1491
36
  if (
LocVT == MVT::v16i136
) {
1492
0
    LocVT = MVT::v16i8;
1493
0
    if (ArgFlags.isSExt())
1494
0
        LocInfo = CCValAssign::SExt;
1495
0
    else 
if (0
ArgFlags.isZExt()0
)
1496
0
        LocInfo = CCValAssign::ZExt;
1497
0
    else
1498
0
        LocInfo = CCValAssign::AExt;
1499
0
  }
1500
36
1501
36
  if (
LocVT == MVT::v32i136
) {
1502
0
    LocVT = MVT::v32i8;
1503
0
    if (ArgFlags.isSExt())
1504
0
        LocInfo = CCValAssign::SExt;
1505
0
    else 
if (0
ArgFlags.isZExt()0
)
1506
0
        LocInfo = CCValAssign::ZExt;
1507
0
    else
1508
0
        LocInfo = CCValAssign::AExt;
1509
0
  }
1510
36
1511
36
  if (
LocVT == MVT::v64i136
) {
1512
0
    LocVT = MVT::v64i8;
1513
0
    if (ArgFlags.isSExt())
1514
0
        LocInfo = CCValAssign::SExt;
1515
0
    else 
if (0
ArgFlags.isZExt()0
)
1516
0
        LocInfo = CCValAssign::ZExt;
1517
0
    else
1518
0
        LocInfo = CCValAssign::AExt;
1519
0
  }
1520
36
1521
36
  if (LocVT == MVT::f32 ||
1522
35
      LocVT == MVT::f64 ||
1523
25
      LocVT == MVT::f128 ||
1524
25
      LocVT == MVT::v16i8 ||
1525
25
      LocVT == MVT::v8i16 ||
1526
25
      LocVT == MVT::v4i32 ||
1527
25
      LocVT == MVT::v2i64 ||
1528
24
      LocVT == MVT::v4f32 ||
1529
36
      
LocVT == MVT::v2f6424
) {
1530
12
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()12
) {
1531
12
      static const MCPhysReg RegList3[] = {
1532
12
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1533
12
      };
1534
12
      if (unsigned 
Reg12
= State.AllocateReg(RegList3)) {
1535
12
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1536
12
        return false;
1537
12
      }
1538
12
    }
1539
12
  }
1540
36
1541
24
  
if (24
!State.isVarArg()24
) {
1542
24
    if (LocVT == MVT::v32i8 ||
1543
24
        LocVT == MVT::v16i16 ||
1544
24
        LocVT == MVT::v8i32 ||
1545
24
        LocVT == MVT::v4i64 ||
1546
23
        LocVT == MVT::v8f32 ||
1547
24
        
LocVT == MVT::v4f6422
) {
1548
3
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasFp256()3
) {
1549
3
        static const MCPhysReg RegList4[] = {
1550
3
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1551
3
        };
1552
3
        if (unsigned 
Reg3
= State.AllocateReg(RegList4)) {
1553
3
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1554
3
          return false;
1555
3
        }
1556
3
      }
1557
3
    }
1558
24
  }
1559
24
1560
21
  
if (21
!State.isVarArg()21
) {
1561
21
    if (LocVT == MVT::v64i8 ||
1562
21
        LocVT == MVT::v32i16 ||
1563
21
        LocVT == MVT::v16i32 ||
1564
21
        LocVT == MVT::v8i64 ||
1565
21
        LocVT == MVT::v16f32 ||
1566
21
        
LocVT == MVT::v8f6421
) {
1567
0
      if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()0
) {
1568
0
        static const MCPhysReg RegList5[] = {
1569
0
          X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1570
0
        };
1571
0
        if (unsigned 
Reg0
= State.AllocateReg(RegList5)) {
1572
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1573
0
          return false;
1574
0
        }
1575
0
      }
1576
0
    }
1577
21
  }
1578
21
1579
21
  
if (21
LocVT == MVT::i32 ||
1580
12
      LocVT == MVT::i64 ||
1581
0
      LocVT == MVT::f32 ||
1582
21
      
LocVT == MVT::f640
) {
1583
21
    unsigned Offset6 = State.AllocateStack(8, 8);
1584
21
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1585
21
    return false;
1586
21
  }
1587
21
1588
0
  
if (0
LocVT == MVT::f80 ||
1589
0
      
LocVT == MVT::f1280
) {
1590
0
    unsigned Offset7 = State.AllocateStack(
1591
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
1592
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
1593
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1594
0
    return false;
1595
0
  }
1596
0
1597
0
  
if (0
LocVT == MVT::v16i8 ||
1598
0
      LocVT == MVT::v8i16 ||
1599
0
      LocVT == MVT::v4i32 ||
1600
0
      LocVT == MVT::v2i64 ||
1601
0
      LocVT == MVT::v4f32 ||
1602
0
      
LocVT == MVT::v2f640
) {
1603
0
    unsigned Offset8 = State.AllocateStack(16, 16);
1604
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1605
0
    return false;
1606
0
  }
1607
0
1608
0
  
if (0
LocVT == MVT::v32i8 ||
1609
0
      LocVT == MVT::v16i16 ||
1610
0
      LocVT == MVT::v8i32 ||
1611
0
      LocVT == MVT::v4i64 ||
1612
0
      LocVT == MVT::v8f32 ||
1613
0
      
LocVT == MVT::v4f640
) {
1614
0
    unsigned Offset9 = State.AllocateStack(32, 32);
1615
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1616
0
    return false;
1617
0
  }
1618
0
1619
0
  
if (0
LocVT == MVT::v16i32 ||
1620
0
      LocVT == MVT::v8i64 ||
1621
0
      LocVT == MVT::v16f32 ||
1622
0
      
LocVT == MVT::v8f640
) {
1623
0
    unsigned Offset10 = State.AllocateStack(64, 64);
1624
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1625
0
    return false;
1626
0
  }
1627
0
1628
0
  return true;  // CC didn't match.
1629
727
}
1630
1631
1632
static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
1633
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
1634
62
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
1635
62
1636
62
  if (LocVT == MVT::i8 ||
1637
62
      LocVT == MVT::i16 ||
1638
62
      
LocVT == MVT::i3262
) {
1639
0
    LocVT = MVT::i64;
1640
0
    if (ArgFlags.isSExt())
1641
0
        LocInfo = CCValAssign::SExt;
1642
0
    else 
if (0
ArgFlags.isZExt()0
)
1643
0
        LocInfo = CCValAssign::ZExt;
1644
0
    else
1645
0
        LocInfo = CCValAssign::AExt;
1646
0
  }
1647
62
1648
62
  if (
LocVT == MVT::i6462
) {
1649
56
    static const MCPhysReg RegList1[] = {
1650
56
      X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1651
56
    };
1652
56
    if (unsigned 
Reg56
= State.AllocateReg(RegList1)) {
1653
56
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1654
56
      return false;
1655
56
    }
1656
56
  }
1657
62
1658
6
  
if (6
LocVT == MVT::f32 ||
1659
2
      LocVT == MVT::f64 ||
1660
0
      LocVT == MVT::v16i8 ||
1661
0
      LocVT == MVT::v8i16 ||
1662
0
      LocVT == MVT::v4i32 ||
1663
0
      LocVT == MVT::v2i64 ||
1664
0
      LocVT == MVT::v4f32 ||
1665
6
      
LocVT == MVT::v2f640
) {
1666
6
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()6
) {
1667
6
      static const MCPhysReg RegList2[] = {
1668
6
        X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
1669
6
      };
1670
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList2)) {
1671
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1672
6
        return false;
1673
6
      }
1674
6
    }
1675
6
  }
1676
6
1677
0
  
if (0
LocVT == MVT::v32i8 ||
1678
0
      LocVT == MVT::v16i16 ||
1679
0
      LocVT == MVT::v8i32 ||
1680
0
      LocVT == MVT::v4i64 ||
1681
0
      LocVT == MVT::v8f32 ||
1682
0
      
LocVT == MVT::v4f640
) {
1683
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()0
) {
1684
0
      static const MCPhysReg RegList3[] = {
1685
0
        X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
1686
0
      };
1687
0
      if (unsigned 
Reg0
= State.AllocateReg(RegList3)) {
1688
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1689
0
        return false;
1690
0
      }
1691
0
    }
1692
0
  }
1693
0
1694
0
  
if (0
LocVT == MVT::v64i8 ||
1695
0
      LocVT == MVT::v32i16 ||
1696
0
      LocVT == MVT::v16i32 ||
1697
0
      LocVT == MVT::v8i64 ||
1698
0
      LocVT == MVT::v16f32 ||
1699
0
      
LocVT == MVT::v8f640
) {
1700
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()0
) {
1701
0
      static const MCPhysReg RegList4[] = {
1702
0
        X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
1703
0
      };
1704
0
      if (unsigned 
Reg0
= State.AllocateReg(RegList4)) {
1705
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1706
0
        return false;
1707
0
      }
1708
0
    }
1709
0
  }
1710
0
1711
0
  return true;  // CC didn't match.
1712
62
}
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_64_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1634
62
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
1635
62
1636
62
  if (LocVT == MVT::i8 ||
1637
62
      LocVT == MVT::i16 ||
1638
62
      
LocVT == MVT::i3262
) {
1639
0
    LocVT = MVT::i64;
1640
0
    if (ArgFlags.isSExt())
1641
0
        LocInfo = CCValAssign::SExt;
1642
0
    else 
if (0
ArgFlags.isZExt()0
)
1643
0
        LocInfo = CCValAssign::ZExt;
1644
0
    else
1645
0
        LocInfo = CCValAssign::AExt;
1646
0
  }
1647
62
1648
62
  if (
LocVT == MVT::i6462
) {
1649
56
    static const MCPhysReg RegList1[] = {
1650
56
      X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1651
56
    };
1652
56
    if (unsigned 
Reg56
= State.AllocateReg(RegList1)) {
1653
56
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1654
56
      return false;
1655
56
    }
1656
56
  }
1657
62
1658
6
  
if (6
LocVT == MVT::f32 ||
1659
2
      LocVT == MVT::f64 ||
1660
0
      LocVT == MVT::v16i8 ||
1661
0
      LocVT == MVT::v8i16 ||
1662
0
      LocVT == MVT::v4i32 ||
1663
0
      LocVT == MVT::v2i64 ||
1664
0
      LocVT == MVT::v4f32 ||
1665
6
      
LocVT == MVT::v2f640
) {
1666
6
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()6
) {
1667
6
      static const MCPhysReg RegList2[] = {
1668
6
        X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
1669
6
      };
1670
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList2)) {
1671
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1672
6
        return false;
1673
6
      }
1674
6
    }
1675
6
  }
1676
6
1677
0
  
if (0
LocVT == MVT::v32i8 ||
1678
0
      LocVT == MVT::v16i16 ||
1679
0
      LocVT == MVT::v8i32 ||
1680
0
      LocVT == MVT::v4i64 ||
1681
0
      LocVT == MVT::v8f32 ||
1682
0
      
LocVT == MVT::v4f640
) {
1683
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()0
) {
1684
0
      static const MCPhysReg RegList3[] = {
1685
0
        X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
1686
0
      };
1687
0
      if (unsigned 
Reg0
= State.AllocateReg(RegList3)) {
1688
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1689
0
        return false;
1690
0
      }
1691
0
    }
1692
0
  }
1693
0
1694
0
  
if (0
LocVT == MVT::v64i8 ||
1695
0
      LocVT == MVT::v32i16 ||
1696
0
      LocVT == MVT::v16i32 ||
1697
0
      LocVT == MVT::v8i64 ||
1698
0
      LocVT == MVT::v16f32 ||
1699
0
      
LocVT == MVT::v8f640
) {
1700
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()0
) {
1701
0
      static const MCPhysReg RegList4[] = {
1702
0
        X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
1703
0
      };
1704
0
      if (unsigned 
Reg0
= State.AllocateReg(RegList4)) {
1705
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1706
0
        return false;
1707
0
      }
1708
0
    }
1709
0
  }
1710
0
1711
0
  return true;  // CC didn't match.
1712
62
}
1713
1714
1715
static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
1716
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1717
112
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1718
112
1719
112
  if (
LocVT == MVT::i64112
) {
1720
112
    static const MCPhysReg RegList1[] = {
1721
112
      X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14
1722
112
    };
1723
112
    if (unsigned 
Reg112
= State.AllocateReg(RegList1)) {
1724
112
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1725
112
      return false;
1726
112
    }
1727
112
  }
1728
112
1729
0
  return true;  // CC didn't match.
1730
112
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_HHVM(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_HHVM(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_64_HHVM(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1717
112
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1718
112
1719
112
  if (
LocVT == MVT::i64112
) {
1720
112
    static const MCPhysReg RegList1[] = {
1721
112
      X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14
1722
112
    };
1723
112
    if (unsigned 
Reg112
= State.AllocateReg(RegList1)) {
1724
112
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1725
112
      return false;
1726
112
    }
1727
112
  }
1728
112
1729
0
  return true;  // CC didn't match.
1730
112
}
1731
1732
1733
static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
1734
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
1735
25
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1736
25
1737
25
  if (
LocVT == MVT::i6425
) {
1738
24
    if (unsigned 
Reg24
= State.AllocateReg(X86::RBP)) {
1739
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1740
5
      return false;
1741
5
    }
1742
24
  }
1743
25
1744
20
  
if (20
!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)20
)
1745
20
    return false;
1746
20
1747
0
  return true;  // CC didn't match.
1748
25
}
X86ISelLowering.cpp:CC_X86_64_HHVM_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1735
25
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1736
25
1737
25
  if (
LocVT == MVT::i6425
) {
1738
24
    if (unsigned 
Reg24
= State.AllocateReg(X86::RBP)) {
1739
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1740
5
      return false;
1741
5
    }
1742
24
  }
1743
25
1744
20
  
if (20
!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)20
)
1745
20
    return false;
1746
20
1747
0
  return true;  // CC didn't match.
1748
25
}
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_HHVM_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_HHVM_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
1749
1750
1751
static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
1752
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1753
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1754
42
1755
42
  if (LocVT == MVT::i8 ||
1756
42
      LocVT == MVT::i16 ||
1757
42
      
LocVT == MVT::i3242
) {
1758
6
    LocVT = MVT::i64;
1759
6
    if (ArgFlags.isSExt())
1760
0
        LocInfo = CCValAssign::SExt;
1761
6
    else 
if (6
ArgFlags.isZExt()6
)
1762
0
        LocInfo = CCValAssign::ZExt;
1763
6
    else
1764
6
        LocInfo = CCValAssign::AExt;
1765
6
  }
1766
42
1767
42
  if (
LocVT == MVT::i6442
) {
1768
42
    static const MCPhysReg RegList1[] = {
1769
42
      X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
1770
42
    };
1771
42
    if (unsigned 
Reg42
= State.AllocateReg(RegList1)) {
1772
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1773
41
      return false;
1774
41
    }
1775
42
  }
1776
42
1777
1
  
if (1
LocVT == MVT::i32 ||
1778
1
      LocVT == MVT::i64 ||
1779
0
      LocVT == MVT::f32 ||
1780
1
      
LocVT == MVT::f640
) {
1781
1
    unsigned Offset2 = State.AllocateStack(8, 8);
1782
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1783
1
    return false;
1784
1
  }
1785
1
1786
0
  return true;  // CC didn't match.
1787
42
}
X86ISelLowering.cpp:CC_X86_64_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1753
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1754
42
1755
42
  if (LocVT == MVT::i8 ||
1756
42
      LocVT == MVT::i16 ||
1757
42
      
LocVT == MVT::i3242
) {
1758
6
    LocVT = MVT::i64;
1759
6
    if (ArgFlags.isSExt())
1760
0
        LocInfo = CCValAssign::SExt;
1761
6
    else 
if (6
ArgFlags.isZExt()6
)
1762
0
        LocInfo = CCValAssign::ZExt;
1763
6
    else
1764
6
        LocInfo = CCValAssign::AExt;
1765
6
  }
1766
42
1767
42
  if (
LocVT == MVT::i6442
) {
1768
42
    static const MCPhysReg RegList1[] = {
1769
42
      X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
1770
42
    };
1771
42
    if (unsigned 
Reg42
= State.AllocateReg(RegList1)) {
1772
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1773
41
      return false;
1774
41
    }
1775
42
  }
1776
42
1777
1
  
if (1
LocVT == MVT::i32 ||
1778
1
      LocVT == MVT::i64 ||
1779
0
      LocVT == MVT::f32 ||
1780
1
      
LocVT == MVT::f640
) {
1781
1
    unsigned Offset2 = State.AllocateStack(8, 8);
1782
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1783
1
    return false;
1784
1
  }
1785
1
1786
0
  return true;  // CC didn't match.
1787
42
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
1788
1789
1790
static bool CC_X86_64_Intr(unsigned ValNo, MVT ValVT,
1791
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1792
19
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1793
19
1794
19
  unsigned Offset1 = State.AllocateStack(8, 8);
1795
19
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1796
19
  return false;
1797
19
1798
0
  return true;  // CC didn't match.
1799
19
}
X86ISelLowering.cpp:CC_X86_64_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1792
19
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1793
19
1794
19
  unsigned Offset1 = State.AllocateStack(8, 8);
1795
19
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1796
19
  return false;
1797
19
1798
0
  return true;  // CC didn't match.
1799
19
}
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
1800
1801
1802
static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
1803
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
1804
69
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
1805
69
1806
69
  if (LocVT == MVT::i8 ||
1807
69
      
LocVT == MVT::i1669
) {
1808
0
    LocVT = MVT::i32;
1809
0
    if (ArgFlags.isSExt())
1810
0
        LocInfo = CCValAssign::SExt;
1811
0
    else 
if (0
ArgFlags.isZExt()0
)
1812
0
        LocInfo = CCValAssign::ZExt;
1813
0
    else
1814
0
        LocInfo = CCValAssign::AExt;
1815
0
  }
1816
69
1817
69
  if (
LocVT == MVT::i3269
) {
1818
26
    if (unsigned 
Reg26
= State.AllocateReg(X86::EAX)) {
1819
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1820
4
      return false;
1821
4
    }
1822
26
  }
1823
69
1824
65
  
if (65
LocVT == MVT::i6465
) {
1825
43
    if (unsigned 
Reg43
= State.AllocateReg(X86::RAX)) {
1826
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1827
9
      return false;
1828
9
    }
1829
43
  }
1830
65
1831
56
  
if (56
LocVT == MVT::i32 ||
1832
56
      
LocVT == MVT::f3234
) {
1833
22
    unsigned Offset1 = State.AllocateStack(4, 4);
1834
22
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1835
22
    return false;
1836
22
  }
1837
56
1838
34
  
if (34
LocVT == MVT::i64 ||
1839
34
      
LocVT == MVT::f640
) {
1840
34
    unsigned Offset2 = State.AllocateStack(8, 8);
1841
34
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1842
34
    return false;
1843
34
  }
1844
34
1845
0
  return true;  // CC didn't match.
1846
69
}
X86FastISel.cpp:CC_X86_64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1804
20
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
1805
20
1806
20
  if (LocVT == MVT::i8 ||
1807
20
      
LocVT == MVT::i1620
) {
1808
0
    LocVT = MVT::i32;
1809
0
    if (ArgFlags.isSExt())
1810
0
        LocInfo = CCValAssign::SExt;
1811
0
    else 
if (0
ArgFlags.isZExt()0
)
1812
0
        LocInfo = CCValAssign::ZExt;
1813
0
    else
1814
0
        LocInfo = CCValAssign::AExt;
1815
0
  }
1816
20
1817
20
  if (
LocVT == MVT::i3220
) {
1818
7
    if (unsigned 
Reg7
= State.AllocateReg(X86::EAX)) {
1819
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1820
0
      return false;
1821
0
    }
1822
7
  }
1823
20
1824
20
  
if (20
LocVT == MVT::i6420
) {
1825
13
    if (unsigned 
Reg13
= State.AllocateReg(X86::RAX)) {
1826
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1827
4
      return false;
1828
4
    }
1829
13
  }
1830
20
1831
16
  
if (16
LocVT == MVT::i32 ||
1832
16
      
LocVT == MVT::f329
) {
1833
7
    unsigned Offset1 = State.AllocateStack(4, 4);
1834
7
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1835
7
    return false;
1836
7
  }
1837
16
1838
9
  
if (9
LocVT == MVT::i64 ||
1839
9
      
LocVT == MVT::f640
) {
1840
9
    unsigned Offset2 = State.AllocateStack(8, 8);
1841
9
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1842
9
    return false;
1843
9
  }
1844
9
1845
0
  return true;  // CC didn't match.
1846
20
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1804
49
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
1805
49
1806
49
  if (LocVT == MVT::i8 ||
1807
49
      
LocVT == MVT::i1649
) {
1808
0
    LocVT = MVT::i32;
1809
0
    if (ArgFlags.isSExt())
1810
0
        LocInfo = CCValAssign::SExt;
1811
0
    else 
if (0
ArgFlags.isZExt()0
)
1812
0
        LocInfo = CCValAssign::ZExt;
1813
0
    else
1814
0
        LocInfo = CCValAssign::AExt;
1815
0
  }
1816
49
1817
49
  if (
LocVT == MVT::i3249
) {
1818
19
    if (unsigned 
Reg19
= State.AllocateReg(X86::EAX)) {
1819
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1820
4
      return false;
1821
4
    }
1822
19
  }
1823
49
1824
45
  
if (45
LocVT == MVT::i6445
) {
1825
30
    if (unsigned 
Reg30
= State.AllocateReg(X86::RAX)) {
1826
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1827
5
      return false;
1828
5
    }
1829
30
  }
1830
45
1831
40
  
if (40
LocVT == MVT::i32 ||
1832
40
      
LocVT == MVT::f3225
) {
1833
15
    unsigned Offset1 = State.AllocateStack(4, 4);
1834
15
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1835
15
    return false;
1836
15
  }
1837
40
1838
25
  
if (25
LocVT == MVT::i64 ||
1839
25
      
LocVT == MVT::f640
) {
1840
25
    unsigned Offset2 = State.AllocateStack(8, 8);
1841
25
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1842
25
    return false;
1843
25
  }
1844
25
1845
0
  return true;  // CC didn't match.
1846
49
}
1847
1848
1849
static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
1850
                                  MVT LocVT, CCValAssign::LocInfo LocInfo,
1851
185
                                  ISD::ArgFlagsTy ArgFlags, CCState &State) {
1852
185
1853
185
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()185
) {
1854
185
    if (
ArgFlags.isByVal()185
) {
1855
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1856
0
      return false;
1857
0
    }
1858
185
  }
1859
185
1860
185
  
if (185
ArgFlags.isByVal()185
) {
1861
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
1862
0
    return false;
1863
0
  }
1864
185
1865
185
  
if (185
LocVT == MVT::i1 ||
1866
185
      LocVT == MVT::i8 ||
1867
174
      LocVT == MVT::i16 ||
1868
185
      
LocVT == MVT::v1i1170
) {
1869
15
    LocVT = MVT::i32;
1870
15
    if (ArgFlags.isSExt())
1871
2
        LocInfo = CCValAssign::SExt;
1872
13
    else 
if (13
ArgFlags.isZExt()13
)
1873
0
        LocInfo = CCValAssign::ZExt;
1874
13
    else
1875
13
        LocInfo = CCValAssign::AExt;
1876
15
  }
1877
185
1878
185
  if (LocVT == MVT::v8i1 ||
1879
179
      LocVT == MVT::v16i1 ||
1880
185
      
LocVT == MVT::v32i1173
) {
1881
18
    LocVT = MVT::i32;
1882
18
    if (ArgFlags.isSExt())
1883
0
        LocInfo = CCValAssign::SExt;
1884
18
    else 
if (18
ArgFlags.isZExt()18
)
1885
0
        LocInfo = CCValAssign::ZExt;
1886
18
    else
1887
18
        LocInfo = CCValAssign::AExt;
1888
18
  }
1889
185
1890
185
  if (
LocVT == MVT::i32185
) {
1891
62
    static const MCPhysReg RegList1[] = {
1892
62
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
1893
62
    };
1894
62
    if (unsigned 
Reg62
= State.AllocateReg(RegList1)) {
1895
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1896
60
      return false;
1897
60
    }
1898
62
  }
1899
185
1900
125
  
if (125
LocVT == MVT::i64125
) {
1901
9
    static const MCPhysReg RegList2[] = {
1902
9
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1903
9
    };
1904
9
    if (unsigned 
Reg9
= State.AllocateReg(RegList2)) {
1905
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1906
9
      return false;
1907
9
    }
1908
9
  }
1909
125
1910
116
  
if (116
LocVT == MVT::v64i1116
) {
1911
26
    LocVT = MVT::i64;
1912
26
    if (ArgFlags.isSExt())
1913
0
        LocInfo = CCValAssign::SExt;
1914
26
    else 
if (26
ArgFlags.isZExt()26
)
1915
0
        LocInfo = CCValAssign::ZExt;
1916
26
    else
1917
26
        LocInfo = CCValAssign::AExt;
1918
26
  }
1919
116
1920
116
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()116
) {
1921
116
    if (
LocVT == MVT::i64116
) {
1922
26
      static const MCPhysReg RegList3[] = {
1923
26
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1924
26
      };
1925
26
      if (unsigned 
Reg26
= State.AllocateReg(RegList3)) {
1926
22
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1927
22
        return false;
1928
22
      }
1929
26
    }
1930
116
  }
1931
116
1932
94
  
if (94
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()94
) {
1933
0
    if (
LocVT == MVT::i640
) {
1934
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1935
0
            return false;
1936
0
    }
1937
0
  }
1938
94
1939
94
  
if (94
LocVT == MVT::f32 ||
1940
89
      LocVT == MVT::f64 ||
1941
94
      
LocVT == MVT::f12884
) {
1942
10
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()10
) {
1943
10
      static const MCPhysReg RegList4[] = {
1944
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
1945
10
      };
1946
10
      if (unsigned 
Reg10
= State.AllocateReg(RegList4)) {
1947
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1948
10
        return false;
1949
10
      }
1950
10
    }
1951
10
  }
1952
94
1953
84
  
if (84
LocVT == MVT::f8084
) {
1954
3
    if (unsigned 
Reg3
= State.AllocateReg(X86::FP0)) {
1955
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1956
3
      return false;
1957
3
    }
1958
3
  }
1959
84
1960
81
  
if (81
LocVT == MVT::v16i8 ||
1961
81
      LocVT == MVT::v8i16 ||
1962
81
      LocVT == MVT::v4i32 ||
1963
76
      LocVT == MVT::v2i64 ||
1964
76
      LocVT == MVT::v4f32 ||
1965
81
      
LocVT == MVT::v2f6440
) {
1966
41
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()41
) {
1967
41
      static const MCPhysReg RegList5[] = {
1968
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
1969
41
      };
1970
41
      if (unsigned 
Reg41
= State.AllocateReg(RegList5)) {
1971
33
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1972
33
        return false;
1973
33
      }
1974
41
    }
1975
41
  }
1976
81
1977
48
  
if (48
LocVT == MVT::v32i8 ||
1978
48
      LocVT == MVT::v16i16 ||
1979
48
      LocVT == MVT::v8i32 ||
1980
43
      LocVT == MVT::v4i64 ||
1981
43
      LocVT == MVT::v8f32 ||
1982
48
      
LocVT == MVT::v4f6443
) {
1983
5
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()5
) {
1984
5
      static const MCPhysReg RegList6[] = {
1985
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
1986
5
      };
1987
5
      if (unsigned 
Reg5
= State.AllocateReg(RegList6)) {
1988
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1989
5
        return false;
1990
5
      }
1991
5
    }
1992
5
  }
1993
48
1994
43
  
if (43
LocVT == MVT::v64i8 ||
1995
43
      LocVT == MVT::v32i16 ||
1996
43
      LocVT == MVT::v16i32 ||
1997
38
      LocVT == MVT::v8i64 ||
1998
38
      LocVT == MVT::v16f32 ||
1999
43
      
LocVT == MVT::v8f6414
) {
2000
29
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()29
) {
2001
29
      static const MCPhysReg RegList7[] = {
2002
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2003
29
      };
2004
29
      if (unsigned 
Reg29
= State.AllocateReg(RegList7)) {
2005
27
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2006
27
        return false;
2007
27
      }
2008
29
    }
2009
29
  }
2010
43
2011
16
  
if (16
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()16
) {
2012
16
    if (LocVT == MVT::i32 ||
2013
14
        LocVT == MVT::i64 ||
2014
10
        LocVT == MVT::f32 ||
2015
16
        
LocVT == MVT::f6410
) {
2016
6
      unsigned Offset8 = State.AllocateStack(8, 8);
2017
6
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2018
6
      return false;
2019
6
    }
2020
16
  }
2021
16
2022
10
  
if (10
LocVT == MVT::i32 ||
2023
10
      
LocVT == MVT::f3210
) {
2024
0
    unsigned Offset9 = State.AllocateStack(4, 4);
2025
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2026
0
    return false;
2027
0
  }
2028
10
2029
10
  
if (10
LocVT == MVT::i64 ||
2030
10
      
LocVT == MVT::f6410
) {
2031
0
    unsigned Offset10 = State.AllocateStack(8, 4);
2032
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2033
0
    return false;
2034
0
  }
2035
10
2036
10
  
if (10
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()10
) {
2037
10
    if (
LocVT == MVT::x86mmx10
) {
2038
0
      unsigned Offset11 = State.AllocateStack(8, 8);
2039
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2040
0
      return false;
2041
0
    }
2042
10
  }
2043
10
2044
10
  
if (10
LocVT == MVT::x86mmx10
) {
2045
0
    unsigned Offset12 = State.AllocateStack(8, 4);
2046
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2047
0
    return false;
2048
0
  }
2049
10
2050
10
  
if (10
LocVT == MVT::f80 ||
2051
10
      
LocVT == MVT::f12810
) {
2052
0
    unsigned Offset13 = State.AllocateStack(
2053
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
2054
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2055
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2056
0
    return false;
2057
0
  }
2058
10
2059
10
  
if (10
LocVT == MVT::v16i8 ||
2060
10
      LocVT == MVT::v8i16 ||
2061
10
      LocVT == MVT::v4i32 ||
2062
10
      LocVT == MVT::v2i64 ||
2063
10
      LocVT == MVT::v4f32 ||
2064
10
      
LocVT == MVT::v2f642
) {
2065
8
    unsigned Offset14 = State.AllocateStack(16, 16);
2066
8
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2067
8
    return false;
2068
8
  }
2069
10
2070
2
  
if (2
LocVT == MVT::v32i8 ||
2071
2
      LocVT == MVT::v16i16 ||
2072
2
      LocVT == MVT::v8i32 ||
2073
2
      LocVT == MVT::v4i64 ||
2074
2
      LocVT == MVT::v8f32 ||
2075
2
      
LocVT == MVT::v4f642
) {
2076
0
    unsigned Offset15 = State.AllocateStack(32, 32);
2077
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2078
0
    return false;
2079
0
  }
2080
2
2081
2
  
if (2
LocVT == MVT::v16i32 ||
2082
2
      LocVT == MVT::v8i64 ||
2083
2
      LocVT == MVT::v16f32 ||
2084
2
      
LocVT == MVT::v8f640
) {
2085
2
    unsigned Offset16 = State.AllocateStack(64, 64);
2086
2
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2087
2
    return false;
2088
2
  }
2089
2
2090
0
  return true;  // CC didn't match.
2091
185
}
Unexecuted instantiation: X86FastISel.cpp:CC_X86_SysV64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_SysV64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1851
185
                                  ISD::ArgFlagsTy ArgFlags, CCState &State) {
1852
185
1853
185
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()185
) {
1854
185
    if (
ArgFlags.isByVal()185
) {
1855
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1856
0
      return false;
1857
0
    }
1858
185
  }
1859
185
1860
185
  
if (185
ArgFlags.isByVal()185
) {
1861
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
1862
0
    return false;
1863
0
  }
1864
185
1865
185
  
if (185
LocVT == MVT::i1 ||
1866
185
      LocVT == MVT::i8 ||
1867
174
      LocVT == MVT::i16 ||
1868
185
      
LocVT == MVT::v1i1170
) {
1869
15
    LocVT = MVT::i32;
1870
15
    if (ArgFlags.isSExt())
1871
2
        LocInfo = CCValAssign::SExt;
1872
13
    else 
if (13
ArgFlags.isZExt()13
)
1873
0
        LocInfo = CCValAssign::ZExt;
1874
13
    else
1875
13
        LocInfo = CCValAssign::AExt;
1876
15
  }
1877
185
1878
185
  if (LocVT == MVT::v8i1 ||
1879
179
      LocVT == MVT::v16i1 ||
1880
185
      
LocVT == MVT::v32i1173
) {
1881
18
    LocVT = MVT::i32;
1882
18
    if (ArgFlags.isSExt())
1883
0
        LocInfo = CCValAssign::SExt;
1884
18
    else 
if (18
ArgFlags.isZExt()18
)
1885
0
        LocInfo = CCValAssign::ZExt;
1886
18
    else
1887
18
        LocInfo = CCValAssign::AExt;
1888
18
  }
1889
185
1890
185
  if (
LocVT == MVT::i32185
) {
1891
62
    static const MCPhysReg RegList1[] = {
1892
62
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
1893
62
    };
1894
62
    if (unsigned 
Reg62
= State.AllocateReg(RegList1)) {
1895
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1896
60
      return false;
1897
60
    }
1898
62
  }
1899
185
1900
125
  
if (125
LocVT == MVT::i64125
) {
1901
9
    static const MCPhysReg RegList2[] = {
1902
9
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1903
9
    };
1904
9
    if (unsigned 
Reg9
= State.AllocateReg(RegList2)) {
1905
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1906
9
      return false;
1907
9
    }
1908
9
  }
1909
125
1910
116
  
if (116
LocVT == MVT::v64i1116
) {
1911
26
    LocVT = MVT::i64;
1912
26
    if (ArgFlags.isSExt())
1913
0
        LocInfo = CCValAssign::SExt;
1914
26
    else 
if (26
ArgFlags.isZExt()26
)
1915
0
        LocInfo = CCValAssign::ZExt;
1916
26
    else
1917
26
        LocInfo = CCValAssign::AExt;
1918
26
  }
1919
116
1920
116
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()116
) {
1921
116
    if (
LocVT == MVT::i64116
) {
1922
26
      static const MCPhysReg RegList3[] = {
1923
26
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1924
26
      };
1925
26
      if (unsigned 
Reg26
= State.AllocateReg(RegList3)) {
1926
22
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1927
22
        return false;
1928
22
      }
1929
26
    }
1930
116
  }
1931
116
1932
94
  
if (94
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()94
) {
1933
0
    if (
LocVT == MVT::i640
) {
1934
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1935
0
            return false;
1936
0
    }
1937
0
  }
1938
94
1939
94
  
if (94
LocVT == MVT::f32 ||
1940
89
      LocVT == MVT::f64 ||
1941
94
      
LocVT == MVT::f12884
) {
1942
10
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()10
) {
1943
10
      static const MCPhysReg RegList4[] = {
1944
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
1945
10
      };
1946
10
      if (unsigned 
Reg10
= State.AllocateReg(RegList4)) {
1947
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1948
10
        return false;
1949
10
      }
1950
10
    }
1951
10
  }
1952
94
1953
84
  
if (84
LocVT == MVT::f8084
) {
1954
3
    if (unsigned 
Reg3
= State.AllocateReg(X86::FP0)) {
1955
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1956
3
      return false;
1957
3
    }
1958
3
  }
1959
84
1960
81
  
if (81
LocVT == MVT::v16i8 ||
1961
81
      LocVT == MVT::v8i16 ||
1962
81
      LocVT == MVT::v4i32 ||
1963
76
      LocVT == MVT::v2i64 ||
1964
76
      LocVT == MVT::v4f32 ||
1965
81
      
LocVT == MVT::v2f6440
) {
1966
41
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()41
) {
1967
41
      static const MCPhysReg RegList5[] = {
1968
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
1969
41
      };
1970
41
      if (unsigned 
Reg41
= State.AllocateReg(RegList5)) {
1971
33
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1972
33
        return false;
1973
33
      }
1974
41
    }
1975
41
  }
1976
81
1977
48
  
if (48
LocVT == MVT::v32i8 ||
1978
48
      LocVT == MVT::v16i16 ||
1979
48
      LocVT == MVT::v8i32 ||
1980
43
      LocVT == MVT::v4i64 ||
1981
43
      LocVT == MVT::v8f32 ||
1982
48
      
LocVT == MVT::v4f6443
) {
1983
5
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()5
) {
1984
5
      static const MCPhysReg RegList6[] = {
1985
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
1986
5
      };
1987
5
      if (unsigned 
Reg5
= State.AllocateReg(RegList6)) {
1988
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1989
5
        return false;
1990
5
      }
1991
5
    }
1992
5
  }
1993
48
1994
43
  
if (43
LocVT == MVT::v64i8 ||
1995
43
      LocVT == MVT::v32i16 ||
1996
43
      LocVT == MVT::v16i32 ||
1997
38
      LocVT == MVT::v8i64 ||
1998
38
      LocVT == MVT::v16f32 ||
1999
43
      
LocVT == MVT::v8f6414
) {
2000
29
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()29
) {
2001
29
      static const MCPhysReg RegList7[] = {
2002
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2003
29
      };
2004
29
      if (unsigned 
Reg29
= State.AllocateReg(RegList7)) {
2005
27
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2006
27
        return false;
2007
27
      }
2008
29
    }
2009
29
  }
2010
43
2011
16
  
if (16
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()16
) {
2012
16
    if (LocVT == MVT::i32 ||
2013
14
        LocVT == MVT::i64 ||
2014
10
        LocVT == MVT::f32 ||
2015
16
        
LocVT == MVT::f6410
) {
2016
6
      unsigned Offset8 = State.AllocateStack(8, 8);
2017
6
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2018
6
      return false;
2019
6
    }
2020
16
  }
2021
16
2022
10
  
if (10
LocVT == MVT::i32 ||
2023
10
      
LocVT == MVT::f3210
) {
2024
0
    unsigned Offset9 = State.AllocateStack(4, 4);
2025
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2026
0
    return false;
2027
0
  }
2028
10
2029
10
  
if (10
LocVT == MVT::i64 ||
2030
10
      
LocVT == MVT::f6410
) {
2031
0
    unsigned Offset10 = State.AllocateStack(8, 4);
2032
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2033
0
    return false;
2034
0
  }
2035
10
2036
10
  
if (10
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()10
) {
2037
10
    if (
LocVT == MVT::x86mmx10
) {
2038
0
      unsigned Offset11 = State.AllocateStack(8, 8);
2039
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2040
0
      return false;
2041
0
    }
2042
10
  }
2043
10
2044
10
  
if (10
LocVT == MVT::x86mmx10
) {
2045
0
    unsigned Offset12 = State.AllocateStack(8, 4);
2046
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2047
0
    return false;
2048
0
  }
2049
10
2050
10
  
if (10
LocVT == MVT::f80 ||
2051
10
      
LocVT == MVT::f12810
) {
2052
0
    unsigned Offset13 = State.AllocateStack(
2053
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
2054
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2055
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2056
0
    return false;
2057
0
  }
2058
10
2059
10
  
if (10
LocVT == MVT::v16i8 ||
2060
10
      LocVT == MVT::v8i16 ||
2061
10
      LocVT == MVT::v4i32 ||
2062
10
      LocVT == MVT::v2i64 ||
2063
10
      LocVT == MVT::v4f32 ||
2064
10
      
LocVT == MVT::v2f642
) {
2065
8
    unsigned Offset14 = State.AllocateStack(16, 16);
2066
8
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2067
8
    return false;
2068
8
  }
2069
10
2070
2
  
if (2
LocVT == MVT::v32i8 ||
2071
2
      LocVT == MVT::v16i16 ||
2072
2
      LocVT == MVT::v8i32 ||
2073
2
      LocVT == MVT::v4i64 ||
2074
2
      LocVT == MVT::v8f32 ||
2075
2
      
LocVT == MVT::v4f642
) {
2076
0
    unsigned Offset15 = State.AllocateStack(32, 32);
2077
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2078
0
    return false;
2079
0
  }
2080
2
2081
2
  
if (2
LocVT == MVT::v16i32 ||
2082
2
      LocVT == MVT::v8i64 ||
2083
2
      LocVT == MVT::v16f32 ||
2084
2
      
LocVT == MVT::v8f640
) {
2085
2
    unsigned Offset16 = State.AllocateStack(64, 64);
2086
2
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2087
2
    return false;
2088
2
  }
2089
2
2090
0
  return true;  // CC didn't match.
2091
185
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_SysV64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
2092
2093
2094
static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
2095
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
2096
240
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
2097
240
2098
240
  if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2099
182
    return false;
2100
240
2101
58
  
if (58
!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)58
)
2102
58
    return false;
2103
58
2104
0
  return true;  // CC didn't match.
2105
240
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_Win32_VectorCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_Win32_VectorCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_Win32_VectorCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2096
240
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
2097
240
2098
240
  if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2099
182
    return false;
2100
240
2101
58
  
if (58
!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)58
)
2102
58
    return false;
2103
58
2104
0
  return true;  // CC didn't match.
2105
240
}
2106
2107
2108
static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
2109
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
2110
2.13k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2111
2.13k
2112
2.13k
  if (LocVT == MVT::i1 ||
2113
2.13k
      LocVT == MVT::i8 ||
2114
2.10k
      LocVT == MVT::i16 ||
2115
2.13k
      
LocVT == MVT::v1i12.09k
) {
2116
38
    LocVT = MVT::i32;
2117
38
    if (ArgFlags.isSExt())
2118
0
        LocInfo = CCValAssign::SExt;
2119
38
    else 
if (38
ArgFlags.isZExt()38
)
2120
4
        LocInfo = CCValAssign::ZExt;
2121
38
    else
2122
34
        LocInfo = CCValAssign::AExt;
2123
38
  }
2124
2.13k
2125
2.13k
  if (
ArgFlags.isNest()2.13k
) {
2126
2
    if (unsigned 
Reg2
= State.AllocateReg(X86::R10)) {
2127
2
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2128
2
      return false;
2129
2
    }
2130
2
  }
2131
2.13k
2132
2.12k
  
if (2.12k
ArgFlags.isSwiftError()2.12k
) {
2133
2
    if (
LocVT == MVT::i642
) {
2134
2
      if (unsigned 
Reg2
= State.AllocateReg(X86::R12)) {
2135
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2136
2
        return false;
2137
2
      }
2138
2
    }
2139
2
  }
2140
2.12k
2141
2.12k
  
if (2.12k
LocVT == MVT::v16i8 ||
2142
2.12k
      LocVT == MVT::v8i16 ||
2143
2.12k
      LocVT == MVT::v4i32 ||
2144
2.11k
      LocVT == MVT::v2i64 ||
2145
2.11k
      LocVT == MVT::v4f32 ||
2146
2.12k
      
LocVT == MVT::v2f641.85k
) {
2147
511
    LocVT = MVT::i64;
2148
511
    LocInfo = CCValAssign::Indirect;
2149
511
  }
2150
2.12k
2151
2.12k
  if (LocVT == MVT::v32i8 ||
2152
2.12k
      LocVT == MVT::v16i16 ||
2153
2.12k
      LocVT == MVT::v8i32 ||
2154
2.12k
      LocVT == MVT::v4i64 ||
2155
2.12k
      LocVT == MVT::v8f32 ||
2156
2.12k
      
LocVT == MVT::v4f641.99k
) {
2157
250
    LocVT = MVT::i64;
2158
250
    LocInfo = CCValAssign::Indirect;
2159
250
  }
2160
2.12k
2161
2.12k
  if (LocVT == MVT::v16i32 ||
2162
2.12k
      LocVT == MVT::v16f32 ||
2163
2.12k
      LocVT == MVT::v8f64 ||
2164
2.12k
      
LocVT == MVT::v8i642.12k
) {
2165
7
    LocVT = MVT::i64;
2166
7
    LocInfo = CCValAssign::Indirect;
2167
7
  }
2168
2.12k
2169
2.12k
  if (
LocVT == MVT::x86mmx2.12k
) {
2170
0
    LocVT = MVT::i64;
2171
0
    LocInfo = CCValAssign::BCvt;
2172
0
  }
2173
2.12k
2174
2.12k
  if (
LocVT == MVT::i322.12k
) {
2175
608
    static const MCPhysReg RegList1[] = {
2176
608
      X86::ECX, X86::EDX, X86::R8D, X86::R9D
2177
608
    };
2178
608
    static const MCPhysReg RegList2[] = {
2179
608
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2180
608
    };
2181
608
    if (unsigned 
Reg608
= State.AllocateReg(RegList1, RegList2)) {
2182
539
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2183
539
      return false;
2184
539
    }
2185
608
  }
2186
2.12k
2187
1.58k
  
if (1.58k
State.getCallingConv() == CallingConv::X86_ThisCall1.58k
) {
2188
14
    if (
ArgFlags.isSRet()14
) {
2189
0
      if (
LocVT == MVT::i640
) {
2190
0
        static const MCPhysReg RegList3[] = {
2191
0
          X86::RDX, X86::R8, X86::R9
2192
0
        };
2193
0
        static const MCPhysReg RegList4[] = {
2194
0
          X86::XMM1, X86::XMM2, X86::XMM3
2195
0
        };
2196
0
        if (unsigned 
Reg0
= State.AllocateReg(RegList3, RegList4)) {
2197
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2198
0
          return false;
2199
0
        }
2200
0
      }
2201
0
    }
2202
14
  }
2203
1.58k
2204
1.58k
  
if (1.58k
LocVT == MVT::i641.58k
) {
2205
1.43k
    static const MCPhysReg RegList5[] = {
2206
1.43k
      X86::RCX, X86::RDX, X86::R8, X86::R9
2207
1.43k
    };
2208
1.43k
    static const MCPhysReg RegList6[] = {
2209
1.43k
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2210
1.43k
    };
2211
1.43k
    if (unsigned 
Reg1.43k
= State.AllocateReg(RegList5, RegList6)) {
2212
1.35k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2213
1.35k
      return false;
2214
1.35k
    }
2215
1.43k
  }
2216
1.58k
2217
230
  
if (230
LocVT == MVT::f32 ||
2218
186
      LocVT == MVT::f64 ||
2219
158
      LocVT == MVT::v16i8 ||
2220
158
      LocVT == MVT::v8i16 ||
2221
158
      LocVT == MVT::v4i32 ||
2222
158
      LocVT == MVT::v2i64 ||
2223
158
      LocVT == MVT::v4f32 ||
2224
230
      
LocVT == MVT::v2f64158
) {
2225
72
    static const MCPhysReg RegList7[] = {
2226
72
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2227
72
    };
2228
72
    static const MCPhysReg RegList8[] = {
2229
72
      X86::RCX, X86::RDX, X86::R8, X86::R9
2230
72
    };
2231
72
    if (unsigned 
Reg72
= State.AllocateReg(RegList7, RegList8)) {
2232
51
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2233
51
      return false;
2234
51
    }
2235
72
  }
2236
230
2237
179
  
if (179
LocVT == MVT::i32 ||
2238
110
      LocVT == MVT::i64 ||
2239
36
      LocVT == MVT::f32 ||
2240
179
      
LocVT == MVT::f6420
) {
2241
164
    unsigned Offset9 = State.AllocateStack(8, 8);
2242
164
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2243
164
    return false;
2244
164
  }
2245
179
2246
15
  
if (15
LocVT == MVT::f8015
) {
2247
6
    unsigned Offset10 = State.AllocateStack(
2248
6
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
2249
6
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2250
6
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2251
6
    return false;
2252
6
  }
2253
15
2254
9
  return true;  // CC didn't match.
2255
2.13k
}
X86FastISel.cpp:CC_X86_Win64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2110
4
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2111
4
2112
4
  if (LocVT == MVT::i1 ||
2113
4
      LocVT == MVT::i8 ||
2114
4
      LocVT == MVT::i16 ||
2115
4
      
LocVT == MVT::v1i14
) {
2116
0
    LocVT = MVT::i32;
2117
0
    if (ArgFlags.isSExt())
2118
0
        LocInfo = CCValAssign::SExt;
2119
0
    else 
if (0
ArgFlags.isZExt()0
)
2120
0
        LocInfo = CCValAssign::ZExt;
2121
0
    else
2122
0
        LocInfo = CCValAssign::AExt;
2123
0
  }
2124
4
2125
4
  if (
ArgFlags.isNest()4
) {
2126
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::R10)) {
2127
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2128
0
      return false;
2129
0
    }
2130
0
  }
2131
4
2132
4
  
if (4
ArgFlags.isSwiftError()4
) {
2133
0
    if (
LocVT == MVT::i640
) {
2134
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::R12)) {
2135
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2136
0
        return false;
2137
0
      }
2138
0
    }
2139
0
  }
2140
4
2141
4
  
if (4
LocVT == MVT::v16i8 ||
2142
4
      LocVT == MVT::v8i16 ||
2143
4
      LocVT == MVT::v4i32 ||
2144
4
      LocVT == MVT::v2i64 ||
2145
4
      LocVT == MVT::v4f32 ||
2146
4
      
LocVT == MVT::v2f644
) {
2147
0
    LocVT = MVT::i64;
2148
0
    LocInfo = CCValAssign::Indirect;
2149
0
  }
2150
4
2151
4
  if (LocVT == MVT::v32i8 ||
2152
4
      LocVT == MVT::v16i16 ||
2153
4
      LocVT == MVT::v8i32 ||
2154
4
      LocVT == MVT::v4i64 ||
2155
4
      LocVT == MVT::v8f32 ||
2156
4
      
LocVT == MVT::v4f644
) {
2157
0
    LocVT = MVT::i64;
2158
0
    LocInfo = CCValAssign::Indirect;
2159
0
  }
2160
4
2161
4
  if (LocVT == MVT::v16i32 ||
2162
4
      LocVT == MVT::v16f32 ||
2163
4
      LocVT == MVT::v8f64 ||
2164
4
      
LocVT == MVT::v8i644
) {
2165
0
    LocVT = MVT::i64;
2166
0
    LocInfo = CCValAssign::Indirect;
2167
0
  }
2168
4
2169
4
  if (
LocVT == MVT::x86mmx4
) {
2170
0
    LocVT = MVT::i64;
2171
0
    LocInfo = CCValAssign::BCvt;
2172
0
  }
2173
4
2174
4
  if (
LocVT == MVT::i324
) {
2175
1
    static const MCPhysReg RegList1[] = {
2176
1
      X86::ECX, X86::EDX, X86::R8D, X86::R9D
2177
1
    };
2178
1
    static const MCPhysReg RegList2[] = {
2179
1
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2180
1
    };
2181
1
    if (unsigned 
Reg1
= State.AllocateReg(RegList1, RegList2)) {
2182
1
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2183
1
      return false;
2184
1
    }
2185
1
  }
2186
4
2187
3
  
if (3
State.getCallingConv() == CallingConv::X86_ThisCall3
) {
2188
0
    if (
ArgFlags.isSRet()0
) {
2189
0
      if (
LocVT == MVT::i640
) {
2190
0
        static const MCPhysReg RegList3[] = {
2191
0
          X86::RDX, X86::R8, X86::R9
2192
0
        };
2193
0
        static const MCPhysReg RegList4[] = {
2194
0
          X86::XMM1, X86::XMM2, X86::XMM3
2195
0
        };
2196
0
        if (unsigned 
Reg0
= State.AllocateReg(RegList3, RegList4)) {
2197
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2198
0
          return false;
2199
0
        }
2200
0
      }
2201
0
    }
2202
0
  }
2203
3
2204
3
  
if (3
LocVT == MVT::i643
) {
2205
3
    static const MCPhysReg RegList5[] = {
2206
3
      X86::RCX, X86::RDX, X86::R8, X86::R9
2207
3
    };
2208
3
    static const MCPhysReg RegList6[] = {
2209
3
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2210
3
    };
2211
3
    if (unsigned 
Reg3
= State.AllocateReg(RegList5, RegList6)) {
2212
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2213
3
      return false;
2214
3
    }
2215
3
  }
2216
3
2217
0
  
if (0
LocVT == MVT::f32 ||
2218
0
      LocVT == MVT::f64 ||
2219
0
      LocVT == MVT::v16i8 ||
2220
0
      LocVT == MVT::v8i16 ||
2221
0
      LocVT == MVT::v4i32 ||
2222
0
      LocVT == MVT::v2i64 ||
2223
0
      LocVT == MVT::v4f32 ||
2224
0
      
LocVT == MVT::v2f640
) {
2225
0
    static const MCPhysReg RegList7[] = {
2226
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2227
0
    };
2228
0
    static const MCPhysReg RegList8[] = {
2229
0
      X86::RCX, X86::RDX, X86::R8, X86::R9
2230
0
    };
2231
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList7, RegList8)) {
2232
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2233
0
      return false;
2234
0
    }
2235
0
  }
2236
0
2237
0
  
if (0
LocVT == MVT::i32 ||
2238
0
      LocVT == MVT::i64 ||
2239
0
      LocVT == MVT::f32 ||
2240
0
      
LocVT == MVT::f640
) {
2241
0
    unsigned Offset9 = State.AllocateStack(8, 8);
2242
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2243
0
    return false;
2244
0
  }
2245
0
2246
0
  
if (0
LocVT == MVT::f800
) {
2247
0
    unsigned Offset10 = State.AllocateStack(
2248
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
2249
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2250
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2251
0
    return false;
2252
0
  }
2253
0
2254
0
  return true;  // CC didn't match.
2255
4
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_Win64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_Win64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2110
2.12k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2111
2.12k
2112
2.12k
  if (LocVT == MVT::i1 ||
2113
2.12k
      LocVT == MVT::i8 ||
2114
2.10k
      LocVT == MVT::i16 ||
2115
2.12k
      
LocVT == MVT::v1i12.08k
) {
2116
38
    LocVT = MVT::i32;
2117
38
    if (ArgFlags.isSExt())
2118
0
        LocInfo = CCValAssign::SExt;
2119
38
    else 
if (38
ArgFlags.isZExt()38
)
2120
4
        LocInfo = CCValAssign::ZExt;
2121
38
    else
2122
34
        LocInfo = CCValAssign::AExt;
2123
38
  }
2124
2.12k
2125
2.12k
  if (
ArgFlags.isNest()2.12k
) {
2126
2
    if (unsigned 
Reg2
= State.AllocateReg(X86::R10)) {
2127
2
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2128
2
      return false;
2129
2
    }
2130
2
  }
2131
2.12k
2132
2.12k
  
if (2.12k
ArgFlags.isSwiftError()2.12k
) {
2133
2
    if (
LocVT == MVT::i642
) {
2134
2
      if (unsigned 
Reg2
= State.AllocateReg(X86::R12)) {
2135
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2136
2
        return false;
2137
2
      }
2138
2
    }
2139
2
  }
2140
2.12k
2141
2.12k
  
if (2.12k
LocVT == MVT::v16i8 ||
2142
2.12k
      LocVT == MVT::v8i16 ||
2143
2.12k
      LocVT == MVT::v4i32 ||
2144
2.11k
      LocVT == MVT::v2i64 ||
2145
2.11k
      LocVT == MVT::v4f32 ||
2146
2.12k
      
LocVT == MVT::v2f641.84k
) {
2147
511
    LocVT = MVT::i64;
2148
511
    LocInfo = CCValAssign::Indirect;
2149
511
  }
2150
2.12k
2151
2.12k
  if (LocVT == MVT::v32i8 ||
2152
2.12k
      LocVT == MVT::v16i16 ||
2153
2.12k
      LocVT == MVT::v8i32 ||
2154
2.12k
      LocVT == MVT::v4i64 ||
2155
2.12k
      LocVT == MVT::v8f32 ||
2156
2.12k
      
LocVT == MVT::v4f641.98k
) {
2157
250
    LocVT = MVT::i64;
2158
250
    LocInfo = CCValAssign::Indirect;
2159
250
  }
2160
2.12k
2161
2.12k
  if (LocVT == MVT::v16i32 ||
2162
2.12k
      LocVT == MVT::v16f32 ||
2163
2.11k
      LocVT == MVT::v8f64 ||
2164
2.12k
      
LocVT == MVT::v8i642.11k
) {
2165
7
    LocVT = MVT::i64;
2166
7
    LocInfo = CCValAssign::Indirect;
2167
7
  }
2168
2.12k
2169
2.12k
  if (
LocVT == MVT::x86mmx2.12k
) {
2170
0
    LocVT = MVT::i64;
2171
0
    LocInfo = CCValAssign::BCvt;
2172
0
  }
2173
2.12k
2174
2.12k
  if (
LocVT == MVT::i322.12k
) {
2175
607
    static const MCPhysReg RegList1[] = {
2176
607
      X86::ECX, X86::EDX, X86::R8D, X86::R9D
2177
607
    };
2178
607
    static const MCPhysReg RegList2[] = {
2179
607
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2180
607
    };
2181
607
    if (unsigned 
Reg607
= State.AllocateReg(RegList1, RegList2)) {
2182
538
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2183
538
      return false;
2184
538
    }
2185
607
  }
2186
2.12k
2187
1.58k
  
if (1.58k
State.getCallingConv() == CallingConv::X86_ThisCall1.58k
) {
2188
14
    if (
ArgFlags.isSRet()14
) {
2189
0
      if (
LocVT == MVT::i640
) {
2190
0
        static const MCPhysReg RegList3[] = {
2191
0
          X86::RDX, X86::R8, X86::R9
2192
0
        };
2193
0
        static const MCPhysReg RegList4[] = {
2194
0
          X86::XMM1, X86::XMM2, X86::XMM3
2195
0
        };
2196
0
        if (unsigned 
Reg0
= State.AllocateReg(RegList3, RegList4)) {
2197
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2198
0
          return false;
2199
0
        }
2200
0
      }
2201
0
    }
2202
14
  }
2203
1.58k
2204
1.58k
  
if (1.58k
LocVT == MVT::i641.58k
) {
2205
1.42k
    static const MCPhysReg RegList5[] = {
2206
1.42k
      X86::RCX, X86::RDX, X86::R8, X86::R9
2207
1.42k
    };
2208
1.42k
    static const MCPhysReg RegList6[] = {
2209
1.42k
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2210
1.42k
    };
2211
1.42k
    if (unsigned 
Reg1.42k
= State.AllocateReg(RegList5, RegList6)) {
2212
1.35k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2213
1.35k
      return false;
2214
1.35k
    }
2215
1.42k
  }
2216
1.58k
2217
230
  
if (230
LocVT == MVT::f32 ||
2218
186
      LocVT == MVT::f64 ||
2219
158
      LocVT == MVT::v16i8 ||
2220
158
      LocVT == MVT::v8i16 ||
2221
158
      LocVT == MVT::v4i32 ||
2222
158
      LocVT == MVT::v2i64 ||
2223
158
      LocVT == MVT::v4f32 ||
2224
230
      
LocVT == MVT::v2f64158
) {
2225
72
    static const MCPhysReg RegList7[] = {
2226
72
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2227
72
    };
2228
72
    static const MCPhysReg RegList8[] = {
2229
72
      X86::RCX, X86::RDX, X86::R8, X86::R9
2230
72
    };
2231
72
    if (unsigned 
Reg72
= State.AllocateReg(RegList7, RegList8)) {
2232
51
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2233
51
      return false;
2234
51
    }
2235
72
  }
2236
230
2237
179
  
if (179
LocVT == MVT::i32 ||
2238
110
      LocVT == MVT::i64 ||
2239
36
      LocVT == MVT::f32 ||
2240
179
      
LocVT == MVT::f6420
) {
2241
164
    unsigned Offset9 = State.AllocateStack(8, 8);
2242
164
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2243
164
    return false;
2244
164
  }
2245
179
2246
15
  
if (15
LocVT == MVT::f8015
) {
2247
6
    unsigned Offset10 = State.AllocateStack(
2248
6
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
2249
6
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2250
6
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2251
6
    return false;
2252
6
  }
2253
15
2254
9
  return true;  // CC didn't match.
2255
2.12k
}
2256
2257
2258
static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
2259
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
2260
195
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2261
195
2262
195
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()195
) {
2263
195
    if (
ArgFlags.isByVal()195
) {
2264
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
2265
0
      return false;
2266
0
    }
2267
195
  }
2268
195
2269
195
  
if (195
ArgFlags.isByVal()195
) {
2270
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
2271
0
    return false;
2272
0
  }
2273
195
2274
195
  
if (195
LocVT == MVT::i1 ||
2275
195
      LocVT == MVT::i8 ||
2276
184
      LocVT == MVT::i16 ||
2277
195
      
LocVT == MVT::v1i1180
) {
2278
15
    LocVT = MVT::i32;
2279
15
    if (ArgFlags.isSExt())
2280
2
        LocInfo = CCValAssign::SExt;
2281
13
    else 
if (13
ArgFlags.isZExt()13
)
2282
0
        LocInfo = CCValAssign::ZExt;
2283
13
    else
2284
13
        LocInfo = CCValAssign::AExt;
2285
15
  }
2286
195
2287
195
  if (LocVT == MVT::v8i1 ||
2288
189
      LocVT == MVT::v16i1 ||
2289
195
      
LocVT == MVT::v32i1183
) {
2290
18
    LocVT = MVT::i32;
2291
18
    if (ArgFlags.isSExt())
2292
0
        LocInfo = CCValAssign::SExt;
2293
18
    else 
if (18
ArgFlags.isZExt()18
)
2294
0
        LocInfo = CCValAssign::ZExt;
2295
18
    else
2296
18
        LocInfo = CCValAssign::AExt;
2297
18
  }
2298
195
2299
195
  if (
LocVT == MVT::i32195
) {
2300
72
    static const MCPhysReg RegList1[] = {
2301
72
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2302
72
    };
2303
72
    if (unsigned 
Reg72
= State.AllocateReg(RegList1)) {
2304
72
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2305
72
      return false;
2306
72
    }
2307
72
  }
2308
195
2309
123
  
if (123
LocVT == MVT::i64123
) {
2310
9
    static const MCPhysReg RegList2[] = {
2311
9
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2312
9
    };
2313
9
    if (unsigned 
Reg9
= State.AllocateReg(RegList2)) {
2314
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2315
9
      return false;
2316
9
    }
2317
9
  }
2318
123
2319
114
  
if (114
LocVT == MVT::v64i1114
) {
2320
26
    LocVT = MVT::i64;
2321
26
    if (ArgFlags.isSExt())
2322
0
        LocInfo = CCValAssign::SExt;
2323
26
    else 
if (26
ArgFlags.isZExt()26
)
2324
0
        LocInfo = CCValAssign::ZExt;
2325
26
    else
2326
26
        LocInfo = CCValAssign::AExt;
2327
26
  }
2328
114
2329
114
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()114
) {
2330
114
    if (
LocVT == MVT::i64114
) {
2331
26
      static const MCPhysReg RegList3[] = {
2332
26
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2333
26
      };
2334
26
      if (unsigned 
Reg26
= State.AllocateReg(RegList3)) {
2335
24
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2336
24
        return false;
2337
24
      }
2338
26
    }
2339
114
  }
2340
114
2341
90
  
if (90
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()90
) {
2342
0
    if (
LocVT == MVT::i640
) {
2343
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2344
0
            return false;
2345
0
    }
2346
0
  }
2347
90
2348
90
  
if (90
LocVT == MVT::f32 ||
2349
85
      LocVT == MVT::f64 ||
2350
90
      
LocVT == MVT::f12880
) {
2351
10
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()10
) {
2352
10
      static const MCPhysReg RegList4[] = {
2353
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2354
10
      };
2355
10
      if (unsigned 
Reg10
= State.AllocateReg(RegList4)) {
2356
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2357
10
        return false;
2358
10
      }
2359
10
    }
2360
10
  }
2361
90
2362
80
  
if (80
LocVT == MVT::f8080
) {
2363
3
    if (unsigned 
Reg3
= State.AllocateReg(X86::FP0)) {
2364
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2365
3
      return false;
2366
3
    }
2367
3
  }
2368
80
2369
77
  
if (77
LocVT == MVT::v16i8 ||
2370
77
      LocVT == MVT::v8i16 ||
2371
77
      LocVT == MVT::v4i32 ||
2372
72
      LocVT == MVT::v2i64 ||
2373
72
      LocVT == MVT::v4f32 ||
2374
77
      
LocVT == MVT::v2f6436
) {
2375
41
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()41
) {
2376
41
      static const MCPhysReg RegList5[] = {
2377
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2378
41
      };
2379
41
      if (unsigned 
Reg41
= State.AllocateReg(RegList5)) {
2380
33
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2381
33
        return false;
2382
33
      }
2383
41
    }
2384
41
  }
2385
77
2386
44
  
if (44
LocVT == MVT::v32i8 ||
2387
44
      LocVT == MVT::v16i16 ||
2388
44
      LocVT == MVT::v8i32 ||
2389
39
      LocVT == MVT::v4i64 ||
2390
39
      LocVT == MVT::v8f32 ||
2391
44
      
LocVT == MVT::v4f6439
) {
2392
5
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()5
) {
2393
5
      static const MCPhysReg RegList6[] = {
2394
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2395
5
      };
2396
5
      if (unsigned 
Reg5
= State.AllocateReg(RegList6)) {
2397
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2398
5
        return false;
2399
5
      }
2400
5
    }
2401
5
  }
2402
44
2403
39
  
if (39
LocVT == MVT::v64i8 ||
2404
39
      LocVT == MVT::v32i16 ||
2405
39
      LocVT == MVT::v16i32 ||
2406
34
      LocVT == MVT::v8i64 ||
2407
34
      LocVT == MVT::v16f32 ||
2408
39
      
LocVT == MVT::v8f6410
) {
2409
29
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()29
) {
2410
29
      static const MCPhysReg RegList7[] = {
2411
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2412
29
      };
2413
29
      if (unsigned 
Reg29
= State.AllocateReg(RegList7)) {
2414
27
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2415
27
        return false;
2416
27
      }
2417
29
    }
2418
29
  }
2419
39
2420
12
  
if (12
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()12
) {
2421
12
    if (LocVT == MVT::i32 ||
2422
12
        LocVT == MVT::i64 ||
2423
10
        LocVT == MVT::f32 ||
2424
12
        
LocVT == MVT::f6410
) {
2425
2
      unsigned Offset8 = State.AllocateStack(8, 8);
2426
2
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2427
2
      return false;
2428
2
    }
2429
12
  }
2430
12
2431
10
  
if (10
LocVT == MVT::i32 ||
2432
10
      
LocVT == MVT::f3210
) {
2433
0
    unsigned Offset9 = State.AllocateStack(4, 4);
2434
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2435
0
    return false;
2436
0
  }
2437
10
2438
10
  
if (10
LocVT == MVT::i64 ||
2439
10
      
LocVT == MVT::f6410
) {
2440
0
    unsigned Offset10 = State.AllocateStack(8, 4);
2441
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2442
0
    return false;
2443
0
  }
2444
10
2445
10
  
if (10
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()10
) {
2446
10
    if (
LocVT == MVT::x86mmx10
) {
2447
0
      unsigned Offset11 = State.AllocateStack(8, 8);
2448
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2449
0
      return false;
2450
0
    }
2451
10
  }
2452
10
2453
10
  
if (10
LocVT == MVT::x86mmx10
) {
2454
0
    unsigned Offset12 = State.AllocateStack(8, 4);
2455
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2456
0
    return false;
2457
0
  }
2458
10
2459
10
  
if (10
LocVT == MVT::f80 ||
2460
10
      
LocVT == MVT::f12810
) {
2461
0
    unsigned Offset13 = State.AllocateStack(
2462
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
2463
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2464
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2465
0
    return false;
2466
0
  }
2467
10
2468
10
  
if (10
LocVT == MVT::v16i8 ||
2469
10
      LocVT == MVT::v8i16 ||
2470
10
      LocVT == MVT::v4i32 ||
2471
10
      LocVT == MVT::v2i64 ||
2472
10
      LocVT == MVT::v4f32 ||
2473
10
      
LocVT == MVT::v2f642
) {
2474
8
    unsigned Offset14 = State.AllocateStack(16, 16);
2475
8
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2476
8
    return false;
2477
8
  }
2478
10
2479
2
  
if (2
LocVT == MVT::v32i8 ||
2480
2
      LocVT == MVT::v16i16 ||
2481
2
      LocVT == MVT::v8i32 ||
2482
2
      LocVT == MVT::v4i64 ||
2483
2
      LocVT == MVT::v8f32 ||
2484
2
      
LocVT == MVT::v4f642
) {
2485
0
    unsigned Offset15 = State.AllocateStack(32, 32);
2486
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2487
0
    return false;
2488
0
  }
2489
2
2490
2
  
if (2
LocVT == MVT::v16i32 ||
2491
2
      LocVT == MVT::v8i64 ||
2492
2
      LocVT == MVT::v16f32 ||
2493
2
      
LocVT == MVT::v8f640
) {
2494
2
    unsigned Offset16 = State.AllocateStack(64, 64);
2495
2
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2496
2
    return false;
2497
2
  }
2498
2
2499
0
  return true;  // CC didn't match.
2500
195
}
Unexecuted instantiation: X86FastISel.cpp:CC_X86_Win64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_Win64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2260
195
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2261
195
2262
195
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()195
) {
2263
195
    if (
ArgFlags.isByVal()195
) {
2264
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
2265
0
      return false;
2266
0
    }
2267
195
  }
2268
195
2269
195
  
if (195
ArgFlags.isByVal()195
) {
2270
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
2271
0
    return false;
2272
0
  }
2273
195
2274
195
  
if (195
LocVT == MVT::i1 ||
2275
195
      LocVT == MVT::i8 ||
2276
184
      LocVT == MVT::i16 ||
2277
195
      
LocVT == MVT::v1i1180
) {
2278
15
    LocVT = MVT::i32;
2279
15
    if (ArgFlags.isSExt())
2280
2
        LocInfo = CCValAssign::SExt;
2281
13
    else 
if (13
ArgFlags.isZExt()13
)
2282
0
        LocInfo = CCValAssign::ZExt;
2283
13
    else
2284
13
        LocInfo = CCValAssign::AExt;
2285
15
  }
2286
195
2287
195
  if (LocVT == MVT::v8i1 ||
2288
189
      LocVT == MVT::v16i1 ||
2289
195
      
LocVT == MVT::v32i1183
) {
2290
18
    LocVT = MVT::i32;
2291
18
    if (ArgFlags.isSExt())
2292
0
        LocInfo = CCValAssign::SExt;
2293
18
    else 
if (18
ArgFlags.isZExt()18
)
2294
0
        LocInfo = CCValAssign::ZExt;
2295
18
    else
2296
18
        LocInfo = CCValAssign::AExt;
2297
18
  }
2298
195
2299
195
  if (
LocVT == MVT::i32195
) {
2300
72
    static const MCPhysReg RegList1[] = {
2301
72
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2302
72
    };
2303
72
    if (unsigned 
Reg72
= State.AllocateReg(RegList1)) {
2304
72
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2305
72
      return false;
2306
72
    }
2307
72
  }
2308
195
2309
123
  
if (123
LocVT == MVT::i64123
) {
2310
9
    static const MCPhysReg RegList2[] = {
2311
9
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2312
9
    };
2313
9
    if (unsigned 
Reg9
= State.AllocateReg(RegList2)) {
2314
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2315
9
      return false;
2316
9
    }
2317
9
  }
2318
123
2319
114
  
if (114
LocVT == MVT::v64i1114
) {
2320
26
    LocVT = MVT::i64;
2321
26
    if (ArgFlags.isSExt())
2322
0
        LocInfo = CCValAssign::SExt;
2323
26
    else 
if (26
ArgFlags.isZExt()26
)
2324
0
        LocInfo = CCValAssign::ZExt;
2325
26
    else
2326
26
        LocInfo = CCValAssign::AExt;
2327
26
  }
2328
114
2329
114
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()114
) {
2330
114
    if (
LocVT == MVT::i64114
) {
2331
26
      static const MCPhysReg RegList3[] = {
2332
26
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2333
26
      };
2334
26
      if (unsigned 
Reg26
= State.AllocateReg(RegList3)) {
2335
24
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2336
24
        return false;
2337
24
      }
2338
26
    }
2339
114
  }
2340
114
2341
90
  
if (90
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()90
) {
2342
0
    if (
LocVT == MVT::i640
) {
2343
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2344
0
            return false;
2345
0
    }
2346
0
  }
2347
90
2348
90
  
if (90
LocVT == MVT::f32 ||
2349
85
      LocVT == MVT::f64 ||
2350
90
      
LocVT == MVT::f12880
) {
2351
10
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()10
) {
2352
10
      static const MCPhysReg RegList4[] = {
2353
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2354
10
      };
2355
10
      if (unsigned 
Reg10
= State.AllocateReg(RegList4)) {
2356
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2357
10
        return false;
2358
10
      }
2359
10
    }
2360
10
  }
2361
90
2362
80
  
if (80
LocVT == MVT::f8080
) {
2363
3
    if (unsigned 
Reg3
= State.AllocateReg(X86::FP0)) {
2364
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2365
3
      return false;
2366
3
    }
2367
3
  }
2368
80
2369
77
  
if (77
LocVT == MVT::v16i8 ||
2370
77
      LocVT == MVT::v8i16 ||
2371
77
      LocVT == MVT::v4i32 ||
2372
72
      LocVT == MVT::v2i64 ||
2373
72
      LocVT == MVT::v4f32 ||
2374
77
      
LocVT == MVT::v2f6436
) {
2375
41
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()41
) {
2376
41
      static const MCPhysReg RegList5[] = {
2377
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2378
41
      };
2379
41
      if (unsigned 
Reg41
= State.AllocateReg(RegList5)) {
2380
33
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2381
33
        return false;
2382
33
      }
2383
41
    }
2384
41
  }
2385
77
2386
44
  
if (44
LocVT == MVT::v32i8 ||
2387
44
      LocVT == MVT::v16i16 ||
2388
44
      LocVT == MVT::v8i32 ||
2389
39
      LocVT == MVT::v4i64 ||
2390
39
      LocVT == MVT::v8f32 ||
2391
44
      
LocVT == MVT::v4f6439
) {
2392
5
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()5
) {
2393
5
      static const MCPhysReg RegList6[] = {
2394
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2395
5
      };
2396
5
      if (unsigned 
Reg5
= State.AllocateReg(RegList6)) {
2397
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2398
5
        return false;
2399
5
      }
2400
5
    }
2401
5
  }
2402
44
2403
39
  
if (39
LocVT == MVT::v64i8 ||
2404
39
      LocVT == MVT::v32i16 ||
2405
39
      LocVT == MVT::v16i32 ||
2406
34
      LocVT == MVT::v8i64 ||
2407
34
      LocVT == MVT::v16f32 ||
2408
39
      
LocVT == MVT::v8f6410
) {
2409
29
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()29
) {
2410
29
      static const MCPhysReg RegList7[] = {
2411
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2412
29
      };
2413
29
      if (unsigned 
Reg29
= State.AllocateReg(RegList7)) {
2414
27
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2415
27
        return false;
2416
27
      }
2417
29
    }
2418
29
  }
2419
39
2420
12
  
if (12
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()12
) {
2421
12
    if (LocVT == MVT::i32 ||
2422
12
        LocVT == MVT::i64 ||
2423
10
        LocVT == MVT::f32 ||
2424
12
        
LocVT == MVT::f6410
) {
2425
2
      unsigned Offset8 = State.AllocateStack(8, 8);
2426
2
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2427
2
      return false;
2428
2
    }
2429
12
  }
2430
12
2431
10
  
if (10
LocVT == MVT::i32 ||
2432
10
      
LocVT == MVT::f3210
) {
2433
0
    unsigned Offset9 = State.AllocateStack(4, 4);
2434
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2435
0
    return false;
2436
0
  }
2437
10
2438
10
  
if (10
LocVT == MVT::i64 ||
2439
10
      
LocVT == MVT::f6410
) {
2440
0
    unsigned Offset10 = State.AllocateStack(8, 4);
2441
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2442
0
    return false;
2443
0
  }
2444
10
2445
10
  
if (10
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()10
) {
2446
10
    if (
LocVT == MVT::x86mmx10
) {
2447
0
      unsigned Offset11 = State.AllocateStack(8, 8);
2448
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2449
0
      return false;
2450
0
    }
2451
10
  }
2452
10
2453
10
  
if (10
LocVT == MVT::x86mmx10
) {
2454
0
    unsigned Offset12 = State.AllocateStack(8, 4);
2455
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2456
0
    return false;
2457
0
  }
2458
10
2459
10
  
if (10
LocVT == MVT::f80 ||
2460
10
      
LocVT == MVT::f12810
) {
2461
0
    unsigned Offset13 = State.AllocateStack(
2462
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
2463
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2464
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2465
0
    return false;
2466
0
  }
2467
10
2468
10
  
if (10
LocVT == MVT::v16i8 ||
2469
10
      LocVT == MVT::v8i16 ||
2470
10
      LocVT == MVT::v4i32 ||
2471
10
      LocVT == MVT::v2i64 ||
2472
10
      LocVT == MVT::v4f32 ||
2473
10
      
LocVT == MVT::v2f642
) {
2474
8
    unsigned Offset14 = State.AllocateStack(16, 16);
2475
8
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2476
8
    return false;
2477
8
  }
2478
10
2479
2
  
if (2
LocVT == MVT::v32i8 ||
2480
2
      LocVT == MVT::v16i16 ||
2481
2
      LocVT == MVT::v8i32 ||
2482
2
      LocVT == MVT::v4i64 ||
2483
2
      LocVT == MVT::v8f32 ||
2484
2
      
LocVT == MVT::v4f642
) {
2485
0
    unsigned Offset15 = State.AllocateStack(32, 32);
2486
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2487
0
    return false;
2488
0
  }
2489
2
2490
2
  
if (2
LocVT == MVT::v16i32 ||
2491
2
      LocVT == MVT::v8i64 ||
2492
2
      LocVT == MVT::v16f32 ||
2493
2
      
LocVT == MVT::v8f640
) {
2494
2
    unsigned Offset16 = State.AllocateStack(64, 64);
2495
2
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2496
2
    return false;
2497
2
  }
2498
2
2499
0
  return true;  // CC didn't match.
2500
195
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_Win64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
2501
2502
2503
static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
2504
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
2505
152
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
2506
152
2507
152
  if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2508
135
    return false;
2509
152
2510
17
  
if (17
!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)17
)
2511
17
    return false;
2512
17
2513
0
  return true;  // CC didn't match.
2514
152
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_Win64_VectorCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_Win64_VectorCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_Win64_VectorCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2505
152
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
2506
152
2507
152
  if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2508
135
    return false;
2509
152
2510
17
  
if (17
!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)17
)
2511
17
    return false;
2512
17
2513
0
  return true;  // CC didn't match.
2514
152
}
2515
2516
2517
static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
2518
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
2519
192
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
2520
192
2521
192
  if (LocVT == MVT::f32 ||
2522
192
      LocVT == MVT::f64 ||
2523
192
      LocVT == MVT::v4i32 ||
2524
192
      LocVT == MVT::v2i64 ||
2525
192
      LocVT == MVT::v4f32 ||
2526
192
      
LocVT == MVT::v2f64104
) {
2527
88
    static const MCPhysReg RegList1[] = {
2528
88
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2529
88
    };
2530
88
    if (unsigned 
Reg88
= State.AllocateReg(RegList1)) {
2531
88
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2532
88
      return false;
2533
88
    }
2534
88
  }
2535
192
2536
104
  
if (104
LocVT == MVT::v8f32 ||
2537
56
      LocVT == MVT::v4f64 ||
2538
56
      LocVT == MVT::v8i32 ||
2539
104
      
LocVT == MVT::v4i6456
) {
2540
48
    static const MCPhysReg RegList2[] = {
2541
48
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2542
48
    };
2543
48
    if (unsigned 
Reg48
= State.AllocateReg(RegList2)) {
2544
48
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2545
48
      return false;
2546
48
    }
2547
48
  }
2548
104
2549
56
  
if (56
LocVT == MVT::v16f32 ||
2550
8
      LocVT == MVT::v8f64 ||
2551
8
      LocVT == MVT::v16i32 ||
2552
56
      
LocVT == MVT::v8i648
) {
2553
48
    static const MCPhysReg RegList3[] = {
2554
48
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2555
48
    };
2556
48
    if (unsigned 
Reg48
= State.AllocateReg(RegList3)) {
2557
48
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2558
48
      return false;
2559
48
    }
2560
48
  }
2561
56
2562
8
  
if (8
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)8
)
2563
8
    return false;
2564
8
2565
0
  return true;  // CC didn't match.
2566
192
}
Unexecuted instantiation: X86FastISel.cpp:RetCC_Intel_OCL_BI(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:RetCC_Intel_OCL_BI(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2519
192
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
2520
192
2521
192
  if (LocVT == MVT::f32 ||
2522
192
      LocVT == MVT::f64 ||
2523
192
      LocVT == MVT::v4i32 ||
2524
192
      LocVT == MVT::v2i64 ||
2525
192
      LocVT == MVT::v4f32 ||
2526
192
      
LocVT == MVT::v2f64104
) {
2527
88
    static const MCPhysReg RegList1[] = {
2528
88
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2529
88
    };
2530
88
    if (unsigned 
Reg88
= State.AllocateReg(RegList1)) {
2531
88
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2532
88
      return false;
2533
88
    }
2534
88
  }
2535
192
2536
104
  
if (104
LocVT == MVT::v8f32 ||
2537
56
      LocVT == MVT::v4f64 ||
2538
56
      LocVT == MVT::v8i32 ||
2539
104
      
LocVT == MVT::v4i6456
) {
2540
48
    static const MCPhysReg RegList2[] = {
2541
48
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2542
48
    };
2543
48
    if (unsigned 
Reg48
= State.AllocateReg(RegList2)) {
2544
48
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2545
48
      return false;
2546
48
    }
2547
48
  }
2548
104
2549
56
  
if (56
LocVT == MVT::v16f32 ||
2550
8
      LocVT == MVT::v8f64 ||
2551
8
      LocVT == MVT::v16i32 ||
2552
56
      
LocVT == MVT::v8i648
) {
2553
48
    static const MCPhysReg RegList3[] = {
2554
48
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2555
48
    };
2556
48
    if (unsigned 
Reg48
= State.AllocateReg(RegList3)) {
2557
48
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2558
48
      return false;
2559
48
    }
2560
48
  }
2561
56
2562
8
  
if (8
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)8
)
2563
8
    return false;
2564
8
2565
0
  return true;  // CC didn't match.
2566
192
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_Intel_OCL_BI(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
2567
2568
2569
static bool RetCC_X86(unsigned ValNo, MVT ValVT,
2570
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
2571
161k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
2572
161k
2573
161k
  if (
State.getCallingConv() == CallingConv::Intel_OCL_BI161k
) {
2574
192
    if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2575
192
      return false;
2576
192
  }
2577
161k
2578
160k
  
if (160k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()160k
) {
2579
124k
    if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2580
124k
      return false;
2581
124k
  }
2582
160k
2583
36.0k
  
if (36.0k
!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)36.0k
)
2584
35.4k
    return false;
2585
36.0k
2586
592
  return true;  // CC didn't match.
2587
161k
}
X86ISelLowering.cpp:RetCC_X86(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2571
156k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
2572
156k
2573
156k
  if (
State.getCallingConv() == CallingConv::Intel_OCL_BI156k
) {
2574
192
    if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2575
192
      return false;
2576
192
  }
2577
156k
2578
156k
  
if (156k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()156k
) {
2579
121k
    if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2580
121k
      return false;
2581
121k
  }
2582
156k
2583
34.6k
  
if (34.6k
!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)34.6k
)
2584
34.0k
    return false;
2585
34.6k
2586
592
  return true;  // CC didn't match.
2587
156k
}
X86FastISel.cpp:RetCC_X86(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2571
4.38k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
2572
4.38k
2573
4.38k
  if (
State.getCallingConv() == CallingConv::Intel_OCL_BI4.38k
) {
2574
0
    if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2575
0
      return false;
2576
0
  }
2577
4.38k
2578
4.38k
  
if (4.38k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()4.38k
) {
2579
3.02k
    if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2580
3.02k
      return false;
2581
3.02k
  }
2582
4.38k
2583
1.35k
  
if (1.35k
!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)1.35k
)
2584
1.35k
    return false;
2585
1.35k
2586
0
  return true;  // CC didn't match.
2587
4.38k
}
X86CallLowering.cpp:RetCC_X86(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2571
361
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
2572
361
2573
361
  if (
State.getCallingConv() == CallingConv::Intel_OCL_BI361
) {
2574
0
    if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2575
0
      return false;
2576
0
  }
2577
361
2578
361
  
if (361
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()361
) {
2579
289
    if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2580
289
      return false;
2581
289
  }
2582
361
2583
72
  
if (72
!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)72
)
2584
72
    return false;
2585
72
2586
0
  return true;  // CC didn't match.
2587
361
}
2588
2589
2590
static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
2591
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
2592
152k
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
2593
152k
2594
152k
  if (
LocVT == MVT::v1i1152k
) {
2595
0
    LocVT = MVT::i8;
2596
0
    if (ArgFlags.isSExt())
2597
0
        LocInfo = CCValAssign::SExt;
2598
0
    else 
if (0
ArgFlags.isZExt()0
)
2599
0
        LocInfo = CCValAssign::ZExt;
2600
0
    else
2601
0
        LocInfo = CCValAssign::AExt;
2602
0
  }
2603
152k
2604
152k
  if (
LocVT == MVT::i1152k
) {
2605
5
    LocVT = MVT::i8;
2606
5
    if (ArgFlags.isSExt())
2607
0
        LocInfo = CCValAssign::SExt;
2608
5
    else 
if (5
ArgFlags.isZExt()5
)
2609
0
        LocInfo = CCValAssign::ZExt;
2610
5
    else
2611
5
        LocInfo = CCValAssign::AExt;
2612
5
  }
2613
152k
2614
152k
  if (
LocVT == MVT::i8152k
) {
2615
4.77k
    static const MCPhysReg RegList1[] = {
2616
4.77k
      X86::AL, X86::DL, X86::CL
2617
4.77k
    };
2618
4.77k
    if (unsigned 
Reg4.77k
= State.AllocateReg(RegList1)) {
2619
4.70k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2620
4.70k
      return false;
2621
4.70k
    }
2622
4.77k
  }
2623
152k
2624
148k
  
if (148k
LocVT == MVT::i16148k
) {
2625
2.09k
    static const MCPhysReg RegList2[] = {
2626
2.09k
      X86::AX, X86::DX, X86::CX
2627
2.09k
    };
2628
2.09k
    if (unsigned 
Reg2.09k
= State.AllocateReg(RegList2)) {
2629
2.08k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2630
2.08k
      return false;
2631
2.08k
    }
2632
2.09k
  }
2633
148k
2634
146k
  
if (146k
LocVT == MVT::i32146k
) {
2635
40.8k
    static const MCPhysReg RegList3[] = {
2636
40.8k
      X86::EAX, X86::EDX, X86::ECX
2637
40.8k
    };
2638
40.8k
    if (unsigned 
Reg40.8k
= State.AllocateReg(RegList3)) {
2639
40.4k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2640
40.4k
      return false;
2641
40.4k
    }
2642
40.8k
  }
2643
146k
2644
105k
  
if (105k
LocVT == MVT::i64105k
) {
2645
19.1k
    static const MCPhysReg RegList4[] = {
2646
19.1k
      X86::RAX, X86::RDX, X86::RCX
2647
19.1k
    };
2648
19.1k
    if (unsigned 
Reg19.1k
= State.AllocateReg(RegList4)) {
2649
19.0k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2650
19.0k
      return false;
2651
19.0k
    }
2652
19.1k
  }
2653
105k
2654
86.5k
  
if (86.5k
LocVT == MVT::v2i186.5k
) {
2655
8
    LocVT = MVT::v2i64;
2656
8
    if (ArgFlags.isSExt())
2657
0
        LocInfo = CCValAssign::SExt;
2658
8
    else 
if (8
ArgFlags.isZExt()8
)
2659
0
        LocInfo = CCValAssign::ZExt;
2660
8
    else
2661
8
        LocInfo = CCValAssign::AExt;
2662
8
  }
2663
86.5k
2664
86.5k
  if (
LocVT == MVT::v4i186.5k
) {
2665
18
    LocVT = MVT::v4i32;
2666
18
    if (ArgFlags.isSExt())
2667
0
        LocInfo = CCValAssign::SExt;
2668
18
    else 
if (18
ArgFlags.isZExt()18
)
2669
0
        LocInfo = CCValAssign::ZExt;
2670
18
    else
2671
18
        LocInfo = CCValAssign::AExt;
2672
18
  }
2673
86.5k
2674
86.5k
  if (
LocVT == MVT::v8i186.5k
) {
2675
100
    LocVT = MVT::v8i16;
2676
100
    if (ArgFlags.isSExt())
2677
0
        LocInfo = CCValAssign::SExt;
2678
100
    else 
if (100
ArgFlags.isZExt()100
)
2679
0
        LocInfo = CCValAssign::ZExt;
2680
100
    else
2681
100
        LocInfo = CCValAssign::AExt;
2682
100
  }
2683
86.5k
2684
86.5k
  if (
LocVT == MVT::v16i186.5k
) {
2685
126
    LocVT = MVT::v16i8;
2686
126
    if (ArgFlags.isSExt())
2687
0
        LocInfo = CCValAssign::SExt;
2688
126
    else 
if (126
ArgFlags.isZExt()126
)
2689
0
        LocInfo = CCValAssign::ZExt;
2690
126
    else
2691
126
        LocInfo = CCValAssign::AExt;
2692
126
  }
2693
86.5k
2694
86.5k
  if (
LocVT == MVT::v32i186.5k
) {
2695
22
    LocVT = MVT::v32i8;
2696
22
    if (ArgFlags.isSExt())
2697
0
        LocInfo = CCValAssign::SExt;
2698
22
    else 
if (22
ArgFlags.isZExt()22
)
2699
0
        LocInfo = CCValAssign::ZExt;
2700
22
    else
2701
22
        LocInfo = CCValAssign::AExt;
2702
22
  }
2703
86.5k
2704
86.5k
  if (
LocVT == MVT::v64i186.5k
) {
2705
20
    LocVT = MVT::v64i8;
2706
20
    if (ArgFlags.isSExt())
2707
0
        LocInfo = CCValAssign::SExt;
2708
20
    else 
if (20
ArgFlags.isZExt()20
)
2709
0
        LocInfo = CCValAssign::ZExt;
2710
20
    else
2711
20
        LocInfo = CCValAssign::AExt;
2712
20
  }
2713
86.5k
2714
86.5k
  if (LocVT == MVT::v16i8 ||
2715
80.1k
      LocVT == MVT::v8i16 ||
2716
72.1k
      LocVT == MVT::v4i32 ||
2717
62.0k
      LocVT == MVT::v2i64 ||
2718
54.0k
      LocVT == MVT::v4f32 ||
2719
86.5k
      
LocVT == MVT::v2f6444.6k
) {
2720
47.2k
    static const MCPhysReg RegList5[] = {
2721
47.2k
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2722
47.2k
    };
2723
47.2k
    if (unsigned 
Reg47.2k
= State.AllocateReg(RegList5)) {
2724
47.2k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2725
47.2k
      return false;
2726
47.2k
    }
2727
47.2k
  }
2728
86.5k
2729
39.3k
  
if (39.3k
LocVT == MVT::v32i8 ||
2730
35.3k
      LocVT == MVT::v16i16 ||
2731
30.4k
      LocVT == MVT::v8i32 ||
2732
25.9k
      LocVT == MVT::v4i64 ||
2733
21.4k
      LocVT == MVT::v8f32 ||
2734
39.3k
      
LocVT == MVT::v4f6416.1k
) {
2735
27.5k
    static const MCPhysReg RegList6[] = {
2736
27.5k
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2737
27.5k
    };
2738
27.5k
    if (unsigned 
Reg27.5k
= State.AllocateReg(RegList6)) {
2739
27.5k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2740
27.5k
      return false;
2741
27.5k
    }
2742
27.5k
  }
2743
39.3k
2744
11.8k
  
if (11.8k
LocVT == MVT::v64i8 ||
2745
11.1k
      LocVT == MVT::v32i16 ||
2746
10.0k
      LocVT == MVT::v16i32 ||
2747
8.19k
      LocVT == MVT::v8i64 ||
2748
6.09k
      LocVT == MVT::v16f32 ||
2749
11.8k
      
LocVT == MVT::v8f643.84k
) {
2750
10.3k
    static const MCPhysReg RegList7[] = {
2751
10.3k
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2752
10.3k
    };
2753
10.3k
    if (unsigned 
Reg10.3k
= State.AllocateReg(RegList7)) {
2754
10.3k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2755
10.3k
      return false;
2756
10.3k
    }
2757
10.3k
  }
2758
11.8k
2759
1.45k
  
if (1.45k
LocVT == MVT::x86mmx1.45k
) {
2760
6
    if (unsigned 
Reg6
= State.AllocateReg(X86::MM0)) {
2761
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2762
6
      return false;
2763
6
    }
2764
6
  }
2765
1.45k
2766
1.44k
  
if (1.44k
LocVT == MVT::f801.44k
) {
2767
695
    static const MCPhysReg RegList8[] = {
2768
695
      X86::FP0, X86::FP1
2769
695
    };
2770
695
    if (unsigned 
Reg695
= State.AllocateReg(RegList8)) {
2771
695
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2772
695
      return false;
2773
695
    }
2774
695
  }
2775
1.44k
2776
752
  return true;  // CC didn't match.
2777
152k
}
X86ISelLowering.cpp:RetCC_X86Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2592
148k
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
2593
148k
2594
148k
  if (
LocVT == MVT::v1i1148k
) {
2595
0
    LocVT = MVT::i8;
2596
0
    if (ArgFlags.isSExt())
2597
0
        LocInfo = CCValAssign::SExt;
2598
0
    else 
if (0
ArgFlags.isZExt()0
)
2599
0
        LocInfo = CCValAssign::ZExt;
2600
0
    else
2601
0
        LocInfo = CCValAssign::AExt;
2602
0
  }
2603
148k
2604
148k
  if (
LocVT == MVT::i1148k
) {
2605
0
    LocVT = MVT::i8;
2606
0
    if (ArgFlags.isSExt())
2607
0
        LocInfo = CCValAssign::SExt;
2608
0
    else 
if (0
ArgFlags.isZExt()0
)
2609
0
        LocInfo = CCValAssign::ZExt;
2610
0
    else
2611
0
        LocInfo = CCValAssign::AExt;
2612
0
  }
2613
148k
2614
148k
  if (
LocVT == MVT::i8148k
) {
2615
4.69k
    static const MCPhysReg RegList1[] = {
2616
4.69k
      X86::AL, X86::DL, X86::CL
2617
4.69k
    };
2618
4.69k
    if (unsigned 
Reg4.69k
= State.AllocateReg(RegList1)) {
2619
4.61k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2620
4.61k
      return false;
2621
4.61k
    }
2622
4.69k
  }
2623
148k
2624
143k
  
if (143k
LocVT == MVT::i16143k
) {
2625
2.03k
    static const MCPhysReg RegList2[] = {
2626
2.03k
      X86::AX, X86::DX, X86::CX
2627
2.03k
    };
2628
2.03k
    if (unsigned 
Reg2.03k
= State.AllocateReg(RegList2)) {
2629
2.02k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2630
2.02k
      return false;
2631
2.02k
    }
2632
2.03k
  }
2633
143k
2634
141k
  
if (141k
LocVT == MVT::i32141k
) {
2635
39.5k
    static const MCPhysReg RegList3[] = {
2636
39.5k
      X86::EAX, X86::EDX, X86::ECX
2637
39.5k
    };
2638
39.5k
    if (unsigned 
Reg39.5k
= State.AllocateReg(RegList3)) {
2639
39.1k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2640
39.1k
      return false;
2641
39.1k
    }
2642
39.5k
  }
2643
141k
2644
102k
  
if (102k
LocVT == MVT::i64102k
) {
2645
18.8k
    static const MCPhysReg RegList4[] = {
2646
18.8k
      X86::RAX, X86::RDX, X86::RCX
2647
18.8k
    };
2648
18.8k
    if (unsigned 
Reg18.8k
= State.AllocateReg(RegList4)) {
2649
18.7k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2650
18.7k
      return false;
2651
18.7k
    }
2652
18.8k
  }
2653
102k
2654
83.8k
  
if (83.8k
LocVT == MVT::v2i183.8k
) {
2655
8
    LocVT = MVT::v2i64;
2656
8
    if (ArgFlags.isSExt())
2657
0
        LocInfo = CCValAssign::SExt;
2658
8
    else 
if (8
ArgFlags.isZExt()8
)
2659
0
        LocInfo = CCValAssign::ZExt;
2660
8
    else
2661
8
        LocInfo = CCValAssign::AExt;
2662
8
  }
2663
83.8k
2664
83.8k
  if (
LocVT == MVT::v4i183.8k
) {
2665
18
    LocVT = MVT::v4i32;
2666
18
    if (ArgFlags.isSExt())
2667
0
        LocInfo = CCValAssign::SExt;
2668
18
    else 
if (18
ArgFlags.isZExt()18
)
2669
0
        LocInfo = CCValAssign::ZExt;
2670
18
    else
2671
18
        LocInfo = CCValAssign::AExt;
2672
18
  }
2673
83.8k
2674
83.8k
  if (
LocVT == MVT::v8i183.8k
) {
2675
100
    LocVT = MVT::v8i16;
2676
100
    if (ArgFlags.isSExt())
2677
0
        LocInfo = CCValAssign::SExt;
2678
100
    else 
if (100
ArgFlags.isZExt()100
)
2679
0
        LocInfo = CCValAssign::ZExt;
2680
100
    else
2681
100
        LocInfo = CCValAssign::AExt;
2682
100
  }
2683
83.8k
2684
83.8k
  if (
LocVT == MVT::v16i183.8k
) {
2685
126
    LocVT = MVT::v16i8;
2686
126
    if (ArgFlags.isSExt())
2687
0
        LocInfo = CCValAssign::SExt;
2688
126
    else 
if (126
ArgFlags.isZExt()126
)
2689
0
        LocInfo = CCValAssign::ZExt;
2690
126
    else
2691
126
        LocInfo = CCValAssign::AExt;
2692
126
  }
2693
83.8k
2694
83.8k
  if (
LocVT == MVT::v32i183.8k
) {
2695
22
    LocVT = MVT::v32i8;
2696
22
    if (ArgFlags.isSExt())
2697
0
        LocInfo = CCValAssign::SExt;
2698
22
    else 
if (22
ArgFlags.isZExt()22
)
2699
0
        LocInfo = CCValAssign::ZExt;
2700
22
    else
2701
22
        LocInfo = CCValAssign::AExt;
2702
22
  }
2703
83.8k
2704
83.8k
  if (
LocVT == MVT::v64i183.8k
) {
2705
20
    LocVT = MVT::v64i8;
2706
20
    if (ArgFlags.isSExt())
2707
0
        LocInfo = CCValAssign::SExt;
2708
20
    else 
if (20
ArgFlags.isZExt()20
)
2709
0
        LocInfo = CCValAssign::ZExt;
2710
20
    else
2711
20
        LocInfo = CCValAssign::AExt;
2712
20
  }
2713
83.8k
2714
83.8k
  if (LocVT == MVT::v16i8 ||
2715
77.4k
      LocVT == MVT::v8i16 ||
2716
69.4k
      LocVT == MVT::v4i32 ||
2717
59.5k
      LocVT == MVT::v2i64 ||
2718
52.1k
      LocVT == MVT::v4f32 ||
2719
83.8k
      
LocVT == MVT::v2f6443.1k
) {
2720
45.7k
    static const MCPhysReg RegList5[] = {
2721
45.7k
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2722
45.7k
    };
2723
45.7k
    if (unsigned 
Reg45.7k
= State.AllocateReg(RegList5)) {
2724
45.6k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2725
45.6k
      return false;
2726
45.6k
    }
2727
45.7k
  }
2728
83.8k
2729
38.1k
  
if (38.1k
LocVT == MVT::v32i8 ||
2730
34.1k
      LocVT == MVT::v16i16 ||
2731
29.2k
      LocVT == MVT::v8i32 ||
2732
24.8k
      LocVT == MVT::v4i64 ||
2733
20.7k
      LocVT == MVT::v8f32 ||
2734
38.1k
      
LocVT == MVT::v4f6415.7k
) {
2735
26.6k
    static const MCPhysReg RegList6[] = {
2736
26.6k
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2737
26.6k
    };
2738
26.6k
    if (unsigned 
Reg26.6k
= State.AllocateReg(RegList6)) {
2739
26.6k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2740
26.6k
      return false;
2741
26.6k
    }
2742
26.6k
  }
2743
38.1k
2744
11.5k
  
if (11.5k
LocVT == MVT::v64i8 ||
2745
10.8k
      LocVT == MVT::v32i16 ||
2746
9.76k
      LocVT == MVT::v16i32 ||
2747
7.93k
      LocVT == MVT::v8i64 ||
2748
5.95k
      LocVT == MVT::v16f32 ||
2749
11.5k
      
LocVT == MVT::v8f643.77k
) {
2750
10.0k
    static const MCPhysReg RegList7[] = {
2751
10.0k
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2752
10.0k
    };
2753
10.0k
    if (unsigned 
Reg10.0k
= State.AllocateReg(RegList7)) {
2754
10.0k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2755
10.0k
      return false;
2756
10.0k
    }
2757
10.0k
  }
2758
11.5k
2759
1.45k
  
if (1.45k
LocVT == MVT::x86mmx1.45k
) {
2760
6
    if (unsigned 
Reg6
= State.AllocateReg(X86::MM0)) {
2761
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2762
6
      return false;
2763
6
    }
2764
6
  }
2765
1.45k
2766
1.44k
  
if (1.44k
LocVT == MVT::f801.44k
) {
2767
693
    static const MCPhysReg RegList8[] = {
2768
693
      X86::FP0, X86::FP1
2769
693
    };
2770
693
    if (unsigned 
Reg693
= State.AllocateReg(RegList8)) {
2771
693
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2772
693
      return false;
2773
693
    }
2774
693
  }
2775
1.44k
2776
752
  return true;  // CC didn't match.
2777
148k
}
X86FastISel.cpp:RetCC_X86Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2592
4.20k
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
2593
4.20k
2594
4.20k
  if (
LocVT == MVT::v1i14.20k
) {
2595
0
    LocVT = MVT::i8;
2596
0
    if (ArgFlags.isSExt())
2597
0
        LocInfo = CCValAssign::SExt;
2598
0
    else 
if (0
ArgFlags.isZExt()0
)
2599
0
        LocInfo = CCValAssign::ZExt;
2600
0
    else
2601
0
        LocInfo = CCValAssign::AExt;
2602
0
  }
2603
4.20k
2604
4.20k
  if (
LocVT == MVT::i14.20k
) {
2605
0
    LocVT = MVT::i8;
2606
0
    if (ArgFlags.isSExt())
2607
0
        LocInfo = CCValAssign::SExt;
2608
0
    else 
if (0
ArgFlags.isZExt()0
)
2609
0
        LocInfo = CCValAssign::ZExt;
2610
0
    else
2611
0
        LocInfo = CCValAssign::AExt;
2612
0
  }
2613
4.20k
2614
4.20k
  if (
LocVT == MVT::i84.20k
) {
2615
58
    static const MCPhysReg RegList1[] = {
2616
58
      X86::AL, X86::DL, X86::CL
2617
58
    };
2618
58
    if (unsigned 
Reg58
= State.AllocateReg(RegList1)) {
2619
58
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2620
58
      return false;
2621
58
    }
2622
58
  }
2623
4.20k
2624
4.14k
  
if (4.14k
LocVT == MVT::i164.14k
) {
2625
39
    static const MCPhysReg RegList2[] = {
2626
39
      X86::AX, X86::DX, X86::CX
2627
39
    };
2628
39
    if (unsigned 
Reg39
= State.AllocateReg(RegList2)) {
2629
39
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2630
39
      return false;
2631
39
    }
2632
39
  }
2633
4.14k
2634
4.10k
  
if (4.10k
LocVT == MVT::i324.10k
) {
2635
1.19k
    static const MCPhysReg RegList3[] = {
2636
1.19k
      X86::EAX, X86::EDX, X86::ECX
2637
1.19k
    };
2638
1.19k
    if (unsigned 
Reg1.19k
= State.AllocateReg(RegList3)) {
2639
1.19k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2640
1.19k
      return false;
2641
1.19k
    }
2642
1.19k
  }
2643
4.10k
2644
2.91k
  
if (2.91k
LocVT == MVT::i642.91k
) {
2645
251
    static const MCPhysReg RegList4[] = {
2646
251
      X86::RAX, X86::RDX, X86::RCX
2647
251
    };
2648
251
    if (unsigned 
Reg251
= State.AllocateReg(RegList4)) {
2649
251
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2650
251
      return false;
2651
251
    }
2652
251
  }
2653
2.91k
2654
2.66k
  
if (2.66k
LocVT == MVT::v2i12.66k
) {
2655
0
    LocVT = MVT::v2i64;
2656
0
    if (ArgFlags.isSExt())
2657
0
        LocInfo = CCValAssign::SExt;
2658
0
    else 
if (0
ArgFlags.isZExt()0
)
2659
0
        LocInfo = CCValAssign::ZExt;
2660
0
    else
2661
0
        LocInfo = CCValAssign::AExt;
2662
0
  }
2663
2.66k
2664
2.66k
  if (
LocVT == MVT::v4i12.66k
) {
2665
0
    LocVT = MVT::v4i32;
2666
0
    if (ArgFlags.isSExt())
2667
0
        LocInfo = CCValAssign::SExt;
2668
0
    else 
if (0
ArgFlags.isZExt()0
)
2669
0
        LocInfo = CCValAssign::ZExt;
2670
0
    else
2671
0
        LocInfo = CCValAssign::AExt;
2672
0
  }
2673
2.66k
2674
2.66k
  if (
LocVT == MVT::v8i12.66k
) {
2675
0
    LocVT = MVT::v8i16;
2676
0
    if (ArgFlags.isSExt())
2677
0
        LocInfo = CCValAssign::SExt;
2678
0
    else 
if (0
ArgFlags.isZExt()0
)
2679
0
        LocInfo = CCValAssign::ZExt;
2680
0
    else
2681
0
        LocInfo = CCValAssign::AExt;
2682
0
  }
2683
2.66k
2684
2.66k
  if (
LocVT == MVT::v16i12.66k
) {
2685
0
    LocVT = MVT::v16i8;
2686
0
    if (ArgFlags.isSExt())
2687
0
        LocInfo = CCValAssign::SExt;
2688
0
    else 
if (0
ArgFlags.isZExt()0
)
2689
0
        LocInfo = CCValAssign::ZExt;
2690
0
    else
2691
0
        LocInfo = CCValAssign::AExt;
2692
0
  }
2693
2.66k
2694
2.66k
  if (
LocVT == MVT::v32i12.66k
) {
2695
0
    LocVT = MVT::v32i8;
2696
0
    if (ArgFlags.isSExt())
2697
0
        LocInfo = CCValAssign::SExt;
2698
0
    else 
if (0
ArgFlags.isZExt()0
)
2699
0
        LocInfo = CCValAssign::ZExt;
2700
0
    else
2701
0
        LocInfo = CCValAssign::AExt;
2702
0
  }
2703
2.66k
2704
2.66k
  if (
LocVT == MVT::v64i12.66k
) {
2705
0
    LocVT = MVT::v64i8;
2706
0
    if (ArgFlags.isSExt())
2707
0
        LocInfo = CCValAssign::SExt;
2708
0
    else 
if (0
ArgFlags.isZExt()0
)
2709
0
        LocInfo = CCValAssign::ZExt;
2710
0
    else
2711
0
        LocInfo = CCValAssign::AExt;
2712
0
  }
2713
2.66k
2714
2.66k
  if (LocVT == MVT::v16i8 ||
2715
2.60k
      LocVT == MVT::v8i16 ||
2716
2.54k
      LocVT == MVT::v4i32 ||
2717
2.44k
      LocVT == MVT::v2i64 ||
2718
1.84k
      LocVT == MVT::v4f32 ||
2719
2.66k
      
LocVT == MVT::v2f641.49k
) {
2720
1.47k
    static const MCPhysReg RegList5[] = {
2721
1.47k
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2722
1.47k
    };
2723
1.47k
    if (unsigned 
Reg1.47k
= State.AllocateReg(RegList5)) {
2724
1.47k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2725
1.47k
      return false;
2726
1.47k
    }
2727
1.47k
  }
2728
2.66k
2729
1.18k
  
if (1.18k
LocVT == MVT::v32i8 ||
2730
1.15k
      LocVT == MVT::v16i16 ||
2731
1.12k
      LocVT == MVT::v8i32 ||
2732
1.08k
      LocVT == MVT::v4i64 ||
2733
659
      LocVT == MVT::v8f32 ||
2734
1.18k
      
LocVT == MVT::v4f64476
) {
2735
889
    static const MCPhysReg RegList6[] = {
2736
889
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2737
889
    };
2738
889
    if (unsigned 
Reg889
= State.AllocateReg(RegList6)) {
2739
889
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2740
889
      return false;
2741
889
    }
2742
889
  }
2743
1.18k
2744
297
  
if (297
LocVT == MVT::v64i8 ||
2745
289
      LocVT == MVT::v32i16 ||
2746
281
      LocVT == MVT::v16i32 ||
2747
258
      LocVT == MVT::v8i64 ||
2748
135
      LocVT == MVT::v16f32 ||
2749
297
      
LocVT == MVT::v8f6469
) {
2750
295
    static const MCPhysReg RegList7[] = {
2751
295
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2752
295
    };
2753
295
    if (unsigned 
Reg295
= State.AllocateReg(RegList7)) {
2754
295
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2755
295
      return false;
2756
295
    }
2757
295
  }
2758
297
2759
2
  
if (2
LocVT == MVT::x86mmx2
) {
2760
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::MM0)) {
2761
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2762
0
      return false;
2763
0
    }
2764
0
  }
2765
2
2766
2
  
if (2
LocVT == MVT::f802
) {
2767
2
    static const MCPhysReg RegList8[] = {
2768
2
      X86::FP0, X86::FP1
2769
2
    };
2770
2
    if (unsigned 
Reg2
= State.AllocateReg(RegList8)) {
2771
2
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2772
2
      return false;
2773
2
    }
2774
2
  }
2775
2
2776
0
  return true;  // CC didn't match.
2777
4.20k
}
X86CallLowering.cpp:RetCC_X86Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2592
320
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
2593
320
2594
320
  if (
LocVT == MVT::v1i1320
) {
2595
0
    LocVT = MVT::i8;
2596
0
    if (ArgFlags.isSExt())
2597
0
        LocInfo = CCValAssign::SExt;
2598
0
    else 
if (0
ArgFlags.isZExt()0
)
2599
0
        LocInfo = CCValAssign::ZExt;
2600
0
    else
2601
0
        LocInfo = CCValAssign::AExt;
2602
0
  }
2603
320
2604
320
  if (
LocVT == MVT::i1320
) {
2605
5
    LocVT = MVT::i8;
2606
5
    if (ArgFlags.isSExt())
2607
0
        LocInfo = CCValAssign::SExt;
2608
5
    else 
if (5
ArgFlags.isZExt()5
)
2609
0
        LocInfo = CCValAssign::ZExt;
2610
5
    else
2611
5
        LocInfo = CCValAssign::AExt;
2612
5
  }
2613
320
2614
320
  if (
LocVT == MVT::i8320
) {
2615
27
    static const MCPhysReg RegList1[] = {
2616
27
      X86::AL, X86::DL, X86::CL
2617
27
    };
2618
27
    if (unsigned 
Reg27
= State.AllocateReg(RegList1)) {
2619
27
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2620
27
      return false;
2621
27
    }
2622
27
  }
2623
320
2624
293
  
if (293
LocVT == MVT::i16293
) {
2625
19
    static const MCPhysReg RegList2[] = {
2626
19
      X86::AX, X86::DX, X86::CX
2627
19
    };
2628
19
    if (unsigned 
Reg19
= State.AllocateReg(RegList2)) {
2629
19
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2630
19
      return false;
2631
19
    }
2632
19
  }
2633
293
2634
274
  
if (274
LocVT == MVT::i32274
) {
2635
106
    static const MCPhysReg RegList3[] = {
2636
106
      X86::EAX, X86::EDX, X86::ECX
2637
106
    };
2638
106
    if (unsigned 
Reg106
= State.AllocateReg(RegList3)) {
2639
106
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2640
106
      return false;
2641
106
    }
2642
106
  }
2643
274
2644
168
  
if (168
LocVT == MVT::i64168
) {
2645
47
    static const MCPhysReg RegList4[] = {
2646
47
      X86::RAX, X86::RDX, X86::RCX
2647
47
    };
2648
47
    if (unsigned 
Reg47
= State.AllocateReg(RegList4)) {
2649
47
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2650
47
      return false;
2651
47
    }
2652
47
  }
2653
168
2654
121
  
if (121
LocVT == MVT::v2i1121
) {
2655
0
    LocVT = MVT::v2i64;
2656
0
    if (ArgFlags.isSExt())
2657
0
        LocInfo = CCValAssign::SExt;
2658
0
    else 
if (0
ArgFlags.isZExt()0
)
2659
0
        LocInfo = CCValAssign::ZExt;
2660
0
    else
2661
0
        LocInfo = CCValAssign::AExt;
2662
0
  }
2663
121
2664
121
  if (
LocVT == MVT::v4i1121
) {
2665
0
    LocVT = MVT::v4i32;
2666
0
    if (ArgFlags.isSExt())
2667
0
        LocInfo = CCValAssign::SExt;
2668
0
    else 
if (0
ArgFlags.isZExt()0
)
2669
0
        LocInfo = CCValAssign::ZExt;
2670
0
    else
2671
0
        LocInfo = CCValAssign::AExt;
2672
0
  }
2673
121
2674
121
  if (
LocVT == MVT::v8i1121
) {
2675
0
    LocVT = MVT::v8i16;
2676
0
    if (ArgFlags.isSExt())
2677
0
        LocInfo = CCValAssign::SExt;
2678
0
    else 
if (0
ArgFlags.isZExt()0
)
2679
0
        LocInfo = CCValAssign::ZExt;
2680
0
    else
2681
0
        LocInfo = CCValAssign::AExt;
2682
0
  }
2683
121
2684
121
  if (
LocVT == MVT::v16i1121
) {
2685
0
    LocVT = MVT::v16i8;
2686
0
    if (ArgFlags.isSExt())
2687
0
        LocInfo = CCValAssign::SExt;
2688
0
    else 
if (0
ArgFlags.isZExt()0
)
2689
0
        LocInfo = CCValAssign::ZExt;
2690
0
    else
2691
0
        LocInfo = CCValAssign::AExt;
2692
0
  }
2693
121
2694
121
  if (
LocVT == MVT::v32i1121
) {
2695
0
    LocVT = MVT::v32i8;
2696
0
    if (ArgFlags.isSExt())
2697
0
        LocInfo = CCValAssign::SExt;
2698
0
    else 
if (0
ArgFlags.isZExt()0
)
2699
0
        LocInfo = CCValAssign::ZExt;
2700
0
    else
2701
0
        LocInfo = CCValAssign::AExt;
2702
0
  }
2703
121
2704
121
  if (
LocVT == MVT::v64i1121
) {
2705
0
    LocVT = MVT::v64i8;
2706
0
    if (ArgFlags.isSExt())
2707
0
        LocInfo = CCValAssign::SExt;
2708
0
    else 
if (0
ArgFlags.isZExt()0
)
2709
0
        LocInfo = CCValAssign::ZExt;
2710
0
    else
2711
0
        LocInfo = CCValAssign::AExt;
2712
0
  }
2713
121
2714
121
  if (LocVT == MVT::v16i8 ||
2715
117
      LocVT == MVT::v8i16 ||
2716
112
      LocVT == MVT::v4i32 ||
2717
67
      LocVT == MVT::v2i64 ||
2718
62
      LocVT == MVT::v4f32 ||
2719
121
      
LocVT == MVT::v2f6454
) {
2720
67
    static const MCPhysReg RegList5[] = {
2721
67
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2722
67
    };
2723
67
    if (unsigned 
Reg67
= State.AllocateReg(RegList5)) {
2724
67
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2725
67
      return false;
2726
67
    }
2727
67
  }
2728
121
2729
54
  
if (54
LocVT == MVT::v32i8 ||
2730
46
      LocVT == MVT::v16i16 ||
2731
37
      LocVT == MVT::v8i32 ||
2732
24
      LocVT == MVT::v4i64 ||
2733
15
      LocVT == MVT::v8f32 ||
2734
54
      
LocVT == MVT::v4f6415
) {
2735
39
    static const MCPhysReg RegList6[] = {
2736
39
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2737
39
    };
2738
39
    if (unsigned 
Reg39
= State.AllocateReg(RegList6)) {
2739
39
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2740
39
      return false;
2741
39
    }
2742
39
  }
2743
54
2744
15
  
if (15
LocVT == MVT::v64i8 ||
2745
13
      LocVT == MVT::v32i16 ||
2746
10
      LocVT == MVT::v16i32 ||
2747
3
      LocVT == MVT::v8i64 ||
2748
0
      LocVT == MVT::v16f32 ||
2749
15
      
LocVT == MVT::v8f640
) {
2750
15
    static const MCPhysReg RegList7[] = {
2751
15
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2752
15
    };
2753
15
    if (unsigned 
Reg15
= State.AllocateReg(RegList7)) {
2754
15
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2755
15
      return false;
2756
15
    }
2757
15
  }
2758
15
2759
0
  
if (0
LocVT == MVT::x86mmx0
) {
2760
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::MM0)) {
2761
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2762
0
      return false;
2763
0
    }
2764
0
  }
2765
0
2766
0
  
if (0
LocVT == MVT::f800
) {
2767
0
    static const MCPhysReg RegList8[] = {
2768
0
      X86::FP0, X86::FP1
2769
0
    };
2770
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList8)) {
2771
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2772
0
      return false;
2773
0
    }
2774
0
  }
2775
0
2776
0
  return true;  // CC didn't match.
2777
320
}
2778
2779
2780
static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
2781
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
2782
36.0k
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
2783
36.0k
2784
36.0k
  if (
State.getCallingConv() == CallingConv::Fast36.0k
) {
2785
311
    if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2786
297
      return false;
2787
311
  }
2788
36.0k
2789
35.7k
  
if (35.7k
State.getCallingConv() == CallingConv::HiPE35.7k
) {
2790
30
    if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2791
30
      return false;
2792
30
  }
2793
35.7k
2794
35.7k
  
if (35.7k
State.getCallingConv() == CallingConv::X86_VectorCall35.7k
) {
2795
80
    if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2796
76
      return false;
2797
80
  }
2798
35.7k
2799
35.6k
  
if (35.6k
State.getCallingConv() == CallingConv::X86_RegCall35.6k
) {
2800
178
    if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2801
178
      return false;
2802
178
  }
2803
35.6k
2804
35.4k
  
if (35.4k
!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)35.4k
)
2805
34.9k
    return false;
2806
35.4k
2807
591
  return true;  // CC didn't match.
2808
36.0k
}
X86ISelLowering.cpp:RetCC_X86_32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2782
34.6k
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
2783
34.6k
2784
34.6k
  if (
State.getCallingConv() == CallingConv::Fast34.6k
) {
2785
310
    if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2786
296
      return false;
2787
310
  }
2788
34.6k
2789
34.3k
  
if (34.3k
State.getCallingConv() == CallingConv::HiPE34.3k
) {
2790
30
    if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2791
30
      return false;
2792
30
  }
2793
34.3k
2794
34.3k
  
if (34.3k
State.getCallingConv() == CallingConv::X86_VectorCall34.3k
) {
2795
80
    if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2796
76
      return false;
2797
80
  }
2798
34.3k
2799
34.2k
  
if (34.2k
State.getCallingConv() == CallingConv::X86_RegCall34.2k
) {
2800
178
    if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2801
178
      return false;
2802
178
  }
2803
34.2k
2804
34.0k
  
if (34.0k
!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)34.0k
)
2805
33.4k
    return false;
2806
34.0k
2807
591
  return true;  // CC didn't match.
2808
34.6k
}
X86FastISel.cpp:RetCC_X86_32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2782
1.35k
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
2783
1.35k
2784
1.35k
  if (
State.getCallingConv() == CallingConv::Fast1.35k
) {
2785
1
    if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2786
1
      return false;
2787
1
  }
2788
1.35k
2789
1.35k
  
if (1.35k
State.getCallingConv() == CallingConv::HiPE1.35k
) {
2790
0
    if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2791
0
      return false;
2792
0
  }
2793
1.35k
2794
1.35k
  
if (1.35k
State.getCallingConv() == CallingConv::X86_VectorCall1.35k
) {
2795
0
    if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2796
0
      return false;
2797
0
  }
2798
1.35k
2799
1.35k
  
if (1.35k
State.getCallingConv() == CallingConv::X86_RegCall1.35k
) {
2800
0
    if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2801
0
      return false;
2802
0
  }
2803
1.35k
2804
1.35k
  
if (1.35k
!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)1.35k
)
2805
1.35k
    return false;
2806
1.35k
2807
0
  return true;  // CC didn't match.
2808
1.35k
}
X86CallLowering.cpp:RetCC_X86_32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2782
72
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
2783
72
2784
72
  if (
State.getCallingConv() == CallingConv::Fast72
) {
2785
0
    if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2786
0
      return false;
2787
0
  }
2788
72
2789
72
  
if (72
State.getCallingConv() == CallingConv::HiPE72
) {
2790
0
    if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2791
0
      return false;
2792
0
  }
2793
72
2794
72
  
if (72
State.getCallingConv() == CallingConv::X86_VectorCall72
) {
2795
0
    if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2796
0
      return false;
2797
0
  }
2798
72
2799
72
  
if (72
State.getCallingConv() == CallingConv::X86_RegCall72
) {
2800
0
    if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2801
0
      return false;
2802
0
  }
2803
72
2804
72
  
if (72
!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)72
)
2805
72
    return false;
2806
72
2807
0
  return true;  // CC didn't match.
2808
72
}
2809
2810
2811
static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
2812
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
2813
35.4k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2814
35.4k
2815
35.4k
  if (
ArgFlags.isInReg()35.4k
) {
2816
24
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()24
) {
2817
8
      if (LocVT == MVT::f32 ||
2818
8
          
LocVT == MVT::f644
) {
2819
8
        static const MCPhysReg RegList1[] = {
2820
8
          X86::XMM0, X86::XMM1, X86::XMM2
2821
8
        };
2822
8
        if (unsigned 
Reg8
= State.AllocateReg(RegList1)) {
2823
8
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2824
8
          return false;
2825
8
        }
2826
8
      }
2827
8
    }
2828
24
  }
2829
35.4k
2830
35.4k
  
if (35.4k
LocVT == MVT::f32 ||
2831
35.4k
      
LocVT == MVT::f6434.5k
) {
2832
1.91k
    static const MCPhysReg RegList2[] = {
2833
1.91k
      X86::FP0, X86::FP1
2834
1.91k
    };
2835
1.91k
    if (unsigned 
Reg1.91k
= State.AllocateReg(RegList2)) {
2836
1.82k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2837
1.82k
      return false;
2838
1.82k
    }
2839
1.91k
  }
2840
35.4k
2841
33.6k
  
if (33.6k
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)33.6k
)
2842
33.0k
    return false;
2843
33.6k
2844
591
  return true;  // CC didn't match.
2845
35.4k
}
X86CallLowering.cpp:RetCC_X86_32_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2813
72
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2814
72
2815
72
  if (
ArgFlags.isInReg()72
) {
2816
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()0
) {
2817
0
      if (LocVT == MVT::f32 ||
2818
0
          
LocVT == MVT::f640
) {
2819
0
        static const MCPhysReg RegList1[] = {
2820
0
          X86::XMM0, X86::XMM1, X86::XMM2
2821
0
        };
2822
0
        if (unsigned 
Reg0
= State.AllocateReg(RegList1)) {
2823
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2824
0
          return false;
2825
0
        }
2826
0
      }
2827
0
    }
2828
0
  }
2829
72
2830
72
  
if (72
LocVT == MVT::f32 ||
2831
72
      
LocVT == MVT::f6471
) {
2832
2
    static const MCPhysReg RegList2[] = {
2833
2
      X86::FP0, X86::FP1
2834
2
    };
2835
2
    if (unsigned 
Reg2
= State.AllocateReg(RegList2)) {
2836
2
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2837
2
      return false;
2838
2
    }
2839
2
  }
2840
72
2841
70
  
if (70
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)70
)
2842
70
    return false;
2843
70
2844
0
  return true;  // CC didn't match.
2845
72
}
X86FastISel.cpp:RetCC_X86_32_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2813
1.35k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2814
1.35k
2815
1.35k
  if (
ArgFlags.isInReg()1.35k
) {
2816
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()0
) {
2817
0
      if (LocVT == MVT::f32 ||
2818
0
          
LocVT == MVT::f640
) {
2819
0
        static const MCPhysReg RegList1[] = {
2820
0
          X86::XMM0, X86::XMM1, X86::XMM2
2821
0
        };
2822
0
        if (unsigned 
Reg0
= State.AllocateReg(RegList1)) {
2823
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2824
0
          return false;
2825
0
        }
2826
0
      }
2827
0
    }
2828
0
  }
2829
1.35k
2830
1.35k
  
if (1.35k
LocVT == MVT::f32 ||
2831
1.35k
      
LocVT == MVT::f641.34k
) {
2832
10
    static const MCPhysReg RegList2[] = {
2833
10
      X86::FP0, X86::FP1
2834
10
    };
2835
10
    if (unsigned 
Reg10
= State.AllocateReg(RegList2)) {
2836
10
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2837
10
      return false;
2838
10
    }
2839
10
  }
2840
1.35k
2841
1.34k
  
if (1.34k
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)1.34k
)
2842
1.34k
    return false;
2843
1.34k
2844
0
  return true;  // CC didn't match.
2845
1.35k
}
X86ISelLowering.cpp:RetCC_X86_32_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2813
34.0k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2814
34.0k
2815
34.0k
  if (
ArgFlags.isInReg()34.0k
) {
2816
24
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()24
) {
2817
8
      if (LocVT == MVT::f32 ||
2818
8
          
LocVT == MVT::f644
) {
2819
8
        static const MCPhysReg RegList1[] = {
2820
8
          X86::XMM0, X86::XMM1, X86::XMM2
2821
8
        };
2822
8
        if (unsigned 
Reg8
= State.AllocateReg(RegList1)) {
2823
8
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2824
8
          return false;
2825
8
        }
2826
8
      }
2827
8
    }
2828
24
  }
2829
34.0k
2830
34.0k
  
if (34.0k
LocVT == MVT::f32 ||
2831
34.0k
      
LocVT == MVT::f6433.1k
) {
2832
1.89k
    static const MCPhysReg RegList2[] = {
2833
1.89k
      X86::FP0, X86::FP1
2834
1.89k
    };
2835
1.89k
    if (unsigned 
Reg1.89k
= State.AllocateReg(RegList2)) {
2836
1.81k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2837
1.81k
      return false;
2838
1.81k
    }
2839
1.89k
  }
2840
34.0k
2841
32.2k
  
if (32.2k
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)32.2k
)
2842
31.6k
    return false;
2843
32.2k
2844
591
  return true;  // CC didn't match.
2845
34.0k
}
2846
2847
2848
static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
2849
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
2850
311
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
2851
311
2852
311
  if (
LocVT == MVT::f32311
) {
2853
2
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()2
) {
2854
2
      static const MCPhysReg RegList1[] = {
2855
2
        X86::XMM0, X86::XMM1, X86::XMM2
2856
2
      };
2857
2
      if (unsigned 
Reg2
= State.AllocateReg(RegList1)) {
2858
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2859
2
        return false;
2860
2
      }
2861
2
    }
2862
2
  }
2863
311
2864
309
  
if (309
LocVT == MVT::f64309
) {
2865
17
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()17
) {
2866
9
      static const MCPhysReg RegList2[] = {
2867
9
        X86::XMM0, X86::XMM1, X86::XMM2
2868
9
      };
2869
9
      if (unsigned 
Reg9
= State.AllocateReg(RegList2)) {
2870
9
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2871
9
        return false;
2872
9
      }
2873
9
    }
2874
17
  }
2875
309
2876
300
  
if (300
LocVT == MVT::i8300
) {
2877
21
    static const MCPhysReg RegList3[] = {
2878
21
      X86::AL, X86::DL, X86::CL
2879
21
    };
2880
21
    if (unsigned 
Reg21
= State.AllocateReg(RegList3)) {
2881
21
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2882
21
      return false;
2883
21
    }
2884
21
  }
2885
300
2886
279
  
if (279
LocVT == MVT::i16279
) {
2887
0
    static const MCPhysReg RegList4[] = {
2888
0
      X86::AX, X86::DX, X86::CX
2889
0
    };
2890
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList4)) {
2891
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2892
0
      return false;
2893
0
    }
2894
0
  }
2895
279
2896
279
  
if (279
LocVT == MVT::i32279
) {
2897
266
    static const MCPhysReg RegList5[] = {
2898
266
      X86::EAX, X86::EDX, X86::ECX
2899
266
    };
2900
266
    if (unsigned 
Reg266
= State.AllocateReg(RegList5)) {
2901
261
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2902
261
      return false;
2903
261
    }
2904
266
  }
2905
279
2906
18
  
if (18
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)18
)
2907
4
    return false;
2908
18
2909
14
  return true;  // CC didn't match.
2910
311
}
X86ISelLowering.cpp:RetCC_X86_32_Fast(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2850
310
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
2851
310
2852
310
  if (
LocVT == MVT::f32310
) {
2853
2
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()2
) {
2854
2
      static const MCPhysReg RegList1[] = {
2855
2
        X86::XMM0, X86::XMM1, X86::XMM2
2856
2
      };
2857
2
      if (unsigned 
Reg2
= State.AllocateReg(RegList1)) {
2858
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2859
2
        return false;
2860
2
      }
2861
2
    }
2862
2
  }
2863
310
2864
308
  
if (308
LocVT == MVT::f64308
) {
2865
17
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()17
) {
2866
9
      static const MCPhysReg RegList2[] = {
2867
9
        X86::XMM0, X86::XMM1, X86::XMM2
2868
9
      };
2869
9
      if (unsigned 
Reg9
= State.AllocateReg(RegList2)) {
2870
9
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2871
9
        return false;
2872
9
      }
2873
9
    }
2874
17
  }
2875
308
2876
299
  
if (299
LocVT == MVT::i8299
) {
2877
21
    static const MCPhysReg RegList3[] = {
2878
21
      X86::AL, X86::DL, X86::CL
2879
21
    };
2880
21
    if (unsigned 
Reg21
= State.AllocateReg(RegList3)) {
2881
21
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2882
21
      return false;
2883
21
    }
2884
21
  }
2885
299
2886
278
  
if (278
LocVT == MVT::i16278
) {
2887
0
    static const MCPhysReg RegList4[] = {
2888
0
      X86::AX, X86::DX, X86::CX
2889
0
    };
2890
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList4)) {
2891
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2892
0
      return false;
2893
0
    }
2894
0
  }
2895
278
2896
278
  
if (278
LocVT == MVT::i32278
) {
2897
265
    static const MCPhysReg RegList5[] = {
2898
265
      X86::EAX, X86::EDX, X86::ECX
2899
265
    };
2900
265
    if (unsigned 
Reg265
= State.AllocateReg(RegList5)) {
2901
260
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2902
260
      return false;
2903
260
    }
2904
265
  }
2905
278
2906
18
  
if (18
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)18
)
2907
4
    return false;
2908
18
2909
14
  return true;  // CC didn't match.
2910
310
}
X86FastISel.cpp:RetCC_X86_32_Fast(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2850
1
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
2851
1
2852
1
  if (
LocVT == MVT::f321
) {
2853
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()0
) {
2854
0
      static const MCPhysReg RegList1[] = {
2855
0
        X86::XMM0, X86::XMM1, X86::XMM2
2856
0
      };
2857
0
      if (unsigned 
Reg0
= State.AllocateReg(RegList1)) {
2858
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2859
0
        return false;
2860
0
      }
2861
0
    }
2862
0
  }
2863
1
2864
1
  
if (1
LocVT == MVT::f641
) {
2865
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()0
) {
2866
0
      static const MCPhysReg RegList2[] = {
2867
0
        X86::XMM0, X86::XMM1, X86::XMM2
2868
0
      };
2869
0
      if (unsigned 
Reg0
= State.AllocateReg(RegList2)) {
2870
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2871
0
        return false;
2872
0
      }
2873
0
    }
2874
0
  }
2875
1
2876
1
  
if (1
LocVT == MVT::i81
) {
2877
0
    static const MCPhysReg RegList3[] = {
2878
0
      X86::AL, X86::DL, X86::CL
2879
0
    };
2880
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList3)) {
2881
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2882
0
      return false;
2883
0
    }
2884
0
  }
2885
1
2886
1
  
if (1
LocVT == MVT::i161
) {
2887
0
    static const MCPhysReg RegList4[] = {
2888
0
      X86::AX, X86::DX, X86::CX
2889
0
    };
2890
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList4)) {
2891
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2892
0
      return false;
2893
0
    }
2894
0
  }
2895
1
2896
1
  
if (1
LocVT == MVT::i321
) {
2897
1
    static const MCPhysReg RegList5[] = {
2898
1
      X86::EAX, X86::EDX, X86::ECX
2899
1
    };
2900
1
    if (unsigned 
Reg1
= State.AllocateReg(RegList5)) {
2901
1
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2902
1
      return false;
2903
1
    }
2904
1
  }
2905
1
2906
0
  
if (0
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)0
)
2907
0
    return false;
2908
0
2909
0
  return true;  // CC didn't match.
2910
1
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_32_Fast(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
2911
2912
2913
static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
2914
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
2915
30
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
2916
30
2917
30
  if (LocVT == MVT::i8 ||
2918
30
      
LocVT == MVT::i1630
) {
2919
0
    LocVT = MVT::i32;
2920
0
    if (ArgFlags.isSExt())
2921
0
        LocInfo = CCValAssign::SExt;
2922
0
    else 
if (0
ArgFlags.isZExt()0
)
2923
0
        LocInfo = CCValAssign::ZExt;
2924
0
    else
2925
0
        LocInfo = CCValAssign::AExt;
2926
0
  }
2927
30
2928
30
  if (
LocVT == MVT::i3230
) {
2929
30
    static const MCPhysReg RegList1[] = {
2930
30
      X86::ESI, X86::EBP, X86::EAX, X86::EDX
2931
30
    };
2932
30
    if (unsigned 
Reg30
= State.AllocateReg(RegList1)) {
2933
30
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2934
30
      return false;
2935
30
    }
2936
30
  }
2937
30
2938
0
  return true;  // CC didn't match.
2939
30
}
X86ISelLowering.cpp:RetCC_X86_32_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2915
30
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
2916
30
2917
30
  if (LocVT == MVT::i8 ||
2918
30
      
LocVT == MVT::i1630
) {
2919
0
    LocVT = MVT::i32;
2920
0
    if (ArgFlags.isSExt())
2921
0
        LocInfo = CCValAssign::SExt;
2922
0
    else 
if (0
ArgFlags.isZExt()0
)
2923
0
        LocInfo = CCValAssign::ZExt;
2924
0
    else
2925
0
        LocInfo = CCValAssign::AExt;
2926
0
  }
2927
30
2928
30
  if (
LocVT == MVT::i3230
) {
2929
30
    static const MCPhysReg RegList1[] = {
2930
30
      X86::ESI, X86::EBP, X86::EAX, X86::EDX
2931
30
    };
2932
30
    if (unsigned 
Reg30
= State.AllocateReg(RegList1)) {
2933
30
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2934
30
      return false;
2935
30
    }
2936
30
  }
2937
30
2938
0
  return true;  // CC didn't match.
2939
30
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_32_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:RetCC_X86_32_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
2940
2941
2942
static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
2943
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
2944
178
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2945
178
2946
178
  if (LocVT == MVT::i1 ||
2947
178
      LocVT == MVT::v1i1 ||
2948
178
      
LocVT == MVT::v8i1178
) {
2949
4
    LocVT = MVT::i8;
2950
4
    if (ArgFlags.isSExt())
2951
0
        LocInfo = CCValAssign::SExt;
2952
4
    else 
if (4
ArgFlags.isZExt()4
)
2953
0
        LocInfo = CCValAssign::ZExt;
2954
4
    else
2955
4
        LocInfo = CCValAssign::AExt;
2956
4
  }
2957
178
2958
178
  if (
LocVT == MVT::v16i1178
) {
2959
4
    LocVT = MVT::i16;
2960
4
    if (ArgFlags.isSExt())
2961
0
        LocInfo = CCValAssign::SExt;
2962
4
    else 
if (4
ArgFlags.isZExt()4
)
2963
0
        LocInfo = CCValAssign::ZExt;
2964
4
    else
2965
4
        LocInfo = CCValAssign::AExt;
2966
4
  }
2967
178
2968
178
  if (
LocVT == MVT::v32i1178
) {
2969
4
    LocVT = MVT::i32;
2970
4
    if (ArgFlags.isSExt())
2971
0
        LocInfo = CCValAssign::SExt;
2972
4
    else 
if (4
ArgFlags.isZExt()4
)
2973
0
        LocInfo = CCValAssign::ZExt;
2974
4
    else
2975
4
        LocInfo = CCValAssign::AExt;
2976
4
  }
2977
178
2978
178
  if (
LocVT == MVT::i8178
) {
2979
28
    static const MCPhysReg RegList1[] = {
2980
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
2981
28
    };
2982
28
    if (unsigned 
Reg28
= State.AllocateReg(RegList1)) {
2983
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2984
28
      return false;
2985
28
    }
2986
28
  }
2987
178
2988
150
  
if (150
LocVT == MVT::i16150
) {
2989
14
    static const MCPhysReg RegList2[] = {
2990
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
2991
14
    };
2992
14
    if (unsigned 
Reg14
= State.AllocateReg(RegList2)) {
2993
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2994
14
      return false;
2995
14
    }
2996
14
  }
2997
150
2998
136
  
if (136
LocVT == MVT::i32136
) {
2999
60
    static const MCPhysReg RegList3[] = {
3000
60
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3001
60
    };
3002
60
    if (unsigned 
Reg60
= State.AllocateReg(RegList3)) {
3003
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3004
60
      return false;
3005
60
    }
3006
60
  }
3007
136
3008
76
  
if (76
LocVT == MVT::i6476
) {
3009
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::RAX)) {
3010
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3011
0
      return false;
3012
0
    }
3013
0
  }
3014
76
3015
76
  
if (76
LocVT == MVT::v64i176
) {
3016
4
    LocVT = MVT::i64;
3017
4
    if (ArgFlags.isSExt())
3018
0
        LocInfo = CCValAssign::SExt;
3019
4
    else 
if (4
ArgFlags.isZExt()4
)
3020
0
        LocInfo = CCValAssign::ZExt;
3021
4
    else
3022
4
        LocInfo = CCValAssign::AExt;
3023
4
  }
3024
76
3025
76
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()76
) {
3026
0
    if (
LocVT == MVT::i640
) {
3027
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::RAX)) {
3028
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3029
0
        return false;
3030
0
      }
3031
0
    }
3032
0
  }
3033
76
3034
76
  
if (76
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()76
) {
3035
76
    if (
LocVT == MVT::i6476
) {
3036
4
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3037
4
            return false;
3038
4
    }
3039
76
  }
3040
76
3041
72
  
if (72
LocVT == MVT::f8072
) {
3042
6
    static const MCPhysReg RegList4[] = {
3043
6
      X86::FP0, X86::FP1
3044
6
    };
3045
6
    if (unsigned 
Reg6
= State.AllocateReg(RegList4)) {
3046
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3047
6
      return false;
3048
6
    }
3049
6
  }
3050
72
3051
66
  
if (66
LocVT == MVT::f32 ||
3052
58
      LocVT == MVT::f64 ||
3053
66
      
LocVT == MVT::f12850
) {
3054
16
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()16
) {
3055
16
      static const MCPhysReg RegList5[] = {
3056
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3057
16
      };
3058
16
      if (unsigned 
Reg16
= State.AllocateReg(RegList5)) {
3059
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3060
16
        return false;
3061
16
      }
3062
16
    }
3063
16
  }
3064
66
3065
50
  
if (50
LocVT == MVT::v16i8 ||
3066
50
      LocVT == MVT::v8i16 ||
3067
50
      LocVT == MVT::v4i32 ||
3068
44
      LocVT == MVT::v2i64 ||
3069
44
      LocVT == MVT::v4f32 ||
3070
50
      
LocVT == MVT::v2f6420
) {
3071
30
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()30
) {
3072
30
      static const MCPhysReg RegList6[] = {
3073
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3074
30
      };
3075
30
      if (unsigned 
Reg30
= State.AllocateReg(RegList6)) {
3076
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3077
30
        return false;
3078
30
      }
3079
30
    }
3080
30
  }
3081
50
3082
20
  
if (20
LocVT == MVT::v32i8 ||
3083
20
      LocVT == MVT::v16i16 ||
3084
20
      LocVT == MVT::v8i32 ||
3085
14
      LocVT == MVT::v4i64 ||
3086
14
      LocVT == MVT::v8f32 ||
3087
20
      
LocVT == MVT::v4f6414
) {
3088
6
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()6
) {
3089
6
      static const MCPhysReg RegList7[] = {
3090
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3091
6
      };
3092
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList7)) {
3093
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3094
6
        return false;
3095
6
      }
3096
6
    }
3097
6
  }
3098
20
3099
14
  
if (14
LocVT == MVT::v64i8 ||
3100
14
      LocVT == MVT::v32i16 ||
3101
14
      LocVT == MVT::v16i32 ||
3102
8
      LocVT == MVT::v8i64 ||
3103
8
      LocVT == MVT::v16f32 ||
3104
14
      
LocVT == MVT::v8f640
) {
3105
14
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()14
) {
3106
14
      static const MCPhysReg RegList8[] = {
3107
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3108
14
      };
3109
14
      if (unsigned 
Reg14
= State.AllocateReg(RegList8)) {
3110
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3111
14
        return false;
3112
14
      }
3113
14
    }
3114
14
  }
3115
14
3116
0
  return true;  // CC didn't match.
3117
178
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_32_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:RetCC_X86_32_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:RetCC_X86_32_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
2944
178
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2945
178
2946
178
  if (LocVT == MVT::i1 ||
2947
178
      LocVT == MVT::v1i1 ||
2948
178
      
LocVT == MVT::v8i1178
) {
2949
4
    LocVT = MVT::i8;
2950
4
    if (ArgFlags.isSExt())
2951
0
        LocInfo = CCValAssign::SExt;
2952
4
    else 
if (4
ArgFlags.isZExt()4
)
2953
0
        LocInfo = CCValAssign::ZExt;
2954
4
    else
2955
4
        LocInfo = CCValAssign::AExt;
2956
4
  }
2957
178
2958
178
  if (
LocVT == MVT::v16i1178
) {
2959
4
    LocVT = MVT::i16;
2960
4
    if (ArgFlags.isSExt())
2961
0
        LocInfo = CCValAssign::SExt;
2962
4
    else 
if (4
ArgFlags.isZExt()4
)
2963
0
        LocInfo = CCValAssign::ZExt;
2964
4
    else
2965
4
        LocInfo = CCValAssign::AExt;
2966
4
  }
2967
178
2968
178
  if (
LocVT == MVT::v32i1178
) {
2969
4
    LocVT = MVT::i32;
2970
4
    if (ArgFlags.isSExt())
2971
0
        LocInfo = CCValAssign::SExt;
2972
4
    else 
if (4
ArgFlags.isZExt()4
)
2973
0
        LocInfo = CCValAssign::ZExt;
2974
4
    else
2975
4
        LocInfo = CCValAssign::AExt;
2976
4
  }
2977
178
2978
178
  if (
LocVT == MVT::i8178
) {
2979
28
    static const MCPhysReg RegList1[] = {
2980
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
2981
28
    };
2982
28
    if (unsigned 
Reg28
= State.AllocateReg(RegList1)) {
2983
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2984
28
      return false;
2985
28
    }
2986
28
  }
2987
178
2988
150
  
if (150
LocVT == MVT::i16150
) {
2989
14
    static const MCPhysReg RegList2[] = {
2990
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
2991
14
    };
2992
14
    if (unsigned 
Reg14
= State.AllocateReg(RegList2)) {
2993
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2994
14
      return false;
2995
14
    }
2996
14
  }
2997
150
2998
136
  
if (136
LocVT == MVT::i32136
) {
2999
60
    static const MCPhysReg RegList3[] = {
3000
60
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3001
60
    };
3002
60
    if (unsigned 
Reg60
= State.AllocateReg(RegList3)) {
3003
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3004
60
      return false;
3005
60
    }
3006
60
  }
3007
136
3008
76
  
if (76
LocVT == MVT::i6476
) {
3009
0
    if (unsigned 
Reg0
= State.AllocateReg(X86::RAX)) {
3010
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3011
0
      return false;
3012
0
    }
3013
0
  }
3014
76
3015
76
  
if (76
LocVT == MVT::v64i176
) {
3016
4
    LocVT = MVT::i64;
3017
4
    if (ArgFlags.isSExt())
3018
0
        LocInfo = CCValAssign::SExt;
3019
4
    else 
if (4
ArgFlags.isZExt()4
)
3020
0
        LocInfo = CCValAssign::ZExt;
3021
4
    else
3022
4
        LocInfo = CCValAssign::AExt;
3023
4
  }
3024
76
3025
76
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()76
) {
3026
0
    if (
LocVT == MVT::i640
) {
3027
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::RAX)) {
3028
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3029
0
        return false;
3030
0
      }
3031
0
    }
3032
0
  }
3033
76
3034
76
  
if (76
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()76
) {
3035
76
    if (
LocVT == MVT::i6476
) {
3036
4
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3037
4
            return false;
3038
4
    }
3039
76
  }
3040
76
3041
72
  
if (72
LocVT == MVT::f8072
) {
3042
6
    static const MCPhysReg RegList4[] = {
3043
6
      X86::FP0, X86::FP1
3044
6
    };
3045
6
    if (unsigned 
Reg6
= State.AllocateReg(RegList4)) {
3046
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3047
6
      return false;
3048
6
    }
3049
6
  }
3050
72
3051
66
  
if (66
LocVT == MVT::f32 ||
3052
58
      LocVT == MVT::f64 ||
3053
66
      
LocVT == MVT::f12850
) {
3054
16
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()16
) {
3055
16
      static const MCPhysReg RegList5[] = {
3056
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3057
16
      };
3058
16
      if (unsigned 
Reg16
= State.AllocateReg(RegList5)) {
3059
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3060
16
        return false;
3061
16
      }
3062
16
    }
3063
16
  }
3064
66
3065
50
  
if (50
LocVT == MVT::v16i8 ||
3066
50
      LocVT == MVT::v8i16 ||
3067
50
      LocVT == MVT::v4i32 ||
3068
44
      LocVT == MVT::v2i64 ||
3069
44
      LocVT == MVT::v4f32 ||
3070
50
      
LocVT == MVT::v2f6420
) {
3071
30
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()30
) {
3072
30
      static const MCPhysReg RegList6[] = {
3073
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3074
30
      };
3075
30
      if (unsigned 
Reg30
= State.AllocateReg(RegList6)) {
3076
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3077
30
        return false;
3078
30
      }
3079
30
    }
3080
30
  }
3081
50
3082
20
  
if (20
LocVT == MVT::v32i8 ||
3083
20
      LocVT == MVT::v16i16 ||
3084
20
      LocVT == MVT::v8i32 ||
3085
14
      LocVT == MVT::v4i64 ||
3086
14
      LocVT == MVT::v8f32 ||
3087
20
      
LocVT == MVT::v4f6414
) {
3088
6
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()6
) {
3089
6
      static const MCPhysReg RegList7[] = {
3090
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3091
6
      };
3092
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList7)) {
3093
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3094
6
        return false;
3095
6
      }
3096
6
    }
3097
6
  }
3098
20
3099
14
  
if (14
LocVT == MVT::v64i8 ||
3100
14
      LocVT == MVT::v32i16 ||
3101
14
      LocVT == MVT::v16i32 ||
3102
8
      LocVT == MVT::v8i64 ||
3103
8
      LocVT == MVT::v16f32 ||
3104
14
      
LocVT == MVT::v8f640
) {
3105
14
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()14
) {
3106
14
      static const MCPhysReg RegList8[] = {
3107
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3108
14
      };
3109
14
      if (unsigned 
Reg14
= State.AllocateReg(RegList8)) {
3110
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3111
14
        return false;
3112
14
      }
3113
14
    }
3114
14
  }
3115
14
3116
0
  return true;  // CC didn't match.
3117
178
}
3118
3119
3120
static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
3121
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
3122
80
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3123
80
3124
80
  if (LocVT == MVT::f32 ||
3125
80
      LocVT == MVT::f64 ||
3126
80
      
LocVT == MVT::f12852
) {
3127
28
    static const MCPhysReg RegList1[] = {
3128
28
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3129
28
    };
3130
28
    if (unsigned 
Reg28
= State.AllocateReg(RegList1)) {
3131
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3132
24
      return false;
3133
24
    }
3134
28
  }
3135
80
3136
56
  
if (56
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)56
)
3137
52
    return false;
3138
56
3139
4
  return true;  // CC didn't match.
3140
80
}
Unexecuted instantiation: X86FastISel.cpp:RetCC_X86_32_VectorCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_32_VectorCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:RetCC_X86_32_VectorCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3122
80
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3123
80
3124
80
  if (LocVT == MVT::f32 ||
3125
80
      LocVT == MVT::f64 ||
3126
80
      
LocVT == MVT::f12852
) {
3127
28
    static const MCPhysReg RegList1[] = {
3128
28
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3129
28
    };
3130
28
    if (unsigned 
Reg28
= State.AllocateReg(RegList1)) {
3131
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3132
24
      return false;
3133
24
    }
3134
28
  }
3135
80
3136
56
  
if (56
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)56
)
3137
52
    return false;
3138
56
3139
4
  return true;  // CC didn't match.
3140
80
}
3141
3142
3143
static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
3144
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
3145
124k
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
3146
124k
3147
124k
  if (
State.getCallingConv() == CallingConv::HiPE124k
) {
3148
28
    if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3149
28
      return false;
3150
28
  }
3151
124k
3152
124k
  
if (124k
State.getCallingConv() == CallingConv::WebKit_JS124k
) {
3153
20
    if (!RetCC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3154
20
      return false;
3155
20
  }
3156
124k
3157
124k
  
if (124k
State.getCallingConv() == CallingConv::AnyReg124k
) {
3158
0
    if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3159
0
      return false;
3160
0
  }
3161
124k
3162
124k
  
if (124k
State.getCallingConv() == CallingConv::Swift124k
) {
3163
409
    if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3164
404
      return false;
3165
409
  }
3166
124k
3167
124k
  
if (124k
State.getCallingConv() == CallingConv::Win64124k
) {
3168
36
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3169
36
      return false;
3170
36
  }
3171
124k
3172
124k
  
if (124k
State.getCallingConv() == CallingConv::X86_64_SysV124k
) {
3173
8
    if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3174
8
      return false;
3175
8
  }
3176
124k
3177
124k
  
if (124k
State.getCallingConv() == CallingConv::X86_VectorCall124k
) {
3178
60
    if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3179
58
      return false;
3180
60
  }
3181
124k
3182
124k
  
if (124k
State.getCallingConv() == CallingConv::HHVM124k
) {
3183
70
    if (!RetCC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3184
70
      return false;
3185
70
  }
3186
124k
3187
124k
  
if (124k
State.getCallingConv() == CallingConv::X86_RegCall124k
) {
3188
324
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()324
) {
3189
166
      if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3190
166
        return false;
3191
166
    }
3192
324
  }
3193
124k
3194
124k
  
if (124k
State.getCallingConv() == CallingConv::X86_RegCall124k
) {
3195
158
    if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3196
158
      return false;
3197
158
  }
3198
124k
3199
123k
  
if (123k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()123k
) {
3200
1.78k
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3201
1.78k
      return false;
3202
1.78k
  }
3203
123k
3204
122k
  
if (122k
!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)122k
)
3205
122k
    return false;
3206
122k
3207
135
  return true;  // CC didn't match.
3208
124k
}
X86ISelLowering.cpp:RetCC_X86_64(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3145
121k
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
3146
121k
3147
121k
  if (
State.getCallingConv() == CallingConv::HiPE121k
) {
3148
28
    if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3149
28
      return false;
3150
28
  }
3151
121k
3152
121k
  
if (121k
State.getCallingConv() == CallingConv::WebKit_JS121k
) {
3153
17
    if (!RetCC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3154
17
      return false;
3155
17
  }
3156
121k
3157
121k
  
if (121k
State.getCallingConv() == CallingConv::AnyReg121k
) {
3158
0
    if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3159
0
      return false;
3160
0
  }
3161
121k
3162
121k
  
if (121k
State.getCallingConv() == CallingConv::Swift121k
) {
3163
395
    if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3164
390
      return false;
3165
395
  }
3166
121k
3167
121k
  
if (121k
State.getCallingConv() == CallingConv::Win64121k
) {
3168
36
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3169
36
      return false;
3170
36
  }
3171
121k
3172
121k
  
if (121k
State.getCallingConv() == CallingConv::X86_64_SysV121k
) {
3173
8
    if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3174
8
      return false;
3175
8
  }
3176
121k
3177
121k
  
if (121k
State.getCallingConv() == CallingConv::X86_VectorCall121k
) {
3178
60
    if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3179
58
      return false;
3180
60
  }
3181
121k
3182
121k
  
if (121k
State.getCallingConv() == CallingConv::HHVM121k
) {
3183
70
    if (!RetCC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3184
70
      return false;
3185
70
  }
3186
121k
3187
120k
  
if (120k
State.getCallingConv() == CallingConv::X86_RegCall120k
) {
3188
324
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()324
) {
3189
166
      if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3190
166
        return false;
3191
166
    }
3192
324
  }
3193
120k
3194
120k
  
if (120k
State.getCallingConv() == CallingConv::X86_RegCall120k
) {
3195
158
    if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3196
158
      return false;
3197
158
  }
3198
120k
3199
120k
  
if (120k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()120k
) {
3200
1.76k
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3201
1.76k
      return false;
3202
1.76k
  }
3203
120k
3204
118k
  
if (118k
!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)118k
)
3205
118k
    return false;
3206
118k
3207
135
  return true;  // CC didn't match.
3208
121k
}
X86CallLowering.cpp:RetCC_X86_64(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3145
289
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
3146
289
3147
289
  if (
State.getCallingConv() == CallingConv::HiPE289
) {
3148
0
    if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3149
0
      return false;
3150
0
  }
3151
289
3152
289
  
if (289
State.getCallingConv() == CallingConv::WebKit_JS289
) {
3153
0
    if (!RetCC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3154
0
      return false;
3155
0
  }
3156
289
3157
289
  
if (289
State.getCallingConv() == CallingConv::AnyReg289
) {
3158
0
    if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3159
0
      return false;
3160
0
  }
3161
289
3162
289
  
if (289
State.getCallingConv() == CallingConv::Swift289
) {
3163
0
    if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3164
0
      return false;
3165
0
  }
3166
289
3167
289
  
if (289
State.getCallingConv() == CallingConv::Win64289
) {
3168
0
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3169
0
      return false;
3170
0
  }
3171
289
3172
289
  
if (289
State.getCallingConv() == CallingConv::X86_64_SysV289
) {
3173
0
    if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3174
0
      return false;
3175
0
  }
3176
289
3177
289
  
if (289
State.getCallingConv() == CallingConv::X86_VectorCall289
) {
3178
0
    if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3179
0
      return false;
3180
0
  }
3181
289
3182
289
  
if (289
State.getCallingConv() == CallingConv::HHVM289
) {
3183
0
    if (!RetCC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3184
0
      return false;
3185
0
  }
3186
289
3187
289
  
if (289
State.getCallingConv() == CallingConv::X86_RegCall289
) {
3188
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()0
) {
3189
0
      if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3190
0
        return false;
3191
0
    }
3192
0
  }
3193
289
3194
289
  
if (289
State.getCallingConv() == CallingConv::X86_RegCall289
) {
3195
0
    if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3196
0
      return false;
3197
0
  }
3198
289
3199
289
  
if (289
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()289
) {
3200
0
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3201
0
      return false;
3202
0
  }
3203
289
3204
289
  
if (289
!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)289
)
3205
289
    return false;
3206
289
3207
0
  return true;  // CC didn't match.
3208
289
}
X86FastISel.cpp:RetCC_X86_64(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3145
3.02k
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
3146
3.02k
3147
3.02k
  if (
State.getCallingConv() == CallingConv::HiPE3.02k
) {
3148
0
    if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3149
0
      return false;
3150
0
  }
3151
3.02k
3152
3.02k
  
if (3.02k
State.getCallingConv() == CallingConv::WebKit_JS3.02k
) {
3153
3
    if (!RetCC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3154
3
      return false;
3155
3
  }
3156
3.02k
3157
3.02k
  
if (3.02k
State.getCallingConv() == CallingConv::AnyReg3.02k
) {
3158
0
    if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3159
0
      return false;
3160
0
  }
3161
3.02k
3162
3.02k
  
if (3.02k
State.getCallingConv() == CallingConv::Swift3.02k
) {
3163
14
    if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3164
14
      return false;
3165
14
  }
3166
3.02k
3167
3.01k
  
if (3.01k
State.getCallingConv() == CallingConv::Win643.01k
) {
3168
0
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3169
0
      return false;
3170
0
  }
3171
3.01k
3172
3.01k
  
if (3.01k
State.getCallingConv() == CallingConv::X86_64_SysV3.01k
) {
3173
0
    if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3174
0
      return false;
3175
0
  }
3176
3.01k
3177
3.01k
  
if (3.01k
State.getCallingConv() == CallingConv::X86_VectorCall3.01k
) {
3178
0
    if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3179
0
      return false;
3180
0
  }
3181
3.01k
3182
3.01k
  
if (3.01k
State.getCallingConv() == CallingConv::HHVM3.01k
) {
3183
0
    if (!RetCC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3184
0
      return false;
3185
0
  }
3186
3.01k
3187
3.01k
  
if (3.01k
State.getCallingConv() == CallingConv::X86_RegCall3.01k
) {
3188
0
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()0
) {
3189
0
      if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3190
0
        return false;
3191
0
    }
3192
0
  }
3193
3.01k
3194
3.01k
  
if (3.01k
State.getCallingConv() == CallingConv::X86_RegCall3.01k
) {
3195
0
    if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3196
0
      return false;
3197
0
  }
3198
3.01k
3199
3.01k
  
if (3.01k
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()3.01k
) {
3200
20
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3201
20
      return false;
3202
20
  }
3203
3.01k
3204
2.99k
  
if (2.99k
!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)2.99k
)
3205
2.99k
    return false;
3206
2.99k
3207
0
  return true;  // CC didn't match.
3208
3.02k
}
3209
3210
3211
static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
3212
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
3213
0
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
3214
0
3215
0
  if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3216
0
    return false;
3217
0
3218
0
  return true;  // CC didn't match.
3219
0
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_64_AnyReg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:RetCC_X86_64_AnyReg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86ISelLowering.cpp:RetCC_X86_64_AnyReg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
3220
3221
3222
static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
3223
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
3224
124k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
3225
124k
3226
124k
  if (
LocVT == MVT::f32124k
) {
3227
2.11k
    static const MCPhysReg RegList1[] = {
3228
2.11k
      X86::XMM0, X86::XMM1
3229
2.11k
    };
3230
2.11k
    if (unsigned 
Reg2.11k
= State.AllocateReg(RegList1)) {
3231
2.11k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3232
2.11k
      return false;
3233
2.11k
    }
3234
2.11k
  }
3235
124k
3236
121k
  
if (121k
LocVT == MVT::f64121k
) {
3237
2.43k
    static const MCPhysReg RegList2[] = {
3238
2.43k
      X86::XMM0, X86::XMM1
3239
2.43k
    };
3240
2.43k
    if (unsigned 
Reg2.43k
= State.AllocateReg(RegList2)) {
3241
2.42k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3242
2.42k
      return false;
3243
2.42k
    }
3244
2.43k
  }
3245
121k
3246
119k
  
if (119k
LocVT == MVT::f128119k
) {
3247
208
    static const MCPhysReg RegList3[] = {
3248
208
      X86::XMM0, X86::XMM1
3249
208
    };
3250
208
    if (unsigned 
Reg208
= State.AllocateReg(RegList3)) {
3251
208
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3252
208
      return false;
3253
208
    }
3254
208
  }
3255
119k
3256
119k
  
if (119k
LocVT == MVT::x86mmx119k
) {
3257
204
    static const MCPhysReg RegList4[] = {
3258
204
      X86::XMM0, X86::XMM1
3259
204
    };
3260
204
    if (unsigned 
Reg204
= State.AllocateReg(RegList4)) {
3261
204
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3262
204
      return false;
3263
204
    }
3264
204
  }
3265
119k
3266
119k
  
if (119k
ArgFlags.isSwiftError()119k
) {
3267
26
    if (
LocVT == MVT::i6426
) {
3268
26
      if (unsigned 
Reg26
= State.AllocateReg(X86::R12)) {
3269
26
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3270
26
        return false;
3271
26
      }
3272
26
    }
3273
26
  }
3274
119k
3275
119k
  
if (119k
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)119k
)
3276
118k
    return false;
3277
119k
3278
136
  return true;  // CC didn't match.
3279
124k
}
X86ISelLowering.cpp:RetCC_X86_64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3224
120k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
3225
120k
3226
120k
  if (
LocVT == MVT::f32120k
) {
3227
1.99k
    static const MCPhysReg RegList1[] = {
3228
1.99k
      X86::XMM0, X86::XMM1
3229
1.99k
    };
3230
1.99k
    if (unsigned 
Reg1.99k
= State.AllocateReg(RegList1)) {
3231
1.99k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3232
1.99k
      return false;
3233
1.99k
    }
3234
1.99k
  }
3235
120k
3236
118k
  
if (118k
LocVT == MVT::f64118k
) {
3237
2.35k
    static const MCPhysReg RegList2[] = {
3238
2.35k
      X86::XMM0, X86::XMM1
3239
2.35k
    };
3240
2.35k
    if (unsigned 
Reg2.35k
= State.AllocateReg(RegList2)) {
3241
2.34k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3242
2.34k
      return false;
3243
2.34k
    }
3244
2.35k
  }
3245
118k
3246
116k
  
if (116k
LocVT == MVT::f128116k
) {
3247
208
    static const MCPhysReg RegList3[] = {
3248
208
      X86::XMM0, X86::XMM1
3249
208
    };
3250
208
    if (unsigned 
Reg208
= State.AllocateReg(RegList3)) {
3251
208
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3252
208
      return false;
3253
208
    }
3254
208
  }
3255
116k
3256
116k
  
if (116k
LocVT == MVT::x86mmx116k
) {
3257
204
    static const MCPhysReg RegList4[] = {
3258
204
      X86::XMM0, X86::XMM1
3259
204
    };
3260
204
    if (unsigned 
Reg204
= State.AllocateReg(RegList4)) {
3261
204
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3262
204
      return false;
3263
204
    }
3264
204
  }
3265
116k
3266
115k
  
if (115k
ArgFlags.isSwiftError()115k
) {
3267
26
    if (
LocVT == MVT::i6426
) {
3268
26
      if (unsigned 
Reg26
= State.AllocateReg(X86::R12)) {
3269
26
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3270
26
        return false;
3271
26
      }
3272
26
    }
3273
26
  }
3274
115k
3275
115k
  
if (115k
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)115k
)
3276
115k
    return false;
3277
115k
3278
136
  return true;  // CC didn't match.
3279
120k
}
X86CallLowering.cpp:RetCC_X86_64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3224
289
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
3225
289
3226
289
  if (
LocVT == MVT::f32289
) {
3227
22
    static const MCPhysReg RegList1[] = {
3228
22
      X86::XMM0, X86::XMM1
3229
22
    };
3230
22
    if (unsigned 
Reg22
= State.AllocateReg(RegList1)) {
3231
22
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3232
22
      return false;
3233
22
    }
3234
22
  }
3235
289
3236
267
  
if (267
LocVT == MVT::f64267
) {
3237
17
    static const MCPhysReg RegList2[] = {
3238
17
      X86::XMM0, X86::XMM1
3239
17
    };
3240
17
    if (unsigned 
Reg17
= State.AllocateReg(RegList2)) {
3241
17
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3242
17
      return false;
3243
17
    }
3244
17
  }
3245
267
3246
250
  
if (250
LocVT == MVT::f128250
) {
3247
0
    static const MCPhysReg RegList3[] = {
3248
0
      X86::XMM0, X86::XMM1
3249
0
    };
3250
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList3)) {
3251
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3252
0
      return false;
3253
0
    }
3254
0
  }
3255
250
3256
250
  
if (250
LocVT == MVT::x86mmx250
) {
3257
0
    static const MCPhysReg RegList4[] = {
3258
0
      X86::XMM0, X86::XMM1
3259
0
    };
3260
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList4)) {
3261
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3262
0
      return false;
3263
0
    }
3264
0
  }
3265
250
3266
250
  
if (250
ArgFlags.isSwiftError()250
) {
3267
0
    if (
LocVT == MVT::i640
) {
3268
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::R12)) {
3269
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3270
0
        return false;
3271
0
      }
3272
0
    }
3273
0
  }
3274
250
3275
250
  
if (250
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)250
)
3276
250
    return false;
3277
250
3278
0
  return true;  // CC didn't match.
3279
289
}
X86FastISel.cpp:RetCC_X86_64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3224
3.01k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
3225
3.01k
3226
3.01k
  if (
LocVT == MVT::f323.01k
) {
3227
92
    static const MCPhysReg RegList1[] = {
3228
92
      X86::XMM0, X86::XMM1
3229
92
    };
3230
92
    if (unsigned 
Reg92
= State.AllocateReg(RegList1)) {
3231
92
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3232
92
      return false;
3233
92
    }
3234
92
  }
3235
3.01k
3236
2.91k
  
if (2.91k
LocVT == MVT::f642.91k
) {
3237
60
    static const MCPhysReg RegList2[] = {
3238
60
      X86::XMM0, X86::XMM1
3239
60
    };
3240
60
    if (unsigned 
Reg60
= State.AllocateReg(RegList2)) {
3241
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3242
60
      return false;
3243
60
    }
3244
60
  }
3245
2.91k
3246
2.85k
  
if (2.85k
LocVT == MVT::f1282.85k
) {
3247
0
    static const MCPhysReg RegList3[] = {
3248
0
      X86::XMM0, X86::XMM1
3249
0
    };
3250
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList3)) {
3251
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3252
0
      return false;
3253
0
    }
3254
0
  }
3255
2.85k
3256
2.85k
  
if (2.85k
LocVT == MVT::x86mmx2.85k
) {
3257
0
    static const MCPhysReg RegList4[] = {
3258
0
      X86::XMM0, X86::XMM1
3259
0
    };
3260
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList4)) {
3261
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3262
0
      return false;
3263
0
    }
3264
0
  }
3265
2.85k
3266
2.85k
  
if (2.85k
ArgFlags.isSwiftError()2.85k
) {
3267
0
    if (
LocVT == MVT::i640
) {
3268
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::R12)) {
3269
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3270
0
        return false;
3271
0
      }
3272
0
    }
3273
0
  }
3274
2.85k
3275
2.85k
  
if (2.85k
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)2.85k
)
3276
2.85k
    return false;
3277
2.85k
3278
0
  return true;  // CC didn't match.
3279
3.01k
}
3280
3281
3282
static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
3283
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3284
70
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3285
70
3286
70
  if (LocVT == MVT::i8 ||
3287
70
      LocVT == MVT::i16 ||
3288
70
      
LocVT == MVT::i3270
) {
3289
0
    LocVT = MVT::i64;
3290
0
    if (ArgFlags.isSExt())
3291
0
        LocInfo = CCValAssign::SExt;
3292
0
    else 
if (0
ArgFlags.isZExt()0
)
3293
0
        LocInfo = CCValAssign::ZExt;
3294
0
    else
3295
0
        LocInfo = CCValAssign::AExt;
3296
0
  }
3297
70
3298
70
  if (
LocVT == MVT::i6470
) {
3299
70
    static const MCPhysReg RegList1[] = {
3300
70
      X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14, X86::R15
3301
70
    };
3302
70
    if (unsigned 
Reg70
= State.AllocateReg(RegList1)) {
3303
70
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3304
70
      return false;
3305
70
    }
3306
70
  }
3307
70
3308
0
  return true;  // CC didn't match.
3309
70
}
Unexecuted instantiation: X86FastISel.cpp:RetCC_X86_64_HHVM(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:RetCC_X86_64_HHVM(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3284
70
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3285
70
3286
70
  if (LocVT == MVT::i8 ||
3287
70
      LocVT == MVT::i16 ||
3288
70
      
LocVT == MVT::i3270
) {
3289
0
    LocVT = MVT::i64;
3290
0
    if (ArgFlags.isSExt())
3291
0
        LocInfo = CCValAssign::SExt;
3292
0
    else 
if (0
ArgFlags.isZExt()0
)
3293
0
        LocInfo = CCValAssign::ZExt;
3294
0
    else
3295
0
        LocInfo = CCValAssign::AExt;
3296
0
  }
3297
70
3298
70
  if (
LocVT == MVT::i6470
) {
3299
70
    static const MCPhysReg RegList1[] = {
3300
70
      X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14, X86::R15
3301
70
    };
3302
70
    if (unsigned 
Reg70
= State.AllocateReg(RegList1)) {
3303
70
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3304
70
      return false;
3305
70
    }
3306
70
  }
3307
70
3308
0
  return true;  // CC didn't match.
3309
70
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_64_HHVM(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
3310
3311
3312
static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
3313
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3314
28
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3315
28
3316
28
  if (LocVT == MVT::i8 ||
3317
28
      LocVT == MVT::i16 ||
3318
28
      
LocVT == MVT::i3228
) {
3319
10
    LocVT = MVT::i64;
3320
10
    if (ArgFlags.isSExt())
3321
0
        LocInfo = CCValAssign::SExt;
3322
10
    else 
if (10
ArgFlags.isZExt()10
)
3323
0
        LocInfo = CCValAssign::ZExt;
3324
10
    else
3325
10
        LocInfo = CCValAssign::AExt;
3326
10
  }
3327
28
3328
28
  if (
LocVT == MVT::i6428
) {
3329
28
    static const MCPhysReg RegList1[] = {
3330
28
      X86::R15, X86::RBP, X86::RAX, X86::RDX
3331
28
    };
3332
28
    if (unsigned 
Reg28
= State.AllocateReg(RegList1)) {
3333
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3334
28
      return false;
3335
28
    }
3336
28
  }
3337
28
3338
0
  return true;  // CC didn't match.
3339
28
}
Unexecuted instantiation: X86FastISel.cpp:RetCC_X86_64_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_64_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:RetCC_X86_64_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3314
28
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3315
28
3316
28
  if (LocVT == MVT::i8 ||
3317
28
      LocVT == MVT::i16 ||
3318
28
      
LocVT == MVT::i3228
) {
3319
10
    LocVT = MVT::i64;
3320
10
    if (ArgFlags.isSExt())
3321
0
        LocInfo = CCValAssign::SExt;
3322
10
    else 
if (10
ArgFlags.isZExt()10
)
3323
0
        LocInfo = CCValAssign::ZExt;
3324
10
    else
3325
10
        LocInfo = CCValAssign::AExt;
3326
10
  }
3327
28
3328
28
  if (
LocVT == MVT::i6428
) {
3329
28
    static const MCPhysReg RegList1[] = {
3330
28
      X86::R15, X86::RBP, X86::RAX, X86::RDX
3331
28
    };
3332
28
    if (unsigned 
Reg28
= State.AllocateReg(RegList1)) {
3333
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3334
28
      return false;
3335
28
    }
3336
28
  }
3337
28
3338
0
  return true;  // CC didn't match.
3339
28
}
3340
3341
3342
static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
3343
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
3344
409
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
3345
409
3346
409
  if (
ArgFlags.isSwiftError()409
) {
3347
54
    if (
LocVT == MVT::i6454
) {
3348
54
      if (unsigned 
Reg54
= State.AllocateReg(X86::R12)) {
3349
54
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3350
54
        return false;
3351
54
      }
3352
54
    }
3353
54
  }
3354
409
3355
355
  
if (355
LocVT == MVT::v1i1355
) {
3356
0
    LocVT = MVT::i8;
3357
0
    if (ArgFlags.isSExt())
3358
0
        LocInfo = CCValAssign::SExt;
3359
0
    else 
if (0
ArgFlags.isZExt()0
)
3360
0
        LocInfo = CCValAssign::ZExt;
3361
0
    else
3362
0
        LocInfo = CCValAssign::AExt;
3363
0
  }
3364
355
3365
355
  if (
LocVT == MVT::i1355
) {
3366
0
    LocVT = MVT::i8;
3367
0
    if (ArgFlags.isSExt())
3368
0
        LocInfo = CCValAssign::SExt;
3369
0
    else 
if (0
ArgFlags.isZExt()0
)
3370
0
        LocInfo = CCValAssign::ZExt;
3371
0
    else
3372
0
        LocInfo = CCValAssign::AExt;
3373
0
  }
3374
355
3375
355
  if (
LocVT == MVT::i8355
) {
3376
36
    static const MCPhysReg RegList1[] = {
3377
36
      X86::AL, X86::DL, X86::CL, X86::R8B
3378
36
    };
3379
36
    if (unsigned 
Reg36
= State.AllocateReg(RegList1)) {
3380
36
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3381
36
      return false;
3382
36
    }
3383
36
  }
3384
355
3385
319
  
if (319
LocVT == MVT::i16319
) {
3386
4
    static const MCPhysReg RegList2[] = {
3387
4
      X86::AX, X86::DX, X86::CX, X86::R8W
3388
4
    };
3389
4
    if (unsigned 
Reg4
= State.AllocateReg(RegList2)) {
3390
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3391
4
      return false;
3392
4
    }
3393
4
  }
3394
319
3395
315
  
if (315
LocVT == MVT::i32315
) {
3396
69
    static const MCPhysReg RegList3[] = {
3397
69
      X86::EAX, X86::EDX, X86::ECX, X86::R8D
3398
69
    };
3399
69
    if (unsigned 
Reg69
= State.AllocateReg(RegList3)) {
3400
64
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3401
64
      return false;
3402
64
    }
3403
69
  }
3404
315
3405
251
  
if (251
LocVT == MVT::i64251
) {
3406
100
    static const MCPhysReg RegList4[] = {
3407
100
      X86::RAX, X86::RDX, X86::RCX, X86::R8
3408
100
    };
3409
100
    if (unsigned 
Reg100
= State.AllocateReg(RegList4)) {
3410
100
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3411
100
      return false;
3412
100
    }
3413
100
  }
3414
251
3415
151
  
if (151
LocVT == MVT::f32151
) {
3416
54
    static const MCPhysReg RegList5[] = {
3417
54
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3418
54
    };
3419
54
    if (unsigned 
Reg54
= State.AllocateReg(RegList5)) {
3420
54
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3421
54
      return false;
3422
54
    }
3423
54
  }
3424
151
3425
97
  
if (97
LocVT == MVT::f6497
) {
3426
56
    static const MCPhysReg RegList6[] = {
3427
56
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3428
56
    };
3429
56
    if (unsigned 
Reg56
= State.AllocateReg(RegList6)) {
3430
56
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3431
56
      return false;
3432
56
    }
3433
56
  }
3434
97
3435
41
  
if (41
LocVT == MVT::f12841
) {
3436
0
    static const MCPhysReg RegList7[] = {
3437
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3438
0
    };
3439
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList7)) {
3440
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3441
0
      return false;
3442
0
    }
3443
0
  }
3444
41
3445
41
  
if (41
LocVT == MVT::x86mmx41
) {
3446
0
    static const MCPhysReg RegList8[] = {
3447
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3448
0
    };
3449
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList8)) {
3450
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3451
0
      return false;
3452
0
    }
3453
0
  }
3454
41
3455
41
  
if (41
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)41
)
3456
36
    return false;
3457
41
3458
5
  return true;  // CC didn't match.
3459
409
}
X86ISelLowering.cpp:RetCC_X86_64_Swift(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3344
395
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
3345
395
3346
395
  if (
ArgFlags.isSwiftError()395
) {
3347
54
    if (
LocVT == MVT::i6454
) {
3348
54
      if (unsigned 
Reg54
= State.AllocateReg(X86::R12)) {
3349
54
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3350
54
        return false;
3351
54
      }
3352
54
    }
3353
54
  }
3354
395
3355
341
  
if (341
LocVT == MVT::v1i1341
) {
3356
0
    LocVT = MVT::i8;
3357
0
    if (ArgFlags.isSExt())
3358
0
        LocInfo = CCValAssign::SExt;
3359
0
    else 
if (0
ArgFlags.isZExt()0
)
3360
0
        LocInfo = CCValAssign::ZExt;
3361
0
    else
3362
0
        LocInfo = CCValAssign::AExt;
3363
0
  }
3364
341
3365
341
  if (
LocVT == MVT::i1341
) {
3366
0
    LocVT = MVT::i8;
3367
0
    if (ArgFlags.isSExt())
3368
0
        LocInfo = CCValAssign::SExt;
3369
0
    else 
if (0
ArgFlags.isZExt()0
)
3370
0
        LocInfo = CCValAssign::ZExt;
3371
0
    else
3372
0
        LocInfo = CCValAssign::AExt;
3373
0
  }
3374
341
3375
341
  if (
LocVT == MVT::i8341
) {
3376
31
    static const MCPhysReg RegList1[] = {
3377
31
      X86::AL, X86::DL, X86::CL, X86::R8B
3378
31
    };
3379
31
    if (unsigned 
Reg31
= State.AllocateReg(RegList1)) {
3380
31
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3381
31
      return false;
3382
31
    }
3383
31
  }
3384
341
3385
310
  
if (310
LocVT == MVT::i16310
) {
3386
3
    static const MCPhysReg RegList2[] = {
3387
3
      X86::AX, X86::DX, X86::CX, X86::R8W
3388
3
    };
3389
3
    if (unsigned 
Reg3
= State.AllocateReg(RegList2)) {
3390
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3391
3
      return false;
3392
3
    }
3393
3
  }
3394
310
3395
307
  
if (307
LocVT == MVT::i32307
) {
3396
65
    static const MCPhysReg RegList3[] = {
3397
65
      X86::EAX, X86::EDX, X86::ECX, X86::R8D
3398
65
    };
3399
65
    if (unsigned 
Reg65
= State.AllocateReg(RegList3)) {
3400
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3401
60
      return false;
3402
60
    }
3403
65
  }
3404
307
3405
247
  
if (247
LocVT == MVT::i64247
) {
3406
100
    static const MCPhysReg RegList4[] = {
3407
100
      X86::RAX, X86::RDX, X86::RCX, X86::R8
3408
100
    };
3409
100
    if (unsigned 
Reg100
= State.AllocateReg(RegList4)) {
3410
100
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3411
100
      return false;
3412
100
    }
3413
100
  }
3414
247
3415
147
  
if (147
LocVT == MVT::f32147
) {
3416
50
    static const MCPhysReg RegList5[] = {
3417
50
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3418
50
    };
3419
50
    if (unsigned 
Reg50
= State.AllocateReg(RegList5)) {
3420
50
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3421
50
      return false;
3422
50
    }
3423
50
  }
3424
147
3425
97
  
if (97
LocVT == MVT::f6497
) {
3426
56
    static const MCPhysReg RegList6[] = {
3427
56
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3428
56
    };
3429
56
    if (unsigned 
Reg56
= State.AllocateReg(RegList6)) {
3430
56
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3431
56
      return false;
3432
56
    }
3433
56
  }
3434
97
3435
41
  
if (41
LocVT == MVT::f12841
) {
3436
0
    static const MCPhysReg RegList7[] = {
3437
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3438
0
    };
3439
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList7)) {
3440
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3441
0
      return false;
3442
0
    }
3443
0
  }
3444
41
3445
41
  
if (41
LocVT == MVT::x86mmx41
) {
3446
0
    static const MCPhysReg RegList8[] = {
3447
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3448
0
    };
3449
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList8)) {
3450
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3451
0
      return false;
3452
0
    }
3453
0
  }
3454
41
3455
41
  
if (41
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)41
)
3456
36
    return false;
3457
41
3458
5
  return true;  // CC didn't match.
3459
395
}
X86FastISel.cpp:RetCC_X86_64_Swift(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3344
14
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
3345
14
3346
14
  if (
ArgFlags.isSwiftError()14
) {
3347
0
    if (
LocVT == MVT::i640
) {
3348
0
      if (unsigned 
Reg0
= State.AllocateReg(X86::R12)) {
3349
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3350
0
        return false;
3351
0
      }
3352
0
    }
3353
0
  }
3354
14
3355
14
  
if (14
LocVT == MVT::v1i114
) {
3356
0
    LocVT = MVT::i8;
3357
0
    if (ArgFlags.isSExt())
3358
0
        LocInfo = CCValAssign::SExt;
3359
0
    else 
if (0
ArgFlags.isZExt()0
)
3360
0
        LocInfo = CCValAssign::ZExt;
3361
0
    else
3362
0
        LocInfo = CCValAssign::AExt;
3363
0
  }
3364
14
3365
14
  if (
LocVT == MVT::i114
) {
3366
0
    LocVT = MVT::i8;
3367
0
    if (ArgFlags.isSExt())
3368
0
        LocInfo = CCValAssign::SExt;
3369
0
    else 
if (0
ArgFlags.isZExt()0
)
3370
0
        LocInfo = CCValAssign::ZExt;
3371
0
    else
3372
0
        LocInfo = CCValAssign::AExt;
3373
0
  }
3374
14
3375
14
  if (
LocVT == MVT::i814
) {
3376
5
    static const MCPhysReg RegList1[] = {
3377
5
      X86::AL, X86::DL, X86::CL, X86::R8B
3378
5
    };
3379
5
    if (unsigned 
Reg5
= State.AllocateReg(RegList1)) {
3380
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3381
5
      return false;
3382
5
    }
3383
5
  }
3384
14
3385
9
  
if (9
LocVT == MVT::i169
) {
3386
1
    static const MCPhysReg RegList2[] = {
3387
1
      X86::AX, X86::DX, X86::CX, X86::R8W
3388
1
    };
3389
1
    if (unsigned 
Reg1
= State.AllocateReg(RegList2)) {
3390
1
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3391
1
      return false;
3392
1
    }
3393
1
  }
3394
9
3395
8
  
if (8
LocVT == MVT::i328
) {
3396
4
    static const MCPhysReg RegList3[] = {
3397
4
      X86::EAX, X86::EDX, X86::ECX, X86::R8D
3398
4
    };
3399
4
    if (unsigned 
Reg4
= State.AllocateReg(RegList3)) {
3400
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3401
4
      return false;
3402
4
    }
3403
4
  }
3404
8
3405
4
  
if (4
LocVT == MVT::i644
) {
3406
0
    static const MCPhysReg RegList4[] = {
3407
0
      X86::RAX, X86::RDX, X86::RCX, X86::R8
3408
0
    };
3409
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList4)) {
3410
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3411
0
      return false;
3412
0
    }
3413
0
  }
3414
4
3415
4
  
if (4
LocVT == MVT::f324
) {
3416
4
    static const MCPhysReg RegList5[] = {
3417
4
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3418
4
    };
3419
4
    if (unsigned 
Reg4
= State.AllocateReg(RegList5)) {
3420
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3421
4
      return false;
3422
4
    }
3423
4
  }
3424
4
3425
0
  
if (0
LocVT == MVT::f640
) {
3426
0
    static const MCPhysReg RegList6[] = {
3427
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3428
0
    };
3429
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList6)) {
3430
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3431
0
      return false;
3432
0
    }
3433
0
  }
3434
0
3435
0
  
if (0
LocVT == MVT::f1280
) {
3436
0
    static const MCPhysReg RegList7[] = {
3437
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3438
0
    };
3439
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList7)) {
3440
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3441
0
      return false;
3442
0
    }
3443
0
  }
3444
0
3445
0
  
if (0
LocVT == MVT::x86mmx0
) {
3446
0
    static const MCPhysReg RegList8[] = {
3447
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3448
0
    };
3449
0
    if (unsigned 
Reg0
= State.AllocateReg(RegList8)) {
3450
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3451
0
      return false;
3452
0
    }
3453
0
  }
3454
0
3455
0
  
if (0
!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)0
)
3456
0
    return false;
3457
0
3458
0
  return true;  // CC didn't match.
3459
14
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_64_Swift(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
3460
3461
3462
static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
3463
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
3464
60
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3465
60
3466
60
  if (LocVT == MVT::f32 ||
3467
60
      LocVT == MVT::f64 ||
3468
60
      
LocVT == MVT::f12834
) {
3469
26
    static const MCPhysReg RegList1[] = {
3470
26
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3471
26
    };
3472
26
    if (unsigned 
Reg26
= State.AllocateReg(RegList1)) {
3473
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3474
24
      return false;
3475
24
    }
3476
26
  }
3477
60
3478
36
  
if (36
!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)36
)
3479
34
    return false;
3480
36
3481
2
  return true;  // CC didn't match.
3482
60
}
Unexecuted instantiation: X86FastISel.cpp:RetCC_X86_64_Vectorcall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:RetCC_X86_64_Vectorcall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3464
60
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3465
60
3466
60
  if (LocVT == MVT::f32 ||
3467
60
      LocVT == MVT::f64 ||
3468
60
      
LocVT == MVT::f12834
) {
3469
26
    static const MCPhysReg RegList1[] = {
3470
26
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3471
26
    };
3472
26
    if (unsigned 
Reg26
= State.AllocateReg(RegList1)) {
3473
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3474
24
      return false;
3475
24
    }
3476
26
  }
3477
60
3478
36
  
if (36
!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)36
)
3479
34
    return false;
3480
36
3481
2
  return true;  // CC didn't match.
3482
60
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_64_Vectorcall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
3483
3484
3485
static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
3486
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
3487
20
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
3488
20
3489
20
  if (LocVT == MVT::i8 ||
3490
20
      LocVT == MVT::i16 ||
3491
20
      
LocVT == MVT::i3220
) {
3492
8
    LocVT = MVT::i64;
3493
8
    if (ArgFlags.isSExt())
3494
0
        LocInfo = CCValAssign::SExt;
3495
8
    else 
if (8
ArgFlags.isZExt()8
)
3496
0
        LocInfo = CCValAssign::ZExt;
3497
8
    else
3498
8
        LocInfo = CCValAssign::AExt;
3499
8
  }
3500
20
3501
20
  if (
LocVT == MVT::i6420
) {
3502
20
    if (unsigned 
Reg20
= State.AllocateReg(X86::RAX)) {
3503
20
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3504
20
      return false;
3505
20
    }
3506
20
  }
3507
20
3508
0
  return true;  // CC didn't match.
3509
20
}
X86ISelLowering.cpp:RetCC_X86_64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3487
17
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
3488
17
3489
17
  if (LocVT == MVT::i8 ||
3490
17
      LocVT == MVT::i16 ||
3491
17
      
LocVT == MVT::i3217
) {
3492
8
    LocVT = MVT::i64;
3493
8
    if (ArgFlags.isSExt())
3494
0
        LocInfo = CCValAssign::SExt;
3495
8
    else 
if (8
ArgFlags.isZExt()8
)
3496
0
        LocInfo = CCValAssign::ZExt;
3497
8
    else
3498
8
        LocInfo = CCValAssign::AExt;
3499
8
  }
3500
17
3501
17
  if (
LocVT == MVT::i6417
) {
3502
17
    if (unsigned 
Reg17
= State.AllocateReg(X86::RAX)) {
3503
17
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3504
17
      return false;
3505
17
    }
3506
17
  }
3507
17
3508
0
  return true;  // CC didn't match.
3509
17
}
X86FastISel.cpp:RetCC_X86_64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3487
3
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
3488
3
3489
3
  if (LocVT == MVT::i8 ||
3490
3
      LocVT == MVT::i16 ||
3491
3
      
LocVT == MVT::i323
) {
3492
0
    LocVT = MVT::i64;
3493
0
    if (ArgFlags.isSExt())
3494
0
        LocInfo = CCValAssign::SExt;
3495
0
    else 
if (0
ArgFlags.isZExt()0
)
3496
0
        LocInfo = CCValAssign::ZExt;
3497
0
    else
3498
0
        LocInfo = CCValAssign::AExt;
3499
0
  }
3500
3
3501
3
  if (
LocVT == MVT::i643
) {
3502
3
    if (unsigned 
Reg3
= State.AllocateReg(X86::RAX)) {
3503
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3504
3
      return false;
3505
3
    }
3506
3
  }
3507
3
3508
0
  return true;  // CC didn't match.
3509
3
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
3510
3511
3512
static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
3513
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
3514
158
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
3515
158
3516
158
  if (LocVT == MVT::i1 ||
3517
158
      LocVT == MVT::v1i1 ||
3518
158
      
LocVT == MVT::v8i1158
) {
3519
4
    LocVT = MVT::i8;
3520
4
    if (ArgFlags.isSExt())
3521
0
        LocInfo = CCValAssign::SExt;
3522
4
    else 
if (4
ArgFlags.isZExt()4
)
3523
0
        LocInfo = CCValAssign::ZExt;
3524
4
    else
3525
4
        LocInfo = CCValAssign::AExt;
3526
4
  }
3527
158
3528
158
  if (
LocVT == MVT::v16i1158
) {
3529
4
    LocVT = MVT::i16;
3530
4
    if (ArgFlags.isSExt())
3531
0
        LocInfo = CCValAssign::SExt;
3532
4
    else 
if (4
ArgFlags.isZExt()4
)
3533
0
        LocInfo = CCValAssign::ZExt;
3534
4
    else
3535
4
        LocInfo = CCValAssign::AExt;
3536
4
  }
3537
158
3538
158
  if (
LocVT == MVT::v32i1158
) {
3539
4
    LocVT = MVT::i32;
3540
4
    if (ArgFlags.isSExt())
3541
0
        LocInfo = CCValAssign::SExt;
3542
4
    else 
if (4
ArgFlags.isZExt()4
)
3543
0
        LocInfo = CCValAssign::ZExt;
3544
4
    else
3545
4
        LocInfo = CCValAssign::AExt;
3546
4
  }
3547
158
3548
158
  if (
LocVT == MVT::i8158
) {
3549
28
    static const MCPhysReg RegList1[] = {
3550
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
3551
28
    };
3552
28
    if (unsigned 
Reg28
= State.AllocateReg(RegList1)) {
3553
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3554
28
      return false;
3555
28
    }
3556
28
  }
3557
158
3558
130
  
if (130
LocVT == MVT::i16130
) {
3559
14
    static const MCPhysReg RegList2[] = {
3560
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
3561
14
    };
3562
14
    if (unsigned 
Reg14
= State.AllocateReg(RegList2)) {
3563
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3564
14
      return false;
3565
14
    }
3566
14
  }
3567
130
3568
116
  
if (116
LocVT == MVT::i32116
) {
3569
22
    static const MCPhysReg RegList3[] = {
3570
22
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
3571
22
    };
3572
22
    if (unsigned 
Reg22
= State.AllocateReg(RegList3)) {
3573
22
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3574
22
      return false;
3575
22
    }
3576
22
  }
3577
116
3578
94
  
if (94
LocVT == MVT::i6494
) {
3579
18
    static const MCPhysReg RegList4[] = {
3580
18
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3581
18
    };
3582
18
    if (unsigned 
Reg18
= State.AllocateReg(RegList4)) {
3583
18
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3584
18
      return false;
3585
18
    }
3586
18
  }
3587
94
3588
76
  
if (76
LocVT == MVT::v64i176
) {
3589
4
    LocVT = MVT::i64;
3590
4
    if (ArgFlags.isSExt())
3591
0
        LocInfo = CCValAssign::SExt;
3592
4
    else 
if (4
ArgFlags.isZExt()4
)
3593
0
        LocInfo = CCValAssign::ZExt;
3594
4
    else
3595
4
        LocInfo = CCValAssign::AExt;
3596
4
  }
3597
76
3598
76
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()76
) {
3599
76
    if (
LocVT == MVT::i6476
) {
3600
4
      static const MCPhysReg RegList5[] = {
3601
4
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3602
4
      };
3603
4
      if (unsigned 
Reg4
= State.AllocateReg(RegList5)) {
3604
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3605
4
        return false;
3606
4
      }
3607
4
    }
3608
76
  }
3609
76
3610
72
  
if (72
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()72
) {
3611
0
    if (
LocVT == MVT::i640
) {
3612
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3613
0
            return false;
3614
0
    }
3615
0
  }
3616
72
3617
72
  
if (72
LocVT == MVT::f8072
) {
3618
6
    static const MCPhysReg RegList6[] = {
3619
6
      X86::FP0, X86::FP1
3620
6
    };
3621
6
    if (unsigned 
Reg6
= State.AllocateReg(RegList6)) {
3622
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3623
6
      return false;
3624
6
    }
3625
6
  }
3626
72
3627
66
  
if (66
LocVT == MVT::f32 ||
3628
58
      LocVT == MVT::f64 ||
3629
66
      
LocVT == MVT::f12850
) {
3630
16
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()16
) {
3631
16
      static const MCPhysReg RegList7[] = {
3632
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3633
16
      };
3634
16
      if (unsigned 
Reg16
= State.AllocateReg(RegList7)) {
3635
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3636
16
        return false;
3637
16
      }
3638
16
    }
3639
16
  }
3640
66
3641
50
  
if (50
LocVT == MVT::v16i8 ||
3642
50
      LocVT == MVT::v8i16 ||
3643
50
      LocVT == MVT::v4i32 ||
3644
44
      LocVT == MVT::v2i64 ||
3645
44
      LocVT == MVT::v4f32 ||
3646
50
      
LocVT == MVT::v2f6420
) {
3647
30
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()30
) {
3648
30
      static const MCPhysReg RegList8[] = {
3649
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3650
30
      };
3651
30
      if (unsigned 
Reg30
= State.AllocateReg(RegList8)) {
3652
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3653
30
        return false;
3654
30
      }
3655
30
    }
3656
30
  }
3657
50
3658
20
  
if (20
LocVT == MVT::v32i8 ||
3659
20
      LocVT == MVT::v16i16 ||
3660
20
      LocVT == MVT::v8i32 ||
3661
14
      LocVT == MVT::v4i64 ||
3662
14
      LocVT == MVT::v8f32 ||
3663
20
      
LocVT == MVT::v4f6414
) {
3664
6
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()6
) {
3665
6
      static const MCPhysReg RegList9[] = {
3666
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3667
6
      };
3668
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList9)) {
3669
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3670
6
        return false;
3671
6
      }
3672
6
    }
3673
6
  }
3674
20
3675
14
  
if (14
LocVT == MVT::v64i8 ||
3676
14
      LocVT == MVT::v32i16 ||
3677
14
      LocVT == MVT::v16i32 ||
3678
8
      LocVT == MVT::v8i64 ||
3679
8
      LocVT == MVT::v16f32 ||
3680
14
      
LocVT == MVT::v8f640
) {
3681
14
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()14
) {
3682
14
      static const MCPhysReg RegList10[] = {
3683
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3684
14
      };
3685
14
      if (unsigned 
Reg14
= State.AllocateReg(RegList10)) {
3686
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3687
14
        return false;
3688
14
      }
3689
14
    }
3690
14
  }
3691
14
3692
0
  return true;  // CC didn't match.
3693
158
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_SysV64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:RetCC_X86_SysV64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3514
158
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
3515
158
3516
158
  if (LocVT == MVT::i1 ||
3517
158
      LocVT == MVT::v1i1 ||
3518
158
      
LocVT == MVT::v8i1158
) {
3519
4
    LocVT = MVT::i8;
3520
4
    if (ArgFlags.isSExt())
3521
0
        LocInfo = CCValAssign::SExt;
3522
4
    else 
if (4
ArgFlags.isZExt()4
)
3523
0
        LocInfo = CCValAssign::ZExt;
3524
4
    else
3525
4
        LocInfo = CCValAssign::AExt;
3526
4
  }
3527
158
3528
158
  if (
LocVT == MVT::v16i1158
) {
3529
4
    LocVT = MVT::i16;
3530
4
    if (ArgFlags.isSExt())
3531
0
        LocInfo = CCValAssign::SExt;
3532
4
    else 
if (4
ArgFlags.isZExt()4
)
3533
0
        LocInfo = CCValAssign::ZExt;
3534
4
    else
3535
4
        LocInfo = CCValAssign::AExt;
3536
4
  }
3537
158
3538
158
  if (
LocVT == MVT::v32i1158
) {
3539
4
    LocVT = MVT::i32;
3540
4
    if (ArgFlags.isSExt())
3541
0
        LocInfo = CCValAssign::SExt;
3542
4
    else 
if (4
ArgFlags.isZExt()4
)
3543
0
        LocInfo = CCValAssign::ZExt;
3544
4
    else
3545
4
        LocInfo = CCValAssign::AExt;
3546
4
  }
3547
158
3548
158
  if (
LocVT == MVT::i8158
) {
3549
28
    static const MCPhysReg RegList1[] = {
3550
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
3551
28
    };
3552
28
    if (unsigned 
Reg28
= State.AllocateReg(RegList1)) {
3553
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3554
28
      return false;
3555
28
    }
3556
28
  }
3557
158
3558
130
  
if (130
LocVT == MVT::i16130
) {
3559
14
    static const MCPhysReg RegList2[] = {
3560
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
3561
14
    };
3562
14
    if (unsigned 
Reg14
= State.AllocateReg(RegList2)) {
3563
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3564
14
      return false;
3565
14
    }
3566
14
  }
3567
130
3568
116
  
if (116
LocVT == MVT::i32116
) {
3569
22
    static const MCPhysReg RegList3[] = {
3570
22
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
3571
22
    };
3572
22
    if (unsigned 
Reg22
= State.AllocateReg(RegList3)) {
3573
22
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3574
22
      return false;
3575
22
    }
3576
22
  }
3577
116
3578
94
  
if (94
LocVT == MVT::i6494
) {
3579
18
    static const MCPhysReg RegList4[] = {
3580
18
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3581
18
    };
3582
18
    if (unsigned 
Reg18
= State.AllocateReg(RegList4)) {
3583
18
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3584
18
      return false;
3585
18
    }
3586
18
  }
3587
94
3588
76
  
if (76
LocVT == MVT::v64i176
) {
3589
4
    LocVT = MVT::i64;
3590
4
    if (ArgFlags.isSExt())
3591
0
        LocInfo = CCValAssign::SExt;
3592
4
    else 
if (4
ArgFlags.isZExt()4
)
3593
0
        LocInfo = CCValAssign::ZExt;
3594
4
    else
3595
4
        LocInfo = CCValAssign::AExt;
3596
4
  }
3597
76
3598
76
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()76
) {
3599
76
    if (
LocVT == MVT::i6476
) {
3600
4
      static const MCPhysReg RegList5[] = {
3601
4
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3602
4
      };
3603
4
      if (unsigned 
Reg4
= State.AllocateReg(RegList5)) {
3604
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3605
4
        return false;
3606
4
      }
3607
4
    }
3608
76
  }
3609
76
3610
72
  
if (72
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()72
) {
3611
0
    if (
LocVT == MVT::i640
) {
3612
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3613
0
            return false;
3614
0
    }
3615
0
  }
3616
72
3617
72
  
if (72
LocVT == MVT::f8072
) {
3618
6
    static const MCPhysReg RegList6[] = {
3619
6
      X86::FP0, X86::FP1
3620
6
    };
3621
6
    if (unsigned 
Reg6
= State.AllocateReg(RegList6)) {
3622
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3623
6
      return false;
3624
6
    }
3625
6
  }
3626
72
3627
66
  
if (66
LocVT == MVT::f32 ||
3628
58
      LocVT == MVT::f64 ||
3629
66
      
LocVT == MVT::f12850
) {
3630
16
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()16
) {
3631
16
      static const MCPhysReg RegList7[] = {
3632
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3633
16
      };
3634
16
      if (unsigned 
Reg16
= State.AllocateReg(RegList7)) {
3635
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3636
16
        return false;
3637
16
      }
3638
16
    }
3639
16
  }
3640
66
3641
50
  
if (50
LocVT == MVT::v16i8 ||
3642
50
      LocVT == MVT::v8i16 ||
3643
50
      LocVT == MVT::v4i32 ||
3644
44
      LocVT == MVT::v2i64 ||
3645
44
      LocVT == MVT::v4f32 ||
3646
50
      
LocVT == MVT::v2f6420
) {
3647
30
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()30
) {
3648
30
      static const MCPhysReg RegList8[] = {
3649
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3650
30
      };
3651
30
      if (unsigned 
Reg30
= State.AllocateReg(RegList8)) {
3652
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3653
30
        return false;
3654
30
      }
3655
30
    }
3656
30
  }
3657
50
3658
20
  
if (20
LocVT == MVT::v32i8 ||
3659
20
      LocVT == MVT::v16i16 ||
3660
20
      LocVT == MVT::v8i32 ||
3661
14
      LocVT == MVT::v4i64 ||
3662
14
      LocVT == MVT::v8f32 ||
3663
20
      
LocVT == MVT::v4f6414
) {
3664
6
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()6
) {
3665
6
      static const MCPhysReg RegList9[] = {
3666
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3667
6
      };
3668
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList9)) {
3669
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3670
6
        return false;
3671
6
      }
3672
6
    }
3673
6
  }
3674
20
3675
14
  
if (14
LocVT == MVT::v64i8 ||
3676
14
      LocVT == MVT::v32i16 ||
3677
14
      LocVT == MVT::v16i32 ||
3678
8
      LocVT == MVT::v8i64 ||
3679
8
      LocVT == MVT::v16f32 ||
3680
14
      
LocVT == MVT::v8f640
) {
3681
14
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()14
) {
3682
14
      static const MCPhysReg RegList10[] = {
3683
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3684
14
      };
3685
14
      if (unsigned 
Reg14
= State.AllocateReg(RegList10)) {
3686
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3687
14
        return false;
3688
14
      }
3689
14
    }
3690
14
  }
3691
14
3692
0
  return true;  // CC didn't match.
3693
158
}
Unexecuted instantiation: X86FastISel.cpp:RetCC_X86_SysV64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
3694
3695
3696
static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
3697
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3698
1.85k
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3699
1.85k
3700
1.85k
  if (
LocVT == MVT::x86mmx1.85k
) {
3701
0
    LocVT = MVT::i64;
3702
0
    LocInfo = CCValAssign::BCvt;
3703
0
  }
3704
1.85k
3705
1.85k
  if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3706
1.85k
    return false;
3707
1.85k
3708
4
  return true;  // CC didn't match.
3709
1.85k
}
X86ISelLowering.cpp:RetCC_X86_Win64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3698
1.83k
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3699
1.83k
3700
1.83k
  if (
LocVT == MVT::x86mmx1.83k
) {
3701
0
    LocVT = MVT::i64;
3702
0
    LocInfo = CCValAssign::BCvt;
3703
0
  }
3704
1.83k
3705
1.83k
  if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3706
1.83k
    return false;
3707
1.83k
3708
4
  return true;  // CC didn't match.
3709
1.83k
}
X86FastISel.cpp:RetCC_X86_Win64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3698
20
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3699
20
3700
20
  if (
LocVT == MVT::x86mmx20
) {
3701
0
    LocVT = MVT::i64;
3702
0
    LocInfo = CCValAssign::BCvt;
3703
0
  }
3704
20
3705
20
  if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3706
20
    return false;
3707
20
3708
0
  return true;  // CC didn't match.
3709
20
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_Win64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
3710
3711
3712
static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
3713
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
3714
166
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3715
166
3716
166
  if (LocVT == MVT::i1 ||
3717
166
      LocVT == MVT::v1i1 ||
3718
166
      
LocVT == MVT::v8i1166
) {
3719
4
    LocVT = MVT::i8;
3720
4
    if (ArgFlags.isSExt())
3721
0
        LocInfo = CCValAssign::SExt;
3722
4
    else 
if (4
ArgFlags.isZExt()4
)
3723
0
        LocInfo = CCValAssign::ZExt;
3724
4
    else
3725
4
        LocInfo = CCValAssign::AExt;
3726
4
  }
3727
166
3728
166
  if (
LocVT == MVT::v16i1166
) {
3729
4
    LocVT = MVT::i16;
3730
4
    if (ArgFlags.isSExt())
3731
0
        LocInfo = CCValAssign::SExt;
3732
4
    else 
if (4
ArgFlags.isZExt()4
)
3733
0
        LocInfo = CCValAssign::ZExt;
3734
4
    else
3735
4
        LocInfo = CCValAssign::AExt;
3736
4
  }
3737
166
3738
166
  if (
LocVT == MVT::v32i1166
) {
3739
4
    LocVT = MVT::i32;
3740
4
    if (ArgFlags.isSExt())
3741
0
        LocInfo = CCValAssign::SExt;
3742
4
    else 
if (4
ArgFlags.isZExt()4
)
3743
0
        LocInfo = CCValAssign::ZExt;
3744
4
    else
3745
4
        LocInfo = CCValAssign::AExt;
3746
4
  }
3747
166
3748
166
  if (
LocVT == MVT::i8166
) {
3749
28
    static const MCPhysReg RegList1[] = {
3750
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
3751
28
    };
3752
28
    if (unsigned 
Reg28
= State.AllocateReg(RegList1)) {
3753
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3754
28
      return false;
3755
28
    }
3756
28
  }
3757
166
3758
138
  
if (138
LocVT == MVT::i16138
) {
3759
14
    static const MCPhysReg RegList2[] = {
3760
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
3761
14
    };
3762
14
    if (unsigned 
Reg14
= State.AllocateReg(RegList2)) {
3763
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3764
14
      return false;
3765
14
    }
3766
14
  }
3767
138
3768
124
  
if (124
LocVT == MVT::i32124
) {
3769
30
    static const MCPhysReg RegList3[] = {
3770
30
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
3771
30
    };
3772
30
    if (unsigned 
Reg30
= State.AllocateReg(RegList3)) {
3773
30
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3774
30
      return false;
3775
30
    }
3776
30
  }
3777
124
3778
94
  
if (94
LocVT == MVT::i6494
) {
3779
18
    static const MCPhysReg RegList4[] = {
3780
18
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3781
18
    };
3782
18
    if (unsigned 
Reg18
= State.AllocateReg(RegList4)) {
3783
18
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3784
18
      return false;
3785
18
    }
3786
18
  }
3787
94
3788
76
  
if (76
LocVT == MVT::v64i176
) {
3789
4
    LocVT = MVT::i64;
3790
4
    if (ArgFlags.isSExt())
3791
0
        LocInfo = CCValAssign::SExt;
3792
4
    else 
if (4
ArgFlags.isZExt()4
)
3793
0
        LocInfo = CCValAssign::ZExt;
3794
4
    else
3795
4
        LocInfo = CCValAssign::AExt;
3796
4
  }
3797
76
3798
76
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()76
) {
3799
76
    if (
LocVT == MVT::i6476
) {
3800
4
      static const MCPhysReg RegList5[] = {
3801
4
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3802
4
      };
3803
4
      if (unsigned 
Reg4
= State.AllocateReg(RegList5)) {
3804
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3805
4
        return false;
3806
4
      }
3807
4
    }
3808
76
  }
3809
76
3810
72
  
if (72
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()72
) {
3811
0
    if (
LocVT == MVT::i640
) {
3812
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3813
0
            return false;
3814
0
    }
3815
0
  }
3816
72
3817
72
  
if (72
LocVT == MVT::f8072
) {
3818
6
    static const MCPhysReg RegList6[] = {
3819
6
      X86::FP0, X86::FP1
3820
6
    };
3821
6
    if (unsigned 
Reg6
= State.AllocateReg(RegList6)) {
3822
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3823
6
      return false;
3824
6
    }
3825
6
  }
3826
72
3827
66
  
if (66
LocVT == MVT::f32 ||
3828
58
      LocVT == MVT::f64 ||
3829
66
      
LocVT == MVT::f12850
) {
3830
16
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()16
) {
3831
16
      static const MCPhysReg RegList7[] = {
3832
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3833
16
      };
3834
16
      if (unsigned 
Reg16
= State.AllocateReg(RegList7)) {
3835
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3836
16
        return false;
3837
16
      }
3838
16
    }
3839
16
  }
3840
66
3841
50
  
if (50
LocVT == MVT::v16i8 ||
3842
50
      LocVT == MVT::v8i16 ||
3843
50
      LocVT == MVT::v4i32 ||
3844
44
      LocVT == MVT::v2i64 ||
3845
44
      LocVT == MVT::v4f32 ||
3846
50
      
LocVT == MVT::v2f6420
) {
3847
30
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()30
) {
3848
30
      static const MCPhysReg RegList8[] = {
3849
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3850
30
      };
3851
30
      if (unsigned 
Reg30
= State.AllocateReg(RegList8)) {
3852
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3853
30
        return false;
3854
30
      }
3855
30
    }
3856
30
  }
3857
50
3858
20
  
if (20
LocVT == MVT::v32i8 ||
3859
20
      LocVT == MVT::v16i16 ||
3860
20
      LocVT == MVT::v8i32 ||
3861
14
      LocVT == MVT::v4i64 ||
3862
14
      LocVT == MVT::v8f32 ||
3863
20
      
LocVT == MVT::v4f6414
) {
3864
6
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()6
) {
3865
6
      static const MCPhysReg RegList9[] = {
3866
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3867
6
      };
3868
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList9)) {
3869
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3870
6
        return false;
3871
6
      }
3872
6
    }
3873
6
  }
3874
20
3875
14
  
if (14
LocVT == MVT::v64i8 ||
3876
14
      LocVT == MVT::v32i16 ||
3877
14
      LocVT == MVT::v16i32 ||
3878
8
      LocVT == MVT::v8i64 ||
3879
8
      LocVT == MVT::v16f32 ||
3880
14
      
LocVT == MVT::v8f640
) {
3881
14
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()14
) {
3882
14
      static const MCPhysReg RegList10[] = {
3883
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3884
14
      };
3885
14
      if (unsigned 
Reg14
= State.AllocateReg(RegList10)) {
3886
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3887
14
        return false;
3888
14
      }
3889
14
    }
3890
14
  }
3891
14
3892
0
  return true;  // CC didn't match.
3893
166
}
Unexecuted instantiation: X86CallLowering.cpp:RetCC_X86_Win64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:RetCC_X86_Win64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:RetCC_X86_Win64_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
3714
166
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3715
166
3716
166
  if (LocVT == MVT::i1 ||
3717
166
      LocVT == MVT::v1i1 ||
3718
166
      
LocVT == MVT::v8i1166
) {
3719
4
    LocVT = MVT::i8;
3720
4
    if (ArgFlags.isSExt())
3721
0
        LocInfo = CCValAssign::SExt;
3722
4
    else 
if (4
ArgFlags.isZExt()4
)
3723
0
        LocInfo = CCValAssign::ZExt;
3724
4
    else
3725
4
        LocInfo = CCValAssign::AExt;
3726
4
  }
3727
166
3728
166
  if (
LocVT == MVT::v16i1166
) {
3729
4
    LocVT = MVT::i16;
3730
4
    if (ArgFlags.isSExt())
3731
0
        LocInfo = CCValAssign::SExt;
3732
4
    else 
if (4
ArgFlags.isZExt()4
)
3733
0
        LocInfo = CCValAssign::ZExt;
3734
4
    else
3735
4
        LocInfo = CCValAssign::AExt;
3736
4
  }
3737
166
3738
166
  if (
LocVT == MVT::v32i1166
) {
3739
4
    LocVT = MVT::i32;
3740
4
    if (ArgFlags.isSExt())
3741
0
        LocInfo = CCValAssign::SExt;
3742
4
    else 
if (4
ArgFlags.isZExt()4
)
3743
0
        LocInfo = CCValAssign::ZExt;
3744
4
    else
3745
4
        LocInfo = CCValAssign::AExt;
3746
4
  }
3747
166
3748
166
  if (
LocVT == MVT::i8166
) {
3749
28
    static const MCPhysReg RegList1[] = {
3750
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
3751
28
    };
3752
28
    if (unsigned 
Reg28
= State.AllocateReg(RegList1)) {
3753
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3754
28
      return false;
3755
28
    }
3756
28
  }
3757
166
3758
138
  
if (138
LocVT == MVT::i16138
) {
3759
14
    static const MCPhysReg RegList2[] = {
3760
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
3761
14
    };
3762
14
    if (unsigned 
Reg14
= State.AllocateReg(RegList2)) {
3763
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3764
14
      return false;
3765
14
    }
3766
14
  }
3767
138
3768
124
  
if (124
LocVT == MVT::i32124
) {
3769
30
    static const MCPhysReg RegList3[] = {
3770
30
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
3771
30
    };
3772
30
    if (unsigned 
Reg30
= State.AllocateReg(RegList3)) {
3773
30
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3774
30
      return false;
3775
30
    }
3776
30
  }
3777
124
3778
94
  
if (94
LocVT == MVT::i6494
) {
3779
18
    static const MCPhysReg RegList4[] = {
3780
18
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3781
18
    };
3782
18
    if (unsigned 
Reg18
= State.AllocateReg(RegList4)) {
3783
18
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3784
18
      return false;
3785
18
    }
3786
18
  }
3787
94
3788
76
  
if (76
LocVT == MVT::v64i176
) {
3789
4
    LocVT = MVT::i64;
3790
4
    if (ArgFlags.isSExt())
3791
0
        LocInfo = CCValAssign::SExt;
3792
4
    else 
if (4
ArgFlags.isZExt()4
)
3793
0
        LocInfo = CCValAssign::ZExt;
3794
4
    else
3795
4
        LocInfo = CCValAssign::AExt;
3796
4
  }
3797
76
3798
76
  if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()76
) {
3799
76
    if (
LocVT == MVT::i6476
) {
3800
4
      static const MCPhysReg RegList5[] = {
3801
4
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3802
4
      };
3803
4
      if (unsigned 
Reg4
= State.AllocateReg(RegList5)) {
3804
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3805
4
        return false;
3806
4
      }
3807
4
    }
3808
76
  }
3809
76
3810
72
  
if (72
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()72
) {
3811
0
    if (
LocVT == MVT::i640
) {
3812
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3813
0
            return false;
3814
0
    }
3815
0
  }
3816
72
3817
72
  
if (72
LocVT == MVT::f8072
) {
3818
6
    static const MCPhysReg RegList6[] = {
3819
6
      X86::FP0, X86::FP1
3820
6
    };
3821
6
    if (unsigned 
Reg6
= State.AllocateReg(RegList6)) {
3822
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3823
6
      return false;
3824
6
    }
3825
6
  }
3826
72
3827
66
  
if (66
LocVT == MVT::f32 ||
3828
58
      LocVT == MVT::f64 ||
3829
66
      
LocVT == MVT::f12850
) {
3830
16
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()16
) {
3831
16
      static const MCPhysReg RegList7[] = {
3832
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3833
16
      };
3834
16
      if (unsigned 
Reg16
= State.AllocateReg(RegList7)) {
3835
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3836
16
        return false;
3837
16
      }
3838
16
    }
3839
16
  }
3840
66
3841
50
  
if (50
LocVT == MVT::v16i8 ||
3842
50
      LocVT == MVT::v8i16 ||
3843
50
      LocVT == MVT::v4i32 ||
3844
44
      LocVT == MVT::v2i64 ||
3845
44
      LocVT == MVT::v4f32 ||
3846
50
      
LocVT == MVT::v2f6420
) {
3847
30
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()30
) {
3848
30
      static const MCPhysReg RegList8[] = {
3849
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3850
30
      };
3851
30
      if (unsigned 
Reg30
= State.AllocateReg(RegList8)) {
3852
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3853
30
        return false;
3854
30
      }
3855
30
    }
3856
30
  }
3857
50
3858
20
  
if (20
LocVT == MVT::v32i8 ||
3859
20
      LocVT == MVT::v16i16 ||
3860
20
      LocVT == MVT::v8i32 ||
3861
14
      LocVT == MVT::v4i64 ||
3862
14
      LocVT == MVT::v8f32 ||
3863
20
      
LocVT == MVT::v4f6414
) {
3864
6
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()6
) {
3865
6
      static const MCPhysReg RegList9[] = {
3866
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3867
6
      };
3868
6
      if (unsigned 
Reg6
= State.AllocateReg(RegList9)) {
3869
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3870
6
        return false;
3871
6
      }
3872
6
    }
3873
6
  }
3874
20
3875
14
  
if (14
LocVT == MVT::v64i8 ||
3876
14
      LocVT == MVT::v32i16 ||
3877
14
      LocVT == MVT::v16i32 ||
3878
8
      LocVT == MVT::v8i64 ||
3879
8
      LocVT == MVT::v16f32 ||
3880
14
      
LocVT == MVT::v8f640
) {
3881
14
    if (
static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()14
) {
3882
14
      static const MCPhysReg RegList10[] = {
3883
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3884
14
      };
3885
14
      if (unsigned 
Reg14
= State.AllocateReg(RegList10)) {
3886
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3887
14
        return false;
3888
14
      }
3889
14
    }
3890
14
  }
3891
14
3892
0
  return true;  // CC didn't match.
3893
166
}