/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/clang-build/lib/Target/X86/X86GenFastISel.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* "Fast" Instruction Selector for the X86 target *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | |
10 | | // FastEmit Immediate Predicate functions. |
11 | 10 | static bool Predicate_i16immSExt8(int64_t Imm) { |
12 | 10 | return isInt<8>(Imm); |
13 | 10 | } |
14 | 224 | static bool Predicate_i32immSExt8(int64_t Imm) { |
15 | 224 | return isInt<8>(Imm); |
16 | 224 | } |
17 | 152 | static bool Predicate_i64immSExt8(int64_t Imm) { |
18 | 152 | return isInt<8>(Imm); |
19 | 152 | } |
20 | 0 | static bool Predicate_FROUND_NO_EXC(int64_t Imm) { |
21 | 0 | return Imm == 8; |
22 | 0 | } |
23 | 0 | static bool Predicate_FROUND_CURRENT(int64_t Imm) { |
24 | 0 |
|
25 | 0 | return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION; |
26 | 0 |
|
27 | 0 | } |
28 | 53 | static bool Predicate_i64immSExt32(int64_t Imm) { |
29 | 53 | return isInt<32>(Imm); |
30 | 53 | } |
31 | 0 | static bool Predicate_AndMask64(int64_t Imm) { |
32 | 0 |
|
33 | 0 | return isMask_64(Imm) && Imm > UINT32_MAX; |
34 | 0 |
|
35 | 0 | } |
36 | | |
37 | | |
38 | | // FastEmit functions for ISD::ABS. |
39 | | |
40 | 0 | unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
41 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
42 | 0 | return 0; |
43 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
44 | 0 | return fastEmitInst_r(X86::VPABSBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
45 | 0 | } |
46 | 0 | if (0 (Subtarget->hasSSSE3() && 0 !Subtarget->hasAVX()0 )) { |
47 | 0 | return fastEmitInst_r(X86::PABSBrr, &X86::VR128RegClass, Op0, Op0IsKill); |
48 | 0 | } |
49 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
50 | 0 | return fastEmitInst_r(X86::VPABSBrr, &X86::VR128RegClass, Op0, Op0IsKill); |
51 | 0 | } |
52 | 0 | return 0; |
53 | 0 | } |
54 | | |
55 | 0 | unsigned fastEmit_ISD_ABS_MVT_v32i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
56 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
57 | 0 | return 0; |
58 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
59 | 0 | return fastEmitInst_r(X86::VPABSBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
60 | 0 | } |
61 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
62 | 0 | return fastEmitInst_r(X86::VPABSBYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
63 | 0 | } |
64 | 0 | return 0; |
65 | 0 | } |
66 | | |
67 | 0 | unsigned fastEmit_ISD_ABS_MVT_v64i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
68 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
69 | 0 | return 0; |
70 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
71 | 0 | return fastEmitInst_r(X86::VPABSBZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
72 | 0 | } |
73 | 0 | return 0; |
74 | 0 | } |
75 | | |
76 | 0 | unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
77 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
78 | 0 | return 0; |
79 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
80 | 0 | return fastEmitInst_r(X86::VPABSWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
81 | 0 | } |
82 | 0 | if (0 (Subtarget->hasSSSE3() && 0 !Subtarget->hasAVX()0 )) { |
83 | 0 | return fastEmitInst_r(X86::PABSWrr, &X86::VR128RegClass, Op0, Op0IsKill); |
84 | 0 | } |
85 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
86 | 0 | return fastEmitInst_r(X86::VPABSWrr, &X86::VR128RegClass, Op0, Op0IsKill); |
87 | 0 | } |
88 | 0 | return 0; |
89 | 0 | } |
90 | | |
91 | 0 | unsigned fastEmit_ISD_ABS_MVT_v16i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
92 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
93 | 0 | return 0; |
94 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
95 | 0 | return fastEmitInst_r(X86::VPABSWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
96 | 0 | } |
97 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
98 | 0 | return fastEmitInst_r(X86::VPABSWYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
99 | 0 | } |
100 | 0 | return 0; |
101 | 0 | } |
102 | | |
103 | 0 | unsigned fastEmit_ISD_ABS_MVT_v32i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
104 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
105 | 0 | return 0; |
106 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
107 | 0 | return fastEmitInst_r(X86::VPABSWZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
108 | 0 | } |
109 | 0 | return 0; |
110 | 0 | } |
111 | | |
112 | 0 | unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
113 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
114 | 0 | return 0; |
115 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
116 | 0 | return fastEmitInst_r(X86::VPABSDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
117 | 0 | } |
118 | 0 | if (0 (Subtarget->hasSSSE3() && 0 !Subtarget->hasAVX()0 )) { |
119 | 0 | return fastEmitInst_r(X86::PABSDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
120 | 0 | } |
121 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
122 | 0 | return fastEmitInst_r(X86::VPABSDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
123 | 0 | } |
124 | 0 | return 0; |
125 | 0 | } |
126 | | |
127 | 0 | unsigned fastEmit_ISD_ABS_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
128 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
129 | 0 | return 0; |
130 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
131 | 0 | return fastEmitInst_r(X86::VPABSDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
132 | 0 | } |
133 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
134 | 0 | return fastEmitInst_r(X86::VPABSDYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
135 | 0 | } |
136 | 0 | return 0; |
137 | 0 | } |
138 | | |
139 | 0 | unsigned fastEmit_ISD_ABS_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
140 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
141 | 0 | return 0; |
142 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
143 | 0 | return fastEmitInst_r(X86::VPABSDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
144 | 0 | } |
145 | 0 | return 0; |
146 | 0 | } |
147 | | |
148 | 0 | unsigned fastEmit_ISD_ABS_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
149 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
150 | 0 | return 0; |
151 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
152 | 0 | return fastEmitInst_r(X86::VPABSQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
153 | 0 | } |
154 | 0 | return 0; |
155 | 0 | } |
156 | | |
157 | 0 | unsigned fastEmit_ISD_ABS_MVT_v4i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
158 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
159 | 0 | return 0; |
160 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
161 | 0 | return fastEmitInst_r(X86::VPABSQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
162 | 0 | } |
163 | 0 | return 0; |
164 | 0 | } |
165 | | |
166 | 0 | unsigned fastEmit_ISD_ABS_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
167 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
168 | 0 | return 0; |
169 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
170 | 0 | return fastEmitInst_r(X86::VPABSQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
171 | 0 | } |
172 | 0 | return 0; |
173 | 0 | } |
174 | | |
175 | | unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
176 | | switch (VT.SimpleTy) { |
177 | | case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0, Op0IsKill); |
178 | | case MVT::v32i8: return fastEmit_ISD_ABS_MVT_v32i8_r(RetVT, Op0, Op0IsKill); |
179 | | case MVT::v64i8: return fastEmit_ISD_ABS_MVT_v64i8_r(RetVT, Op0, Op0IsKill); |
180 | | case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0, Op0IsKill); |
181 | | case MVT::v16i16: return fastEmit_ISD_ABS_MVT_v16i16_r(RetVT, Op0, Op0IsKill); |
182 | | case MVT::v32i16: return fastEmit_ISD_ABS_MVT_v32i16_r(RetVT, Op0, Op0IsKill); |
183 | | case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
184 | | case MVT::v8i32: return fastEmit_ISD_ABS_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
185 | | case MVT::v16i32: return fastEmit_ISD_ABS_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
186 | | case MVT::v2i64: return fastEmit_ISD_ABS_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
187 | | case MVT::v4i64: return fastEmit_ISD_ABS_MVT_v4i64_r(RetVT, Op0, Op0IsKill); |
188 | | case MVT::v8i64: return fastEmit_ISD_ABS_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
189 | | default: return 0; |
190 | | } |
191 | | } |
192 | | |
193 | | // FastEmit functions for ISD::ANY_EXTEND. |
194 | | |
195 | 3 | unsigned fastEmit_ISD_ANY_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
196 | 3 | if (RetVT.SimpleTy != MVT::i32) |
197 | 0 | return 0; |
198 | 3 | return fastEmitInst_r(X86::MOVZX32rr8, &X86::GR32RegClass, Op0, Op0IsKill); |
199 | 3 | } |
200 | | |
201 | 6 | unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
202 | 6 | switch (VT.SimpleTy) { |
203 | 3 | case MVT::i8: return fastEmit_ISD_ANY_EXTEND_MVT_i8_r(RetVT, Op0, Op0IsKill); |
204 | 3 | default: return 0; |
205 | 6 | } |
206 | 6 | } |
207 | | |
208 | | // FastEmit functions for ISD::BITCAST. |
209 | | |
210 | 1 | unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
211 | 1 | if (RetVT.SimpleTy != MVT::f32) |
212 | 0 | return 0; |
213 | 1 | if (1 (Subtarget->hasAVX512())1 ) { |
214 | 0 | return fastEmitInst_r(X86::VMOVDI2SSZrr, &X86::FR32XRegClass, Op0, Op0IsKill); |
215 | 0 | } |
216 | 1 | if (1 (Subtarget->hasSSE2() && 1 !Subtarget->hasAVX()1 )) { |
217 | 1 | return fastEmitInst_r(X86::MOVDI2SSrr, &X86::FR32RegClass, Op0, Op0IsKill); |
218 | 1 | } |
219 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
220 | 0 | return fastEmitInst_r(X86::VMOVDI2SSrr, &X86::FR32RegClass, Op0, Op0IsKill); |
221 | 0 | } |
222 | 0 | return 0; |
223 | 1 | } |
224 | | |
225 | 2 | unsigned fastEmit_ISD_BITCAST_MVT_i64_MVT_f64_r(unsigned Op0, bool Op0IsKill) { |
226 | 2 | if ((Subtarget->hasAVX512())2 ) { |
227 | 0 | return fastEmitInst_r(X86::VMOV64toSDZrr, &X86::FR64XRegClass, Op0, Op0IsKill); |
228 | 0 | } |
229 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
230 | 2 | return fastEmitInst_r(X86::MOV64toSDrr, &X86::FR64RegClass, Op0, Op0IsKill); |
231 | 2 | } |
232 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
233 | 0 | return fastEmitInst_r(X86::VMOV64toSDrr, &X86::FR64RegClass, Op0, Op0IsKill); |
234 | 0 | } |
235 | 0 | return 0; |
236 | 2 | } |
237 | | |
238 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_i64_MVT_x86mmx_r(unsigned Op0, bool Op0IsKill) { |
239 | 0 | if ((Subtarget->hasMMX())0 ) { |
240 | 0 | return fastEmitInst_r(X86::MMX_MOVD64to64rr, &X86::VR64RegClass, Op0, Op0IsKill); |
241 | 0 | } |
242 | 0 | return 0; |
243 | 0 | } |
244 | | |
245 | 2 | unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
246 | 2 | switch (RetVT.SimpleTy) { |
247 | 2 | case MVT::f64: return fastEmit_ISD_BITCAST_MVT_i64_MVT_f64_r(Op0, Op0IsKill); |
248 | 0 | case MVT::x86mmx: return fastEmit_ISD_BITCAST_MVT_i64_MVT_x86mmx_r(Op0, Op0IsKill); |
249 | 0 | default: return 0; |
250 | 2 | } |
251 | 2 | } |
252 | | |
253 | 1 | unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
254 | 1 | if (RetVT.SimpleTy != MVT::i32) |
255 | 0 | return 0; |
256 | 1 | if (1 (Subtarget->hasAVX512())1 ) { |
257 | 0 | return fastEmitInst_r(X86::VMOVSS2DIZrr, &X86::GR32RegClass, Op0, Op0IsKill); |
258 | 0 | } |
259 | 1 | if (1 (Subtarget->hasSSE2() && 1 !Subtarget->hasAVX()1 )) { |
260 | 1 | return fastEmitInst_r(X86::MOVSS2DIrr, &X86::GR32RegClass, Op0, Op0IsKill); |
261 | 1 | } |
262 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
263 | 0 | return fastEmitInst_r(X86::VMOVSS2DIrr, &X86::GR32RegClass, Op0, Op0IsKill); |
264 | 0 | } |
265 | 0 | return 0; |
266 | 1 | } |
267 | | |
268 | 3 | unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) { |
269 | 3 | if ((Subtarget->hasAVX512())3 ) { |
270 | 0 | return fastEmitInst_r(X86::VMOVSDto64Zrr, &X86::GR64RegClass, Op0, Op0IsKill); |
271 | 0 | } |
272 | 3 | if (3 (Subtarget->hasSSE2() && 3 !Subtarget->hasAVX()3 )) { |
273 | 2 | return fastEmitInst_r(X86::MOVSDto64rr, &X86::GR64RegClass, Op0, Op0IsKill); |
274 | 2 | } |
275 | 1 | if (1 (Subtarget->hasAVX() && 1 !Subtarget->hasAVX512()1 )) { |
276 | 1 | return fastEmitInst_r(X86::VMOVSDto64rr, &X86::GR64RegClass, Op0, Op0IsKill); |
277 | 1 | } |
278 | 0 | return 0; |
279 | 3 | } |
280 | | |
281 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_x86mmx_r(unsigned Op0, bool Op0IsKill) { |
282 | 0 | if ((Subtarget->hasSSE2())0 ) { |
283 | 0 | return fastEmitInst_r(X86::MMX_MOVFR642Qrr, &X86::VR64RegClass, Op0, Op0IsKill); |
284 | 0 | } |
285 | 0 | return 0; |
286 | 0 | } |
287 | | |
288 | 3 | unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
289 | 3 | switch (RetVT.SimpleTy) { |
290 | 3 | case MVT::i64: return fastEmit_ISD_BITCAST_MVT_f64_MVT_i64_r(Op0, Op0IsKill); |
291 | 0 | case MVT::x86mmx: return fastEmit_ISD_BITCAST_MVT_f64_MVT_x86mmx_r(Op0, Op0IsKill); |
292 | 0 | default: return 0; |
293 | 3 | } |
294 | 3 | } |
295 | | |
296 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_x86mmx_MVT_i64_r(unsigned Op0, bool Op0IsKill) { |
297 | 0 | if ((Subtarget->hasMMX())0 ) { |
298 | 0 | return fastEmitInst_r(X86::MMX_MOVD64from64rr, &X86::GR64RegClass, Op0, Op0IsKill); |
299 | 0 | } |
300 | 0 | return 0; |
301 | 0 | } |
302 | | |
303 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_x86mmx_MVT_f64_r(unsigned Op0, bool Op0IsKill) { |
304 | 0 | if ((Subtarget->hasSSE2())0 ) { |
305 | 0 | return fastEmitInst_r(X86::MMX_MOVQ2FR64rr, &X86::FR64RegClass, Op0, Op0IsKill); |
306 | 0 | } |
307 | 0 | return 0; |
308 | 0 | } |
309 | | |
310 | | unsigned fastEmit_ISD_BITCAST_MVT_x86mmx_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
311 | | switch (RetVT.SimpleTy) { |
312 | | case MVT::i64: return fastEmit_ISD_BITCAST_MVT_x86mmx_MVT_i64_r(Op0, Op0IsKill); |
313 | | case MVT::f64: return fastEmit_ISD_BITCAST_MVT_x86mmx_MVT_f64_r(Op0, Op0IsKill); |
314 | | default: return 0; |
315 | | } |
316 | | } |
317 | | |
318 | 1.69k | unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
319 | 1.69k | switch (VT.SimpleTy) { |
320 | 1 | case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill); |
321 | 2 | case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill); |
322 | 1 | case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill); |
323 | 3 | case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill); |
324 | 0 | case MVT::x86mmx: return fastEmit_ISD_BITCAST_MVT_x86mmx_r(RetVT, Op0, Op0IsKill); |
325 | 1.69k | default: return 0; |
326 | 1.69k | } |
327 | 1.69k | } |
328 | | |
329 | | // FastEmit functions for ISD::BRIND. |
330 | | |
331 | 0 | unsigned fastEmit_ISD_BRIND_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
332 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
333 | 0 | return 0; |
334 | 0 | if (0 (!Subtarget->is64Bit())0 ) { |
335 | 0 | return fastEmitInst_r(X86::JMP16r, &X86::GR16RegClass, Op0, Op0IsKill); |
336 | 0 | } |
337 | 0 | return 0; |
338 | 0 | } |
339 | | |
340 | 0 | unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
341 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
342 | 0 | return 0; |
343 | 0 | if (0 (!Subtarget->is64Bit())0 ) { |
344 | 0 | return fastEmitInst_r(X86::JMP32r, &X86::GR32RegClass, Op0, Op0IsKill); |
345 | 0 | } |
346 | 0 | return 0; |
347 | 0 | } |
348 | | |
349 | 0 | unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
350 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
351 | 0 | return 0; |
352 | 0 | if (0 (Subtarget->is64Bit())0 ) { |
353 | 0 | return fastEmitInst_r(X86::JMP64r, &X86::GR64RegClass, Op0, Op0IsKill); |
354 | 0 | } |
355 | 0 | return 0; |
356 | 0 | } |
357 | | |
358 | | unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
359 | | switch (VT.SimpleTy) { |
360 | | case MVT::i16: return fastEmit_ISD_BRIND_MVT_i16_r(RetVT, Op0, Op0IsKill); |
361 | | case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill); |
362 | | case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill); |
363 | | default: return 0; |
364 | | } |
365 | | } |
366 | | |
367 | | // FastEmit functions for ISD::BSWAP. |
368 | | |
369 | 0 | unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
370 | 0 | if (RetVT.SimpleTy != MVT::i32) |
371 | 0 | return 0; |
372 | 0 | return fastEmitInst_r(X86::BSWAP32r, &X86::GR32RegClass, Op0, Op0IsKill); |
373 | 0 | } |
374 | | |
375 | 0 | unsigned fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
376 | 0 | if (RetVT.SimpleTy != MVT::i64) |
377 | 0 | return 0; |
378 | 0 | return fastEmitInst_r(X86::BSWAP64r, &X86::GR64RegClass, Op0, Op0IsKill); |
379 | 0 | } |
380 | | |
381 | | unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
382 | | switch (VT.SimpleTy) { |
383 | | case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0, Op0IsKill); |
384 | | case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0, Op0IsKill); |
385 | | default: return 0; |
386 | | } |
387 | | } |
388 | | |
389 | | // FastEmit functions for ISD::CTLZ. |
390 | | |
391 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
392 | 0 | if (RetVT.SimpleTy != MVT::i16) |
393 | 0 | return 0; |
394 | 0 | if (0 (Subtarget->hasLZCNT())0 ) { |
395 | 0 | return fastEmitInst_r(X86::LZCNT16rr, &X86::GR16RegClass, Op0, Op0IsKill); |
396 | 0 | } |
397 | 0 | return 0; |
398 | 0 | } |
399 | | |
400 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
401 | 0 | if (RetVT.SimpleTy != MVT::i32) |
402 | 0 | return 0; |
403 | 0 | if (0 (Subtarget->hasLZCNT())0 ) { |
404 | 0 | return fastEmitInst_r(X86::LZCNT32rr, &X86::GR32RegClass, Op0, Op0IsKill); |
405 | 0 | } |
406 | 0 | return 0; |
407 | 0 | } |
408 | | |
409 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
410 | 0 | if (RetVT.SimpleTy != MVT::i64) |
411 | 0 | return 0; |
412 | 0 | if (0 (Subtarget->hasLZCNT())0 ) { |
413 | 0 | return fastEmitInst_r(X86::LZCNT64rr, &X86::GR64RegClass, Op0, Op0IsKill); |
414 | 0 | } |
415 | 0 | return 0; |
416 | 0 | } |
417 | | |
418 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
419 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
420 | 0 | return 0; |
421 | 0 | if (0 (Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
422 | 0 | return fastEmitInst_r(X86::VPLZCNTDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
423 | 0 | } |
424 | 0 | return 0; |
425 | 0 | } |
426 | | |
427 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
428 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
429 | 0 | return 0; |
430 | 0 | if (0 (Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
431 | 0 | return fastEmitInst_r(X86::VPLZCNTDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
432 | 0 | } |
433 | 0 | return 0; |
434 | 0 | } |
435 | | |
436 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
437 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
438 | 0 | return 0; |
439 | 0 | if (0 (Subtarget->hasCDI())0 ) { |
440 | 0 | return fastEmitInst_r(X86::VPLZCNTDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
441 | 0 | } |
442 | 0 | return 0; |
443 | 0 | } |
444 | | |
445 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
446 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
447 | 0 | return 0; |
448 | 0 | if (0 (Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
449 | 0 | return fastEmitInst_r(X86::VPLZCNTQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
450 | 0 | } |
451 | 0 | return 0; |
452 | 0 | } |
453 | | |
454 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v4i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
455 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
456 | 0 | return 0; |
457 | 0 | if (0 (Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
458 | 0 | return fastEmitInst_r(X86::VPLZCNTQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
459 | 0 | } |
460 | 0 | return 0; |
461 | 0 | } |
462 | | |
463 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
464 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
465 | 0 | return 0; |
466 | 0 | if (0 (Subtarget->hasCDI())0 ) { |
467 | 0 | return fastEmitInst_r(X86::VPLZCNTQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
468 | 0 | } |
469 | 0 | return 0; |
470 | 0 | } |
471 | | |
472 | | unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
473 | | switch (VT.SimpleTy) { |
474 | | case MVT::i16: return fastEmit_ISD_CTLZ_MVT_i16_r(RetVT, Op0, Op0IsKill); |
475 | | case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill); |
476 | | case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill); |
477 | | case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
478 | | case MVT::v8i32: return fastEmit_ISD_CTLZ_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
479 | | case MVT::v16i32: return fastEmit_ISD_CTLZ_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
480 | | case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
481 | | case MVT::v4i64: return fastEmit_ISD_CTLZ_MVT_v4i64_r(RetVT, Op0, Op0IsKill); |
482 | | case MVT::v8i64: return fastEmit_ISD_CTLZ_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
483 | | default: return 0; |
484 | | } |
485 | | } |
486 | | |
487 | | // FastEmit functions for ISD::CTPOP. |
488 | | |
489 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
490 | 0 | if (RetVT.SimpleTy != MVT::i16) |
491 | 0 | return 0; |
492 | 0 | if (0 (Subtarget->hasPOPCNT())0 ) { |
493 | 0 | return fastEmitInst_r(X86::POPCNT16rr, &X86::GR16RegClass, Op0, Op0IsKill); |
494 | 0 | } |
495 | 0 | return 0; |
496 | 0 | } |
497 | | |
498 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
499 | 0 | if (RetVT.SimpleTy != MVT::i32) |
500 | 0 | return 0; |
501 | 0 | if (0 (Subtarget->hasPOPCNT())0 ) { |
502 | 0 | return fastEmitInst_r(X86::POPCNT32rr, &X86::GR32RegClass, Op0, Op0IsKill); |
503 | 0 | } |
504 | 0 | return 0; |
505 | 0 | } |
506 | | |
507 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
508 | 0 | if (RetVT.SimpleTy != MVT::i64) |
509 | 0 | return 0; |
510 | 0 | if (0 (Subtarget->hasPOPCNT())0 ) { |
511 | 0 | return fastEmitInst_r(X86::POPCNT64rr, &X86::GR64RegClass, Op0, Op0IsKill); |
512 | 0 | } |
513 | 0 | return 0; |
514 | 0 | } |
515 | | |
516 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
517 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
518 | 0 | return 0; |
519 | 0 | if (0 (Subtarget->hasVPOPCNTDQ())0 ) { |
520 | 0 | return fastEmitInst_r(X86::VPOPCNTDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
521 | 0 | } |
522 | 0 | return 0; |
523 | 0 | } |
524 | | |
525 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
526 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
527 | 0 | return 0; |
528 | 0 | if (0 (Subtarget->hasVPOPCNTDQ())0 ) { |
529 | 0 | return fastEmitInst_r(X86::VPOPCNTQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
530 | 0 | } |
531 | 0 | return 0; |
532 | 0 | } |
533 | | |
534 | | unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
535 | | switch (VT.SimpleTy) { |
536 | | case MVT::i16: return fastEmit_ISD_CTPOP_MVT_i16_r(RetVT, Op0, Op0IsKill); |
537 | | case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill); |
538 | | case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill); |
539 | | case MVT::v16i32: return fastEmit_ISD_CTPOP_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
540 | | case MVT::v8i64: return fastEmit_ISD_CTPOP_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
541 | | default: return 0; |
542 | | } |
543 | | } |
544 | | |
545 | | // FastEmit functions for ISD::CTTZ. |
546 | | |
547 | 0 | unsigned fastEmit_ISD_CTTZ_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
548 | 0 | if (RetVT.SimpleTy != MVT::i16) |
549 | 0 | return 0; |
550 | 0 | if (0 (Subtarget->hasBMI())0 ) { |
551 | 0 | return fastEmitInst_r(X86::TZCNT16rr, &X86::GR16RegClass, Op0, Op0IsKill); |
552 | 0 | } |
553 | 0 | return 0; |
554 | 0 | } |
555 | | |
556 | 0 | unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
557 | 0 | if (RetVT.SimpleTy != MVT::i32) |
558 | 0 | return 0; |
559 | 0 | if (0 (Subtarget->hasBMI())0 ) { |
560 | 0 | return fastEmitInst_r(X86::TZCNT32rr, &X86::GR32RegClass, Op0, Op0IsKill); |
561 | 0 | } |
562 | 0 | return 0; |
563 | 0 | } |
564 | | |
565 | 0 | unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
566 | 0 | if (RetVT.SimpleTy != MVT::i64) |
567 | 0 | return 0; |
568 | 0 | if (0 (Subtarget->hasBMI())0 ) { |
569 | 0 | return fastEmitInst_r(X86::TZCNT64rr, &X86::GR64RegClass, Op0, Op0IsKill); |
570 | 0 | } |
571 | 0 | return 0; |
572 | 0 | } |
573 | | |
574 | | unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
575 | | switch (VT.SimpleTy) { |
576 | | case MVT::i16: return fastEmit_ISD_CTTZ_MVT_i16_r(RetVT, Op0, Op0IsKill); |
577 | | case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0, Op0IsKill); |
578 | | case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0, Op0IsKill); |
579 | | default: return 0; |
580 | | } |
581 | | } |
582 | | |
583 | | // FastEmit functions for ISD::CTTZ_ZERO_UNDEF. |
584 | | |
585 | 0 | unsigned fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
586 | 0 | if (RetVT.SimpleTy != MVT::i16) |
587 | 0 | return 0; |
588 | 0 | return fastEmitInst_r(X86::BSF16rr, &X86::GR16RegClass, Op0, Op0IsKill); |
589 | 0 | } |
590 | | |
591 | 0 | unsigned fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
592 | 0 | if (RetVT.SimpleTy != MVT::i32) |
593 | 0 | return 0; |
594 | 0 | return fastEmitInst_r(X86::BSF32rr, &X86::GR32RegClass, Op0, Op0IsKill); |
595 | 0 | } |
596 | | |
597 | 0 | unsigned fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
598 | 0 | if (RetVT.SimpleTy != MVT::i64) |
599 | 0 | return 0; |
600 | 0 | return fastEmitInst_r(X86::BSF64rr, &X86::GR64RegClass, Op0, Op0IsKill); |
601 | 0 | } |
602 | | |
603 | | unsigned fastEmit_ISD_CTTZ_ZERO_UNDEF_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
604 | | switch (VT.SimpleTy) { |
605 | | case MVT::i16: return fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i16_r(RetVT, Op0, Op0IsKill); |
606 | | case MVT::i32: return fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i32_r(RetVT, Op0, Op0IsKill); |
607 | | case MVT::i64: return fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i64_r(RetVT, Op0, Op0IsKill); |
608 | | default: return 0; |
609 | | } |
610 | | } |
611 | | |
612 | | // FastEmit functions for ISD::FABS. |
613 | | |
614 | 0 | unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
615 | 0 | if (RetVT.SimpleTy != MVT::f32) |
616 | 0 | return 0; |
617 | 0 | if (0 (!Subtarget->hasSSE1())0 ) { |
618 | 0 | return fastEmitInst_r(X86::ABS_Fp32, &X86::RFP32RegClass, Op0, Op0IsKill); |
619 | 0 | } |
620 | 0 | return 0; |
621 | 0 | } |
622 | | |
623 | 0 | unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
624 | 0 | if (RetVT.SimpleTy != MVT::f64) |
625 | 0 | return 0; |
626 | 0 | if (0 (!Subtarget->hasSSE2())0 ) { |
627 | 0 | return fastEmitInst_r(X86::ABS_Fp64, &X86::RFP64RegClass, Op0, Op0IsKill); |
628 | 0 | } |
629 | 0 | return 0; |
630 | 0 | } |
631 | | |
632 | 0 | unsigned fastEmit_ISD_FABS_MVT_f80_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
633 | 0 | if (RetVT.SimpleTy != MVT::f80) |
634 | 0 | return 0; |
635 | 0 | return fastEmitInst_r(X86::ABS_Fp80, &X86::RFP80RegClass, Op0, Op0IsKill); |
636 | 0 | } |
637 | | |
638 | | unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
639 | | switch (VT.SimpleTy) { |
640 | | case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill); |
641 | | case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill); |
642 | | case MVT::f80: return fastEmit_ISD_FABS_MVT_f80_r(RetVT, Op0, Op0IsKill); |
643 | | default: return 0; |
644 | | } |
645 | | } |
646 | | |
647 | | // FastEmit functions for ISD::FCOS. |
648 | | |
649 | 0 | unsigned fastEmit_ISD_FCOS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
650 | 0 | if (RetVT.SimpleTy != MVT::f32) |
651 | 0 | return 0; |
652 | 0 | if (0 (!Subtarget->hasSSE1())0 ) { |
653 | 0 | return fastEmitInst_r(X86::COS_Fp32, &X86::RFP32RegClass, Op0, Op0IsKill); |
654 | 0 | } |
655 | 0 | return 0; |
656 | 0 | } |
657 | | |
658 | 0 | unsigned fastEmit_ISD_FCOS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
659 | 0 | if (RetVT.SimpleTy != MVT::f64) |
660 | 0 | return 0; |
661 | 0 | if (0 (!Subtarget->hasSSE2())0 ) { |
662 | 0 | return fastEmitInst_r(X86::COS_Fp64, &X86::RFP64RegClass, Op0, Op0IsKill); |
663 | 0 | } |
664 | 0 | return 0; |
665 | 0 | } |
666 | | |
667 | 0 | unsigned fastEmit_ISD_FCOS_MVT_f80_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
668 | 0 | if (RetVT.SimpleTy != MVT::f80) |
669 | 0 | return 0; |
670 | 0 | return fastEmitInst_r(X86::COS_Fp80, &X86::RFP80RegClass, Op0, Op0IsKill); |
671 | 0 | } |
672 | | |
673 | | unsigned fastEmit_ISD_FCOS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
674 | | switch (VT.SimpleTy) { |
675 | | case MVT::f32: return fastEmit_ISD_FCOS_MVT_f32_r(RetVT, Op0, Op0IsKill); |
676 | | case MVT::f64: return fastEmit_ISD_FCOS_MVT_f64_r(RetVT, Op0, Op0IsKill); |
677 | | case MVT::f80: return fastEmit_ISD_FCOS_MVT_f80_r(RetVT, Op0, Op0IsKill); |
678 | | default: return 0; |
679 | | } |
680 | | } |
681 | | |
682 | | // FastEmit functions for ISD::FNEG. |
683 | | |
684 | 1 | unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
685 | 1 | if (RetVT.SimpleTy != MVT::f32) |
686 | 0 | return 0; |
687 | 1 | if (1 (!Subtarget->hasSSE1())1 ) { |
688 | 0 | return fastEmitInst_r(X86::CHS_Fp32, &X86::RFP32RegClass, Op0, Op0IsKill); |
689 | 0 | } |
690 | 1 | return 0; |
691 | 1 | } |
692 | | |
693 | 2 | unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
694 | 2 | if (RetVT.SimpleTy != MVT::f64) |
695 | 0 | return 0; |
696 | 2 | if (2 (!Subtarget->hasSSE2())2 ) { |
697 | 0 | return fastEmitInst_r(X86::CHS_Fp64, &X86::RFP64RegClass, Op0, Op0IsKill); |
698 | 0 | } |
699 | 2 | return 0; |
700 | 2 | } |
701 | | |
702 | 0 | unsigned fastEmit_ISD_FNEG_MVT_f80_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
703 | 0 | if (RetVT.SimpleTy != MVT::f80) |
704 | 0 | return 0; |
705 | 0 | return fastEmitInst_r(X86::CHS_Fp80, &X86::RFP80RegClass, Op0, Op0IsKill); |
706 | 0 | } |
707 | | |
708 | 3 | unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
709 | 3 | switch (VT.SimpleTy) { |
710 | 1 | case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill); |
711 | 2 | case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill); |
712 | 0 | case MVT::f80: return fastEmit_ISD_FNEG_MVT_f80_r(RetVT, Op0, Op0IsKill); |
713 | 0 | default: return 0; |
714 | 3 | } |
715 | 3 | } |
716 | | |
717 | | // FastEmit functions for ISD::FP_EXTEND. |
718 | | |
719 | 0 | unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
720 | 0 | if (RetVT.SimpleTy != MVT::f64) |
721 | 0 | return 0; |
722 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
723 | 0 | return fastEmitInst_r(X86::CVTSS2SDrr, &X86::FR64RegClass, Op0, Op0IsKill); |
724 | 0 | } |
725 | 0 | return 0; |
726 | 0 | } |
727 | | |
728 | 0 | unsigned fastEmit_ISD_FP_EXTEND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
729 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
730 | 0 | return 0; |
731 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
732 | 0 | return fastEmitInst_r(X86::VCVTPS2PDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
733 | 0 | } |
734 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
735 | 0 | return fastEmitInst_r(X86::VCVTPS2PDYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
736 | 0 | } |
737 | 0 | return 0; |
738 | 0 | } |
739 | | |
740 | 0 | unsigned fastEmit_ISD_FP_EXTEND_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
741 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
742 | 0 | return 0; |
743 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
744 | 0 | return fastEmitInst_r(X86::VCVTPS2PDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
745 | 0 | } |
746 | 0 | return 0; |
747 | 0 | } |
748 | | |
749 | | unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
750 | | switch (VT.SimpleTy) { |
751 | | case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill); |
752 | | case MVT::v4f32: return fastEmit_ISD_FP_EXTEND_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
753 | | case MVT::v8f32: return fastEmit_ISD_FP_EXTEND_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
754 | | default: return 0; |
755 | | } |
756 | | } |
757 | | |
758 | | // FastEmit functions for ISD::FP_ROUND. |
759 | | |
760 | 0 | unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
761 | 0 | if (RetVT.SimpleTy != MVT::f32) |
762 | 0 | return 0; |
763 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
764 | 0 | return fastEmitInst_r(X86::CVTSD2SSrr, &X86::FR32RegClass, Op0, Op0IsKill); |
765 | 0 | } |
766 | 0 | return 0; |
767 | 0 | } |
768 | | |
769 | 0 | unsigned fastEmit_ISD_FP_ROUND_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
770 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
771 | 0 | return 0; |
772 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
773 | 0 | return fastEmitInst_r(X86::VCVTPD2PSZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
774 | 0 | } |
775 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
776 | 0 | return fastEmitInst_r(X86::VCVTPD2PSYrr, &X86::VR128RegClass, Op0, Op0IsKill); |
777 | 0 | } |
778 | 0 | return 0; |
779 | 0 | } |
780 | | |
781 | 0 | unsigned fastEmit_ISD_FP_ROUND_MVT_v8f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
782 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
783 | 0 | return 0; |
784 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
785 | 0 | return fastEmitInst_r(X86::VCVTPD2PSZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
786 | 0 | } |
787 | 0 | return 0; |
788 | 0 | } |
789 | | |
790 | | unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
791 | | switch (VT.SimpleTy) { |
792 | | case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); |
793 | | case MVT::v4f64: return fastEmit_ISD_FP_ROUND_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
794 | | case MVT::v8f64: return fastEmit_ISD_FP_ROUND_MVT_v8f64_r(RetVT, Op0, Op0IsKill); |
795 | | default: return 0; |
796 | | } |
797 | | } |
798 | | |
799 | | // FastEmit functions for ISD::FP_TO_SINT. |
800 | | |
801 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0, bool Op0IsKill) { |
802 | 0 | if ((Subtarget->hasAVX512())0 ) { |
803 | 0 | return fastEmitInst_r(X86::VCVTTSS2SIZrr, &X86::GR32RegClass, Op0, Op0IsKill); |
804 | 0 | } |
805 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
806 | 0 | return fastEmitInst_r(X86::CVTTSS2SIrr, &X86::GR32RegClass, Op0, Op0IsKill); |
807 | 0 | } |
808 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
809 | 0 | return fastEmitInst_r(X86::VCVTTSS2SIrr, &X86::GR32RegClass, Op0, Op0IsKill); |
810 | 0 | } |
811 | 0 | return 0; |
812 | 0 | } |
813 | | |
814 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0, bool Op0IsKill) { |
815 | 0 | if ((Subtarget->hasAVX512())0 ) { |
816 | 0 | return fastEmitInst_r(X86::VCVTTSS2SI64Zrr, &X86::GR64RegClass, Op0, Op0IsKill); |
817 | 0 | } |
818 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
819 | 0 | return fastEmitInst_r(X86::CVTTSS2SI64rr, &X86::GR64RegClass, Op0, Op0IsKill); |
820 | 0 | } |
821 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
822 | 0 | return fastEmitInst_r(X86::VCVTTSS2SI64rr, &X86::GR64RegClass, Op0, Op0IsKill); |
823 | 0 | } |
824 | 0 | return 0; |
825 | 0 | } |
826 | | |
827 | | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
828 | | switch (RetVT.SimpleTy) { |
829 | | case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0, Op0IsKill); |
830 | | case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0, Op0IsKill); |
831 | | default: return 0; |
832 | | } |
833 | | } |
834 | | |
835 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) { |
836 | 0 | if ((Subtarget->hasAVX512())0 ) { |
837 | 0 | return fastEmitInst_r(X86::VCVTTSD2SIZrr, &X86::GR32RegClass, Op0, Op0IsKill); |
838 | 0 | } |
839 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
840 | 0 | return fastEmitInst_r(X86::CVTTSD2SIrr, &X86::GR32RegClass, Op0, Op0IsKill); |
841 | 0 | } |
842 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
843 | 0 | return fastEmitInst_r(X86::VCVTTSD2SIrr, &X86::GR32RegClass, Op0, Op0IsKill); |
844 | 0 | } |
845 | 0 | return 0; |
846 | 0 | } |
847 | | |
848 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) { |
849 | 0 | if ((Subtarget->hasAVX512())0 ) { |
850 | 0 | return fastEmitInst_r(X86::VCVTTSD2SI64Zrr, &X86::GR64RegClass, Op0, Op0IsKill); |
851 | 0 | } |
852 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
853 | 0 | return fastEmitInst_r(X86::CVTTSD2SI64rr, &X86::GR64RegClass, Op0, Op0IsKill); |
854 | 0 | } |
855 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
856 | 0 | return fastEmitInst_r(X86::VCVTTSD2SI64rr, &X86::GR64RegClass, Op0, Op0IsKill); |
857 | 0 | } |
858 | 0 | return 0; |
859 | 0 | } |
860 | | |
861 | | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
862 | | switch (RetVT.SimpleTy) { |
863 | | case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0, Op0IsKill); |
864 | | case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0, Op0IsKill); |
865 | | default: return 0; |
866 | | } |
867 | | } |
868 | | |
869 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
870 | 0 | if ((Subtarget->hasVLX())0 ) { |
871 | 0 | return fastEmitInst_r(X86::VCVTTPS2DQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
872 | 0 | } |
873 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
874 | 0 | return fastEmitInst_r(X86::CVTTPS2DQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
875 | 0 | } |
876 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
877 | 0 | return fastEmitInst_r(X86::VCVTTPS2DQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
878 | 0 | } |
879 | 0 | return 0; |
880 | 0 | } |
881 | | |
882 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
883 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
884 | 0 | return fastEmitInst_r(X86::VCVTTPS2QQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
885 | 0 | } |
886 | 0 | return 0; |
887 | 0 | } |
888 | | |
889 | | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
890 | | switch (RetVT.SimpleTy) { |
891 | | case MVT::v4i32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_MVT_v4i32_r(Op0, Op0IsKill); |
892 | | case MVT::v4i64: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_MVT_v4i64_r(Op0, Op0IsKill); |
893 | | default: return 0; |
894 | | } |
895 | | } |
896 | | |
897 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f32_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
898 | 0 | if ((Subtarget->hasVLX())0 ) { |
899 | 0 | return fastEmitInst_r(X86::VCVTTPS2DQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
900 | 0 | } |
901 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
902 | 0 | return fastEmitInst_r(X86::VCVTTPS2DQYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
903 | 0 | } |
904 | 0 | return 0; |
905 | 0 | } |
906 | | |
907 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f32_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
908 | 0 | if ((Subtarget->hasDQI())0 ) { |
909 | 0 | return fastEmitInst_r(X86::VCVTTPS2QQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
910 | 0 | } |
911 | 0 | return 0; |
912 | 0 | } |
913 | | |
914 | | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
915 | | switch (RetVT.SimpleTy) { |
916 | | case MVT::v8i32: return fastEmit_ISD_FP_TO_SINT_MVT_v8f32_MVT_v8i32_r(Op0, Op0IsKill); |
917 | | case MVT::v8i64: return fastEmit_ISD_FP_TO_SINT_MVT_v8f32_MVT_v8i64_r(Op0, Op0IsKill); |
918 | | default: return 0; |
919 | | } |
920 | | } |
921 | | |
922 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v16f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
923 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
924 | 0 | return 0; |
925 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
926 | 0 | return fastEmitInst_r(X86::VCVTTPS2DQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
927 | 0 | } |
928 | 0 | return 0; |
929 | 0 | } |
930 | | |
931 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
932 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
933 | 0 | return 0; |
934 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
935 | 0 | return fastEmitInst_r(X86::VCVTTPD2QQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
936 | 0 | } |
937 | 0 | return 0; |
938 | 0 | } |
939 | | |
940 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
941 | 0 | if ((Subtarget->hasVLX())0 ) { |
942 | 0 | return fastEmitInst_r(X86::VCVTTPD2DQZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
943 | 0 | } |
944 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
945 | 0 | return fastEmitInst_r(X86::VCVTTPD2DQYrr, &X86::VR128RegClass, Op0, Op0IsKill); |
946 | 0 | } |
947 | 0 | return 0; |
948 | 0 | } |
949 | | |
950 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f64_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
951 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
952 | 0 | return fastEmitInst_r(X86::VCVTTPD2QQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
953 | 0 | } |
954 | 0 | return 0; |
955 | 0 | } |
956 | | |
957 | | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
958 | | switch (RetVT.SimpleTy) { |
959 | | case MVT::v4i32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f64_MVT_v4i32_r(Op0, Op0IsKill); |
960 | | case MVT::v4i64: return fastEmit_ISD_FP_TO_SINT_MVT_v4f64_MVT_v4i64_r(Op0, Op0IsKill); |
961 | | default: return 0; |
962 | | } |
963 | | } |
964 | | |
965 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f64_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
966 | 0 | if ((Subtarget->hasAVX512())0 ) { |
967 | 0 | return fastEmitInst_r(X86::VCVTTPD2DQZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
968 | 0 | } |
969 | 0 | return 0; |
970 | 0 | } |
971 | | |
972 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f64_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
973 | 0 | if ((Subtarget->hasDQI())0 ) { |
974 | 0 | return fastEmitInst_r(X86::VCVTTPD2QQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
975 | 0 | } |
976 | 0 | return 0; |
977 | 0 | } |
978 | | |
979 | | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
980 | | switch (RetVT.SimpleTy) { |
981 | | case MVT::v8i32: return fastEmit_ISD_FP_TO_SINT_MVT_v8f64_MVT_v8i32_r(Op0, Op0IsKill); |
982 | | case MVT::v8i64: return fastEmit_ISD_FP_TO_SINT_MVT_v8f64_MVT_v8i64_r(Op0, Op0IsKill); |
983 | | default: return 0; |
984 | | } |
985 | | } |
986 | | |
987 | | unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
988 | | switch (VT.SimpleTy) { |
989 | | case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0, Op0IsKill); |
990 | | case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0, Op0IsKill); |
991 | | case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
992 | | case MVT::v8f32: return fastEmit_ISD_FP_TO_SINT_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
993 | | case MVT::v16f32: return fastEmit_ISD_FP_TO_SINT_MVT_v16f32_r(RetVT, Op0, Op0IsKill); |
994 | | case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
995 | | case MVT::v4f64: return fastEmit_ISD_FP_TO_SINT_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
996 | | case MVT::v8f64: return fastEmit_ISD_FP_TO_SINT_MVT_v8f64_r(RetVT, Op0, Op0IsKill); |
997 | | default: return 0; |
998 | | } |
999 | | } |
1000 | | |
1001 | | // FastEmit functions for ISD::FP_TO_UINT. |
1002 | | |
1003 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(unsigned Op0, bool Op0IsKill) { |
1004 | 0 | if ((Subtarget->hasAVX512())0 ) { |
1005 | 0 | return fastEmitInst_r(X86::VCVTTSS2USIZrr, &X86::GR32RegClass, Op0, Op0IsKill); |
1006 | 0 | } |
1007 | 0 | return 0; |
1008 | 0 | } |
1009 | | |
1010 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(unsigned Op0, bool Op0IsKill) { |
1011 | 0 | if ((Subtarget->hasAVX512())0 ) { |
1012 | 0 | return fastEmitInst_r(X86::VCVTTSS2USI64Zrr, &X86::GR64RegClass, Op0, Op0IsKill); |
1013 | 0 | } |
1014 | 0 | return 0; |
1015 | 0 | } |
1016 | | |
1017 | | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1018 | | switch (RetVT.SimpleTy) { |
1019 | | case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0, Op0IsKill); |
1020 | | case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0, Op0IsKill); |
1021 | | default: return 0; |
1022 | | } |
1023 | | } |
1024 | | |
1025 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) { |
1026 | 0 | if ((Subtarget->hasAVX512())0 ) { |
1027 | 0 | return fastEmitInst_r(X86::VCVTTSD2USIZrr, &X86::GR32RegClass, Op0, Op0IsKill); |
1028 | 0 | } |
1029 | 0 | return 0; |
1030 | 0 | } |
1031 | | |
1032 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) { |
1033 | 0 | if ((Subtarget->hasAVX512())0 ) { |
1034 | 0 | return fastEmitInst_r(X86::VCVTTSD2USI64Zrr, &X86::GR64RegClass, Op0, Op0IsKill); |
1035 | 0 | } |
1036 | 0 | return 0; |
1037 | 0 | } |
1038 | | |
1039 | | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1040 | | switch (RetVT.SimpleTy) { |
1041 | | case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0, Op0IsKill); |
1042 | | case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0, Op0IsKill); |
1043 | | default: return 0; |
1044 | | } |
1045 | | } |
1046 | | |
1047 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
1048 | 0 | if ((Subtarget->hasVLX())0 ) { |
1049 | 0 | return fastEmitInst_r(X86::VCVTTPS2UDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1050 | 0 | } |
1051 | 0 | return 0; |
1052 | 0 | } |
1053 | | |
1054 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
1055 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
1056 | 0 | return fastEmitInst_r(X86::VCVTTPS2UQQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1057 | 0 | } |
1058 | 0 | return 0; |
1059 | 0 | } |
1060 | | |
1061 | | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1062 | | switch (RetVT.SimpleTy) { |
1063 | | case MVT::v4i32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_MVT_v4i32_r(Op0, Op0IsKill); |
1064 | | case MVT::v4i64: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_MVT_v4i64_r(Op0, Op0IsKill); |
1065 | | default: return 0; |
1066 | | } |
1067 | | } |
1068 | | |
1069 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f32_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
1070 | 0 | if ((Subtarget->hasVLX())0 ) { |
1071 | 0 | return fastEmitInst_r(X86::VCVTTPS2UDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1072 | 0 | } |
1073 | 0 | return 0; |
1074 | 0 | } |
1075 | | |
1076 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f32_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
1077 | 0 | if ((Subtarget->hasDQI())0 ) { |
1078 | 0 | return fastEmitInst_r(X86::VCVTTPS2UQQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
1079 | 0 | } |
1080 | 0 | return 0; |
1081 | 0 | } |
1082 | | |
1083 | | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1084 | | switch (RetVT.SimpleTy) { |
1085 | | case MVT::v8i32: return fastEmit_ISD_FP_TO_UINT_MVT_v8f32_MVT_v8i32_r(Op0, Op0IsKill); |
1086 | | case MVT::v8i64: return fastEmit_ISD_FP_TO_UINT_MVT_v8f32_MVT_v8i64_r(Op0, Op0IsKill); |
1087 | | default: return 0; |
1088 | | } |
1089 | | } |
1090 | | |
1091 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v16f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1092 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
1093 | 0 | return 0; |
1094 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
1095 | 0 | return fastEmitInst_r(X86::VCVTTPS2UDQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
1096 | 0 | } |
1097 | 0 | return 0; |
1098 | 0 | } |
1099 | | |
1100 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1101 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
1102 | 0 | return 0; |
1103 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
1104 | 0 | return fastEmitInst_r(X86::VCVTTPD2UQQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1105 | 0 | } |
1106 | 0 | return 0; |
1107 | 0 | } |
1108 | | |
1109 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
1110 | 0 | if ((Subtarget->hasVLX())0 ) { |
1111 | 0 | return fastEmitInst_r(X86::VCVTTPD2UDQZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1112 | 0 | } |
1113 | 0 | return 0; |
1114 | 0 | } |
1115 | | |
1116 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f64_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
1117 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
1118 | 0 | return fastEmitInst_r(X86::VCVTTPD2UQQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1119 | 0 | } |
1120 | 0 | return 0; |
1121 | 0 | } |
1122 | | |
1123 | | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1124 | | switch (RetVT.SimpleTy) { |
1125 | | case MVT::v4i32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f64_MVT_v4i32_r(Op0, Op0IsKill); |
1126 | | case MVT::v4i64: return fastEmit_ISD_FP_TO_UINT_MVT_v4f64_MVT_v4i64_r(Op0, Op0IsKill); |
1127 | | default: return 0; |
1128 | | } |
1129 | | } |
1130 | | |
1131 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f64_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
1132 | 0 | if ((Subtarget->hasAVX512())0 ) { |
1133 | 0 | return fastEmitInst_r(X86::VCVTTPD2UDQZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1134 | 0 | } |
1135 | 0 | return 0; |
1136 | 0 | } |
1137 | | |
1138 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f64_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
1139 | 0 | if ((Subtarget->hasDQI())0 ) { |
1140 | 0 | return fastEmitInst_r(X86::VCVTTPD2UQQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
1141 | 0 | } |
1142 | 0 | return 0; |
1143 | 0 | } |
1144 | | |
1145 | | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1146 | | switch (RetVT.SimpleTy) { |
1147 | | case MVT::v8i32: return fastEmit_ISD_FP_TO_UINT_MVT_v8f64_MVT_v8i32_r(Op0, Op0IsKill); |
1148 | | case MVT::v8i64: return fastEmit_ISD_FP_TO_UINT_MVT_v8f64_MVT_v8i64_r(Op0, Op0IsKill); |
1149 | | default: return 0; |
1150 | | } |
1151 | | } |
1152 | | |
1153 | | unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1154 | | switch (VT.SimpleTy) { |
1155 | | case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0, Op0IsKill); |
1156 | | case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0, Op0IsKill); |
1157 | | case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
1158 | | case MVT::v8f32: return fastEmit_ISD_FP_TO_UINT_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
1159 | | case MVT::v16f32: return fastEmit_ISD_FP_TO_UINT_MVT_v16f32_r(RetVT, Op0, Op0IsKill); |
1160 | | case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
1161 | | case MVT::v4f64: return fastEmit_ISD_FP_TO_UINT_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
1162 | | case MVT::v8f64: return fastEmit_ISD_FP_TO_UINT_MVT_v8f64_r(RetVT, Op0, Op0IsKill); |
1163 | | default: return 0; |
1164 | | } |
1165 | | } |
1166 | | |
1167 | | // FastEmit functions for ISD::FSIN. |
1168 | | |
1169 | 0 | unsigned fastEmit_ISD_FSIN_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1170 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1171 | 0 | return 0; |
1172 | 0 | if (0 (!Subtarget->hasSSE1())0 ) { |
1173 | 0 | return fastEmitInst_r(X86::SIN_Fp32, &X86::RFP32RegClass, Op0, Op0IsKill); |
1174 | 0 | } |
1175 | 0 | return 0; |
1176 | 0 | } |
1177 | | |
1178 | 0 | unsigned fastEmit_ISD_FSIN_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1179 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1180 | 0 | return 0; |
1181 | 0 | if (0 (!Subtarget->hasSSE2())0 ) { |
1182 | 0 | return fastEmitInst_r(X86::SIN_Fp64, &X86::RFP64RegClass, Op0, Op0IsKill); |
1183 | 0 | } |
1184 | 0 | return 0; |
1185 | 0 | } |
1186 | | |
1187 | 0 | unsigned fastEmit_ISD_FSIN_MVT_f80_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1188 | 0 | if (RetVT.SimpleTy != MVT::f80) |
1189 | 0 | return 0; |
1190 | 0 | return fastEmitInst_r(X86::SIN_Fp80, &X86::RFP80RegClass, Op0, Op0IsKill); |
1191 | 0 | } |
1192 | | |
1193 | | unsigned fastEmit_ISD_FSIN_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1194 | | switch (VT.SimpleTy) { |
1195 | | case MVT::f32: return fastEmit_ISD_FSIN_MVT_f32_r(RetVT, Op0, Op0IsKill); |
1196 | | case MVT::f64: return fastEmit_ISD_FSIN_MVT_f64_r(RetVT, Op0, Op0IsKill); |
1197 | | case MVT::f80: return fastEmit_ISD_FSIN_MVT_f80_r(RetVT, Op0, Op0IsKill); |
1198 | | default: return 0; |
1199 | | } |
1200 | | } |
1201 | | |
1202 | | // FastEmit functions for ISD::FSQRT. |
1203 | | |
1204 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1205 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1206 | 0 | return 0; |
1207 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
1208 | 0 | return fastEmitInst_r(X86::SQRTSSr, &X86::FR32RegClass, Op0, Op0IsKill); |
1209 | 0 | } |
1210 | 0 | if (0 (!Subtarget->hasSSE1())0 ) { |
1211 | 0 | return fastEmitInst_r(X86::SQRT_Fp32, &X86::RFP32RegClass, Op0, Op0IsKill); |
1212 | 0 | } |
1213 | 0 | return 0; |
1214 | 0 | } |
1215 | | |
1216 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1217 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1218 | 0 | return 0; |
1219 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
1220 | 0 | return fastEmitInst_r(X86::SQRTSDr, &X86::FR64RegClass, Op0, Op0IsKill); |
1221 | 0 | } |
1222 | 0 | if (0 (!Subtarget->hasSSE2())0 ) { |
1223 | 0 | return fastEmitInst_r(X86::SQRT_Fp64, &X86::RFP64RegClass, Op0, Op0IsKill); |
1224 | 0 | } |
1225 | 0 | return 0; |
1226 | 0 | } |
1227 | | |
1228 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_f80_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1229 | 0 | if (RetVT.SimpleTy != MVT::f80) |
1230 | 0 | return 0; |
1231 | 0 | return fastEmitInst_r(X86::SQRT_Fp80, &X86::RFP80RegClass, Op0, Op0IsKill); |
1232 | 0 | } |
1233 | | |
1234 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1235 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1236 | 0 | return 0; |
1237 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
1238 | 0 | return fastEmitInst_r(X86::VSQRTPSZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
1239 | 0 | } |
1240 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
1241 | 0 | return fastEmitInst_r(X86::SQRTPSr, &X86::VR128RegClass, Op0, Op0IsKill); |
1242 | 0 | } |
1243 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
1244 | 0 | return fastEmitInst_r(X86::VSQRTPSr, &X86::VR128RegClass, Op0, Op0IsKill); |
1245 | 0 | } |
1246 | 0 | return 0; |
1247 | 0 | } |
1248 | | |
1249 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1250 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
1251 | 0 | return 0; |
1252 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
1253 | 0 | return fastEmitInst_r(X86::VSQRTPSZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
1254 | 0 | } |
1255 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
1256 | 0 | return fastEmitInst_r(X86::VSQRTPSYr, &X86::VR256RegClass, Op0, Op0IsKill); |
1257 | 0 | } |
1258 | 0 | return 0; |
1259 | 0 | } |
1260 | | |
1261 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v16f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1262 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
1263 | 0 | return 0; |
1264 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
1265 | 0 | return fastEmitInst_r(X86::VSQRTPSZr, &X86::VR512RegClass, Op0, Op0IsKill); |
1266 | 0 | } |
1267 | 0 | return 0; |
1268 | 0 | } |
1269 | | |
1270 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1271 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1272 | 0 | return 0; |
1273 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
1274 | 0 | return fastEmitInst_r(X86::VSQRTPDZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
1275 | 0 | } |
1276 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
1277 | 0 | return fastEmitInst_r(X86::SQRTPDr, &X86::VR128RegClass, Op0, Op0IsKill); |
1278 | 0 | } |
1279 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
1280 | 0 | return fastEmitInst_r(X86::VSQRTPDr, &X86::VR128RegClass, Op0, Op0IsKill); |
1281 | 0 | } |
1282 | 0 | return 0; |
1283 | 0 | } |
1284 | | |
1285 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1286 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
1287 | 0 | return 0; |
1288 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
1289 | 0 | return fastEmitInst_r(X86::VSQRTPDZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
1290 | 0 | } |
1291 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
1292 | 0 | return fastEmitInst_r(X86::VSQRTPDYr, &X86::VR256RegClass, Op0, Op0IsKill); |
1293 | 0 | } |
1294 | 0 | return 0; |
1295 | 0 | } |
1296 | | |
1297 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v8f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1298 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
1299 | 0 | return 0; |
1300 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
1301 | 0 | return fastEmitInst_r(X86::VSQRTPDZr, &X86::VR512RegClass, Op0, Op0IsKill); |
1302 | 0 | } |
1303 | 0 | return 0; |
1304 | 0 | } |
1305 | | |
1306 | | unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1307 | | switch (VT.SimpleTy) { |
1308 | | case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill); |
1309 | | case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill); |
1310 | | case MVT::f80: return fastEmit_ISD_FSQRT_MVT_f80_r(RetVT, Op0, Op0IsKill); |
1311 | | case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
1312 | | case MVT::v8f32: return fastEmit_ISD_FSQRT_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
1313 | | case MVT::v16f32: return fastEmit_ISD_FSQRT_MVT_v16f32_r(RetVT, Op0, Op0IsKill); |
1314 | | case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
1315 | | case MVT::v4f64: return fastEmit_ISD_FSQRT_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
1316 | | case MVT::v8f64: return fastEmit_ISD_FSQRT_MVT_v8f64_r(RetVT, Op0, Op0IsKill); |
1317 | | default: return 0; |
1318 | | } |
1319 | | } |
1320 | | |
1321 | | // FastEmit functions for ISD::SCALAR_TO_VECTOR. |
1322 | | |
1323 | 1 | unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
1324 | 1 | if ((Subtarget->hasAVX512())1 ) { |
1325 | 0 | return fastEmitInst_r(X86::VMOVDI2PDIZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1326 | 0 | } |
1327 | 1 | if (1 (Subtarget->hasSSE2() && 1 !Subtarget->hasAVX()1 )) { |
1328 | 0 | return fastEmitInst_r(X86::MOVDI2PDIrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1329 | 0 | } |
1330 | 1 | if (1 (Subtarget->hasAVX() && 1 !Subtarget->hasAVX512()1 )) { |
1331 | 1 | return fastEmitInst_r(X86::VMOVDI2PDIrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1332 | 1 | } |
1333 | 0 | return 0; |
1334 | 1 | } |
1335 | | |
1336 | 0 | unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_x86mmx_r(unsigned Op0, bool Op0IsKill) { |
1337 | 0 | if ((Subtarget->hasMMX())0 ) { |
1338 | 0 | return fastEmitInst_r(X86::MMX_MOVD64rr, &X86::VR64RegClass, Op0, Op0IsKill); |
1339 | 0 | } |
1340 | 0 | return 0; |
1341 | 0 | } |
1342 | | |
1343 | 1 | unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1344 | 1 | switch (RetVT.SimpleTy) { |
1345 | 1 | case MVT::v4i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill); |
1346 | 0 | case MVT::x86mmx: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_x86mmx_r(Op0, Op0IsKill); |
1347 | 0 | default: return 0; |
1348 | 1 | } |
1349 | 1 | } |
1350 | | |
1351 | 0 | unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1352 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
1353 | 0 | return 0; |
1354 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
1355 | 0 | return fastEmitInst_r(X86::VMOV64toPQIZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1356 | 0 | } |
1357 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
1358 | 0 | return fastEmitInst_r(X86::MOV64toPQIrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1359 | 0 | } |
1360 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
1361 | 0 | return fastEmitInst_r(X86::VMOV64toPQIrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1362 | 0 | } |
1363 | 0 | return 0; |
1364 | 0 | } |
1365 | | |
1366 | 1 | unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1367 | 1 | switch (VT.SimpleTy) { |
1368 | 1 | case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0, Op0IsKill); |
1369 | 0 | case MVT::i64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(RetVT, Op0, Op0IsKill); |
1370 | 0 | default: return 0; |
1371 | 1 | } |
1372 | 1 | } |
1373 | | |
1374 | | // FastEmit functions for ISD::SIGN_EXTEND. |
1375 | | |
1376 | 45 | unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i32_r(unsigned Op0, bool Op0IsKill) { |
1377 | 45 | return fastEmitInst_r(X86::MOVSX32rr8, &X86::GR32RegClass, Op0, Op0IsKill); |
1378 | 45 | } |
1379 | | |
1380 | 3 | unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i64_r(unsigned Op0, bool Op0IsKill) { |
1381 | 3 | return fastEmitInst_r(X86::MOVSX64rr8, &X86::GR64RegClass, Op0, Op0IsKill); |
1382 | 3 | } |
1383 | | |
1384 | 56 | unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1385 | 56 | switch (RetVT.SimpleTy) { |
1386 | 45 | case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i32_r(Op0, Op0IsKill); |
1387 | 3 | case MVT::i64: return fastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i64_r(Op0, Op0IsKill); |
1388 | 8 | default: return 0; |
1389 | 56 | } |
1390 | 56 | } |
1391 | | |
1392 | 7 | unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i32_r(unsigned Op0, bool Op0IsKill) { |
1393 | 7 | return fastEmitInst_r(X86::MOVSX32rr16, &X86::GR32RegClass, Op0, Op0IsKill); |
1394 | 7 | } |
1395 | | |
1396 | 1 | unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i64_r(unsigned Op0, bool Op0IsKill) { |
1397 | 1 | return fastEmitInst_r(X86::MOVSX64rr16, &X86::GR64RegClass, Op0, Op0IsKill); |
1398 | 1 | } |
1399 | | |
1400 | 8 | unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1401 | 8 | switch (RetVT.SimpleTy) { |
1402 | 7 | case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i32_r(Op0, Op0IsKill); |
1403 | 1 | case MVT::i64: return fastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i64_r(Op0, Op0IsKill); |
1404 | 0 | default: return 0; |
1405 | 8 | } |
1406 | 8 | } |
1407 | | |
1408 | 63 | unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1409 | 63 | if (RetVT.SimpleTy != MVT::i64) |
1410 | 0 | return 0; |
1411 | 63 | if (63 (Subtarget->is64Bit())63 ) { |
1412 | 63 | return fastEmitInst_r(X86::MOVSX64rr32, &X86::GR64RegClass, Op0, Op0IsKill); |
1413 | 63 | } |
1414 | 0 | return 0; |
1415 | 63 | } |
1416 | | |
1417 | 133 | unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1418 | 133 | switch (VT.SimpleTy) { |
1419 | 56 | case MVT::i8: return fastEmit_ISD_SIGN_EXTEND_MVT_i8_r(RetVT, Op0, Op0IsKill); |
1420 | 8 | case MVT::i16: return fastEmit_ISD_SIGN_EXTEND_MVT_i16_r(RetVT, Op0, Op0IsKill); |
1421 | 63 | case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill); |
1422 | 6 | default: return 0; |
1423 | 133 | } |
1424 | 133 | } |
1425 | | |
1426 | | // FastEmit functions for ISD::SIGN_EXTEND_VECTOR_INREG. |
1427 | | |
1428 | 0 | unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
1429 | 0 | if ((Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
1430 | 0 | return fastEmitInst_r(X86::PMOVSXBWrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1431 | 0 | } |
1432 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
1433 | 0 | return fastEmitInst_r(X86::VPMOVSXBWrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1434 | 0 | } |
1435 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
1436 | 0 | return fastEmitInst_r(X86::VPMOVSXBWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1437 | 0 | } |
1438 | 0 | return 0; |
1439 | 0 | } |
1440 | | |
1441 | 0 | unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
1442 | 0 | if ((Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
1443 | 0 | return fastEmitInst_r(X86::PMOVSXBDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1444 | 0 | } |
1445 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
1446 | 0 | return fastEmitInst_r(X86::VPMOVSXBDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1447 | 0 | } |
1448 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
1449 | 0 | return fastEmitInst_r(X86::VPMOVSXBDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1450 | 0 | } |
1451 | 0 | return 0; |
1452 | 0 | } |
1453 | | |
1454 | 0 | unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { |
1455 | 0 | if ((Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
1456 | 0 | return fastEmitInst_r(X86::PMOVSXBQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1457 | 0 | } |
1458 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
1459 | 0 | return fastEmitInst_r(X86::VPMOVSXBQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1460 | 0 | } |
1461 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
1462 | 0 | return fastEmitInst_r(X86::VPMOVSXBQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1463 | 0 | } |
1464 | 0 | return 0; |
1465 | 0 | } |
1466 | | |
1467 | | unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1468 | | switch (RetVT.SimpleTy) { |
1469 | | case MVT::v8i16: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill); |
1470 | | case MVT::v4i32: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill); |
1471 | | case MVT::v2i64: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill); |
1472 | | default: return 0; |
1473 | | } |
1474 | | } |
1475 | | |
1476 | 0 | unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
1477 | 0 | if ((Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
1478 | 0 | return fastEmitInst_r(X86::PMOVSXWDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1479 | 0 | } |
1480 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
1481 | 0 | return fastEmitInst_r(X86::VPMOVSXWDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1482 | 0 | } |
1483 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
1484 | 0 | return fastEmitInst_r(X86::VPMOVSXWDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1485 | 0 | } |
1486 | 0 | return 0; |
1487 | 0 | } |
1488 | | |
1489 | 0 | unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { |
1490 | 0 | if ((Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
1491 | 0 | return fastEmitInst_r(X86::PMOVSXWQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1492 | 0 | } |
1493 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
1494 | 0 | return fastEmitInst_r(X86::VPMOVSXWQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1495 | 0 | } |
1496 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
1497 | 0 | return fastEmitInst_r(X86::VPMOVSXWQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1498 | 0 | } |
1499 | 0 | return 0; |
1500 | 0 | } |
1501 | | |
1502 | | unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1503 | | switch (RetVT.SimpleTy) { |
1504 | | case MVT::v4i32: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill); |
1505 | | case MVT::v2i64: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill); |
1506 | | default: return 0; |
1507 | | } |
1508 | | } |
1509 | | |
1510 | 0 | unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1511 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
1512 | 0 | return 0; |
1513 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
1514 | 0 | return fastEmitInst_r(X86::PMOVSXDQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1515 | 0 | } |
1516 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
1517 | 0 | return fastEmitInst_r(X86::VPMOVSXDQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1518 | 0 | } |
1519 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
1520 | 0 | return fastEmitInst_r(X86::VPMOVSXDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1521 | 0 | } |
1522 | 0 | return 0; |
1523 | 0 | } |
1524 | | |
1525 | | unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1526 | | switch (VT.SimpleTy) { |
1527 | | case MVT::v16i8: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_r(RetVT, Op0, Op0IsKill); |
1528 | | case MVT::v8i16: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_r(RetVT, Op0, Op0IsKill); |
1529 | | case MVT::v4i32: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
1530 | | default: return 0; |
1531 | | } |
1532 | | } |
1533 | | |
1534 | | // FastEmit functions for ISD::SINT_TO_FP. |
1535 | | |
1536 | 4 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) { |
1537 | 4 | if ((Subtarget->hasSSE1() && 4 !Subtarget->hasAVX()4 )) { |
1538 | 2 | return fastEmitInst_r(X86::CVTSI2SSrr, &X86::FR32RegClass, Op0, Op0IsKill); |
1539 | 2 | } |
1540 | 2 | return 0; |
1541 | 4 | } |
1542 | | |
1543 | 6 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { |
1544 | 6 | if ((Subtarget->hasSSE2() && 6 !Subtarget->hasAVX()4 )) { |
1545 | 2 | return fastEmitInst_r(X86::CVTSI2SDrr, &X86::FR64RegClass, Op0, Op0IsKill); |
1546 | 2 | } |
1547 | 4 | return 0; |
1548 | 6 | } |
1549 | | |
1550 | 10 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1551 | 10 | switch (RetVT.SimpleTy) { |
1552 | 4 | case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill); |
1553 | 6 | case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill); |
1554 | 0 | default: return 0; |
1555 | 10 | } |
1556 | 10 | } |
1557 | | |
1558 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { |
1559 | 0 | if ((Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
1560 | 0 | return fastEmitInst_r(X86::CVTSI2SS64rr, &X86::FR32RegClass, Op0, Op0IsKill); |
1561 | 0 | } |
1562 | 0 | return 0; |
1563 | 0 | } |
1564 | | |
1565 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0, bool Op0IsKill) { |
1566 | 0 | if ((Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
1567 | 0 | return fastEmitInst_r(X86::CVTSI2SD64rr, &X86::FR64RegClass, Op0, Op0IsKill); |
1568 | 0 | } |
1569 | 0 | return 0; |
1570 | 0 | } |
1571 | | |
1572 | | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1573 | | switch (RetVT.SimpleTy) { |
1574 | | case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill); |
1575 | | case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0, Op0IsKill); |
1576 | | default: return 0; |
1577 | | } |
1578 | | } |
1579 | | |
1580 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { |
1581 | 0 | if ((Subtarget->hasVLX())0 ) { |
1582 | 0 | return fastEmitInst_r(X86::VCVTDQ2PSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1583 | 0 | } |
1584 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
1585 | 0 | return fastEmitInst_r(X86::CVTDQ2PSrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1586 | 0 | } |
1587 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
1588 | 0 | return fastEmitInst_r(X86::VCVTDQ2PSrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1589 | 0 | } |
1590 | 0 | return 0; |
1591 | 0 | } |
1592 | | |
1593 | 2 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_MVT_v4f64_r(unsigned Op0, bool Op0IsKill) { |
1594 | 2 | if ((Subtarget->hasVLX())2 ) { |
1595 | 0 | return fastEmitInst_r(X86::VCVTDQ2PDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1596 | 0 | } |
1597 | 2 | if (2 (Subtarget->hasAVX()) && 2 (!Subtarget->hasVLX())2 ) { |
1598 | 2 | return fastEmitInst_r(X86::VCVTDQ2PDYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
1599 | 2 | } |
1600 | 0 | return 0; |
1601 | 2 | } |
1602 | | |
1603 | 2 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1604 | 2 | switch (RetVT.SimpleTy) { |
1605 | 0 | case MVT::v4f32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_MVT_v4f32_r(Op0, Op0IsKill); |
1606 | 2 | case MVT::v4f64: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_MVT_v4f64_r(Op0, Op0IsKill); |
1607 | 0 | default: return 0; |
1608 | 2 | } |
1609 | 2 | } |
1610 | | |
1611 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i32_MVT_v8f32_r(unsigned Op0, bool Op0IsKill) { |
1612 | 0 | if ((Subtarget->hasVLX())0 ) { |
1613 | 0 | return fastEmitInst_r(X86::VCVTDQ2PSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1614 | 0 | } |
1615 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
1616 | 0 | return fastEmitInst_r(X86::VCVTDQ2PSYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
1617 | 0 | } |
1618 | 0 | return 0; |
1619 | 0 | } |
1620 | | |
1621 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i32_MVT_v8f64_r(unsigned Op0, bool Op0IsKill) { |
1622 | 0 | if ((Subtarget->hasAVX512())0 ) { |
1623 | 0 | return fastEmitInst_r(X86::VCVTDQ2PDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
1624 | 0 | } |
1625 | 0 | return 0; |
1626 | 0 | } |
1627 | | |
1628 | | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1629 | | switch (RetVT.SimpleTy) { |
1630 | | case MVT::v8f32: return fastEmit_ISD_SINT_TO_FP_MVT_v8i32_MVT_v8f32_r(Op0, Op0IsKill); |
1631 | | case MVT::v8f64: return fastEmit_ISD_SINT_TO_FP_MVT_v8i32_MVT_v8f64_r(Op0, Op0IsKill); |
1632 | | default: return 0; |
1633 | | } |
1634 | | } |
1635 | | |
1636 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1637 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
1638 | 0 | return 0; |
1639 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
1640 | 0 | return fastEmitInst_r(X86::VCVTDQ2PSZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
1641 | 0 | } |
1642 | 0 | return 0; |
1643 | 0 | } |
1644 | | |
1645 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1646 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1647 | 0 | return 0; |
1648 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
1649 | 0 | return fastEmitInst_r(X86::VCVTQQ2PDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1650 | 0 | } |
1651 | 0 | return 0; |
1652 | 0 | } |
1653 | | |
1654 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { |
1655 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
1656 | 0 | return fastEmitInst_r(X86::VCVTQQ2PSZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1657 | 0 | } |
1658 | 0 | return 0; |
1659 | 0 | } |
1660 | | |
1661 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i64_MVT_v4f64_r(unsigned Op0, bool Op0IsKill) { |
1662 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
1663 | 0 | return fastEmitInst_r(X86::VCVTQQ2PDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1664 | 0 | } |
1665 | 0 | return 0; |
1666 | 0 | } |
1667 | | |
1668 | | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1669 | | switch (RetVT.SimpleTy) { |
1670 | | case MVT::v4f32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i64_MVT_v4f32_r(Op0, Op0IsKill); |
1671 | | case MVT::v4f64: return fastEmit_ISD_SINT_TO_FP_MVT_v4i64_MVT_v4f64_r(Op0, Op0IsKill); |
1672 | | default: return 0; |
1673 | | } |
1674 | | } |
1675 | | |
1676 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i64_MVT_v8f32_r(unsigned Op0, bool Op0IsKill) { |
1677 | 0 | if ((Subtarget->hasDQI())0 ) { |
1678 | 0 | return fastEmitInst_r(X86::VCVTQQ2PSZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1679 | 0 | } |
1680 | 0 | return 0; |
1681 | 0 | } |
1682 | | |
1683 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i64_MVT_v8f64_r(unsigned Op0, bool Op0IsKill) { |
1684 | 0 | if ((Subtarget->hasDQI())0 ) { |
1685 | 0 | return fastEmitInst_r(X86::VCVTQQ2PDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
1686 | 0 | } |
1687 | 0 | return 0; |
1688 | 0 | } |
1689 | | |
1690 | | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1691 | | switch (RetVT.SimpleTy) { |
1692 | | case MVT::v8f32: return fastEmit_ISD_SINT_TO_FP_MVT_v8i64_MVT_v8f32_r(Op0, Op0IsKill); |
1693 | | case MVT::v8f64: return fastEmit_ISD_SINT_TO_FP_MVT_v8i64_MVT_v8f64_r(Op0, Op0IsKill); |
1694 | | default: return 0; |
1695 | | } |
1696 | | } |
1697 | | |
1698 | 12 | unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1699 | 12 | switch (VT.SimpleTy) { |
1700 | 10 | case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill); |
1701 | 0 | case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill); |
1702 | 2 | case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
1703 | 0 | case MVT::v8i32: return fastEmit_ISD_SINT_TO_FP_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
1704 | 0 | case MVT::v16i32: return fastEmit_ISD_SINT_TO_FP_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
1705 | 0 | case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
1706 | 0 | case MVT::v4i64: return fastEmit_ISD_SINT_TO_FP_MVT_v4i64_r(RetVT, Op0, Op0IsKill); |
1707 | 0 | case MVT::v8i64: return fastEmit_ISD_SINT_TO_FP_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
1708 | 0 | default: return 0; |
1709 | 12 | } |
1710 | 12 | } |
1711 | | |
1712 | | // FastEmit functions for ISD::TRUNCATE. |
1713 | | |
1714 | 2 | unsigned fastEmit_ISD_TRUNCATE_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1715 | 2 | if (RetVT.SimpleTy != MVT::i8) |
1716 | 0 | return 0; |
1717 | 2 | if (2 (Subtarget->is64Bit())2 ) { |
1718 | 1 | return fastEmitInst_extractsubreg(RetVT, Op0, Op0IsKill, X86::sub_8bit); |
1719 | 1 | } |
1720 | 1 | return 0; |
1721 | 2 | } |
1722 | | |
1723 | 8 | unsigned fastEmit_ISD_TRUNCATE_MVT_i32_MVT_i8_r(unsigned Op0, bool Op0IsKill) { |
1724 | 8 | if ((Subtarget->is64Bit())8 ) { |
1725 | 4 | return fastEmitInst_extractsubreg(MVT::i8, Op0, Op0IsKill, X86::sub_8bit); |
1726 | 4 | } |
1727 | 4 | return 0; |
1728 | 8 | } |
1729 | | |
1730 | 9 | unsigned fastEmit_ISD_TRUNCATE_MVT_i32_MVT_i16_r(unsigned Op0, bool Op0IsKill) { |
1731 | 9 | return fastEmitInst_extractsubreg(MVT::i16, Op0, Op0IsKill, X86::sub_16bit); |
1732 | 9 | } |
1733 | | |
1734 | 17 | unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1735 | 17 | switch (RetVT.SimpleTy) { |
1736 | 8 | case MVT::i8: return fastEmit_ISD_TRUNCATE_MVT_i32_MVT_i8_r(Op0, Op0IsKill); |
1737 | 9 | case MVT::i16: return fastEmit_ISD_TRUNCATE_MVT_i32_MVT_i16_r(Op0, Op0IsKill); |
1738 | 0 | default: return 0; |
1739 | 17 | } |
1740 | 17 | } |
1741 | | |
1742 | 12 | unsigned fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i8_r(unsigned Op0, bool Op0IsKill) { |
1743 | 12 | return fastEmitInst_extractsubreg(MVT::i8, Op0, Op0IsKill, X86::sub_8bit); |
1744 | 12 | } |
1745 | | |
1746 | 3 | unsigned fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i16_r(unsigned Op0, bool Op0IsKill) { |
1747 | 3 | return fastEmitInst_extractsubreg(MVT::i16, Op0, Op0IsKill, X86::sub_16bit); |
1748 | 3 | } |
1749 | | |
1750 | 8 | unsigned fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i32_r(unsigned Op0, bool Op0IsKill) { |
1751 | 8 | return fastEmitInst_extractsubreg(MVT::i32, Op0, Op0IsKill, X86::sub_32bit); |
1752 | 8 | } |
1753 | | |
1754 | 23 | unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1755 | 23 | switch (RetVT.SimpleTy) { |
1756 | 12 | case MVT::i8: return fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i8_r(Op0, Op0IsKill); |
1757 | 3 | case MVT::i16: return fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i16_r(Op0, Op0IsKill); |
1758 | 8 | case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i32_r(Op0, Op0IsKill); |
1759 | 0 | default: return 0; |
1760 | 23 | } |
1761 | 23 | } |
1762 | | |
1763 | 49 | unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1764 | 49 | switch (VT.SimpleTy) { |
1765 | 2 | case MVT::i16: return fastEmit_ISD_TRUNCATE_MVT_i16_r(RetVT, Op0, Op0IsKill); |
1766 | 17 | case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0, Op0IsKill); |
1767 | 23 | case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0, Op0IsKill); |
1768 | 7 | default: return 0; |
1769 | 49 | } |
1770 | 49 | } |
1771 | | |
1772 | | // FastEmit functions for ISD::UINT_TO_FP. |
1773 | | |
1774 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { |
1775 | 0 | if ((Subtarget->hasVLX())0 ) { |
1776 | 0 | return fastEmitInst_r(X86::VCVTUDQ2PSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1777 | 0 | } |
1778 | 0 | return 0; |
1779 | 0 | } |
1780 | | |
1781 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_MVT_v4f64_r(unsigned Op0, bool Op0IsKill) { |
1782 | 0 | if ((Subtarget->hasVLX())0 ) { |
1783 | 0 | return fastEmitInst_r(X86::VCVTUDQ2PDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1784 | 0 | } |
1785 | 0 | return 0; |
1786 | 0 | } |
1787 | | |
1788 | | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1789 | | switch (RetVT.SimpleTy) { |
1790 | | case MVT::v4f32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_MVT_v4f32_r(Op0, Op0IsKill); |
1791 | | case MVT::v4f64: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_MVT_v4f64_r(Op0, Op0IsKill); |
1792 | | default: return 0; |
1793 | | } |
1794 | | } |
1795 | | |
1796 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i32_MVT_v8f32_r(unsigned Op0, bool Op0IsKill) { |
1797 | 0 | if ((Subtarget->hasVLX())0 ) { |
1798 | 0 | return fastEmitInst_r(X86::VCVTUDQ2PSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1799 | 0 | } |
1800 | 0 | return 0; |
1801 | 0 | } |
1802 | | |
1803 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i32_MVT_v8f64_r(unsigned Op0, bool Op0IsKill) { |
1804 | 0 | if ((Subtarget->hasAVX512())0 ) { |
1805 | 0 | return fastEmitInst_r(X86::VCVTUDQ2PDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
1806 | 0 | } |
1807 | 0 | return 0; |
1808 | 0 | } |
1809 | | |
1810 | | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1811 | | switch (RetVT.SimpleTy) { |
1812 | | case MVT::v8f32: return fastEmit_ISD_UINT_TO_FP_MVT_v8i32_MVT_v8f32_r(Op0, Op0IsKill); |
1813 | | case MVT::v8f64: return fastEmit_ISD_UINT_TO_FP_MVT_v8i32_MVT_v8f64_r(Op0, Op0IsKill); |
1814 | | default: return 0; |
1815 | | } |
1816 | | } |
1817 | | |
1818 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1819 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
1820 | 0 | return 0; |
1821 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
1822 | 0 | return fastEmitInst_r(X86::VCVTUDQ2PSZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
1823 | 0 | } |
1824 | 0 | return 0; |
1825 | 0 | } |
1826 | | |
1827 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1828 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1829 | 0 | return 0; |
1830 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
1831 | 0 | return fastEmitInst_r(X86::VCVTUQQ2PDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1832 | 0 | } |
1833 | 0 | return 0; |
1834 | 0 | } |
1835 | | |
1836 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { |
1837 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
1838 | 0 | return fastEmitInst_r(X86::VCVTUQQ2PSZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1839 | 0 | } |
1840 | 0 | return 0; |
1841 | 0 | } |
1842 | | |
1843 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i64_MVT_v4f64_r(unsigned Op0, bool Op0IsKill) { |
1844 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
1845 | 0 | return fastEmitInst_r(X86::VCVTUQQ2PDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1846 | 0 | } |
1847 | 0 | return 0; |
1848 | 0 | } |
1849 | | |
1850 | | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1851 | | switch (RetVT.SimpleTy) { |
1852 | | case MVT::v4f32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i64_MVT_v4f32_r(Op0, Op0IsKill); |
1853 | | case MVT::v4f64: return fastEmit_ISD_UINT_TO_FP_MVT_v4i64_MVT_v4f64_r(Op0, Op0IsKill); |
1854 | | default: return 0; |
1855 | | } |
1856 | | } |
1857 | | |
1858 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i64_MVT_v8f32_r(unsigned Op0, bool Op0IsKill) { |
1859 | 0 | if ((Subtarget->hasDQI())0 ) { |
1860 | 0 | return fastEmitInst_r(X86::VCVTUQQ2PSZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
1861 | 0 | } |
1862 | 0 | return 0; |
1863 | 0 | } |
1864 | | |
1865 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i64_MVT_v8f64_r(unsigned Op0, bool Op0IsKill) { |
1866 | 0 | if ((Subtarget->hasDQI())0 ) { |
1867 | 0 | return fastEmitInst_r(X86::VCVTUQQ2PDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
1868 | 0 | } |
1869 | 0 | return 0; |
1870 | 0 | } |
1871 | | |
1872 | | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1873 | | switch (RetVT.SimpleTy) { |
1874 | | case MVT::v8f32: return fastEmit_ISD_UINT_TO_FP_MVT_v8i64_MVT_v8f32_r(Op0, Op0IsKill); |
1875 | | case MVT::v8f64: return fastEmit_ISD_UINT_TO_FP_MVT_v8i64_MVT_v8f64_r(Op0, Op0IsKill); |
1876 | | default: return 0; |
1877 | | } |
1878 | | } |
1879 | | |
1880 | | unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1881 | | switch (VT.SimpleTy) { |
1882 | | case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
1883 | | case MVT::v8i32: return fastEmit_ISD_UINT_TO_FP_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
1884 | | case MVT::v16i32: return fastEmit_ISD_UINT_TO_FP_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
1885 | | case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
1886 | | case MVT::v4i64: return fastEmit_ISD_UINT_TO_FP_MVT_v4i64_r(RetVT, Op0, Op0IsKill); |
1887 | | case MVT::v8i64: return fastEmit_ISD_UINT_TO_FP_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
1888 | | default: return 0; |
1889 | | } |
1890 | | } |
1891 | | |
1892 | | // FastEmit functions for ISD::ZERO_EXTEND. |
1893 | | |
1894 | 182 | unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1895 | 182 | if (RetVT.SimpleTy != MVT::i32) |
1896 | 11 | return 0; |
1897 | 171 | return fastEmitInst_r(X86::MOVZX32rr8, &X86::GR32RegClass, Op0, Op0IsKill); |
1898 | 182 | } |
1899 | | |
1900 | 39 | unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1901 | 39 | if (RetVT.SimpleTy != MVT::i32) |
1902 | 2 | return 0; |
1903 | 37 | return fastEmitInst_r(X86::MOVZX32rr16, &X86::GR32RegClass, Op0, Op0IsKill); |
1904 | 39 | } |
1905 | | |
1906 | 235 | unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1907 | 235 | switch (VT.SimpleTy) { |
1908 | 182 | case MVT::i8: return fastEmit_ISD_ZERO_EXTEND_MVT_i8_r(RetVT, Op0, Op0IsKill); |
1909 | 39 | case MVT::i16: return fastEmit_ISD_ZERO_EXTEND_MVT_i16_r(RetVT, Op0, Op0IsKill); |
1910 | 14 | default: return 0; |
1911 | 235 | } |
1912 | 235 | } |
1913 | | |
1914 | | // FastEmit functions for ISD::ZERO_EXTEND_VECTOR_INREG. |
1915 | | |
1916 | 0 | unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
1917 | 0 | if ((Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
1918 | 0 | return fastEmitInst_r(X86::PMOVZXBWrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1919 | 0 | } |
1920 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
1921 | 0 | return fastEmitInst_r(X86::VPMOVZXBWrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1922 | 0 | } |
1923 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
1924 | 0 | return fastEmitInst_r(X86::VPMOVZXBWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1925 | 0 | } |
1926 | 0 | return 0; |
1927 | 0 | } |
1928 | | |
1929 | 0 | unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
1930 | 0 | if ((Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
1931 | 0 | return fastEmitInst_r(X86::PMOVZXBDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1932 | 0 | } |
1933 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
1934 | 0 | return fastEmitInst_r(X86::VPMOVZXBDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1935 | 0 | } |
1936 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
1937 | 0 | return fastEmitInst_r(X86::VPMOVZXBDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1938 | 0 | } |
1939 | 0 | return 0; |
1940 | 0 | } |
1941 | | |
1942 | 0 | unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { |
1943 | 0 | if ((Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
1944 | 0 | return fastEmitInst_r(X86::PMOVZXBQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1945 | 0 | } |
1946 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
1947 | 0 | return fastEmitInst_r(X86::VPMOVZXBQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1948 | 0 | } |
1949 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
1950 | 0 | return fastEmitInst_r(X86::VPMOVZXBQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1951 | 0 | } |
1952 | 0 | return 0; |
1953 | 0 | } |
1954 | | |
1955 | | unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1956 | | switch (RetVT.SimpleTy) { |
1957 | | case MVT::v8i16: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill); |
1958 | | case MVT::v4i32: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill); |
1959 | | case MVT::v2i64: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill); |
1960 | | default: return 0; |
1961 | | } |
1962 | | } |
1963 | | |
1964 | 0 | unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
1965 | 0 | if ((Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
1966 | 0 | return fastEmitInst_r(X86::PMOVZXWDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1967 | 0 | } |
1968 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
1969 | 0 | return fastEmitInst_r(X86::VPMOVZXWDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1970 | 0 | } |
1971 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
1972 | 0 | return fastEmitInst_r(X86::VPMOVZXWDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1973 | 0 | } |
1974 | 0 | return 0; |
1975 | 0 | } |
1976 | | |
1977 | 0 | unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { |
1978 | 0 | if ((Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
1979 | 0 | return fastEmitInst_r(X86::PMOVZXWQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1980 | 0 | } |
1981 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
1982 | 0 | return fastEmitInst_r(X86::VPMOVZXWQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
1983 | 0 | } |
1984 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
1985 | 0 | return fastEmitInst_r(X86::VPMOVZXWQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
1986 | 0 | } |
1987 | 0 | return 0; |
1988 | 0 | } |
1989 | | |
1990 | | unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1991 | | switch (RetVT.SimpleTy) { |
1992 | | case MVT::v4i32: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill); |
1993 | | case MVT::v2i64: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill); |
1994 | | default: return 0; |
1995 | | } |
1996 | | } |
1997 | | |
1998 | 0 | unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
1999 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
2000 | 0 | return 0; |
2001 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
2002 | 0 | return fastEmitInst_r(X86::PMOVZXDQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
2003 | 0 | } |
2004 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
2005 | 0 | return fastEmitInst_r(X86::VPMOVZXDQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
2006 | 0 | } |
2007 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
2008 | 0 | return fastEmitInst_r(X86::VPMOVZXDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2009 | 0 | } |
2010 | 0 | return 0; |
2011 | 0 | } |
2012 | | |
2013 | | unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2014 | | switch (VT.SimpleTy) { |
2015 | | case MVT::v16i8: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_r(RetVT, Op0, Op0IsKill); |
2016 | | case MVT::v8i16: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_r(RetVT, Op0, Op0IsKill); |
2017 | | case MVT::v4i32: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
2018 | | default: return 0; |
2019 | | } |
2020 | | } |
2021 | | |
2022 | | // FastEmit functions for X86ISD::CALL. |
2023 | | |
2024 | 0 | unsigned fastEmit_X86ISD_CALL_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2025 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
2026 | 0 | return 0; |
2027 | 0 | if (0 (!Subtarget->is64Bit())0 ) { |
2028 | 0 | return fastEmitInst_r(X86::CALL16r, &X86::GR16RegClass, Op0, Op0IsKill); |
2029 | 0 | } |
2030 | 0 | return 0; |
2031 | 0 | } |
2032 | | |
2033 | 0 | unsigned fastEmit_X86ISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2034 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
2035 | 0 | return 0; |
2036 | 0 | if (0 (!Subtarget->is64Bit())0 ) { |
2037 | 0 | return fastEmitInst_r(X86::CALL32r, &X86::GR32RegClass, Op0, Op0IsKill); |
2038 | 0 | } |
2039 | 0 | return 0; |
2040 | 0 | } |
2041 | | |
2042 | 0 | unsigned fastEmit_X86ISD_CALL_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2043 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
2044 | 0 | return 0; |
2045 | 0 | if (0 (Subtarget->is64Bit())0 ) { |
2046 | 0 | return fastEmitInst_r(X86::CALL64r, &X86::GR64RegClass, Op0, Op0IsKill); |
2047 | 0 | } |
2048 | 0 | return 0; |
2049 | 0 | } |
2050 | | |
2051 | | unsigned fastEmit_X86ISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2052 | | switch (VT.SimpleTy) { |
2053 | | case MVT::i16: return fastEmit_X86ISD_CALL_MVT_i16_r(RetVT, Op0, Op0IsKill); |
2054 | | case MVT::i32: return fastEmit_X86ISD_CALL_MVT_i32_r(RetVT, Op0, Op0IsKill); |
2055 | | case MVT::i64: return fastEmit_X86ISD_CALL_MVT_i64_r(RetVT, Op0, Op0IsKill); |
2056 | | default: return 0; |
2057 | | } |
2058 | | } |
2059 | | |
2060 | | // FastEmit functions for X86ISD::COMPRESS. |
2061 | | |
2062 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2063 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
2064 | 0 | return 0; |
2065 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2066 | 0 | return fastEmitInst_r(X86::VPCOMPRESSDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2067 | 0 | } |
2068 | 0 | return 0; |
2069 | 0 | } |
2070 | | |
2071 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2072 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
2073 | 0 | return 0; |
2074 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2075 | 0 | return fastEmitInst_r(X86::VPCOMPRESSDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2076 | 0 | } |
2077 | 0 | return 0; |
2078 | 0 | } |
2079 | | |
2080 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2081 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
2082 | 0 | return 0; |
2083 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
2084 | 0 | return fastEmitInst_r(X86::VPCOMPRESSDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2085 | 0 | } |
2086 | 0 | return 0; |
2087 | 0 | } |
2088 | | |
2089 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2090 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
2091 | 0 | return 0; |
2092 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2093 | 0 | return fastEmitInst_r(X86::VPCOMPRESSQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2094 | 0 | } |
2095 | 0 | return 0; |
2096 | 0 | } |
2097 | | |
2098 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v4i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2099 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
2100 | 0 | return 0; |
2101 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2102 | 0 | return fastEmitInst_r(X86::VPCOMPRESSQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2103 | 0 | } |
2104 | 0 | return 0; |
2105 | 0 | } |
2106 | | |
2107 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2108 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
2109 | 0 | return 0; |
2110 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
2111 | 0 | return fastEmitInst_r(X86::VPCOMPRESSQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2112 | 0 | } |
2113 | 0 | return 0; |
2114 | 0 | } |
2115 | | |
2116 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2117 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
2118 | 0 | return 0; |
2119 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2120 | 0 | return fastEmitInst_r(X86::VCOMPRESSPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2121 | 0 | } |
2122 | 0 | return 0; |
2123 | 0 | } |
2124 | | |
2125 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2126 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
2127 | 0 | return 0; |
2128 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2129 | 0 | return fastEmitInst_r(X86::VCOMPRESSPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2130 | 0 | } |
2131 | 0 | return 0; |
2132 | 0 | } |
2133 | | |
2134 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v16f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2135 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
2136 | 0 | return 0; |
2137 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
2138 | 0 | return fastEmitInst_r(X86::VCOMPRESSPSZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2139 | 0 | } |
2140 | 0 | return 0; |
2141 | 0 | } |
2142 | | |
2143 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2144 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
2145 | 0 | return 0; |
2146 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2147 | 0 | return fastEmitInst_r(X86::VCOMPRESSPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2148 | 0 | } |
2149 | 0 | return 0; |
2150 | 0 | } |
2151 | | |
2152 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2153 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
2154 | 0 | return 0; |
2155 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2156 | 0 | return fastEmitInst_r(X86::VCOMPRESSPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2157 | 0 | } |
2158 | 0 | return 0; |
2159 | 0 | } |
2160 | | |
2161 | 0 | unsigned fastEmit_X86ISD_COMPRESS_MVT_v8f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2162 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
2163 | 0 | return 0; |
2164 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
2165 | 0 | return fastEmitInst_r(X86::VCOMPRESSPDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2166 | 0 | } |
2167 | 0 | return 0; |
2168 | 0 | } |
2169 | | |
2170 | | unsigned fastEmit_X86ISD_COMPRESS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2171 | | switch (VT.SimpleTy) { |
2172 | | case MVT::v4i32: return fastEmit_X86ISD_COMPRESS_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
2173 | | case MVT::v8i32: return fastEmit_X86ISD_COMPRESS_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
2174 | | case MVT::v16i32: return fastEmit_X86ISD_COMPRESS_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
2175 | | case MVT::v2i64: return fastEmit_X86ISD_COMPRESS_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
2176 | | case MVT::v4i64: return fastEmit_X86ISD_COMPRESS_MVT_v4i64_r(RetVT, Op0, Op0IsKill); |
2177 | | case MVT::v8i64: return fastEmit_X86ISD_COMPRESS_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
2178 | | case MVT::v4f32: return fastEmit_X86ISD_COMPRESS_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
2179 | | case MVT::v8f32: return fastEmit_X86ISD_COMPRESS_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
2180 | | case MVT::v16f32: return fastEmit_X86ISD_COMPRESS_MVT_v16f32_r(RetVT, Op0, Op0IsKill); |
2181 | | case MVT::v2f64: return fastEmit_X86ISD_COMPRESS_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
2182 | | case MVT::v4f64: return fastEmit_X86ISD_COMPRESS_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
2183 | | case MVT::v8f64: return fastEmit_X86ISD_COMPRESS_MVT_v8f64_r(RetVT, Op0, Op0IsKill); |
2184 | | default: return 0; |
2185 | | } |
2186 | | } |
2187 | | |
2188 | | // FastEmit functions for X86ISD::CONFLICT. |
2189 | | |
2190 | 0 | unsigned fastEmit_X86ISD_CONFLICT_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2191 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
2192 | 0 | return 0; |
2193 | 0 | if (0 (Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
2194 | 0 | return fastEmitInst_r(X86::VPCONFLICTDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2195 | 0 | } |
2196 | 0 | return 0; |
2197 | 0 | } |
2198 | | |
2199 | 0 | unsigned fastEmit_X86ISD_CONFLICT_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2200 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
2201 | 0 | return 0; |
2202 | 0 | if (0 (Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
2203 | 0 | return fastEmitInst_r(X86::VPCONFLICTDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2204 | 0 | } |
2205 | 0 | return 0; |
2206 | 0 | } |
2207 | | |
2208 | 0 | unsigned fastEmit_X86ISD_CONFLICT_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2209 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
2210 | 0 | return 0; |
2211 | 0 | if (0 (Subtarget->hasCDI())0 ) { |
2212 | 0 | return fastEmitInst_r(X86::VPCONFLICTDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2213 | 0 | } |
2214 | 0 | return 0; |
2215 | 0 | } |
2216 | | |
2217 | 0 | unsigned fastEmit_X86ISD_CONFLICT_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2218 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
2219 | 0 | return 0; |
2220 | 0 | if (0 (Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
2221 | 0 | return fastEmitInst_r(X86::VPCONFLICTQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2222 | 0 | } |
2223 | 0 | return 0; |
2224 | 0 | } |
2225 | | |
2226 | 0 | unsigned fastEmit_X86ISD_CONFLICT_MVT_v4i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2227 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
2228 | 0 | return 0; |
2229 | 0 | if (0 (Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
2230 | 0 | return fastEmitInst_r(X86::VPCONFLICTQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2231 | 0 | } |
2232 | 0 | return 0; |
2233 | 0 | } |
2234 | | |
2235 | 0 | unsigned fastEmit_X86ISD_CONFLICT_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2236 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
2237 | 0 | return 0; |
2238 | 0 | if (0 (Subtarget->hasCDI())0 ) { |
2239 | 0 | return fastEmitInst_r(X86::VPCONFLICTQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2240 | 0 | } |
2241 | 0 | return 0; |
2242 | 0 | } |
2243 | | |
2244 | | unsigned fastEmit_X86ISD_CONFLICT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2245 | | switch (VT.SimpleTy) { |
2246 | | case MVT::v4i32: return fastEmit_X86ISD_CONFLICT_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
2247 | | case MVT::v8i32: return fastEmit_X86ISD_CONFLICT_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
2248 | | case MVT::v16i32: return fastEmit_X86ISD_CONFLICT_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
2249 | | case MVT::v2i64: return fastEmit_X86ISD_CONFLICT_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
2250 | | case MVT::v4i64: return fastEmit_X86ISD_CONFLICT_MVT_v4i64_r(RetVT, Op0, Op0IsKill); |
2251 | | case MVT::v8i64: return fastEmit_X86ISD_CONFLICT_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
2252 | | default: return 0; |
2253 | | } |
2254 | | } |
2255 | | |
2256 | | // FastEmit functions for X86ISD::CVT2MASK. |
2257 | | |
2258 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2259 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
2260 | 0 | return 0; |
2261 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
2262 | 0 | return fastEmitInst_r(X86::VPMOVB2MZ128rr, &X86::VK16RegClass, Op0, Op0IsKill); |
2263 | 0 | } |
2264 | 0 | return 0; |
2265 | 0 | } |
2266 | | |
2267 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v32i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2268 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
2269 | 0 | return 0; |
2270 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
2271 | 0 | return fastEmitInst_r(X86::VPMOVB2MZ256rr, &X86::VK32RegClass, Op0, Op0IsKill); |
2272 | 0 | } |
2273 | 0 | return 0; |
2274 | 0 | } |
2275 | | |
2276 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v64i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2277 | 0 | if (RetVT.SimpleTy != MVT::v64i1) |
2278 | 0 | return 0; |
2279 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
2280 | 0 | return fastEmitInst_r(X86::VPMOVB2MZrr, &X86::VK64RegClass, Op0, Op0IsKill); |
2281 | 0 | } |
2282 | 0 | return 0; |
2283 | 0 | } |
2284 | | |
2285 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2286 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
2287 | 0 | return 0; |
2288 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
2289 | 0 | return fastEmitInst_r(X86::VPMOVW2MZ128rr, &X86::VK8RegClass, Op0, Op0IsKill); |
2290 | 0 | } |
2291 | 0 | return 0; |
2292 | 0 | } |
2293 | | |
2294 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v16i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2295 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
2296 | 0 | return 0; |
2297 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
2298 | 0 | return fastEmitInst_r(X86::VPMOVW2MZ256rr, &X86::VK16RegClass, Op0, Op0IsKill); |
2299 | 0 | } |
2300 | 0 | return 0; |
2301 | 0 | } |
2302 | | |
2303 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v32i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2304 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
2305 | 0 | return 0; |
2306 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
2307 | 0 | return fastEmitInst_r(X86::VPMOVW2MZrr, &X86::VK32RegClass, Op0, Op0IsKill); |
2308 | 0 | } |
2309 | 0 | return 0; |
2310 | 0 | } |
2311 | | |
2312 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2313 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
2314 | 0 | return 0; |
2315 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2316 | 0 | return fastEmitInst_r(X86::VPMOVD2MZ128rr, &X86::VK4RegClass, Op0, Op0IsKill); |
2317 | 0 | } |
2318 | 0 | return 0; |
2319 | 0 | } |
2320 | | |
2321 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2322 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
2323 | 0 | return 0; |
2324 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2325 | 0 | return fastEmitInst_r(X86::VPMOVD2MZ256rr, &X86::VK8RegClass, Op0, Op0IsKill); |
2326 | 0 | } |
2327 | 0 | return 0; |
2328 | 0 | } |
2329 | | |
2330 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2331 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
2332 | 0 | return 0; |
2333 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
2334 | 0 | return fastEmitInst_r(X86::VPMOVD2MZrr, &X86::VK16RegClass, Op0, Op0IsKill); |
2335 | 0 | } |
2336 | 0 | return 0; |
2337 | 0 | } |
2338 | | |
2339 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2340 | 0 | if (RetVT.SimpleTy != MVT::v2i1) |
2341 | 0 | return 0; |
2342 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2343 | 0 | return fastEmitInst_r(X86::VPMOVQ2MZ128rr, &X86::VK2RegClass, Op0, Op0IsKill); |
2344 | 0 | } |
2345 | 0 | return 0; |
2346 | 0 | } |
2347 | | |
2348 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v4i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2349 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
2350 | 0 | return 0; |
2351 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2352 | 0 | return fastEmitInst_r(X86::VPMOVQ2MZ256rr, &X86::VK4RegClass, Op0, Op0IsKill); |
2353 | 0 | } |
2354 | 0 | return 0; |
2355 | 0 | } |
2356 | | |
2357 | 0 | unsigned fastEmit_X86ISD_CVT2MASK_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2358 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
2359 | 0 | return 0; |
2360 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
2361 | 0 | return fastEmitInst_r(X86::VPMOVQ2MZrr, &X86::VK8RegClass, Op0, Op0IsKill); |
2362 | 0 | } |
2363 | 0 | return 0; |
2364 | 0 | } |
2365 | | |
2366 | | unsigned fastEmit_X86ISD_CVT2MASK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2367 | | switch (VT.SimpleTy) { |
2368 | | case MVT::v16i8: return fastEmit_X86ISD_CVT2MASK_MVT_v16i8_r(RetVT, Op0, Op0IsKill); |
2369 | | case MVT::v32i8: return fastEmit_X86ISD_CVT2MASK_MVT_v32i8_r(RetVT, Op0, Op0IsKill); |
2370 | | case MVT::v64i8: return fastEmit_X86ISD_CVT2MASK_MVT_v64i8_r(RetVT, Op0, Op0IsKill); |
2371 | | case MVT::v8i16: return fastEmit_X86ISD_CVT2MASK_MVT_v8i16_r(RetVT, Op0, Op0IsKill); |
2372 | | case MVT::v16i16: return fastEmit_X86ISD_CVT2MASK_MVT_v16i16_r(RetVT, Op0, Op0IsKill); |
2373 | | case MVT::v32i16: return fastEmit_X86ISD_CVT2MASK_MVT_v32i16_r(RetVT, Op0, Op0IsKill); |
2374 | | case MVT::v4i32: return fastEmit_X86ISD_CVT2MASK_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
2375 | | case MVT::v8i32: return fastEmit_X86ISD_CVT2MASK_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
2376 | | case MVT::v16i32: return fastEmit_X86ISD_CVT2MASK_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
2377 | | case MVT::v2i64: return fastEmit_X86ISD_CVT2MASK_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
2378 | | case MVT::v4i64: return fastEmit_X86ISD_CVT2MASK_MVT_v4i64_r(RetVT, Op0, Op0IsKill); |
2379 | | case MVT::v8i64: return fastEmit_X86ISD_CVT2MASK_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
2380 | | default: return 0; |
2381 | | } |
2382 | | } |
2383 | | |
2384 | | // FastEmit functions for X86ISD::CVTP2SI. |
2385 | | |
2386 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
2387 | 0 | if ((Subtarget->hasVLX())0 ) { |
2388 | 0 | return fastEmitInst_r(X86::VCVTPS2DQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2389 | 0 | } |
2390 | 0 | return 0; |
2391 | 0 | } |
2392 | | |
2393 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { |
2394 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2395 | 0 | return fastEmitInst_r(X86::VCVTPS2QQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2396 | 0 | } |
2397 | 0 | return 0; |
2398 | 0 | } |
2399 | | |
2400 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
2401 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2402 | 0 | return fastEmitInst_r(X86::VCVTPS2QQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2403 | 0 | } |
2404 | 0 | return 0; |
2405 | 0 | } |
2406 | | |
2407 | | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2408 | | switch (RetVT.SimpleTy) { |
2409 | | case MVT::v4i32: return fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v4i32_r(Op0, Op0IsKill); |
2410 | | case MVT::v2i64: return fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill); |
2411 | | case MVT::v4i64: return fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v4i64_r(Op0, Op0IsKill); |
2412 | | default: return 0; |
2413 | | } |
2414 | | } |
2415 | | |
2416 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f32_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
2417 | 0 | if ((Subtarget->hasVLX())0 ) { |
2418 | 0 | return fastEmitInst_r(X86::VCVTPS2DQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2419 | 0 | } |
2420 | 0 | return 0; |
2421 | 0 | } |
2422 | | |
2423 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f32_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
2424 | 0 | if ((Subtarget->hasDQI())0 ) { |
2425 | 0 | return fastEmitInst_r(X86::VCVTPS2QQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2426 | 0 | } |
2427 | 0 | return 0; |
2428 | 0 | } |
2429 | | |
2430 | | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2431 | | switch (RetVT.SimpleTy) { |
2432 | | case MVT::v8i32: return fastEmit_X86ISD_CVTP2SI_MVT_v8f32_MVT_v8i32_r(Op0, Op0IsKill); |
2433 | | case MVT::v8i64: return fastEmit_X86ISD_CVTP2SI_MVT_v8f32_MVT_v8i64_r(Op0, Op0IsKill); |
2434 | | default: return 0; |
2435 | | } |
2436 | | } |
2437 | | |
2438 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v16f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2439 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
2440 | 0 | return 0; |
2441 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
2442 | 0 | return fastEmitInst_r(X86::VCVTPS2DQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2443 | 0 | } |
2444 | 0 | return 0; |
2445 | 0 | } |
2446 | | |
2447 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
2448 | 0 | if ((Subtarget->hasVLX())0 ) { |
2449 | 0 | return fastEmitInst_r(X86::VCVTPD2DQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2450 | 0 | } |
2451 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
2452 | 0 | return fastEmitInst_r(X86::CVTPD2DQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
2453 | 0 | } |
2454 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
2455 | 0 | return fastEmitInst_r(X86::VCVTPD2DQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
2456 | 0 | } |
2457 | 0 | return 0; |
2458 | 0 | } |
2459 | | |
2460 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v2f64_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { |
2461 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2462 | 0 | return fastEmitInst_r(X86::VCVTPD2QQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2463 | 0 | } |
2464 | 0 | return 0; |
2465 | 0 | } |
2466 | | |
2467 | | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2468 | | switch (RetVT.SimpleTy) { |
2469 | | case MVT::v4i32: return fastEmit_X86ISD_CVTP2SI_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill); |
2470 | | case MVT::v2i64: return fastEmit_X86ISD_CVTP2SI_MVT_v2f64_MVT_v2i64_r(Op0, Op0IsKill); |
2471 | | default: return 0; |
2472 | | } |
2473 | | } |
2474 | | |
2475 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
2476 | 0 | if ((Subtarget->hasVLX())0 ) { |
2477 | 0 | return fastEmitInst_r(X86::VCVTPD2DQZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2478 | 0 | } |
2479 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
2480 | 0 | return fastEmitInst_r(X86::VCVTPD2DQYrr, &X86::VR128RegClass, Op0, Op0IsKill); |
2481 | 0 | } |
2482 | 0 | return 0; |
2483 | 0 | } |
2484 | | |
2485 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f64_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
2486 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2487 | 0 | return fastEmitInst_r(X86::VCVTPD2QQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2488 | 0 | } |
2489 | 0 | return 0; |
2490 | 0 | } |
2491 | | |
2492 | | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2493 | | switch (RetVT.SimpleTy) { |
2494 | | case MVT::v4i32: return fastEmit_X86ISD_CVTP2SI_MVT_v4f64_MVT_v4i32_r(Op0, Op0IsKill); |
2495 | | case MVT::v4i64: return fastEmit_X86ISD_CVTP2SI_MVT_v4f64_MVT_v4i64_r(Op0, Op0IsKill); |
2496 | | default: return 0; |
2497 | | } |
2498 | | } |
2499 | | |
2500 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f64_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
2501 | 0 | if ((Subtarget->hasAVX512())0 ) { |
2502 | 0 | return fastEmitInst_r(X86::VCVTPD2DQZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2503 | 0 | } |
2504 | 0 | return 0; |
2505 | 0 | } |
2506 | | |
2507 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f64_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
2508 | 0 | if ((Subtarget->hasDQI())0 ) { |
2509 | 0 | return fastEmitInst_r(X86::VCVTPD2QQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2510 | 0 | } |
2511 | 0 | return 0; |
2512 | 0 | } |
2513 | | |
2514 | | unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2515 | | switch (RetVT.SimpleTy) { |
2516 | | case MVT::v8i32: return fastEmit_X86ISD_CVTP2SI_MVT_v8f64_MVT_v8i32_r(Op0, Op0IsKill); |
2517 | | case MVT::v8i64: return fastEmit_X86ISD_CVTP2SI_MVT_v8f64_MVT_v8i64_r(Op0, Op0IsKill); |
2518 | | default: return 0; |
2519 | | } |
2520 | | } |
2521 | | |
2522 | | unsigned fastEmit_X86ISD_CVTP2SI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2523 | | switch (VT.SimpleTy) { |
2524 | | case MVT::v4f32: return fastEmit_X86ISD_CVTP2SI_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
2525 | | case MVT::v8f32: return fastEmit_X86ISD_CVTP2SI_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
2526 | | case MVT::v16f32: return fastEmit_X86ISD_CVTP2SI_MVT_v16f32_r(RetVT, Op0, Op0IsKill); |
2527 | | case MVT::v2f64: return fastEmit_X86ISD_CVTP2SI_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
2528 | | case MVT::v4f64: return fastEmit_X86ISD_CVTP2SI_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
2529 | | case MVT::v8f64: return fastEmit_X86ISD_CVTP2SI_MVT_v8f64_r(RetVT, Op0, Op0IsKill); |
2530 | | default: return 0; |
2531 | | } |
2532 | | } |
2533 | | |
2534 | | // FastEmit functions for X86ISD::CVTP2UI. |
2535 | | |
2536 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
2537 | 0 | if ((Subtarget->hasVLX())0 ) { |
2538 | 0 | return fastEmitInst_r(X86::VCVTPS2UDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2539 | 0 | } |
2540 | 0 | return 0; |
2541 | 0 | } |
2542 | | |
2543 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { |
2544 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2545 | 0 | return fastEmitInst_r(X86::VCVTPS2UQQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2546 | 0 | } |
2547 | 0 | return 0; |
2548 | 0 | } |
2549 | | |
2550 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
2551 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2552 | 0 | return fastEmitInst_r(X86::VCVTPS2UQQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2553 | 0 | } |
2554 | 0 | return 0; |
2555 | 0 | } |
2556 | | |
2557 | | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2558 | | switch (RetVT.SimpleTy) { |
2559 | | case MVT::v4i32: return fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v4i32_r(Op0, Op0IsKill); |
2560 | | case MVT::v2i64: return fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill); |
2561 | | case MVT::v4i64: return fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v4i64_r(Op0, Op0IsKill); |
2562 | | default: return 0; |
2563 | | } |
2564 | | } |
2565 | | |
2566 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f32_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
2567 | 0 | if ((Subtarget->hasVLX())0 ) { |
2568 | 0 | return fastEmitInst_r(X86::VCVTPS2UDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2569 | 0 | } |
2570 | 0 | return 0; |
2571 | 0 | } |
2572 | | |
2573 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f32_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
2574 | 0 | if ((Subtarget->hasDQI())0 ) { |
2575 | 0 | return fastEmitInst_r(X86::VCVTPS2UQQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2576 | 0 | } |
2577 | 0 | return 0; |
2578 | 0 | } |
2579 | | |
2580 | | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2581 | | switch (RetVT.SimpleTy) { |
2582 | | case MVT::v8i32: return fastEmit_X86ISD_CVTP2UI_MVT_v8f32_MVT_v8i32_r(Op0, Op0IsKill); |
2583 | | case MVT::v8i64: return fastEmit_X86ISD_CVTP2UI_MVT_v8f32_MVT_v8i64_r(Op0, Op0IsKill); |
2584 | | default: return 0; |
2585 | | } |
2586 | | } |
2587 | | |
2588 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v16f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2589 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
2590 | 0 | return 0; |
2591 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
2592 | 0 | return fastEmitInst_r(X86::VCVTPS2UDQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2593 | 0 | } |
2594 | 0 | return 0; |
2595 | 0 | } |
2596 | | |
2597 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
2598 | 0 | if ((Subtarget->hasVLX())0 ) { |
2599 | 0 | return fastEmitInst_r(X86::VCVTPD2UDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2600 | 0 | } |
2601 | 0 | return 0; |
2602 | 0 | } |
2603 | | |
2604 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v2f64_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { |
2605 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2606 | 0 | return fastEmitInst_r(X86::VCVTPD2UQQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2607 | 0 | } |
2608 | 0 | return 0; |
2609 | 0 | } |
2610 | | |
2611 | | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2612 | | switch (RetVT.SimpleTy) { |
2613 | | case MVT::v4i32: return fastEmit_X86ISD_CVTP2UI_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill); |
2614 | | case MVT::v2i64: return fastEmit_X86ISD_CVTP2UI_MVT_v2f64_MVT_v2i64_r(Op0, Op0IsKill); |
2615 | | default: return 0; |
2616 | | } |
2617 | | } |
2618 | | |
2619 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
2620 | 0 | if ((Subtarget->hasVLX())0 ) { |
2621 | 0 | return fastEmitInst_r(X86::VCVTPD2UDQZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2622 | 0 | } |
2623 | 0 | return 0; |
2624 | 0 | } |
2625 | | |
2626 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f64_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
2627 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2628 | 0 | return fastEmitInst_r(X86::VCVTPD2UQQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2629 | 0 | } |
2630 | 0 | return 0; |
2631 | 0 | } |
2632 | | |
2633 | | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2634 | | switch (RetVT.SimpleTy) { |
2635 | | case MVT::v4i32: return fastEmit_X86ISD_CVTP2UI_MVT_v4f64_MVT_v4i32_r(Op0, Op0IsKill); |
2636 | | case MVT::v4i64: return fastEmit_X86ISD_CVTP2UI_MVT_v4f64_MVT_v4i64_r(Op0, Op0IsKill); |
2637 | | default: return 0; |
2638 | | } |
2639 | | } |
2640 | | |
2641 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f64_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
2642 | 0 | if ((Subtarget->hasAVX512())0 ) { |
2643 | 0 | return fastEmitInst_r(X86::VCVTPD2UDQZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2644 | 0 | } |
2645 | 0 | return 0; |
2646 | 0 | } |
2647 | | |
2648 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f64_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
2649 | 0 | if ((Subtarget->hasDQI())0 ) { |
2650 | 0 | return fastEmitInst_r(X86::VCVTPD2UQQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2651 | 0 | } |
2652 | 0 | return 0; |
2653 | 0 | } |
2654 | | |
2655 | | unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2656 | | switch (RetVT.SimpleTy) { |
2657 | | case MVT::v8i32: return fastEmit_X86ISD_CVTP2UI_MVT_v8f64_MVT_v8i32_r(Op0, Op0IsKill); |
2658 | | case MVT::v8i64: return fastEmit_X86ISD_CVTP2UI_MVT_v8f64_MVT_v8i64_r(Op0, Op0IsKill); |
2659 | | default: return 0; |
2660 | | } |
2661 | | } |
2662 | | |
2663 | | unsigned fastEmit_X86ISD_CVTP2UI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2664 | | switch (VT.SimpleTy) { |
2665 | | case MVT::v4f32: return fastEmit_X86ISD_CVTP2UI_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
2666 | | case MVT::v8f32: return fastEmit_X86ISD_CVTP2UI_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
2667 | | case MVT::v16f32: return fastEmit_X86ISD_CVTP2UI_MVT_v16f32_r(RetVT, Op0, Op0IsKill); |
2668 | | case MVT::v2f64: return fastEmit_X86ISD_CVTP2UI_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
2669 | | case MVT::v4f64: return fastEmit_X86ISD_CVTP2UI_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
2670 | | case MVT::v8f64: return fastEmit_X86ISD_CVTP2UI_MVT_v8f64_r(RetVT, Op0, Op0IsKill); |
2671 | | default: return 0; |
2672 | | } |
2673 | | } |
2674 | | |
2675 | | // FastEmit functions for X86ISD::CVTSI2P. |
2676 | | |
2677 | 0 | unsigned fastEmit_X86ISD_CVTSI2P_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2678 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
2679 | 0 | return 0; |
2680 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2681 | 0 | return fastEmitInst_r(X86::VCVTDQ2PDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2682 | 0 | } |
2683 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
2684 | 0 | return fastEmitInst_r(X86::CVTDQ2PDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
2685 | 0 | } |
2686 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
2687 | 0 | return fastEmitInst_r(X86::VCVTDQ2PDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
2688 | 0 | } |
2689 | 0 | return 0; |
2690 | 0 | } |
2691 | | |
2692 | 0 | unsigned fastEmit_X86ISD_CVTSI2P_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2693 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
2694 | 0 | return 0; |
2695 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2696 | 0 | return fastEmitInst_r(X86::VCVTQQ2PSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2697 | 0 | } |
2698 | 0 | return 0; |
2699 | 0 | } |
2700 | | |
2701 | | unsigned fastEmit_X86ISD_CVTSI2P_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2702 | | switch (VT.SimpleTy) { |
2703 | | case MVT::v4i32: return fastEmit_X86ISD_CVTSI2P_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
2704 | | case MVT::v2i64: return fastEmit_X86ISD_CVTSI2P_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
2705 | | default: return 0; |
2706 | | } |
2707 | | } |
2708 | | |
2709 | | // FastEmit functions for X86ISD::CVTTP2SI. |
2710 | | |
2711 | 0 | unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2712 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
2713 | 0 | return 0; |
2714 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2715 | 0 | return fastEmitInst_r(X86::VCVTTPS2QQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2716 | 0 | } |
2717 | 0 | return 0; |
2718 | 0 | } |
2719 | | |
2720 | 0 | unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2721 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
2722 | 0 | return 0; |
2723 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2724 | 0 | return fastEmitInst_r(X86::VCVTTPD2DQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2725 | 0 | } |
2726 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
2727 | 0 | return fastEmitInst_r(X86::CVTTPD2DQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
2728 | 0 | } |
2729 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
2730 | 0 | return fastEmitInst_r(X86::VCVTTPD2DQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
2731 | 0 | } |
2732 | 0 | return 0; |
2733 | 0 | } |
2734 | | |
2735 | | unsigned fastEmit_X86ISD_CVTTP2SI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2736 | | switch (VT.SimpleTy) { |
2737 | | case MVT::v4f32: return fastEmit_X86ISD_CVTTP2SI_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
2738 | | case MVT::v2f64: return fastEmit_X86ISD_CVTTP2SI_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
2739 | | default: return 0; |
2740 | | } |
2741 | | } |
2742 | | |
2743 | | // FastEmit functions for X86ISD::CVTTP2UI. |
2744 | | |
2745 | 0 | unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2746 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
2747 | 0 | return 0; |
2748 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2749 | 0 | return fastEmitInst_r(X86::VCVTTPS2UQQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2750 | 0 | } |
2751 | 0 | return 0; |
2752 | 0 | } |
2753 | | |
2754 | 0 | unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2755 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
2756 | 0 | return 0; |
2757 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2758 | 0 | return fastEmitInst_r(X86::VCVTTPD2UDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2759 | 0 | } |
2760 | 0 | return 0; |
2761 | 0 | } |
2762 | | |
2763 | | unsigned fastEmit_X86ISD_CVTTP2UI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2764 | | switch (VT.SimpleTy) { |
2765 | | case MVT::v4f32: return fastEmit_X86ISD_CVTTP2UI_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
2766 | | case MVT::v2f64: return fastEmit_X86ISD_CVTTP2UI_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
2767 | | default: return 0; |
2768 | | } |
2769 | | } |
2770 | | |
2771 | | // FastEmit functions for X86ISD::CVTUI2P. |
2772 | | |
2773 | 0 | unsigned fastEmit_X86ISD_CVTUI2P_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2774 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
2775 | 0 | return 0; |
2776 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2777 | 0 | return fastEmitInst_r(X86::VCVTUDQ2PDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2778 | 0 | } |
2779 | 0 | return 0; |
2780 | 0 | } |
2781 | | |
2782 | 0 | unsigned fastEmit_X86ISD_CVTUI2P_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2783 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
2784 | 0 | return 0; |
2785 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
2786 | 0 | return fastEmitInst_r(X86::VCVTUQQ2PSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2787 | 0 | } |
2788 | 0 | return 0; |
2789 | 0 | } |
2790 | | |
2791 | | unsigned fastEmit_X86ISD_CVTUI2P_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2792 | | switch (VT.SimpleTy) { |
2793 | | case MVT::v4i32: return fastEmit_X86ISD_CVTUI2P_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
2794 | | case MVT::v2i64: return fastEmit_X86ISD_CVTUI2P_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
2795 | | default: return 0; |
2796 | | } |
2797 | | } |
2798 | | |
2799 | | // FastEmit functions for X86ISD::EH_RETURN. |
2800 | | |
2801 | 0 | unsigned fastEmit_X86ISD_EH_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2802 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
2803 | 0 | return 0; |
2804 | 0 | return fastEmitInst_r(X86::EH_RETURN, &X86::GR32RegClass, Op0, Op0IsKill); |
2805 | 0 | } |
2806 | | |
2807 | 0 | unsigned fastEmit_X86ISD_EH_RETURN_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2808 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
2809 | 0 | return 0; |
2810 | 0 | return fastEmitInst_r(X86::EH_RETURN64, &X86::GR64RegClass, Op0, Op0IsKill); |
2811 | 0 | } |
2812 | | |
2813 | | unsigned fastEmit_X86ISD_EH_RETURN_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2814 | | switch (VT.SimpleTy) { |
2815 | | case MVT::i32: return fastEmit_X86ISD_EH_RETURN_MVT_i32_r(RetVT, Op0, Op0IsKill); |
2816 | | case MVT::i64: return fastEmit_X86ISD_EH_RETURN_MVT_i64_r(RetVT, Op0, Op0IsKill); |
2817 | | default: return 0; |
2818 | | } |
2819 | | } |
2820 | | |
2821 | | // FastEmit functions for X86ISD::EXPAND. |
2822 | | |
2823 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2824 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
2825 | 0 | return 0; |
2826 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2827 | 0 | return fastEmitInst_r(X86::VPEXPANDDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2828 | 0 | } |
2829 | 0 | return 0; |
2830 | 0 | } |
2831 | | |
2832 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2833 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
2834 | 0 | return 0; |
2835 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2836 | 0 | return fastEmitInst_r(X86::VPEXPANDDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2837 | 0 | } |
2838 | 0 | return 0; |
2839 | 0 | } |
2840 | | |
2841 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2842 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
2843 | 0 | return 0; |
2844 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
2845 | 0 | return fastEmitInst_r(X86::VPEXPANDDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2846 | 0 | } |
2847 | 0 | return 0; |
2848 | 0 | } |
2849 | | |
2850 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2851 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
2852 | 0 | return 0; |
2853 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2854 | 0 | return fastEmitInst_r(X86::VPEXPANDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2855 | 0 | } |
2856 | 0 | return 0; |
2857 | 0 | } |
2858 | | |
2859 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v4i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2860 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
2861 | 0 | return 0; |
2862 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2863 | 0 | return fastEmitInst_r(X86::VPEXPANDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2864 | 0 | } |
2865 | 0 | return 0; |
2866 | 0 | } |
2867 | | |
2868 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2869 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
2870 | 0 | return 0; |
2871 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
2872 | 0 | return fastEmitInst_r(X86::VPEXPANDQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2873 | 0 | } |
2874 | 0 | return 0; |
2875 | 0 | } |
2876 | | |
2877 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2878 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
2879 | 0 | return 0; |
2880 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2881 | 0 | return fastEmitInst_r(X86::VEXPANDPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2882 | 0 | } |
2883 | 0 | return 0; |
2884 | 0 | } |
2885 | | |
2886 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2887 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
2888 | 0 | return 0; |
2889 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2890 | 0 | return fastEmitInst_r(X86::VEXPANDPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2891 | 0 | } |
2892 | 0 | return 0; |
2893 | 0 | } |
2894 | | |
2895 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v16f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2896 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
2897 | 0 | return 0; |
2898 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
2899 | 0 | return fastEmitInst_r(X86::VEXPANDPSZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2900 | 0 | } |
2901 | 0 | return 0; |
2902 | 0 | } |
2903 | | |
2904 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2905 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
2906 | 0 | return 0; |
2907 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2908 | 0 | return fastEmitInst_r(X86::VEXPANDPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
2909 | 0 | } |
2910 | 0 | return 0; |
2911 | 0 | } |
2912 | | |
2913 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2914 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
2915 | 0 | return 0; |
2916 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2917 | 0 | return fastEmitInst_r(X86::VEXPANDPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
2918 | 0 | } |
2919 | 0 | return 0; |
2920 | 0 | } |
2921 | | |
2922 | 0 | unsigned fastEmit_X86ISD_EXPAND_MVT_v8f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2923 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
2924 | 0 | return 0; |
2925 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
2926 | 0 | return fastEmitInst_r(X86::VEXPANDPDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
2927 | 0 | } |
2928 | 0 | return 0; |
2929 | 0 | } |
2930 | | |
2931 | | unsigned fastEmit_X86ISD_EXPAND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2932 | | switch (VT.SimpleTy) { |
2933 | | case MVT::v4i32: return fastEmit_X86ISD_EXPAND_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
2934 | | case MVT::v8i32: return fastEmit_X86ISD_EXPAND_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
2935 | | case MVT::v16i32: return fastEmit_X86ISD_EXPAND_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
2936 | | case MVT::v2i64: return fastEmit_X86ISD_EXPAND_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
2937 | | case MVT::v4i64: return fastEmit_X86ISD_EXPAND_MVT_v4i64_r(RetVT, Op0, Op0IsKill); |
2938 | | case MVT::v8i64: return fastEmit_X86ISD_EXPAND_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
2939 | | case MVT::v4f32: return fastEmit_X86ISD_EXPAND_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
2940 | | case MVT::v8f32: return fastEmit_X86ISD_EXPAND_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
2941 | | case MVT::v16f32: return fastEmit_X86ISD_EXPAND_MVT_v16f32_r(RetVT, Op0, Op0IsKill); |
2942 | | case MVT::v2f64: return fastEmit_X86ISD_EXPAND_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
2943 | | case MVT::v4f64: return fastEmit_X86ISD_EXPAND_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
2944 | | case MVT::v8f64: return fastEmit_X86ISD_EXPAND_MVT_v8f64_r(RetVT, Op0, Op0IsKill); |
2945 | | default: return 0; |
2946 | | } |
2947 | | } |
2948 | | |
2949 | | // FastEmit functions for X86ISD::FRCP. |
2950 | | |
2951 | 0 | unsigned fastEmit_X86ISD_FRCP_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2952 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2953 | 0 | return 0; |
2954 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
2955 | 0 | return fastEmitInst_r(X86::RCPSSr, &X86::FR32RegClass, Op0, Op0IsKill); |
2956 | 0 | } |
2957 | 0 | return 0; |
2958 | 0 | } |
2959 | | |
2960 | 0 | unsigned fastEmit_X86ISD_FRCP_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2961 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
2962 | 0 | return 0; |
2963 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2964 | 0 | return fastEmitInst_r(X86::VRCP14PSZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
2965 | 0 | } |
2966 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
2967 | 0 | return fastEmitInst_r(X86::RCPPSr, &X86::VR128RegClass, Op0, Op0IsKill); |
2968 | 0 | } |
2969 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
2970 | 0 | return fastEmitInst_r(X86::VRCPPSr, &X86::VR128RegClass, Op0, Op0IsKill); |
2971 | 0 | } |
2972 | 0 | return 0; |
2973 | 0 | } |
2974 | | |
2975 | 0 | unsigned fastEmit_X86ISD_FRCP_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2976 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
2977 | 0 | return 0; |
2978 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
2979 | 0 | return fastEmitInst_r(X86::VRCP14PSZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
2980 | 0 | } |
2981 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
2982 | 0 | return fastEmitInst_r(X86::VRCPPSYr, &X86::VR256RegClass, Op0, Op0IsKill); |
2983 | 0 | } |
2984 | 0 | return 0; |
2985 | 0 | } |
2986 | | |
2987 | 0 | unsigned fastEmit_X86ISD_FRCP_MVT_v16f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2988 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
2989 | 0 | return 0; |
2990 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
2991 | 0 | return fastEmitInst_r(X86::VRCP14PSZr, &X86::VR512RegClass, Op0, Op0IsKill); |
2992 | 0 | } |
2993 | 0 | return 0; |
2994 | 0 | } |
2995 | | |
2996 | 0 | unsigned fastEmit_X86ISD_FRCP_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
2997 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
2998 | 0 | return 0; |
2999 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
3000 | 0 | return fastEmitInst_r(X86::VRCP14PDZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
3001 | 0 | } |
3002 | 0 | return 0; |
3003 | 0 | } |
3004 | | |
3005 | 0 | unsigned fastEmit_X86ISD_FRCP_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3006 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
3007 | 0 | return 0; |
3008 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
3009 | 0 | return fastEmitInst_r(X86::VRCP14PDZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
3010 | 0 | } |
3011 | 0 | return 0; |
3012 | 0 | } |
3013 | | |
3014 | 0 | unsigned fastEmit_X86ISD_FRCP_MVT_v8f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3015 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
3016 | 0 | return 0; |
3017 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
3018 | 0 | return fastEmitInst_r(X86::VRCP14PDZr, &X86::VR512RegClass, Op0, Op0IsKill); |
3019 | 0 | } |
3020 | 0 | return 0; |
3021 | 0 | } |
3022 | | |
3023 | | unsigned fastEmit_X86ISD_FRCP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3024 | | switch (VT.SimpleTy) { |
3025 | | case MVT::f32: return fastEmit_X86ISD_FRCP_MVT_f32_r(RetVT, Op0, Op0IsKill); |
3026 | | case MVT::v4f32: return fastEmit_X86ISD_FRCP_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
3027 | | case MVT::v8f32: return fastEmit_X86ISD_FRCP_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
3028 | | case MVT::v16f32: return fastEmit_X86ISD_FRCP_MVT_v16f32_r(RetVT, Op0, Op0IsKill); |
3029 | | case MVT::v2f64: return fastEmit_X86ISD_FRCP_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
3030 | | case MVT::v4f64: return fastEmit_X86ISD_FRCP_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
3031 | | case MVT::v8f64: return fastEmit_X86ISD_FRCP_MVT_v8f64_r(RetVT, Op0, Op0IsKill); |
3032 | | default: return 0; |
3033 | | } |
3034 | | } |
3035 | | |
3036 | | // FastEmit functions for X86ISD::FRSQRT. |
3037 | | |
3038 | 0 | unsigned fastEmit_X86ISD_FRSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3039 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3040 | 0 | return 0; |
3041 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
3042 | 0 | return fastEmitInst_r(X86::RSQRTSSr, &X86::FR32RegClass, Op0, Op0IsKill); |
3043 | 0 | } |
3044 | 0 | return 0; |
3045 | 0 | } |
3046 | | |
3047 | 0 | unsigned fastEmit_X86ISD_FRSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3048 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3049 | 0 | return 0; |
3050 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
3051 | 0 | return fastEmitInst_r(X86::VRSQRT14PSZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
3052 | 0 | } |
3053 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
3054 | 0 | return fastEmitInst_r(X86::RSQRTPSr, &X86::VR128RegClass, Op0, Op0IsKill); |
3055 | 0 | } |
3056 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3057 | 0 | return fastEmitInst_r(X86::VRSQRTPSr, &X86::VR128RegClass, Op0, Op0IsKill); |
3058 | 0 | } |
3059 | 0 | return 0; |
3060 | 0 | } |
3061 | | |
3062 | 0 | unsigned fastEmit_X86ISD_FRSQRT_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3063 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
3064 | 0 | return 0; |
3065 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
3066 | 0 | return fastEmitInst_r(X86::VRSQRT14PSZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
3067 | 0 | } |
3068 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3069 | 0 | return fastEmitInst_r(X86::VRSQRTPSYr, &X86::VR256RegClass, Op0, Op0IsKill); |
3070 | 0 | } |
3071 | 0 | return 0; |
3072 | 0 | } |
3073 | | |
3074 | 0 | unsigned fastEmit_X86ISD_FRSQRT_MVT_v16f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3075 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
3076 | 0 | return 0; |
3077 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
3078 | 0 | return fastEmitInst_r(X86::VRSQRT14PSZr, &X86::VR512RegClass, Op0, Op0IsKill); |
3079 | 0 | } |
3080 | 0 | return 0; |
3081 | 0 | } |
3082 | | |
3083 | 0 | unsigned fastEmit_X86ISD_FRSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3084 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3085 | 0 | return 0; |
3086 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
3087 | 0 | return fastEmitInst_r(X86::VRSQRT14PDZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
3088 | 0 | } |
3089 | 0 | return 0; |
3090 | 0 | } |
3091 | | |
3092 | 0 | unsigned fastEmit_X86ISD_FRSQRT_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3093 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
3094 | 0 | return 0; |
3095 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
3096 | 0 | return fastEmitInst_r(X86::VRSQRT14PDZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
3097 | 0 | } |
3098 | 0 | return 0; |
3099 | 0 | } |
3100 | | |
3101 | 0 | unsigned fastEmit_X86ISD_FRSQRT_MVT_v8f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3102 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
3103 | 0 | return 0; |
3104 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
3105 | 0 | return fastEmitInst_r(X86::VRSQRT14PDZr, &X86::VR512RegClass, Op0, Op0IsKill); |
3106 | 0 | } |
3107 | 0 | return 0; |
3108 | 0 | } |
3109 | | |
3110 | | unsigned fastEmit_X86ISD_FRSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3111 | | switch (VT.SimpleTy) { |
3112 | | case MVT::f32: return fastEmit_X86ISD_FRSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill); |
3113 | | case MVT::v4f32: return fastEmit_X86ISD_FRSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
3114 | | case MVT::v8f32: return fastEmit_X86ISD_FRSQRT_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
3115 | | case MVT::v16f32: return fastEmit_X86ISD_FRSQRT_MVT_v16f32_r(RetVT, Op0, Op0IsKill); |
3116 | | case MVT::v2f64: return fastEmit_X86ISD_FRSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
3117 | | case MVT::v4f64: return fastEmit_X86ISD_FRSQRT_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
3118 | | case MVT::v8f64: return fastEmit_X86ISD_FRSQRT_MVT_v8f64_r(RetVT, Op0, Op0IsKill); |
3119 | | default: return 0; |
3120 | | } |
3121 | | } |
3122 | | |
3123 | | // FastEmit functions for X86ISD::MMX_MOVD2W. |
3124 | | |
3125 | 0 | unsigned fastEmit_X86ISD_MMX_MOVD2W_MVT_x86mmx_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3126 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3127 | 0 | return 0; |
3128 | 0 | if (0 (Subtarget->hasMMX())0 ) { |
3129 | 0 | return fastEmitInst_r(X86::MMX_MOVD64grr, &X86::GR32RegClass, Op0, Op0IsKill); |
3130 | 0 | } |
3131 | 0 | return 0; |
3132 | 0 | } |
3133 | | |
3134 | | unsigned fastEmit_X86ISD_MMX_MOVD2W_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3135 | | switch (VT.SimpleTy) { |
3136 | | case MVT::x86mmx: return fastEmit_X86ISD_MMX_MOVD2W_MVT_x86mmx_r(RetVT, Op0, Op0IsKill); |
3137 | | default: return 0; |
3138 | | } |
3139 | | } |
3140 | | |
3141 | | // FastEmit functions for X86ISD::MMX_MOVW2D. |
3142 | | |
3143 | 0 | unsigned fastEmit_X86ISD_MMX_MOVW2D_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3144 | 0 | if (RetVT.SimpleTy != MVT::x86mmx) |
3145 | 0 | return 0; |
3146 | 0 | if (0 (Subtarget->hasMMX())0 ) { |
3147 | 0 | return fastEmitInst_r(X86::MMX_MOVD64rr, &X86::VR64RegClass, Op0, Op0IsKill); |
3148 | 0 | } |
3149 | 0 | return 0; |
3150 | 0 | } |
3151 | | |
3152 | | unsigned fastEmit_X86ISD_MMX_MOVW2D_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3153 | | switch (VT.SimpleTy) { |
3154 | | case MVT::i32: return fastEmit_X86ISD_MMX_MOVW2D_MVT_i32_r(RetVT, Op0, Op0IsKill); |
3155 | | default: return 0; |
3156 | | } |
3157 | | } |
3158 | | |
3159 | | // FastEmit functions for X86ISD::MOVDDUP. |
3160 | | |
3161 | 0 | unsigned fastEmit_X86ISD_MOVDDUP_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3162 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3163 | 0 | return 0; |
3164 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3165 | 0 | return fastEmitInst_r(X86::VMOVDDUPZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
3166 | 0 | } |
3167 | 0 | if (0 (Subtarget->hasSSE3() && 0 !Subtarget->hasAVX()0 )) { |
3168 | 0 | return fastEmitInst_r(X86::MOVDDUPrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3169 | 0 | } |
3170 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3171 | 0 | return fastEmitInst_r(X86::VMOVDDUPrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3172 | 0 | } |
3173 | 0 | return 0; |
3174 | 0 | } |
3175 | | |
3176 | 0 | unsigned fastEmit_X86ISD_MOVDDUP_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3177 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
3178 | 0 | return 0; |
3179 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3180 | 0 | return fastEmitInst_r(X86::VMOVDDUPZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
3181 | 0 | } |
3182 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3183 | 0 | return fastEmitInst_r(X86::VMOVDDUPYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3184 | 0 | } |
3185 | 0 | return 0; |
3186 | 0 | } |
3187 | | |
3188 | 0 | unsigned fastEmit_X86ISD_MOVDDUP_MVT_v8f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3189 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
3190 | 0 | return 0; |
3191 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
3192 | 0 | return fastEmitInst_r(X86::VMOVDDUPZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
3193 | 0 | } |
3194 | 0 | return 0; |
3195 | 0 | } |
3196 | | |
3197 | | unsigned fastEmit_X86ISD_MOVDDUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3198 | | switch (VT.SimpleTy) { |
3199 | | case MVT::v2f64: return fastEmit_X86ISD_MOVDDUP_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
3200 | | case MVT::v4f64: return fastEmit_X86ISD_MOVDDUP_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
3201 | | case MVT::v8f64: return fastEmit_X86ISD_MOVDDUP_MVT_v8f64_r(RetVT, Op0, Op0IsKill); |
3202 | | default: return 0; |
3203 | | } |
3204 | | } |
3205 | | |
3206 | | // FastEmit functions for X86ISD::MOVDQ2Q. |
3207 | | |
3208 | 0 | unsigned fastEmit_X86ISD_MOVDQ2Q_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3209 | 0 | if (RetVT.SimpleTy != MVT::x86mmx) |
3210 | 0 | return 0; |
3211 | 0 | return fastEmitInst_r(X86::MMX_MOVDQ2Qrr, &X86::VR64RegClass, Op0, Op0IsKill); |
3212 | 0 | } |
3213 | | |
3214 | | unsigned fastEmit_X86ISD_MOVDQ2Q_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3215 | | switch (VT.SimpleTy) { |
3216 | | case MVT::v2i64: return fastEmit_X86ISD_MOVDQ2Q_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
3217 | | default: return 0; |
3218 | | } |
3219 | | } |
3220 | | |
3221 | | // FastEmit functions for X86ISD::MOVMSK. |
3222 | | |
3223 | 0 | unsigned fastEmit_X86ISD_MOVMSK_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3224 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3225 | 0 | return 0; |
3226 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
3227 | 0 | return fastEmitInst_r(X86::PMOVMSKBrr, &X86::GR32RegClass, Op0, Op0IsKill); |
3228 | 0 | } |
3229 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
3230 | 0 | return fastEmitInst_r(X86::VPMOVMSKBrr, &X86::GR32RegClass, Op0, Op0IsKill); |
3231 | 0 | } |
3232 | 0 | return 0; |
3233 | 0 | } |
3234 | | |
3235 | 0 | unsigned fastEmit_X86ISD_MOVMSK_MVT_v32i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3236 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3237 | 0 | return 0; |
3238 | 0 | if (0 (Subtarget->hasAVX2())0 ) { |
3239 | 0 | return fastEmitInst_r(X86::VPMOVMSKBYrr, &X86::GR32RegClass, Op0, Op0IsKill); |
3240 | 0 | } |
3241 | 0 | return 0; |
3242 | 0 | } |
3243 | | |
3244 | 0 | unsigned fastEmit_X86ISD_MOVMSK_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3245 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3246 | 0 | return 0; |
3247 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
3248 | 0 | return fastEmitInst_r(X86::MOVMSKPSrr, &X86::GR32RegClass, Op0, Op0IsKill); |
3249 | 0 | } |
3250 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
3251 | 0 | return fastEmitInst_r(X86::VMOVMSKPSrr, &X86::GR32RegClass, Op0, Op0IsKill); |
3252 | 0 | } |
3253 | 0 | return 0; |
3254 | 0 | } |
3255 | | |
3256 | 0 | unsigned fastEmit_X86ISD_MOVMSK_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3257 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3258 | 0 | return 0; |
3259 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
3260 | 0 | return fastEmitInst_r(X86::VMOVMSKPSYrr, &X86::GR32RegClass, Op0, Op0IsKill); |
3261 | 0 | } |
3262 | 0 | return 0; |
3263 | 0 | } |
3264 | | |
3265 | 0 | unsigned fastEmit_X86ISD_MOVMSK_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3266 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3267 | 0 | return 0; |
3268 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
3269 | 0 | return fastEmitInst_r(X86::MOVMSKPDrr, &X86::GR32RegClass, Op0, Op0IsKill); |
3270 | 0 | } |
3271 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
3272 | 0 | return fastEmitInst_r(X86::VMOVMSKPDrr, &X86::GR32RegClass, Op0, Op0IsKill); |
3273 | 0 | } |
3274 | 0 | return 0; |
3275 | 0 | } |
3276 | | |
3277 | 0 | unsigned fastEmit_X86ISD_MOVMSK_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3278 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3279 | 0 | return 0; |
3280 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
3281 | 0 | return fastEmitInst_r(X86::VMOVMSKPDYrr, &X86::GR32RegClass, Op0, Op0IsKill); |
3282 | 0 | } |
3283 | 0 | return 0; |
3284 | 0 | } |
3285 | | |
3286 | | unsigned fastEmit_X86ISD_MOVMSK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3287 | | switch (VT.SimpleTy) { |
3288 | | case MVT::v16i8: return fastEmit_X86ISD_MOVMSK_MVT_v16i8_r(RetVT, Op0, Op0IsKill); |
3289 | | case MVT::v32i8: return fastEmit_X86ISD_MOVMSK_MVT_v32i8_r(RetVT, Op0, Op0IsKill); |
3290 | | case MVT::v4f32: return fastEmit_X86ISD_MOVMSK_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
3291 | | case MVT::v8f32: return fastEmit_X86ISD_MOVMSK_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
3292 | | case MVT::v2f64: return fastEmit_X86ISD_MOVMSK_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
3293 | | case MVT::v4f64: return fastEmit_X86ISD_MOVMSK_MVT_v4f64_r(RetVT, Op0, Op0IsKill); |
3294 | | default: return 0; |
3295 | | } |
3296 | | } |
3297 | | |
3298 | | // FastEmit functions for X86ISD::MOVSHDUP. |
3299 | | |
3300 | 0 | unsigned fastEmit_X86ISD_MOVSHDUP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3301 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3302 | 0 | return 0; |
3303 | 0 | if (0 (Subtarget->hasSSE3() && 0 !Subtarget->hasAVX()0 )) { |
3304 | 0 | return fastEmitInst_r(X86::MOVSHDUPrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3305 | 0 | } |
3306 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3307 | 0 | return fastEmitInst_r(X86::VMOVSHDUPrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3308 | 0 | } |
3309 | 0 | return 0; |
3310 | 0 | } |
3311 | | |
3312 | 0 | unsigned fastEmit_X86ISD_MOVSHDUP_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3313 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
3314 | 0 | return 0; |
3315 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3316 | 0 | return fastEmitInst_r(X86::VMOVSHDUPYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3317 | 0 | } |
3318 | 0 | return 0; |
3319 | 0 | } |
3320 | | |
3321 | 0 | unsigned fastEmit_X86ISD_MOVSHDUP_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3322 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3323 | 0 | return 0; |
3324 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3325 | 0 | return fastEmitInst_r(X86::VMOVSHDUPZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
3326 | 0 | } |
3327 | 0 | if (0 (Subtarget->hasSSE3() && 0 !Subtarget->hasAVX()0 )) { |
3328 | 0 | return fastEmitInst_r(X86::MOVSHDUPrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3329 | 0 | } |
3330 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3331 | 0 | return fastEmitInst_r(X86::VMOVSHDUPrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3332 | 0 | } |
3333 | 0 | return 0; |
3334 | 0 | } |
3335 | | |
3336 | 0 | unsigned fastEmit_X86ISD_MOVSHDUP_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3337 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
3338 | 0 | return 0; |
3339 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3340 | 0 | return fastEmitInst_r(X86::VMOVSHDUPZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
3341 | 0 | } |
3342 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3343 | 0 | return fastEmitInst_r(X86::VMOVSHDUPYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3344 | 0 | } |
3345 | 0 | return 0; |
3346 | 0 | } |
3347 | | |
3348 | 0 | unsigned fastEmit_X86ISD_MOVSHDUP_MVT_v16f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3349 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
3350 | 0 | return 0; |
3351 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
3352 | 0 | return fastEmitInst_r(X86::VMOVSHDUPZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
3353 | 0 | } |
3354 | 0 | return 0; |
3355 | 0 | } |
3356 | | |
3357 | | unsigned fastEmit_X86ISD_MOVSHDUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3358 | | switch (VT.SimpleTy) { |
3359 | | case MVT::v4i32: return fastEmit_X86ISD_MOVSHDUP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
3360 | | case MVT::v8i32: return fastEmit_X86ISD_MOVSHDUP_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
3361 | | case MVT::v4f32: return fastEmit_X86ISD_MOVSHDUP_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
3362 | | case MVT::v8f32: return fastEmit_X86ISD_MOVSHDUP_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
3363 | | case MVT::v16f32: return fastEmit_X86ISD_MOVSHDUP_MVT_v16f32_r(RetVT, Op0, Op0IsKill); |
3364 | | default: return 0; |
3365 | | } |
3366 | | } |
3367 | | |
3368 | | // FastEmit functions for X86ISD::MOVSLDUP. |
3369 | | |
3370 | 0 | unsigned fastEmit_X86ISD_MOVSLDUP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3371 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3372 | 0 | return 0; |
3373 | 0 | if (0 (Subtarget->hasSSE3() && 0 !Subtarget->hasAVX()0 )) { |
3374 | 0 | return fastEmitInst_r(X86::MOVSLDUPrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3375 | 0 | } |
3376 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3377 | 0 | return fastEmitInst_r(X86::VMOVSLDUPrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3378 | 0 | } |
3379 | 0 | return 0; |
3380 | 0 | } |
3381 | | |
3382 | 0 | unsigned fastEmit_X86ISD_MOVSLDUP_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3383 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
3384 | 0 | return 0; |
3385 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3386 | 0 | return fastEmitInst_r(X86::VMOVSLDUPYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3387 | 0 | } |
3388 | 0 | return 0; |
3389 | 0 | } |
3390 | | |
3391 | 0 | unsigned fastEmit_X86ISD_MOVSLDUP_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3392 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3393 | 0 | return 0; |
3394 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3395 | 0 | return fastEmitInst_r(X86::VMOVSLDUPZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
3396 | 0 | } |
3397 | 0 | if (0 (Subtarget->hasSSE3() && 0 !Subtarget->hasAVX()0 )) { |
3398 | 0 | return fastEmitInst_r(X86::MOVSLDUPrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3399 | 0 | } |
3400 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3401 | 0 | return fastEmitInst_r(X86::VMOVSLDUPrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3402 | 0 | } |
3403 | 0 | return 0; |
3404 | 0 | } |
3405 | | |
3406 | 0 | unsigned fastEmit_X86ISD_MOVSLDUP_MVT_v8f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3407 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
3408 | 0 | return 0; |
3409 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3410 | 0 | return fastEmitInst_r(X86::VMOVSLDUPZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
3411 | 0 | } |
3412 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3413 | 0 | return fastEmitInst_r(X86::VMOVSLDUPYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3414 | 0 | } |
3415 | 0 | return 0; |
3416 | 0 | } |
3417 | | |
3418 | 0 | unsigned fastEmit_X86ISD_MOVSLDUP_MVT_v16f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3419 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
3420 | 0 | return 0; |
3421 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
3422 | 0 | return fastEmitInst_r(X86::VMOVSLDUPZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
3423 | 0 | } |
3424 | 0 | return 0; |
3425 | 0 | } |
3426 | | |
3427 | | unsigned fastEmit_X86ISD_MOVSLDUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3428 | | switch (VT.SimpleTy) { |
3429 | | case MVT::v4i32: return fastEmit_X86ISD_MOVSLDUP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
3430 | | case MVT::v8i32: return fastEmit_X86ISD_MOVSLDUP_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
3431 | | case MVT::v4f32: return fastEmit_X86ISD_MOVSLDUP_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
3432 | | case MVT::v8f32: return fastEmit_X86ISD_MOVSLDUP_MVT_v8f32_r(RetVT, Op0, Op0IsKill); |
3433 | | case MVT::v16f32: return fastEmit_X86ISD_MOVSLDUP_MVT_v16f32_r(RetVT, Op0, Op0IsKill); |
3434 | | default: return 0; |
3435 | | } |
3436 | | } |
3437 | | |
3438 | | // FastEmit functions for X86ISD::SEG_ALLOCA. |
3439 | | |
3440 | 0 | unsigned fastEmit_X86ISD_SEG_ALLOCA_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3441 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3442 | 0 | return 0; |
3443 | 0 | if (0 (!Subtarget->isTarget64BitLP64())0 ) { |
3444 | 0 | return fastEmitInst_r(X86::SEG_ALLOCA_32, &X86::GR32RegClass, Op0, Op0IsKill); |
3445 | 0 | } |
3446 | 0 | return 0; |
3447 | 0 | } |
3448 | | |
3449 | 0 | unsigned fastEmit_X86ISD_SEG_ALLOCA_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3450 | 0 | if (RetVT.SimpleTy != MVT::i64) |
3451 | 0 | return 0; |
3452 | 0 | if (0 (Subtarget->is64Bit())0 ) { |
3453 | 0 | return fastEmitInst_r(X86::SEG_ALLOCA_64, &X86::GR64RegClass, Op0, Op0IsKill); |
3454 | 0 | } |
3455 | 0 | return 0; |
3456 | 0 | } |
3457 | | |
3458 | | unsigned fastEmit_X86ISD_SEG_ALLOCA_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3459 | | switch (VT.SimpleTy) { |
3460 | | case MVT::i32: return fastEmit_X86ISD_SEG_ALLOCA_MVT_i32_r(RetVT, Op0, Op0IsKill); |
3461 | | case MVT::i64: return fastEmit_X86ISD_SEG_ALLOCA_MVT_i64_r(RetVT, Op0, Op0IsKill); |
3462 | | default: return 0; |
3463 | | } |
3464 | | } |
3465 | | |
3466 | | // FastEmit functions for X86ISD::VBROADCAST. |
3467 | | |
3468 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
3469 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3470 | 0 | return fastEmitInst_r(X86::VPBROADCASTDrZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
3471 | 0 | } |
3472 | 0 | return 0; |
3473 | 0 | } |
3474 | | |
3475 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
3476 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3477 | 0 | return fastEmitInst_r(X86::VPBROADCASTDrZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
3478 | 0 | } |
3479 | 0 | return 0; |
3480 | 0 | } |
3481 | | |
3482 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v16i32_r(unsigned Op0, bool Op0IsKill) { |
3483 | 0 | if ((Subtarget->hasAVX512())0 ) { |
3484 | 0 | return fastEmitInst_r(X86::VPBROADCASTDrZr, &X86::VR512RegClass, Op0, Op0IsKill); |
3485 | 0 | } |
3486 | 0 | return 0; |
3487 | 0 | } |
3488 | | |
3489 | | unsigned fastEmit_X86ISD_VBROADCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3490 | | switch (RetVT.SimpleTy) { |
3491 | | case MVT::v4i32: return fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill); |
3492 | | case MVT::v8i32: return fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v8i32_r(Op0, Op0IsKill); |
3493 | | case MVT::v16i32: return fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v16i32_r(Op0, Op0IsKill); |
3494 | | default: return 0; |
3495 | | } |
3496 | | } |
3497 | | |
3498 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { |
3499 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3500 | 0 | return fastEmitInst_r(X86::VPBROADCASTQrZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
3501 | 0 | } |
3502 | 0 | return 0; |
3503 | 0 | } |
3504 | | |
3505 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
3506 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3507 | 0 | return fastEmitInst_r(X86::VPBROADCASTQrZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
3508 | 0 | } |
3509 | 0 | return 0; |
3510 | 0 | } |
3511 | | |
3512 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
3513 | 0 | if ((Subtarget->hasAVX512())0 ) { |
3514 | 0 | return fastEmitInst_r(X86::VPBROADCASTQrZr, &X86::VR512RegClass, Op0, Op0IsKill); |
3515 | 0 | } |
3516 | 0 | return 0; |
3517 | 0 | } |
3518 | | |
3519 | | unsigned fastEmit_X86ISD_VBROADCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3520 | | switch (RetVT.SimpleTy) { |
3521 | | case MVT::v2i64: return fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v2i64_r(Op0, Op0IsKill); |
3522 | | case MVT::v4i64: return fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v4i64_r(Op0, Op0IsKill); |
3523 | | case MVT::v8i64: return fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v8i64_r(Op0, Op0IsKill); |
3524 | | default: return 0; |
3525 | | } |
3526 | | } |
3527 | | |
3528 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
3529 | 0 | if ((Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
3530 | 0 | return fastEmitInst_r(X86::VPBROADCASTBZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
3531 | 0 | } |
3532 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
3533 | 0 | return fastEmitInst_r(X86::VPBROADCASTBrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3534 | 0 | } |
3535 | 0 | return 0; |
3536 | 0 | } |
3537 | | |
3538 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v32i8_r(unsigned Op0, bool Op0IsKill) { |
3539 | 0 | if ((Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
3540 | 0 | return fastEmitInst_r(X86::VPBROADCASTBZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
3541 | 0 | } |
3542 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
3543 | 0 | return fastEmitInst_r(X86::VPBROADCASTBYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3544 | 0 | } |
3545 | 0 | return 0; |
3546 | 0 | } |
3547 | | |
3548 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v64i8_r(unsigned Op0, bool Op0IsKill) { |
3549 | 0 | if ((Subtarget->hasBWI())0 ) { |
3550 | 0 | return fastEmitInst_r(X86::VPBROADCASTBZr, &X86::VR512RegClass, Op0, Op0IsKill); |
3551 | 0 | } |
3552 | 0 | return 0; |
3553 | 0 | } |
3554 | | |
3555 | | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3556 | | switch (RetVT.SimpleTy) { |
3557 | | case MVT::v16i8: return fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v16i8_r(Op0, Op0IsKill); |
3558 | | case MVT::v32i8: return fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v32i8_r(Op0, Op0IsKill); |
3559 | | case MVT::v64i8: return fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v64i8_r(Op0, Op0IsKill); |
3560 | | default: return 0; |
3561 | | } |
3562 | | } |
3563 | | |
3564 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
3565 | 0 | if ((Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
3566 | 0 | return fastEmitInst_r(X86::VPBROADCASTWZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
3567 | 0 | } |
3568 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
3569 | 0 | return fastEmitInst_r(X86::VPBROADCASTWrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3570 | 0 | } |
3571 | 0 | return 0; |
3572 | 0 | } |
3573 | | |
3574 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v16i16_r(unsigned Op0, bool Op0IsKill) { |
3575 | 0 | if ((Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
3576 | 0 | return fastEmitInst_r(X86::VPBROADCASTWZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
3577 | 0 | } |
3578 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
3579 | 0 | return fastEmitInst_r(X86::VPBROADCASTWYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3580 | 0 | } |
3581 | 0 | return 0; |
3582 | 0 | } |
3583 | | |
3584 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v32i16_r(unsigned Op0, bool Op0IsKill) { |
3585 | 0 | if ((Subtarget->hasBWI())0 ) { |
3586 | 0 | return fastEmitInst_r(X86::VPBROADCASTWZr, &X86::VR512RegClass, Op0, Op0IsKill); |
3587 | 0 | } |
3588 | 0 | return 0; |
3589 | 0 | } |
3590 | | |
3591 | | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3592 | | switch (RetVT.SimpleTy) { |
3593 | | case MVT::v8i16: return fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v8i16_r(Op0, Op0IsKill); |
3594 | | case MVT::v16i16: return fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v16i16_r(Op0, Op0IsKill); |
3595 | | case MVT::v32i16: return fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v32i16_r(Op0, Op0IsKill); |
3596 | | default: return 0; |
3597 | | } |
3598 | | } |
3599 | | |
3600 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
3601 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3602 | 0 | return fastEmitInst_r(X86::VPBROADCASTDZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
3603 | 0 | } |
3604 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
3605 | 0 | return fastEmitInst_r(X86::VPBROADCASTDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3606 | 0 | } |
3607 | 0 | return 0; |
3608 | 0 | } |
3609 | | |
3610 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
3611 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3612 | 0 | return fastEmitInst_r(X86::VPBROADCASTDZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
3613 | 0 | } |
3614 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
3615 | 0 | return fastEmitInst_r(X86::VPBROADCASTDYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3616 | 0 | } |
3617 | 0 | return 0; |
3618 | 0 | } |
3619 | | |
3620 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v16i32_r(unsigned Op0, bool Op0IsKill) { |
3621 | 0 | if ((Subtarget->hasAVX512())0 ) { |
3622 | 0 | return fastEmitInst_r(X86::VPBROADCASTDZr, &X86::VR512RegClass, Op0, Op0IsKill); |
3623 | 0 | } |
3624 | 0 | return 0; |
3625 | 0 | } |
3626 | | |
3627 | | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3628 | | switch (RetVT.SimpleTy) { |
3629 | | case MVT::v4i32: return fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v4i32_r(Op0, Op0IsKill); |
3630 | | case MVT::v8i32: return fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v8i32_r(Op0, Op0IsKill); |
3631 | | case MVT::v16i32: return fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v16i32_r(Op0, Op0IsKill); |
3632 | | default: return 0; |
3633 | | } |
3634 | | } |
3635 | | |
3636 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { |
3637 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3638 | 0 | return fastEmitInst_r(X86::VPBROADCASTQZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
3639 | 0 | } |
3640 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
3641 | 0 | return fastEmitInst_r(X86::VPBROADCASTQrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3642 | 0 | } |
3643 | 0 | return 0; |
3644 | 0 | } |
3645 | | |
3646 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
3647 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
3648 | 0 | return fastEmitInst_r(X86::VPBROADCASTQZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
3649 | 0 | } |
3650 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
3651 | 0 | return fastEmitInst_r(X86::VPBROADCASTQYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3652 | 0 | } |
3653 | 0 | return 0; |
3654 | 0 | } |
3655 | | |
3656 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
3657 | 0 | if ((Subtarget->hasAVX512())0 ) { |
3658 | 0 | return fastEmitInst_r(X86::VPBROADCASTQZr, &X86::VR512RegClass, Op0, Op0IsKill); |
3659 | 0 | } |
3660 | 0 | return 0; |
3661 | 0 | } |
3662 | | |
3663 | | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3664 | | switch (RetVT.SimpleTy) { |
3665 | | case MVT::v2i64: return fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v2i64_r(Op0, Op0IsKill); |
3666 | | case MVT::v4i64: return fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v4i64_r(Op0, Op0IsKill); |
3667 | | case MVT::v8i64: return fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v8i64_r(Op0, Op0IsKill); |
3668 | | default: return 0; |
3669 | | } |
3670 | | } |
3671 | | |
3672 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { |
3673 | 0 | if ((Subtarget->hasVLX())0 ) { |
3674 | 0 | return fastEmitInst_r(X86::VBROADCASTSSZ128r, &X86::VR128XRegClass, Op0, Op0IsKill); |
3675 | 0 | } |
3676 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
3677 | 0 | return fastEmitInst_r(X86::VBROADCASTSSrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3678 | 0 | } |
3679 | 0 | return 0; |
3680 | 0 | } |
3681 | | |
3682 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v8f32_r(unsigned Op0, bool Op0IsKill) { |
3683 | 0 | if ((Subtarget->hasVLX())0 ) { |
3684 | 0 | return fastEmitInst_r(X86::VBROADCASTSSZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
3685 | 0 | } |
3686 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
3687 | 0 | return fastEmitInst_r(X86::VBROADCASTSSYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3688 | 0 | } |
3689 | 0 | return 0; |
3690 | 0 | } |
3691 | | |
3692 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v16f32_r(unsigned Op0, bool Op0IsKill) { |
3693 | 0 | if ((Subtarget->hasAVX512())0 ) { |
3694 | 0 | return fastEmitInst_r(X86::VBROADCASTSSZr, &X86::VR512RegClass, Op0, Op0IsKill); |
3695 | 0 | } |
3696 | 0 | return 0; |
3697 | 0 | } |
3698 | | |
3699 | | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3700 | | switch (RetVT.SimpleTy) { |
3701 | | case MVT::v4f32: return fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v4f32_r(Op0, Op0IsKill); |
3702 | | case MVT::v8f32: return fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v8f32_r(Op0, Op0IsKill); |
3703 | | case MVT::v16f32: return fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v16f32_r(Op0, Op0IsKill); |
3704 | | default: return 0; |
3705 | | } |
3706 | | } |
3707 | | |
3708 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2f64_MVT_v4f64_r(unsigned Op0, bool Op0IsKill) { |
3709 | 0 | if ((Subtarget->hasVLX())0 ) { |
3710 | 0 | return fastEmitInst_r(X86::VBROADCASTSDZ256r, &X86::VR256XRegClass, Op0, Op0IsKill); |
3711 | 0 | } |
3712 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
3713 | 0 | return fastEmitInst_r(X86::VBROADCASTSDYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3714 | 0 | } |
3715 | 0 | return 0; |
3716 | 0 | } |
3717 | | |
3718 | 0 | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2f64_MVT_v8f64_r(unsigned Op0, bool Op0IsKill) { |
3719 | 0 | if ((Subtarget->hasAVX512())0 ) { |
3720 | 0 | return fastEmitInst_r(X86::VBROADCASTSDZr, &X86::VR512RegClass, Op0, Op0IsKill); |
3721 | 0 | } |
3722 | 0 | return 0; |
3723 | 0 | } |
3724 | | |
3725 | | unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3726 | | switch (RetVT.SimpleTy) { |
3727 | | case MVT::v4f64: return fastEmit_X86ISD_VBROADCAST_MVT_v2f64_MVT_v4f64_r(Op0, Op0IsKill); |
3728 | | case MVT::v8f64: return fastEmit_X86ISD_VBROADCAST_MVT_v2f64_MVT_v8f64_r(Op0, Op0IsKill); |
3729 | | default: return 0; |
3730 | | } |
3731 | | } |
3732 | | |
3733 | | unsigned fastEmit_X86ISD_VBROADCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3734 | | switch (VT.SimpleTy) { |
3735 | | case MVT::i32: return fastEmit_X86ISD_VBROADCAST_MVT_i32_r(RetVT, Op0, Op0IsKill); |
3736 | | case MVT::i64: return fastEmit_X86ISD_VBROADCAST_MVT_i64_r(RetVT, Op0, Op0IsKill); |
3737 | | case MVT::v16i8: return fastEmit_X86ISD_VBROADCAST_MVT_v16i8_r(RetVT, Op0, Op0IsKill); |
3738 | | case MVT::v8i16: return fastEmit_X86ISD_VBROADCAST_MVT_v8i16_r(RetVT, Op0, Op0IsKill); |
3739 | | case MVT::v4i32: return fastEmit_X86ISD_VBROADCAST_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
3740 | | case MVT::v2i64: return fastEmit_X86ISD_VBROADCAST_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
3741 | | case MVT::v4f32: return fastEmit_X86ISD_VBROADCAST_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
3742 | | case MVT::v2f64: return fastEmit_X86ISD_VBROADCAST_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
3743 | | default: return 0; |
3744 | | } |
3745 | | } |
3746 | | |
3747 | | // FastEmit functions for X86ISD::VBROADCASTM. |
3748 | | |
3749 | 0 | unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { |
3750 | 0 | if ((Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
3751 | 0 | return fastEmitInst_r(X86::VPBROADCASTMB2QZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
3752 | 0 | } |
3753 | 0 | return 0; |
3754 | 0 | } |
3755 | | |
3756 | 0 | unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
3757 | 0 | if ((Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
3758 | 0 | return fastEmitInst_r(X86::VPBROADCASTMB2QZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
3759 | 0 | } |
3760 | 0 | return 0; |
3761 | 0 | } |
3762 | | |
3763 | 0 | unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
3764 | 0 | if ((Subtarget->hasCDI())0 ) { |
3765 | 0 | return fastEmitInst_r(X86::VPBROADCASTMB2QZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
3766 | 0 | } |
3767 | 0 | return 0; |
3768 | 0 | } |
3769 | | |
3770 | | unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3771 | | switch (RetVT.SimpleTy) { |
3772 | | case MVT::v2i64: return fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v2i64_r(Op0, Op0IsKill); |
3773 | | case MVT::v4i64: return fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v4i64_r(Op0, Op0IsKill); |
3774 | | case MVT::v8i64: return fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v8i64_r(Op0, Op0IsKill); |
3775 | | default: return 0; |
3776 | | } |
3777 | | } |
3778 | | |
3779 | 0 | unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
3780 | 0 | if ((Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
3781 | 0 | return fastEmitInst_r(X86::VPBROADCASTMW2DZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
3782 | 0 | } |
3783 | 0 | return 0; |
3784 | 0 | } |
3785 | | |
3786 | 0 | unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
3787 | 0 | if ((Subtarget->hasCDI()) && 0 (Subtarget->hasVLX())0 ) { |
3788 | 0 | return fastEmitInst_r(X86::VPBROADCASTMW2DZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
3789 | 0 | } |
3790 | 0 | return 0; |
3791 | 0 | } |
3792 | | |
3793 | 0 | unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v16i32_r(unsigned Op0, bool Op0IsKill) { |
3794 | 0 | if ((Subtarget->hasCDI())0 ) { |
3795 | 0 | return fastEmitInst_r(X86::VPBROADCASTMW2DZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
3796 | 0 | } |
3797 | 0 | return 0; |
3798 | 0 | } |
3799 | | |
3800 | | unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3801 | | switch (RetVT.SimpleTy) { |
3802 | | case MVT::v4i32: return fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v4i32_r(Op0, Op0IsKill); |
3803 | | case MVT::v8i32: return fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v8i32_r(Op0, Op0IsKill); |
3804 | | case MVT::v16i32: return fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v16i32_r(Op0, Op0IsKill); |
3805 | | default: return 0; |
3806 | | } |
3807 | | } |
3808 | | |
3809 | | unsigned fastEmit_X86ISD_VBROADCASTM_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3810 | | switch (VT.SimpleTy) { |
3811 | | case MVT::v8i1: return fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_r(RetVT, Op0, Op0IsKill); |
3812 | | case MVT::v16i1: return fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_r(RetVT, Op0, Op0IsKill); |
3813 | | default: return 0; |
3814 | | } |
3815 | | } |
3816 | | |
3817 | | // FastEmit functions for X86ISD::VFPEXT. |
3818 | | |
3819 | 0 | unsigned fastEmit_X86ISD_VFPEXT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3820 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3821 | 0 | return 0; |
3822 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
3823 | 0 | return fastEmitInst_r(X86::VCVTPS2PDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
3824 | 0 | } |
3825 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
3826 | 0 | return fastEmitInst_r(X86::CVTPS2PDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3827 | 0 | } |
3828 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3829 | 0 | return fastEmitInst_r(X86::VCVTPS2PDrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3830 | 0 | } |
3831 | 0 | return 0; |
3832 | 0 | } |
3833 | | |
3834 | | unsigned fastEmit_X86ISD_VFPEXT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3835 | | switch (VT.SimpleTy) { |
3836 | | case MVT::v4f32: return fastEmit_X86ISD_VFPEXT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); |
3837 | | default: return 0; |
3838 | | } |
3839 | | } |
3840 | | |
3841 | | // FastEmit functions for X86ISD::VFPROUND. |
3842 | | |
3843 | 0 | unsigned fastEmit_X86ISD_VFPROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3844 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3845 | 0 | return 0; |
3846 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
3847 | 0 | return fastEmitInst_r(X86::VCVTPD2PSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
3848 | 0 | } |
3849 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
3850 | 0 | return fastEmitInst_r(X86::CVTPD2PSrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3851 | 0 | } |
3852 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
3853 | 0 | return fastEmitInst_r(X86::VCVTPD2PSrr, &X86::VR128RegClass, Op0, Op0IsKill); |
3854 | 0 | } |
3855 | 0 | return 0; |
3856 | 0 | } |
3857 | | |
3858 | | unsigned fastEmit_X86ISD_VFPROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3859 | | switch (VT.SimpleTy) { |
3860 | | case MVT::v2f64: return fastEmit_X86ISD_VFPROUND_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
3861 | | default: return 0; |
3862 | | } |
3863 | | } |
3864 | | |
3865 | | // FastEmit functions for X86ISD::VSEXT. |
3866 | | |
3867 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v2i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3868 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3869 | 0 | return 0; |
3870 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
3871 | 0 | return fastEmitInst_r(X86::VPMOVM2QZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
3872 | 0 | } |
3873 | 0 | return 0; |
3874 | 0 | } |
3875 | | |
3876 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v4i1_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
3877 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
3878 | 0 | return fastEmitInst_r(X86::VPMOVM2DZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
3879 | 0 | } |
3880 | 0 | return 0; |
3881 | 0 | } |
3882 | | |
3883 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v4i1_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
3884 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
3885 | 0 | return fastEmitInst_r(X86::VPMOVM2QZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
3886 | 0 | } |
3887 | 0 | return 0; |
3888 | 0 | } |
3889 | | |
3890 | | unsigned fastEmit_X86ISD_VSEXT_MVT_v4i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3891 | | switch (RetVT.SimpleTy) { |
3892 | | case MVT::v4i32: return fastEmit_X86ISD_VSEXT_MVT_v4i1_MVT_v4i32_r(Op0, Op0IsKill); |
3893 | | case MVT::v4i64: return fastEmit_X86ISD_VSEXT_MVT_v4i1_MVT_v4i64_r(Op0, Op0IsKill); |
3894 | | default: return 0; |
3895 | | } |
3896 | | } |
3897 | | |
3898 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v8i1_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
3899 | 0 | if ((Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
3900 | 0 | return fastEmitInst_r(X86::VPMOVM2WZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
3901 | 0 | } |
3902 | 0 | return 0; |
3903 | 0 | } |
3904 | | |
3905 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v8i1_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
3906 | 0 | if ((Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
3907 | 0 | return fastEmitInst_r(X86::VPMOVM2DZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
3908 | 0 | } |
3909 | 0 | return 0; |
3910 | 0 | } |
3911 | | |
3912 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v8i1_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
3913 | 0 | if ((Subtarget->hasDQI())0 ) { |
3914 | 0 | return fastEmitInst_r(X86::VPMOVM2QZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
3915 | 0 | } |
3916 | 0 | return 0; |
3917 | 0 | } |
3918 | | |
3919 | | unsigned fastEmit_X86ISD_VSEXT_MVT_v8i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3920 | | switch (RetVT.SimpleTy) { |
3921 | | case MVT::v8i16: return fastEmit_X86ISD_VSEXT_MVT_v8i1_MVT_v8i16_r(Op0, Op0IsKill); |
3922 | | case MVT::v8i32: return fastEmit_X86ISD_VSEXT_MVT_v8i1_MVT_v8i32_r(Op0, Op0IsKill); |
3923 | | case MVT::v8i64: return fastEmit_X86ISD_VSEXT_MVT_v8i1_MVT_v8i64_r(Op0, Op0IsKill); |
3924 | | default: return 0; |
3925 | | } |
3926 | | } |
3927 | | |
3928 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v16i1_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
3929 | 0 | if ((Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
3930 | 0 | return fastEmitInst_r(X86::VPMOVM2BZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
3931 | 0 | } |
3932 | 0 | return 0; |
3933 | 0 | } |
3934 | | |
3935 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v16i1_MVT_v16i16_r(unsigned Op0, bool Op0IsKill) { |
3936 | 0 | if ((Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
3937 | 0 | return fastEmitInst_r(X86::VPMOVM2WZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
3938 | 0 | } |
3939 | 0 | return 0; |
3940 | 0 | } |
3941 | | |
3942 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v16i1_MVT_v16i32_r(unsigned Op0, bool Op0IsKill) { |
3943 | 0 | if ((Subtarget->hasDQI())0 ) { |
3944 | 0 | return fastEmitInst_r(X86::VPMOVM2DZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
3945 | 0 | } |
3946 | 0 | return 0; |
3947 | 0 | } |
3948 | | |
3949 | | unsigned fastEmit_X86ISD_VSEXT_MVT_v16i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3950 | | switch (RetVT.SimpleTy) { |
3951 | | case MVT::v16i8: return fastEmit_X86ISD_VSEXT_MVT_v16i1_MVT_v16i8_r(Op0, Op0IsKill); |
3952 | | case MVT::v16i16: return fastEmit_X86ISD_VSEXT_MVT_v16i1_MVT_v16i16_r(Op0, Op0IsKill); |
3953 | | case MVT::v16i32: return fastEmit_X86ISD_VSEXT_MVT_v16i1_MVT_v16i32_r(Op0, Op0IsKill); |
3954 | | default: return 0; |
3955 | | } |
3956 | | } |
3957 | | |
3958 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v32i1_MVT_v32i8_r(unsigned Op0, bool Op0IsKill) { |
3959 | 0 | if ((Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
3960 | 0 | return fastEmitInst_r(X86::VPMOVM2BZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
3961 | 0 | } |
3962 | 0 | return 0; |
3963 | 0 | } |
3964 | | |
3965 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v32i1_MVT_v32i16_r(unsigned Op0, bool Op0IsKill) { |
3966 | 0 | if ((Subtarget->hasBWI())0 ) { |
3967 | 0 | return fastEmitInst_r(X86::VPMOVM2WZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
3968 | 0 | } |
3969 | 0 | return 0; |
3970 | 0 | } |
3971 | | |
3972 | | unsigned fastEmit_X86ISD_VSEXT_MVT_v32i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3973 | | switch (RetVT.SimpleTy) { |
3974 | | case MVT::v32i8: return fastEmit_X86ISD_VSEXT_MVT_v32i1_MVT_v32i8_r(Op0, Op0IsKill); |
3975 | | case MVT::v32i16: return fastEmit_X86ISD_VSEXT_MVT_v32i1_MVT_v32i16_r(Op0, Op0IsKill); |
3976 | | default: return 0; |
3977 | | } |
3978 | | } |
3979 | | |
3980 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v64i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
3981 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
3982 | 0 | return 0; |
3983 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
3984 | 0 | return fastEmitInst_r(X86::VPMOVM2BZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
3985 | 0 | } |
3986 | 0 | return 0; |
3987 | 0 | } |
3988 | | |
3989 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v16i8_MVT_v16i16_r(unsigned Op0, bool Op0IsKill) { |
3990 | 0 | if ((Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
3991 | 0 | return fastEmitInst_r(X86::VPMOVSXBWYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
3992 | 0 | } |
3993 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
3994 | 0 | return fastEmitInst_r(X86::VPMOVSXBWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
3995 | 0 | } |
3996 | 0 | return 0; |
3997 | 0 | } |
3998 | | |
3999 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v16i8_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
4000 | 0 | if ((Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
4001 | 0 | return fastEmitInst_r(X86::VPMOVSXBDYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
4002 | 0 | } |
4003 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4004 | 0 | return fastEmitInst_r(X86::VPMOVSXBDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4005 | 0 | } |
4006 | 0 | return 0; |
4007 | 0 | } |
4008 | | |
4009 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v16i8_MVT_v16i32_r(unsigned Op0, bool Op0IsKill) { |
4010 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4011 | 0 | return fastEmitInst_r(X86::VPMOVSXBDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4012 | 0 | } |
4013 | 0 | return 0; |
4014 | 0 | } |
4015 | | |
4016 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v16i8_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
4017 | 0 | if ((Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
4018 | 0 | return fastEmitInst_r(X86::VPMOVSXBQYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
4019 | 0 | } |
4020 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4021 | 0 | return fastEmitInst_r(X86::VPMOVSXBQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4022 | 0 | } |
4023 | 0 | return 0; |
4024 | 0 | } |
4025 | | |
4026 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v16i8_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
4027 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4028 | 0 | return fastEmitInst_r(X86::VPMOVSXBQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4029 | 0 | } |
4030 | 0 | return 0; |
4031 | 0 | } |
4032 | | |
4033 | | unsigned fastEmit_X86ISD_VSEXT_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4034 | | switch (RetVT.SimpleTy) { |
4035 | | case MVT::v16i16: return fastEmit_X86ISD_VSEXT_MVT_v16i8_MVT_v16i16_r(Op0, Op0IsKill); |
4036 | | case MVT::v8i32: return fastEmit_X86ISD_VSEXT_MVT_v16i8_MVT_v8i32_r(Op0, Op0IsKill); |
4037 | | case MVT::v16i32: return fastEmit_X86ISD_VSEXT_MVT_v16i8_MVT_v16i32_r(Op0, Op0IsKill); |
4038 | | case MVT::v4i64: return fastEmit_X86ISD_VSEXT_MVT_v16i8_MVT_v4i64_r(Op0, Op0IsKill); |
4039 | | case MVT::v8i64: return fastEmit_X86ISD_VSEXT_MVT_v16i8_MVT_v8i64_r(Op0, Op0IsKill); |
4040 | | default: return 0; |
4041 | | } |
4042 | | } |
4043 | | |
4044 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v32i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4045 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
4046 | 0 | return 0; |
4047 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
4048 | 0 | return fastEmitInst_r(X86::VPMOVSXBWZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4049 | 0 | } |
4050 | 0 | return 0; |
4051 | 0 | } |
4052 | | |
4053 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v8i16_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
4054 | 0 | if ((Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
4055 | 0 | return fastEmitInst_r(X86::VPMOVSXWDYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
4056 | 0 | } |
4057 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4058 | 0 | return fastEmitInst_r(X86::VPMOVSXWDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4059 | 0 | } |
4060 | 0 | return 0; |
4061 | 0 | } |
4062 | | |
4063 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v8i16_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
4064 | 0 | if ((Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
4065 | 0 | return fastEmitInst_r(X86::VPMOVSXWQYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
4066 | 0 | } |
4067 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4068 | 0 | return fastEmitInst_r(X86::VPMOVSXWQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4069 | 0 | } |
4070 | 0 | return 0; |
4071 | 0 | } |
4072 | | |
4073 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v8i16_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
4074 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4075 | 0 | return fastEmitInst_r(X86::VPMOVSXWQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4076 | 0 | } |
4077 | 0 | return 0; |
4078 | 0 | } |
4079 | | |
4080 | | unsigned fastEmit_X86ISD_VSEXT_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4081 | | switch (RetVT.SimpleTy) { |
4082 | | case MVT::v8i32: return fastEmit_X86ISD_VSEXT_MVT_v8i16_MVT_v8i32_r(Op0, Op0IsKill); |
4083 | | case MVT::v4i64: return fastEmit_X86ISD_VSEXT_MVT_v8i16_MVT_v4i64_r(Op0, Op0IsKill); |
4084 | | case MVT::v8i64: return fastEmit_X86ISD_VSEXT_MVT_v8i16_MVT_v8i64_r(Op0, Op0IsKill); |
4085 | | default: return 0; |
4086 | | } |
4087 | | } |
4088 | | |
4089 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v16i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4090 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
4091 | 0 | return 0; |
4092 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
4093 | 0 | return fastEmitInst_r(X86::VPMOVSXWDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4094 | 0 | } |
4095 | 0 | return 0; |
4096 | 0 | } |
4097 | | |
4098 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4099 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
4100 | 0 | return 0; |
4101 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
4102 | 0 | return fastEmitInst_r(X86::VPMOVSXDQYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
4103 | 0 | } |
4104 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4105 | 0 | return fastEmitInst_r(X86::VPMOVSXDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4106 | 0 | } |
4107 | 0 | return 0; |
4108 | 0 | } |
4109 | | |
4110 | 0 | unsigned fastEmit_X86ISD_VSEXT_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4111 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
4112 | 0 | return 0; |
4113 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
4114 | 0 | return fastEmitInst_r(X86::VPMOVSXDQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4115 | 0 | } |
4116 | 0 | return 0; |
4117 | 0 | } |
4118 | | |
4119 | | unsigned fastEmit_X86ISD_VSEXT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4120 | | switch (VT.SimpleTy) { |
4121 | | case MVT::v2i1: return fastEmit_X86ISD_VSEXT_MVT_v2i1_r(RetVT, Op0, Op0IsKill); |
4122 | | case MVT::v4i1: return fastEmit_X86ISD_VSEXT_MVT_v4i1_r(RetVT, Op0, Op0IsKill); |
4123 | | case MVT::v8i1: return fastEmit_X86ISD_VSEXT_MVT_v8i1_r(RetVT, Op0, Op0IsKill); |
4124 | | case MVT::v16i1: return fastEmit_X86ISD_VSEXT_MVT_v16i1_r(RetVT, Op0, Op0IsKill); |
4125 | | case MVT::v32i1: return fastEmit_X86ISD_VSEXT_MVT_v32i1_r(RetVT, Op0, Op0IsKill); |
4126 | | case MVT::v64i1: return fastEmit_X86ISD_VSEXT_MVT_v64i1_r(RetVT, Op0, Op0IsKill); |
4127 | | case MVT::v16i8: return fastEmit_X86ISD_VSEXT_MVT_v16i8_r(RetVT, Op0, Op0IsKill); |
4128 | | case MVT::v32i8: return fastEmit_X86ISD_VSEXT_MVT_v32i8_r(RetVT, Op0, Op0IsKill); |
4129 | | case MVT::v8i16: return fastEmit_X86ISD_VSEXT_MVT_v8i16_r(RetVT, Op0, Op0IsKill); |
4130 | | case MVT::v16i16: return fastEmit_X86ISD_VSEXT_MVT_v16i16_r(RetVT, Op0, Op0IsKill); |
4131 | | case MVT::v4i32: return fastEmit_X86ISD_VSEXT_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
4132 | | case MVT::v8i32: return fastEmit_X86ISD_VSEXT_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
4133 | | default: return 0; |
4134 | | } |
4135 | | } |
4136 | | |
4137 | | // FastEmit functions for X86ISD::VTRUNC. |
4138 | | |
4139 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4140 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4141 | 0 | return 0; |
4142 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
4143 | 0 | return fastEmitInst_r(X86::VPMOVWBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4144 | 0 | } |
4145 | 0 | return 0; |
4146 | 0 | } |
4147 | | |
4148 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v16i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4149 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4150 | 0 | return 0; |
4151 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
4152 | 0 | return fastEmitInst_r(X86::VPMOVWBZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4153 | 0 | } |
4154 | 0 | return 0; |
4155 | 0 | } |
4156 | | |
4157 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v32i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4158 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
4159 | 0 | return 0; |
4160 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
4161 | 0 | return fastEmitInst_r(X86::VPMOVWBZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4162 | 0 | } |
4163 | 0 | return 0; |
4164 | 0 | } |
4165 | | |
4166 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4167 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4168 | 0 | return fastEmitInst_r(X86::VPMOVDBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4169 | 0 | } |
4170 | 0 | return 0; |
4171 | 0 | } |
4172 | | |
4173 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4174 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4175 | 0 | return fastEmitInst_r(X86::VPMOVDWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4176 | 0 | } |
4177 | 0 | return 0; |
4178 | 0 | } |
4179 | | |
4180 | | unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4181 | | switch (RetVT.SimpleTy) { |
4182 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNC_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill); |
4183 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNC_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill); |
4184 | | default: return 0; |
4185 | | } |
4186 | | } |
4187 | | |
4188 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v8i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4189 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4190 | 0 | return fastEmitInst_r(X86::VPMOVDBZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4191 | 0 | } |
4192 | 0 | return 0; |
4193 | 0 | } |
4194 | | |
4195 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v8i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4196 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4197 | 0 | return fastEmitInst_r(X86::VPMOVDWZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4198 | 0 | } |
4199 | 0 | return 0; |
4200 | 0 | } |
4201 | | |
4202 | | unsigned fastEmit_X86ISD_VTRUNC_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4203 | | switch (RetVT.SimpleTy) { |
4204 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNC_MVT_v8i32_MVT_v16i8_r(Op0, Op0IsKill); |
4205 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNC_MVT_v8i32_MVT_v8i16_r(Op0, Op0IsKill); |
4206 | | default: return 0; |
4207 | | } |
4208 | | } |
4209 | | |
4210 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v16i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4211 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4212 | 0 | return fastEmitInst_r(X86::VPMOVDBZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4213 | 0 | } |
4214 | 0 | return 0; |
4215 | 0 | } |
4216 | | |
4217 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v16i32_MVT_v16i16_r(unsigned Op0, bool Op0IsKill) { |
4218 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4219 | 0 | return fastEmitInst_r(X86::VPMOVDWZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4220 | 0 | } |
4221 | 0 | return 0; |
4222 | 0 | } |
4223 | | |
4224 | | unsigned fastEmit_X86ISD_VTRUNC_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4225 | | switch (RetVT.SimpleTy) { |
4226 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNC_MVT_v16i32_MVT_v16i8_r(Op0, Op0IsKill); |
4227 | | case MVT::v16i16: return fastEmit_X86ISD_VTRUNC_MVT_v16i32_MVT_v16i16_r(Op0, Op0IsKill); |
4228 | | default: return 0; |
4229 | | } |
4230 | | } |
4231 | | |
4232 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4233 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4234 | 0 | return fastEmitInst_r(X86::VPMOVQBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4235 | 0 | } |
4236 | 0 | return 0; |
4237 | 0 | } |
4238 | | |
4239 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4240 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4241 | 0 | return fastEmitInst_r(X86::VPMOVQWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4242 | 0 | } |
4243 | 0 | return 0; |
4244 | 0 | } |
4245 | | |
4246 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
4247 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4248 | 0 | return fastEmitInst_r(X86::VPMOVQDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4249 | 0 | } |
4250 | 0 | return 0; |
4251 | 0 | } |
4252 | | |
4253 | | unsigned fastEmit_X86ISD_VTRUNC_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4254 | | switch (RetVT.SimpleTy) { |
4255 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill); |
4256 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill); |
4257 | | case MVT::v4i32: return fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill); |
4258 | | default: return 0; |
4259 | | } |
4260 | | } |
4261 | | |
4262 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4263 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4264 | 0 | return fastEmitInst_r(X86::VPMOVQBZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4265 | 0 | } |
4266 | 0 | return 0; |
4267 | 0 | } |
4268 | | |
4269 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4270 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4271 | 0 | return fastEmitInst_r(X86::VPMOVQWZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4272 | 0 | } |
4273 | 0 | return 0; |
4274 | 0 | } |
4275 | | |
4276 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
4277 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4278 | 0 | return fastEmitInst_r(X86::VPMOVQDZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4279 | 0 | } |
4280 | 0 | return 0; |
4281 | 0 | } |
4282 | | |
4283 | | unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4284 | | switch (RetVT.SimpleTy) { |
4285 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNC_MVT_v4i64_MVT_v16i8_r(Op0, Op0IsKill); |
4286 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNC_MVT_v4i64_MVT_v8i16_r(Op0, Op0IsKill); |
4287 | | case MVT::v4i32: return fastEmit_X86ISD_VTRUNC_MVT_v4i64_MVT_v4i32_r(Op0, Op0IsKill); |
4288 | | default: return 0; |
4289 | | } |
4290 | | } |
4291 | | |
4292 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v8i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4293 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4294 | 0 | return fastEmitInst_r(X86::VPMOVQBZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4295 | 0 | } |
4296 | 0 | return 0; |
4297 | 0 | } |
4298 | | |
4299 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v8i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4300 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4301 | 0 | return fastEmitInst_r(X86::VPMOVQWZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4302 | 0 | } |
4303 | 0 | return 0; |
4304 | 0 | } |
4305 | | |
4306 | 0 | unsigned fastEmit_X86ISD_VTRUNC_MVT_v8i64_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
4307 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4308 | 0 | return fastEmitInst_r(X86::VPMOVQDZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4309 | 0 | } |
4310 | 0 | return 0; |
4311 | 0 | } |
4312 | | |
4313 | | unsigned fastEmit_X86ISD_VTRUNC_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4314 | | switch (RetVT.SimpleTy) { |
4315 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNC_MVT_v8i64_MVT_v16i8_r(Op0, Op0IsKill); |
4316 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNC_MVT_v8i64_MVT_v8i16_r(Op0, Op0IsKill); |
4317 | | case MVT::v8i32: return fastEmit_X86ISD_VTRUNC_MVT_v8i64_MVT_v8i32_r(Op0, Op0IsKill); |
4318 | | default: return 0; |
4319 | | } |
4320 | | } |
4321 | | |
4322 | | unsigned fastEmit_X86ISD_VTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4323 | | switch (VT.SimpleTy) { |
4324 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNC_MVT_v8i16_r(RetVT, Op0, Op0IsKill); |
4325 | | case MVT::v16i16: return fastEmit_X86ISD_VTRUNC_MVT_v16i16_r(RetVT, Op0, Op0IsKill); |
4326 | | case MVT::v32i16: return fastEmit_X86ISD_VTRUNC_MVT_v32i16_r(RetVT, Op0, Op0IsKill); |
4327 | | case MVT::v4i32: return fastEmit_X86ISD_VTRUNC_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
4328 | | case MVT::v8i32: return fastEmit_X86ISD_VTRUNC_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
4329 | | case MVT::v16i32: return fastEmit_X86ISD_VTRUNC_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
4330 | | case MVT::v2i64: return fastEmit_X86ISD_VTRUNC_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
4331 | | case MVT::v4i64: return fastEmit_X86ISD_VTRUNC_MVT_v4i64_r(RetVT, Op0, Op0IsKill); |
4332 | | case MVT::v8i64: return fastEmit_X86ISD_VTRUNC_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
4333 | | default: return 0; |
4334 | | } |
4335 | | } |
4336 | | |
4337 | | // FastEmit functions for X86ISD::VTRUNCS. |
4338 | | |
4339 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4340 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4341 | 0 | return 0; |
4342 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
4343 | 0 | return fastEmitInst_r(X86::VPMOVSWBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4344 | 0 | } |
4345 | 0 | return 0; |
4346 | 0 | } |
4347 | | |
4348 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v16i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4349 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4350 | 0 | return 0; |
4351 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
4352 | 0 | return fastEmitInst_r(X86::VPMOVSWBZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4353 | 0 | } |
4354 | 0 | return 0; |
4355 | 0 | } |
4356 | | |
4357 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v32i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4358 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
4359 | 0 | return 0; |
4360 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
4361 | 0 | return fastEmitInst_r(X86::VPMOVSWBZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4362 | 0 | } |
4363 | 0 | return 0; |
4364 | 0 | } |
4365 | | |
4366 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4367 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4368 | 0 | return fastEmitInst_r(X86::VPMOVSDBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4369 | 0 | } |
4370 | 0 | return 0; |
4371 | 0 | } |
4372 | | |
4373 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4374 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4375 | 0 | return fastEmitInst_r(X86::VPMOVSDWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4376 | 0 | } |
4377 | 0 | return 0; |
4378 | 0 | } |
4379 | | |
4380 | | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4381 | | switch (RetVT.SimpleTy) { |
4382 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill); |
4383 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill); |
4384 | | default: return 0; |
4385 | | } |
4386 | | } |
4387 | | |
4388 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4389 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4390 | 0 | return fastEmitInst_r(X86::VPMOVSDBZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4391 | 0 | } |
4392 | 0 | return 0; |
4393 | 0 | } |
4394 | | |
4395 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4396 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4397 | 0 | return fastEmitInst_r(X86::VPMOVSDWZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4398 | 0 | } |
4399 | 0 | return 0; |
4400 | 0 | } |
4401 | | |
4402 | | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4403 | | switch (RetVT.SimpleTy) { |
4404 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v8i32_MVT_v16i8_r(Op0, Op0IsKill); |
4405 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v8i32_MVT_v8i16_r(Op0, Op0IsKill); |
4406 | | default: return 0; |
4407 | | } |
4408 | | } |
4409 | | |
4410 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v16i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4411 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4412 | 0 | return fastEmitInst_r(X86::VPMOVSDBZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4413 | 0 | } |
4414 | 0 | return 0; |
4415 | 0 | } |
4416 | | |
4417 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v16i32_MVT_v16i16_r(unsigned Op0, bool Op0IsKill) { |
4418 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4419 | 0 | return fastEmitInst_r(X86::VPMOVSDWZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4420 | 0 | } |
4421 | 0 | return 0; |
4422 | 0 | } |
4423 | | |
4424 | | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4425 | | switch (RetVT.SimpleTy) { |
4426 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v16i32_MVT_v16i8_r(Op0, Op0IsKill); |
4427 | | case MVT::v16i16: return fastEmit_X86ISD_VTRUNCS_MVT_v16i32_MVT_v16i16_r(Op0, Op0IsKill); |
4428 | | default: return 0; |
4429 | | } |
4430 | | } |
4431 | | |
4432 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4433 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4434 | 0 | return fastEmitInst_r(X86::VPMOVSQBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4435 | 0 | } |
4436 | 0 | return 0; |
4437 | 0 | } |
4438 | | |
4439 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4440 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4441 | 0 | return fastEmitInst_r(X86::VPMOVSQWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4442 | 0 | } |
4443 | 0 | return 0; |
4444 | 0 | } |
4445 | | |
4446 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
4447 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4448 | 0 | return fastEmitInst_r(X86::VPMOVSQDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4449 | 0 | } |
4450 | 0 | return 0; |
4451 | 0 | } |
4452 | | |
4453 | | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4454 | | switch (RetVT.SimpleTy) { |
4455 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill); |
4456 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill); |
4457 | | case MVT::v4i32: return fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill); |
4458 | | default: return 0; |
4459 | | } |
4460 | | } |
4461 | | |
4462 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4463 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4464 | 0 | return fastEmitInst_r(X86::VPMOVSQBZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4465 | 0 | } |
4466 | 0 | return 0; |
4467 | 0 | } |
4468 | | |
4469 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4470 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4471 | 0 | return fastEmitInst_r(X86::VPMOVSQWZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4472 | 0 | } |
4473 | 0 | return 0; |
4474 | 0 | } |
4475 | | |
4476 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
4477 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4478 | 0 | return fastEmitInst_r(X86::VPMOVSQDZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4479 | 0 | } |
4480 | 0 | return 0; |
4481 | 0 | } |
4482 | | |
4483 | | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4484 | | switch (RetVT.SimpleTy) { |
4485 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v16i8_r(Op0, Op0IsKill); |
4486 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v8i16_r(Op0, Op0IsKill); |
4487 | | case MVT::v4i32: return fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v4i32_r(Op0, Op0IsKill); |
4488 | | default: return 0; |
4489 | | } |
4490 | | } |
4491 | | |
4492 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4493 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4494 | 0 | return fastEmitInst_r(X86::VPMOVSQBZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4495 | 0 | } |
4496 | 0 | return 0; |
4497 | 0 | } |
4498 | | |
4499 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4500 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4501 | 0 | return fastEmitInst_r(X86::VPMOVSQWZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4502 | 0 | } |
4503 | 0 | return 0; |
4504 | 0 | } |
4505 | | |
4506 | 0 | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
4507 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4508 | 0 | return fastEmitInst_r(X86::VPMOVSQDZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4509 | 0 | } |
4510 | 0 | return 0; |
4511 | 0 | } |
4512 | | |
4513 | | unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4514 | | switch (RetVT.SimpleTy) { |
4515 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v16i8_r(Op0, Op0IsKill); |
4516 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v8i16_r(Op0, Op0IsKill); |
4517 | | case MVT::v8i32: return fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v8i32_r(Op0, Op0IsKill); |
4518 | | default: return 0; |
4519 | | } |
4520 | | } |
4521 | | |
4522 | | unsigned fastEmit_X86ISD_VTRUNCS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4523 | | switch (VT.SimpleTy) { |
4524 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v8i16_r(RetVT, Op0, Op0IsKill); |
4525 | | case MVT::v16i16: return fastEmit_X86ISD_VTRUNCS_MVT_v16i16_r(RetVT, Op0, Op0IsKill); |
4526 | | case MVT::v32i16: return fastEmit_X86ISD_VTRUNCS_MVT_v32i16_r(RetVT, Op0, Op0IsKill); |
4527 | | case MVT::v4i32: return fastEmit_X86ISD_VTRUNCS_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
4528 | | case MVT::v8i32: return fastEmit_X86ISD_VTRUNCS_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
4529 | | case MVT::v16i32: return fastEmit_X86ISD_VTRUNCS_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
4530 | | case MVT::v2i64: return fastEmit_X86ISD_VTRUNCS_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
4531 | | case MVT::v4i64: return fastEmit_X86ISD_VTRUNCS_MVT_v4i64_r(RetVT, Op0, Op0IsKill); |
4532 | | case MVT::v8i64: return fastEmit_X86ISD_VTRUNCS_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
4533 | | default: return 0; |
4534 | | } |
4535 | | } |
4536 | | |
4537 | | // FastEmit functions for X86ISD::VTRUNCUS. |
4538 | | |
4539 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4540 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4541 | 0 | return 0; |
4542 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
4543 | 0 | return fastEmitInst_r(X86::VPMOVUSWBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4544 | 0 | } |
4545 | 0 | return 0; |
4546 | 0 | } |
4547 | | |
4548 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v16i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4549 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4550 | 0 | return 0; |
4551 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
4552 | 0 | return fastEmitInst_r(X86::VPMOVUSWBZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4553 | 0 | } |
4554 | 0 | return 0; |
4555 | 0 | } |
4556 | | |
4557 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v32i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4558 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
4559 | 0 | return 0; |
4560 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
4561 | 0 | return fastEmitInst_r(X86::VPMOVUSWBZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4562 | 0 | } |
4563 | 0 | return 0; |
4564 | 0 | } |
4565 | | |
4566 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4567 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4568 | 0 | return fastEmitInst_r(X86::VPMOVUSDBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4569 | 0 | } |
4570 | 0 | return 0; |
4571 | 0 | } |
4572 | | |
4573 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4574 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4575 | 0 | return fastEmitInst_r(X86::VPMOVUSDWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4576 | 0 | } |
4577 | 0 | return 0; |
4578 | 0 | } |
4579 | | |
4580 | | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4581 | | switch (RetVT.SimpleTy) { |
4582 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill); |
4583 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill); |
4584 | | default: return 0; |
4585 | | } |
4586 | | } |
4587 | | |
4588 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4589 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4590 | 0 | return fastEmitInst_r(X86::VPMOVUSDBZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4591 | 0 | } |
4592 | 0 | return 0; |
4593 | 0 | } |
4594 | | |
4595 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4596 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4597 | 0 | return fastEmitInst_r(X86::VPMOVUSDWZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4598 | 0 | } |
4599 | 0 | return 0; |
4600 | 0 | } |
4601 | | |
4602 | | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4603 | | switch (RetVT.SimpleTy) { |
4604 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_MVT_v16i8_r(Op0, Op0IsKill); |
4605 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_MVT_v8i16_r(Op0, Op0IsKill); |
4606 | | default: return 0; |
4607 | | } |
4608 | | } |
4609 | | |
4610 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4611 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4612 | 0 | return fastEmitInst_r(X86::VPMOVUSDBZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4613 | 0 | } |
4614 | 0 | return 0; |
4615 | 0 | } |
4616 | | |
4617 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_MVT_v16i16_r(unsigned Op0, bool Op0IsKill) { |
4618 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4619 | 0 | return fastEmitInst_r(X86::VPMOVUSDWZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4620 | 0 | } |
4621 | 0 | return 0; |
4622 | 0 | } |
4623 | | |
4624 | | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4625 | | switch (RetVT.SimpleTy) { |
4626 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_MVT_v16i8_r(Op0, Op0IsKill); |
4627 | | case MVT::v16i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_MVT_v16i16_r(Op0, Op0IsKill); |
4628 | | default: return 0; |
4629 | | } |
4630 | | } |
4631 | | |
4632 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4633 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4634 | 0 | return fastEmitInst_r(X86::VPMOVUSQBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4635 | 0 | } |
4636 | 0 | return 0; |
4637 | 0 | } |
4638 | | |
4639 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4640 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4641 | 0 | return fastEmitInst_r(X86::VPMOVUSQWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4642 | 0 | } |
4643 | 0 | return 0; |
4644 | 0 | } |
4645 | | |
4646 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
4647 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4648 | 0 | return fastEmitInst_r(X86::VPMOVUSQDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4649 | 0 | } |
4650 | 0 | return 0; |
4651 | 0 | } |
4652 | | |
4653 | | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4654 | | switch (RetVT.SimpleTy) { |
4655 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill); |
4656 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill); |
4657 | | case MVT::v4i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill); |
4658 | | default: return 0; |
4659 | | } |
4660 | | } |
4661 | | |
4662 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4663 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4664 | 0 | return fastEmitInst_r(X86::VPMOVUSQBZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4665 | 0 | } |
4666 | 0 | return 0; |
4667 | 0 | } |
4668 | | |
4669 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4670 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4671 | 0 | return fastEmitInst_r(X86::VPMOVUSQWZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4672 | 0 | } |
4673 | 0 | return 0; |
4674 | 0 | } |
4675 | | |
4676 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { |
4677 | 0 | if ((Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4678 | 0 | return fastEmitInst_r(X86::VPMOVUSQDZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4679 | 0 | } |
4680 | 0 | return 0; |
4681 | 0 | } |
4682 | | |
4683 | | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4684 | | switch (RetVT.SimpleTy) { |
4685 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v16i8_r(Op0, Op0IsKill); |
4686 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v8i16_r(Op0, Op0IsKill); |
4687 | | case MVT::v4i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v4i32_r(Op0, Op0IsKill); |
4688 | | default: return 0; |
4689 | | } |
4690 | | } |
4691 | | |
4692 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { |
4693 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4694 | 0 | return fastEmitInst_r(X86::VPMOVUSQBZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4695 | 0 | } |
4696 | 0 | return 0; |
4697 | 0 | } |
4698 | | |
4699 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { |
4700 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4701 | 0 | return fastEmitInst_r(X86::VPMOVUSQWZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4702 | 0 | } |
4703 | 0 | return 0; |
4704 | 0 | } |
4705 | | |
4706 | 0 | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
4707 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4708 | 0 | return fastEmitInst_r(X86::VPMOVUSQDZrr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4709 | 0 | } |
4710 | 0 | return 0; |
4711 | 0 | } |
4712 | | |
4713 | | unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4714 | | switch (RetVT.SimpleTy) { |
4715 | | case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v16i8_r(Op0, Op0IsKill); |
4716 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v8i16_r(Op0, Op0IsKill); |
4717 | | case MVT::v8i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v8i32_r(Op0, Op0IsKill); |
4718 | | default: return 0; |
4719 | | } |
4720 | | } |
4721 | | |
4722 | | unsigned fastEmit_X86ISD_VTRUNCUS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4723 | | switch (VT.SimpleTy) { |
4724 | | case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i16_r(RetVT, Op0, Op0IsKill); |
4725 | | case MVT::v16i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v16i16_r(RetVT, Op0, Op0IsKill); |
4726 | | case MVT::v32i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v32i16_r(RetVT, Op0, Op0IsKill); |
4727 | | case MVT::v4i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
4728 | | case MVT::v8i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
4729 | | case MVT::v16i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_r(RetVT, Op0, Op0IsKill); |
4730 | | case MVT::v2i64: return fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
4731 | | case MVT::v4i64: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_r(RetVT, Op0, Op0IsKill); |
4732 | | case MVT::v8i64: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_r(RetVT, Op0, Op0IsKill); |
4733 | | default: return 0; |
4734 | | } |
4735 | | } |
4736 | | |
4737 | | // FastEmit functions for X86ISD::VZEXT. |
4738 | | |
4739 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v16i8_MVT_v16i16_r(unsigned Op0, bool Op0IsKill) { |
4740 | 0 | if ((Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
4741 | 0 | return fastEmitInst_r(X86::VPMOVZXBWYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
4742 | 0 | } |
4743 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
4744 | 0 | return fastEmitInst_r(X86::VPMOVZXBWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4745 | 0 | } |
4746 | 0 | return 0; |
4747 | 0 | } |
4748 | | |
4749 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v16i8_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
4750 | 0 | if ((Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
4751 | 0 | return fastEmitInst_r(X86::VPMOVZXBDYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
4752 | 0 | } |
4753 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4754 | 0 | return fastEmitInst_r(X86::VPMOVZXBDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4755 | 0 | } |
4756 | 0 | return 0; |
4757 | 0 | } |
4758 | | |
4759 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v16i8_MVT_v16i32_r(unsigned Op0, bool Op0IsKill) { |
4760 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4761 | 0 | return fastEmitInst_r(X86::VPMOVZXBDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4762 | 0 | } |
4763 | 0 | return 0; |
4764 | 0 | } |
4765 | | |
4766 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v16i8_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
4767 | 0 | if ((Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
4768 | 0 | return fastEmitInst_r(X86::VPMOVZXBQYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
4769 | 0 | } |
4770 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4771 | 0 | return fastEmitInst_r(X86::VPMOVZXBQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4772 | 0 | } |
4773 | 0 | return 0; |
4774 | 0 | } |
4775 | | |
4776 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v16i8_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
4777 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4778 | 0 | return fastEmitInst_r(X86::VPMOVZXBQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4779 | 0 | } |
4780 | 0 | return 0; |
4781 | 0 | } |
4782 | | |
4783 | | unsigned fastEmit_X86ISD_VZEXT_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4784 | | switch (RetVT.SimpleTy) { |
4785 | | case MVT::v16i16: return fastEmit_X86ISD_VZEXT_MVT_v16i8_MVT_v16i16_r(Op0, Op0IsKill); |
4786 | | case MVT::v8i32: return fastEmit_X86ISD_VZEXT_MVT_v16i8_MVT_v8i32_r(Op0, Op0IsKill); |
4787 | | case MVT::v16i32: return fastEmit_X86ISD_VZEXT_MVT_v16i8_MVT_v16i32_r(Op0, Op0IsKill); |
4788 | | case MVT::v4i64: return fastEmit_X86ISD_VZEXT_MVT_v16i8_MVT_v4i64_r(Op0, Op0IsKill); |
4789 | | case MVT::v8i64: return fastEmit_X86ISD_VZEXT_MVT_v16i8_MVT_v8i64_r(Op0, Op0IsKill); |
4790 | | default: return 0; |
4791 | | } |
4792 | | } |
4793 | | |
4794 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v32i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4795 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
4796 | 0 | return 0; |
4797 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
4798 | 0 | return fastEmitInst_r(X86::VPMOVZXBWZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4799 | 0 | } |
4800 | 0 | return 0; |
4801 | 0 | } |
4802 | | |
4803 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v8i16_MVT_v8i32_r(unsigned Op0, bool Op0IsKill) { |
4804 | 0 | if ((Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
4805 | 0 | return fastEmitInst_r(X86::VPMOVZXWDYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
4806 | 0 | } |
4807 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4808 | 0 | return fastEmitInst_r(X86::VPMOVZXWDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4809 | 0 | } |
4810 | 0 | return 0; |
4811 | 0 | } |
4812 | | |
4813 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v8i16_MVT_v4i64_r(unsigned Op0, bool Op0IsKill) { |
4814 | 0 | if ((Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
4815 | 0 | return fastEmitInst_r(X86::VPMOVZXWQYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
4816 | 0 | } |
4817 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4818 | 0 | return fastEmitInst_r(X86::VPMOVZXWQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4819 | 0 | } |
4820 | 0 | return 0; |
4821 | 0 | } |
4822 | | |
4823 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v8i16_MVT_v8i64_r(unsigned Op0, bool Op0IsKill) { |
4824 | 0 | if ((Subtarget->hasAVX512())0 ) { |
4825 | 0 | return fastEmitInst_r(X86::VPMOVZXWQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4826 | 0 | } |
4827 | 0 | return 0; |
4828 | 0 | } |
4829 | | |
4830 | | unsigned fastEmit_X86ISD_VZEXT_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4831 | | switch (RetVT.SimpleTy) { |
4832 | | case MVT::v8i32: return fastEmit_X86ISD_VZEXT_MVT_v8i16_MVT_v8i32_r(Op0, Op0IsKill); |
4833 | | case MVT::v4i64: return fastEmit_X86ISD_VZEXT_MVT_v8i16_MVT_v4i64_r(Op0, Op0IsKill); |
4834 | | case MVT::v8i64: return fastEmit_X86ISD_VZEXT_MVT_v8i16_MVT_v8i64_r(Op0, Op0IsKill); |
4835 | | default: return 0; |
4836 | | } |
4837 | | } |
4838 | | |
4839 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v16i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4840 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
4841 | 0 | return 0; |
4842 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
4843 | 0 | return fastEmitInst_r(X86::VPMOVZXWDZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4844 | 0 | } |
4845 | 0 | return 0; |
4846 | 0 | } |
4847 | | |
4848 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4849 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
4850 | 0 | return 0; |
4851 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
4852 | 0 | return fastEmitInst_r(X86::VPMOVZXDQYrr, &X86::VR256RegClass, Op0, Op0IsKill); |
4853 | 0 | } |
4854 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
4855 | 0 | return fastEmitInst_r(X86::VPMOVZXDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill); |
4856 | 0 | } |
4857 | 0 | return 0; |
4858 | 0 | } |
4859 | | |
4860 | 0 | unsigned fastEmit_X86ISD_VZEXT_MVT_v8i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4861 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
4862 | 0 | return 0; |
4863 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
4864 | 0 | return fastEmitInst_r(X86::VPMOVZXDQZrr, &X86::VR512RegClass, Op0, Op0IsKill); |
4865 | 0 | } |
4866 | 0 | return 0; |
4867 | 0 | } |
4868 | | |
4869 | | unsigned fastEmit_X86ISD_VZEXT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4870 | | switch (VT.SimpleTy) { |
4871 | | case MVT::v16i8: return fastEmit_X86ISD_VZEXT_MVT_v16i8_r(RetVT, Op0, Op0IsKill); |
4872 | | case MVT::v32i8: return fastEmit_X86ISD_VZEXT_MVT_v32i8_r(RetVT, Op0, Op0IsKill); |
4873 | | case MVT::v8i16: return fastEmit_X86ISD_VZEXT_MVT_v8i16_r(RetVT, Op0, Op0IsKill); |
4874 | | case MVT::v16i16: return fastEmit_X86ISD_VZEXT_MVT_v16i16_r(RetVT, Op0, Op0IsKill); |
4875 | | case MVT::v4i32: return fastEmit_X86ISD_VZEXT_MVT_v4i32_r(RetVT, Op0, Op0IsKill); |
4876 | | case MVT::v8i32: return fastEmit_X86ISD_VZEXT_MVT_v8i32_r(RetVT, Op0, Op0IsKill); |
4877 | | default: return 0; |
4878 | | } |
4879 | | } |
4880 | | |
4881 | | // FastEmit functions for X86ISD::VZEXT_MOVL. |
4882 | | |
4883 | 0 | unsigned fastEmit_X86ISD_VZEXT_MOVL_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4884 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
4885 | 0 | return 0; |
4886 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
4887 | 0 | return fastEmitInst_r(X86::VMOVZPQILo2PQIZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4888 | 0 | } |
4889 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
4890 | 0 | return fastEmitInst_r(X86::MOVZPQILo2PQIrr, &X86::VR128RegClass, Op0, Op0IsKill); |
4891 | 0 | } |
4892 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
4893 | 0 | return fastEmitInst_r(X86::VMOVZPQILo2PQIrr, &X86::VR128RegClass, Op0, Op0IsKill); |
4894 | 0 | } |
4895 | 0 | return 0; |
4896 | 0 | } |
4897 | | |
4898 | 0 | unsigned fastEmit_X86ISD_VZEXT_MOVL_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4899 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4900 | 0 | return 0; |
4901 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
4902 | 0 | return fastEmitInst_r(X86::MOVZPQILo2PQIrr, &X86::VR128RegClass, Op0, Op0IsKill); |
4903 | 0 | } |
4904 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
4905 | 0 | return fastEmitInst_r(X86::VMOVZPQILo2PQIrr, &X86::VR128RegClass, Op0, Op0IsKill); |
4906 | 0 | } |
4907 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
4908 | 0 | return fastEmitInst_r(X86::VMOVZPQILo2PQIZrr, &X86::VR128XRegClass, Op0, Op0IsKill); |
4909 | 0 | } |
4910 | 0 | return 0; |
4911 | 0 | } |
4912 | | |
4913 | | unsigned fastEmit_X86ISD_VZEXT_MOVL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4914 | | switch (VT.SimpleTy) { |
4915 | | case MVT::v2i64: return fastEmit_X86ISD_VZEXT_MOVL_MVT_v2i64_r(RetVT, Op0, Op0IsKill); |
4916 | | case MVT::v2f64: return fastEmit_X86ISD_VZEXT_MOVL_MVT_v2f64_r(RetVT, Op0, Op0IsKill); |
4917 | | default: return 0; |
4918 | | } |
4919 | | } |
4920 | | |
4921 | | // FastEmit functions for X86ISD::WIN_ALLOCA. |
4922 | | |
4923 | 0 | unsigned fastEmit_X86ISD_WIN_ALLOCA_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4924 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
4925 | 0 | return 0; |
4926 | 0 | if (0 (!Subtarget->isTarget64BitLP64())0 ) { |
4927 | 0 | return fastEmitInst_r(X86::WIN_ALLOCA_32, &X86::GR32RegClass, Op0, Op0IsKill); |
4928 | 0 | } |
4929 | 0 | return 0; |
4930 | 0 | } |
4931 | | |
4932 | 0 | unsigned fastEmit_X86ISD_WIN_ALLOCA_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4933 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
4934 | 0 | return 0; |
4935 | 0 | if (0 (Subtarget->is64Bit())0 ) { |
4936 | 0 | return fastEmitInst_r(X86::WIN_ALLOCA_64, &X86::GR64RegClass, Op0, Op0IsKill); |
4937 | 0 | } |
4938 | 0 | return 0; |
4939 | 0 | } |
4940 | | |
4941 | | unsigned fastEmit_X86ISD_WIN_ALLOCA_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { |
4942 | | switch (VT.SimpleTy) { |
4943 | | case MVT::i32: return fastEmit_X86ISD_WIN_ALLOCA_MVT_i32_r(RetVT, Op0, Op0IsKill); |
4944 | | case MVT::i64: return fastEmit_X86ISD_WIN_ALLOCA_MVT_i64_r(RetVT, Op0, Op0IsKill); |
4945 | | default: return 0; |
4946 | | } |
4947 | | } |
4948 | | |
4949 | | // Top-level FastEmit function. |
4950 | | |
4951 | 2.13k | unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override { |
4952 | 2.13k | switch (Opcode) { |
4953 | 0 | case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0, Op0IsKill); |
4954 | 6 | case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0, Op0IsKill); |
4955 | 1.69k | case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill); |
4956 | 0 | case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill); |
4957 | 0 | case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill); |
4958 | 0 | case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill); |
4959 | 0 | case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill); |
4960 | 0 | case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0, Op0IsKill); |
4961 | 0 | case ISD::CTTZ_ZERO_UNDEF: return fastEmit_ISD_CTTZ_ZERO_UNDEF_r(VT, RetVT, Op0, Op0IsKill); |
4962 | 0 | case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill); |
4963 | 0 | case ISD::FCOS: return fastEmit_ISD_FCOS_r(VT, RetVT, Op0, Op0IsKill); |
4964 | 3 | case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill); |
4965 | 0 | case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill); |
4966 | 0 | case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill); |
4967 | 0 | case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill); |
4968 | 0 | case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill); |
4969 | 0 | case ISD::FSIN: return fastEmit_ISD_FSIN_r(VT, RetVT, Op0, Op0IsKill); |
4970 | 0 | case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill); |
4971 | 1 | case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0, Op0IsKill); |
4972 | 133 | case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill); |
4973 | 0 | case ISD::SIGN_EXTEND_VECTOR_INREG: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_r(VT, RetVT, Op0, Op0IsKill); |
4974 | 12 | case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); |
4975 | 49 | case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill); |
4976 | 0 | case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); |
4977 | 235 | case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill); |
4978 | 0 | case ISD::ZERO_EXTEND_VECTOR_INREG: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_r(VT, RetVT, Op0, Op0IsKill); |
4979 | 0 | case X86ISD::CALL: return fastEmit_X86ISD_CALL_r(VT, RetVT, Op0, Op0IsKill); |
4980 | 0 | case X86ISD::COMPRESS: return fastEmit_X86ISD_COMPRESS_r(VT, RetVT, Op0, Op0IsKill); |
4981 | 0 | case X86ISD::CONFLICT: return fastEmit_X86ISD_CONFLICT_r(VT, RetVT, Op0, Op0IsKill); |
4982 | 0 | case X86ISD::CVT2MASK: return fastEmit_X86ISD_CVT2MASK_r(VT, RetVT, Op0, Op0IsKill); |
4983 | 0 | case X86ISD::CVTP2SI: return fastEmit_X86ISD_CVTP2SI_r(VT, RetVT, Op0, Op0IsKill); |
4984 | 0 | case X86ISD::CVTP2UI: return fastEmit_X86ISD_CVTP2UI_r(VT, RetVT, Op0, Op0IsKill); |
4985 | 0 | case X86ISD::CVTSI2P: return fastEmit_X86ISD_CVTSI2P_r(VT, RetVT, Op0, Op0IsKill); |
4986 | 0 | case X86ISD::CVTTP2SI: return fastEmit_X86ISD_CVTTP2SI_r(VT, RetVT, Op0, Op0IsKill); |
4987 | 0 | case X86ISD::CVTTP2UI: return fastEmit_X86ISD_CVTTP2UI_r(VT, RetVT, Op0, Op0IsKill); |
4988 | 0 | case X86ISD::CVTUI2P: return fastEmit_X86ISD_CVTUI2P_r(VT, RetVT, Op0, Op0IsKill); |
4989 | 0 | case X86ISD::EH_RETURN: return fastEmit_X86ISD_EH_RETURN_r(VT, RetVT, Op0, Op0IsKill); |
4990 | 0 | case X86ISD::EXPAND: return fastEmit_X86ISD_EXPAND_r(VT, RetVT, Op0, Op0IsKill); |
4991 | 0 | case X86ISD::FRCP: return fastEmit_X86ISD_FRCP_r(VT, RetVT, Op0, Op0IsKill); |
4992 | 0 | case X86ISD::FRSQRT: return fastEmit_X86ISD_FRSQRT_r(VT, RetVT, Op0, Op0IsKill); |
4993 | 0 | case X86ISD::MMX_MOVD2W: return fastEmit_X86ISD_MMX_MOVD2W_r(VT, RetVT, Op0, Op0IsKill); |
4994 | 0 | case X86ISD::MMX_MOVW2D: return fastEmit_X86ISD_MMX_MOVW2D_r(VT, RetVT, Op0, Op0IsKill); |
4995 | 0 | case X86ISD::MOVDDUP: return fastEmit_X86ISD_MOVDDUP_r(VT, RetVT, Op0, Op0IsKill); |
4996 | 0 | case X86ISD::MOVDQ2Q: return fastEmit_X86ISD_MOVDQ2Q_r(VT, RetVT, Op0, Op0IsKill); |
4997 | 0 | case X86ISD::MOVMSK: return fastEmit_X86ISD_MOVMSK_r(VT, RetVT, Op0, Op0IsKill); |
4998 | 0 | case X86ISD::MOVSHDUP: return fastEmit_X86ISD_MOVSHDUP_r(VT, RetVT, Op0, Op0IsKill); |
4999 | 0 | case X86ISD::MOVSLDUP: return fastEmit_X86ISD_MOVSLDUP_r(VT, RetVT, Op0, Op0IsKill); |
5000 | 0 | case X86ISD::SEG_ALLOCA: return fastEmit_X86ISD_SEG_ALLOCA_r(VT, RetVT, Op0, Op0IsKill); |
5001 | 0 | case X86ISD::VBROADCAST: return fastEmit_X86ISD_VBROADCAST_r(VT, RetVT, Op0, Op0IsKill); |
5002 | 0 | case X86ISD::VBROADCASTM: return fastEmit_X86ISD_VBROADCASTM_r(VT, RetVT, Op0, Op0IsKill); |
5003 | 0 | case X86ISD::VFPEXT: return fastEmit_X86ISD_VFPEXT_r(VT, RetVT, Op0, Op0IsKill); |
5004 | 0 | case X86ISD::VFPROUND: return fastEmit_X86ISD_VFPROUND_r(VT, RetVT, Op0, Op0IsKill); |
5005 | 0 | case X86ISD::VSEXT: return fastEmit_X86ISD_VSEXT_r(VT, RetVT, Op0, Op0IsKill); |
5006 | 0 | case X86ISD::VTRUNC: return fastEmit_X86ISD_VTRUNC_r(VT, RetVT, Op0, Op0IsKill); |
5007 | 0 | case X86ISD::VTRUNCS: return fastEmit_X86ISD_VTRUNCS_r(VT, RetVT, Op0, Op0IsKill); |
5008 | 0 | case X86ISD::VTRUNCUS: return fastEmit_X86ISD_VTRUNCUS_r(VT, RetVT, Op0, Op0IsKill); |
5009 | 0 | case X86ISD::VZEXT: return fastEmit_X86ISD_VZEXT_r(VT, RetVT, Op0, Op0IsKill); |
5010 | 0 | case X86ISD::VZEXT_MOVL: return fastEmit_X86ISD_VZEXT_MOVL_r(VT, RetVT, Op0, Op0IsKill); |
5011 | 0 | case X86ISD::WIN_ALLOCA: return fastEmit_X86ISD_WIN_ALLOCA_r(VT, RetVT, Op0, Op0IsKill); |
5012 | 0 | default: return 0; |
5013 | 2.13k | } |
5014 | 2.13k | } |
5015 | | |
5016 | | // FastEmit functions for ISD::ADD. |
5017 | | |
5018 | 1 | unsigned fastEmit_ISD_ADD_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5019 | 1 | if (RetVT.SimpleTy != MVT::i8) |
5020 | 0 | return 0; |
5021 | 1 | return fastEmitInst_rr(X86::ADD8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5022 | 1 | } |
5023 | | |
5024 | 1 | unsigned fastEmit_ISD_ADD_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5025 | 1 | if (RetVT.SimpleTy != MVT::i16) |
5026 | 0 | return 0; |
5027 | 1 | return fastEmitInst_rr(X86::ADD16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5028 | 1 | } |
5029 | | |
5030 | 107 | unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5031 | 107 | if (RetVT.SimpleTy != MVT::i32) |
5032 | 0 | return 0; |
5033 | 107 | return fastEmitInst_rr(X86::ADD32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5034 | 107 | } |
5035 | | |
5036 | 32 | unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5037 | 32 | if (RetVT.SimpleTy != MVT::i64) |
5038 | 0 | return 0; |
5039 | 32 | return fastEmitInst_rr(X86::ADD64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5040 | 32 | } |
5041 | | |
5042 | 0 | unsigned fastEmit_ISD_ADD_MVT_v8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5043 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
5044 | 0 | return 0; |
5045 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
5046 | 0 | return fastEmitInst_rr(X86::KADDBrr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5047 | 0 | } |
5048 | 0 | return 0; |
5049 | 0 | } |
5050 | | |
5051 | 0 | unsigned fastEmit_ISD_ADD_MVT_v16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5052 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
5053 | 0 | return 0; |
5054 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
5055 | 0 | return fastEmitInst_rr(X86::KADDWrr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5056 | 0 | } |
5057 | 0 | return 0; |
5058 | 0 | } |
5059 | | |
5060 | 0 | unsigned fastEmit_ISD_ADD_MVT_v32i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5061 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
5062 | 0 | return 0; |
5063 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
5064 | 0 | return fastEmitInst_rr(X86::KADDDrr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5065 | 0 | } |
5066 | 0 | return 0; |
5067 | 0 | } |
5068 | | |
5069 | 0 | unsigned fastEmit_ISD_ADD_MVT_v64i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5070 | 0 | if (RetVT.SimpleTy != MVT::v64i1) |
5071 | 0 | return 0; |
5072 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
5073 | 0 | return fastEmitInst_rr(X86::KADDQrr, &X86::VK64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5074 | 0 | } |
5075 | 0 | return 0; |
5076 | 0 | } |
5077 | | |
5078 | 2 | unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5079 | 2 | if (RetVT.SimpleTy != MVT::v16i8) |
5080 | 0 | return 0; |
5081 | 2 | if (2 (Subtarget->hasBWI()) && 2 (Subtarget->hasVLX())0 ) { |
5082 | 0 | return fastEmitInst_rr(X86::VPADDBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5083 | 0 | } |
5084 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
5085 | 2 | return fastEmitInst_rr(X86::PADDBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5086 | 2 | } |
5087 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
5088 | 0 | return fastEmitInst_rr(X86::VPADDBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5089 | 0 | } |
5090 | 0 | return 0; |
5091 | 2 | } |
5092 | | |
5093 | 2 | unsigned fastEmit_ISD_ADD_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5094 | 2 | if (RetVT.SimpleTy != MVT::v32i8) |
5095 | 0 | return 0; |
5096 | 2 | if (2 (Subtarget->hasBWI()) && 2 (Subtarget->hasVLX())0 ) { |
5097 | 0 | return fastEmitInst_rr(X86::VPADDBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5098 | 0 | } |
5099 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX() || 2 !Subtarget->hasBWI()0 )) { |
5100 | 2 | return fastEmitInst_rr(X86::VPADDBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5101 | 2 | } |
5102 | 0 | return 0; |
5103 | 2 | } |
5104 | | |
5105 | 0 | unsigned fastEmit_ISD_ADD_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5106 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
5107 | 0 | return 0; |
5108 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
5109 | 0 | return fastEmitInst_rr(X86::VPADDBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5110 | 0 | } |
5111 | 0 | return 0; |
5112 | 0 | } |
5113 | | |
5114 | 2 | unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5115 | 2 | if (RetVT.SimpleTy != MVT::v8i16) |
5116 | 0 | return 0; |
5117 | 2 | if (2 (Subtarget->hasBWI()) && 2 (Subtarget->hasVLX())0 ) { |
5118 | 0 | return fastEmitInst_rr(X86::VPADDWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5119 | 0 | } |
5120 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
5121 | 2 | return fastEmitInst_rr(X86::PADDWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5122 | 2 | } |
5123 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
5124 | 0 | return fastEmitInst_rr(X86::VPADDWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5125 | 0 | } |
5126 | 0 | return 0; |
5127 | 2 | } |
5128 | | |
5129 | 2 | unsigned fastEmit_ISD_ADD_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5130 | 2 | if (RetVT.SimpleTy != MVT::v16i16) |
5131 | 0 | return 0; |
5132 | 2 | if (2 (Subtarget->hasBWI()) && 2 (Subtarget->hasVLX())0 ) { |
5133 | 0 | return fastEmitInst_rr(X86::VPADDWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5134 | 0 | } |
5135 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX() || 2 !Subtarget->hasBWI()0 )) { |
5136 | 2 | return fastEmitInst_rr(X86::VPADDWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5137 | 2 | } |
5138 | 0 | return 0; |
5139 | 2 | } |
5140 | | |
5141 | 0 | unsigned fastEmit_ISD_ADD_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5142 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
5143 | 0 | return 0; |
5144 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
5145 | 0 | return fastEmitInst_rr(X86::VPADDWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5146 | 0 | } |
5147 | 0 | return 0; |
5148 | 0 | } |
5149 | | |
5150 | 18 | unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5151 | 18 | if (RetVT.SimpleTy != MVT::v4i32) |
5152 | 0 | return 0; |
5153 | 18 | if (18 (Subtarget->hasAVX512()) && 18 (Subtarget->hasVLX())8 ) { |
5154 | 2 | return fastEmitInst_rr(X86::VPADDDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5155 | 2 | } |
5156 | 16 | if (16 (Subtarget->hasSSE2() && 16 !Subtarget->hasAVX()16 )) { |
5157 | 6 | return fastEmitInst_rr(X86::PADDDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5158 | 6 | } |
5159 | 10 | if (10 (Subtarget->hasAVX()) && 10 (!Subtarget->hasVLX())10 ) { |
5160 | 10 | return fastEmitInst_rr(X86::VPADDDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5161 | 10 | } |
5162 | 0 | return 0; |
5163 | 18 | } |
5164 | | |
5165 | 3 | unsigned fastEmit_ISD_ADD_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5166 | 3 | if (RetVT.SimpleTy != MVT::v8i32) |
5167 | 0 | return 0; |
5168 | 3 | if (3 (Subtarget->hasAVX512()) && 3 (Subtarget->hasVLX())1 ) { |
5169 | 1 | return fastEmitInst_rr(X86::VPADDDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5170 | 1 | } |
5171 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX())2 ) { |
5172 | 2 | return fastEmitInst_rr(X86::VPADDDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5173 | 2 | } |
5174 | 0 | return 0; |
5175 | 3 | } |
5176 | | |
5177 | 2 | unsigned fastEmit_ISD_ADD_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5178 | 2 | if (RetVT.SimpleTy != MVT::v16i32) |
5179 | 0 | return 0; |
5180 | 2 | if (2 (Subtarget->hasAVX512())2 ) { |
5181 | 2 | return fastEmitInst_rr(X86::VPADDDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5182 | 2 | } |
5183 | 0 | return 0; |
5184 | 2 | } |
5185 | | |
5186 | 2 | unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5187 | 2 | if (RetVT.SimpleTy != MVT::v2i64) |
5188 | 0 | return 0; |
5189 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5190 | 0 | return fastEmitInst_rr(X86::VPADDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5191 | 0 | } |
5192 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
5193 | 2 | return fastEmitInst_rr(X86::PADDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5194 | 2 | } |
5195 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
5196 | 0 | return fastEmitInst_rr(X86::VPADDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5197 | 0 | } |
5198 | 0 | return 0; |
5199 | 2 | } |
5200 | | |
5201 | 4 | unsigned fastEmit_ISD_ADD_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5202 | 4 | if (RetVT.SimpleTy != MVT::v4i64) |
5203 | 0 | return 0; |
5204 | 4 | if (4 (Subtarget->hasAVX512()) && 4 (Subtarget->hasVLX())2 ) { |
5205 | 2 | return fastEmitInst_rr(X86::VPADDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5206 | 2 | } |
5207 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX())2 ) { |
5208 | 2 | return fastEmitInst_rr(X86::VPADDQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5209 | 2 | } |
5210 | 0 | return 0; |
5211 | 4 | } |
5212 | | |
5213 | 0 | unsigned fastEmit_ISD_ADD_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5214 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
5215 | 0 | return 0; |
5216 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5217 | 0 | return fastEmitInst_rr(X86::VPADDQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5218 | 0 | } |
5219 | 0 | return 0; |
5220 | 0 | } |
5221 | | |
5222 | 178 | unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5223 | 178 | switch (VT.SimpleTy) { |
5224 | 1 | case MVT::i8: return fastEmit_ISD_ADD_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5225 | 1 | case MVT::i16: return fastEmit_ISD_ADD_MVT_i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5226 | 107 | case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5227 | 32 | case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5228 | 0 | case MVT::v8i1: return fastEmit_ISD_ADD_MVT_v8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5229 | 0 | case MVT::v16i1: return fastEmit_ISD_ADD_MVT_v16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5230 | 0 | case MVT::v32i1: return fastEmit_ISD_ADD_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5231 | 0 | case MVT::v64i1: return fastEmit_ISD_ADD_MVT_v64i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5232 | 2 | case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5233 | 2 | case MVT::v32i8: return fastEmit_ISD_ADD_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5234 | 0 | case MVT::v64i8: return fastEmit_ISD_ADD_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5235 | 2 | case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5236 | 2 | case MVT::v16i16: return fastEmit_ISD_ADD_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5237 | 0 | case MVT::v32i16: return fastEmit_ISD_ADD_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5238 | 18 | case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5239 | 3 | case MVT::v8i32: return fastEmit_ISD_ADD_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5240 | 2 | case MVT::v16i32: return fastEmit_ISD_ADD_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5241 | 2 | case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5242 | 4 | case MVT::v4i64: return fastEmit_ISD_ADD_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5243 | 0 | case MVT::v8i64: return fastEmit_ISD_ADD_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5244 | 0 | default: return 0; |
5245 | 178 | } |
5246 | 178 | } |
5247 | | |
5248 | | // FastEmit functions for ISD::AND. |
5249 | | |
5250 | 0 | unsigned fastEmit_ISD_AND_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5251 | 0 | if (RetVT.SimpleTy != MVT::i8) |
5252 | 0 | return 0; |
5253 | 0 | return fastEmitInst_rr(X86::AND8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5254 | 0 | } |
5255 | | |
5256 | 0 | unsigned fastEmit_ISD_AND_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5257 | 0 | if (RetVT.SimpleTy != MVT::i16) |
5258 | 0 | return 0; |
5259 | 0 | return fastEmitInst_rr(X86::AND16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5260 | 0 | } |
5261 | | |
5262 | 20 | unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5263 | 20 | if (RetVT.SimpleTy != MVT::i32) |
5264 | 0 | return 0; |
5265 | 20 | return fastEmitInst_rr(X86::AND32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5266 | 20 | } |
5267 | | |
5268 | 9 | unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5269 | 9 | if (RetVT.SimpleTy != MVT::i64) |
5270 | 0 | return 0; |
5271 | 9 | return fastEmitInst_rr(X86::AND64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5272 | 9 | } |
5273 | | |
5274 | 0 | unsigned fastEmit_ISD_AND_MVT_v8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5275 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
5276 | 0 | return 0; |
5277 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
5278 | 0 | return fastEmitInst_rr(X86::KANDBrr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5279 | 0 | } |
5280 | 0 | return 0; |
5281 | 0 | } |
5282 | | |
5283 | 0 | unsigned fastEmit_ISD_AND_MVT_v16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5284 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
5285 | 0 | return 0; |
5286 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5287 | 0 | return fastEmitInst_rr(X86::KANDWrr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5288 | 0 | } |
5289 | 0 | return 0; |
5290 | 0 | } |
5291 | | |
5292 | 0 | unsigned fastEmit_ISD_AND_MVT_v32i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5293 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
5294 | 0 | return 0; |
5295 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
5296 | 0 | return fastEmitInst_rr(X86::KANDDrr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5297 | 0 | } |
5298 | 0 | return 0; |
5299 | 0 | } |
5300 | | |
5301 | 0 | unsigned fastEmit_ISD_AND_MVT_v64i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5302 | 0 | if (RetVT.SimpleTy != MVT::v64i1) |
5303 | 0 | return 0; |
5304 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
5305 | 0 | return fastEmitInst_rr(X86::KANDQrr, &X86::VK64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5306 | 0 | } |
5307 | 0 | return 0; |
5308 | 0 | } |
5309 | | |
5310 | 8 | unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5311 | 8 | if (RetVT.SimpleTy != MVT::v2i64) |
5312 | 0 | return 0; |
5313 | 8 | if (8 (Subtarget->hasAVX512()) && 8 (Subtarget->hasVLX())0 ) { |
5314 | 0 | return fastEmitInst_rr(X86::VPANDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5315 | 0 | } |
5316 | 8 | if (8 (Subtarget->hasSSE2() && 8 !Subtarget->hasAVX()8 )) { |
5317 | 4 | return fastEmitInst_rr(X86::PANDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5318 | 4 | } |
5319 | 4 | if (4 (Subtarget->hasAVX()) && 4 (!Subtarget->hasVLX())4 ) { |
5320 | 4 | return fastEmitInst_rr(X86::VPANDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5321 | 4 | } |
5322 | 0 | return 0; |
5323 | 8 | } |
5324 | | |
5325 | 12 | unsigned fastEmit_ISD_AND_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5326 | 12 | if (RetVT.SimpleTy != MVT::v4i64) |
5327 | 0 | return 0; |
5328 | 12 | if (12 (Subtarget->hasAVX() && 12 !Subtarget->hasAVX2()12 )) { |
5329 | 8 | return fastEmitInst_rr(X86::VANDPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5330 | 8 | } |
5331 | 4 | if (4 (Subtarget->hasAVX512()) && 4 (Subtarget->hasVLX())0 ) { |
5332 | 0 | return fastEmitInst_rr(X86::VPANDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5333 | 0 | } |
5334 | 4 | if (4 (Subtarget->hasAVX2()) && 4 (!Subtarget->hasVLX())4 ) { |
5335 | 4 | return fastEmitInst_rr(X86::VPANDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5336 | 4 | } |
5337 | 0 | return 0; |
5338 | 12 | } |
5339 | | |
5340 | 0 | unsigned fastEmit_ISD_AND_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5341 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
5342 | 0 | return 0; |
5343 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5344 | 0 | return fastEmitInst_rr(X86::VPANDQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5345 | 0 | } |
5346 | 0 | return 0; |
5347 | 0 | } |
5348 | | |
5349 | 57 | unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5350 | 57 | switch (VT.SimpleTy) { |
5351 | 0 | case MVT::i8: return fastEmit_ISD_AND_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5352 | 0 | case MVT::i16: return fastEmit_ISD_AND_MVT_i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5353 | 20 | case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5354 | 9 | case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5355 | 0 | case MVT::v8i1: return fastEmit_ISD_AND_MVT_v8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5356 | 0 | case MVT::v16i1: return fastEmit_ISD_AND_MVT_v16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5357 | 0 | case MVT::v32i1: return fastEmit_ISD_AND_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5358 | 0 | case MVT::v64i1: return fastEmit_ISD_AND_MVT_v64i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5359 | 8 | case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5360 | 12 | case MVT::v4i64: return fastEmit_ISD_AND_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5361 | 0 | case MVT::v8i64: return fastEmit_ISD_AND_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5362 | 8 | default: return 0; |
5363 | 57 | } |
5364 | 57 | } |
5365 | | |
5366 | | // FastEmit functions for ISD::FADD. |
5367 | | |
5368 | 13 | unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5369 | 13 | if (RetVT.SimpleTy != MVT::f32) |
5370 | 0 | return 0; |
5371 | 13 | if (13 (Subtarget->hasAVX512())13 ) { |
5372 | 0 | return fastEmitInst_rr(X86::VADDSSZrr, &X86::FR32XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5373 | 0 | } |
5374 | 13 | if (13 (Subtarget->hasSSE1() && 13 !Subtarget->hasAVX()13 )) { |
5375 | 13 | return fastEmitInst_rr(X86::ADDSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5376 | 13 | } |
5377 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
5378 | 0 | return fastEmitInst_rr(X86::VADDSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5379 | 0 | } |
5380 | 0 | if (0 (!Subtarget->hasSSE1())0 ) { |
5381 | 0 | return fastEmitInst_rr(X86::ADD_Fp32, &X86::RFP32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5382 | 0 | } |
5383 | 0 | return 0; |
5384 | 13 | } |
5385 | | |
5386 | 13 | unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5387 | 13 | if (RetVT.SimpleTy != MVT::f64) |
5388 | 0 | return 0; |
5389 | 13 | if (13 (Subtarget->hasAVX512())13 ) { |
5390 | 0 | return fastEmitInst_rr(X86::VADDSDZrr, &X86::FR64XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5391 | 0 | } |
5392 | 13 | if (13 (Subtarget->hasSSE2() && 13 !Subtarget->hasAVX()13 )) { |
5393 | 13 | return fastEmitInst_rr(X86::ADDSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5394 | 13 | } |
5395 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
5396 | 0 | return fastEmitInst_rr(X86::VADDSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5397 | 0 | } |
5398 | 0 | if (0 (!Subtarget->hasSSE2())0 ) { |
5399 | 0 | return fastEmitInst_rr(X86::ADD_Fp64, &X86::RFP64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5400 | 0 | } |
5401 | 0 | return 0; |
5402 | 13 | } |
5403 | | |
5404 | 0 | unsigned fastEmit_ISD_FADD_MVT_f80_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5405 | 0 | if (RetVT.SimpleTy != MVT::f80) |
5406 | 0 | return 0; |
5407 | 0 | return fastEmitInst_rr(X86::ADD_Fp80, &X86::RFP80RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5408 | 0 | } |
5409 | | |
5410 | 2 | unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5411 | 2 | if (RetVT.SimpleTy != MVT::v4f32) |
5412 | 0 | return 0; |
5413 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5414 | 0 | return fastEmitInst_rr(X86::VADDPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5415 | 0 | } |
5416 | 2 | if (2 (Subtarget->hasSSE1() && 2 !Subtarget->hasAVX()2 )) { |
5417 | 2 | return fastEmitInst_rr(X86::ADDPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5418 | 2 | } |
5419 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
5420 | 0 | return fastEmitInst_rr(X86::VADDPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5421 | 0 | } |
5422 | 0 | return 0; |
5423 | 2 | } |
5424 | | |
5425 | 2 | unsigned fastEmit_ISD_FADD_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5426 | 2 | if (RetVT.SimpleTy != MVT::v8f32) |
5427 | 0 | return 0; |
5428 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5429 | 0 | return fastEmitInst_rr(X86::VADDPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5430 | 0 | } |
5431 | 2 | if (2 (Subtarget->hasAVX()) && 2 (!Subtarget->hasVLX())2 ) { |
5432 | 2 | return fastEmitInst_rr(X86::VADDPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5433 | 2 | } |
5434 | 0 | return 0; |
5435 | 2 | } |
5436 | | |
5437 | 0 | unsigned fastEmit_ISD_FADD_MVT_v16f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5438 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
5439 | 0 | return 0; |
5440 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5441 | 0 | return fastEmitInst_rr(X86::VADDPSZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5442 | 0 | } |
5443 | 0 | return 0; |
5444 | 0 | } |
5445 | | |
5446 | 18 | unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5447 | 18 | if (RetVT.SimpleTy != MVT::v2f64) |
5448 | 0 | return 0; |
5449 | 18 | if (18 (Subtarget->hasAVX512()) && 18 (Subtarget->hasVLX())8 ) { |
5450 | 2 | return fastEmitInst_rr(X86::VADDPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5451 | 2 | } |
5452 | 16 | if (16 (Subtarget->hasSSE2() && 16 !Subtarget->hasAVX()16 )) { |
5453 | 6 | return fastEmitInst_rr(X86::ADDPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5454 | 6 | } |
5455 | 10 | if (10 (Subtarget->hasAVX()) && 10 (!Subtarget->hasVLX())10 ) { |
5456 | 10 | return fastEmitInst_rr(X86::VADDPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5457 | 10 | } |
5458 | 0 | return 0; |
5459 | 18 | } |
5460 | | |
5461 | 14 | unsigned fastEmit_ISD_FADD_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5462 | 14 | if (RetVT.SimpleTy != MVT::v4f64) |
5463 | 0 | return 0; |
5464 | 14 | if (14 (Subtarget->hasAVX512()) && 14 (Subtarget->hasVLX())8 ) { |
5465 | 2 | return fastEmitInst_rr(X86::VADDPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5466 | 2 | } |
5467 | 12 | if (12 (Subtarget->hasAVX()) && 12 (!Subtarget->hasVLX())12 ) { |
5468 | 12 | return fastEmitInst_rr(X86::VADDPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5469 | 12 | } |
5470 | 0 | return 0; |
5471 | 14 | } |
5472 | | |
5473 | 8 | unsigned fastEmit_ISD_FADD_MVT_v8f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5474 | 8 | if (RetVT.SimpleTy != MVT::v8f64) |
5475 | 0 | return 0; |
5476 | 8 | if (8 (Subtarget->hasAVX512())8 ) { |
5477 | 8 | return fastEmitInst_rr(X86::VADDPDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5478 | 8 | } |
5479 | 0 | return 0; |
5480 | 8 | } |
5481 | | |
5482 | 70 | unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5483 | 70 | switch (VT.SimpleTy) { |
5484 | 13 | case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5485 | 13 | case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5486 | 0 | case MVT::f80: return fastEmit_ISD_FADD_MVT_f80_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5487 | 2 | case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5488 | 2 | case MVT::v8f32: return fastEmit_ISD_FADD_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5489 | 0 | case MVT::v16f32: return fastEmit_ISD_FADD_MVT_v16f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5490 | 18 | case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5491 | 14 | case MVT::v4f64: return fastEmit_ISD_FADD_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5492 | 8 | case MVT::v8f64: return fastEmit_ISD_FADD_MVT_v8f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5493 | 0 | default: return 0; |
5494 | 70 | } |
5495 | 70 | } |
5496 | | |
5497 | | // FastEmit functions for ISD::FDIV. |
5498 | | |
5499 | 0 | unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5500 | 0 | if (RetVT.SimpleTy != MVT::f32) |
5501 | 0 | return 0; |
5502 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5503 | 0 | return fastEmitInst_rr(X86::VDIVSSZrr, &X86::FR32XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5504 | 0 | } |
5505 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
5506 | 0 | return fastEmitInst_rr(X86::DIVSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5507 | 0 | } |
5508 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
5509 | 0 | return fastEmitInst_rr(X86::VDIVSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5510 | 0 | } |
5511 | 0 | if (0 (!Subtarget->hasSSE1())0 ) { |
5512 | 0 | return fastEmitInst_rr(X86::DIV_Fp32, &X86::RFP32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5513 | 0 | } |
5514 | 0 | return 0; |
5515 | 0 | } |
5516 | | |
5517 | 0 | unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5518 | 0 | if (RetVT.SimpleTy != MVT::f64) |
5519 | 0 | return 0; |
5520 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5521 | 0 | return fastEmitInst_rr(X86::VDIVSDZrr, &X86::FR64XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5522 | 0 | } |
5523 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
5524 | 0 | return fastEmitInst_rr(X86::DIVSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5525 | 0 | } |
5526 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
5527 | 0 | return fastEmitInst_rr(X86::VDIVSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5528 | 0 | } |
5529 | 0 | if (0 (!Subtarget->hasSSE2())0 ) { |
5530 | 0 | return fastEmitInst_rr(X86::DIV_Fp64, &X86::RFP64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5531 | 0 | } |
5532 | 0 | return 0; |
5533 | 0 | } |
5534 | | |
5535 | 0 | unsigned fastEmit_ISD_FDIV_MVT_f80_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5536 | 0 | if (RetVT.SimpleTy != MVT::f80) |
5537 | 0 | return 0; |
5538 | 0 | return fastEmitInst_rr(X86::DIV_Fp80, &X86::RFP80RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5539 | 0 | } |
5540 | | |
5541 | 2 | unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5542 | 2 | if (RetVT.SimpleTy != MVT::v4f32) |
5543 | 0 | return 0; |
5544 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5545 | 0 | return fastEmitInst_rr(X86::VDIVPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5546 | 0 | } |
5547 | 2 | if (2 (Subtarget->hasSSE1() && 2 !Subtarget->hasAVX()2 )) { |
5548 | 2 | return fastEmitInst_rr(X86::DIVPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5549 | 2 | } |
5550 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
5551 | 0 | return fastEmitInst_rr(X86::VDIVPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5552 | 0 | } |
5553 | 0 | return 0; |
5554 | 2 | } |
5555 | | |
5556 | 2 | unsigned fastEmit_ISD_FDIV_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5557 | 2 | if (RetVT.SimpleTy != MVT::v8f32) |
5558 | 0 | return 0; |
5559 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5560 | 0 | return fastEmitInst_rr(X86::VDIVPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5561 | 0 | } |
5562 | 2 | if (2 (Subtarget->hasAVX()) && 2 (!Subtarget->hasVLX())2 ) { |
5563 | 2 | return fastEmitInst_rr(X86::VDIVPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5564 | 2 | } |
5565 | 0 | return 0; |
5566 | 2 | } |
5567 | | |
5568 | 0 | unsigned fastEmit_ISD_FDIV_MVT_v16f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5569 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
5570 | 0 | return 0; |
5571 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5572 | 0 | return fastEmitInst_rr(X86::VDIVPSZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5573 | 0 | } |
5574 | 0 | return 0; |
5575 | 0 | } |
5576 | | |
5577 | 2 | unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5578 | 2 | if (RetVT.SimpleTy != MVT::v2f64) |
5579 | 0 | return 0; |
5580 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5581 | 0 | return fastEmitInst_rr(X86::VDIVPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5582 | 0 | } |
5583 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
5584 | 2 | return fastEmitInst_rr(X86::DIVPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5585 | 2 | } |
5586 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
5587 | 0 | return fastEmitInst_rr(X86::VDIVPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5588 | 0 | } |
5589 | 0 | return 0; |
5590 | 2 | } |
5591 | | |
5592 | 2 | unsigned fastEmit_ISD_FDIV_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5593 | 2 | if (RetVT.SimpleTy != MVT::v4f64) |
5594 | 0 | return 0; |
5595 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5596 | 0 | return fastEmitInst_rr(X86::VDIVPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5597 | 0 | } |
5598 | 2 | if (2 (Subtarget->hasAVX()) && 2 (!Subtarget->hasVLX())2 ) { |
5599 | 2 | return fastEmitInst_rr(X86::VDIVPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5600 | 2 | } |
5601 | 0 | return 0; |
5602 | 2 | } |
5603 | | |
5604 | 0 | unsigned fastEmit_ISD_FDIV_MVT_v8f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5605 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
5606 | 0 | return 0; |
5607 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5608 | 0 | return fastEmitInst_rr(X86::VDIVPDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5609 | 0 | } |
5610 | 0 | return 0; |
5611 | 0 | } |
5612 | | |
5613 | 8 | unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5614 | 8 | switch (VT.SimpleTy) { |
5615 | 0 | case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5616 | 0 | case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5617 | 0 | case MVT::f80: return fastEmit_ISD_FDIV_MVT_f80_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5618 | 2 | case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5619 | 2 | case MVT::v8f32: return fastEmit_ISD_FDIV_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5620 | 0 | case MVT::v16f32: return fastEmit_ISD_FDIV_MVT_v16f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5621 | 2 | case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5622 | 2 | case MVT::v4f64: return fastEmit_ISD_FDIV_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5623 | 0 | case MVT::v8f64: return fastEmit_ISD_FDIV_MVT_v8f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5624 | 0 | default: return 0; |
5625 | 8 | } |
5626 | 8 | } |
5627 | | |
5628 | | // FastEmit functions for ISD::FMUL. |
5629 | | |
5630 | 0 | unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5631 | 0 | if (RetVT.SimpleTy != MVT::f32) |
5632 | 0 | return 0; |
5633 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5634 | 0 | return fastEmitInst_rr(X86::VMULSSZrr, &X86::FR32XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5635 | 0 | } |
5636 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
5637 | 0 | return fastEmitInst_rr(X86::MULSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5638 | 0 | } |
5639 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
5640 | 0 | return fastEmitInst_rr(X86::VMULSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5641 | 0 | } |
5642 | 0 | if (0 (!Subtarget->hasSSE1())0 ) { |
5643 | 0 | return fastEmitInst_rr(X86::MUL_Fp32, &X86::RFP32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5644 | 0 | } |
5645 | 0 | return 0; |
5646 | 0 | } |
5647 | | |
5648 | 2 | unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5649 | 2 | if (RetVT.SimpleTy != MVT::f64) |
5650 | 0 | return 0; |
5651 | 2 | if (2 (Subtarget->hasAVX512())2 ) { |
5652 | 0 | return fastEmitInst_rr(X86::VMULSDZrr, &X86::FR64XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5653 | 0 | } |
5654 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
5655 | 2 | return fastEmitInst_rr(X86::MULSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5656 | 2 | } |
5657 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
5658 | 0 | return fastEmitInst_rr(X86::VMULSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5659 | 0 | } |
5660 | 0 | if (0 (!Subtarget->hasSSE2())0 ) { |
5661 | 0 | return fastEmitInst_rr(X86::MUL_Fp64, &X86::RFP64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5662 | 0 | } |
5663 | 0 | return 0; |
5664 | 2 | } |
5665 | | |
5666 | 0 | unsigned fastEmit_ISD_FMUL_MVT_f80_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5667 | 0 | if (RetVT.SimpleTy != MVT::f80) |
5668 | 0 | return 0; |
5669 | 0 | return fastEmitInst_rr(X86::MUL_Fp80, &X86::RFP80RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5670 | 0 | } |
5671 | | |
5672 | 2 | unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5673 | 2 | if (RetVT.SimpleTy != MVT::v4f32) |
5674 | 0 | return 0; |
5675 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5676 | 0 | return fastEmitInst_rr(X86::VMULPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5677 | 0 | } |
5678 | 2 | if (2 (Subtarget->hasSSE1() && 2 !Subtarget->hasAVX()2 )) { |
5679 | 2 | return fastEmitInst_rr(X86::MULPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5680 | 2 | } |
5681 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
5682 | 0 | return fastEmitInst_rr(X86::VMULPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5683 | 0 | } |
5684 | 0 | return 0; |
5685 | 2 | } |
5686 | | |
5687 | 2 | unsigned fastEmit_ISD_FMUL_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5688 | 2 | if (RetVT.SimpleTy != MVT::v8f32) |
5689 | 0 | return 0; |
5690 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5691 | 0 | return fastEmitInst_rr(X86::VMULPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5692 | 0 | } |
5693 | 2 | if (2 (Subtarget->hasAVX()) && 2 (!Subtarget->hasVLX())2 ) { |
5694 | 2 | return fastEmitInst_rr(X86::VMULPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5695 | 2 | } |
5696 | 0 | return 0; |
5697 | 2 | } |
5698 | | |
5699 | 0 | unsigned fastEmit_ISD_FMUL_MVT_v16f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5700 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
5701 | 0 | return 0; |
5702 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5703 | 0 | return fastEmitInst_rr(X86::VMULPSZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5704 | 0 | } |
5705 | 0 | return 0; |
5706 | 0 | } |
5707 | | |
5708 | 2 | unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5709 | 2 | if (RetVT.SimpleTy != MVT::v2f64) |
5710 | 0 | return 0; |
5711 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5712 | 0 | return fastEmitInst_rr(X86::VMULPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5713 | 0 | } |
5714 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
5715 | 2 | return fastEmitInst_rr(X86::MULPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5716 | 2 | } |
5717 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
5718 | 0 | return fastEmitInst_rr(X86::VMULPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5719 | 0 | } |
5720 | 0 | return 0; |
5721 | 2 | } |
5722 | | |
5723 | 2 | unsigned fastEmit_ISD_FMUL_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5724 | 2 | if (RetVT.SimpleTy != MVT::v4f64) |
5725 | 0 | return 0; |
5726 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5727 | 0 | return fastEmitInst_rr(X86::VMULPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5728 | 0 | } |
5729 | 2 | if (2 (Subtarget->hasAVX()) && 2 (!Subtarget->hasVLX())2 ) { |
5730 | 2 | return fastEmitInst_rr(X86::VMULPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5731 | 2 | } |
5732 | 0 | return 0; |
5733 | 2 | } |
5734 | | |
5735 | 0 | unsigned fastEmit_ISD_FMUL_MVT_v8f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5736 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
5737 | 0 | return 0; |
5738 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5739 | 0 | return fastEmitInst_rr(X86::VMULPDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5740 | 0 | } |
5741 | 0 | return 0; |
5742 | 0 | } |
5743 | | |
5744 | 10 | unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5745 | 10 | switch (VT.SimpleTy) { |
5746 | 0 | case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5747 | 2 | case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5748 | 0 | case MVT::f80: return fastEmit_ISD_FMUL_MVT_f80_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5749 | 2 | case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5750 | 2 | case MVT::v8f32: return fastEmit_ISD_FMUL_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5751 | 0 | case MVT::v16f32: return fastEmit_ISD_FMUL_MVT_v16f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5752 | 2 | case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5753 | 2 | case MVT::v4f64: return fastEmit_ISD_FMUL_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5754 | 0 | case MVT::v8f64: return fastEmit_ISD_FMUL_MVT_v8f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5755 | 0 | default: return 0; |
5756 | 10 | } |
5757 | 10 | } |
5758 | | |
5759 | | // FastEmit functions for ISD::FSUB. |
5760 | | |
5761 | 0 | unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5762 | 0 | if (RetVT.SimpleTy != MVT::f32) |
5763 | 0 | return 0; |
5764 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5765 | 0 | return fastEmitInst_rr(X86::VSUBSSZrr, &X86::FR32XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5766 | 0 | } |
5767 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
5768 | 0 | return fastEmitInst_rr(X86::SUBSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5769 | 0 | } |
5770 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
5771 | 0 | return fastEmitInst_rr(X86::VSUBSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5772 | 0 | } |
5773 | 0 | if (0 (!Subtarget->hasSSE1())0 ) { |
5774 | 0 | return fastEmitInst_rr(X86::SUB_Fp32, &X86::RFP32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5775 | 0 | } |
5776 | 0 | return 0; |
5777 | 0 | } |
5778 | | |
5779 | 2 | unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5780 | 2 | if (RetVT.SimpleTy != MVT::f64) |
5781 | 0 | return 0; |
5782 | 2 | if (2 (Subtarget->hasAVX512())2 ) { |
5783 | 0 | return fastEmitInst_rr(X86::VSUBSDZrr, &X86::FR64XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5784 | 0 | } |
5785 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
5786 | 2 | return fastEmitInst_rr(X86::SUBSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5787 | 2 | } |
5788 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
5789 | 0 | return fastEmitInst_rr(X86::VSUBSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5790 | 0 | } |
5791 | 0 | if (0 (!Subtarget->hasSSE2())0 ) { |
5792 | 0 | return fastEmitInst_rr(X86::SUB_Fp64, &X86::RFP64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5793 | 0 | } |
5794 | 0 | return 0; |
5795 | 2 | } |
5796 | | |
5797 | 0 | unsigned fastEmit_ISD_FSUB_MVT_f80_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5798 | 0 | if (RetVT.SimpleTy != MVT::f80) |
5799 | 0 | return 0; |
5800 | 0 | return fastEmitInst_rr(X86::SUB_Fp80, &X86::RFP80RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5801 | 0 | } |
5802 | | |
5803 | 2 | unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5804 | 2 | if (RetVT.SimpleTy != MVT::v4f32) |
5805 | 0 | return 0; |
5806 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5807 | 0 | return fastEmitInst_rr(X86::VSUBPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5808 | 0 | } |
5809 | 2 | if (2 (Subtarget->hasSSE1() && 2 !Subtarget->hasAVX()2 )) { |
5810 | 2 | return fastEmitInst_rr(X86::SUBPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5811 | 2 | } |
5812 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
5813 | 0 | return fastEmitInst_rr(X86::VSUBPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5814 | 0 | } |
5815 | 0 | return 0; |
5816 | 2 | } |
5817 | | |
5818 | 2 | unsigned fastEmit_ISD_FSUB_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5819 | 2 | if (RetVT.SimpleTy != MVT::v8f32) |
5820 | 0 | return 0; |
5821 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5822 | 0 | return fastEmitInst_rr(X86::VSUBPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5823 | 0 | } |
5824 | 2 | if (2 (Subtarget->hasAVX()) && 2 (!Subtarget->hasVLX())2 ) { |
5825 | 2 | return fastEmitInst_rr(X86::VSUBPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5826 | 2 | } |
5827 | 0 | return 0; |
5828 | 2 | } |
5829 | | |
5830 | 0 | unsigned fastEmit_ISD_FSUB_MVT_v16f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5831 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
5832 | 0 | return 0; |
5833 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5834 | 0 | return fastEmitInst_rr(X86::VSUBPSZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5835 | 0 | } |
5836 | 0 | return 0; |
5837 | 0 | } |
5838 | | |
5839 | 2 | unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5840 | 2 | if (RetVT.SimpleTy != MVT::v2f64) |
5841 | 0 | return 0; |
5842 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5843 | 0 | return fastEmitInst_rr(X86::VSUBPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5844 | 0 | } |
5845 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
5846 | 2 | return fastEmitInst_rr(X86::SUBPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5847 | 2 | } |
5848 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
5849 | 0 | return fastEmitInst_rr(X86::VSUBPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5850 | 0 | } |
5851 | 0 | return 0; |
5852 | 2 | } |
5853 | | |
5854 | 2 | unsigned fastEmit_ISD_FSUB_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5855 | 2 | if (RetVT.SimpleTy != MVT::v4f64) |
5856 | 0 | return 0; |
5857 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5858 | 0 | return fastEmitInst_rr(X86::VSUBPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5859 | 0 | } |
5860 | 2 | if (2 (Subtarget->hasAVX()) && 2 (!Subtarget->hasVLX())2 ) { |
5861 | 2 | return fastEmitInst_rr(X86::VSUBPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5862 | 2 | } |
5863 | 0 | return 0; |
5864 | 2 | } |
5865 | | |
5866 | 0 | unsigned fastEmit_ISD_FSUB_MVT_v8f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5867 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
5868 | 0 | return 0; |
5869 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5870 | 0 | return fastEmitInst_rr(X86::VSUBPDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5871 | 0 | } |
5872 | 0 | return 0; |
5873 | 0 | } |
5874 | | |
5875 | 10 | unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5876 | 10 | switch (VT.SimpleTy) { |
5877 | 0 | case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5878 | 2 | case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5879 | 0 | case MVT::f80: return fastEmit_ISD_FSUB_MVT_f80_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5880 | 2 | case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5881 | 2 | case MVT::v8f32: return fastEmit_ISD_FSUB_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5882 | 0 | case MVT::v16f32: return fastEmit_ISD_FSUB_MVT_v16f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5883 | 2 | case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5884 | 2 | case MVT::v4f64: return fastEmit_ISD_FSUB_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5885 | 0 | case MVT::v8f64: return fastEmit_ISD_FSUB_MVT_v8f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
5886 | 0 | default: return 0; |
5887 | 10 | } |
5888 | 10 | } |
5889 | | |
5890 | | // FastEmit functions for ISD::MUL. |
5891 | | |
5892 | 2 | unsigned fastEmit_ISD_MUL_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5893 | 2 | if (RetVT.SimpleTy != MVT::i8) |
5894 | 0 | return 0; |
5895 | 2 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::AL).addReg(Op0); |
5896 | 2 | return fastEmitInst_r(X86::MUL8r, &X86::GR8RegClass, Op1, Op1IsKill); |
5897 | 2 | } |
5898 | | |
5899 | 0 | unsigned fastEmit_ISD_MUL_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5900 | 0 | if (RetVT.SimpleTy != MVT::i16) |
5901 | 0 | return 0; |
5902 | 0 | return fastEmitInst_rr(X86::IMUL16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5903 | 0 | } |
5904 | | |
5905 | 6 | unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5906 | 6 | if (RetVT.SimpleTy != MVT::i32) |
5907 | 0 | return 0; |
5908 | 6 | return fastEmitInst_rr(X86::IMUL32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5909 | 6 | } |
5910 | | |
5911 | 0 | unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5912 | 0 | if (RetVT.SimpleTy != MVT::i64) |
5913 | 0 | return 0; |
5914 | 0 | return fastEmitInst_rr(X86::IMUL64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5915 | 0 | } |
5916 | | |
5917 | 2 | unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5918 | 2 | if (RetVT.SimpleTy != MVT::v8i16) |
5919 | 0 | return 0; |
5920 | 2 | if (2 (Subtarget->hasBWI()) && 2 (Subtarget->hasVLX())0 ) { |
5921 | 0 | return fastEmitInst_rr(X86::VPMULLWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5922 | 0 | } |
5923 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
5924 | 2 | return fastEmitInst_rr(X86::PMULLWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5925 | 2 | } |
5926 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
5927 | 0 | return fastEmitInst_rr(X86::VPMULLWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5928 | 0 | } |
5929 | 0 | return 0; |
5930 | 2 | } |
5931 | | |
5932 | 2 | unsigned fastEmit_ISD_MUL_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5933 | 2 | if (RetVT.SimpleTy != MVT::v16i16) |
5934 | 0 | return 0; |
5935 | 2 | if (2 (Subtarget->hasBWI()) && 2 (Subtarget->hasVLX())0 ) { |
5936 | 0 | return fastEmitInst_rr(X86::VPMULLWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5937 | 0 | } |
5938 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX() || 2 !Subtarget->hasBWI()0 )) { |
5939 | 2 | return fastEmitInst_rr(X86::VPMULLWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5940 | 2 | } |
5941 | 0 | return 0; |
5942 | 2 | } |
5943 | | |
5944 | 0 | unsigned fastEmit_ISD_MUL_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5945 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
5946 | 0 | return 0; |
5947 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
5948 | 0 | return fastEmitInst_rr(X86::VPMULLWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5949 | 0 | } |
5950 | 0 | return 0; |
5951 | 0 | } |
5952 | | |
5953 | 2 | unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5954 | 2 | if (RetVT.SimpleTy != MVT::v4i32) |
5955 | 0 | return 0; |
5956 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5957 | 0 | return fastEmitInst_rr(X86::VPMULLDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5958 | 0 | } |
5959 | 2 | if (2 (Subtarget->hasSSE41() && 2 !Subtarget->hasAVX()2 )) { |
5960 | 2 | return fastEmitInst_rr(X86::PMULLDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5961 | 2 | } |
5962 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
5963 | 0 | return fastEmitInst_rr(X86::VPMULLDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5964 | 0 | } |
5965 | 0 | return 0; |
5966 | 2 | } |
5967 | | |
5968 | 2 | unsigned fastEmit_ISD_MUL_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5969 | 2 | if (RetVT.SimpleTy != MVT::v8i32) |
5970 | 0 | return 0; |
5971 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
5972 | 0 | return fastEmitInst_rr(X86::VPMULLDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5973 | 0 | } |
5974 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX())2 ) { |
5975 | 2 | return fastEmitInst_rr(X86::VPMULLDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5976 | 2 | } |
5977 | 0 | return 0; |
5978 | 2 | } |
5979 | | |
5980 | 0 | unsigned fastEmit_ISD_MUL_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5981 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
5982 | 0 | return 0; |
5983 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
5984 | 0 | return fastEmitInst_rr(X86::VPMULLDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5985 | 0 | } |
5986 | 0 | return 0; |
5987 | 0 | } |
5988 | | |
5989 | 0 | unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5990 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
5991 | 0 | return 0; |
5992 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
5993 | 0 | return fastEmitInst_rr(X86::VPMULLQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
5994 | 0 | } |
5995 | 0 | return 0; |
5996 | 0 | } |
5997 | | |
5998 | 0 | unsigned fastEmit_ISD_MUL_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
5999 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
6000 | 0 | return 0; |
6001 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
6002 | 0 | return fastEmitInst_rr(X86::VPMULLQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6003 | 0 | } |
6004 | 0 | return 0; |
6005 | 0 | } |
6006 | | |
6007 | 0 | unsigned fastEmit_ISD_MUL_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6008 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
6009 | 0 | return 0; |
6010 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
6011 | 0 | return fastEmitInst_rr(X86::VPMULLQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6012 | 0 | } |
6013 | 0 | return 0; |
6014 | 0 | } |
6015 | | |
6016 | 16 | unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6017 | 16 | switch (VT.SimpleTy) { |
6018 | 2 | case MVT::i8: return fastEmit_ISD_MUL_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6019 | 0 | case MVT::i16: return fastEmit_ISD_MUL_MVT_i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6020 | 6 | case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6021 | 0 | case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6022 | 2 | case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6023 | 2 | case MVT::v16i16: return fastEmit_ISD_MUL_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6024 | 0 | case MVT::v32i16: return fastEmit_ISD_MUL_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6025 | 2 | case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6026 | 2 | case MVT::v8i32: return fastEmit_ISD_MUL_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6027 | 0 | case MVT::v16i32: return fastEmit_ISD_MUL_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6028 | 0 | case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6029 | 0 | case MVT::v4i64: return fastEmit_ISD_MUL_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6030 | 0 | case MVT::v8i64: return fastEmit_ISD_MUL_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6031 | 0 | default: return 0; |
6032 | 16 | } |
6033 | 16 | } |
6034 | | |
6035 | | // FastEmit functions for ISD::MULHS. |
6036 | | |
6037 | 0 | unsigned fastEmit_ISD_MULHS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6038 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
6039 | 0 | return 0; |
6040 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6041 | 0 | return fastEmitInst_rr(X86::VPMULHWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6042 | 0 | } |
6043 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
6044 | 0 | return fastEmitInst_rr(X86::PMULHWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6045 | 0 | } |
6046 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6047 | 0 | return fastEmitInst_rr(X86::VPMULHWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6048 | 0 | } |
6049 | 0 | return 0; |
6050 | 0 | } |
6051 | | |
6052 | 0 | unsigned fastEmit_ISD_MULHS_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6053 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
6054 | 0 | return 0; |
6055 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6056 | 0 | return fastEmitInst_rr(X86::VPMULHWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6057 | 0 | } |
6058 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6059 | 0 | return fastEmitInst_rr(X86::VPMULHWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6060 | 0 | } |
6061 | 0 | return 0; |
6062 | 0 | } |
6063 | | |
6064 | 0 | unsigned fastEmit_ISD_MULHS_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6065 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
6066 | 0 | return 0; |
6067 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
6068 | 0 | return fastEmitInst_rr(X86::VPMULHWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6069 | 0 | } |
6070 | 0 | return 0; |
6071 | 0 | } |
6072 | | |
6073 | | unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6074 | | switch (VT.SimpleTy) { |
6075 | | case MVT::v8i16: return fastEmit_ISD_MULHS_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6076 | | case MVT::v16i16: return fastEmit_ISD_MULHS_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6077 | | case MVT::v32i16: return fastEmit_ISD_MULHS_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6078 | | default: return 0; |
6079 | | } |
6080 | | } |
6081 | | |
6082 | | // FastEmit functions for ISD::MULHU. |
6083 | | |
6084 | 0 | unsigned fastEmit_ISD_MULHU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6085 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
6086 | 0 | return 0; |
6087 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6088 | 0 | return fastEmitInst_rr(X86::VPMULHUWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6089 | 0 | } |
6090 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
6091 | 0 | return fastEmitInst_rr(X86::PMULHUWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6092 | 0 | } |
6093 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6094 | 0 | return fastEmitInst_rr(X86::VPMULHUWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6095 | 0 | } |
6096 | 0 | return 0; |
6097 | 0 | } |
6098 | | |
6099 | 0 | unsigned fastEmit_ISD_MULHU_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6100 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
6101 | 0 | return 0; |
6102 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6103 | 0 | return fastEmitInst_rr(X86::VPMULHUWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6104 | 0 | } |
6105 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6106 | 0 | return fastEmitInst_rr(X86::VPMULHUWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6107 | 0 | } |
6108 | 0 | return 0; |
6109 | 0 | } |
6110 | | |
6111 | 0 | unsigned fastEmit_ISD_MULHU_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6112 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
6113 | 0 | return 0; |
6114 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
6115 | 0 | return fastEmitInst_rr(X86::VPMULHUWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6116 | 0 | } |
6117 | 0 | return 0; |
6118 | 0 | } |
6119 | | |
6120 | | unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6121 | | switch (VT.SimpleTy) { |
6122 | | case MVT::v8i16: return fastEmit_ISD_MULHU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6123 | | case MVT::v16i16: return fastEmit_ISD_MULHU_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6124 | | case MVT::v32i16: return fastEmit_ISD_MULHU_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6125 | | default: return 0; |
6126 | | } |
6127 | | } |
6128 | | |
6129 | | // FastEmit functions for ISD::OR. |
6130 | | |
6131 | 0 | unsigned fastEmit_ISD_OR_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6132 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6133 | 0 | return 0; |
6134 | 0 | return fastEmitInst_rr(X86::OR8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6135 | 0 | } |
6136 | | |
6137 | 2 | unsigned fastEmit_ISD_OR_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6138 | 2 | if (RetVT.SimpleTy != MVT::i16) |
6139 | 0 | return 0; |
6140 | 2 | return fastEmitInst_rr(X86::OR16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6141 | 2 | } |
6142 | | |
6143 | 26 | unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6144 | 26 | if (RetVT.SimpleTy != MVT::i32) |
6145 | 0 | return 0; |
6146 | 26 | return fastEmitInst_rr(X86::OR32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6147 | 26 | } |
6148 | | |
6149 | 19 | unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6150 | 19 | if (RetVT.SimpleTy != MVT::i64) |
6151 | 0 | return 0; |
6152 | 19 | return fastEmitInst_rr(X86::OR64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6153 | 19 | } |
6154 | | |
6155 | 0 | unsigned fastEmit_ISD_OR_MVT_v8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6156 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
6157 | 0 | return 0; |
6158 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
6159 | 0 | return fastEmitInst_rr(X86::KORBrr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6160 | 0 | } |
6161 | 0 | return 0; |
6162 | 0 | } |
6163 | | |
6164 | 0 | unsigned fastEmit_ISD_OR_MVT_v16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6165 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
6166 | 0 | return 0; |
6167 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6168 | 0 | return fastEmitInst_rr(X86::KORWrr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6169 | 0 | } |
6170 | 0 | return 0; |
6171 | 0 | } |
6172 | | |
6173 | 0 | unsigned fastEmit_ISD_OR_MVT_v32i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6174 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
6175 | 0 | return 0; |
6176 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
6177 | 0 | return fastEmitInst_rr(X86::KORDrr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6178 | 0 | } |
6179 | 0 | return 0; |
6180 | 0 | } |
6181 | | |
6182 | 0 | unsigned fastEmit_ISD_OR_MVT_v64i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6183 | 0 | if (RetVT.SimpleTy != MVT::v64i1) |
6184 | 0 | return 0; |
6185 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
6186 | 0 | return fastEmitInst_rr(X86::KORQrr, &X86::VK64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6187 | 0 | } |
6188 | 0 | return 0; |
6189 | 0 | } |
6190 | | |
6191 | 4 | unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6192 | 4 | if (RetVT.SimpleTy != MVT::v2i64) |
6193 | 0 | return 0; |
6194 | 4 | if (4 (Subtarget->hasAVX512()) && 4 (Subtarget->hasVLX())0 ) { |
6195 | 0 | return fastEmitInst_rr(X86::VPORQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6196 | 0 | } |
6197 | 4 | if (4 (Subtarget->hasSSE2() && 4 !Subtarget->hasAVX()4 )) { |
6198 | 2 | return fastEmitInst_rr(X86::PORrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6199 | 2 | } |
6200 | 2 | if (2 (Subtarget->hasAVX()) && 2 (!Subtarget->hasVLX())2 ) { |
6201 | 2 | return fastEmitInst_rr(X86::VPORrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6202 | 2 | } |
6203 | 0 | return 0; |
6204 | 4 | } |
6205 | | |
6206 | 6 | unsigned fastEmit_ISD_OR_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6207 | 6 | if (RetVT.SimpleTy != MVT::v4i64) |
6208 | 0 | return 0; |
6209 | 6 | if (6 (Subtarget->hasAVX() && 6 !Subtarget->hasAVX2()6 )) { |
6210 | 4 | return fastEmitInst_rr(X86::VORPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6211 | 4 | } |
6212 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
6213 | 0 | return fastEmitInst_rr(X86::VPORQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6214 | 0 | } |
6215 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX())2 ) { |
6216 | 2 | return fastEmitInst_rr(X86::VPORYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6217 | 2 | } |
6218 | 0 | return 0; |
6219 | 6 | } |
6220 | | |
6221 | 0 | unsigned fastEmit_ISD_OR_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6222 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
6223 | 0 | return 0; |
6224 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6225 | 0 | return fastEmitInst_rr(X86::VPORQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6226 | 0 | } |
6227 | 0 | return 0; |
6228 | 0 | } |
6229 | | |
6230 | 61 | unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6231 | 61 | switch (VT.SimpleTy) { |
6232 | 0 | case MVT::i8: return fastEmit_ISD_OR_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6233 | 2 | case MVT::i16: return fastEmit_ISD_OR_MVT_i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6234 | 26 | case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6235 | 19 | case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6236 | 0 | case MVT::v8i1: return fastEmit_ISD_OR_MVT_v8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6237 | 0 | case MVT::v16i1: return fastEmit_ISD_OR_MVT_v16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6238 | 0 | case MVT::v32i1: return fastEmit_ISD_OR_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6239 | 0 | case MVT::v64i1: return fastEmit_ISD_OR_MVT_v64i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6240 | 4 | case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6241 | 6 | case MVT::v4i64: return fastEmit_ISD_OR_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6242 | 0 | case MVT::v8i64: return fastEmit_ISD_OR_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6243 | 4 | default: return 0; |
6244 | 61 | } |
6245 | 61 | } |
6246 | | |
6247 | | // FastEmit functions for ISD::ROTL. |
6248 | | |
6249 | 0 | unsigned fastEmit_ISD_ROTL_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6250 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6251 | 0 | return 0; |
6252 | 0 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1); |
6253 | 0 | return fastEmitInst_r(X86::ROL8rCL, &X86::GR8RegClass, Op0, Op0IsKill); |
6254 | 0 | } |
6255 | | |
6256 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6257 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
6258 | 0 | return 0; |
6259 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
6260 | 0 | return fastEmitInst_rr(X86::VPROTBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6261 | 0 | } |
6262 | 0 | return 0; |
6263 | 0 | } |
6264 | | |
6265 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6266 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
6267 | 0 | return 0; |
6268 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
6269 | 0 | return fastEmitInst_rr(X86::VPROTWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6270 | 0 | } |
6271 | 0 | return 0; |
6272 | 0 | } |
6273 | | |
6274 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6275 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
6276 | 0 | return 0; |
6277 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6278 | 0 | return fastEmitInst_rr(X86::VPROLVDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6279 | 0 | } |
6280 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
6281 | 0 | return fastEmitInst_rr(X86::VPROTDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6282 | 0 | } |
6283 | 0 | return 0; |
6284 | 0 | } |
6285 | | |
6286 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6287 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
6288 | 0 | return 0; |
6289 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6290 | 0 | return fastEmitInst_rr(X86::VPROLVDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6291 | 0 | } |
6292 | 0 | return 0; |
6293 | 0 | } |
6294 | | |
6295 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6296 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
6297 | 0 | return 0; |
6298 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6299 | 0 | return fastEmitInst_rr(X86::VPROLVDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6300 | 0 | } |
6301 | 0 | return 0; |
6302 | 0 | } |
6303 | | |
6304 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6305 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
6306 | 0 | return 0; |
6307 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6308 | 0 | return fastEmitInst_rr(X86::VPROLVQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6309 | 0 | } |
6310 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
6311 | 0 | return fastEmitInst_rr(X86::VPROTQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6312 | 0 | } |
6313 | 0 | return 0; |
6314 | 0 | } |
6315 | | |
6316 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6317 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
6318 | 0 | return 0; |
6319 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6320 | 0 | return fastEmitInst_rr(X86::VPROLVQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6321 | 0 | } |
6322 | 0 | return 0; |
6323 | 0 | } |
6324 | | |
6325 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6326 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
6327 | 0 | return 0; |
6328 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6329 | 0 | return fastEmitInst_rr(X86::VPROLVQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6330 | 0 | } |
6331 | 0 | return 0; |
6332 | 0 | } |
6333 | | |
6334 | | unsigned fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6335 | | switch (VT.SimpleTy) { |
6336 | | case MVT::i8: return fastEmit_ISD_ROTL_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6337 | | case MVT::v16i8: return fastEmit_ISD_ROTL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6338 | | case MVT::v8i16: return fastEmit_ISD_ROTL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6339 | | case MVT::v4i32: return fastEmit_ISD_ROTL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6340 | | case MVT::v8i32: return fastEmit_ISD_ROTL_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6341 | | case MVT::v16i32: return fastEmit_ISD_ROTL_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6342 | | case MVT::v2i64: return fastEmit_ISD_ROTL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6343 | | case MVT::v4i64: return fastEmit_ISD_ROTL_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6344 | | case MVT::v8i64: return fastEmit_ISD_ROTL_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6345 | | default: return 0; |
6346 | | } |
6347 | | } |
6348 | | |
6349 | | // FastEmit functions for ISD::ROTR. |
6350 | | |
6351 | 0 | unsigned fastEmit_ISD_ROTR_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6352 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6353 | 0 | return 0; |
6354 | 0 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1); |
6355 | 0 | return fastEmitInst_r(X86::ROR8rCL, &X86::GR8RegClass, Op0, Op0IsKill); |
6356 | 0 | } |
6357 | | |
6358 | 0 | unsigned fastEmit_ISD_ROTR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6359 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
6360 | 0 | return 0; |
6361 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6362 | 0 | return fastEmitInst_rr(X86::VPRORVDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6363 | 0 | } |
6364 | 0 | return 0; |
6365 | 0 | } |
6366 | | |
6367 | 0 | unsigned fastEmit_ISD_ROTR_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6368 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
6369 | 0 | return 0; |
6370 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6371 | 0 | return fastEmitInst_rr(X86::VPRORVDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6372 | 0 | } |
6373 | 0 | return 0; |
6374 | 0 | } |
6375 | | |
6376 | 0 | unsigned fastEmit_ISD_ROTR_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6377 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
6378 | 0 | return 0; |
6379 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6380 | 0 | return fastEmitInst_rr(X86::VPRORVDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6381 | 0 | } |
6382 | 0 | return 0; |
6383 | 0 | } |
6384 | | |
6385 | 0 | unsigned fastEmit_ISD_ROTR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6386 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
6387 | 0 | return 0; |
6388 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6389 | 0 | return fastEmitInst_rr(X86::VPRORVQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6390 | 0 | } |
6391 | 0 | return 0; |
6392 | 0 | } |
6393 | | |
6394 | 0 | unsigned fastEmit_ISD_ROTR_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6395 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
6396 | 0 | return 0; |
6397 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6398 | 0 | return fastEmitInst_rr(X86::VPRORVQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6399 | 0 | } |
6400 | 0 | return 0; |
6401 | 0 | } |
6402 | | |
6403 | 0 | unsigned fastEmit_ISD_ROTR_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6404 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
6405 | 0 | return 0; |
6406 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6407 | 0 | return fastEmitInst_rr(X86::VPRORVQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6408 | 0 | } |
6409 | 0 | return 0; |
6410 | 0 | } |
6411 | | |
6412 | | unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6413 | | switch (VT.SimpleTy) { |
6414 | | case MVT::i8: return fastEmit_ISD_ROTR_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6415 | | case MVT::v4i32: return fastEmit_ISD_ROTR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6416 | | case MVT::v8i32: return fastEmit_ISD_ROTR_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6417 | | case MVT::v16i32: return fastEmit_ISD_ROTR_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6418 | | case MVT::v2i64: return fastEmit_ISD_ROTR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6419 | | case MVT::v4i64: return fastEmit_ISD_ROTR_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6420 | | case MVT::v8i64: return fastEmit_ISD_ROTR_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6421 | | default: return 0; |
6422 | | } |
6423 | | } |
6424 | | |
6425 | | // FastEmit functions for ISD::SHL. |
6426 | | |
6427 | 2 | unsigned fastEmit_ISD_SHL_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6428 | 2 | if (RetVT.SimpleTy != MVT::i8) |
6429 | 0 | return 0; |
6430 | 2 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1); |
6431 | 2 | return fastEmitInst_r(X86::SHL8rCL, &X86::GR8RegClass, Op0, Op0IsKill); |
6432 | 2 | } |
6433 | | |
6434 | 0 | unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6435 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
6436 | 0 | return 0; |
6437 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6438 | 0 | return fastEmitInst_rr(X86::VPSLLVWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6439 | 0 | } |
6440 | 0 | return 0; |
6441 | 0 | } |
6442 | | |
6443 | 0 | unsigned fastEmit_ISD_SHL_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6444 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
6445 | 0 | return 0; |
6446 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6447 | 0 | return fastEmitInst_rr(X86::VPSLLVWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6448 | 0 | } |
6449 | 0 | return 0; |
6450 | 0 | } |
6451 | | |
6452 | 0 | unsigned fastEmit_ISD_SHL_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6453 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
6454 | 0 | return 0; |
6455 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
6456 | 0 | return fastEmitInst_rr(X86::VPSLLVWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6457 | 0 | } |
6458 | 0 | return 0; |
6459 | 0 | } |
6460 | | |
6461 | 0 | unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6462 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
6463 | 0 | return 0; |
6464 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6465 | 0 | return fastEmitInst_rr(X86::VPSLLVDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6466 | 0 | } |
6467 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
6468 | 0 | return fastEmitInst_rr(X86::VPSLLVDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6469 | 0 | } |
6470 | 0 | return 0; |
6471 | 0 | } |
6472 | | |
6473 | 0 | unsigned fastEmit_ISD_SHL_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6474 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
6475 | 0 | return 0; |
6476 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6477 | 0 | return fastEmitInst_rr(X86::VPSLLVDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6478 | 0 | } |
6479 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
6480 | 0 | return fastEmitInst_rr(X86::VPSLLVDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6481 | 0 | } |
6482 | 0 | return 0; |
6483 | 0 | } |
6484 | | |
6485 | 0 | unsigned fastEmit_ISD_SHL_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6486 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
6487 | 0 | return 0; |
6488 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6489 | 0 | return fastEmitInst_rr(X86::VPSLLVDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6490 | 0 | } |
6491 | 0 | return 0; |
6492 | 0 | } |
6493 | | |
6494 | 0 | unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6495 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
6496 | 0 | return 0; |
6497 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6498 | 0 | return fastEmitInst_rr(X86::VPSLLVQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6499 | 0 | } |
6500 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
6501 | 0 | return fastEmitInst_rr(X86::VPSLLVQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6502 | 0 | } |
6503 | 0 | return 0; |
6504 | 0 | } |
6505 | | |
6506 | 0 | unsigned fastEmit_ISD_SHL_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6507 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
6508 | 0 | return 0; |
6509 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6510 | 0 | return fastEmitInst_rr(X86::VPSLLVQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6511 | 0 | } |
6512 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
6513 | 0 | return fastEmitInst_rr(X86::VPSLLVQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6514 | 0 | } |
6515 | 0 | return 0; |
6516 | 0 | } |
6517 | | |
6518 | 0 | unsigned fastEmit_ISD_SHL_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6519 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
6520 | 0 | return 0; |
6521 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6522 | 0 | return fastEmitInst_rr(X86::VPSLLVQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6523 | 0 | } |
6524 | 0 | return 0; |
6525 | 0 | } |
6526 | | |
6527 | 4 | unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6528 | 4 | switch (VT.SimpleTy) { |
6529 | 2 | case MVT::i8: return fastEmit_ISD_SHL_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6530 | 0 | case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6531 | 0 | case MVT::v16i16: return fastEmit_ISD_SHL_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6532 | 0 | case MVT::v32i16: return fastEmit_ISD_SHL_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6533 | 0 | case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6534 | 0 | case MVT::v8i32: return fastEmit_ISD_SHL_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6535 | 0 | case MVT::v16i32: return fastEmit_ISD_SHL_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6536 | 0 | case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6537 | 0 | case MVT::v4i64: return fastEmit_ISD_SHL_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6538 | 0 | case MVT::v8i64: return fastEmit_ISD_SHL_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6539 | 2 | default: return 0; |
6540 | 4 | } |
6541 | 4 | } |
6542 | | |
6543 | | // FastEmit functions for ISD::SMAX. |
6544 | | |
6545 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6546 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
6547 | 0 | return 0; |
6548 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6549 | 0 | return fastEmitInst_rr(X86::VPMAXSBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6550 | 0 | } |
6551 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
6552 | 0 | return fastEmitInst_rr(X86::PMAXSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6553 | 0 | } |
6554 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6555 | 0 | return fastEmitInst_rr(X86::VPMAXSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6556 | 0 | } |
6557 | 0 | return 0; |
6558 | 0 | } |
6559 | | |
6560 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6561 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
6562 | 0 | return 0; |
6563 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6564 | 0 | return fastEmitInst_rr(X86::VPMAXSBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6565 | 0 | } |
6566 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6567 | 0 | return fastEmitInst_rr(X86::VPMAXSBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6568 | 0 | } |
6569 | 0 | return 0; |
6570 | 0 | } |
6571 | | |
6572 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6573 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
6574 | 0 | return 0; |
6575 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
6576 | 0 | return fastEmitInst_rr(X86::VPMAXSBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6577 | 0 | } |
6578 | 0 | return 0; |
6579 | 0 | } |
6580 | | |
6581 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6582 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
6583 | 0 | return 0; |
6584 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6585 | 0 | return fastEmitInst_rr(X86::VPMAXSWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6586 | 0 | } |
6587 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
6588 | 0 | return fastEmitInst_rr(X86::PMAXSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6589 | 0 | } |
6590 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6591 | 0 | return fastEmitInst_rr(X86::VPMAXSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6592 | 0 | } |
6593 | 0 | return 0; |
6594 | 0 | } |
6595 | | |
6596 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6597 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
6598 | 0 | return 0; |
6599 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6600 | 0 | return fastEmitInst_rr(X86::VPMAXSWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6601 | 0 | } |
6602 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6603 | 0 | return fastEmitInst_rr(X86::VPMAXSWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6604 | 0 | } |
6605 | 0 | return 0; |
6606 | 0 | } |
6607 | | |
6608 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6609 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
6610 | 0 | return 0; |
6611 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
6612 | 0 | return fastEmitInst_rr(X86::VPMAXSWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6613 | 0 | } |
6614 | 0 | return 0; |
6615 | 0 | } |
6616 | | |
6617 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6618 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
6619 | 0 | return 0; |
6620 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6621 | 0 | return fastEmitInst_rr(X86::VPMAXSDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6622 | 0 | } |
6623 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
6624 | 0 | return fastEmitInst_rr(X86::PMAXSDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6625 | 0 | } |
6626 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
6627 | 0 | return fastEmitInst_rr(X86::VPMAXSDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6628 | 0 | } |
6629 | 0 | return 0; |
6630 | 0 | } |
6631 | | |
6632 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6633 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
6634 | 0 | return 0; |
6635 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6636 | 0 | return fastEmitInst_rr(X86::VPMAXSDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6637 | 0 | } |
6638 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
6639 | 0 | return fastEmitInst_rr(X86::VPMAXSDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6640 | 0 | } |
6641 | 0 | return 0; |
6642 | 0 | } |
6643 | | |
6644 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6645 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
6646 | 0 | return 0; |
6647 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6648 | 0 | return fastEmitInst_rr(X86::VPMAXSDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6649 | 0 | } |
6650 | 0 | return 0; |
6651 | 0 | } |
6652 | | |
6653 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6654 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
6655 | 0 | return 0; |
6656 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6657 | 0 | return fastEmitInst_rr(X86::VPMAXSQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6658 | 0 | } |
6659 | 0 | return 0; |
6660 | 0 | } |
6661 | | |
6662 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6663 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
6664 | 0 | return 0; |
6665 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6666 | 0 | return fastEmitInst_rr(X86::VPMAXSQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6667 | 0 | } |
6668 | 0 | return 0; |
6669 | 0 | } |
6670 | | |
6671 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6672 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
6673 | 0 | return 0; |
6674 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6675 | 0 | return fastEmitInst_rr(X86::VPMAXSQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6676 | 0 | } |
6677 | 0 | return 0; |
6678 | 0 | } |
6679 | | |
6680 | | unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6681 | | switch (VT.SimpleTy) { |
6682 | | case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6683 | | case MVT::v32i8: return fastEmit_ISD_SMAX_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6684 | | case MVT::v64i8: return fastEmit_ISD_SMAX_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6685 | | case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6686 | | case MVT::v16i16: return fastEmit_ISD_SMAX_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6687 | | case MVT::v32i16: return fastEmit_ISD_SMAX_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6688 | | case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6689 | | case MVT::v8i32: return fastEmit_ISD_SMAX_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6690 | | case MVT::v16i32: return fastEmit_ISD_SMAX_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6691 | | case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6692 | | case MVT::v4i64: return fastEmit_ISD_SMAX_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6693 | | case MVT::v8i64: return fastEmit_ISD_SMAX_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6694 | | default: return 0; |
6695 | | } |
6696 | | } |
6697 | | |
6698 | | // FastEmit functions for ISD::SMIN. |
6699 | | |
6700 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6701 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
6702 | 0 | return 0; |
6703 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6704 | 0 | return fastEmitInst_rr(X86::VPMINSBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6705 | 0 | } |
6706 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
6707 | 0 | return fastEmitInst_rr(X86::PMINSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6708 | 0 | } |
6709 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6710 | 0 | return fastEmitInst_rr(X86::VPMINSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6711 | 0 | } |
6712 | 0 | return 0; |
6713 | 0 | } |
6714 | | |
6715 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6716 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
6717 | 0 | return 0; |
6718 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6719 | 0 | return fastEmitInst_rr(X86::VPMINSBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6720 | 0 | } |
6721 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6722 | 0 | return fastEmitInst_rr(X86::VPMINSBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6723 | 0 | } |
6724 | 0 | return 0; |
6725 | 0 | } |
6726 | | |
6727 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6728 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
6729 | 0 | return 0; |
6730 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
6731 | 0 | return fastEmitInst_rr(X86::VPMINSBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6732 | 0 | } |
6733 | 0 | return 0; |
6734 | 0 | } |
6735 | | |
6736 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6737 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
6738 | 0 | return 0; |
6739 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6740 | 0 | return fastEmitInst_rr(X86::VPMINSWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6741 | 0 | } |
6742 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
6743 | 0 | return fastEmitInst_rr(X86::PMINSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6744 | 0 | } |
6745 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6746 | 0 | return fastEmitInst_rr(X86::VPMINSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6747 | 0 | } |
6748 | 0 | return 0; |
6749 | 0 | } |
6750 | | |
6751 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6752 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
6753 | 0 | return 0; |
6754 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6755 | 0 | return fastEmitInst_rr(X86::VPMINSWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6756 | 0 | } |
6757 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
6758 | 0 | return fastEmitInst_rr(X86::VPMINSWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6759 | 0 | } |
6760 | 0 | return 0; |
6761 | 0 | } |
6762 | | |
6763 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6764 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
6765 | 0 | return 0; |
6766 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
6767 | 0 | return fastEmitInst_rr(X86::VPMINSWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6768 | 0 | } |
6769 | 0 | return 0; |
6770 | 0 | } |
6771 | | |
6772 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6773 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
6774 | 0 | return 0; |
6775 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6776 | 0 | return fastEmitInst_rr(X86::VPMINSDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6777 | 0 | } |
6778 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
6779 | 0 | return fastEmitInst_rr(X86::PMINSDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6780 | 0 | } |
6781 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
6782 | 0 | return fastEmitInst_rr(X86::VPMINSDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6783 | 0 | } |
6784 | 0 | return 0; |
6785 | 0 | } |
6786 | | |
6787 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6788 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
6789 | 0 | return 0; |
6790 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6791 | 0 | return fastEmitInst_rr(X86::VPMINSDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6792 | 0 | } |
6793 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
6794 | 0 | return fastEmitInst_rr(X86::VPMINSDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6795 | 0 | } |
6796 | 0 | return 0; |
6797 | 0 | } |
6798 | | |
6799 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6800 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
6801 | 0 | return 0; |
6802 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6803 | 0 | return fastEmitInst_rr(X86::VPMINSDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6804 | 0 | } |
6805 | 0 | return 0; |
6806 | 0 | } |
6807 | | |
6808 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6809 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
6810 | 0 | return 0; |
6811 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6812 | 0 | return fastEmitInst_rr(X86::VPMINSQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6813 | 0 | } |
6814 | 0 | return 0; |
6815 | 0 | } |
6816 | | |
6817 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6818 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
6819 | 0 | return 0; |
6820 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6821 | 0 | return fastEmitInst_rr(X86::VPMINSQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6822 | 0 | } |
6823 | 0 | return 0; |
6824 | 0 | } |
6825 | | |
6826 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6827 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
6828 | 0 | return 0; |
6829 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6830 | 0 | return fastEmitInst_rr(X86::VPMINSQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6831 | 0 | } |
6832 | 0 | return 0; |
6833 | 0 | } |
6834 | | |
6835 | | unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6836 | | switch (VT.SimpleTy) { |
6837 | | case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6838 | | case MVT::v32i8: return fastEmit_ISD_SMIN_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6839 | | case MVT::v64i8: return fastEmit_ISD_SMIN_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6840 | | case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6841 | | case MVT::v16i16: return fastEmit_ISD_SMIN_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6842 | | case MVT::v32i16: return fastEmit_ISD_SMIN_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6843 | | case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6844 | | case MVT::v8i32: return fastEmit_ISD_SMIN_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6845 | | case MVT::v16i32: return fastEmit_ISD_SMIN_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6846 | | case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6847 | | case MVT::v4i64: return fastEmit_ISD_SMIN_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6848 | | case MVT::v8i64: return fastEmit_ISD_SMIN_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6849 | | default: return 0; |
6850 | | } |
6851 | | } |
6852 | | |
6853 | | // FastEmit functions for ISD::SRA. |
6854 | | |
6855 | 0 | unsigned fastEmit_ISD_SRA_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6856 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6857 | 0 | return 0; |
6858 | 0 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1); |
6859 | 0 | return fastEmitInst_r(X86::SAR8rCL, &X86::GR8RegClass, Op0, Op0IsKill); |
6860 | 0 | } |
6861 | | |
6862 | 0 | unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6863 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
6864 | 0 | return 0; |
6865 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6866 | 0 | return fastEmitInst_rr(X86::VPSRAVWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6867 | 0 | } |
6868 | 0 | return 0; |
6869 | 0 | } |
6870 | | |
6871 | 0 | unsigned fastEmit_ISD_SRA_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6872 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
6873 | 0 | return 0; |
6874 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6875 | 0 | return fastEmitInst_rr(X86::VPSRAVWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6876 | 0 | } |
6877 | 0 | return 0; |
6878 | 0 | } |
6879 | | |
6880 | 0 | unsigned fastEmit_ISD_SRA_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6881 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
6882 | 0 | return 0; |
6883 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
6884 | 0 | return fastEmitInst_rr(X86::VPSRAVWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6885 | 0 | } |
6886 | 0 | return 0; |
6887 | 0 | } |
6888 | | |
6889 | 0 | unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6890 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
6891 | 0 | return 0; |
6892 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6893 | 0 | return fastEmitInst_rr(X86::VPSRAVDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6894 | 0 | } |
6895 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
6896 | 0 | return fastEmitInst_rr(X86::VPSRAVDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6897 | 0 | } |
6898 | 0 | return 0; |
6899 | 0 | } |
6900 | | |
6901 | 0 | unsigned fastEmit_ISD_SRA_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6902 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
6903 | 0 | return 0; |
6904 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6905 | 0 | return fastEmitInst_rr(X86::VPSRAVDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6906 | 0 | } |
6907 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
6908 | 0 | return fastEmitInst_rr(X86::VPSRAVDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6909 | 0 | } |
6910 | 0 | return 0; |
6911 | 0 | } |
6912 | | |
6913 | 0 | unsigned fastEmit_ISD_SRA_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6914 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
6915 | 0 | return 0; |
6916 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6917 | 0 | return fastEmitInst_rr(X86::VPSRAVDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6918 | 0 | } |
6919 | 0 | return 0; |
6920 | 0 | } |
6921 | | |
6922 | 0 | unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6923 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
6924 | 0 | return 0; |
6925 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6926 | 0 | return fastEmitInst_rr(X86::VPSRAVQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6927 | 0 | } |
6928 | 0 | return 0; |
6929 | 0 | } |
6930 | | |
6931 | 0 | unsigned fastEmit_ISD_SRA_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6932 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
6933 | 0 | return 0; |
6934 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
6935 | 0 | return fastEmitInst_rr(X86::VPSRAVQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6936 | 0 | } |
6937 | 0 | return 0; |
6938 | 0 | } |
6939 | | |
6940 | 0 | unsigned fastEmit_ISD_SRA_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6941 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
6942 | 0 | return 0; |
6943 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
6944 | 0 | return fastEmitInst_rr(X86::VPSRAVQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6945 | 0 | } |
6946 | 0 | return 0; |
6947 | 0 | } |
6948 | | |
6949 | 1 | unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6950 | 1 | switch (VT.SimpleTy) { |
6951 | 0 | case MVT::i8: return fastEmit_ISD_SRA_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6952 | 0 | case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6953 | 0 | case MVT::v16i16: return fastEmit_ISD_SRA_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6954 | 0 | case MVT::v32i16: return fastEmit_ISD_SRA_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6955 | 0 | case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6956 | 0 | case MVT::v8i32: return fastEmit_ISD_SRA_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6957 | 0 | case MVT::v16i32: return fastEmit_ISD_SRA_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6958 | 0 | case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6959 | 0 | case MVT::v4i64: return fastEmit_ISD_SRA_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6960 | 0 | case MVT::v8i64: return fastEmit_ISD_SRA_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
6961 | 1 | default: return 0; |
6962 | 1 | } |
6963 | 1 | } |
6964 | | |
6965 | | // FastEmit functions for ISD::SRL. |
6966 | | |
6967 | 0 | unsigned fastEmit_ISD_SRL_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6968 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6969 | 0 | return 0; |
6970 | 0 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1); |
6971 | 0 | return fastEmitInst_r(X86::SHR8rCL, &X86::GR8RegClass, Op0, Op0IsKill); |
6972 | 0 | } |
6973 | | |
6974 | 0 | unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6975 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
6976 | 0 | return 0; |
6977 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6978 | 0 | return fastEmitInst_rr(X86::VPSRLVWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6979 | 0 | } |
6980 | 0 | return 0; |
6981 | 0 | } |
6982 | | |
6983 | 0 | unsigned fastEmit_ISD_SRL_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6984 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
6985 | 0 | return 0; |
6986 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
6987 | 0 | return fastEmitInst_rr(X86::VPSRLVWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6988 | 0 | } |
6989 | 0 | return 0; |
6990 | 0 | } |
6991 | | |
6992 | 0 | unsigned fastEmit_ISD_SRL_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
6993 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
6994 | 0 | return 0; |
6995 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
6996 | 0 | return fastEmitInst_rr(X86::VPSRLVWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
6997 | 0 | } |
6998 | 0 | return 0; |
6999 | 0 | } |
7000 | | |
7001 | 0 | unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7002 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
7003 | 0 | return 0; |
7004 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7005 | 0 | return fastEmitInst_rr(X86::VPSRLVDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7006 | 0 | } |
7007 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
7008 | 0 | return fastEmitInst_rr(X86::VPSRLVDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7009 | 0 | } |
7010 | 0 | return 0; |
7011 | 0 | } |
7012 | | |
7013 | 0 | unsigned fastEmit_ISD_SRL_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7014 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
7015 | 0 | return 0; |
7016 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7017 | 0 | return fastEmitInst_rr(X86::VPSRLVDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7018 | 0 | } |
7019 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
7020 | 0 | return fastEmitInst_rr(X86::VPSRLVDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7021 | 0 | } |
7022 | 0 | return 0; |
7023 | 0 | } |
7024 | | |
7025 | 0 | unsigned fastEmit_ISD_SRL_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7026 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
7027 | 0 | return 0; |
7028 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
7029 | 0 | return fastEmitInst_rr(X86::VPSRLVDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7030 | 0 | } |
7031 | 0 | return 0; |
7032 | 0 | } |
7033 | | |
7034 | 0 | unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7035 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7036 | 0 | return 0; |
7037 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7038 | 0 | return fastEmitInst_rr(X86::VPSRLVQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7039 | 0 | } |
7040 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
7041 | 0 | return fastEmitInst_rr(X86::VPSRLVQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7042 | 0 | } |
7043 | 0 | return 0; |
7044 | 0 | } |
7045 | | |
7046 | 0 | unsigned fastEmit_ISD_SRL_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7047 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
7048 | 0 | return 0; |
7049 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7050 | 0 | return fastEmitInst_rr(X86::VPSRLVQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7051 | 0 | } |
7052 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
7053 | 0 | return fastEmitInst_rr(X86::VPSRLVQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7054 | 0 | } |
7055 | 0 | return 0; |
7056 | 0 | } |
7057 | | |
7058 | 0 | unsigned fastEmit_ISD_SRL_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7059 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
7060 | 0 | return 0; |
7061 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
7062 | 0 | return fastEmitInst_rr(X86::VPSRLVQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7063 | 0 | } |
7064 | 0 | return 0; |
7065 | 0 | } |
7066 | | |
7067 | | unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7068 | | switch (VT.SimpleTy) { |
7069 | | case MVT::i8: return fastEmit_ISD_SRL_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7070 | | case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7071 | | case MVT::v16i16: return fastEmit_ISD_SRL_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7072 | | case MVT::v32i16: return fastEmit_ISD_SRL_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7073 | | case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7074 | | case MVT::v8i32: return fastEmit_ISD_SRL_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7075 | | case MVT::v16i32: return fastEmit_ISD_SRL_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7076 | | case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7077 | | case MVT::v4i64: return fastEmit_ISD_SRL_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7078 | | case MVT::v8i64: return fastEmit_ISD_SRL_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7079 | | default: return 0; |
7080 | | } |
7081 | | } |
7082 | | |
7083 | | // FastEmit functions for ISD::SUB. |
7084 | | |
7085 | 0 | unsigned fastEmit_ISD_SUB_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7086 | 0 | if (RetVT.SimpleTy != MVT::i8) |
7087 | 0 | return 0; |
7088 | 0 | return fastEmitInst_rr(X86::SUB8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7089 | 0 | } |
7090 | | |
7091 | 0 | unsigned fastEmit_ISD_SUB_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7092 | 0 | if (RetVT.SimpleTy != MVT::i16) |
7093 | 0 | return 0; |
7094 | 0 | return fastEmitInst_rr(X86::SUB16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7095 | 0 | } |
7096 | | |
7097 | 13 | unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7098 | 13 | if (RetVT.SimpleTy != MVT::i32) |
7099 | 0 | return 0; |
7100 | 13 | return fastEmitInst_rr(X86::SUB32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7101 | 13 | } |
7102 | | |
7103 | 14 | unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7104 | 14 | if (RetVT.SimpleTy != MVT::i64) |
7105 | 0 | return 0; |
7106 | 14 | return fastEmitInst_rr(X86::SUB64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7107 | 14 | } |
7108 | | |
7109 | 2 | unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7110 | 2 | if (RetVT.SimpleTy != MVT::v16i8) |
7111 | 0 | return 0; |
7112 | 2 | if (2 (Subtarget->hasBWI()) && 2 (Subtarget->hasVLX())0 ) { |
7113 | 0 | return fastEmitInst_rr(X86::VPSUBBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7114 | 0 | } |
7115 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
7116 | 2 | return fastEmitInst_rr(X86::PSUBBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7117 | 2 | } |
7118 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7119 | 0 | return fastEmitInst_rr(X86::VPSUBBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7120 | 0 | } |
7121 | 0 | return 0; |
7122 | 2 | } |
7123 | | |
7124 | 2 | unsigned fastEmit_ISD_SUB_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7125 | 2 | if (RetVT.SimpleTy != MVT::v32i8) |
7126 | 0 | return 0; |
7127 | 2 | if (2 (Subtarget->hasBWI()) && 2 (Subtarget->hasVLX())0 ) { |
7128 | 0 | return fastEmitInst_rr(X86::VPSUBBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7129 | 0 | } |
7130 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX() || 2 !Subtarget->hasBWI()0 )) { |
7131 | 2 | return fastEmitInst_rr(X86::VPSUBBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7132 | 2 | } |
7133 | 0 | return 0; |
7134 | 2 | } |
7135 | | |
7136 | 0 | unsigned fastEmit_ISD_SUB_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7137 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
7138 | 0 | return 0; |
7139 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7140 | 0 | return fastEmitInst_rr(X86::VPSUBBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7141 | 0 | } |
7142 | 0 | return 0; |
7143 | 0 | } |
7144 | | |
7145 | 2 | unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7146 | 2 | if (RetVT.SimpleTy != MVT::v8i16) |
7147 | 0 | return 0; |
7148 | 2 | if (2 (Subtarget->hasBWI()) && 2 (Subtarget->hasVLX())0 ) { |
7149 | 0 | return fastEmitInst_rr(X86::VPSUBWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7150 | 0 | } |
7151 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
7152 | 2 | return fastEmitInst_rr(X86::PSUBWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7153 | 2 | } |
7154 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7155 | 0 | return fastEmitInst_rr(X86::VPSUBWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7156 | 0 | } |
7157 | 0 | return 0; |
7158 | 2 | } |
7159 | | |
7160 | 2 | unsigned fastEmit_ISD_SUB_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7161 | 2 | if (RetVT.SimpleTy != MVT::v16i16) |
7162 | 0 | return 0; |
7163 | 2 | if (2 (Subtarget->hasBWI()) && 2 (Subtarget->hasVLX())0 ) { |
7164 | 0 | return fastEmitInst_rr(X86::VPSUBWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7165 | 0 | } |
7166 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX() || 2 !Subtarget->hasBWI()0 )) { |
7167 | 2 | return fastEmitInst_rr(X86::VPSUBWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7168 | 2 | } |
7169 | 0 | return 0; |
7170 | 2 | } |
7171 | | |
7172 | 0 | unsigned fastEmit_ISD_SUB_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7173 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
7174 | 0 | return 0; |
7175 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7176 | 0 | return fastEmitInst_rr(X86::VPSUBWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7177 | 0 | } |
7178 | 0 | return 0; |
7179 | 0 | } |
7180 | | |
7181 | 2 | unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7182 | 2 | if (RetVT.SimpleTy != MVT::v4i32) |
7183 | 0 | return 0; |
7184 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
7185 | 0 | return fastEmitInst_rr(X86::VPSUBDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7186 | 0 | } |
7187 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
7188 | 2 | return fastEmitInst_rr(X86::PSUBDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7189 | 2 | } |
7190 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
7191 | 0 | return fastEmitInst_rr(X86::VPSUBDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7192 | 0 | } |
7193 | 0 | return 0; |
7194 | 2 | } |
7195 | | |
7196 | 2 | unsigned fastEmit_ISD_SUB_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7197 | 2 | if (RetVT.SimpleTy != MVT::v8i32) |
7198 | 0 | return 0; |
7199 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
7200 | 0 | return fastEmitInst_rr(X86::VPSUBDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7201 | 0 | } |
7202 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX())2 ) { |
7203 | 2 | return fastEmitInst_rr(X86::VPSUBDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7204 | 2 | } |
7205 | 0 | return 0; |
7206 | 2 | } |
7207 | | |
7208 | 0 | unsigned fastEmit_ISD_SUB_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7209 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
7210 | 0 | return 0; |
7211 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
7212 | 0 | return fastEmitInst_rr(X86::VPSUBDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7213 | 0 | } |
7214 | 0 | return 0; |
7215 | 0 | } |
7216 | | |
7217 | 2 | unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7218 | 2 | if (RetVT.SimpleTy != MVT::v2i64) |
7219 | 0 | return 0; |
7220 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
7221 | 0 | return fastEmitInst_rr(X86::VPSUBQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7222 | 0 | } |
7223 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
7224 | 2 | return fastEmitInst_rr(X86::PSUBQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7225 | 2 | } |
7226 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
7227 | 0 | return fastEmitInst_rr(X86::VPSUBQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7228 | 0 | } |
7229 | 0 | return 0; |
7230 | 2 | } |
7231 | | |
7232 | 2 | unsigned fastEmit_ISD_SUB_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7233 | 2 | if (RetVT.SimpleTy != MVT::v4i64) |
7234 | 0 | return 0; |
7235 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
7236 | 0 | return fastEmitInst_rr(X86::VPSUBQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7237 | 0 | } |
7238 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX())2 ) { |
7239 | 2 | return fastEmitInst_rr(X86::VPSUBQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7240 | 2 | } |
7241 | 0 | return 0; |
7242 | 2 | } |
7243 | | |
7244 | 0 | unsigned fastEmit_ISD_SUB_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7245 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
7246 | 0 | return 0; |
7247 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
7248 | 0 | return fastEmitInst_rr(X86::VPSUBQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7249 | 0 | } |
7250 | 0 | return 0; |
7251 | 0 | } |
7252 | | |
7253 | 43 | unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7254 | 43 | switch (VT.SimpleTy) { |
7255 | 0 | case MVT::i8: return fastEmit_ISD_SUB_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7256 | 0 | case MVT::i16: return fastEmit_ISD_SUB_MVT_i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7257 | 13 | case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7258 | 14 | case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7259 | 2 | case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7260 | 2 | case MVT::v32i8: return fastEmit_ISD_SUB_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7261 | 0 | case MVT::v64i8: return fastEmit_ISD_SUB_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7262 | 2 | case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7263 | 2 | case MVT::v16i16: return fastEmit_ISD_SUB_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7264 | 0 | case MVT::v32i16: return fastEmit_ISD_SUB_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7265 | 2 | case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7266 | 2 | case MVT::v8i32: return fastEmit_ISD_SUB_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7267 | 0 | case MVT::v16i32: return fastEmit_ISD_SUB_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7268 | 2 | case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7269 | 2 | case MVT::v4i64: return fastEmit_ISD_SUB_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7270 | 0 | case MVT::v8i64: return fastEmit_ISD_SUB_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7271 | 0 | default: return 0; |
7272 | 43 | } |
7273 | 43 | } |
7274 | | |
7275 | | // FastEmit functions for ISD::UMAX. |
7276 | | |
7277 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7278 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
7279 | 0 | return 0; |
7280 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7281 | 0 | return fastEmitInst_rr(X86::VPMAXUBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7282 | 0 | } |
7283 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
7284 | 0 | return fastEmitInst_rr(X86::PMAXUBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7285 | 0 | } |
7286 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7287 | 0 | return fastEmitInst_rr(X86::VPMAXUBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7288 | 0 | } |
7289 | 0 | return 0; |
7290 | 0 | } |
7291 | | |
7292 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7293 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
7294 | 0 | return 0; |
7295 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7296 | 0 | return fastEmitInst_rr(X86::VPMAXUBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7297 | 0 | } |
7298 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7299 | 0 | return fastEmitInst_rr(X86::VPMAXUBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7300 | 0 | } |
7301 | 0 | return 0; |
7302 | 0 | } |
7303 | | |
7304 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7305 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
7306 | 0 | return 0; |
7307 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7308 | 0 | return fastEmitInst_rr(X86::VPMAXUBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7309 | 0 | } |
7310 | 0 | return 0; |
7311 | 0 | } |
7312 | | |
7313 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7314 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7315 | 0 | return 0; |
7316 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7317 | 0 | return fastEmitInst_rr(X86::VPMAXUWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7318 | 0 | } |
7319 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
7320 | 0 | return fastEmitInst_rr(X86::PMAXUWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7321 | 0 | } |
7322 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7323 | 0 | return fastEmitInst_rr(X86::VPMAXUWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7324 | 0 | } |
7325 | 0 | return 0; |
7326 | 0 | } |
7327 | | |
7328 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7329 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
7330 | 0 | return 0; |
7331 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7332 | 0 | return fastEmitInst_rr(X86::VPMAXUWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7333 | 0 | } |
7334 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7335 | 0 | return fastEmitInst_rr(X86::VPMAXUWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7336 | 0 | } |
7337 | 0 | return 0; |
7338 | 0 | } |
7339 | | |
7340 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7341 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
7342 | 0 | return 0; |
7343 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7344 | 0 | return fastEmitInst_rr(X86::VPMAXUWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7345 | 0 | } |
7346 | 0 | return 0; |
7347 | 0 | } |
7348 | | |
7349 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7350 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
7351 | 0 | return 0; |
7352 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7353 | 0 | return fastEmitInst_rr(X86::VPMAXUDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7354 | 0 | } |
7355 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
7356 | 0 | return fastEmitInst_rr(X86::PMAXUDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7357 | 0 | } |
7358 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
7359 | 0 | return fastEmitInst_rr(X86::VPMAXUDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7360 | 0 | } |
7361 | 0 | return 0; |
7362 | 0 | } |
7363 | | |
7364 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7365 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
7366 | 0 | return 0; |
7367 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7368 | 0 | return fastEmitInst_rr(X86::VPMAXUDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7369 | 0 | } |
7370 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
7371 | 0 | return fastEmitInst_rr(X86::VPMAXUDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7372 | 0 | } |
7373 | 0 | return 0; |
7374 | 0 | } |
7375 | | |
7376 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7377 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
7378 | 0 | return 0; |
7379 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
7380 | 0 | return fastEmitInst_rr(X86::VPMAXUDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7381 | 0 | } |
7382 | 0 | return 0; |
7383 | 0 | } |
7384 | | |
7385 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7386 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7387 | 0 | return 0; |
7388 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7389 | 0 | return fastEmitInst_rr(X86::VPMAXUQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7390 | 0 | } |
7391 | 0 | return 0; |
7392 | 0 | } |
7393 | | |
7394 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7395 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
7396 | 0 | return 0; |
7397 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7398 | 0 | return fastEmitInst_rr(X86::VPMAXUQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7399 | 0 | } |
7400 | 0 | return 0; |
7401 | 0 | } |
7402 | | |
7403 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7404 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
7405 | 0 | return 0; |
7406 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
7407 | 0 | return fastEmitInst_rr(X86::VPMAXUQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7408 | 0 | } |
7409 | 0 | return 0; |
7410 | 0 | } |
7411 | | |
7412 | | unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7413 | | switch (VT.SimpleTy) { |
7414 | | case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7415 | | case MVT::v32i8: return fastEmit_ISD_UMAX_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7416 | | case MVT::v64i8: return fastEmit_ISD_UMAX_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7417 | | case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7418 | | case MVT::v16i16: return fastEmit_ISD_UMAX_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7419 | | case MVT::v32i16: return fastEmit_ISD_UMAX_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7420 | | case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7421 | | case MVT::v8i32: return fastEmit_ISD_UMAX_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7422 | | case MVT::v16i32: return fastEmit_ISD_UMAX_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7423 | | case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7424 | | case MVT::v4i64: return fastEmit_ISD_UMAX_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7425 | | case MVT::v8i64: return fastEmit_ISD_UMAX_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7426 | | default: return 0; |
7427 | | } |
7428 | | } |
7429 | | |
7430 | | // FastEmit functions for ISD::UMIN. |
7431 | | |
7432 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7433 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
7434 | 0 | return 0; |
7435 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7436 | 0 | return fastEmitInst_rr(X86::VPMINUBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7437 | 0 | } |
7438 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
7439 | 0 | return fastEmitInst_rr(X86::PMINUBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7440 | 0 | } |
7441 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7442 | 0 | return fastEmitInst_rr(X86::VPMINUBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7443 | 0 | } |
7444 | 0 | return 0; |
7445 | 0 | } |
7446 | | |
7447 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7448 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
7449 | 0 | return 0; |
7450 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7451 | 0 | return fastEmitInst_rr(X86::VPMINUBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7452 | 0 | } |
7453 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7454 | 0 | return fastEmitInst_rr(X86::VPMINUBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7455 | 0 | } |
7456 | 0 | return 0; |
7457 | 0 | } |
7458 | | |
7459 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7460 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
7461 | 0 | return 0; |
7462 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7463 | 0 | return fastEmitInst_rr(X86::VPMINUBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7464 | 0 | } |
7465 | 0 | return 0; |
7466 | 0 | } |
7467 | | |
7468 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7469 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7470 | 0 | return 0; |
7471 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7472 | 0 | return fastEmitInst_rr(X86::VPMINUWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7473 | 0 | } |
7474 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
7475 | 0 | return fastEmitInst_rr(X86::PMINUWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7476 | 0 | } |
7477 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7478 | 0 | return fastEmitInst_rr(X86::VPMINUWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7479 | 0 | } |
7480 | 0 | return 0; |
7481 | 0 | } |
7482 | | |
7483 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7484 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
7485 | 0 | return 0; |
7486 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7487 | 0 | return fastEmitInst_rr(X86::VPMINUWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7488 | 0 | } |
7489 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7490 | 0 | return fastEmitInst_rr(X86::VPMINUWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7491 | 0 | } |
7492 | 0 | return 0; |
7493 | 0 | } |
7494 | | |
7495 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7496 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
7497 | 0 | return 0; |
7498 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7499 | 0 | return fastEmitInst_rr(X86::VPMINUWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7500 | 0 | } |
7501 | 0 | return 0; |
7502 | 0 | } |
7503 | | |
7504 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7505 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
7506 | 0 | return 0; |
7507 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7508 | 0 | return fastEmitInst_rr(X86::VPMINUDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7509 | 0 | } |
7510 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
7511 | 0 | return fastEmitInst_rr(X86::PMINUDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7512 | 0 | } |
7513 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
7514 | 0 | return fastEmitInst_rr(X86::VPMINUDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7515 | 0 | } |
7516 | 0 | return 0; |
7517 | 0 | } |
7518 | | |
7519 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7520 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
7521 | 0 | return 0; |
7522 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7523 | 0 | return fastEmitInst_rr(X86::VPMINUDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7524 | 0 | } |
7525 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
7526 | 0 | return fastEmitInst_rr(X86::VPMINUDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7527 | 0 | } |
7528 | 0 | return 0; |
7529 | 0 | } |
7530 | | |
7531 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7532 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
7533 | 0 | return 0; |
7534 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
7535 | 0 | return fastEmitInst_rr(X86::VPMINUDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7536 | 0 | } |
7537 | 0 | return 0; |
7538 | 0 | } |
7539 | | |
7540 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7541 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7542 | 0 | return 0; |
7543 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7544 | 0 | return fastEmitInst_rr(X86::VPMINUQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7545 | 0 | } |
7546 | 0 | return 0; |
7547 | 0 | } |
7548 | | |
7549 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7550 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
7551 | 0 | return 0; |
7552 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7553 | 0 | return fastEmitInst_rr(X86::VPMINUQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7554 | 0 | } |
7555 | 0 | return 0; |
7556 | 0 | } |
7557 | | |
7558 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7559 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
7560 | 0 | return 0; |
7561 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
7562 | 0 | return fastEmitInst_rr(X86::VPMINUQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7563 | 0 | } |
7564 | 0 | return 0; |
7565 | 0 | } |
7566 | | |
7567 | | unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7568 | | switch (VT.SimpleTy) { |
7569 | | case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7570 | | case MVT::v32i8: return fastEmit_ISD_UMIN_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7571 | | case MVT::v64i8: return fastEmit_ISD_UMIN_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7572 | | case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7573 | | case MVT::v16i16: return fastEmit_ISD_UMIN_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7574 | | case MVT::v32i16: return fastEmit_ISD_UMIN_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7575 | | case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7576 | | case MVT::v8i32: return fastEmit_ISD_UMIN_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7577 | | case MVT::v16i32: return fastEmit_ISD_UMIN_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7578 | | case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7579 | | case MVT::v4i64: return fastEmit_ISD_UMIN_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7580 | | case MVT::v8i64: return fastEmit_ISD_UMIN_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7581 | | default: return 0; |
7582 | | } |
7583 | | } |
7584 | | |
7585 | | // FastEmit functions for ISD::XOR. |
7586 | | |
7587 | 0 | unsigned fastEmit_ISD_XOR_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7588 | 0 | if (RetVT.SimpleTy != MVT::i8) |
7589 | 0 | return 0; |
7590 | 0 | return fastEmitInst_rr(X86::XOR8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7591 | 0 | } |
7592 | | |
7593 | 0 | unsigned fastEmit_ISD_XOR_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7594 | 0 | if (RetVT.SimpleTy != MVT::i16) |
7595 | 0 | return 0; |
7596 | 0 | return fastEmitInst_rr(X86::XOR16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7597 | 0 | } |
7598 | | |
7599 | 14 | unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7600 | 14 | if (RetVT.SimpleTy != MVT::i32) |
7601 | 0 | return 0; |
7602 | 14 | return fastEmitInst_rr(X86::XOR32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7603 | 14 | } |
7604 | | |
7605 | 8 | unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7606 | 8 | if (RetVT.SimpleTy != MVT::i64) |
7607 | 0 | return 0; |
7608 | 8 | return fastEmitInst_rr(X86::XOR64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7609 | 8 | } |
7610 | | |
7611 | 0 | unsigned fastEmit_ISD_XOR_MVT_v8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7612 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
7613 | 0 | return 0; |
7614 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
7615 | 0 | return fastEmitInst_rr(X86::KXORBrr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7616 | 0 | } |
7617 | 0 | return 0; |
7618 | 0 | } |
7619 | | |
7620 | 0 | unsigned fastEmit_ISD_XOR_MVT_v16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7621 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
7622 | 0 | return 0; |
7623 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
7624 | 0 | return fastEmitInst_rr(X86::KXORWrr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7625 | 0 | } |
7626 | 0 | return 0; |
7627 | 0 | } |
7628 | | |
7629 | 0 | unsigned fastEmit_ISD_XOR_MVT_v32i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7630 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
7631 | 0 | return 0; |
7632 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7633 | 0 | return fastEmitInst_rr(X86::KXORDrr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7634 | 0 | } |
7635 | 0 | return 0; |
7636 | 0 | } |
7637 | | |
7638 | 0 | unsigned fastEmit_ISD_XOR_MVT_v64i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7639 | 0 | if (RetVT.SimpleTy != MVT::v64i1) |
7640 | 0 | return 0; |
7641 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7642 | 0 | return fastEmitInst_rr(X86::KXORQrr, &X86::VK64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7643 | 0 | } |
7644 | 0 | return 0; |
7645 | 0 | } |
7646 | | |
7647 | 2 | unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7648 | 2 | if (RetVT.SimpleTy != MVT::v2i64) |
7649 | 0 | return 0; |
7650 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
7651 | 0 | return fastEmitInst_rr(X86::VPXORQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7652 | 0 | } |
7653 | 2 | if (2 (Subtarget->hasSSE2() && 2 !Subtarget->hasAVX()2 )) { |
7654 | 2 | return fastEmitInst_rr(X86::PXORrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7655 | 2 | } |
7656 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
7657 | 0 | return fastEmitInst_rr(X86::VPXORrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7658 | 0 | } |
7659 | 0 | return 0; |
7660 | 2 | } |
7661 | | |
7662 | 4 | unsigned fastEmit_ISD_XOR_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7663 | 4 | if (RetVT.SimpleTy != MVT::v4i64) |
7664 | 0 | return 0; |
7665 | 4 | if (4 (Subtarget->hasAVX() && 4 !Subtarget->hasAVX2()4 )) { |
7666 | 2 | return fastEmitInst_rr(X86::VXORPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7667 | 2 | } |
7668 | 2 | if (2 (Subtarget->hasAVX512()) && 2 (Subtarget->hasVLX())0 ) { |
7669 | 0 | return fastEmitInst_rr(X86::VPXORQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7670 | 0 | } |
7671 | 2 | if (2 (Subtarget->hasAVX2()) && 2 (!Subtarget->hasVLX())2 ) { |
7672 | 2 | return fastEmitInst_rr(X86::VPXORYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7673 | 2 | } |
7674 | 0 | return 0; |
7675 | 4 | } |
7676 | | |
7677 | 0 | unsigned fastEmit_ISD_XOR_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7678 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
7679 | 0 | return 0; |
7680 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
7681 | 0 | return fastEmitInst_rr(X86::VPXORQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7682 | 0 | } |
7683 | 0 | return 0; |
7684 | 0 | } |
7685 | | |
7686 | 32 | unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7687 | 32 | switch (VT.SimpleTy) { |
7688 | 0 | case MVT::i8: return fastEmit_ISD_XOR_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7689 | 0 | case MVT::i16: return fastEmit_ISD_XOR_MVT_i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7690 | 14 | case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7691 | 8 | case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7692 | 0 | case MVT::v8i1: return fastEmit_ISD_XOR_MVT_v8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7693 | 0 | case MVT::v16i1: return fastEmit_ISD_XOR_MVT_v16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7694 | 0 | case MVT::v32i1: return fastEmit_ISD_XOR_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7695 | 0 | case MVT::v64i1: return fastEmit_ISD_XOR_MVT_v64i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7696 | 2 | case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7697 | 4 | case MVT::v4i64: return fastEmit_ISD_XOR_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7698 | 0 | case MVT::v8i64: return fastEmit_ISD_XOR_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7699 | 4 | default: return 0; |
7700 | 32 | } |
7701 | 32 | } |
7702 | | |
7703 | | // FastEmit functions for X86ISD::ADDS. |
7704 | | |
7705 | 0 | unsigned fastEmit_X86ISD_ADDS_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7706 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
7707 | 0 | return 0; |
7708 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7709 | 0 | return fastEmitInst_rr(X86::VPADDSBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7710 | 0 | } |
7711 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
7712 | 0 | return fastEmitInst_rr(X86::PADDSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7713 | 0 | } |
7714 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7715 | 0 | return fastEmitInst_rr(X86::VPADDSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7716 | 0 | } |
7717 | 0 | return 0; |
7718 | 0 | } |
7719 | | |
7720 | 0 | unsigned fastEmit_X86ISD_ADDS_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7721 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
7722 | 0 | return 0; |
7723 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7724 | 0 | return fastEmitInst_rr(X86::VPADDSBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7725 | 0 | } |
7726 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7727 | 0 | return fastEmitInst_rr(X86::VPADDSBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7728 | 0 | } |
7729 | 0 | return 0; |
7730 | 0 | } |
7731 | | |
7732 | 0 | unsigned fastEmit_X86ISD_ADDS_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7733 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
7734 | 0 | return 0; |
7735 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7736 | 0 | return fastEmitInst_rr(X86::VPADDSBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7737 | 0 | } |
7738 | 0 | return 0; |
7739 | 0 | } |
7740 | | |
7741 | 0 | unsigned fastEmit_X86ISD_ADDS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7742 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7743 | 0 | return 0; |
7744 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7745 | 0 | return fastEmitInst_rr(X86::VPADDSWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7746 | 0 | } |
7747 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
7748 | 0 | return fastEmitInst_rr(X86::PADDSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7749 | 0 | } |
7750 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7751 | 0 | return fastEmitInst_rr(X86::VPADDSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7752 | 0 | } |
7753 | 0 | return 0; |
7754 | 0 | } |
7755 | | |
7756 | 0 | unsigned fastEmit_X86ISD_ADDS_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7757 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
7758 | 0 | return 0; |
7759 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7760 | 0 | return fastEmitInst_rr(X86::VPADDSWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7761 | 0 | } |
7762 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7763 | 0 | return fastEmitInst_rr(X86::VPADDSWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7764 | 0 | } |
7765 | 0 | return 0; |
7766 | 0 | } |
7767 | | |
7768 | 0 | unsigned fastEmit_X86ISD_ADDS_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7769 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
7770 | 0 | return 0; |
7771 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7772 | 0 | return fastEmitInst_rr(X86::VPADDSWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7773 | 0 | } |
7774 | 0 | return 0; |
7775 | 0 | } |
7776 | | |
7777 | | unsigned fastEmit_X86ISD_ADDS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7778 | | switch (VT.SimpleTy) { |
7779 | | case MVT::v16i8: return fastEmit_X86ISD_ADDS_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7780 | | case MVT::v32i8: return fastEmit_X86ISD_ADDS_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7781 | | case MVT::v64i8: return fastEmit_X86ISD_ADDS_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7782 | | case MVT::v8i16: return fastEmit_X86ISD_ADDS_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7783 | | case MVT::v16i16: return fastEmit_X86ISD_ADDS_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7784 | | case MVT::v32i16: return fastEmit_X86ISD_ADDS_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7785 | | default: return 0; |
7786 | | } |
7787 | | } |
7788 | | |
7789 | | // FastEmit functions for X86ISD::ADDSUB. |
7790 | | |
7791 | 0 | unsigned fastEmit_X86ISD_ADDSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7792 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
7793 | 0 | return 0; |
7794 | 0 | if (0 (Subtarget->hasSSE3() && 0 !Subtarget->hasAVX()0 )) { |
7795 | 0 | return fastEmitInst_rr(X86::ADDSUBPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7796 | 0 | } |
7797 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
7798 | 0 | return fastEmitInst_rr(X86::VADDSUBPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7799 | 0 | } |
7800 | 0 | return 0; |
7801 | 0 | } |
7802 | | |
7803 | 0 | unsigned fastEmit_X86ISD_ADDSUB_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7804 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
7805 | 0 | return 0; |
7806 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
7807 | 0 | return fastEmitInst_rr(X86::VADDSUBPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7808 | 0 | } |
7809 | 0 | return 0; |
7810 | 0 | } |
7811 | | |
7812 | 0 | unsigned fastEmit_X86ISD_ADDSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7813 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
7814 | 0 | return 0; |
7815 | 0 | if (0 (Subtarget->hasSSE3() && 0 !Subtarget->hasAVX()0 )) { |
7816 | 0 | return fastEmitInst_rr(X86::ADDSUBPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7817 | 0 | } |
7818 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
7819 | 0 | return fastEmitInst_rr(X86::VADDSUBPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7820 | 0 | } |
7821 | 0 | return 0; |
7822 | 0 | } |
7823 | | |
7824 | 0 | unsigned fastEmit_X86ISD_ADDSUB_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7825 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
7826 | 0 | return 0; |
7827 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
7828 | 0 | return fastEmitInst_rr(X86::VADDSUBPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7829 | 0 | } |
7830 | 0 | return 0; |
7831 | 0 | } |
7832 | | |
7833 | | unsigned fastEmit_X86ISD_ADDSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7834 | | switch (VT.SimpleTy) { |
7835 | | case MVT::v4f32: return fastEmit_X86ISD_ADDSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7836 | | case MVT::v8f32: return fastEmit_X86ISD_ADDSUB_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7837 | | case MVT::v2f64: return fastEmit_X86ISD_ADDSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7838 | | case MVT::v4f64: return fastEmit_X86ISD_ADDSUB_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7839 | | default: return 0; |
7840 | | } |
7841 | | } |
7842 | | |
7843 | | // FastEmit functions for X86ISD::ADDUS. |
7844 | | |
7845 | 0 | unsigned fastEmit_X86ISD_ADDUS_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7846 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
7847 | 0 | return 0; |
7848 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7849 | 0 | return fastEmitInst_rr(X86::VPADDUSBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7850 | 0 | } |
7851 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
7852 | 0 | return fastEmitInst_rr(X86::PADDUSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7853 | 0 | } |
7854 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7855 | 0 | return fastEmitInst_rr(X86::VPADDUSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7856 | 0 | } |
7857 | 0 | return 0; |
7858 | 0 | } |
7859 | | |
7860 | 0 | unsigned fastEmit_X86ISD_ADDUS_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7861 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
7862 | 0 | return 0; |
7863 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7864 | 0 | return fastEmitInst_rr(X86::VPADDUSBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7865 | 0 | } |
7866 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7867 | 0 | return fastEmitInst_rr(X86::VPADDUSBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7868 | 0 | } |
7869 | 0 | return 0; |
7870 | 0 | } |
7871 | | |
7872 | 0 | unsigned fastEmit_X86ISD_ADDUS_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7873 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
7874 | 0 | return 0; |
7875 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7876 | 0 | return fastEmitInst_rr(X86::VPADDUSBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7877 | 0 | } |
7878 | 0 | return 0; |
7879 | 0 | } |
7880 | | |
7881 | 0 | unsigned fastEmit_X86ISD_ADDUS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7882 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7883 | 0 | return 0; |
7884 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7885 | 0 | return fastEmitInst_rr(X86::VPADDUSWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7886 | 0 | } |
7887 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
7888 | 0 | return fastEmitInst_rr(X86::PADDUSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7889 | 0 | } |
7890 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7891 | 0 | return fastEmitInst_rr(X86::VPADDUSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7892 | 0 | } |
7893 | 0 | return 0; |
7894 | 0 | } |
7895 | | |
7896 | 0 | unsigned fastEmit_X86ISD_ADDUS_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7897 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
7898 | 0 | return 0; |
7899 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7900 | 0 | return fastEmitInst_rr(X86::VPADDUSWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7901 | 0 | } |
7902 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7903 | 0 | return fastEmitInst_rr(X86::VPADDUSWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7904 | 0 | } |
7905 | 0 | return 0; |
7906 | 0 | } |
7907 | | |
7908 | 0 | unsigned fastEmit_X86ISD_ADDUS_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7909 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
7910 | 0 | return 0; |
7911 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
7912 | 0 | return fastEmitInst_rr(X86::VPADDUSWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7913 | 0 | } |
7914 | 0 | return 0; |
7915 | 0 | } |
7916 | | |
7917 | | unsigned fastEmit_X86ISD_ADDUS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7918 | | switch (VT.SimpleTy) { |
7919 | | case MVT::v16i8: return fastEmit_X86ISD_ADDUS_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7920 | | case MVT::v32i8: return fastEmit_X86ISD_ADDUS_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7921 | | case MVT::v64i8: return fastEmit_X86ISD_ADDUS_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7922 | | case MVT::v8i16: return fastEmit_X86ISD_ADDUS_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7923 | | case MVT::v16i16: return fastEmit_X86ISD_ADDUS_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7924 | | case MVT::v32i16: return fastEmit_X86ISD_ADDUS_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7925 | | default: return 0; |
7926 | | } |
7927 | | } |
7928 | | |
7929 | | // FastEmit functions for X86ISD::ANDNP. |
7930 | | |
7931 | 0 | unsigned fastEmit_X86ISD_ANDNP_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7932 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7933 | 0 | return 0; |
7934 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7935 | 0 | return fastEmitInst_rr(X86::VPANDNQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7936 | 0 | } |
7937 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
7938 | 0 | return fastEmitInst_rr(X86::PANDNrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7939 | 0 | } |
7940 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
7941 | 0 | return fastEmitInst_rr(X86::VPANDNrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7942 | 0 | } |
7943 | 0 | return 0; |
7944 | 0 | } |
7945 | | |
7946 | 0 | unsigned fastEmit_X86ISD_ANDNP_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7947 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
7948 | 0 | return 0; |
7949 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX2()0 )) { |
7950 | 0 | return fastEmitInst_rr(X86::VANDNPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7951 | 0 | } |
7952 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
7953 | 0 | return fastEmitInst_rr(X86::VPANDNQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7954 | 0 | } |
7955 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
7956 | 0 | return fastEmitInst_rr(X86::VPANDNYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7957 | 0 | } |
7958 | 0 | return 0; |
7959 | 0 | } |
7960 | | |
7961 | 0 | unsigned fastEmit_X86ISD_ANDNP_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7962 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
7963 | 0 | return 0; |
7964 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
7965 | 0 | return fastEmitInst_rr(X86::VPANDNQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7966 | 0 | } |
7967 | 0 | return 0; |
7968 | 0 | } |
7969 | | |
7970 | | unsigned fastEmit_X86ISD_ANDNP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7971 | | switch (VT.SimpleTy) { |
7972 | | case MVT::v2i64: return fastEmit_X86ISD_ANDNP_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7973 | | case MVT::v4i64: return fastEmit_X86ISD_ANDNP_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7974 | | case MVT::v8i64: return fastEmit_X86ISD_ANDNP_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
7975 | | default: return 0; |
7976 | | } |
7977 | | } |
7978 | | |
7979 | | // FastEmit functions for X86ISD::AVG. |
7980 | | |
7981 | 0 | unsigned fastEmit_X86ISD_AVG_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7982 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
7983 | 0 | return 0; |
7984 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
7985 | 0 | return fastEmitInst_rr(X86::VPAVGBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7986 | 0 | } |
7987 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
7988 | 0 | return fastEmitInst_rr(X86::PAVGBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7989 | 0 | } |
7990 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
7991 | 0 | return fastEmitInst_rr(X86::VPAVGBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
7992 | 0 | } |
7993 | 0 | return 0; |
7994 | 0 | } |
7995 | | |
7996 | 0 | unsigned fastEmit_X86ISD_AVG_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
7997 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
7998 | 0 | return 0; |
7999 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
8000 | 0 | return fastEmitInst_rr(X86::VPAVGBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8001 | 0 | } |
8002 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
8003 | 0 | return fastEmitInst_rr(X86::VPAVGBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8004 | 0 | } |
8005 | 0 | return 0; |
8006 | 0 | } |
8007 | | |
8008 | 0 | unsigned fastEmit_X86ISD_AVG_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8009 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
8010 | 0 | return 0; |
8011 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
8012 | 0 | return fastEmitInst_rr(X86::VPAVGBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8013 | 0 | } |
8014 | 0 | return 0; |
8015 | 0 | } |
8016 | | |
8017 | 0 | unsigned fastEmit_X86ISD_AVG_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8018 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
8019 | 0 | return 0; |
8020 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
8021 | 0 | return fastEmitInst_rr(X86::VPAVGWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8022 | 0 | } |
8023 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8024 | 0 | return fastEmitInst_rr(X86::PAVGWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8025 | 0 | } |
8026 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
8027 | 0 | return fastEmitInst_rr(X86::VPAVGWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8028 | 0 | } |
8029 | 0 | return 0; |
8030 | 0 | } |
8031 | | |
8032 | 0 | unsigned fastEmit_X86ISD_AVG_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8033 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
8034 | 0 | return 0; |
8035 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
8036 | 0 | return fastEmitInst_rr(X86::VPAVGWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8037 | 0 | } |
8038 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
8039 | 0 | return fastEmitInst_rr(X86::VPAVGWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8040 | 0 | } |
8041 | 0 | return 0; |
8042 | 0 | } |
8043 | | |
8044 | 0 | unsigned fastEmit_X86ISD_AVG_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8045 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
8046 | 0 | return 0; |
8047 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
8048 | 0 | return fastEmitInst_rr(X86::VPAVGWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8049 | 0 | } |
8050 | 0 | return 0; |
8051 | 0 | } |
8052 | | |
8053 | | unsigned fastEmit_X86ISD_AVG_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8054 | | switch (VT.SimpleTy) { |
8055 | | case MVT::v16i8: return fastEmit_X86ISD_AVG_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8056 | | case MVT::v32i8: return fastEmit_X86ISD_AVG_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8057 | | case MVT::v64i8: return fastEmit_X86ISD_AVG_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8058 | | case MVT::v8i16: return fastEmit_X86ISD_AVG_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8059 | | case MVT::v16i16: return fastEmit_X86ISD_AVG_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8060 | | case MVT::v32i16: return fastEmit_X86ISD_AVG_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8061 | | default: return 0; |
8062 | | } |
8063 | | } |
8064 | | |
8065 | | // FastEmit functions for X86ISD::BT. |
8066 | | |
8067 | 0 | unsigned fastEmit_X86ISD_BT_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8068 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8069 | 0 | return 0; |
8070 | 0 | return fastEmitInst_rr(X86::BT16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8071 | 0 | } |
8072 | | |
8073 | 0 | unsigned fastEmit_X86ISD_BT_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8074 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8075 | 0 | return 0; |
8076 | 0 | return fastEmitInst_rr(X86::BT32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8077 | 0 | } |
8078 | | |
8079 | 0 | unsigned fastEmit_X86ISD_BT_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8080 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8081 | 0 | return 0; |
8082 | 0 | return fastEmitInst_rr(X86::BT64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8083 | 0 | } |
8084 | | |
8085 | | unsigned fastEmit_X86ISD_BT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8086 | | switch (VT.SimpleTy) { |
8087 | | case MVT::i16: return fastEmit_X86ISD_BT_MVT_i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8088 | | case MVT::i32: return fastEmit_X86ISD_BT_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8089 | | case MVT::i64: return fastEmit_X86ISD_BT_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8090 | | default: return 0; |
8091 | | } |
8092 | | } |
8093 | | |
8094 | | // FastEmit functions for X86ISD::CMP. |
8095 | | |
8096 | 0 | unsigned fastEmit_X86ISD_CMP_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8097 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8098 | 0 | return 0; |
8099 | 0 | return fastEmitInst_rr(X86::CMP8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8100 | 0 | } |
8101 | | |
8102 | 0 | unsigned fastEmit_X86ISD_CMP_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8103 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8104 | 0 | return 0; |
8105 | 0 | return fastEmitInst_rr(X86::CMP16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8106 | 0 | } |
8107 | | |
8108 | 0 | unsigned fastEmit_X86ISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8109 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8110 | 0 | return 0; |
8111 | 0 | return fastEmitInst_rr(X86::CMP32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8112 | 0 | } |
8113 | | |
8114 | 0 | unsigned fastEmit_X86ISD_CMP_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8115 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8116 | 0 | return 0; |
8117 | 0 | return fastEmitInst_rr(X86::CMP64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8118 | 0 | } |
8119 | | |
8120 | 0 | unsigned fastEmit_X86ISD_CMP_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8121 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8122 | 0 | return 0; |
8123 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8124 | 0 | return fastEmitInst_rr(X86::VUCOMISSZrr, &X86::FR32XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8125 | 0 | } |
8126 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8127 | 0 | return fastEmitInst_rr(X86::UCOMISSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8128 | 0 | } |
8129 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8130 | 0 | return fastEmitInst_rr(X86::VUCOMISSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8131 | 0 | } |
8132 | 0 | if (0 (!Subtarget->hasSSE1())0 ) { |
8133 | 0 | return fastEmitInst_rr(X86::UCOM_FpIr32, &X86::RFP32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8134 | 0 | } |
8135 | 0 | return 0; |
8136 | 0 | } |
8137 | | |
8138 | 0 | unsigned fastEmit_X86ISD_CMP_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8139 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8140 | 0 | return 0; |
8141 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8142 | 0 | return fastEmitInst_rr(X86::VUCOMISDZrr, &X86::FR64XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8143 | 0 | } |
8144 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8145 | 0 | return fastEmitInst_rr(X86::UCOMISDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8146 | 0 | } |
8147 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8148 | 0 | return fastEmitInst_rr(X86::VUCOMISDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8149 | 0 | } |
8150 | 0 | if (0 (!Subtarget->hasSSE2())0 ) { |
8151 | 0 | return fastEmitInst_rr(X86::UCOM_FpIr64, &X86::RFP64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8152 | 0 | } |
8153 | 0 | return 0; |
8154 | 0 | } |
8155 | | |
8156 | 0 | unsigned fastEmit_X86ISD_CMP_MVT_f80_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8157 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8158 | 0 | return 0; |
8159 | 0 | return fastEmitInst_rr(X86::UCOM_FpIr80, &X86::RFP80RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8160 | 0 | } |
8161 | | |
8162 | | unsigned fastEmit_X86ISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8163 | | switch (VT.SimpleTy) { |
8164 | | case MVT::i8: return fastEmit_X86ISD_CMP_MVT_i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8165 | | case MVT::i16: return fastEmit_X86ISD_CMP_MVT_i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8166 | | case MVT::i32: return fastEmit_X86ISD_CMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8167 | | case MVT::i64: return fastEmit_X86ISD_CMP_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8168 | | case MVT::f32: return fastEmit_X86ISD_CMP_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8169 | | case MVT::f64: return fastEmit_X86ISD_CMP_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8170 | | case MVT::f80: return fastEmit_X86ISD_CMP_MVT_f80_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8171 | | default: return 0; |
8172 | | } |
8173 | | } |
8174 | | |
8175 | | // FastEmit functions for X86ISD::COMI. |
8176 | | |
8177 | 0 | unsigned fastEmit_X86ISD_COMI_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8178 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8179 | 0 | return 0; |
8180 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8181 | 0 | return fastEmitInst_rr(X86::Int_VCOMISSZrr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8182 | 0 | } |
8183 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8184 | 0 | return fastEmitInst_rr(X86::Int_COMISSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8185 | 0 | } |
8186 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8187 | 0 | return fastEmitInst_rr(X86::Int_VCOMISSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8188 | 0 | } |
8189 | 0 | return 0; |
8190 | 0 | } |
8191 | | |
8192 | 0 | unsigned fastEmit_X86ISD_COMI_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8193 | 0 | if (RetVT.SimpleTy != MVT::i32) |
8194 | 0 | return 0; |
8195 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8196 | 0 | return fastEmitInst_rr(X86::Int_VCOMISDZrr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8197 | 0 | } |
8198 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8199 | 0 | return fastEmitInst_rr(X86::Int_COMISDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8200 | 0 | } |
8201 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8202 | 0 | return fastEmitInst_rr(X86::Int_VCOMISDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8203 | 0 | } |
8204 | 0 | return 0; |
8205 | 0 | } |
8206 | | |
8207 | | unsigned fastEmit_X86ISD_COMI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8208 | | switch (VT.SimpleTy) { |
8209 | | case MVT::v4f32: return fastEmit_X86ISD_COMI_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8210 | | case MVT::v2f64: return fastEmit_X86ISD_COMI_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8211 | | default: return 0; |
8212 | | } |
8213 | | } |
8214 | | |
8215 | | // FastEmit functions for X86ISD::FAND. |
8216 | | |
8217 | 0 | unsigned fastEmit_X86ISD_FAND_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8218 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8219 | 0 | return 0; |
8220 | 0 | return fastEmitInst_rr(X86::ANDPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8221 | 0 | } |
8222 | | |
8223 | | unsigned fastEmit_X86ISD_FAND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8224 | | switch (VT.SimpleTy) { |
8225 | | case MVT::v4f32: return fastEmit_X86ISD_FAND_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8226 | | default: return 0; |
8227 | | } |
8228 | | } |
8229 | | |
8230 | | // FastEmit functions for X86ISD::FANDN. |
8231 | | |
8232 | 0 | unsigned fastEmit_X86ISD_FANDN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8233 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8234 | 0 | return 0; |
8235 | 0 | return fastEmitInst_rr(X86::ANDNPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8236 | 0 | } |
8237 | | |
8238 | | unsigned fastEmit_X86ISD_FANDN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8239 | | switch (VT.SimpleTy) { |
8240 | | case MVT::v4f32: return fastEmit_X86ISD_FANDN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8241 | | default: return 0; |
8242 | | } |
8243 | | } |
8244 | | |
8245 | | // FastEmit functions for X86ISD::FHADD. |
8246 | | |
8247 | 0 | unsigned fastEmit_X86ISD_FHADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8248 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8249 | 0 | return 0; |
8250 | 0 | if (0 (Subtarget->hasSSE3() && 0 !Subtarget->hasAVX()0 )) { |
8251 | 0 | return fastEmitInst_rr(X86::HADDPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8252 | 0 | } |
8253 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
8254 | 0 | return fastEmitInst_rr(X86::VHADDPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8255 | 0 | } |
8256 | 0 | return 0; |
8257 | 0 | } |
8258 | | |
8259 | 0 | unsigned fastEmit_X86ISD_FHADD_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8260 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
8261 | 0 | return 0; |
8262 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
8263 | 0 | return fastEmitInst_rr(X86::VHADDPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8264 | 0 | } |
8265 | 0 | return 0; |
8266 | 0 | } |
8267 | | |
8268 | 0 | unsigned fastEmit_X86ISD_FHADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8269 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8270 | 0 | return 0; |
8271 | 0 | if (0 (Subtarget->hasSSE3() && 0 !Subtarget->hasAVX()0 )) { |
8272 | 0 | return fastEmitInst_rr(X86::HADDPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8273 | 0 | } |
8274 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
8275 | 0 | return fastEmitInst_rr(X86::VHADDPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8276 | 0 | } |
8277 | 0 | return 0; |
8278 | 0 | } |
8279 | | |
8280 | 0 | unsigned fastEmit_X86ISD_FHADD_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8281 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
8282 | 0 | return 0; |
8283 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
8284 | 0 | return fastEmitInst_rr(X86::VHADDPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8285 | 0 | } |
8286 | 0 | return 0; |
8287 | 0 | } |
8288 | | |
8289 | | unsigned fastEmit_X86ISD_FHADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8290 | | switch (VT.SimpleTy) { |
8291 | | case MVT::v4f32: return fastEmit_X86ISD_FHADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8292 | | case MVT::v8f32: return fastEmit_X86ISD_FHADD_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8293 | | case MVT::v2f64: return fastEmit_X86ISD_FHADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8294 | | case MVT::v4f64: return fastEmit_X86ISD_FHADD_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8295 | | default: return 0; |
8296 | | } |
8297 | | } |
8298 | | |
8299 | | // FastEmit functions for X86ISD::FHSUB. |
8300 | | |
8301 | 0 | unsigned fastEmit_X86ISD_FHSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8302 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8303 | 0 | return 0; |
8304 | 0 | if (0 (Subtarget->hasSSE3() && 0 !Subtarget->hasAVX()0 )) { |
8305 | 0 | return fastEmitInst_rr(X86::HSUBPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8306 | 0 | } |
8307 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
8308 | 0 | return fastEmitInst_rr(X86::VHSUBPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8309 | 0 | } |
8310 | 0 | return 0; |
8311 | 0 | } |
8312 | | |
8313 | 0 | unsigned fastEmit_X86ISD_FHSUB_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8314 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
8315 | 0 | return 0; |
8316 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
8317 | 0 | return fastEmitInst_rr(X86::VHSUBPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8318 | 0 | } |
8319 | 0 | return 0; |
8320 | 0 | } |
8321 | | |
8322 | 0 | unsigned fastEmit_X86ISD_FHSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8323 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8324 | 0 | return 0; |
8325 | 0 | if (0 (Subtarget->hasSSE3() && 0 !Subtarget->hasAVX()0 )) { |
8326 | 0 | return fastEmitInst_rr(X86::HSUBPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8327 | 0 | } |
8328 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
8329 | 0 | return fastEmitInst_rr(X86::VHSUBPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8330 | 0 | } |
8331 | 0 | return 0; |
8332 | 0 | } |
8333 | | |
8334 | 0 | unsigned fastEmit_X86ISD_FHSUB_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8335 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
8336 | 0 | return 0; |
8337 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
8338 | 0 | return fastEmitInst_rr(X86::VHSUBPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8339 | 0 | } |
8340 | 0 | return 0; |
8341 | 0 | } |
8342 | | |
8343 | | unsigned fastEmit_X86ISD_FHSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8344 | | switch (VT.SimpleTy) { |
8345 | | case MVT::v4f32: return fastEmit_X86ISD_FHSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8346 | | case MVT::v8f32: return fastEmit_X86ISD_FHSUB_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8347 | | case MVT::v2f64: return fastEmit_X86ISD_FHSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8348 | | case MVT::v4f64: return fastEmit_X86ISD_FHSUB_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8349 | | default: return 0; |
8350 | | } |
8351 | | } |
8352 | | |
8353 | | // FastEmit functions for X86ISD::FMAX. |
8354 | | |
8355 | 0 | unsigned fastEmit_X86ISD_FMAX_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8356 | 0 | if (RetVT.SimpleTy != MVT::f32) |
8357 | 0 | return 0; |
8358 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8359 | 0 | return fastEmitInst_rr(X86::VMAXSSZrr, &X86::FR32XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8360 | 0 | } |
8361 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8362 | 0 | return fastEmitInst_rr(X86::MAXSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8363 | 0 | } |
8364 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8365 | 0 | return fastEmitInst_rr(X86::VMAXSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8366 | 0 | } |
8367 | 0 | return 0; |
8368 | 0 | } |
8369 | | |
8370 | 0 | unsigned fastEmit_X86ISD_FMAX_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8371 | 0 | if (RetVT.SimpleTy != MVT::f64) |
8372 | 0 | return 0; |
8373 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8374 | 0 | return fastEmitInst_rr(X86::VMAXSDZrr, &X86::FR64XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8375 | 0 | } |
8376 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8377 | 0 | return fastEmitInst_rr(X86::MAXSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8378 | 0 | } |
8379 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8380 | 0 | return fastEmitInst_rr(X86::VMAXSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8381 | 0 | } |
8382 | 0 | return 0; |
8383 | 0 | } |
8384 | | |
8385 | 0 | unsigned fastEmit_X86ISD_FMAX_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8386 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8387 | 0 | return 0; |
8388 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8389 | 0 | return fastEmitInst_rr(X86::VMAXPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8390 | 0 | } |
8391 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8392 | 0 | return fastEmitInst_rr(X86::MAXPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8393 | 0 | } |
8394 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8395 | 0 | return fastEmitInst_rr(X86::VMAXPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8396 | 0 | } |
8397 | 0 | return 0; |
8398 | 0 | } |
8399 | | |
8400 | 0 | unsigned fastEmit_X86ISD_FMAX_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8401 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
8402 | 0 | return 0; |
8403 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8404 | 0 | return fastEmitInst_rr(X86::VMAXPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8405 | 0 | } |
8406 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8407 | 0 | return fastEmitInst_rr(X86::VMAXPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8408 | 0 | } |
8409 | 0 | return 0; |
8410 | 0 | } |
8411 | | |
8412 | 0 | unsigned fastEmit_X86ISD_FMAX_MVT_v16f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8413 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
8414 | 0 | return 0; |
8415 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8416 | 0 | return fastEmitInst_rr(X86::VMAXPSZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8417 | 0 | } |
8418 | 0 | return 0; |
8419 | 0 | } |
8420 | | |
8421 | 0 | unsigned fastEmit_X86ISD_FMAX_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8422 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8423 | 0 | return 0; |
8424 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8425 | 0 | return fastEmitInst_rr(X86::VMAXPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8426 | 0 | } |
8427 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8428 | 0 | return fastEmitInst_rr(X86::MAXPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8429 | 0 | } |
8430 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8431 | 0 | return fastEmitInst_rr(X86::VMAXPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8432 | 0 | } |
8433 | 0 | return 0; |
8434 | 0 | } |
8435 | | |
8436 | 0 | unsigned fastEmit_X86ISD_FMAX_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8437 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
8438 | 0 | return 0; |
8439 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8440 | 0 | return fastEmitInst_rr(X86::VMAXPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8441 | 0 | } |
8442 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8443 | 0 | return fastEmitInst_rr(X86::VMAXPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8444 | 0 | } |
8445 | 0 | return 0; |
8446 | 0 | } |
8447 | | |
8448 | 0 | unsigned fastEmit_X86ISD_FMAX_MVT_v8f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8449 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
8450 | 0 | return 0; |
8451 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8452 | 0 | return fastEmitInst_rr(X86::VMAXPDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8453 | 0 | } |
8454 | 0 | return 0; |
8455 | 0 | } |
8456 | | |
8457 | | unsigned fastEmit_X86ISD_FMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8458 | | switch (VT.SimpleTy) { |
8459 | | case MVT::f32: return fastEmit_X86ISD_FMAX_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8460 | | case MVT::f64: return fastEmit_X86ISD_FMAX_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8461 | | case MVT::v4f32: return fastEmit_X86ISD_FMAX_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8462 | | case MVT::v8f32: return fastEmit_X86ISD_FMAX_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8463 | | case MVT::v16f32: return fastEmit_X86ISD_FMAX_MVT_v16f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8464 | | case MVT::v2f64: return fastEmit_X86ISD_FMAX_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8465 | | case MVT::v4f64: return fastEmit_X86ISD_FMAX_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8466 | | case MVT::v8f64: return fastEmit_X86ISD_FMAX_MVT_v8f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8467 | | default: return 0; |
8468 | | } |
8469 | | } |
8470 | | |
8471 | | // FastEmit functions for X86ISD::FMAXC. |
8472 | | |
8473 | 0 | unsigned fastEmit_X86ISD_FMAXC_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8474 | 0 | if (RetVT.SimpleTy != MVT::f32) |
8475 | 0 | return 0; |
8476 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8477 | 0 | return fastEmitInst_rr(X86::VMAXCSSZrr, &X86::FR32XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8478 | 0 | } |
8479 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8480 | 0 | return fastEmitInst_rr(X86::MAXCSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8481 | 0 | } |
8482 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8483 | 0 | return fastEmitInst_rr(X86::VMAXCSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8484 | 0 | } |
8485 | 0 | return 0; |
8486 | 0 | } |
8487 | | |
8488 | 0 | unsigned fastEmit_X86ISD_FMAXC_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8489 | 0 | if (RetVT.SimpleTy != MVT::f64) |
8490 | 0 | return 0; |
8491 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8492 | 0 | return fastEmitInst_rr(X86::VMAXCSDZrr, &X86::FR64XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8493 | 0 | } |
8494 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8495 | 0 | return fastEmitInst_rr(X86::MAXCSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8496 | 0 | } |
8497 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8498 | 0 | return fastEmitInst_rr(X86::VMAXCSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8499 | 0 | } |
8500 | 0 | return 0; |
8501 | 0 | } |
8502 | | |
8503 | 0 | unsigned fastEmit_X86ISD_FMAXC_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8504 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8505 | 0 | return 0; |
8506 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8507 | 0 | return fastEmitInst_rr(X86::VMAXCPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8508 | 0 | } |
8509 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8510 | 0 | return fastEmitInst_rr(X86::MAXCPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8511 | 0 | } |
8512 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8513 | 0 | return fastEmitInst_rr(X86::VMAXCPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8514 | 0 | } |
8515 | 0 | return 0; |
8516 | 0 | } |
8517 | | |
8518 | 0 | unsigned fastEmit_X86ISD_FMAXC_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8519 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
8520 | 0 | return 0; |
8521 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8522 | 0 | return fastEmitInst_rr(X86::VMAXCPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8523 | 0 | } |
8524 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8525 | 0 | return fastEmitInst_rr(X86::VMAXCPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8526 | 0 | } |
8527 | 0 | return 0; |
8528 | 0 | } |
8529 | | |
8530 | 0 | unsigned fastEmit_X86ISD_FMAXC_MVT_v16f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8531 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
8532 | 0 | return 0; |
8533 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8534 | 0 | return fastEmitInst_rr(X86::VMAXCPSZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8535 | 0 | } |
8536 | 0 | return 0; |
8537 | 0 | } |
8538 | | |
8539 | 0 | unsigned fastEmit_X86ISD_FMAXC_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8540 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8541 | 0 | return 0; |
8542 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8543 | 0 | return fastEmitInst_rr(X86::VMAXCPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8544 | 0 | } |
8545 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8546 | 0 | return fastEmitInst_rr(X86::MAXCPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8547 | 0 | } |
8548 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8549 | 0 | return fastEmitInst_rr(X86::VMAXCPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8550 | 0 | } |
8551 | 0 | return 0; |
8552 | 0 | } |
8553 | | |
8554 | 0 | unsigned fastEmit_X86ISD_FMAXC_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8555 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
8556 | 0 | return 0; |
8557 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8558 | 0 | return fastEmitInst_rr(X86::VMAXCPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8559 | 0 | } |
8560 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8561 | 0 | return fastEmitInst_rr(X86::VMAXCPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8562 | 0 | } |
8563 | 0 | return 0; |
8564 | 0 | } |
8565 | | |
8566 | 0 | unsigned fastEmit_X86ISD_FMAXC_MVT_v8f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8567 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
8568 | 0 | return 0; |
8569 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8570 | 0 | return fastEmitInst_rr(X86::VMAXCPDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8571 | 0 | } |
8572 | 0 | return 0; |
8573 | 0 | } |
8574 | | |
8575 | | unsigned fastEmit_X86ISD_FMAXC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8576 | | switch (VT.SimpleTy) { |
8577 | | case MVT::f32: return fastEmit_X86ISD_FMAXC_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8578 | | case MVT::f64: return fastEmit_X86ISD_FMAXC_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8579 | | case MVT::v4f32: return fastEmit_X86ISD_FMAXC_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8580 | | case MVT::v8f32: return fastEmit_X86ISD_FMAXC_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8581 | | case MVT::v16f32: return fastEmit_X86ISD_FMAXC_MVT_v16f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8582 | | case MVT::v2f64: return fastEmit_X86ISD_FMAXC_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8583 | | case MVT::v4f64: return fastEmit_X86ISD_FMAXC_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8584 | | case MVT::v8f64: return fastEmit_X86ISD_FMAXC_MVT_v8f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8585 | | default: return 0; |
8586 | | } |
8587 | | } |
8588 | | |
8589 | | // FastEmit functions for X86ISD::FMAXS. |
8590 | | |
8591 | 0 | unsigned fastEmit_X86ISD_FMAXS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8592 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8593 | 0 | return 0; |
8594 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8595 | 0 | return fastEmitInst_rr(X86::VMAXSSZrr_Int, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8596 | 0 | } |
8597 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8598 | 0 | return fastEmitInst_rr(X86::MAXSSrr_Int, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8599 | 0 | } |
8600 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8601 | 0 | return fastEmitInst_rr(X86::VMAXSSrr_Int, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8602 | 0 | } |
8603 | 0 | return 0; |
8604 | 0 | } |
8605 | | |
8606 | 0 | unsigned fastEmit_X86ISD_FMAXS_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8607 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8608 | 0 | return 0; |
8609 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8610 | 0 | return fastEmitInst_rr(X86::VMAXSDZrr_Int, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8611 | 0 | } |
8612 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8613 | 0 | return fastEmitInst_rr(X86::MAXSDrr_Int, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8614 | 0 | } |
8615 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8616 | 0 | return fastEmitInst_rr(X86::VMAXSDrr_Int, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8617 | 0 | } |
8618 | 0 | return 0; |
8619 | 0 | } |
8620 | | |
8621 | | unsigned fastEmit_X86ISD_FMAXS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8622 | | switch (VT.SimpleTy) { |
8623 | | case MVT::v4f32: return fastEmit_X86ISD_FMAXS_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8624 | | case MVT::v2f64: return fastEmit_X86ISD_FMAXS_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8625 | | default: return 0; |
8626 | | } |
8627 | | } |
8628 | | |
8629 | | // FastEmit functions for X86ISD::FMIN. |
8630 | | |
8631 | 0 | unsigned fastEmit_X86ISD_FMIN_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8632 | 0 | if (RetVT.SimpleTy != MVT::f32) |
8633 | 0 | return 0; |
8634 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8635 | 0 | return fastEmitInst_rr(X86::VMINSSZrr, &X86::FR32XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8636 | 0 | } |
8637 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8638 | 0 | return fastEmitInst_rr(X86::MINSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8639 | 0 | } |
8640 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8641 | 0 | return fastEmitInst_rr(X86::VMINSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8642 | 0 | } |
8643 | 0 | return 0; |
8644 | 0 | } |
8645 | | |
8646 | 0 | unsigned fastEmit_X86ISD_FMIN_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8647 | 0 | if (RetVT.SimpleTy != MVT::f64) |
8648 | 0 | return 0; |
8649 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8650 | 0 | return fastEmitInst_rr(X86::VMINSDZrr, &X86::FR64XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8651 | 0 | } |
8652 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8653 | 0 | return fastEmitInst_rr(X86::MINSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8654 | 0 | } |
8655 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8656 | 0 | return fastEmitInst_rr(X86::VMINSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8657 | 0 | } |
8658 | 0 | return 0; |
8659 | 0 | } |
8660 | | |
8661 | 0 | unsigned fastEmit_X86ISD_FMIN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8662 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8663 | 0 | return 0; |
8664 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8665 | 0 | return fastEmitInst_rr(X86::VMINPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8666 | 0 | } |
8667 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8668 | 0 | return fastEmitInst_rr(X86::MINPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8669 | 0 | } |
8670 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8671 | 0 | return fastEmitInst_rr(X86::VMINPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8672 | 0 | } |
8673 | 0 | return 0; |
8674 | 0 | } |
8675 | | |
8676 | 0 | unsigned fastEmit_X86ISD_FMIN_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8677 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
8678 | 0 | return 0; |
8679 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8680 | 0 | return fastEmitInst_rr(X86::VMINPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8681 | 0 | } |
8682 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8683 | 0 | return fastEmitInst_rr(X86::VMINPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8684 | 0 | } |
8685 | 0 | return 0; |
8686 | 0 | } |
8687 | | |
8688 | 0 | unsigned fastEmit_X86ISD_FMIN_MVT_v16f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8689 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
8690 | 0 | return 0; |
8691 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8692 | 0 | return fastEmitInst_rr(X86::VMINPSZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8693 | 0 | } |
8694 | 0 | return 0; |
8695 | 0 | } |
8696 | | |
8697 | 0 | unsigned fastEmit_X86ISD_FMIN_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8698 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8699 | 0 | return 0; |
8700 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8701 | 0 | return fastEmitInst_rr(X86::VMINPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8702 | 0 | } |
8703 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8704 | 0 | return fastEmitInst_rr(X86::MINPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8705 | 0 | } |
8706 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8707 | 0 | return fastEmitInst_rr(X86::VMINPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8708 | 0 | } |
8709 | 0 | return 0; |
8710 | 0 | } |
8711 | | |
8712 | 0 | unsigned fastEmit_X86ISD_FMIN_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8713 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
8714 | 0 | return 0; |
8715 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8716 | 0 | return fastEmitInst_rr(X86::VMINPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8717 | 0 | } |
8718 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8719 | 0 | return fastEmitInst_rr(X86::VMINPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8720 | 0 | } |
8721 | 0 | return 0; |
8722 | 0 | } |
8723 | | |
8724 | 0 | unsigned fastEmit_X86ISD_FMIN_MVT_v8f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8725 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
8726 | 0 | return 0; |
8727 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8728 | 0 | return fastEmitInst_rr(X86::VMINPDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8729 | 0 | } |
8730 | 0 | return 0; |
8731 | 0 | } |
8732 | | |
8733 | | unsigned fastEmit_X86ISD_FMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8734 | | switch (VT.SimpleTy) { |
8735 | | case MVT::f32: return fastEmit_X86ISD_FMIN_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8736 | | case MVT::f64: return fastEmit_X86ISD_FMIN_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8737 | | case MVT::v4f32: return fastEmit_X86ISD_FMIN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8738 | | case MVT::v8f32: return fastEmit_X86ISD_FMIN_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8739 | | case MVT::v16f32: return fastEmit_X86ISD_FMIN_MVT_v16f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8740 | | case MVT::v2f64: return fastEmit_X86ISD_FMIN_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8741 | | case MVT::v4f64: return fastEmit_X86ISD_FMIN_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8742 | | case MVT::v8f64: return fastEmit_X86ISD_FMIN_MVT_v8f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8743 | | default: return 0; |
8744 | | } |
8745 | | } |
8746 | | |
8747 | | // FastEmit functions for X86ISD::FMINC. |
8748 | | |
8749 | 0 | unsigned fastEmit_X86ISD_FMINC_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8750 | 0 | if (RetVT.SimpleTy != MVT::f32) |
8751 | 0 | return 0; |
8752 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8753 | 0 | return fastEmitInst_rr(X86::VMINCSSZrr, &X86::FR32XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8754 | 0 | } |
8755 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8756 | 0 | return fastEmitInst_rr(X86::MINCSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8757 | 0 | } |
8758 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8759 | 0 | return fastEmitInst_rr(X86::VMINCSSrr, &X86::FR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8760 | 0 | } |
8761 | 0 | return 0; |
8762 | 0 | } |
8763 | | |
8764 | 0 | unsigned fastEmit_X86ISD_FMINC_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8765 | 0 | if (RetVT.SimpleTy != MVT::f64) |
8766 | 0 | return 0; |
8767 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8768 | 0 | return fastEmitInst_rr(X86::VMINCSDZrr, &X86::FR64XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8769 | 0 | } |
8770 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8771 | 0 | return fastEmitInst_rr(X86::MINCSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8772 | 0 | } |
8773 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8774 | 0 | return fastEmitInst_rr(X86::VMINCSDrr, &X86::FR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8775 | 0 | } |
8776 | 0 | return 0; |
8777 | 0 | } |
8778 | | |
8779 | 0 | unsigned fastEmit_X86ISD_FMINC_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8780 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8781 | 0 | return 0; |
8782 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8783 | 0 | return fastEmitInst_rr(X86::VMINCPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8784 | 0 | } |
8785 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8786 | 0 | return fastEmitInst_rr(X86::MINCPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8787 | 0 | } |
8788 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8789 | 0 | return fastEmitInst_rr(X86::VMINCPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8790 | 0 | } |
8791 | 0 | return 0; |
8792 | 0 | } |
8793 | | |
8794 | 0 | unsigned fastEmit_X86ISD_FMINC_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8795 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
8796 | 0 | return 0; |
8797 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8798 | 0 | return fastEmitInst_rr(X86::VMINCPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8799 | 0 | } |
8800 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8801 | 0 | return fastEmitInst_rr(X86::VMINCPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8802 | 0 | } |
8803 | 0 | return 0; |
8804 | 0 | } |
8805 | | |
8806 | 0 | unsigned fastEmit_X86ISD_FMINC_MVT_v16f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8807 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
8808 | 0 | return 0; |
8809 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8810 | 0 | return fastEmitInst_rr(X86::VMINCPSZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8811 | 0 | } |
8812 | 0 | return 0; |
8813 | 0 | } |
8814 | | |
8815 | 0 | unsigned fastEmit_X86ISD_FMINC_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8816 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8817 | 0 | return 0; |
8818 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8819 | 0 | return fastEmitInst_rr(X86::VMINCPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8820 | 0 | } |
8821 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8822 | 0 | return fastEmitInst_rr(X86::MINCPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8823 | 0 | } |
8824 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8825 | 0 | return fastEmitInst_rr(X86::VMINCPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8826 | 0 | } |
8827 | 0 | return 0; |
8828 | 0 | } |
8829 | | |
8830 | 0 | unsigned fastEmit_X86ISD_FMINC_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8831 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
8832 | 0 | return 0; |
8833 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
8834 | 0 | return fastEmitInst_rr(X86::VMINCPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8835 | 0 | } |
8836 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
8837 | 0 | return fastEmitInst_rr(X86::VMINCPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8838 | 0 | } |
8839 | 0 | return 0; |
8840 | 0 | } |
8841 | | |
8842 | 0 | unsigned fastEmit_X86ISD_FMINC_MVT_v8f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8843 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
8844 | 0 | return 0; |
8845 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8846 | 0 | return fastEmitInst_rr(X86::VMINCPDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8847 | 0 | } |
8848 | 0 | return 0; |
8849 | 0 | } |
8850 | | |
8851 | | unsigned fastEmit_X86ISD_FMINC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8852 | | switch (VT.SimpleTy) { |
8853 | | case MVT::f32: return fastEmit_X86ISD_FMINC_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8854 | | case MVT::f64: return fastEmit_X86ISD_FMINC_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8855 | | case MVT::v4f32: return fastEmit_X86ISD_FMINC_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8856 | | case MVT::v8f32: return fastEmit_X86ISD_FMINC_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8857 | | case MVT::v16f32: return fastEmit_X86ISD_FMINC_MVT_v16f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8858 | | case MVT::v2f64: return fastEmit_X86ISD_FMINC_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8859 | | case MVT::v4f64: return fastEmit_X86ISD_FMINC_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8860 | | case MVT::v8f64: return fastEmit_X86ISD_FMINC_MVT_v8f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8861 | | default: return 0; |
8862 | | } |
8863 | | } |
8864 | | |
8865 | | // FastEmit functions for X86ISD::FMINS. |
8866 | | |
8867 | 0 | unsigned fastEmit_X86ISD_FMINS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8868 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8869 | 0 | return 0; |
8870 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8871 | 0 | return fastEmitInst_rr(X86::VMINSSZrr_Int, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8872 | 0 | } |
8873 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
8874 | 0 | return fastEmitInst_rr(X86::MINSSrr_Int, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8875 | 0 | } |
8876 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8877 | 0 | return fastEmitInst_rr(X86::VMINSSrr_Int, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8878 | 0 | } |
8879 | 0 | return 0; |
8880 | 0 | } |
8881 | | |
8882 | 0 | unsigned fastEmit_X86ISD_FMINS_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8883 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8884 | 0 | return 0; |
8885 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8886 | 0 | return fastEmitInst_rr(X86::VMINSDZrr_Int, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8887 | 0 | } |
8888 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
8889 | 0 | return fastEmitInst_rr(X86::MINSDrr_Int, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8890 | 0 | } |
8891 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
8892 | 0 | return fastEmitInst_rr(X86::VMINSDrr_Int, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8893 | 0 | } |
8894 | 0 | return 0; |
8895 | 0 | } |
8896 | | |
8897 | | unsigned fastEmit_X86ISD_FMINS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8898 | | switch (VT.SimpleTy) { |
8899 | | case MVT::v4f32: return fastEmit_X86ISD_FMINS_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8900 | | case MVT::v2f64: return fastEmit_X86ISD_FMINS_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8901 | | default: return 0; |
8902 | | } |
8903 | | } |
8904 | | |
8905 | | // FastEmit functions for X86ISD::FOR. |
8906 | | |
8907 | 0 | unsigned fastEmit_X86ISD_FOR_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8908 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8909 | 0 | return 0; |
8910 | 0 | return fastEmitInst_rr(X86::ORPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8911 | 0 | } |
8912 | | |
8913 | | unsigned fastEmit_X86ISD_FOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8914 | | switch (VT.SimpleTy) { |
8915 | | case MVT::v4f32: return fastEmit_X86ISD_FOR_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8916 | | default: return 0; |
8917 | | } |
8918 | | } |
8919 | | |
8920 | | // FastEmit functions for X86ISD::FRCPS. |
8921 | | |
8922 | 0 | unsigned fastEmit_X86ISD_FRCPS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8923 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8924 | 0 | return 0; |
8925 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8926 | 0 | return fastEmitInst_rr(X86::VRCP14SSrr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8927 | 0 | } |
8928 | 0 | return 0; |
8929 | 0 | } |
8930 | | |
8931 | 0 | unsigned fastEmit_X86ISD_FRCPS_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8932 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8933 | 0 | return 0; |
8934 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8935 | 0 | return fastEmitInst_rr(X86::VRCP14SDrr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8936 | 0 | } |
8937 | 0 | return 0; |
8938 | 0 | } |
8939 | | |
8940 | | unsigned fastEmit_X86ISD_FRCPS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8941 | | switch (VT.SimpleTy) { |
8942 | | case MVT::v4f32: return fastEmit_X86ISD_FRCPS_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8943 | | case MVT::v2f64: return fastEmit_X86ISD_FRCPS_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8944 | | default: return 0; |
8945 | | } |
8946 | | } |
8947 | | |
8948 | | // FastEmit functions for X86ISD::FRSQRTS. |
8949 | | |
8950 | 0 | unsigned fastEmit_X86ISD_FRSQRTS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8951 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8952 | 0 | return 0; |
8953 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8954 | 0 | return fastEmitInst_rr(X86::VRSQRT14SSrr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8955 | 0 | } |
8956 | 0 | return 0; |
8957 | 0 | } |
8958 | | |
8959 | 0 | unsigned fastEmit_X86ISD_FRSQRTS_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8960 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8961 | 0 | return 0; |
8962 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
8963 | 0 | return fastEmitInst_rr(X86::VRSQRT14SDrr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8964 | 0 | } |
8965 | 0 | return 0; |
8966 | 0 | } |
8967 | | |
8968 | | unsigned fastEmit_X86ISD_FRSQRTS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8969 | | switch (VT.SimpleTy) { |
8970 | | case MVT::v4f32: return fastEmit_X86ISD_FRSQRTS_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8971 | | case MVT::v2f64: return fastEmit_X86ISD_FRSQRTS_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8972 | | default: return 0; |
8973 | | } |
8974 | | } |
8975 | | |
8976 | | // FastEmit functions for X86ISD::FXOR. |
8977 | | |
8978 | 0 | unsigned fastEmit_X86ISD_FXOR_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8979 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8980 | 0 | return 0; |
8981 | 0 | return fastEmitInst_rr(X86::XORPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8982 | 0 | } |
8983 | | |
8984 | | unsigned fastEmit_X86ISD_FXOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8985 | | switch (VT.SimpleTy) { |
8986 | | case MVT::v4f32: return fastEmit_X86ISD_FXOR_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
8987 | | default: return 0; |
8988 | | } |
8989 | | } |
8990 | | |
8991 | | // FastEmit functions for X86ISD::HADD. |
8992 | | |
8993 | 0 | unsigned fastEmit_X86ISD_HADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
8994 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
8995 | 0 | return 0; |
8996 | 0 | if (0 (Subtarget->hasSSSE3() && 0 !Subtarget->hasAVX()0 )) { |
8997 | 0 | return fastEmitInst_rr(X86::PHADDWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
8998 | 0 | } |
8999 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
9000 | 0 | return fastEmitInst_rr(X86::VPHADDWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9001 | 0 | } |
9002 | 0 | return 0; |
9003 | 0 | } |
9004 | | |
9005 | 0 | unsigned fastEmit_X86ISD_HADD_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9006 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
9007 | 0 | return 0; |
9008 | 0 | if (0 (Subtarget->hasAVX2())0 ) { |
9009 | 0 | return fastEmitInst_rr(X86::VPHADDWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9010 | 0 | } |
9011 | 0 | return 0; |
9012 | 0 | } |
9013 | | |
9014 | 0 | unsigned fastEmit_X86ISD_HADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9015 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
9016 | 0 | return 0; |
9017 | 0 | if (0 (Subtarget->hasSSSE3() && 0 !Subtarget->hasAVX()0 )) { |
9018 | 0 | return fastEmitInst_rr(X86::PHADDDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9019 | 0 | } |
9020 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
9021 | 0 | return fastEmitInst_rr(X86::VPHADDDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9022 | 0 | } |
9023 | 0 | return 0; |
9024 | 0 | } |
9025 | | |
9026 | 0 | unsigned fastEmit_X86ISD_HADD_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9027 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
9028 | 0 | return 0; |
9029 | 0 | if (0 (Subtarget->hasAVX2())0 ) { |
9030 | 0 | return fastEmitInst_rr(X86::VPHADDDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9031 | 0 | } |
9032 | 0 | return 0; |
9033 | 0 | } |
9034 | | |
9035 | | unsigned fastEmit_X86ISD_HADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9036 | | switch (VT.SimpleTy) { |
9037 | | case MVT::v8i16: return fastEmit_X86ISD_HADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9038 | | case MVT::v16i16: return fastEmit_X86ISD_HADD_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9039 | | case MVT::v4i32: return fastEmit_X86ISD_HADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9040 | | case MVT::v8i32: return fastEmit_X86ISD_HADD_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9041 | | default: return 0; |
9042 | | } |
9043 | | } |
9044 | | |
9045 | | // FastEmit functions for X86ISD::HSUB. |
9046 | | |
9047 | 0 | unsigned fastEmit_X86ISD_HSUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9048 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
9049 | 0 | return 0; |
9050 | 0 | if (0 (Subtarget->hasSSSE3() && 0 !Subtarget->hasAVX()0 )) { |
9051 | 0 | return fastEmitInst_rr(X86::PHSUBWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9052 | 0 | } |
9053 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
9054 | 0 | return fastEmitInst_rr(X86::VPHSUBWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9055 | 0 | } |
9056 | 0 | return 0; |
9057 | 0 | } |
9058 | | |
9059 | 0 | unsigned fastEmit_X86ISD_HSUB_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9060 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
9061 | 0 | return 0; |
9062 | 0 | if (0 (Subtarget->hasAVX2())0 ) { |
9063 | 0 | return fastEmitInst_rr(X86::VPHSUBWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9064 | 0 | } |
9065 | 0 | return 0; |
9066 | 0 | } |
9067 | | |
9068 | 0 | unsigned fastEmit_X86ISD_HSUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9069 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
9070 | 0 | return 0; |
9071 | 0 | if (0 (Subtarget->hasSSSE3() && 0 !Subtarget->hasAVX()0 )) { |
9072 | 0 | return fastEmitInst_rr(X86::PHSUBDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9073 | 0 | } |
9074 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
9075 | 0 | return fastEmitInst_rr(X86::VPHSUBDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9076 | 0 | } |
9077 | 0 | return 0; |
9078 | 0 | } |
9079 | | |
9080 | 0 | unsigned fastEmit_X86ISD_HSUB_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9081 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
9082 | 0 | return 0; |
9083 | 0 | if (0 (Subtarget->hasAVX2())0 ) { |
9084 | 0 | return fastEmitInst_rr(X86::VPHSUBDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9085 | 0 | } |
9086 | 0 | return 0; |
9087 | 0 | } |
9088 | | |
9089 | | unsigned fastEmit_X86ISD_HSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9090 | | switch (VT.SimpleTy) { |
9091 | | case MVT::v8i16: return fastEmit_X86ISD_HSUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9092 | | case MVT::v16i16: return fastEmit_X86ISD_HSUB_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9093 | | case MVT::v4i32: return fastEmit_X86ISD_HSUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9094 | | case MVT::v8i32: return fastEmit_X86ISD_HSUB_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9095 | | default: return 0; |
9096 | | } |
9097 | | } |
9098 | | |
9099 | | // FastEmit functions for X86ISD::KORTEST. |
9100 | | |
9101 | 0 | unsigned fastEmit_X86ISD_KORTEST_MVT_v8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9102 | 0 | if (RetVT.SimpleTy != MVT::i32) |
9103 | 0 | return 0; |
9104 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
9105 | 0 | return fastEmitInst_rr(X86::KORTESTBrr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9106 | 0 | } |
9107 | 0 | return 0; |
9108 | 0 | } |
9109 | | |
9110 | 0 | unsigned fastEmit_X86ISD_KORTEST_MVT_v16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9111 | 0 | if (RetVT.SimpleTy != MVT::i32) |
9112 | 0 | return 0; |
9113 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
9114 | 0 | return fastEmitInst_rr(X86::KORTESTWrr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9115 | 0 | } |
9116 | 0 | return 0; |
9117 | 0 | } |
9118 | | |
9119 | 0 | unsigned fastEmit_X86ISD_KORTEST_MVT_v32i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9120 | 0 | if (RetVT.SimpleTy != MVT::i32) |
9121 | 0 | return 0; |
9122 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9123 | 0 | return fastEmitInst_rr(X86::KORTESTDrr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9124 | 0 | } |
9125 | 0 | return 0; |
9126 | 0 | } |
9127 | | |
9128 | 0 | unsigned fastEmit_X86ISD_KORTEST_MVT_v64i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9129 | 0 | if (RetVT.SimpleTy != MVT::i32) |
9130 | 0 | return 0; |
9131 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9132 | 0 | return fastEmitInst_rr(X86::KORTESTQrr, &X86::VK64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9133 | 0 | } |
9134 | 0 | return 0; |
9135 | 0 | } |
9136 | | |
9137 | | unsigned fastEmit_X86ISD_KORTEST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9138 | | switch (VT.SimpleTy) { |
9139 | | case MVT::v8i1: return fastEmit_X86ISD_KORTEST_MVT_v8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9140 | | case MVT::v16i1: return fastEmit_X86ISD_KORTEST_MVT_v16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9141 | | case MVT::v32i1: return fastEmit_X86ISD_KORTEST_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9142 | | case MVT::v64i1: return fastEmit_X86ISD_KORTEST_MVT_v64i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9143 | | default: return 0; |
9144 | | } |
9145 | | } |
9146 | | |
9147 | | // FastEmit functions for X86ISD::KTEST. |
9148 | | |
9149 | 0 | unsigned fastEmit_X86ISD_KTEST_MVT_v8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9150 | 0 | if (RetVT.SimpleTy != MVT::i32) |
9151 | 0 | return 0; |
9152 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
9153 | 0 | return fastEmitInst_rr(X86::KTESTBrr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9154 | 0 | } |
9155 | 0 | return 0; |
9156 | 0 | } |
9157 | | |
9158 | 0 | unsigned fastEmit_X86ISD_KTEST_MVT_v16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9159 | 0 | if (RetVT.SimpleTy != MVT::i32) |
9160 | 0 | return 0; |
9161 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
9162 | 0 | return fastEmitInst_rr(X86::KTESTWrr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9163 | 0 | } |
9164 | 0 | return 0; |
9165 | 0 | } |
9166 | | |
9167 | 0 | unsigned fastEmit_X86ISD_KTEST_MVT_v32i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9168 | 0 | if (RetVT.SimpleTy != MVT::i32) |
9169 | 0 | return 0; |
9170 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9171 | 0 | return fastEmitInst_rr(X86::KTESTDrr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9172 | 0 | } |
9173 | 0 | return 0; |
9174 | 0 | } |
9175 | | |
9176 | 0 | unsigned fastEmit_X86ISD_KTEST_MVT_v64i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9177 | 0 | if (RetVT.SimpleTy != MVT::i32) |
9178 | 0 | return 0; |
9179 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9180 | 0 | return fastEmitInst_rr(X86::KTESTQrr, &X86::VK64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9181 | 0 | } |
9182 | 0 | return 0; |
9183 | 0 | } |
9184 | | |
9185 | | unsigned fastEmit_X86ISD_KTEST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9186 | | switch (VT.SimpleTy) { |
9187 | | case MVT::v8i1: return fastEmit_X86ISD_KTEST_MVT_v8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9188 | | case MVT::v16i1: return fastEmit_X86ISD_KTEST_MVT_v16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9189 | | case MVT::v32i1: return fastEmit_X86ISD_KTEST_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9190 | | case MVT::v64i1: return fastEmit_X86ISD_KTEST_MVT_v64i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9191 | | default: return 0; |
9192 | | } |
9193 | | } |
9194 | | |
9195 | | // FastEmit functions for X86ISD::MOVHLPS. |
9196 | | |
9197 | 0 | unsigned fastEmit_X86ISD_MOVHLPS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9198 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
9199 | 0 | return 0; |
9200 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
9201 | 0 | return fastEmitInst_rr(X86::MOVHLPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9202 | 0 | } |
9203 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
9204 | 0 | return fastEmitInst_rr(X86::VMOVHLPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9205 | 0 | } |
9206 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
9207 | 0 | return fastEmitInst_rr(X86::VMOVHLPSZrr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9208 | 0 | } |
9209 | 0 | return 0; |
9210 | 0 | } |
9211 | | |
9212 | | unsigned fastEmit_X86ISD_MOVHLPS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9213 | | switch (VT.SimpleTy) { |
9214 | | case MVT::v4f32: return fastEmit_X86ISD_MOVHLPS_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9215 | | default: return 0; |
9216 | | } |
9217 | | } |
9218 | | |
9219 | | // FastEmit functions for X86ISD::MOVLHPS. |
9220 | | |
9221 | 0 | unsigned fastEmit_X86ISD_MOVLHPS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9222 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
9223 | 0 | return 0; |
9224 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
9225 | 0 | return fastEmitInst_rr(X86::MOVLHPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9226 | 0 | } |
9227 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
9228 | 0 | return fastEmitInst_rr(X86::VMOVLHPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9229 | 0 | } |
9230 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
9231 | 0 | return fastEmitInst_rr(X86::VMOVLHPSZrr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9232 | 0 | } |
9233 | 0 | return 0; |
9234 | 0 | } |
9235 | | |
9236 | | unsigned fastEmit_X86ISD_MOVLHPS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9237 | | switch (VT.SimpleTy) { |
9238 | | case MVT::v4f32: return fastEmit_X86ISD_MOVLHPS_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9239 | | default: return 0; |
9240 | | } |
9241 | | } |
9242 | | |
9243 | | // FastEmit functions for X86ISD::MULHRS. |
9244 | | |
9245 | 0 | unsigned fastEmit_X86ISD_MULHRS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9246 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
9247 | 0 | return 0; |
9248 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9249 | 0 | return fastEmitInst_rr(X86::VPMULHRSWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9250 | 0 | } |
9251 | 0 | if (0 (Subtarget->hasSSSE3() && 0 !Subtarget->hasAVX()0 )) { |
9252 | 0 | return fastEmitInst_rr(X86::PMULHRSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9253 | 0 | } |
9254 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
9255 | 0 | return fastEmitInst_rr(X86::VPMULHRSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9256 | 0 | } |
9257 | 0 | return 0; |
9258 | 0 | } |
9259 | | |
9260 | 0 | unsigned fastEmit_X86ISD_MULHRS_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9261 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
9262 | 0 | return 0; |
9263 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9264 | 0 | return fastEmitInst_rr(X86::VPMULHRSWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9265 | 0 | } |
9266 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
9267 | 0 | return fastEmitInst_rr(X86::VPMULHRSWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9268 | 0 | } |
9269 | 0 | return 0; |
9270 | 0 | } |
9271 | | |
9272 | 0 | unsigned fastEmit_X86ISD_MULHRS_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9273 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
9274 | 0 | return 0; |
9275 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9276 | 0 | return fastEmitInst_rr(X86::VPMULHRSWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9277 | 0 | } |
9278 | 0 | return 0; |
9279 | 0 | } |
9280 | | |
9281 | | unsigned fastEmit_X86ISD_MULHRS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9282 | | switch (VT.SimpleTy) { |
9283 | | case MVT::v8i16: return fastEmit_X86ISD_MULHRS_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9284 | | case MVT::v16i16: return fastEmit_X86ISD_MULHRS_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9285 | | case MVT::v32i16: return fastEmit_X86ISD_MULHRS_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9286 | | default: return 0; |
9287 | | } |
9288 | | } |
9289 | | |
9290 | | // FastEmit functions for X86ISD::MULTISHIFT. |
9291 | | |
9292 | 0 | unsigned fastEmit_X86ISD_MULTISHIFT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9293 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
9294 | 0 | return 0; |
9295 | 0 | if (0 (Subtarget->hasVBMI()) && 0 (Subtarget->hasVLX())0 ) { |
9296 | 0 | return fastEmitInst_rr(X86::VPMULTISHIFTQBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9297 | 0 | } |
9298 | 0 | return 0; |
9299 | 0 | } |
9300 | | |
9301 | 0 | unsigned fastEmit_X86ISD_MULTISHIFT_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9302 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
9303 | 0 | return 0; |
9304 | 0 | if (0 (Subtarget->hasVBMI()) && 0 (Subtarget->hasVLX())0 ) { |
9305 | 0 | return fastEmitInst_rr(X86::VPMULTISHIFTQBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9306 | 0 | } |
9307 | 0 | return 0; |
9308 | 0 | } |
9309 | | |
9310 | 0 | unsigned fastEmit_X86ISD_MULTISHIFT_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9311 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
9312 | 0 | return 0; |
9313 | 0 | if (0 (Subtarget->hasVBMI())0 ) { |
9314 | 0 | return fastEmitInst_rr(X86::VPMULTISHIFTQBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9315 | 0 | } |
9316 | 0 | return 0; |
9317 | 0 | } |
9318 | | |
9319 | | unsigned fastEmit_X86ISD_MULTISHIFT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9320 | | switch (VT.SimpleTy) { |
9321 | | case MVT::v16i8: return fastEmit_X86ISD_MULTISHIFT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9322 | | case MVT::v32i8: return fastEmit_X86ISD_MULTISHIFT_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9323 | | case MVT::v64i8: return fastEmit_X86ISD_MULTISHIFT_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9324 | | default: return 0; |
9325 | | } |
9326 | | } |
9327 | | |
9328 | | // FastEmit functions for X86ISD::PACKSS. |
9329 | | |
9330 | 0 | unsigned fastEmit_X86ISD_PACKSS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9331 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
9332 | 0 | return 0; |
9333 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9334 | 0 | return fastEmitInst_rr(X86::VPACKSSWBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9335 | 0 | } |
9336 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
9337 | 0 | return fastEmitInst_rr(X86::PACKSSWBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9338 | 0 | } |
9339 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
9340 | 0 | return fastEmitInst_rr(X86::VPACKSSWBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9341 | 0 | } |
9342 | 0 | return 0; |
9343 | 0 | } |
9344 | | |
9345 | 0 | unsigned fastEmit_X86ISD_PACKSS_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9346 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
9347 | 0 | return 0; |
9348 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9349 | 0 | return fastEmitInst_rr(X86::VPACKSSWBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9350 | 0 | } |
9351 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
9352 | 0 | return fastEmitInst_rr(X86::VPACKSSWBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9353 | 0 | } |
9354 | 0 | return 0; |
9355 | 0 | } |
9356 | | |
9357 | 0 | unsigned fastEmit_X86ISD_PACKSS_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9358 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
9359 | 0 | return 0; |
9360 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9361 | 0 | return fastEmitInst_rr(X86::VPACKSSWBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9362 | 0 | } |
9363 | 0 | return 0; |
9364 | 0 | } |
9365 | | |
9366 | 0 | unsigned fastEmit_X86ISD_PACKSS_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9367 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
9368 | 0 | return 0; |
9369 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9370 | 0 | return fastEmitInst_rr(X86::VPACKSSDWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9371 | 0 | } |
9372 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
9373 | 0 | return fastEmitInst_rr(X86::PACKSSDWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9374 | 0 | } |
9375 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
9376 | 0 | return fastEmitInst_rr(X86::VPACKSSDWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9377 | 0 | } |
9378 | 0 | return 0; |
9379 | 0 | } |
9380 | | |
9381 | 0 | unsigned fastEmit_X86ISD_PACKSS_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9382 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
9383 | 0 | return 0; |
9384 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9385 | 0 | return fastEmitInst_rr(X86::VPACKSSDWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9386 | 0 | } |
9387 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
9388 | 0 | return fastEmitInst_rr(X86::VPACKSSDWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9389 | 0 | } |
9390 | 0 | return 0; |
9391 | 0 | } |
9392 | | |
9393 | 0 | unsigned fastEmit_X86ISD_PACKSS_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9394 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
9395 | 0 | return 0; |
9396 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9397 | 0 | return fastEmitInst_rr(X86::VPACKSSDWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9398 | 0 | } |
9399 | 0 | return 0; |
9400 | 0 | } |
9401 | | |
9402 | | unsigned fastEmit_X86ISD_PACKSS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9403 | | switch (VT.SimpleTy) { |
9404 | | case MVT::v8i16: return fastEmit_X86ISD_PACKSS_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9405 | | case MVT::v16i16: return fastEmit_X86ISD_PACKSS_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9406 | | case MVT::v32i16: return fastEmit_X86ISD_PACKSS_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9407 | | case MVT::v4i32: return fastEmit_X86ISD_PACKSS_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9408 | | case MVT::v8i32: return fastEmit_X86ISD_PACKSS_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9409 | | case MVT::v16i32: return fastEmit_X86ISD_PACKSS_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9410 | | default: return 0; |
9411 | | } |
9412 | | } |
9413 | | |
9414 | | // FastEmit functions for X86ISD::PACKUS. |
9415 | | |
9416 | 0 | unsigned fastEmit_X86ISD_PACKUS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9417 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
9418 | 0 | return 0; |
9419 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9420 | 0 | return fastEmitInst_rr(X86::VPACKUSWBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9421 | 0 | } |
9422 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
9423 | 0 | return fastEmitInst_rr(X86::PACKUSWBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9424 | 0 | } |
9425 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
9426 | 0 | return fastEmitInst_rr(X86::VPACKUSWBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9427 | 0 | } |
9428 | 0 | return 0; |
9429 | 0 | } |
9430 | | |
9431 | 0 | unsigned fastEmit_X86ISD_PACKUS_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9432 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
9433 | 0 | return 0; |
9434 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9435 | 0 | return fastEmitInst_rr(X86::VPACKUSWBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9436 | 0 | } |
9437 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
9438 | 0 | return fastEmitInst_rr(X86::VPACKUSWBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9439 | 0 | } |
9440 | 0 | return 0; |
9441 | 0 | } |
9442 | | |
9443 | 0 | unsigned fastEmit_X86ISD_PACKUS_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9444 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
9445 | 0 | return 0; |
9446 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9447 | 0 | return fastEmitInst_rr(X86::VPACKUSWBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9448 | 0 | } |
9449 | 0 | return 0; |
9450 | 0 | } |
9451 | | |
9452 | 0 | unsigned fastEmit_X86ISD_PACKUS_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9453 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
9454 | 0 | return 0; |
9455 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9456 | 0 | return fastEmitInst_rr(X86::VPACKUSDWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9457 | 0 | } |
9458 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
9459 | 0 | return fastEmitInst_rr(X86::PACKUSDWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9460 | 0 | } |
9461 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
9462 | 0 | return fastEmitInst_rr(X86::VPACKUSDWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9463 | 0 | } |
9464 | 0 | return 0; |
9465 | 0 | } |
9466 | | |
9467 | 0 | unsigned fastEmit_X86ISD_PACKUS_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9468 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
9469 | 0 | return 0; |
9470 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9471 | 0 | return fastEmitInst_rr(X86::VPACKUSDWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9472 | 0 | } |
9473 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
9474 | 0 | return fastEmitInst_rr(X86::VPACKUSDWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9475 | 0 | } |
9476 | 0 | return 0; |
9477 | 0 | } |
9478 | | |
9479 | 0 | unsigned fastEmit_X86ISD_PACKUS_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9480 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
9481 | 0 | return 0; |
9482 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9483 | 0 | return fastEmitInst_rr(X86::VPACKUSDWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9484 | 0 | } |
9485 | 0 | return 0; |
9486 | 0 | } |
9487 | | |
9488 | | unsigned fastEmit_X86ISD_PACKUS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9489 | | switch (VT.SimpleTy) { |
9490 | | case MVT::v8i16: return fastEmit_X86ISD_PACKUS_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9491 | | case MVT::v16i16: return fastEmit_X86ISD_PACKUS_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9492 | | case MVT::v32i16: return fastEmit_X86ISD_PACKUS_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9493 | | case MVT::v4i32: return fastEmit_X86ISD_PACKUS_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9494 | | case MVT::v8i32: return fastEmit_X86ISD_PACKUS_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9495 | | case MVT::v16i32: return fastEmit_X86ISD_PACKUS_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9496 | | default: return 0; |
9497 | | } |
9498 | | } |
9499 | | |
9500 | | // FastEmit functions for X86ISD::PCMPEQ. |
9501 | | |
9502 | 0 | unsigned fastEmit_X86ISD_PCMPEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9503 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
9504 | 0 | return 0; |
9505 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
9506 | 0 | return fastEmitInst_rr(X86::PCMPEQBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9507 | 0 | } |
9508 | 0 | if (0 (Subtarget->hasAVX()) && 0 (true)0 ) { |
9509 | 0 | return fastEmitInst_rr(X86::VPCMPEQBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9510 | 0 | } |
9511 | 0 | return 0; |
9512 | 0 | } |
9513 | | |
9514 | 0 | unsigned fastEmit_X86ISD_PCMPEQ_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9515 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
9516 | 0 | return 0; |
9517 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (true)0 ) { |
9518 | 0 | return fastEmitInst_rr(X86::VPCMPEQBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9519 | 0 | } |
9520 | 0 | return 0; |
9521 | 0 | } |
9522 | | |
9523 | 0 | unsigned fastEmit_X86ISD_PCMPEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9524 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
9525 | 0 | return 0; |
9526 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
9527 | 0 | return fastEmitInst_rr(X86::PCMPEQWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9528 | 0 | } |
9529 | 0 | if (0 (Subtarget->hasAVX()) && 0 (true)0 ) { |
9530 | 0 | return fastEmitInst_rr(X86::VPCMPEQWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9531 | 0 | } |
9532 | 0 | return 0; |
9533 | 0 | } |
9534 | | |
9535 | 0 | unsigned fastEmit_X86ISD_PCMPEQ_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9536 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
9537 | 0 | return 0; |
9538 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (true)0 ) { |
9539 | 0 | return fastEmitInst_rr(X86::VPCMPEQWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9540 | 0 | } |
9541 | 0 | return 0; |
9542 | 0 | } |
9543 | | |
9544 | 0 | unsigned fastEmit_X86ISD_PCMPEQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9545 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
9546 | 0 | return 0; |
9547 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
9548 | 0 | return fastEmitInst_rr(X86::PCMPEQDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9549 | 0 | } |
9550 | 0 | if (0 (Subtarget->hasAVX()) && 0 (true)0 ) { |
9551 | 0 | return fastEmitInst_rr(X86::VPCMPEQDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9552 | 0 | } |
9553 | 0 | return 0; |
9554 | 0 | } |
9555 | | |
9556 | 0 | unsigned fastEmit_X86ISD_PCMPEQ_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9557 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
9558 | 0 | return 0; |
9559 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (true)0 ) { |
9560 | 0 | return fastEmitInst_rr(X86::VPCMPEQDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9561 | 0 | } |
9562 | 0 | return 0; |
9563 | 0 | } |
9564 | | |
9565 | 0 | unsigned fastEmit_X86ISD_PCMPEQ_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9566 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
9567 | 0 | return 0; |
9568 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
9569 | 0 | return fastEmitInst_rr(X86::PCMPEQQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9570 | 0 | } |
9571 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
9572 | 0 | return fastEmitInst_rr(X86::VPCMPEQQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9573 | 0 | } |
9574 | 0 | return 0; |
9575 | 0 | } |
9576 | | |
9577 | 0 | unsigned fastEmit_X86ISD_PCMPEQ_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9578 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
9579 | 0 | return 0; |
9580 | 0 | if (0 (Subtarget->hasAVX2())0 ) { |
9581 | 0 | return fastEmitInst_rr(X86::VPCMPEQQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9582 | 0 | } |
9583 | 0 | return 0; |
9584 | 0 | } |
9585 | | |
9586 | | unsigned fastEmit_X86ISD_PCMPEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9587 | | switch (VT.SimpleTy) { |
9588 | | case MVT::v16i8: return fastEmit_X86ISD_PCMPEQ_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9589 | | case MVT::v32i8: return fastEmit_X86ISD_PCMPEQ_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9590 | | case MVT::v8i16: return fastEmit_X86ISD_PCMPEQ_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9591 | | case MVT::v16i16: return fastEmit_X86ISD_PCMPEQ_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9592 | | case MVT::v4i32: return fastEmit_X86ISD_PCMPEQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9593 | | case MVT::v8i32: return fastEmit_X86ISD_PCMPEQ_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9594 | | case MVT::v2i64: return fastEmit_X86ISD_PCMPEQ_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9595 | | case MVT::v4i64: return fastEmit_X86ISD_PCMPEQ_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9596 | | default: return 0; |
9597 | | } |
9598 | | } |
9599 | | |
9600 | | // FastEmit functions for X86ISD::PCMPEQM. |
9601 | | |
9602 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9603 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
9604 | 0 | return 0; |
9605 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9606 | 0 | return fastEmitInst_rr(X86::VPCMPEQBZ128rr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9607 | 0 | } |
9608 | 0 | return 0; |
9609 | 0 | } |
9610 | | |
9611 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9612 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
9613 | 0 | return 0; |
9614 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9615 | 0 | return fastEmitInst_rr(X86::VPCMPEQBZ256rr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9616 | 0 | } |
9617 | 0 | return 0; |
9618 | 0 | } |
9619 | | |
9620 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9621 | 0 | if (RetVT.SimpleTy != MVT::v64i1) |
9622 | 0 | return 0; |
9623 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9624 | 0 | return fastEmitInst_rr(X86::VPCMPEQBZrr, &X86::VK64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9625 | 0 | } |
9626 | 0 | return 0; |
9627 | 0 | } |
9628 | | |
9629 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9630 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
9631 | 0 | return 0; |
9632 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9633 | 0 | return fastEmitInst_rr(X86::VPCMPEQWZ128rr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9634 | 0 | } |
9635 | 0 | return 0; |
9636 | 0 | } |
9637 | | |
9638 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9639 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
9640 | 0 | return 0; |
9641 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9642 | 0 | return fastEmitInst_rr(X86::VPCMPEQWZ256rr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9643 | 0 | } |
9644 | 0 | return 0; |
9645 | 0 | } |
9646 | | |
9647 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9648 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
9649 | 0 | return 0; |
9650 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9651 | 0 | return fastEmitInst_rr(X86::VPCMPEQWZrr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9652 | 0 | } |
9653 | 0 | return 0; |
9654 | 0 | } |
9655 | | |
9656 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9657 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
9658 | 0 | return 0; |
9659 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
9660 | 0 | return fastEmitInst_rr(X86::VPCMPEQDZ128rr, &X86::VK4RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9661 | 0 | } |
9662 | 0 | return 0; |
9663 | 0 | } |
9664 | | |
9665 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9666 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
9667 | 0 | return 0; |
9668 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
9669 | 0 | return fastEmitInst_rr(X86::VPCMPEQDZ256rr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9670 | 0 | } |
9671 | 0 | return 0; |
9672 | 0 | } |
9673 | | |
9674 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9675 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
9676 | 0 | return 0; |
9677 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
9678 | 0 | return fastEmitInst_rr(X86::VPCMPEQDZrr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9679 | 0 | } |
9680 | 0 | return 0; |
9681 | 0 | } |
9682 | | |
9683 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9684 | 0 | if (RetVT.SimpleTy != MVT::v2i1) |
9685 | 0 | return 0; |
9686 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
9687 | 0 | return fastEmitInst_rr(X86::VPCMPEQQZ128rr, &X86::VK2RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9688 | 0 | } |
9689 | 0 | return 0; |
9690 | 0 | } |
9691 | | |
9692 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9693 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
9694 | 0 | return 0; |
9695 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
9696 | 0 | return fastEmitInst_rr(X86::VPCMPEQQZ256rr, &X86::VK4RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9697 | 0 | } |
9698 | 0 | return 0; |
9699 | 0 | } |
9700 | | |
9701 | 0 | unsigned fastEmit_X86ISD_PCMPEQM_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9702 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
9703 | 0 | return 0; |
9704 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
9705 | 0 | return fastEmitInst_rr(X86::VPCMPEQQZrr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9706 | 0 | } |
9707 | 0 | return 0; |
9708 | 0 | } |
9709 | | |
9710 | | unsigned fastEmit_X86ISD_PCMPEQM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9711 | | switch (VT.SimpleTy) { |
9712 | | case MVT::v16i8: return fastEmit_X86ISD_PCMPEQM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9713 | | case MVT::v32i8: return fastEmit_X86ISD_PCMPEQM_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9714 | | case MVT::v64i8: return fastEmit_X86ISD_PCMPEQM_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9715 | | case MVT::v8i16: return fastEmit_X86ISD_PCMPEQM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9716 | | case MVT::v16i16: return fastEmit_X86ISD_PCMPEQM_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9717 | | case MVT::v32i16: return fastEmit_X86ISD_PCMPEQM_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9718 | | case MVT::v4i32: return fastEmit_X86ISD_PCMPEQM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9719 | | case MVT::v8i32: return fastEmit_X86ISD_PCMPEQM_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9720 | | case MVT::v16i32: return fastEmit_X86ISD_PCMPEQM_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9721 | | case MVT::v2i64: return fastEmit_X86ISD_PCMPEQM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9722 | | case MVT::v4i64: return fastEmit_X86ISD_PCMPEQM_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9723 | | case MVT::v8i64: return fastEmit_X86ISD_PCMPEQM_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9724 | | default: return 0; |
9725 | | } |
9726 | | } |
9727 | | |
9728 | | // FastEmit functions for X86ISD::PCMPGT. |
9729 | | |
9730 | 0 | unsigned fastEmit_X86ISD_PCMPGT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9731 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
9732 | 0 | return 0; |
9733 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
9734 | 0 | return fastEmitInst_rr(X86::PCMPGTBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9735 | 0 | } |
9736 | 0 | if (0 (Subtarget->hasAVX()) && 0 (true)0 ) { |
9737 | 0 | return fastEmitInst_rr(X86::VPCMPGTBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9738 | 0 | } |
9739 | 0 | return 0; |
9740 | 0 | } |
9741 | | |
9742 | 0 | unsigned fastEmit_X86ISD_PCMPGT_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9743 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
9744 | 0 | return 0; |
9745 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (true)0 ) { |
9746 | 0 | return fastEmitInst_rr(X86::VPCMPGTBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9747 | 0 | } |
9748 | 0 | return 0; |
9749 | 0 | } |
9750 | | |
9751 | 0 | unsigned fastEmit_X86ISD_PCMPGT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9752 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
9753 | 0 | return 0; |
9754 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
9755 | 0 | return fastEmitInst_rr(X86::PCMPGTWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9756 | 0 | } |
9757 | 0 | if (0 (Subtarget->hasAVX()) && 0 (true)0 ) { |
9758 | 0 | return fastEmitInst_rr(X86::VPCMPGTWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9759 | 0 | } |
9760 | 0 | return 0; |
9761 | 0 | } |
9762 | | |
9763 | 0 | unsigned fastEmit_X86ISD_PCMPGT_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9764 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
9765 | 0 | return 0; |
9766 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (true)0 ) { |
9767 | 0 | return fastEmitInst_rr(X86::VPCMPGTWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9768 | 0 | } |
9769 | 0 | return 0; |
9770 | 0 | } |
9771 | | |
9772 | 0 | unsigned fastEmit_X86ISD_PCMPGT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9773 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
9774 | 0 | return 0; |
9775 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
9776 | 0 | return fastEmitInst_rr(X86::PCMPGTDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9777 | 0 | } |
9778 | 0 | if (0 (Subtarget->hasAVX()) && 0 (true)0 ) { |
9779 | 0 | return fastEmitInst_rr(X86::VPCMPGTDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9780 | 0 | } |
9781 | 0 | return 0; |
9782 | 0 | } |
9783 | | |
9784 | 0 | unsigned fastEmit_X86ISD_PCMPGT_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9785 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
9786 | 0 | return 0; |
9787 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (true)0 ) { |
9788 | 0 | return fastEmitInst_rr(X86::VPCMPGTDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9789 | 0 | } |
9790 | 0 | return 0; |
9791 | 0 | } |
9792 | | |
9793 | 0 | unsigned fastEmit_X86ISD_PCMPGT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9794 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
9795 | 0 | return 0; |
9796 | 0 | if (0 (Subtarget->hasSSE42() && 0 !Subtarget->hasAVX()0 )) { |
9797 | 0 | return fastEmitInst_rr(X86::PCMPGTQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9798 | 0 | } |
9799 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
9800 | 0 | return fastEmitInst_rr(X86::VPCMPGTQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9801 | 0 | } |
9802 | 0 | return 0; |
9803 | 0 | } |
9804 | | |
9805 | 0 | unsigned fastEmit_X86ISD_PCMPGT_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9806 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
9807 | 0 | return 0; |
9808 | 0 | if (0 (Subtarget->hasAVX2())0 ) { |
9809 | 0 | return fastEmitInst_rr(X86::VPCMPGTQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9810 | 0 | } |
9811 | 0 | return 0; |
9812 | 0 | } |
9813 | | |
9814 | | unsigned fastEmit_X86ISD_PCMPGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9815 | | switch (VT.SimpleTy) { |
9816 | | case MVT::v16i8: return fastEmit_X86ISD_PCMPGT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9817 | | case MVT::v32i8: return fastEmit_X86ISD_PCMPGT_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9818 | | case MVT::v8i16: return fastEmit_X86ISD_PCMPGT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9819 | | case MVT::v16i16: return fastEmit_X86ISD_PCMPGT_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9820 | | case MVT::v4i32: return fastEmit_X86ISD_PCMPGT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9821 | | case MVT::v8i32: return fastEmit_X86ISD_PCMPGT_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9822 | | case MVT::v2i64: return fastEmit_X86ISD_PCMPGT_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9823 | | case MVT::v4i64: return fastEmit_X86ISD_PCMPGT_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9824 | | default: return 0; |
9825 | | } |
9826 | | } |
9827 | | |
9828 | | // FastEmit functions for X86ISD::PCMPGTM. |
9829 | | |
9830 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9831 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
9832 | 0 | return 0; |
9833 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9834 | 0 | return fastEmitInst_rr(X86::VPCMPGTBZ128rr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9835 | 0 | } |
9836 | 0 | return 0; |
9837 | 0 | } |
9838 | | |
9839 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9840 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
9841 | 0 | return 0; |
9842 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9843 | 0 | return fastEmitInst_rr(X86::VPCMPGTBZ256rr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9844 | 0 | } |
9845 | 0 | return 0; |
9846 | 0 | } |
9847 | | |
9848 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9849 | 0 | if (RetVT.SimpleTy != MVT::v64i1) |
9850 | 0 | return 0; |
9851 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9852 | 0 | return fastEmitInst_rr(X86::VPCMPGTBZrr, &X86::VK64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9853 | 0 | } |
9854 | 0 | return 0; |
9855 | 0 | } |
9856 | | |
9857 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9858 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
9859 | 0 | return 0; |
9860 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9861 | 0 | return fastEmitInst_rr(X86::VPCMPGTWZ128rr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9862 | 0 | } |
9863 | 0 | return 0; |
9864 | 0 | } |
9865 | | |
9866 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9867 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
9868 | 0 | return 0; |
9869 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
9870 | 0 | return fastEmitInst_rr(X86::VPCMPGTWZ256rr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9871 | 0 | } |
9872 | 0 | return 0; |
9873 | 0 | } |
9874 | | |
9875 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9876 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
9877 | 0 | return 0; |
9878 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
9879 | 0 | return fastEmitInst_rr(X86::VPCMPGTWZrr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9880 | 0 | } |
9881 | 0 | return 0; |
9882 | 0 | } |
9883 | | |
9884 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9885 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
9886 | 0 | return 0; |
9887 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
9888 | 0 | return fastEmitInst_rr(X86::VPCMPGTDZ128rr, &X86::VK4RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9889 | 0 | } |
9890 | 0 | return 0; |
9891 | 0 | } |
9892 | | |
9893 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9894 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
9895 | 0 | return 0; |
9896 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
9897 | 0 | return fastEmitInst_rr(X86::VPCMPGTDZ256rr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9898 | 0 | } |
9899 | 0 | return 0; |
9900 | 0 | } |
9901 | | |
9902 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9903 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
9904 | 0 | return 0; |
9905 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
9906 | 0 | return fastEmitInst_rr(X86::VPCMPGTDZrr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9907 | 0 | } |
9908 | 0 | return 0; |
9909 | 0 | } |
9910 | | |
9911 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9912 | 0 | if (RetVT.SimpleTy != MVT::v2i1) |
9913 | 0 | return 0; |
9914 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
9915 | 0 | return fastEmitInst_rr(X86::VPCMPGTQZ128rr, &X86::VK2RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9916 | 0 | } |
9917 | 0 | return 0; |
9918 | 0 | } |
9919 | | |
9920 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9921 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
9922 | 0 | return 0; |
9923 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
9924 | 0 | return fastEmitInst_rr(X86::VPCMPGTQZ256rr, &X86::VK4RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9925 | 0 | } |
9926 | 0 | return 0; |
9927 | 0 | } |
9928 | | |
9929 | 0 | unsigned fastEmit_X86ISD_PCMPGTM_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9930 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
9931 | 0 | return 0; |
9932 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
9933 | 0 | return fastEmitInst_rr(X86::VPCMPGTQZrr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9934 | 0 | } |
9935 | 0 | return 0; |
9936 | 0 | } |
9937 | | |
9938 | | unsigned fastEmit_X86ISD_PCMPGTM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9939 | | switch (VT.SimpleTy) { |
9940 | | case MVT::v16i8: return fastEmit_X86ISD_PCMPGTM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9941 | | case MVT::v32i8: return fastEmit_X86ISD_PCMPGTM_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9942 | | case MVT::v64i8: return fastEmit_X86ISD_PCMPGTM_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9943 | | case MVT::v8i16: return fastEmit_X86ISD_PCMPGTM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9944 | | case MVT::v16i16: return fastEmit_X86ISD_PCMPGTM_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9945 | | case MVT::v32i16: return fastEmit_X86ISD_PCMPGTM_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9946 | | case MVT::v4i32: return fastEmit_X86ISD_PCMPGTM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9947 | | case MVT::v8i32: return fastEmit_X86ISD_PCMPGTM_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9948 | | case MVT::v16i32: return fastEmit_X86ISD_PCMPGTM_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9949 | | case MVT::v2i64: return fastEmit_X86ISD_PCMPGTM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9950 | | case MVT::v4i64: return fastEmit_X86ISD_PCMPGTM_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9951 | | case MVT::v8i64: return fastEmit_X86ISD_PCMPGTM_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9952 | | default: return 0; |
9953 | | } |
9954 | | } |
9955 | | |
9956 | | // FastEmit functions for X86ISD::PMULDQ. |
9957 | | |
9958 | 0 | unsigned fastEmit_X86ISD_PMULDQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9959 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
9960 | 0 | return 0; |
9961 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
9962 | 0 | return fastEmitInst_rr(X86::VPMULDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9963 | 0 | } |
9964 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
9965 | 0 | return fastEmitInst_rr(X86::PMULDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9966 | 0 | } |
9967 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
9968 | 0 | return fastEmitInst_rr(X86::VPMULDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9969 | 0 | } |
9970 | 0 | return 0; |
9971 | 0 | } |
9972 | | |
9973 | 0 | unsigned fastEmit_X86ISD_PMULDQ_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9974 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
9975 | 0 | return 0; |
9976 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
9977 | 0 | return fastEmitInst_rr(X86::VPMULDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9978 | 0 | } |
9979 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
9980 | 0 | return fastEmitInst_rr(X86::VPMULDQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9981 | 0 | } |
9982 | 0 | return 0; |
9983 | 0 | } |
9984 | | |
9985 | 0 | unsigned fastEmit_X86ISD_PMULDQ_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9986 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
9987 | 0 | return 0; |
9988 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
9989 | 0 | return fastEmitInst_rr(X86::VPMULDQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
9990 | 0 | } |
9991 | 0 | return 0; |
9992 | 0 | } |
9993 | | |
9994 | | unsigned fastEmit_X86ISD_PMULDQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
9995 | | switch (VT.SimpleTy) { |
9996 | | case MVT::v4i32: return fastEmit_X86ISD_PMULDQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9997 | | case MVT::v8i32: return fastEmit_X86ISD_PMULDQ_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9998 | | case MVT::v16i32: return fastEmit_X86ISD_PMULDQ_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
9999 | | default: return 0; |
10000 | | } |
10001 | | } |
10002 | | |
10003 | | // FastEmit functions for X86ISD::PMULUDQ. |
10004 | | |
10005 | 0 | unsigned fastEmit_X86ISD_PMULUDQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10006 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
10007 | 0 | return 0; |
10008 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10009 | 0 | return fastEmitInst_rr(X86::VPMULUDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10010 | 0 | } |
10011 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10012 | 0 | return fastEmitInst_rr(X86::PMULUDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10013 | 0 | } |
10014 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
10015 | 0 | return fastEmitInst_rr(X86::VPMULUDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10016 | 0 | } |
10017 | 0 | return 0; |
10018 | 0 | } |
10019 | | |
10020 | 0 | unsigned fastEmit_X86ISD_PMULUDQ_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10021 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
10022 | 0 | return 0; |
10023 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10024 | 0 | return fastEmitInst_rr(X86::VPMULUDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10025 | 0 | } |
10026 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
10027 | 0 | return fastEmitInst_rr(X86::VPMULUDQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10028 | 0 | } |
10029 | 0 | return 0; |
10030 | 0 | } |
10031 | | |
10032 | 0 | unsigned fastEmit_X86ISD_PMULUDQ_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10033 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
10034 | 0 | return 0; |
10035 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
10036 | 0 | return fastEmitInst_rr(X86::VPMULUDQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10037 | 0 | } |
10038 | 0 | return 0; |
10039 | 0 | } |
10040 | | |
10041 | | unsigned fastEmit_X86ISD_PMULUDQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10042 | | switch (VT.SimpleTy) { |
10043 | | case MVT::v4i32: return fastEmit_X86ISD_PMULUDQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10044 | | case MVT::v8i32: return fastEmit_X86ISD_PMULUDQ_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10045 | | case MVT::v16i32: return fastEmit_X86ISD_PMULUDQ_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10046 | | default: return 0; |
10047 | | } |
10048 | | } |
10049 | | |
10050 | | // FastEmit functions for X86ISD::PSADBW. |
10051 | | |
10052 | 0 | unsigned fastEmit_X86ISD_PSADBW_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10053 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
10054 | 0 | return 0; |
10055 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10056 | 0 | return fastEmitInst_rr(X86::VPSADBWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10057 | 0 | } |
10058 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10059 | 0 | return fastEmitInst_rr(X86::PSADBWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10060 | 0 | } |
10061 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10062 | 0 | return fastEmitInst_rr(X86::VPSADBWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10063 | 0 | } |
10064 | 0 | return 0; |
10065 | 0 | } |
10066 | | |
10067 | 0 | unsigned fastEmit_X86ISD_PSADBW_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10068 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
10069 | 0 | return 0; |
10070 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10071 | 0 | return fastEmitInst_rr(X86::VPSADBWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10072 | 0 | } |
10073 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10074 | 0 | return fastEmitInst_rr(X86::VPSADBWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10075 | 0 | } |
10076 | 0 | return 0; |
10077 | 0 | } |
10078 | | |
10079 | 0 | unsigned fastEmit_X86ISD_PSADBW_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10080 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
10081 | 0 | return 0; |
10082 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10083 | 0 | return fastEmitInst_rr(X86::VPSADBWZ512rr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10084 | 0 | } |
10085 | 0 | return 0; |
10086 | 0 | } |
10087 | | |
10088 | | unsigned fastEmit_X86ISD_PSADBW_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10089 | | switch (VT.SimpleTy) { |
10090 | | case MVT::v16i8: return fastEmit_X86ISD_PSADBW_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10091 | | case MVT::v32i8: return fastEmit_X86ISD_PSADBW_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10092 | | case MVT::v64i8: return fastEmit_X86ISD_PSADBW_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10093 | | default: return 0; |
10094 | | } |
10095 | | } |
10096 | | |
10097 | | // FastEmit functions for X86ISD::PSHUFB. |
10098 | | |
10099 | 0 | unsigned fastEmit_X86ISD_PSHUFB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10100 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10101 | 0 | return 0; |
10102 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10103 | 0 | return fastEmitInst_rr(X86::VPSHUFBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10104 | 0 | } |
10105 | 0 | if (0 (Subtarget->hasSSSE3() && 0 !Subtarget->hasAVX()0 )) { |
10106 | 0 | return fastEmitInst_rr(X86::PSHUFBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10107 | 0 | } |
10108 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10109 | 0 | return fastEmitInst_rr(X86::VPSHUFBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10110 | 0 | } |
10111 | 0 | return 0; |
10112 | 0 | } |
10113 | | |
10114 | 0 | unsigned fastEmit_X86ISD_PSHUFB_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10115 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
10116 | 0 | return 0; |
10117 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10118 | 0 | return fastEmitInst_rr(X86::VPSHUFBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10119 | 0 | } |
10120 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10121 | 0 | return fastEmitInst_rr(X86::VPSHUFBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10122 | 0 | } |
10123 | 0 | return 0; |
10124 | 0 | } |
10125 | | |
10126 | 0 | unsigned fastEmit_X86ISD_PSHUFB_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10127 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
10128 | 0 | return 0; |
10129 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10130 | 0 | return fastEmitInst_rr(X86::VPSHUFBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10131 | 0 | } |
10132 | 0 | return 0; |
10133 | 0 | } |
10134 | | |
10135 | | unsigned fastEmit_X86ISD_PSHUFB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10136 | | switch (VT.SimpleTy) { |
10137 | | case MVT::v16i8: return fastEmit_X86ISD_PSHUFB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10138 | | case MVT::v32i8: return fastEmit_X86ISD_PSHUFB_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10139 | | case MVT::v64i8: return fastEmit_X86ISD_PSHUFB_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10140 | | default: return 0; |
10141 | | } |
10142 | | } |
10143 | | |
10144 | | // FastEmit functions for X86ISD::PTEST. |
10145 | | |
10146 | 0 | unsigned fastEmit_X86ISD_PTEST_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10147 | 0 | if (RetVT.SimpleTy != MVT::i32) |
10148 | 0 | return 0; |
10149 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
10150 | 0 | return fastEmitInst_rr(X86::PTESTrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10151 | 0 | } |
10152 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
10153 | 0 | return fastEmitInst_rr(X86::VPTESTrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10154 | 0 | } |
10155 | 0 | return 0; |
10156 | 0 | } |
10157 | | |
10158 | 0 | unsigned fastEmit_X86ISD_PTEST_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10159 | 0 | if (RetVT.SimpleTy != MVT::i32) |
10160 | 0 | return 0; |
10161 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
10162 | 0 | return fastEmitInst_rr(X86::VPTESTYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10163 | 0 | } |
10164 | 0 | return 0; |
10165 | 0 | } |
10166 | | |
10167 | | unsigned fastEmit_X86ISD_PTEST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10168 | | switch (VT.SimpleTy) { |
10169 | | case MVT::v2i64: return fastEmit_X86ISD_PTEST_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10170 | | case MVT::v4i64: return fastEmit_X86ISD_PTEST_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10171 | | default: return 0; |
10172 | | } |
10173 | | } |
10174 | | |
10175 | | // FastEmit functions for X86ISD::SUBS. |
10176 | | |
10177 | 0 | unsigned fastEmit_X86ISD_SUBS_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10178 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10179 | 0 | return 0; |
10180 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10181 | 0 | return fastEmitInst_rr(X86::VPSUBSBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10182 | 0 | } |
10183 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10184 | 0 | return fastEmitInst_rr(X86::PSUBSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10185 | 0 | } |
10186 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10187 | 0 | return fastEmitInst_rr(X86::VPSUBSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10188 | 0 | } |
10189 | 0 | return 0; |
10190 | 0 | } |
10191 | | |
10192 | 0 | unsigned fastEmit_X86ISD_SUBS_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10193 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
10194 | 0 | return 0; |
10195 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10196 | 0 | return fastEmitInst_rr(X86::VPSUBSBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10197 | 0 | } |
10198 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10199 | 0 | return fastEmitInst_rr(X86::VPSUBSBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10200 | 0 | } |
10201 | 0 | return 0; |
10202 | 0 | } |
10203 | | |
10204 | 0 | unsigned fastEmit_X86ISD_SUBS_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10205 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
10206 | 0 | return 0; |
10207 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10208 | 0 | return fastEmitInst_rr(X86::VPSUBSBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10209 | 0 | } |
10210 | 0 | return 0; |
10211 | 0 | } |
10212 | | |
10213 | 0 | unsigned fastEmit_X86ISD_SUBS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10214 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10215 | 0 | return 0; |
10216 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10217 | 0 | return fastEmitInst_rr(X86::VPSUBSWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10218 | 0 | } |
10219 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10220 | 0 | return fastEmitInst_rr(X86::PSUBSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10221 | 0 | } |
10222 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10223 | 0 | return fastEmitInst_rr(X86::VPSUBSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10224 | 0 | } |
10225 | 0 | return 0; |
10226 | 0 | } |
10227 | | |
10228 | 0 | unsigned fastEmit_X86ISD_SUBS_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10229 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
10230 | 0 | return 0; |
10231 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10232 | 0 | return fastEmitInst_rr(X86::VPSUBSWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10233 | 0 | } |
10234 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10235 | 0 | return fastEmitInst_rr(X86::VPSUBSWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10236 | 0 | } |
10237 | 0 | return 0; |
10238 | 0 | } |
10239 | | |
10240 | 0 | unsigned fastEmit_X86ISD_SUBS_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10241 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
10242 | 0 | return 0; |
10243 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10244 | 0 | return fastEmitInst_rr(X86::VPSUBSWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10245 | 0 | } |
10246 | 0 | return 0; |
10247 | 0 | } |
10248 | | |
10249 | | unsigned fastEmit_X86ISD_SUBS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10250 | | switch (VT.SimpleTy) { |
10251 | | case MVT::v16i8: return fastEmit_X86ISD_SUBS_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10252 | | case MVT::v32i8: return fastEmit_X86ISD_SUBS_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10253 | | case MVT::v64i8: return fastEmit_X86ISD_SUBS_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10254 | | case MVT::v8i16: return fastEmit_X86ISD_SUBS_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10255 | | case MVT::v16i16: return fastEmit_X86ISD_SUBS_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10256 | | case MVT::v32i16: return fastEmit_X86ISD_SUBS_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10257 | | default: return 0; |
10258 | | } |
10259 | | } |
10260 | | |
10261 | | // FastEmit functions for X86ISD::SUBUS. |
10262 | | |
10263 | 0 | unsigned fastEmit_X86ISD_SUBUS_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10264 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10265 | 0 | return 0; |
10266 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10267 | 0 | return fastEmitInst_rr(X86::VPSUBUSBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10268 | 0 | } |
10269 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10270 | 0 | return fastEmitInst_rr(X86::PSUBUSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10271 | 0 | } |
10272 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10273 | 0 | return fastEmitInst_rr(X86::VPSUBUSBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10274 | 0 | } |
10275 | 0 | return 0; |
10276 | 0 | } |
10277 | | |
10278 | 0 | unsigned fastEmit_X86ISD_SUBUS_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10279 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
10280 | 0 | return 0; |
10281 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10282 | 0 | return fastEmitInst_rr(X86::VPSUBUSBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10283 | 0 | } |
10284 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10285 | 0 | return fastEmitInst_rr(X86::VPSUBUSBYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10286 | 0 | } |
10287 | 0 | return 0; |
10288 | 0 | } |
10289 | | |
10290 | 0 | unsigned fastEmit_X86ISD_SUBUS_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10291 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
10292 | 0 | return 0; |
10293 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10294 | 0 | return fastEmitInst_rr(X86::VPSUBUSBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10295 | 0 | } |
10296 | 0 | return 0; |
10297 | 0 | } |
10298 | | |
10299 | 0 | unsigned fastEmit_X86ISD_SUBUS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10300 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10301 | 0 | return 0; |
10302 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10303 | 0 | return fastEmitInst_rr(X86::VPSUBUSWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10304 | 0 | } |
10305 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10306 | 0 | return fastEmitInst_rr(X86::PSUBUSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10307 | 0 | } |
10308 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10309 | 0 | return fastEmitInst_rr(X86::VPSUBUSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10310 | 0 | } |
10311 | 0 | return 0; |
10312 | 0 | } |
10313 | | |
10314 | 0 | unsigned fastEmit_X86ISD_SUBUS_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10315 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
10316 | 0 | return 0; |
10317 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10318 | 0 | return fastEmitInst_rr(X86::VPSUBUSWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10319 | 0 | } |
10320 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10321 | 0 | return fastEmitInst_rr(X86::VPSUBUSWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10322 | 0 | } |
10323 | 0 | return 0; |
10324 | 0 | } |
10325 | | |
10326 | 0 | unsigned fastEmit_X86ISD_SUBUS_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10327 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
10328 | 0 | return 0; |
10329 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10330 | 0 | return fastEmitInst_rr(X86::VPSUBUSWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10331 | 0 | } |
10332 | 0 | return 0; |
10333 | 0 | } |
10334 | | |
10335 | | unsigned fastEmit_X86ISD_SUBUS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10336 | | switch (VT.SimpleTy) { |
10337 | | case MVT::v16i8: return fastEmit_X86ISD_SUBUS_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10338 | | case MVT::v32i8: return fastEmit_X86ISD_SUBUS_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10339 | | case MVT::v64i8: return fastEmit_X86ISD_SUBUS_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10340 | | case MVT::v8i16: return fastEmit_X86ISD_SUBUS_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10341 | | case MVT::v16i16: return fastEmit_X86ISD_SUBUS_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10342 | | case MVT::v32i16: return fastEmit_X86ISD_SUBUS_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10343 | | default: return 0; |
10344 | | } |
10345 | | } |
10346 | | |
10347 | | // FastEmit functions for X86ISD::TESTM. |
10348 | | |
10349 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10350 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
10351 | 0 | return 0; |
10352 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10353 | 0 | return fastEmitInst_rr(X86::VPTESTMBZ128rr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10354 | 0 | } |
10355 | 0 | return 0; |
10356 | 0 | } |
10357 | | |
10358 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10359 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
10360 | 0 | return 0; |
10361 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10362 | 0 | return fastEmitInst_rr(X86::VPTESTMBZ256rr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10363 | 0 | } |
10364 | 0 | return 0; |
10365 | 0 | } |
10366 | | |
10367 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10368 | 0 | if (RetVT.SimpleTy != MVT::v64i1) |
10369 | 0 | return 0; |
10370 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10371 | 0 | return fastEmitInst_rr(X86::VPTESTMBZrr, &X86::VK64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10372 | 0 | } |
10373 | 0 | return 0; |
10374 | 0 | } |
10375 | | |
10376 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10377 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
10378 | 0 | return 0; |
10379 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10380 | 0 | return fastEmitInst_rr(X86::VPTESTMWZ128rr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10381 | 0 | } |
10382 | 0 | return 0; |
10383 | 0 | } |
10384 | | |
10385 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10386 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
10387 | 0 | return 0; |
10388 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10389 | 0 | return fastEmitInst_rr(X86::VPTESTMWZ256rr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10390 | 0 | } |
10391 | 0 | return 0; |
10392 | 0 | } |
10393 | | |
10394 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10395 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
10396 | 0 | return 0; |
10397 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10398 | 0 | return fastEmitInst_rr(X86::VPTESTMWZrr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10399 | 0 | } |
10400 | 0 | return 0; |
10401 | 0 | } |
10402 | | |
10403 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10404 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
10405 | 0 | return 0; |
10406 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10407 | 0 | return fastEmitInst_rr(X86::VPTESTMDZ128rr, &X86::VK4RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10408 | 0 | } |
10409 | 0 | return 0; |
10410 | 0 | } |
10411 | | |
10412 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10413 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
10414 | 0 | return 0; |
10415 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10416 | 0 | return fastEmitInst_rr(X86::VPTESTMDZ256rr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10417 | 0 | } |
10418 | 0 | return 0; |
10419 | 0 | } |
10420 | | |
10421 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10422 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
10423 | 0 | return 0; |
10424 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
10425 | 0 | return fastEmitInst_rr(X86::VPTESTMDZrr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10426 | 0 | } |
10427 | 0 | return 0; |
10428 | 0 | } |
10429 | | |
10430 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10431 | 0 | if (RetVT.SimpleTy != MVT::v2i1) |
10432 | 0 | return 0; |
10433 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10434 | 0 | return fastEmitInst_rr(X86::VPTESTMQZ128rr, &X86::VK2RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10435 | 0 | } |
10436 | 0 | return 0; |
10437 | 0 | } |
10438 | | |
10439 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10440 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
10441 | 0 | return 0; |
10442 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10443 | 0 | return fastEmitInst_rr(X86::VPTESTMQZ256rr, &X86::VK4RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10444 | 0 | } |
10445 | 0 | return 0; |
10446 | 0 | } |
10447 | | |
10448 | 0 | unsigned fastEmit_X86ISD_TESTM_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10449 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
10450 | 0 | return 0; |
10451 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
10452 | 0 | return fastEmitInst_rr(X86::VPTESTMQZrr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10453 | 0 | } |
10454 | 0 | return 0; |
10455 | 0 | } |
10456 | | |
10457 | | unsigned fastEmit_X86ISD_TESTM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10458 | | switch (VT.SimpleTy) { |
10459 | | case MVT::v16i8: return fastEmit_X86ISD_TESTM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10460 | | case MVT::v32i8: return fastEmit_X86ISD_TESTM_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10461 | | case MVT::v64i8: return fastEmit_X86ISD_TESTM_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10462 | | case MVT::v8i16: return fastEmit_X86ISD_TESTM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10463 | | case MVT::v16i16: return fastEmit_X86ISD_TESTM_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10464 | | case MVT::v32i16: return fastEmit_X86ISD_TESTM_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10465 | | case MVT::v4i32: return fastEmit_X86ISD_TESTM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10466 | | case MVT::v8i32: return fastEmit_X86ISD_TESTM_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10467 | | case MVT::v16i32: return fastEmit_X86ISD_TESTM_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10468 | | case MVT::v2i64: return fastEmit_X86ISD_TESTM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10469 | | case MVT::v4i64: return fastEmit_X86ISD_TESTM_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10470 | | case MVT::v8i64: return fastEmit_X86ISD_TESTM_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10471 | | default: return 0; |
10472 | | } |
10473 | | } |
10474 | | |
10475 | | // FastEmit functions for X86ISD::TESTNM. |
10476 | | |
10477 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10478 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
10479 | 0 | return 0; |
10480 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10481 | 0 | return fastEmitInst_rr(X86::VPTESTNMBZ128rr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10482 | 0 | } |
10483 | 0 | return 0; |
10484 | 0 | } |
10485 | | |
10486 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10487 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
10488 | 0 | return 0; |
10489 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10490 | 0 | return fastEmitInst_rr(X86::VPTESTNMBZ256rr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10491 | 0 | } |
10492 | 0 | return 0; |
10493 | 0 | } |
10494 | | |
10495 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10496 | 0 | if (RetVT.SimpleTy != MVT::v64i1) |
10497 | 0 | return 0; |
10498 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10499 | 0 | return fastEmitInst_rr(X86::VPTESTNMBZrr, &X86::VK64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10500 | 0 | } |
10501 | 0 | return 0; |
10502 | 0 | } |
10503 | | |
10504 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10505 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
10506 | 0 | return 0; |
10507 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10508 | 0 | return fastEmitInst_rr(X86::VPTESTNMWZ128rr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10509 | 0 | } |
10510 | 0 | return 0; |
10511 | 0 | } |
10512 | | |
10513 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10514 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
10515 | 0 | return 0; |
10516 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10517 | 0 | return fastEmitInst_rr(X86::VPTESTNMWZ256rr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10518 | 0 | } |
10519 | 0 | return 0; |
10520 | 0 | } |
10521 | | |
10522 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10523 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
10524 | 0 | return 0; |
10525 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10526 | 0 | return fastEmitInst_rr(X86::VPTESTNMWZrr, &X86::VK32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10527 | 0 | } |
10528 | 0 | return 0; |
10529 | 0 | } |
10530 | | |
10531 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10532 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
10533 | 0 | return 0; |
10534 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10535 | 0 | return fastEmitInst_rr(X86::VPTESTNMDZ128rr, &X86::VK4RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10536 | 0 | } |
10537 | 0 | return 0; |
10538 | 0 | } |
10539 | | |
10540 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10541 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
10542 | 0 | return 0; |
10543 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10544 | 0 | return fastEmitInst_rr(X86::VPTESTNMDZ256rr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10545 | 0 | } |
10546 | 0 | return 0; |
10547 | 0 | } |
10548 | | |
10549 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10550 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
10551 | 0 | return 0; |
10552 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
10553 | 0 | return fastEmitInst_rr(X86::VPTESTNMDZrr, &X86::VK16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10554 | 0 | } |
10555 | 0 | return 0; |
10556 | 0 | } |
10557 | | |
10558 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10559 | 0 | if (RetVT.SimpleTy != MVT::v2i1) |
10560 | 0 | return 0; |
10561 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10562 | 0 | return fastEmitInst_rr(X86::VPTESTNMQZ128rr, &X86::VK2RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10563 | 0 | } |
10564 | 0 | return 0; |
10565 | 0 | } |
10566 | | |
10567 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10568 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
10569 | 0 | return 0; |
10570 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10571 | 0 | return fastEmitInst_rr(X86::VPTESTNMQZ256rr, &X86::VK4RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10572 | 0 | } |
10573 | 0 | return 0; |
10574 | 0 | } |
10575 | | |
10576 | 0 | unsigned fastEmit_X86ISD_TESTNM_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10577 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
10578 | 0 | return 0; |
10579 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
10580 | 0 | return fastEmitInst_rr(X86::VPTESTNMQZrr, &X86::VK8RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10581 | 0 | } |
10582 | 0 | return 0; |
10583 | 0 | } |
10584 | | |
10585 | | unsigned fastEmit_X86ISD_TESTNM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10586 | | switch (VT.SimpleTy) { |
10587 | | case MVT::v16i8: return fastEmit_X86ISD_TESTNM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10588 | | case MVT::v32i8: return fastEmit_X86ISD_TESTNM_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10589 | | case MVT::v64i8: return fastEmit_X86ISD_TESTNM_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10590 | | case MVT::v8i16: return fastEmit_X86ISD_TESTNM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10591 | | case MVT::v16i16: return fastEmit_X86ISD_TESTNM_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10592 | | case MVT::v32i16: return fastEmit_X86ISD_TESTNM_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10593 | | case MVT::v4i32: return fastEmit_X86ISD_TESTNM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10594 | | case MVT::v8i32: return fastEmit_X86ISD_TESTNM_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10595 | | case MVT::v16i32: return fastEmit_X86ISD_TESTNM_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10596 | | case MVT::v2i64: return fastEmit_X86ISD_TESTNM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10597 | | case MVT::v4i64: return fastEmit_X86ISD_TESTNM_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10598 | | case MVT::v8i64: return fastEmit_X86ISD_TESTNM_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10599 | | default: return 0; |
10600 | | } |
10601 | | } |
10602 | | |
10603 | | // FastEmit functions for X86ISD::TESTP. |
10604 | | |
10605 | 0 | unsigned fastEmit_X86ISD_TESTP_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10606 | 0 | if (RetVT.SimpleTy != MVT::i32) |
10607 | 0 | return 0; |
10608 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
10609 | 0 | return fastEmitInst_rr(X86::VTESTPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10610 | 0 | } |
10611 | 0 | return 0; |
10612 | 0 | } |
10613 | | |
10614 | 0 | unsigned fastEmit_X86ISD_TESTP_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10615 | 0 | if (RetVT.SimpleTy != MVT::i32) |
10616 | 0 | return 0; |
10617 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
10618 | 0 | return fastEmitInst_rr(X86::VTESTPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10619 | 0 | } |
10620 | 0 | return 0; |
10621 | 0 | } |
10622 | | |
10623 | 0 | unsigned fastEmit_X86ISD_TESTP_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10624 | 0 | if (RetVT.SimpleTy != MVT::i32) |
10625 | 0 | return 0; |
10626 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
10627 | 0 | return fastEmitInst_rr(X86::VTESTPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10628 | 0 | } |
10629 | 0 | return 0; |
10630 | 0 | } |
10631 | | |
10632 | 0 | unsigned fastEmit_X86ISD_TESTP_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10633 | 0 | if (RetVT.SimpleTy != MVT::i32) |
10634 | 0 | return 0; |
10635 | 0 | if (0 (Subtarget->hasAVX())0 ) { |
10636 | 0 | return fastEmitInst_rr(X86::VTESTPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10637 | 0 | } |
10638 | 0 | return 0; |
10639 | 0 | } |
10640 | | |
10641 | | unsigned fastEmit_X86ISD_TESTP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10642 | | switch (VT.SimpleTy) { |
10643 | | case MVT::v4f32: return fastEmit_X86ISD_TESTP_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10644 | | case MVT::v8f32: return fastEmit_X86ISD_TESTP_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10645 | | case MVT::v2f64: return fastEmit_X86ISD_TESTP_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10646 | | case MVT::v4f64: return fastEmit_X86ISD_TESTP_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10647 | | default: return 0; |
10648 | | } |
10649 | | } |
10650 | | |
10651 | | // FastEmit functions for X86ISD::UCOMI. |
10652 | | |
10653 | 0 | unsigned fastEmit_X86ISD_UCOMI_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10654 | 0 | if (RetVT.SimpleTy != MVT::i32) |
10655 | 0 | return 0; |
10656 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
10657 | 0 | return fastEmitInst_rr(X86::Int_VUCOMISSZrr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10658 | 0 | } |
10659 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
10660 | 0 | return fastEmitInst_rr(X86::Int_UCOMISSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10661 | 0 | } |
10662 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
10663 | 0 | return fastEmitInst_rr(X86::Int_VUCOMISSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10664 | 0 | } |
10665 | 0 | return 0; |
10666 | 0 | } |
10667 | | |
10668 | 0 | unsigned fastEmit_X86ISD_UCOMI_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10669 | 0 | if (RetVT.SimpleTy != MVT::i32) |
10670 | 0 | return 0; |
10671 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
10672 | 0 | return fastEmitInst_rr(X86::Int_VUCOMISDZrr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10673 | 0 | } |
10674 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10675 | 0 | return fastEmitInst_rr(X86::Int_UCOMISDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10676 | 0 | } |
10677 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX512()0 )) { |
10678 | 0 | return fastEmitInst_rr(X86::Int_VUCOMISDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10679 | 0 | } |
10680 | 0 | return 0; |
10681 | 0 | } |
10682 | | |
10683 | | unsigned fastEmit_X86ISD_UCOMI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10684 | | switch (VT.SimpleTy) { |
10685 | | case MVT::v4f32: return fastEmit_X86ISD_UCOMI_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10686 | | case MVT::v2f64: return fastEmit_X86ISD_UCOMI_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10687 | | default: return 0; |
10688 | | } |
10689 | | } |
10690 | | |
10691 | | // FastEmit functions for X86ISD::UNPCKH. |
10692 | | |
10693 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10694 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10695 | 0 | return 0; |
10696 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10697 | 0 | return fastEmitInst_rr(X86::VPUNPCKHBWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10698 | 0 | } |
10699 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10700 | 0 | return fastEmitInst_rr(X86::PUNPCKHBWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10701 | 0 | } |
10702 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10703 | 0 | return fastEmitInst_rr(X86::VPUNPCKHBWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10704 | 0 | } |
10705 | 0 | return 0; |
10706 | 0 | } |
10707 | | |
10708 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10709 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
10710 | 0 | return 0; |
10711 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10712 | 0 | return fastEmitInst_rr(X86::VPUNPCKHBWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10713 | 0 | } |
10714 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10715 | 0 | return fastEmitInst_rr(X86::VPUNPCKHBWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10716 | 0 | } |
10717 | 0 | return 0; |
10718 | 0 | } |
10719 | | |
10720 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10721 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
10722 | 0 | return 0; |
10723 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10724 | 0 | return fastEmitInst_rr(X86::VPUNPCKHBWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10725 | 0 | } |
10726 | 0 | return 0; |
10727 | 0 | } |
10728 | | |
10729 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10730 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10731 | 0 | return 0; |
10732 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10733 | 0 | return fastEmitInst_rr(X86::VPUNPCKHWDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10734 | 0 | } |
10735 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10736 | 0 | return fastEmitInst_rr(X86::PUNPCKHWDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10737 | 0 | } |
10738 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10739 | 0 | return fastEmitInst_rr(X86::VPUNPCKHWDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10740 | 0 | } |
10741 | 0 | return 0; |
10742 | 0 | } |
10743 | | |
10744 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10745 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
10746 | 0 | return 0; |
10747 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10748 | 0 | return fastEmitInst_rr(X86::VPUNPCKHWDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10749 | 0 | } |
10750 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10751 | 0 | return fastEmitInst_rr(X86::VPUNPCKHWDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10752 | 0 | } |
10753 | 0 | return 0; |
10754 | 0 | } |
10755 | | |
10756 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10757 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
10758 | 0 | return 0; |
10759 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10760 | 0 | return fastEmitInst_rr(X86::VPUNPCKHWDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10761 | 0 | } |
10762 | 0 | return 0; |
10763 | 0 | } |
10764 | | |
10765 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10766 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
10767 | 0 | return 0; |
10768 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10769 | 0 | return fastEmitInst_rr(X86::VPUNPCKHDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10770 | 0 | } |
10771 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10772 | 0 | return fastEmitInst_rr(X86::PUNPCKHDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10773 | 0 | } |
10774 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
10775 | 0 | return fastEmitInst_rr(X86::VPUNPCKHDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10776 | 0 | } |
10777 | 0 | return 0; |
10778 | 0 | } |
10779 | | |
10780 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10781 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
10782 | 0 | return 0; |
10783 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX2()0 )) { |
10784 | 0 | return fastEmitInst_rr(X86::VUNPCKHPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10785 | 0 | } |
10786 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10787 | 0 | return fastEmitInst_rr(X86::VPUNPCKHDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10788 | 0 | } |
10789 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
10790 | 0 | return fastEmitInst_rr(X86::VPUNPCKHDQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10791 | 0 | } |
10792 | 0 | return 0; |
10793 | 0 | } |
10794 | | |
10795 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10796 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
10797 | 0 | return 0; |
10798 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
10799 | 0 | return fastEmitInst_rr(X86::VPUNPCKHDQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10800 | 0 | } |
10801 | 0 | return 0; |
10802 | 0 | } |
10803 | | |
10804 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10805 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
10806 | 0 | return 0; |
10807 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10808 | 0 | return fastEmitInst_rr(X86::VPUNPCKHQDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10809 | 0 | } |
10810 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10811 | 0 | return fastEmitInst_rr(X86::PUNPCKHQDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10812 | 0 | } |
10813 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
10814 | 0 | return fastEmitInst_rr(X86::VPUNPCKHQDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10815 | 0 | } |
10816 | 0 | return 0; |
10817 | 0 | } |
10818 | | |
10819 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10820 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
10821 | 0 | return 0; |
10822 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX2()0 )) { |
10823 | 0 | return fastEmitInst_rr(X86::VUNPCKHPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10824 | 0 | } |
10825 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10826 | 0 | return fastEmitInst_rr(X86::VPUNPCKHQDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10827 | 0 | } |
10828 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
10829 | 0 | return fastEmitInst_rr(X86::VPUNPCKHQDQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10830 | 0 | } |
10831 | 0 | return 0; |
10832 | 0 | } |
10833 | | |
10834 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10835 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
10836 | 0 | return 0; |
10837 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
10838 | 0 | return fastEmitInst_rr(X86::VPUNPCKHQDQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10839 | 0 | } |
10840 | 0 | return 0; |
10841 | 0 | } |
10842 | | |
10843 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10844 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
10845 | 0 | return 0; |
10846 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10847 | 0 | return fastEmitInst_rr(X86::VUNPCKHPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10848 | 0 | } |
10849 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
10850 | 0 | return fastEmitInst_rr(X86::UNPCKHPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10851 | 0 | } |
10852 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
10853 | 0 | return fastEmitInst_rr(X86::VUNPCKHPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10854 | 0 | } |
10855 | 0 | return 0; |
10856 | 0 | } |
10857 | | |
10858 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10859 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
10860 | 0 | return 0; |
10861 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10862 | 0 | return fastEmitInst_rr(X86::VUNPCKHPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10863 | 0 | } |
10864 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
10865 | 0 | return fastEmitInst_rr(X86::VUNPCKHPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10866 | 0 | } |
10867 | 0 | return 0; |
10868 | 0 | } |
10869 | | |
10870 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v16f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10871 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
10872 | 0 | return 0; |
10873 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
10874 | 0 | return fastEmitInst_rr(X86::VUNPCKHPSZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10875 | 0 | } |
10876 | 0 | return 0; |
10877 | 0 | } |
10878 | | |
10879 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10880 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
10881 | 0 | return 0; |
10882 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10883 | 0 | return fastEmitInst_rr(X86::VUNPCKHPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10884 | 0 | } |
10885 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10886 | 0 | return fastEmitInst_rr(X86::UNPCKHPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10887 | 0 | } |
10888 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
10889 | 0 | return fastEmitInst_rr(X86::VUNPCKHPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10890 | 0 | } |
10891 | 0 | return 0; |
10892 | 0 | } |
10893 | | |
10894 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10895 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
10896 | 0 | return 0; |
10897 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
10898 | 0 | return fastEmitInst_rr(X86::VUNPCKHPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10899 | 0 | } |
10900 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
10901 | 0 | return fastEmitInst_rr(X86::VUNPCKHPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10902 | 0 | } |
10903 | 0 | return 0; |
10904 | 0 | } |
10905 | | |
10906 | 0 | unsigned fastEmit_X86ISD_UNPCKH_MVT_v8f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10907 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
10908 | 0 | return 0; |
10909 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
10910 | 0 | return fastEmitInst_rr(X86::VUNPCKHPDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10911 | 0 | } |
10912 | 0 | return 0; |
10913 | 0 | } |
10914 | | |
10915 | | unsigned fastEmit_X86ISD_UNPCKH_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10916 | | switch (VT.SimpleTy) { |
10917 | | case MVT::v16i8: return fastEmit_X86ISD_UNPCKH_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10918 | | case MVT::v32i8: return fastEmit_X86ISD_UNPCKH_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10919 | | case MVT::v64i8: return fastEmit_X86ISD_UNPCKH_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10920 | | case MVT::v8i16: return fastEmit_X86ISD_UNPCKH_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10921 | | case MVT::v16i16: return fastEmit_X86ISD_UNPCKH_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10922 | | case MVT::v32i16: return fastEmit_X86ISD_UNPCKH_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10923 | | case MVT::v4i32: return fastEmit_X86ISD_UNPCKH_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10924 | | case MVT::v8i32: return fastEmit_X86ISD_UNPCKH_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10925 | | case MVT::v16i32: return fastEmit_X86ISD_UNPCKH_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10926 | | case MVT::v2i64: return fastEmit_X86ISD_UNPCKH_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10927 | | case MVT::v4i64: return fastEmit_X86ISD_UNPCKH_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10928 | | case MVT::v8i64: return fastEmit_X86ISD_UNPCKH_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10929 | | case MVT::v4f32: return fastEmit_X86ISD_UNPCKH_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10930 | | case MVT::v8f32: return fastEmit_X86ISD_UNPCKH_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10931 | | case MVT::v16f32: return fastEmit_X86ISD_UNPCKH_MVT_v16f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10932 | | case MVT::v2f64: return fastEmit_X86ISD_UNPCKH_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10933 | | case MVT::v4f64: return fastEmit_X86ISD_UNPCKH_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10934 | | case MVT::v8f64: return fastEmit_X86ISD_UNPCKH_MVT_v8f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
10935 | | default: return 0; |
10936 | | } |
10937 | | } |
10938 | | |
10939 | | // FastEmit functions for X86ISD::UNPCKL. |
10940 | | |
10941 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10942 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10943 | 0 | return 0; |
10944 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10945 | 0 | return fastEmitInst_rr(X86::VPUNPCKLBWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10946 | 0 | } |
10947 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10948 | 0 | return fastEmitInst_rr(X86::PUNPCKLBWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10949 | 0 | } |
10950 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10951 | 0 | return fastEmitInst_rr(X86::VPUNPCKLBWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10952 | 0 | } |
10953 | 0 | return 0; |
10954 | 0 | } |
10955 | | |
10956 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10957 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
10958 | 0 | return 0; |
10959 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10960 | 0 | return fastEmitInst_rr(X86::VPUNPCKLBWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10961 | 0 | } |
10962 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10963 | 0 | return fastEmitInst_rr(X86::VPUNPCKLBWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10964 | 0 | } |
10965 | 0 | return 0; |
10966 | 0 | } |
10967 | | |
10968 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10969 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
10970 | 0 | return 0; |
10971 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
10972 | 0 | return fastEmitInst_rr(X86::VPUNPCKLBWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10973 | 0 | } |
10974 | 0 | return 0; |
10975 | 0 | } |
10976 | | |
10977 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10978 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10979 | 0 | return 0; |
10980 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10981 | 0 | return fastEmitInst_rr(X86::VPUNPCKLWDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10982 | 0 | } |
10983 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
10984 | 0 | return fastEmitInst_rr(X86::PUNPCKLWDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10985 | 0 | } |
10986 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10987 | 0 | return fastEmitInst_rr(X86::VPUNPCKLWDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10988 | 0 | } |
10989 | 0 | return 0; |
10990 | 0 | } |
10991 | | |
10992 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
10993 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
10994 | 0 | return 0; |
10995 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
10996 | 0 | return fastEmitInst_rr(X86::VPUNPCKLWDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
10997 | 0 | } |
10998 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
10999 | 0 | return fastEmitInst_rr(X86::VPUNPCKLWDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11000 | 0 | } |
11001 | 0 | return 0; |
11002 | 0 | } |
11003 | | |
11004 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11005 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
11006 | 0 | return 0; |
11007 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
11008 | 0 | return fastEmitInst_rr(X86::VPUNPCKLWDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11009 | 0 | } |
11010 | 0 | return 0; |
11011 | 0 | } |
11012 | | |
11013 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11014 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11015 | 0 | return 0; |
11016 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11017 | 0 | return fastEmitInst_rr(X86::VPUNPCKLDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11018 | 0 | } |
11019 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11020 | 0 | return fastEmitInst_rr(X86::PUNPCKLDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11021 | 0 | } |
11022 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
11023 | 0 | return fastEmitInst_rr(X86::VPUNPCKLDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11024 | 0 | } |
11025 | 0 | return 0; |
11026 | 0 | } |
11027 | | |
11028 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11029 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
11030 | 0 | return 0; |
11031 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX2()0 )) { |
11032 | 0 | return fastEmitInst_rr(X86::VUNPCKLPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11033 | 0 | } |
11034 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11035 | 0 | return fastEmitInst_rr(X86::VPUNPCKLDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11036 | 0 | } |
11037 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
11038 | 0 | return fastEmitInst_rr(X86::VPUNPCKLDQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11039 | 0 | } |
11040 | 0 | return 0; |
11041 | 0 | } |
11042 | | |
11043 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11044 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
11045 | 0 | return 0; |
11046 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
11047 | 0 | return fastEmitInst_rr(X86::VPUNPCKLDQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11048 | 0 | } |
11049 | 0 | return 0; |
11050 | 0 | } |
11051 | | |
11052 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11053 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
11054 | 0 | return 0; |
11055 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11056 | 0 | return fastEmitInst_rr(X86::VPUNPCKLQDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11057 | 0 | } |
11058 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11059 | 0 | return fastEmitInst_rr(X86::PUNPCKLQDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11060 | 0 | } |
11061 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
11062 | 0 | return fastEmitInst_rr(X86::VPUNPCKLQDQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11063 | 0 | } |
11064 | 0 | return 0; |
11065 | 0 | } |
11066 | | |
11067 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11068 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
11069 | 0 | return 0; |
11070 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX2()0 )) { |
11071 | 0 | return fastEmitInst_rr(X86::VUNPCKLPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11072 | 0 | } |
11073 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11074 | 0 | return fastEmitInst_rr(X86::VPUNPCKLQDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11075 | 0 | } |
11076 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
11077 | 0 | return fastEmitInst_rr(X86::VPUNPCKLQDQYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11078 | 0 | } |
11079 | 0 | return 0; |
11080 | 0 | } |
11081 | | |
11082 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11083 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
11084 | 0 | return 0; |
11085 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
11086 | 0 | return fastEmitInst_rr(X86::VPUNPCKLQDQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11087 | 0 | } |
11088 | 0 | return 0; |
11089 | 0 | } |
11090 | | |
11091 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11092 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
11093 | 0 | return 0; |
11094 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11095 | 0 | return fastEmitInst_rr(X86::VUNPCKLPSZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11096 | 0 | } |
11097 | 0 | if (0 (Subtarget->hasSSE1() && 0 !Subtarget->hasAVX()0 )) { |
11098 | 0 | return fastEmitInst_rr(X86::UNPCKLPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11099 | 0 | } |
11100 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
11101 | 0 | return fastEmitInst_rr(X86::VUNPCKLPSrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11102 | 0 | } |
11103 | 0 | return 0; |
11104 | 0 | } |
11105 | | |
11106 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v8f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11107 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
11108 | 0 | return 0; |
11109 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11110 | 0 | return fastEmitInst_rr(X86::VUNPCKLPSZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11111 | 0 | } |
11112 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
11113 | 0 | return fastEmitInst_rr(X86::VUNPCKLPSYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11114 | 0 | } |
11115 | 0 | return 0; |
11116 | 0 | } |
11117 | | |
11118 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v16f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11119 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
11120 | 0 | return 0; |
11121 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
11122 | 0 | return fastEmitInst_rr(X86::VUNPCKLPSZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11123 | 0 | } |
11124 | 0 | return 0; |
11125 | 0 | } |
11126 | | |
11127 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11128 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
11129 | 0 | return 0; |
11130 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11131 | 0 | return fastEmitInst_rr(X86::VUNPCKLPDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11132 | 0 | } |
11133 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11134 | 0 | return fastEmitInst_rr(X86::UNPCKLPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11135 | 0 | } |
11136 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
11137 | 0 | return fastEmitInst_rr(X86::VUNPCKLPDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11138 | 0 | } |
11139 | 0 | return 0; |
11140 | 0 | } |
11141 | | |
11142 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11143 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
11144 | 0 | return 0; |
11145 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11146 | 0 | return fastEmitInst_rr(X86::VUNPCKLPDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11147 | 0 | } |
11148 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
11149 | 0 | return fastEmitInst_rr(X86::VUNPCKLPDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11150 | 0 | } |
11151 | 0 | return 0; |
11152 | 0 | } |
11153 | | |
11154 | 0 | unsigned fastEmit_X86ISD_UNPCKL_MVT_v8f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11155 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
11156 | 0 | return 0; |
11157 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
11158 | 0 | return fastEmitInst_rr(X86::VUNPCKLPDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11159 | 0 | } |
11160 | 0 | return 0; |
11161 | 0 | } |
11162 | | |
11163 | | unsigned fastEmit_X86ISD_UNPCKL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11164 | | switch (VT.SimpleTy) { |
11165 | | case MVT::v16i8: return fastEmit_X86ISD_UNPCKL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11166 | | case MVT::v32i8: return fastEmit_X86ISD_UNPCKL_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11167 | | case MVT::v64i8: return fastEmit_X86ISD_UNPCKL_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11168 | | case MVT::v8i16: return fastEmit_X86ISD_UNPCKL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11169 | | case MVT::v16i16: return fastEmit_X86ISD_UNPCKL_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11170 | | case MVT::v32i16: return fastEmit_X86ISD_UNPCKL_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11171 | | case MVT::v4i32: return fastEmit_X86ISD_UNPCKL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11172 | | case MVT::v8i32: return fastEmit_X86ISD_UNPCKL_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11173 | | case MVT::v16i32: return fastEmit_X86ISD_UNPCKL_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11174 | | case MVT::v2i64: return fastEmit_X86ISD_UNPCKL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11175 | | case MVT::v4i64: return fastEmit_X86ISD_UNPCKL_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11176 | | case MVT::v8i64: return fastEmit_X86ISD_UNPCKL_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11177 | | case MVT::v4f32: return fastEmit_X86ISD_UNPCKL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11178 | | case MVT::v8f32: return fastEmit_X86ISD_UNPCKL_MVT_v8f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11179 | | case MVT::v16f32: return fastEmit_X86ISD_UNPCKL_MVT_v16f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11180 | | case MVT::v2f64: return fastEmit_X86ISD_UNPCKL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11181 | | case MVT::v4f64: return fastEmit_X86ISD_UNPCKL_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11182 | | case MVT::v8f64: return fastEmit_X86ISD_UNPCKL_MVT_v8f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11183 | | default: return 0; |
11184 | | } |
11185 | | } |
11186 | | |
11187 | | // FastEmit functions for X86ISD::VPERMV. |
11188 | | |
11189 | 0 | unsigned fastEmit_X86ISD_VPERMV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11190 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
11191 | 0 | return 0; |
11192 | 0 | if (0 (Subtarget->hasVBMI()) && 0 (Subtarget->hasVLX())0 ) { |
11193 | 0 | return fastEmitInst_rr(X86::VPERMBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11194 | 0 | } |
11195 | 0 | return 0; |
11196 | 0 | } |
11197 | | |
11198 | 0 | unsigned fastEmit_X86ISD_VPERMV_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11199 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
11200 | 0 | return 0; |
11201 | 0 | if (0 (Subtarget->hasVBMI()) && 0 (Subtarget->hasVLX())0 ) { |
11202 | 0 | return fastEmitInst_rr(X86::VPERMBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11203 | 0 | } |
11204 | 0 | return 0; |
11205 | 0 | } |
11206 | | |
11207 | 0 | unsigned fastEmit_X86ISD_VPERMV_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11208 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
11209 | 0 | return 0; |
11210 | 0 | if (0 (Subtarget->hasVBMI())0 ) { |
11211 | 0 | return fastEmitInst_rr(X86::VPERMBZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11212 | 0 | } |
11213 | 0 | return 0; |
11214 | 0 | } |
11215 | | |
11216 | 0 | unsigned fastEmit_X86ISD_VPERMV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11217 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11218 | 0 | return 0; |
11219 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
11220 | 0 | return fastEmitInst_rr(X86::VPERMWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11221 | 0 | } |
11222 | 0 | return 0; |
11223 | 0 | } |
11224 | | |
11225 | 0 | unsigned fastEmit_X86ISD_VPERMV_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11226 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
11227 | 0 | return 0; |
11228 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
11229 | 0 | return fastEmitInst_rr(X86::VPERMWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11230 | 0 | } |
11231 | 0 | return 0; |
11232 | 0 | } |
11233 | | |
11234 | 0 | unsigned fastEmit_X86ISD_VPERMV_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11235 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
11236 | 0 | return 0; |
11237 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
11238 | 0 | return fastEmitInst_rr(X86::VPERMWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11239 | 0 | } |
11240 | 0 | return 0; |
11241 | 0 | } |
11242 | | |
11243 | 0 | unsigned fastEmit_X86ISD_VPERMV_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11244 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
11245 | 0 | return 0; |
11246 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11247 | 0 | return fastEmitInst_rr(X86::VPERMDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11248 | 0 | } |
11249 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
11250 | 0 | return fastEmitInst_rr(X86::VPERMDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11251 | 0 | } |
11252 | 0 | return 0; |
11253 | 0 | } |
11254 | | |
11255 | 0 | unsigned fastEmit_X86ISD_VPERMV_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11256 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
11257 | 0 | return 0; |
11258 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
11259 | 0 | return fastEmitInst_rr(X86::VPERMDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11260 | 0 | } |
11261 | 0 | return 0; |
11262 | 0 | } |
11263 | | |
11264 | 0 | unsigned fastEmit_X86ISD_VPERMV_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11265 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
11266 | 0 | return 0; |
11267 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11268 | 0 | return fastEmitInst_rr(X86::VPERMQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11269 | 0 | } |
11270 | 0 | return 0; |
11271 | 0 | } |
11272 | | |
11273 | 0 | unsigned fastEmit_X86ISD_VPERMV_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11274 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
11275 | 0 | return 0; |
11276 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
11277 | 0 | return fastEmitInst_rr(X86::VPERMQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11278 | 0 | } |
11279 | 0 | return 0; |
11280 | 0 | } |
11281 | | |
11282 | | unsigned fastEmit_X86ISD_VPERMV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11283 | | switch (VT.SimpleTy) { |
11284 | | case MVT::v16i8: return fastEmit_X86ISD_VPERMV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11285 | | case MVT::v32i8: return fastEmit_X86ISD_VPERMV_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11286 | | case MVT::v64i8: return fastEmit_X86ISD_VPERMV_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11287 | | case MVT::v8i16: return fastEmit_X86ISD_VPERMV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11288 | | case MVT::v16i16: return fastEmit_X86ISD_VPERMV_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11289 | | case MVT::v32i16: return fastEmit_X86ISD_VPERMV_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11290 | | case MVT::v8i32: return fastEmit_X86ISD_VPERMV_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11291 | | case MVT::v16i32: return fastEmit_X86ISD_VPERMV_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11292 | | case MVT::v4i64: return fastEmit_X86ISD_VPERMV_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11293 | | case MVT::v8i64: return fastEmit_X86ISD_VPERMV_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11294 | | default: return 0; |
11295 | | } |
11296 | | } |
11297 | | |
11298 | | // FastEmit functions for X86ISD::VPMADDUBSW. |
11299 | | |
11300 | 0 | unsigned fastEmit_X86ISD_VPMADDUBSW_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11301 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11302 | 0 | return 0; |
11303 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
11304 | 0 | return fastEmitInst_rr(X86::VPMADDUBSWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11305 | 0 | } |
11306 | 0 | if (0 (Subtarget->hasSSSE3() && 0 !Subtarget->hasAVX()0 )) { |
11307 | 0 | return fastEmitInst_rr(X86::PMADDUBSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11308 | 0 | } |
11309 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
11310 | 0 | return fastEmitInst_rr(X86::VPMADDUBSWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11311 | 0 | } |
11312 | 0 | return 0; |
11313 | 0 | } |
11314 | | |
11315 | 0 | unsigned fastEmit_X86ISD_VPMADDUBSW_MVT_v32i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11316 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
11317 | 0 | return 0; |
11318 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
11319 | 0 | return fastEmitInst_rr(X86::VPMADDUBSWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11320 | 0 | } |
11321 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
11322 | 0 | return fastEmitInst_rr(X86::VPMADDUBSWYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11323 | 0 | } |
11324 | 0 | return 0; |
11325 | 0 | } |
11326 | | |
11327 | 0 | unsigned fastEmit_X86ISD_VPMADDUBSW_MVT_v64i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11328 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
11329 | 0 | return 0; |
11330 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
11331 | 0 | return fastEmitInst_rr(X86::VPMADDUBSWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11332 | 0 | } |
11333 | 0 | return 0; |
11334 | 0 | } |
11335 | | |
11336 | | unsigned fastEmit_X86ISD_VPMADDUBSW_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11337 | | switch (VT.SimpleTy) { |
11338 | | case MVT::v16i8: return fastEmit_X86ISD_VPMADDUBSW_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11339 | | case MVT::v32i8: return fastEmit_X86ISD_VPMADDUBSW_MVT_v32i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11340 | | case MVT::v64i8: return fastEmit_X86ISD_VPMADDUBSW_MVT_v64i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11341 | | default: return 0; |
11342 | | } |
11343 | | } |
11344 | | |
11345 | | // FastEmit functions for X86ISD::VPMADDWD. |
11346 | | |
11347 | 0 | unsigned fastEmit_X86ISD_VPMADDWD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11348 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11349 | 0 | return 0; |
11350 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
11351 | 0 | return fastEmitInst_rr(X86::VPMADDWDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11352 | 0 | } |
11353 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11354 | 0 | return fastEmitInst_rr(X86::PMADDWDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11355 | 0 | } |
11356 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
11357 | 0 | return fastEmitInst_rr(X86::VPMADDWDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11358 | 0 | } |
11359 | 0 | return 0; |
11360 | 0 | } |
11361 | | |
11362 | 0 | unsigned fastEmit_X86ISD_VPMADDWD_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11363 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
11364 | 0 | return 0; |
11365 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
11366 | 0 | return fastEmitInst_rr(X86::VPMADDWDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11367 | 0 | } |
11368 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
11369 | 0 | return fastEmitInst_rr(X86::VPMADDWDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11370 | 0 | } |
11371 | 0 | return 0; |
11372 | 0 | } |
11373 | | |
11374 | 0 | unsigned fastEmit_X86ISD_VPMADDWD_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11375 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
11376 | 0 | return 0; |
11377 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
11378 | 0 | return fastEmitInst_rr(X86::VPMADDWDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11379 | 0 | } |
11380 | 0 | return 0; |
11381 | 0 | } |
11382 | | |
11383 | | unsigned fastEmit_X86ISD_VPMADDWD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11384 | | switch (VT.SimpleTy) { |
11385 | | case MVT::v8i16: return fastEmit_X86ISD_VPMADDWD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11386 | | case MVT::v16i16: return fastEmit_X86ISD_VPMADDWD_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11387 | | case MVT::v32i16: return fastEmit_X86ISD_VPMADDWD_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11388 | | default: return 0; |
11389 | | } |
11390 | | } |
11391 | | |
11392 | | // FastEmit functions for X86ISD::VPSHA. |
11393 | | |
11394 | 0 | unsigned fastEmit_X86ISD_VPSHA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11395 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
11396 | 0 | return 0; |
11397 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
11398 | 0 | return fastEmitInst_rr(X86::VPSHABrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11399 | 0 | } |
11400 | 0 | return 0; |
11401 | 0 | } |
11402 | | |
11403 | 0 | unsigned fastEmit_X86ISD_VPSHA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11404 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11405 | 0 | return 0; |
11406 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
11407 | 0 | return fastEmitInst_rr(X86::VPSHAWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11408 | 0 | } |
11409 | 0 | return 0; |
11410 | 0 | } |
11411 | | |
11412 | 0 | unsigned fastEmit_X86ISD_VPSHA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11413 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11414 | 0 | return 0; |
11415 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
11416 | 0 | return fastEmitInst_rr(X86::VPSHADrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11417 | 0 | } |
11418 | 0 | return 0; |
11419 | 0 | } |
11420 | | |
11421 | 0 | unsigned fastEmit_X86ISD_VPSHA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11422 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
11423 | 0 | return 0; |
11424 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
11425 | 0 | return fastEmitInst_rr(X86::VPSHAQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11426 | 0 | } |
11427 | 0 | return 0; |
11428 | 0 | } |
11429 | | |
11430 | | unsigned fastEmit_X86ISD_VPSHA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11431 | | switch (VT.SimpleTy) { |
11432 | | case MVT::v16i8: return fastEmit_X86ISD_VPSHA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11433 | | case MVT::v8i16: return fastEmit_X86ISD_VPSHA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11434 | | case MVT::v4i32: return fastEmit_X86ISD_VPSHA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11435 | | case MVT::v2i64: return fastEmit_X86ISD_VPSHA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11436 | | default: return 0; |
11437 | | } |
11438 | | } |
11439 | | |
11440 | | // FastEmit functions for X86ISD::VPSHL. |
11441 | | |
11442 | 0 | unsigned fastEmit_X86ISD_VPSHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11443 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
11444 | 0 | return 0; |
11445 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
11446 | 0 | return fastEmitInst_rr(X86::VPSHLBrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11447 | 0 | } |
11448 | 0 | return 0; |
11449 | 0 | } |
11450 | | |
11451 | 0 | unsigned fastEmit_X86ISD_VPSHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11452 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11453 | 0 | return 0; |
11454 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
11455 | 0 | return fastEmitInst_rr(X86::VPSHLWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11456 | 0 | } |
11457 | 0 | return 0; |
11458 | 0 | } |
11459 | | |
11460 | 0 | unsigned fastEmit_X86ISD_VPSHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11461 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11462 | 0 | return 0; |
11463 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
11464 | 0 | return fastEmitInst_rr(X86::VPSHLDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11465 | 0 | } |
11466 | 0 | return 0; |
11467 | 0 | } |
11468 | | |
11469 | 0 | unsigned fastEmit_X86ISD_VPSHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11470 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
11471 | 0 | return 0; |
11472 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
11473 | 0 | return fastEmitInst_rr(X86::VPSHLQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11474 | 0 | } |
11475 | 0 | return 0; |
11476 | 0 | } |
11477 | | |
11478 | | unsigned fastEmit_X86ISD_VPSHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11479 | | switch (VT.SimpleTy) { |
11480 | | case MVT::v16i8: return fastEmit_X86ISD_VPSHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11481 | | case MVT::v8i16: return fastEmit_X86ISD_VPSHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11482 | | case MVT::v4i32: return fastEmit_X86ISD_VPSHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11483 | | case MVT::v2i64: return fastEmit_X86ISD_VPSHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11484 | | default: return 0; |
11485 | | } |
11486 | | } |
11487 | | |
11488 | | // FastEmit functions for X86ISD::VSHL. |
11489 | | |
11490 | 0 | unsigned fastEmit_X86ISD_VSHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11491 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11492 | 0 | return 0; |
11493 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
11494 | 0 | return fastEmitInst_rr(X86::VPSLLWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11495 | 0 | } |
11496 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11497 | 0 | return fastEmitInst_rr(X86::PSLLWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11498 | 0 | } |
11499 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
11500 | 0 | return fastEmitInst_rr(X86::VPSLLWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11501 | 0 | } |
11502 | 0 | return 0; |
11503 | 0 | } |
11504 | | |
11505 | 0 | unsigned fastEmit_X86ISD_VSHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11506 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11507 | 0 | return 0; |
11508 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11509 | 0 | return fastEmitInst_rr(X86::VPSLLDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11510 | 0 | } |
11511 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11512 | 0 | return fastEmitInst_rr(X86::PSLLDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11513 | 0 | } |
11514 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
11515 | 0 | return fastEmitInst_rr(X86::VPSLLDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11516 | 0 | } |
11517 | 0 | return 0; |
11518 | 0 | } |
11519 | | |
11520 | 0 | unsigned fastEmit_X86ISD_VSHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11521 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
11522 | 0 | return 0; |
11523 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11524 | 0 | return fastEmitInst_rr(X86::VPSLLQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11525 | 0 | } |
11526 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11527 | 0 | return fastEmitInst_rr(X86::PSLLQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11528 | 0 | } |
11529 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
11530 | 0 | return fastEmitInst_rr(X86::VPSLLQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11531 | 0 | } |
11532 | 0 | return 0; |
11533 | 0 | } |
11534 | | |
11535 | | unsigned fastEmit_X86ISD_VSHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11536 | | switch (VT.SimpleTy) { |
11537 | | case MVT::v8i16: return fastEmit_X86ISD_VSHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11538 | | case MVT::v4i32: return fastEmit_X86ISD_VSHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11539 | | case MVT::v2i64: return fastEmit_X86ISD_VSHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11540 | | default: return 0; |
11541 | | } |
11542 | | } |
11543 | | |
11544 | | // FastEmit functions for X86ISD::VSRA. |
11545 | | |
11546 | 0 | unsigned fastEmit_X86ISD_VSRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11547 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11548 | 0 | return 0; |
11549 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
11550 | 0 | return fastEmitInst_rr(X86::VPSRAWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11551 | 0 | } |
11552 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11553 | 0 | return fastEmitInst_rr(X86::PSRAWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11554 | 0 | } |
11555 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
11556 | 0 | return fastEmitInst_rr(X86::VPSRAWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11557 | 0 | } |
11558 | 0 | return 0; |
11559 | 0 | } |
11560 | | |
11561 | 0 | unsigned fastEmit_X86ISD_VSRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11562 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11563 | 0 | return 0; |
11564 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11565 | 0 | return fastEmitInst_rr(X86::VPSRADZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11566 | 0 | } |
11567 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11568 | 0 | return fastEmitInst_rr(X86::PSRADrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11569 | 0 | } |
11570 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
11571 | 0 | return fastEmitInst_rr(X86::VPSRADrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11572 | 0 | } |
11573 | 0 | return 0; |
11574 | 0 | } |
11575 | | |
11576 | 0 | unsigned fastEmit_X86ISD_VSRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11577 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
11578 | 0 | return 0; |
11579 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11580 | 0 | return fastEmitInst_rr(X86::VPSRAQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11581 | 0 | } |
11582 | 0 | return 0; |
11583 | 0 | } |
11584 | | |
11585 | | unsigned fastEmit_X86ISD_VSRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11586 | | switch (VT.SimpleTy) { |
11587 | | case MVT::v8i16: return fastEmit_X86ISD_VSRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11588 | | case MVT::v4i32: return fastEmit_X86ISD_VSRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11589 | | case MVT::v2i64: return fastEmit_X86ISD_VSRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11590 | | default: return 0; |
11591 | | } |
11592 | | } |
11593 | | |
11594 | | // FastEmit functions for X86ISD::VSRAV. |
11595 | | |
11596 | 0 | unsigned fastEmit_X86ISD_VSRAV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11597 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11598 | 0 | return 0; |
11599 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
11600 | 0 | return fastEmitInst_rr(X86::VPSRAVWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11601 | 0 | } |
11602 | 0 | return 0; |
11603 | 0 | } |
11604 | | |
11605 | 0 | unsigned fastEmit_X86ISD_VSRAV_MVT_v16i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11606 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
11607 | 0 | return 0; |
11608 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
11609 | 0 | return fastEmitInst_rr(X86::VPSRAVWZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11610 | 0 | } |
11611 | 0 | return 0; |
11612 | 0 | } |
11613 | | |
11614 | 0 | unsigned fastEmit_X86ISD_VSRAV_MVT_v32i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11615 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
11616 | 0 | return 0; |
11617 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
11618 | 0 | return fastEmitInst_rr(X86::VPSRAVWZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11619 | 0 | } |
11620 | 0 | return 0; |
11621 | 0 | } |
11622 | | |
11623 | 0 | unsigned fastEmit_X86ISD_VSRAV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11624 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11625 | 0 | return 0; |
11626 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
11627 | 0 | return fastEmitInst_rr(X86::VPSRAVDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11628 | 0 | } |
11629 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
11630 | 0 | return fastEmitInst_rr(X86::VPSRAVDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11631 | 0 | } |
11632 | 0 | return 0; |
11633 | 0 | } |
11634 | | |
11635 | 0 | unsigned fastEmit_X86ISD_VSRAV_MVT_v8i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11636 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
11637 | 0 | return 0; |
11638 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
11639 | 0 | return fastEmitInst_rr(X86::VPSRAVDZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11640 | 0 | } |
11641 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
11642 | 0 | return fastEmitInst_rr(X86::VPSRAVDYrr, &X86::VR256RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11643 | 0 | } |
11644 | 0 | return 0; |
11645 | 0 | } |
11646 | | |
11647 | 0 | unsigned fastEmit_X86ISD_VSRAV_MVT_v16i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11648 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
11649 | 0 | return 0; |
11650 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
11651 | 0 | return fastEmitInst_rr(X86::VPSRAVDZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11652 | 0 | } |
11653 | 0 | return 0; |
11654 | 0 | } |
11655 | | |
11656 | 0 | unsigned fastEmit_X86ISD_VSRAV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11657 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
11658 | 0 | return 0; |
11659 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
11660 | 0 | return fastEmitInst_rr(X86::VPSRAVQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11661 | 0 | } |
11662 | 0 | return 0; |
11663 | 0 | } |
11664 | | |
11665 | 0 | unsigned fastEmit_X86ISD_VSRAV_MVT_v4i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11666 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
11667 | 0 | return 0; |
11668 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
11669 | 0 | return fastEmitInst_rr(X86::VPSRAVQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11670 | 0 | } |
11671 | 0 | return 0; |
11672 | 0 | } |
11673 | | |
11674 | 0 | unsigned fastEmit_X86ISD_VSRAV_MVT_v8i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11675 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
11676 | 0 | return 0; |
11677 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
11678 | 0 | return fastEmitInst_rr(X86::VPSRAVQZrr, &X86::VR512RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11679 | 0 | } |
11680 | 0 | return 0; |
11681 | 0 | } |
11682 | | |
11683 | | unsigned fastEmit_X86ISD_VSRAV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11684 | | switch (VT.SimpleTy) { |
11685 | | case MVT::v8i16: return fastEmit_X86ISD_VSRAV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11686 | | case MVT::v16i16: return fastEmit_X86ISD_VSRAV_MVT_v16i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11687 | | case MVT::v32i16: return fastEmit_X86ISD_VSRAV_MVT_v32i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11688 | | case MVT::v4i32: return fastEmit_X86ISD_VSRAV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11689 | | case MVT::v8i32: return fastEmit_X86ISD_VSRAV_MVT_v8i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11690 | | case MVT::v16i32: return fastEmit_X86ISD_VSRAV_MVT_v16i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11691 | | case MVT::v2i64: return fastEmit_X86ISD_VSRAV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11692 | | case MVT::v4i64: return fastEmit_X86ISD_VSRAV_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11693 | | case MVT::v8i64: return fastEmit_X86ISD_VSRAV_MVT_v8i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11694 | | default: return 0; |
11695 | | } |
11696 | | } |
11697 | | |
11698 | | // FastEmit functions for X86ISD::VSRL. |
11699 | | |
11700 | 0 | unsigned fastEmit_X86ISD_VSRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11701 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11702 | 0 | return 0; |
11703 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
11704 | 0 | return fastEmitInst_rr(X86::VPSRLWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11705 | 0 | } |
11706 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11707 | 0 | return fastEmitInst_rr(X86::PSRLWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11708 | 0 | } |
11709 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
11710 | 0 | return fastEmitInst_rr(X86::VPSRLWrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11711 | 0 | } |
11712 | 0 | return 0; |
11713 | 0 | } |
11714 | | |
11715 | 0 | unsigned fastEmit_X86ISD_VSRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11716 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11717 | 0 | return 0; |
11718 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11719 | 0 | return fastEmitInst_rr(X86::VPSRLDZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11720 | 0 | } |
11721 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11722 | 0 | return fastEmitInst_rr(X86::PSRLDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11723 | 0 | } |
11724 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
11725 | 0 | return fastEmitInst_rr(X86::VPSRLDrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11726 | 0 | } |
11727 | 0 | return 0; |
11728 | 0 | } |
11729 | | |
11730 | 0 | unsigned fastEmit_X86ISD_VSRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11731 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
11732 | 0 | return 0; |
11733 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
11734 | 0 | return fastEmitInst_rr(X86::VPSRLQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11735 | 0 | } |
11736 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
11737 | 0 | return fastEmitInst_rr(X86::PSRLQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11738 | 0 | } |
11739 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
11740 | 0 | return fastEmitInst_rr(X86::VPSRLQrr, &X86::VR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); |
11741 | 0 | } |
11742 | 0 | return 0; |
11743 | 0 | } |
11744 | | |
11745 | | unsigned fastEmit_X86ISD_VSRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { |
11746 | | switch (VT.SimpleTy) { |
11747 | | case MVT::v8i16: return fastEmit_X86ISD_VSRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11748 | | case MVT::v4i32: return fastEmit_X86ISD_VSRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11749 | | case MVT::v2i64: return fastEmit_X86ISD_VSRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11750 | | default: return 0; |
11751 | | } |
11752 | | } |
11753 | | |
11754 | | // Top-level FastEmit function. |
11755 | | |
11756 | 538 | unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override { |
11757 | 538 | switch (Opcode) { |
11758 | 178 | case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11759 | 57 | case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11760 | 70 | case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11761 | 8 | case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11762 | 10 | case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11763 | 10 | case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11764 | 16 | case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11765 | 0 | case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11766 | 0 | case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11767 | 61 | case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11768 | 0 | case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11769 | 0 | case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11770 | 4 | case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11771 | 0 | case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11772 | 0 | case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11773 | 1 | case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11774 | 0 | case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11775 | 43 | case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11776 | 0 | case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11777 | 0 | case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11778 | 32 | case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11779 | 0 | case X86ISD::ADDS: return fastEmit_X86ISD_ADDS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11780 | 0 | case X86ISD::ADDSUB: return fastEmit_X86ISD_ADDSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11781 | 0 | case X86ISD::ADDUS: return fastEmit_X86ISD_ADDUS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11782 | 0 | case X86ISD::ANDNP: return fastEmit_X86ISD_ANDNP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11783 | 0 | case X86ISD::AVG: return fastEmit_X86ISD_AVG_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11784 | 0 | case X86ISD::BT: return fastEmit_X86ISD_BT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11785 | 0 | case X86ISD::CMP: return fastEmit_X86ISD_CMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11786 | 0 | case X86ISD::COMI: return fastEmit_X86ISD_COMI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11787 | 0 | case X86ISD::FAND: return fastEmit_X86ISD_FAND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11788 | 0 | case X86ISD::FANDN: return fastEmit_X86ISD_FANDN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11789 | 0 | case X86ISD::FHADD: return fastEmit_X86ISD_FHADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11790 | 0 | case X86ISD::FHSUB: return fastEmit_X86ISD_FHSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11791 | 0 | case X86ISD::FMAX: return fastEmit_X86ISD_FMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11792 | 0 | case X86ISD::FMAXC: return fastEmit_X86ISD_FMAXC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11793 | 0 | case X86ISD::FMAXS: return fastEmit_X86ISD_FMAXS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11794 | 0 | case X86ISD::FMIN: return fastEmit_X86ISD_FMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11795 | 0 | case X86ISD::FMINC: return fastEmit_X86ISD_FMINC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11796 | 0 | case X86ISD::FMINS: return fastEmit_X86ISD_FMINS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11797 | 0 | case X86ISD::FOR: return fastEmit_X86ISD_FOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11798 | 0 | case X86ISD::FRCPS: return fastEmit_X86ISD_FRCPS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11799 | 0 | case X86ISD::FRSQRTS: return fastEmit_X86ISD_FRSQRTS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11800 | 0 | case X86ISD::FXOR: return fastEmit_X86ISD_FXOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11801 | 0 | case X86ISD::HADD: return fastEmit_X86ISD_HADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11802 | 0 | case X86ISD::HSUB: return fastEmit_X86ISD_HSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11803 | 0 | case X86ISD::KORTEST: return fastEmit_X86ISD_KORTEST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11804 | 0 | case X86ISD::KTEST: return fastEmit_X86ISD_KTEST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11805 | 0 | case X86ISD::MOVHLPS: return fastEmit_X86ISD_MOVHLPS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11806 | 0 | case X86ISD::MOVLHPS: return fastEmit_X86ISD_MOVLHPS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11807 | 0 | case X86ISD::MULHRS: return fastEmit_X86ISD_MULHRS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11808 | 0 | case X86ISD::MULTISHIFT: return fastEmit_X86ISD_MULTISHIFT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11809 | 0 | case X86ISD::PACKSS: return fastEmit_X86ISD_PACKSS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11810 | 0 | case X86ISD::PACKUS: return fastEmit_X86ISD_PACKUS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11811 | 0 | case X86ISD::PCMPEQ: return fastEmit_X86ISD_PCMPEQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11812 | 0 | case X86ISD::PCMPEQM: return fastEmit_X86ISD_PCMPEQM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11813 | 0 | case X86ISD::PCMPGT: return fastEmit_X86ISD_PCMPGT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11814 | 0 | case X86ISD::PCMPGTM: return fastEmit_X86ISD_PCMPGTM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11815 | 0 | case X86ISD::PMULDQ: return fastEmit_X86ISD_PMULDQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11816 | 0 | case X86ISD::PMULUDQ: return fastEmit_X86ISD_PMULUDQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11817 | 0 | case X86ISD::PSADBW: return fastEmit_X86ISD_PSADBW_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11818 | 0 | case X86ISD::PSHUFB: return fastEmit_X86ISD_PSHUFB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11819 | 0 | case X86ISD::PTEST: return fastEmit_X86ISD_PTEST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11820 | 0 | case X86ISD::SUBS: return fastEmit_X86ISD_SUBS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11821 | 0 | case X86ISD::SUBUS: return fastEmit_X86ISD_SUBUS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11822 | 0 | case X86ISD::TESTM: return fastEmit_X86ISD_TESTM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11823 | 0 | case X86ISD::TESTNM: return fastEmit_X86ISD_TESTNM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11824 | 0 | case X86ISD::TESTP: return fastEmit_X86ISD_TESTP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11825 | 0 | case X86ISD::UCOMI: return fastEmit_X86ISD_UCOMI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11826 | 0 | case X86ISD::UNPCKH: return fastEmit_X86ISD_UNPCKH_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11827 | 0 | case X86ISD::UNPCKL: return fastEmit_X86ISD_UNPCKL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11828 | 0 | case X86ISD::VPERMV: return fastEmit_X86ISD_VPERMV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11829 | 0 | case X86ISD::VPMADDUBSW: return fastEmit_X86ISD_VPMADDUBSW_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11830 | 0 | case X86ISD::VPMADDWD: return fastEmit_X86ISD_VPMADDWD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11831 | 0 | case X86ISD::VPSHA: return fastEmit_X86ISD_VPSHA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11832 | 0 | case X86ISD::VPSHL: return fastEmit_X86ISD_VPSHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11833 | 0 | case X86ISD::VSHL: return fastEmit_X86ISD_VSHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11834 | 0 | case X86ISD::VSRA: return fastEmit_X86ISD_VSRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11835 | 0 | case X86ISD::VSRAV: return fastEmit_X86ISD_VSRAV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11836 | 0 | case X86ISD::VSRL: return fastEmit_X86ISD_VSRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); |
11837 | 48 | default: return 0; |
11838 | 538 | } |
11839 | 538 | } |
11840 | | |
11841 | | // FastEmit functions for ISD::ADD. |
11842 | | |
11843 | 3 | unsigned fastEmit_ISD_ADD_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11844 | 3 | if (RetVT.SimpleTy != MVT::i8) |
11845 | 0 | return 0; |
11846 | 3 | return fastEmitInst_ri(X86::ADD8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1); |
11847 | 3 | } |
11848 | | |
11849 | 0 | unsigned fastEmit_ISD_ADD_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11850 | 0 | if (RetVT.SimpleTy != MVT::i16) |
11851 | 0 | return 0; |
11852 | 0 | return fastEmitInst_ri(X86::ADD16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
11853 | 0 | } |
11854 | | |
11855 | 2 | unsigned fastEmit_ISD_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11856 | 2 | if (RetVT.SimpleTy != MVT::i32) |
11857 | 0 | return 0; |
11858 | 2 | return fastEmitInst_ri(X86::ADD32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
11859 | 2 | } |
11860 | | |
11861 | 7 | unsigned fastEmit_ISD_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11862 | 7 | switch (VT.SimpleTy) { |
11863 | 3 | case MVT::i8: return fastEmit_ISD_ADD_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1); |
11864 | 0 | case MVT::i16: return fastEmit_ISD_ADD_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1); |
11865 | 2 | case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); |
11866 | 2 | default: return 0; |
11867 | 7 | } |
11868 | 7 | } |
11869 | | |
11870 | | // FastEmit functions for ISD::AND. |
11871 | | |
11872 | 178 | unsigned fastEmit_ISD_AND_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11873 | 178 | if (RetVT.SimpleTy != MVT::i8) |
11874 | 0 | return 0; |
11875 | 178 | return fastEmitInst_ri(X86::AND8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1); |
11876 | 178 | } |
11877 | | |
11878 | 6 | unsigned fastEmit_ISD_AND_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11879 | 6 | if (RetVT.SimpleTy != MVT::i16) |
11880 | 0 | return 0; |
11881 | 6 | return fastEmitInst_ri(X86::AND16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
11882 | 6 | } |
11883 | | |
11884 | 21 | unsigned fastEmit_ISD_AND_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11885 | 21 | if (RetVT.SimpleTy != MVT::i32) |
11886 | 0 | return 0; |
11887 | 21 | return fastEmitInst_ri(X86::AND32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
11888 | 21 | } |
11889 | | |
11890 | 205 | unsigned fastEmit_ISD_AND_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11891 | 205 | switch (VT.SimpleTy) { |
11892 | 178 | case MVT::i8: return fastEmit_ISD_AND_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1); |
11893 | 6 | case MVT::i16: return fastEmit_ISD_AND_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1); |
11894 | 21 | case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); |
11895 | 0 | default: return 0; |
11896 | 205 | } |
11897 | 205 | } |
11898 | | |
11899 | | // FastEmit functions for ISD::EXTRACT_SUBVECTOR. |
11900 | | |
11901 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v32i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11902 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
11903 | 0 | return 0; |
11904 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
11905 | 0 | return fastEmitInst_ri(X86::VEXTRACTI32x4Z256rr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
11906 | 0 | } |
11907 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
11908 | 0 | return fastEmitInst_ri(X86::VEXTRACTI128rr, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
11909 | 0 | } |
11910 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX2()0 )) { |
11911 | 0 | return fastEmitInst_ri(X86::VEXTRACTF128rr, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
11912 | 0 | } |
11913 | 0 | return 0; |
11914 | 0 | } |
11915 | | |
11916 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v64i8_MVT_v16i8_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11917 | 0 | if ((Subtarget->hasAVX512())0 ) { |
11918 | 0 | return fastEmitInst_ri(X86::VEXTRACTI32x4Zrr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
11919 | 0 | } |
11920 | 0 | return 0; |
11921 | 0 | } |
11922 | | |
11923 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v64i8_MVT_v32i8_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11924 | 0 | if ((Subtarget->hasAVX512())0 ) { |
11925 | 0 | return fastEmitInst_ri(X86::VEXTRACTI64x4Zrr, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
11926 | 0 | } |
11927 | 0 | return 0; |
11928 | 0 | } |
11929 | | |
11930 | | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v64i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11931 | | switch (RetVT.SimpleTy) { |
11932 | | case MVT::v16i8: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v64i8_MVT_v16i8_ri(Op0, Op0IsKill, imm1); |
11933 | | case MVT::v32i8: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v64i8_MVT_v32i8_ri(Op0, Op0IsKill, imm1); |
11934 | | default: return 0; |
11935 | | } |
11936 | | } |
11937 | | |
11938 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11939 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11940 | 0 | return 0; |
11941 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
11942 | 0 | return fastEmitInst_ri(X86::VEXTRACTI32x4Z256rr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
11943 | 0 | } |
11944 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
11945 | 0 | return fastEmitInst_ri(X86::VEXTRACTI128rr, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
11946 | 0 | } |
11947 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX2()0 )) { |
11948 | 0 | return fastEmitInst_ri(X86::VEXTRACTF128rr, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
11949 | 0 | } |
11950 | 0 | return 0; |
11951 | 0 | } |
11952 | | |
11953 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v32i16_MVT_v8i16_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11954 | 0 | if ((Subtarget->hasAVX512())0 ) { |
11955 | 0 | return fastEmitInst_ri(X86::VEXTRACTI32x4Zrr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
11956 | 0 | } |
11957 | 0 | return 0; |
11958 | 0 | } |
11959 | | |
11960 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v32i16_MVT_v16i16_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11961 | 0 | if ((Subtarget->hasAVX512())0 ) { |
11962 | 0 | return fastEmitInst_ri(X86::VEXTRACTI64x4Zrr, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
11963 | 0 | } |
11964 | 0 | return 0; |
11965 | 0 | } |
11966 | | |
11967 | | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v32i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11968 | | switch (RetVT.SimpleTy) { |
11969 | | case MVT::v8i16: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v32i16_MVT_v8i16_ri(Op0, Op0IsKill, imm1); |
11970 | | case MVT::v16i16: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v32i16_MVT_v16i16_ri(Op0, Op0IsKill, imm1); |
11971 | | default: return 0; |
11972 | | } |
11973 | | } |
11974 | | |
11975 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11976 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11977 | 0 | return 0; |
11978 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
11979 | 0 | return fastEmitInst_ri(X86::VEXTRACTI128rr, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
11980 | 0 | } |
11981 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX2()0 )) { |
11982 | 0 | return fastEmitInst_ri(X86::VEXTRACTF128rr, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
11983 | 0 | } |
11984 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
11985 | 0 | return fastEmitInst_ri(X86::VEXTRACTI32x4Z256rr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
11986 | 0 | } |
11987 | 0 | return 0; |
11988 | 0 | } |
11989 | | |
11990 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16i32_MVT_v4i32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11991 | 0 | if ((Subtarget->hasAVX512())0 ) { |
11992 | 0 | return fastEmitInst_ri(X86::VEXTRACTI32x4Zrr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
11993 | 0 | } |
11994 | 0 | return 0; |
11995 | 0 | } |
11996 | | |
11997 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16i32_MVT_v8i32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
11998 | 0 | if ((Subtarget->hasAVX512())0 ) { |
11999 | 0 | return fastEmitInst_ri(X86::VEXTRACTI64x4Zrr, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
12000 | 0 | } |
12001 | 0 | return 0; |
12002 | 0 | } |
12003 | | |
12004 | | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12005 | | switch (RetVT.SimpleTy) { |
12006 | | case MVT::v4i32: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16i32_MVT_v4i32_ri(Op0, Op0IsKill, imm1); |
12007 | | case MVT::v8i32: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16i32_MVT_v8i32_ri(Op0, Op0IsKill, imm1); |
12008 | | default: return 0; |
12009 | | } |
12010 | | } |
12011 | | |
12012 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v4i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12013 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
12014 | 0 | return 0; |
12015 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
12016 | 0 | return fastEmitInst_ri(X86::VEXTRACTI32x4Z256rr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
12017 | 0 | } |
12018 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
12019 | 0 | return fastEmitInst_ri(X86::VEXTRACTI128rr, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
12020 | 0 | } |
12021 | 0 | if (0 (Subtarget->hasAVX() && 0 !Subtarget->hasAVX2()0 )) { |
12022 | 0 | return fastEmitInst_ri(X86::VEXTRACTF128rr, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
12023 | 0 | } |
12024 | 0 | return 0; |
12025 | 0 | } |
12026 | | |
12027 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8i64_MVT_v2i64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12028 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12029 | 0 | return fastEmitInst_ri(X86::VEXTRACTI32x4Zrr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
12030 | 0 | } |
12031 | 0 | return 0; |
12032 | 0 | } |
12033 | | |
12034 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8i64_MVT_v4i64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12035 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12036 | 0 | return fastEmitInst_ri(X86::VEXTRACTI64x4Zrr, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
12037 | 0 | } |
12038 | 0 | return 0; |
12039 | 0 | } |
12040 | | |
12041 | | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12042 | | switch (RetVT.SimpleTy) { |
12043 | | case MVT::v2i64: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8i64_MVT_v2i64_ri(Op0, Op0IsKill, imm1); |
12044 | | case MVT::v4i64: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8i64_MVT_v4i64_ri(Op0, Op0IsKill, imm1); |
12045 | | default: return 0; |
12046 | | } |
12047 | | } |
12048 | | |
12049 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12050 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
12051 | 0 | return 0; |
12052 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
12053 | 0 | return fastEmitInst_ri(X86::VEXTRACTF128rr, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
12054 | 0 | } |
12055 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
12056 | 0 | return fastEmitInst_ri(X86::VEXTRACTF32x4Z256rr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
12057 | 0 | } |
12058 | 0 | return 0; |
12059 | 0 | } |
12060 | | |
12061 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16f32_MVT_v4f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12062 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12063 | 0 | return fastEmitInst_ri(X86::VEXTRACTF32x4Zrr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
12064 | 0 | } |
12065 | 0 | return 0; |
12066 | 0 | } |
12067 | | |
12068 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16f32_MVT_v8f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12069 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12070 | 0 | return fastEmitInst_ri(X86::VEXTRACTF64x4Zrr, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
12071 | 0 | } |
12072 | 0 | return 0; |
12073 | 0 | } |
12074 | | |
12075 | | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12076 | | switch (RetVT.SimpleTy) { |
12077 | | case MVT::v4f32: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16f32_MVT_v4f32_ri(Op0, Op0IsKill, imm1); |
12078 | | case MVT::v8f32: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16f32_MVT_v8f32_ri(Op0, Op0IsKill, imm1); |
12079 | | default: return 0; |
12080 | | } |
12081 | | } |
12082 | | |
12083 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v4f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12084 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
12085 | 0 | return 0; |
12086 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
12087 | 0 | return fastEmitInst_ri(X86::VEXTRACTF32x4Z256rr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
12088 | 0 | } |
12089 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
12090 | 0 | return fastEmitInst_ri(X86::VEXTRACTF128rr, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
12091 | 0 | } |
12092 | 0 | return 0; |
12093 | 0 | } |
12094 | | |
12095 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8f64_MVT_v2f64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12096 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12097 | 0 | return fastEmitInst_ri(X86::VEXTRACTF32x4Zrr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
12098 | 0 | } |
12099 | 0 | return 0; |
12100 | 0 | } |
12101 | | |
12102 | 0 | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8f64_MVT_v4f64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12103 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12104 | 0 | return fastEmitInst_ri(X86::VEXTRACTF64x4Zrr, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
12105 | 0 | } |
12106 | 0 | return 0; |
12107 | 0 | } |
12108 | | |
12109 | | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12110 | | switch (RetVT.SimpleTy) { |
12111 | | case MVT::v2f64: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8f64_MVT_v2f64_ri(Op0, Op0IsKill, imm1); |
12112 | | case MVT::v4f64: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8f64_MVT_v4f64_ri(Op0, Op0IsKill, imm1); |
12113 | | default: return 0; |
12114 | | } |
12115 | | } |
12116 | | |
12117 | | unsigned fastEmit_ISD_EXTRACT_SUBVECTOR_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12118 | | switch (VT.SimpleTy) { |
12119 | | case MVT::v32i8: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v32i8_ri(RetVT, Op0, Op0IsKill, imm1); |
12120 | | case MVT::v64i8: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v64i8_ri(RetVT, Op0, Op0IsKill, imm1); |
12121 | | case MVT::v16i16: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12122 | | case MVT::v32i16: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v32i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12123 | | case MVT::v8i32: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12124 | | case MVT::v16i32: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12125 | | case MVT::v4i64: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v4i64_ri(RetVT, Op0, Op0IsKill, imm1); |
12126 | | case MVT::v8i64: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8i64_ri(RetVT, Op0, Op0IsKill, imm1); |
12127 | | case MVT::v8f32: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12128 | | case MVT::v16f32: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v16f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12129 | | case MVT::v4f64: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v4f64_ri(RetVT, Op0, Op0IsKill, imm1); |
12130 | | case MVT::v8f64: return fastEmit_ISD_EXTRACT_SUBVECTOR_MVT_v8f64_ri(RetVT, Op0, Op0IsKill, imm1); |
12131 | | default: return 0; |
12132 | | } |
12133 | | } |
12134 | | |
12135 | | // FastEmit functions for ISD::EXTRACT_VECTOR_ELT. |
12136 | | |
12137 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12138 | 0 | if (RetVT.SimpleTy != MVT::i32) |
12139 | 0 | return 0; |
12140 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
12141 | 0 | return fastEmitInst_ri(X86::VPEXTRDZrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12142 | 0 | } |
12143 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
12144 | 0 | return fastEmitInst_ri(X86::PEXTRDrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12145 | 0 | } |
12146 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasDQI())0 ) { |
12147 | 0 | return fastEmitInst_ri(X86::VPEXTRDrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12148 | 0 | } |
12149 | 0 | return 0; |
12150 | 0 | } |
12151 | | |
12152 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12153 | 0 | if (RetVT.SimpleTy != MVT::i64) |
12154 | 0 | return 0; |
12155 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
12156 | 0 | return fastEmitInst_ri(X86::VPEXTRQZrr, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
12157 | 0 | } |
12158 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
12159 | 0 | return fastEmitInst_ri(X86::PEXTRQrr, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
12160 | 0 | } |
12161 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasDQI())0 ) { |
12162 | 0 | return fastEmitInst_ri(X86::VPEXTRQrr, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
12163 | 0 | } |
12164 | 0 | return 0; |
12165 | 0 | } |
12166 | | |
12167 | | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12168 | | switch (VT.SimpleTy) { |
12169 | | case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12170 | | case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); |
12171 | | default: return 0; |
12172 | | } |
12173 | | } |
12174 | | |
12175 | | // FastEmit functions for ISD::MUL. |
12176 | | |
12177 | 0 | unsigned fastEmit_ISD_MUL_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12178 | 0 | if (RetVT.SimpleTy != MVT::i16) |
12179 | 0 | return 0; |
12180 | 0 | return fastEmitInst_ri(X86::IMUL16rri, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
12181 | 0 | } |
12182 | | |
12183 | 0 | unsigned fastEmit_ISD_MUL_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12184 | 0 | if (RetVT.SimpleTy != MVT::i32) |
12185 | 0 | return 0; |
12186 | 0 | return fastEmitInst_ri(X86::IMUL32rri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12187 | 0 | } |
12188 | | |
12189 | 2 | unsigned fastEmit_ISD_MUL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12190 | 2 | switch (VT.SimpleTy) { |
12191 | 0 | case MVT::i16: return fastEmit_ISD_MUL_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12192 | 0 | case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12193 | 2 | default: return 0; |
12194 | 2 | } |
12195 | 2 | } |
12196 | | |
12197 | | // FastEmit functions for ISD::OR. |
12198 | | |
12199 | 1 | unsigned fastEmit_ISD_OR_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12200 | 1 | if (RetVT.SimpleTy != MVT::i8) |
12201 | 0 | return 0; |
12202 | 1 | return fastEmitInst_ri(X86::OR8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1); |
12203 | 1 | } |
12204 | | |
12205 | 0 | unsigned fastEmit_ISD_OR_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12206 | 0 | if (RetVT.SimpleTy != MVT::i16) |
12207 | 0 | return 0; |
12208 | 0 | return fastEmitInst_ri(X86::OR16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
12209 | 0 | } |
12210 | | |
12211 | 0 | unsigned fastEmit_ISD_OR_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12212 | 0 | if (RetVT.SimpleTy != MVT::i32) |
12213 | 0 | return 0; |
12214 | 0 | return fastEmitInst_ri(X86::OR32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12215 | 0 | } |
12216 | | |
12217 | 13 | unsigned fastEmit_ISD_OR_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12218 | 13 | switch (VT.SimpleTy) { |
12219 | 1 | case MVT::i8: return fastEmit_ISD_OR_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1); |
12220 | 0 | case MVT::i16: return fastEmit_ISD_OR_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12221 | 0 | case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12222 | 12 | default: return 0; |
12223 | 13 | } |
12224 | 13 | } |
12225 | | |
12226 | | // FastEmit functions for ISD::ROTL. |
12227 | | |
12228 | 0 | unsigned fastEmit_ISD_ROTL_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12229 | 0 | if (RetVT.SimpleTy != MVT::i8) |
12230 | 0 | return 0; |
12231 | 0 | return fastEmitInst_ri(X86::ROL8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1); |
12232 | 0 | } |
12233 | | |
12234 | 0 | unsigned fastEmit_ISD_ROTL_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12235 | 0 | if (RetVT.SimpleTy != MVT::i16) |
12236 | 0 | return 0; |
12237 | 0 | return fastEmitInst_ri(X86::ROL16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
12238 | 0 | } |
12239 | | |
12240 | 0 | unsigned fastEmit_ISD_ROTL_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12241 | 0 | if (RetVT.SimpleTy != MVT::i32) |
12242 | 0 | return 0; |
12243 | 0 | return fastEmitInst_ri(X86::ROL32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12244 | 0 | } |
12245 | | |
12246 | 0 | unsigned fastEmit_ISD_ROTL_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12247 | 0 | if (RetVT.SimpleTy != MVT::i64) |
12248 | 0 | return 0; |
12249 | 0 | return fastEmitInst_ri(X86::ROL64ri, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
12250 | 0 | } |
12251 | | |
12252 | | unsigned fastEmit_ISD_ROTL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12253 | | switch (VT.SimpleTy) { |
12254 | | case MVT::i8: return fastEmit_ISD_ROTL_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1); |
12255 | | case MVT::i16: return fastEmit_ISD_ROTL_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12256 | | case MVT::i32: return fastEmit_ISD_ROTL_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12257 | | case MVT::i64: return fastEmit_ISD_ROTL_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1); |
12258 | | default: return 0; |
12259 | | } |
12260 | | } |
12261 | | |
12262 | | // FastEmit functions for ISD::SHL. |
12263 | | |
12264 | 0 | unsigned fastEmit_ISD_SHL_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12265 | 0 | if (RetVT.SimpleTy != MVT::i8) |
12266 | 0 | return 0; |
12267 | 0 | return fastEmitInst_ri(X86::SHL8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1); |
12268 | 0 | } |
12269 | | |
12270 | 2 | unsigned fastEmit_ISD_SHL_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12271 | 2 | if (RetVT.SimpleTy != MVT::i16) |
12272 | 0 | return 0; |
12273 | 2 | return fastEmitInst_ri(X86::SHL16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
12274 | 2 | } |
12275 | | |
12276 | 23 | unsigned fastEmit_ISD_SHL_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12277 | 23 | if (RetVT.SimpleTy != MVT::i32) |
12278 | 0 | return 0; |
12279 | 23 | return fastEmitInst_ri(X86::SHL32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12280 | 23 | } |
12281 | | |
12282 | 6 | unsigned fastEmit_ISD_SHL_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12283 | 6 | if (RetVT.SimpleTy != MVT::i64) |
12284 | 0 | return 0; |
12285 | 6 | return fastEmitInst_ri(X86::SHL64ri, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
12286 | 6 | } |
12287 | | |
12288 | 31 | unsigned fastEmit_ISD_SHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12289 | 31 | switch (VT.SimpleTy) { |
12290 | 0 | case MVT::i8: return fastEmit_ISD_SHL_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1); |
12291 | 2 | case MVT::i16: return fastEmit_ISD_SHL_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12292 | 23 | case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12293 | 6 | case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1); |
12294 | 0 | default: return 0; |
12295 | 31 | } |
12296 | 31 | } |
12297 | | |
12298 | | // FastEmit functions for ISD::SRA. |
12299 | | |
12300 | 0 | unsigned fastEmit_ISD_SRA_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12301 | 0 | if (RetVT.SimpleTy != MVT::i8) |
12302 | 0 | return 0; |
12303 | 0 | return fastEmitInst_ri(X86::SAR8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1); |
12304 | 0 | } |
12305 | | |
12306 | 0 | unsigned fastEmit_ISD_SRA_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12307 | 0 | if (RetVT.SimpleTy != MVT::i16) |
12308 | 0 | return 0; |
12309 | 0 | return fastEmitInst_ri(X86::SAR16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
12310 | 0 | } |
12311 | | |
12312 | 3 | unsigned fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12313 | 3 | if (RetVT.SimpleTy != MVT::i32) |
12314 | 0 | return 0; |
12315 | 3 | return fastEmitInst_ri(X86::SAR32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12316 | 3 | } |
12317 | | |
12318 | 1 | unsigned fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12319 | 1 | if (RetVT.SimpleTy != MVT::i64) |
12320 | 0 | return 0; |
12321 | 1 | return fastEmitInst_ri(X86::SAR64ri, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
12322 | 1 | } |
12323 | | |
12324 | 4 | unsigned fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12325 | 4 | switch (VT.SimpleTy) { |
12326 | 0 | case MVT::i8: return fastEmit_ISD_SRA_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1); |
12327 | 0 | case MVT::i16: return fastEmit_ISD_SRA_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12328 | 3 | case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12329 | 1 | case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1); |
12330 | 0 | default: return 0; |
12331 | 4 | } |
12332 | 4 | } |
12333 | | |
12334 | | // FastEmit functions for ISD::SRL. |
12335 | | |
12336 | 0 | unsigned fastEmit_ISD_SRL_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12337 | 0 | if (RetVT.SimpleTy != MVT::i8) |
12338 | 0 | return 0; |
12339 | 0 | return fastEmitInst_ri(X86::SHR8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1); |
12340 | 0 | } |
12341 | | |
12342 | 1 | unsigned fastEmit_ISD_SRL_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12343 | 1 | if (RetVT.SimpleTy != MVT::i16) |
12344 | 0 | return 0; |
12345 | 1 | return fastEmitInst_ri(X86::SHR16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
12346 | 1 | } |
12347 | | |
12348 | 5 | unsigned fastEmit_ISD_SRL_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12349 | 5 | if (RetVT.SimpleTy != MVT::i32) |
12350 | 0 | return 0; |
12351 | 5 | return fastEmitInst_ri(X86::SHR32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12352 | 5 | } |
12353 | | |
12354 | 21 | unsigned fastEmit_ISD_SRL_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12355 | 21 | if (RetVT.SimpleTy != MVT::i64) |
12356 | 0 | return 0; |
12357 | 21 | return fastEmitInst_ri(X86::SHR64ri, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
12358 | 21 | } |
12359 | | |
12360 | 27 | unsigned fastEmit_ISD_SRL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12361 | 27 | switch (VT.SimpleTy) { |
12362 | 0 | case MVT::i8: return fastEmit_ISD_SRL_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1); |
12363 | 1 | case MVT::i16: return fastEmit_ISD_SRL_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12364 | 5 | case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12365 | 21 | case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1); |
12366 | 0 | default: return 0; |
12367 | 27 | } |
12368 | 27 | } |
12369 | | |
12370 | | // FastEmit functions for ISD::SUB. |
12371 | | |
12372 | 0 | unsigned fastEmit_ISD_SUB_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12373 | 0 | if (RetVT.SimpleTy != MVT::i8) |
12374 | 0 | return 0; |
12375 | 0 | return fastEmitInst_ri(X86::SUB8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1); |
12376 | 0 | } |
12377 | | |
12378 | 0 | unsigned fastEmit_ISD_SUB_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12379 | 0 | if (RetVT.SimpleTy != MVT::i16) |
12380 | 0 | return 0; |
12381 | 0 | return fastEmitInst_ri(X86::SUB16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
12382 | 0 | } |
12383 | | |
12384 | 1 | unsigned fastEmit_ISD_SUB_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12385 | 1 | if (RetVT.SimpleTy != MVT::i32) |
12386 | 0 | return 0; |
12387 | 1 | return fastEmitInst_ri(X86::SUB32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12388 | 1 | } |
12389 | | |
12390 | 1 | unsigned fastEmit_ISD_SUB_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12391 | 1 | switch (VT.SimpleTy) { |
12392 | 0 | case MVT::i8: return fastEmit_ISD_SUB_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1); |
12393 | 0 | case MVT::i16: return fastEmit_ISD_SUB_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12394 | 1 | case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12395 | 0 | default: return 0; |
12396 | 1 | } |
12397 | 1 | } |
12398 | | |
12399 | | // FastEmit functions for ISD::XOR. |
12400 | | |
12401 | 5 | unsigned fastEmit_ISD_XOR_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12402 | 5 | if (RetVT.SimpleTy != MVT::i8) |
12403 | 0 | return 0; |
12404 | 5 | return fastEmitInst_ri(X86::XOR8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1); |
12405 | 5 | } |
12406 | | |
12407 | 0 | unsigned fastEmit_ISD_XOR_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12408 | 0 | if (RetVT.SimpleTy != MVT::i16) |
12409 | 0 | return 0; |
12410 | 0 | return fastEmitInst_ri(X86::XOR16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
12411 | 0 | } |
12412 | | |
12413 | 2 | unsigned fastEmit_ISD_XOR_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12414 | 2 | if (RetVT.SimpleTy != MVT::i32) |
12415 | 0 | return 0; |
12416 | 2 | return fastEmitInst_ri(X86::XOR32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12417 | 2 | } |
12418 | | |
12419 | 10 | unsigned fastEmit_ISD_XOR_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12420 | 10 | switch (VT.SimpleTy) { |
12421 | 5 | case MVT::i8: return fastEmit_ISD_XOR_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1); |
12422 | 0 | case MVT::i16: return fastEmit_ISD_XOR_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12423 | 2 | case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12424 | 3 | default: return 0; |
12425 | 10 | } |
12426 | 10 | } |
12427 | | |
12428 | | // FastEmit functions for X86ISD::CVTP2SI_RND. |
12429 | | |
12430 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_RND_MVT_v8f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12431 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
12432 | 0 | return 0; |
12433 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
12434 | 0 | return fastEmitInst_ri(X86::VCVTPS2QQZrrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12435 | 0 | } |
12436 | 0 | return 0; |
12437 | 0 | } |
12438 | | |
12439 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_RND_MVT_v16f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12440 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
12441 | 0 | return 0; |
12442 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
12443 | 0 | return fastEmitInst_ri(X86::VCVTPS2DQZrrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12444 | 0 | } |
12445 | 0 | return 0; |
12446 | 0 | } |
12447 | | |
12448 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_RND_MVT_v8f64_MVT_v8i32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12449 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12450 | 0 | return fastEmitInst_ri(X86::VCVTPD2DQZrrb, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
12451 | 0 | } |
12452 | 0 | return 0; |
12453 | 0 | } |
12454 | | |
12455 | 0 | unsigned fastEmit_X86ISD_CVTP2SI_RND_MVT_v8f64_MVT_v8i64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12456 | 0 | if ((Subtarget->hasDQI())0 ) { |
12457 | 0 | return fastEmitInst_ri(X86::VCVTPD2QQZrrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12458 | 0 | } |
12459 | 0 | return 0; |
12460 | 0 | } |
12461 | | |
12462 | | unsigned fastEmit_X86ISD_CVTP2SI_RND_MVT_v8f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12463 | | switch (RetVT.SimpleTy) { |
12464 | | case MVT::v8i32: return fastEmit_X86ISD_CVTP2SI_RND_MVT_v8f64_MVT_v8i32_ri(Op0, Op0IsKill, imm1); |
12465 | | case MVT::v8i64: return fastEmit_X86ISD_CVTP2SI_RND_MVT_v8f64_MVT_v8i64_ri(Op0, Op0IsKill, imm1); |
12466 | | default: return 0; |
12467 | | } |
12468 | | } |
12469 | | |
12470 | | unsigned fastEmit_X86ISD_CVTP2SI_RND_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12471 | | switch (VT.SimpleTy) { |
12472 | | case MVT::v8f32: return fastEmit_X86ISD_CVTP2SI_RND_MVT_v8f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12473 | | case MVT::v16f32: return fastEmit_X86ISD_CVTP2SI_RND_MVT_v16f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12474 | | case MVT::v8f64: return fastEmit_X86ISD_CVTP2SI_RND_MVT_v8f64_ri(RetVT, Op0, Op0IsKill, imm1); |
12475 | | default: return 0; |
12476 | | } |
12477 | | } |
12478 | | |
12479 | | // FastEmit functions for X86ISD::CVTP2UI_RND. |
12480 | | |
12481 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_RND_MVT_v8f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12482 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
12483 | 0 | return 0; |
12484 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
12485 | 0 | return fastEmitInst_ri(X86::VCVTPS2UQQZrrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12486 | 0 | } |
12487 | 0 | return 0; |
12488 | 0 | } |
12489 | | |
12490 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_RND_MVT_v16f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12491 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
12492 | 0 | return 0; |
12493 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
12494 | 0 | return fastEmitInst_ri(X86::VCVTPS2UDQZrrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12495 | 0 | } |
12496 | 0 | return 0; |
12497 | 0 | } |
12498 | | |
12499 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_RND_MVT_v8f64_MVT_v8i32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12500 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12501 | 0 | return fastEmitInst_ri(X86::VCVTPD2UDQZrrb, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
12502 | 0 | } |
12503 | 0 | return 0; |
12504 | 0 | } |
12505 | | |
12506 | 0 | unsigned fastEmit_X86ISD_CVTP2UI_RND_MVT_v8f64_MVT_v8i64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12507 | 0 | if ((Subtarget->hasDQI())0 ) { |
12508 | 0 | return fastEmitInst_ri(X86::VCVTPD2UQQZrrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12509 | 0 | } |
12510 | 0 | return 0; |
12511 | 0 | } |
12512 | | |
12513 | | unsigned fastEmit_X86ISD_CVTP2UI_RND_MVT_v8f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12514 | | switch (RetVT.SimpleTy) { |
12515 | | case MVT::v8i32: return fastEmit_X86ISD_CVTP2UI_RND_MVT_v8f64_MVT_v8i32_ri(Op0, Op0IsKill, imm1); |
12516 | | case MVT::v8i64: return fastEmit_X86ISD_CVTP2UI_RND_MVT_v8f64_MVT_v8i64_ri(Op0, Op0IsKill, imm1); |
12517 | | default: return 0; |
12518 | | } |
12519 | | } |
12520 | | |
12521 | | unsigned fastEmit_X86ISD_CVTP2UI_RND_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12522 | | switch (VT.SimpleTy) { |
12523 | | case MVT::v8f32: return fastEmit_X86ISD_CVTP2UI_RND_MVT_v8f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12524 | | case MVT::v16f32: return fastEmit_X86ISD_CVTP2UI_RND_MVT_v16f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12525 | | case MVT::v8f64: return fastEmit_X86ISD_CVTP2UI_RND_MVT_v8f64_ri(RetVT, Op0, Op0IsKill, imm1); |
12526 | | default: return 0; |
12527 | | } |
12528 | | } |
12529 | | |
12530 | | // FastEmit functions for X86ISD::CVTPS2PH. |
12531 | | |
12532 | 0 | unsigned fastEmit_X86ISD_CVTPS2PH_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12533 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
12534 | 0 | return 0; |
12535 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
12536 | 0 | return fastEmitInst_ri(X86::VCVTPS2PHZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
12537 | 0 | } |
12538 | 0 | return 0; |
12539 | 0 | } |
12540 | | |
12541 | 0 | unsigned fastEmit_X86ISD_CVTPS2PH_MVT_v8f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12542 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
12543 | 0 | return 0; |
12544 | 0 | if (0 (Subtarget->hasVLX())0 ) { |
12545 | 0 | return fastEmitInst_ri(X86::VCVTPS2PHZ256rr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
12546 | 0 | } |
12547 | 0 | return 0; |
12548 | 0 | } |
12549 | | |
12550 | 0 | unsigned fastEmit_X86ISD_CVTPS2PH_MVT_v16f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12551 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
12552 | 0 | return 0; |
12553 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
12554 | 0 | return fastEmitInst_ri(X86::VCVTPS2PHZrr, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
12555 | 0 | } |
12556 | 0 | return 0; |
12557 | 0 | } |
12558 | | |
12559 | | unsigned fastEmit_X86ISD_CVTPS2PH_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12560 | | switch (VT.SimpleTy) { |
12561 | | case MVT::v4f32: return fastEmit_X86ISD_CVTPS2PH_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12562 | | case MVT::v8f32: return fastEmit_X86ISD_CVTPS2PH_MVT_v8f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12563 | | case MVT::v16f32: return fastEmit_X86ISD_CVTPS2PH_MVT_v16f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12564 | | default: return 0; |
12565 | | } |
12566 | | } |
12567 | | |
12568 | | // FastEmit functions for X86ISD::CVTS2SI_RND. |
12569 | | |
12570 | 0 | unsigned fastEmit_X86ISD_CVTS2SI_RND_MVT_v4f32_MVT_i32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12571 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12572 | 0 | return fastEmitInst_ri(X86::VCVTSS2SIZrb, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12573 | 0 | } |
12574 | 0 | return 0; |
12575 | 0 | } |
12576 | | |
12577 | 0 | unsigned fastEmit_X86ISD_CVTS2SI_RND_MVT_v4f32_MVT_i64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12578 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12579 | 0 | return fastEmitInst_ri(X86::VCVTSS2SI64Zrb, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
12580 | 0 | } |
12581 | 0 | return 0; |
12582 | 0 | } |
12583 | | |
12584 | | unsigned fastEmit_X86ISD_CVTS2SI_RND_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12585 | | switch (RetVT.SimpleTy) { |
12586 | | case MVT::i32: return fastEmit_X86ISD_CVTS2SI_RND_MVT_v4f32_MVT_i32_ri(Op0, Op0IsKill, imm1); |
12587 | | case MVT::i64: return fastEmit_X86ISD_CVTS2SI_RND_MVT_v4f32_MVT_i64_ri(Op0, Op0IsKill, imm1); |
12588 | | default: return 0; |
12589 | | } |
12590 | | } |
12591 | | |
12592 | 0 | unsigned fastEmit_X86ISD_CVTS2SI_RND_MVT_v2f64_MVT_i32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12593 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12594 | 0 | return fastEmitInst_ri(X86::VCVTSD2SIZrb, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12595 | 0 | } |
12596 | 0 | return 0; |
12597 | 0 | } |
12598 | | |
12599 | 0 | unsigned fastEmit_X86ISD_CVTS2SI_RND_MVT_v2f64_MVT_i64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12600 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12601 | 0 | return fastEmitInst_ri(X86::VCVTSD2SI64Zrb, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
12602 | 0 | } |
12603 | 0 | return 0; |
12604 | 0 | } |
12605 | | |
12606 | | unsigned fastEmit_X86ISD_CVTS2SI_RND_MVT_v2f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12607 | | switch (RetVT.SimpleTy) { |
12608 | | case MVT::i32: return fastEmit_X86ISD_CVTS2SI_RND_MVT_v2f64_MVT_i32_ri(Op0, Op0IsKill, imm1); |
12609 | | case MVT::i64: return fastEmit_X86ISD_CVTS2SI_RND_MVT_v2f64_MVT_i64_ri(Op0, Op0IsKill, imm1); |
12610 | | default: return 0; |
12611 | | } |
12612 | | } |
12613 | | |
12614 | | unsigned fastEmit_X86ISD_CVTS2SI_RND_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12615 | | switch (VT.SimpleTy) { |
12616 | | case MVT::v4f32: return fastEmit_X86ISD_CVTS2SI_RND_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12617 | | case MVT::v2f64: return fastEmit_X86ISD_CVTS2SI_RND_MVT_v2f64_ri(RetVT, Op0, Op0IsKill, imm1); |
12618 | | default: return 0; |
12619 | | } |
12620 | | } |
12621 | | |
12622 | | // FastEmit functions for X86ISD::CVTS2UI_RND. |
12623 | | |
12624 | 0 | unsigned fastEmit_X86ISD_CVTS2UI_RND_MVT_v4f32_MVT_i32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12625 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12626 | 0 | return fastEmitInst_ri(X86::VCVTSS2USIZrb, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12627 | 0 | } |
12628 | 0 | return 0; |
12629 | 0 | } |
12630 | | |
12631 | 0 | unsigned fastEmit_X86ISD_CVTS2UI_RND_MVT_v4f32_MVT_i64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12632 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12633 | 0 | return fastEmitInst_ri(X86::VCVTSS2USI64Zrb, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
12634 | 0 | } |
12635 | 0 | return 0; |
12636 | 0 | } |
12637 | | |
12638 | | unsigned fastEmit_X86ISD_CVTS2UI_RND_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12639 | | switch (RetVT.SimpleTy) { |
12640 | | case MVT::i32: return fastEmit_X86ISD_CVTS2UI_RND_MVT_v4f32_MVT_i32_ri(Op0, Op0IsKill, imm1); |
12641 | | case MVT::i64: return fastEmit_X86ISD_CVTS2UI_RND_MVT_v4f32_MVT_i64_ri(Op0, Op0IsKill, imm1); |
12642 | | default: return 0; |
12643 | | } |
12644 | | } |
12645 | | |
12646 | 0 | unsigned fastEmit_X86ISD_CVTS2UI_RND_MVT_v2f64_MVT_i32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12647 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12648 | 0 | return fastEmitInst_ri(X86::VCVTSD2USIZrb, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12649 | 0 | } |
12650 | 0 | return 0; |
12651 | 0 | } |
12652 | | |
12653 | 0 | unsigned fastEmit_X86ISD_CVTS2UI_RND_MVT_v2f64_MVT_i64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12654 | 0 | if ((Subtarget->hasAVX512())0 ) { |
12655 | 0 | return fastEmitInst_ri(X86::VCVTSD2USI64Zrb, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
12656 | 0 | } |
12657 | 0 | return 0; |
12658 | 0 | } |
12659 | | |
12660 | | unsigned fastEmit_X86ISD_CVTS2UI_RND_MVT_v2f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12661 | | switch (RetVT.SimpleTy) { |
12662 | | case MVT::i32: return fastEmit_X86ISD_CVTS2UI_RND_MVT_v2f64_MVT_i32_ri(Op0, Op0IsKill, imm1); |
12663 | | case MVT::i64: return fastEmit_X86ISD_CVTS2UI_RND_MVT_v2f64_MVT_i64_ri(Op0, Op0IsKill, imm1); |
12664 | | default: return 0; |
12665 | | } |
12666 | | } |
12667 | | |
12668 | | unsigned fastEmit_X86ISD_CVTS2UI_RND_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12669 | | switch (VT.SimpleTy) { |
12670 | | case MVT::v4f32: return fastEmit_X86ISD_CVTS2UI_RND_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12671 | | case MVT::v2f64: return fastEmit_X86ISD_CVTS2UI_RND_MVT_v2f64_ri(RetVT, Op0, Op0IsKill, imm1); |
12672 | | default: return 0; |
12673 | | } |
12674 | | } |
12675 | | |
12676 | | // FastEmit functions for X86ISD::FSQRT_RND. |
12677 | | |
12678 | 0 | unsigned fastEmit_X86ISD_FSQRT_RND_MVT_v16f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12679 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
12680 | 0 | return 0; |
12681 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
12682 | 0 | return fastEmitInst_ri(X86::VSQRTPSZrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12683 | 0 | } |
12684 | 0 | return 0; |
12685 | 0 | } |
12686 | | |
12687 | 0 | unsigned fastEmit_X86ISD_FSQRT_RND_MVT_v8f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12688 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
12689 | 0 | return 0; |
12690 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
12691 | 0 | return fastEmitInst_ri(X86::VSQRTPDZrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12692 | 0 | } |
12693 | 0 | return 0; |
12694 | 0 | } |
12695 | | |
12696 | | unsigned fastEmit_X86ISD_FSQRT_RND_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12697 | | switch (VT.SimpleTy) { |
12698 | | case MVT::v16f32: return fastEmit_X86ISD_FSQRT_RND_MVT_v16f32_ri(RetVT, Op0, Op0IsKill, imm1); |
12699 | | case MVT::v8f64: return fastEmit_X86ISD_FSQRT_RND_MVT_v8f64_ri(RetVT, Op0, Op0IsKill, imm1); |
12700 | | default: return 0; |
12701 | | } |
12702 | | } |
12703 | | |
12704 | | // FastEmit functions for X86ISD::KSHIFTL. |
12705 | | |
12706 | 0 | unsigned fastEmit_X86ISD_KSHIFTL_MVT_v8i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12707 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
12708 | 0 | return 0; |
12709 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
12710 | 0 | return fastEmitInst_ri(X86::KSHIFTLBri, &X86::VK8RegClass, Op0, Op0IsKill, imm1); |
12711 | 0 | } |
12712 | 0 | return 0; |
12713 | 0 | } |
12714 | | |
12715 | 0 | unsigned fastEmit_X86ISD_KSHIFTL_MVT_v16i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12716 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
12717 | 0 | return 0; |
12718 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
12719 | 0 | return fastEmitInst_ri(X86::KSHIFTLWri, &X86::VK16RegClass, Op0, Op0IsKill, imm1); |
12720 | 0 | } |
12721 | 0 | return 0; |
12722 | 0 | } |
12723 | | |
12724 | 0 | unsigned fastEmit_X86ISD_KSHIFTL_MVT_v32i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12725 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
12726 | 0 | return 0; |
12727 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
12728 | 0 | return fastEmitInst_ri(X86::KSHIFTLDri, &X86::VK32RegClass, Op0, Op0IsKill, imm1); |
12729 | 0 | } |
12730 | 0 | return 0; |
12731 | 0 | } |
12732 | | |
12733 | 0 | unsigned fastEmit_X86ISD_KSHIFTL_MVT_v64i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12734 | 0 | if (RetVT.SimpleTy != MVT::v64i1) |
12735 | 0 | return 0; |
12736 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
12737 | 0 | return fastEmitInst_ri(X86::KSHIFTLQri, &X86::VK64RegClass, Op0, Op0IsKill, imm1); |
12738 | 0 | } |
12739 | 0 | return 0; |
12740 | 0 | } |
12741 | | |
12742 | | unsigned fastEmit_X86ISD_KSHIFTL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12743 | | switch (VT.SimpleTy) { |
12744 | | case MVT::v8i1: return fastEmit_X86ISD_KSHIFTL_MVT_v8i1_ri(RetVT, Op0, Op0IsKill, imm1); |
12745 | | case MVT::v16i1: return fastEmit_X86ISD_KSHIFTL_MVT_v16i1_ri(RetVT, Op0, Op0IsKill, imm1); |
12746 | | case MVT::v32i1: return fastEmit_X86ISD_KSHIFTL_MVT_v32i1_ri(RetVT, Op0, Op0IsKill, imm1); |
12747 | | case MVT::v64i1: return fastEmit_X86ISD_KSHIFTL_MVT_v64i1_ri(RetVT, Op0, Op0IsKill, imm1); |
12748 | | default: return 0; |
12749 | | } |
12750 | | } |
12751 | | |
12752 | | // FastEmit functions for X86ISD::KSHIFTR. |
12753 | | |
12754 | 0 | unsigned fastEmit_X86ISD_KSHIFTR_MVT_v8i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12755 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
12756 | 0 | return 0; |
12757 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
12758 | 0 | return fastEmitInst_ri(X86::KSHIFTRBri, &X86::VK8RegClass, Op0, Op0IsKill, imm1); |
12759 | 0 | } |
12760 | 0 | return 0; |
12761 | 0 | } |
12762 | | |
12763 | 0 | unsigned fastEmit_X86ISD_KSHIFTR_MVT_v16i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12764 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
12765 | 0 | return 0; |
12766 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
12767 | 0 | return fastEmitInst_ri(X86::KSHIFTRWri, &X86::VK16RegClass, Op0, Op0IsKill, imm1); |
12768 | 0 | } |
12769 | 0 | return 0; |
12770 | 0 | } |
12771 | | |
12772 | 0 | unsigned fastEmit_X86ISD_KSHIFTR_MVT_v32i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12773 | 0 | if (RetVT.SimpleTy != MVT::v32i1) |
12774 | 0 | return 0; |
12775 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
12776 | 0 | return fastEmitInst_ri(X86::KSHIFTRDri, &X86::VK32RegClass, Op0, Op0IsKill, imm1); |
12777 | 0 | } |
12778 | 0 | return 0; |
12779 | 0 | } |
12780 | | |
12781 | 0 | unsigned fastEmit_X86ISD_KSHIFTR_MVT_v64i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12782 | 0 | if (RetVT.SimpleTy != MVT::v64i1) |
12783 | 0 | return 0; |
12784 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
12785 | 0 | return fastEmitInst_ri(X86::KSHIFTRQri, &X86::VK64RegClass, Op0, Op0IsKill, imm1); |
12786 | 0 | } |
12787 | 0 | return 0; |
12788 | 0 | } |
12789 | | |
12790 | | unsigned fastEmit_X86ISD_KSHIFTR_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12791 | | switch (VT.SimpleTy) { |
12792 | | case MVT::v8i1: return fastEmit_X86ISD_KSHIFTR_MVT_v8i1_ri(RetVT, Op0, Op0IsKill, imm1); |
12793 | | case MVT::v16i1: return fastEmit_X86ISD_KSHIFTR_MVT_v16i1_ri(RetVT, Op0, Op0IsKill, imm1); |
12794 | | case MVT::v32i1: return fastEmit_X86ISD_KSHIFTR_MVT_v32i1_ri(RetVT, Op0, Op0IsKill, imm1); |
12795 | | case MVT::v64i1: return fastEmit_X86ISD_KSHIFTR_MVT_v64i1_ri(RetVT, Op0, Op0IsKill, imm1); |
12796 | | default: return 0; |
12797 | | } |
12798 | | } |
12799 | | |
12800 | | // FastEmit functions for X86ISD::PEXTRB. |
12801 | | |
12802 | 0 | unsigned fastEmit_X86ISD_PEXTRB_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12803 | 0 | if (RetVT.SimpleTy != MVT::i32) |
12804 | 0 | return 0; |
12805 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
12806 | 0 | return fastEmitInst_ri(X86::VPEXTRBZrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12807 | 0 | } |
12808 | 0 | if (0 (Subtarget->hasSSE41() && 0 !Subtarget->hasAVX()0 )) { |
12809 | 0 | return fastEmitInst_ri(X86::PEXTRBrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12810 | 0 | } |
12811 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasBWI())0 ) { |
12812 | 0 | return fastEmitInst_ri(X86::VPEXTRBrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12813 | 0 | } |
12814 | 0 | return 0; |
12815 | 0 | } |
12816 | | |
12817 | | unsigned fastEmit_X86ISD_PEXTRB_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12818 | | switch (VT.SimpleTy) { |
12819 | | case MVT::v16i8: return fastEmit_X86ISD_PEXTRB_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); |
12820 | | default: return 0; |
12821 | | } |
12822 | | } |
12823 | | |
12824 | | // FastEmit functions for X86ISD::PEXTRW. |
12825 | | |
12826 | 0 | unsigned fastEmit_X86ISD_PEXTRW_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12827 | 0 | if (RetVT.SimpleTy != MVT::i32) |
12828 | 0 | return 0; |
12829 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
12830 | 0 | return fastEmitInst_ri(X86::VPEXTRWZrr, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12831 | 0 | } |
12832 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
12833 | 0 | return fastEmitInst_ri(X86::PEXTRWri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12834 | 0 | } |
12835 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasBWI())0 ) { |
12836 | 0 | return fastEmitInst_ri(X86::VPEXTRWri, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
12837 | 0 | } |
12838 | 0 | return 0; |
12839 | 0 | } |
12840 | | |
12841 | | unsigned fastEmit_X86ISD_PEXTRW_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12842 | | switch (VT.SimpleTy) { |
12843 | | case MVT::v8i16: return fastEmit_X86ISD_PEXTRW_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12844 | | default: return 0; |
12845 | | } |
12846 | | } |
12847 | | |
12848 | | // FastEmit functions for X86ISD::PSHUFD. |
12849 | | |
12850 | 0 | unsigned fastEmit_X86ISD_PSHUFD_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12851 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
12852 | 0 | return 0; |
12853 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
12854 | 0 | return fastEmitInst_ri(X86::VPSHUFDZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
12855 | 0 | } |
12856 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
12857 | 0 | return fastEmitInst_ri(X86::PSHUFDri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
12858 | 0 | } |
12859 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
12860 | 0 | return fastEmitInst_ri(X86::VPSHUFDri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
12861 | 0 | } |
12862 | 0 | return 0; |
12863 | 0 | } |
12864 | | |
12865 | 0 | unsigned fastEmit_X86ISD_PSHUFD_MVT_v8i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12866 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
12867 | 0 | return 0; |
12868 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
12869 | 0 | return fastEmitInst_ri(X86::VPSHUFDZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
12870 | 0 | } |
12871 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
12872 | 0 | return fastEmitInst_ri(X86::VPSHUFDYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
12873 | 0 | } |
12874 | 0 | return 0; |
12875 | 0 | } |
12876 | | |
12877 | 0 | unsigned fastEmit_X86ISD_PSHUFD_MVT_v16i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12878 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
12879 | 0 | return 0; |
12880 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
12881 | 0 | return fastEmitInst_ri(X86::VPSHUFDZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12882 | 0 | } |
12883 | 0 | return 0; |
12884 | 0 | } |
12885 | | |
12886 | | unsigned fastEmit_X86ISD_PSHUFD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12887 | | switch (VT.SimpleTy) { |
12888 | | case MVT::v4i32: return fastEmit_X86ISD_PSHUFD_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12889 | | case MVT::v8i32: return fastEmit_X86ISD_PSHUFD_MVT_v8i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12890 | | case MVT::v16i32: return fastEmit_X86ISD_PSHUFD_MVT_v16i32_ri(RetVT, Op0, Op0IsKill, imm1); |
12891 | | default: return 0; |
12892 | | } |
12893 | | } |
12894 | | |
12895 | | // FastEmit functions for X86ISD::PSHUFHW. |
12896 | | |
12897 | 0 | unsigned fastEmit_X86ISD_PSHUFHW_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12898 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
12899 | 0 | return 0; |
12900 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
12901 | 0 | return fastEmitInst_ri(X86::VPSHUFHWZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
12902 | 0 | } |
12903 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
12904 | 0 | return fastEmitInst_ri(X86::PSHUFHWri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
12905 | 0 | } |
12906 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
12907 | 0 | return fastEmitInst_ri(X86::VPSHUFHWri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
12908 | 0 | } |
12909 | 0 | return 0; |
12910 | 0 | } |
12911 | | |
12912 | 0 | unsigned fastEmit_X86ISD_PSHUFHW_MVT_v16i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12913 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
12914 | 0 | return 0; |
12915 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
12916 | 0 | return fastEmitInst_ri(X86::VPSHUFHWZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
12917 | 0 | } |
12918 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
12919 | 0 | return fastEmitInst_ri(X86::VPSHUFHWYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
12920 | 0 | } |
12921 | 0 | return 0; |
12922 | 0 | } |
12923 | | |
12924 | 0 | unsigned fastEmit_X86ISD_PSHUFHW_MVT_v32i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12925 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
12926 | 0 | return 0; |
12927 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
12928 | 0 | return fastEmitInst_ri(X86::VPSHUFHWZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12929 | 0 | } |
12930 | 0 | return 0; |
12931 | 0 | } |
12932 | | |
12933 | | unsigned fastEmit_X86ISD_PSHUFHW_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12934 | | switch (VT.SimpleTy) { |
12935 | | case MVT::v8i16: return fastEmit_X86ISD_PSHUFHW_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12936 | | case MVT::v16i16: return fastEmit_X86ISD_PSHUFHW_MVT_v16i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12937 | | case MVT::v32i16: return fastEmit_X86ISD_PSHUFHW_MVT_v32i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12938 | | default: return 0; |
12939 | | } |
12940 | | } |
12941 | | |
12942 | | // FastEmit functions for X86ISD::PSHUFLW. |
12943 | | |
12944 | 0 | unsigned fastEmit_X86ISD_PSHUFLW_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12945 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
12946 | 0 | return 0; |
12947 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
12948 | 0 | return fastEmitInst_ri(X86::VPSHUFLWZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
12949 | 0 | } |
12950 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
12951 | 0 | return fastEmitInst_ri(X86::PSHUFLWri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
12952 | 0 | } |
12953 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
12954 | 0 | return fastEmitInst_ri(X86::VPSHUFLWri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
12955 | 0 | } |
12956 | 0 | return 0; |
12957 | 0 | } |
12958 | | |
12959 | 0 | unsigned fastEmit_X86ISD_PSHUFLW_MVT_v16i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12960 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
12961 | 0 | return 0; |
12962 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
12963 | 0 | return fastEmitInst_ri(X86::VPSHUFLWZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
12964 | 0 | } |
12965 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
12966 | 0 | return fastEmitInst_ri(X86::VPSHUFLWYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
12967 | 0 | } |
12968 | 0 | return 0; |
12969 | 0 | } |
12970 | | |
12971 | 0 | unsigned fastEmit_X86ISD_PSHUFLW_MVT_v32i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12972 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
12973 | 0 | return 0; |
12974 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
12975 | 0 | return fastEmitInst_ri(X86::VPSHUFLWZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12976 | 0 | } |
12977 | 0 | return 0; |
12978 | 0 | } |
12979 | | |
12980 | | unsigned fastEmit_X86ISD_PSHUFLW_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12981 | | switch (VT.SimpleTy) { |
12982 | | case MVT::v8i16: return fastEmit_X86ISD_PSHUFLW_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12983 | | case MVT::v16i16: return fastEmit_X86ISD_PSHUFLW_MVT_v16i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12984 | | case MVT::v32i16: return fastEmit_X86ISD_PSHUFLW_MVT_v32i16_ri(RetVT, Op0, Op0IsKill, imm1); |
12985 | | default: return 0; |
12986 | | } |
12987 | | } |
12988 | | |
12989 | | // FastEmit functions for X86ISD::SINT_TO_FP_RND. |
12990 | | |
12991 | 0 | unsigned fastEmit_X86ISD_SINT_TO_FP_RND_MVT_v16i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
12992 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
12993 | 0 | return 0; |
12994 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
12995 | 0 | return fastEmitInst_ri(X86::VCVTDQ2PSZrrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
12996 | 0 | } |
12997 | 0 | return 0; |
12998 | 0 | } |
12999 | | |
13000 | 0 | unsigned fastEmit_X86ISD_SINT_TO_FP_RND_MVT_v8i64_MVT_v8f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13001 | 0 | if ((Subtarget->hasDQI())0 ) { |
13002 | 0 | return fastEmitInst_ri(X86::VCVTQQ2PSZrrb, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13003 | 0 | } |
13004 | 0 | return 0; |
13005 | 0 | } |
13006 | | |
13007 | 0 | unsigned fastEmit_X86ISD_SINT_TO_FP_RND_MVT_v8i64_MVT_v8f64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13008 | 0 | if ((Subtarget->hasDQI())0 ) { |
13009 | 0 | return fastEmitInst_ri(X86::VCVTQQ2PDZrrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13010 | 0 | } |
13011 | 0 | return 0; |
13012 | 0 | } |
13013 | | |
13014 | | unsigned fastEmit_X86ISD_SINT_TO_FP_RND_MVT_v8i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13015 | | switch (RetVT.SimpleTy) { |
13016 | | case MVT::v8f32: return fastEmit_X86ISD_SINT_TO_FP_RND_MVT_v8i64_MVT_v8f32_ri(Op0, Op0IsKill, imm1); |
13017 | | case MVT::v8f64: return fastEmit_X86ISD_SINT_TO_FP_RND_MVT_v8i64_MVT_v8f64_ri(Op0, Op0IsKill, imm1); |
13018 | | default: return 0; |
13019 | | } |
13020 | | } |
13021 | | |
13022 | | unsigned fastEmit_X86ISD_SINT_TO_FP_RND_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13023 | | switch (VT.SimpleTy) { |
13024 | | case MVT::v16i32: return fastEmit_X86ISD_SINT_TO_FP_RND_MVT_v16i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13025 | | case MVT::v8i64: return fastEmit_X86ISD_SINT_TO_FP_RND_MVT_v8i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13026 | | default: return 0; |
13027 | | } |
13028 | | } |
13029 | | |
13030 | | // FastEmit functions for X86ISD::UINT_TO_FP_RND. |
13031 | | |
13032 | 0 | unsigned fastEmit_X86ISD_UINT_TO_FP_RND_MVT_v16i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13033 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
13034 | 0 | return 0; |
13035 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13036 | 0 | return fastEmitInst_ri(X86::VCVTUDQ2PSZrrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13037 | 0 | } |
13038 | 0 | return 0; |
13039 | 0 | } |
13040 | | |
13041 | 0 | unsigned fastEmit_X86ISD_UINT_TO_FP_RND_MVT_v8i64_MVT_v8f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13042 | 0 | if ((Subtarget->hasDQI())0 ) { |
13043 | 0 | return fastEmitInst_ri(X86::VCVTUQQ2PSZrrb, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13044 | 0 | } |
13045 | 0 | return 0; |
13046 | 0 | } |
13047 | | |
13048 | 0 | unsigned fastEmit_X86ISD_UINT_TO_FP_RND_MVT_v8i64_MVT_v8f64_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13049 | 0 | if ((Subtarget->hasDQI())0 ) { |
13050 | 0 | return fastEmitInst_ri(X86::VCVTUQQ2PDZrrb, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13051 | 0 | } |
13052 | 0 | return 0; |
13053 | 0 | } |
13054 | | |
13055 | | unsigned fastEmit_X86ISD_UINT_TO_FP_RND_MVT_v8i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13056 | | switch (RetVT.SimpleTy) { |
13057 | | case MVT::v8f32: return fastEmit_X86ISD_UINT_TO_FP_RND_MVT_v8i64_MVT_v8f32_ri(Op0, Op0IsKill, imm1); |
13058 | | case MVT::v8f64: return fastEmit_X86ISD_UINT_TO_FP_RND_MVT_v8i64_MVT_v8f64_ri(Op0, Op0IsKill, imm1); |
13059 | | default: return 0; |
13060 | | } |
13061 | | } |
13062 | | |
13063 | | unsigned fastEmit_X86ISD_UINT_TO_FP_RND_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13064 | | switch (VT.SimpleTy) { |
13065 | | case MVT::v16i32: return fastEmit_X86ISD_UINT_TO_FP_RND_MVT_v16i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13066 | | case MVT::v8i64: return fastEmit_X86ISD_UINT_TO_FP_RND_MVT_v8i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13067 | | default: return 0; |
13068 | | } |
13069 | | } |
13070 | | |
13071 | | // FastEmit functions for X86ISD::VFPCLASS. |
13072 | | |
13073 | 0 | unsigned fastEmit_X86ISD_VFPCLASS_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13074 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
13075 | 0 | return 0; |
13076 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
13077 | 0 | return fastEmitInst_ri(X86::VFPCLASSPSZ128rr, &X86::VK4RegClass, Op0, Op0IsKill, imm1); |
13078 | 0 | } |
13079 | 0 | return 0; |
13080 | 0 | } |
13081 | | |
13082 | 0 | unsigned fastEmit_X86ISD_VFPCLASS_MVT_v8f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13083 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
13084 | 0 | return 0; |
13085 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
13086 | 0 | return fastEmitInst_ri(X86::VFPCLASSPSZ256rr, &X86::VK8RegClass, Op0, Op0IsKill, imm1); |
13087 | 0 | } |
13088 | 0 | return 0; |
13089 | 0 | } |
13090 | | |
13091 | 0 | unsigned fastEmit_X86ISD_VFPCLASS_MVT_v16f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13092 | 0 | if (RetVT.SimpleTy != MVT::v16i1) |
13093 | 0 | return 0; |
13094 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
13095 | 0 | return fastEmitInst_ri(X86::VFPCLASSPSZrr, &X86::VK16RegClass, Op0, Op0IsKill, imm1); |
13096 | 0 | } |
13097 | 0 | return 0; |
13098 | 0 | } |
13099 | | |
13100 | 0 | unsigned fastEmit_X86ISD_VFPCLASS_MVT_v2f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13101 | 0 | if (RetVT.SimpleTy != MVT::v2i1) |
13102 | 0 | return 0; |
13103 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
13104 | 0 | return fastEmitInst_ri(X86::VFPCLASSPDZ128rr, &X86::VK2RegClass, Op0, Op0IsKill, imm1); |
13105 | 0 | } |
13106 | 0 | return 0; |
13107 | 0 | } |
13108 | | |
13109 | 0 | unsigned fastEmit_X86ISD_VFPCLASS_MVT_v4f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13110 | 0 | if (RetVT.SimpleTy != MVT::v4i1) |
13111 | 0 | return 0; |
13112 | 0 | if (0 (Subtarget->hasDQI()) && 0 (Subtarget->hasVLX())0 ) { |
13113 | 0 | return fastEmitInst_ri(X86::VFPCLASSPDZ256rr, &X86::VK4RegClass, Op0, Op0IsKill, imm1); |
13114 | 0 | } |
13115 | 0 | return 0; |
13116 | 0 | } |
13117 | | |
13118 | 0 | unsigned fastEmit_X86ISD_VFPCLASS_MVT_v8f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13119 | 0 | if (RetVT.SimpleTy != MVT::v8i1) |
13120 | 0 | return 0; |
13121 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
13122 | 0 | return fastEmitInst_ri(X86::VFPCLASSPDZrr, &X86::VK8RegClass, Op0, Op0IsKill, imm1); |
13123 | 0 | } |
13124 | 0 | return 0; |
13125 | 0 | } |
13126 | | |
13127 | | unsigned fastEmit_X86ISD_VFPCLASS_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13128 | | switch (VT.SimpleTy) { |
13129 | | case MVT::v4f32: return fastEmit_X86ISD_VFPCLASS_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1); |
13130 | | case MVT::v8f32: return fastEmit_X86ISD_VFPCLASS_MVT_v8f32_ri(RetVT, Op0, Op0IsKill, imm1); |
13131 | | case MVT::v16f32: return fastEmit_X86ISD_VFPCLASS_MVT_v16f32_ri(RetVT, Op0, Op0IsKill, imm1); |
13132 | | case MVT::v2f64: return fastEmit_X86ISD_VFPCLASS_MVT_v2f64_ri(RetVT, Op0, Op0IsKill, imm1); |
13133 | | case MVT::v4f64: return fastEmit_X86ISD_VFPCLASS_MVT_v4f64_ri(RetVT, Op0, Op0IsKill, imm1); |
13134 | | case MVT::v8f64: return fastEmit_X86ISD_VFPCLASS_MVT_v8f64_ri(RetVT, Op0, Op0IsKill, imm1); |
13135 | | default: return 0; |
13136 | | } |
13137 | | } |
13138 | | |
13139 | | // FastEmit functions for X86ISD::VFPCLASSS. |
13140 | | |
13141 | 0 | unsigned fastEmit_X86ISD_VFPCLASSS_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13142 | 0 | if (RetVT.SimpleTy != MVT::v1i1) |
13143 | 0 | return 0; |
13144 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
13145 | 0 | return fastEmitInst_ri(X86::VFPCLASSSSrr, &X86::VK1RegClass, Op0, Op0IsKill, imm1); |
13146 | 0 | } |
13147 | 0 | return 0; |
13148 | 0 | } |
13149 | | |
13150 | 0 | unsigned fastEmit_X86ISD_VFPCLASSS_MVT_v2f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13151 | 0 | if (RetVT.SimpleTy != MVT::v1i1) |
13152 | 0 | return 0; |
13153 | 0 | if (0 (Subtarget->hasDQI())0 ) { |
13154 | 0 | return fastEmitInst_ri(X86::VFPCLASSSDrr, &X86::VK1RegClass, Op0, Op0IsKill, imm1); |
13155 | 0 | } |
13156 | 0 | return 0; |
13157 | 0 | } |
13158 | | |
13159 | | unsigned fastEmit_X86ISD_VFPCLASSS_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13160 | | switch (VT.SimpleTy) { |
13161 | | case MVT::v4f32: return fastEmit_X86ISD_VFPCLASSS_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1); |
13162 | | case MVT::v2f64: return fastEmit_X86ISD_VFPCLASSS_MVT_v2f64_ri(RetVT, Op0, Op0IsKill, imm1); |
13163 | | default: return 0; |
13164 | | } |
13165 | | } |
13166 | | |
13167 | | // FastEmit functions for X86ISD::VFPROUND_RND. |
13168 | | |
13169 | 0 | unsigned fastEmit_X86ISD_VFPROUND_RND_MVT_v8f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13170 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
13171 | 0 | return 0; |
13172 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13173 | 0 | return fastEmitInst_ri(X86::VCVTPD2PSZrrb, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13174 | 0 | } |
13175 | 0 | return 0; |
13176 | 0 | } |
13177 | | |
13178 | | unsigned fastEmit_X86ISD_VFPROUND_RND_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13179 | | switch (VT.SimpleTy) { |
13180 | | case MVT::v8f64: return fastEmit_X86ISD_VFPROUND_RND_MVT_v8f64_ri(RetVT, Op0, Op0IsKill, imm1); |
13181 | | default: return 0; |
13182 | | } |
13183 | | } |
13184 | | |
13185 | | // FastEmit functions for X86ISD::VPERMI. |
13186 | | |
13187 | 0 | unsigned fastEmit_X86ISD_VPERMI_MVT_v4i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13188 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
13189 | 0 | return 0; |
13190 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13191 | 0 | return fastEmitInst_ri(X86::VPERMQZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13192 | 0 | } |
13193 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
13194 | 0 | return fastEmitInst_ri(X86::VPERMQYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13195 | 0 | } |
13196 | 0 | return 0; |
13197 | 0 | } |
13198 | | |
13199 | 0 | unsigned fastEmit_X86ISD_VPERMI_MVT_v8i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13200 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
13201 | 0 | return 0; |
13202 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13203 | 0 | return fastEmitInst_ri(X86::VPERMQZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13204 | 0 | } |
13205 | 0 | return 0; |
13206 | 0 | } |
13207 | | |
13208 | 0 | unsigned fastEmit_X86ISD_VPERMI_MVT_v4f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13209 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
13210 | 0 | return 0; |
13211 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13212 | 0 | return fastEmitInst_ri(X86::VPERMPDZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13213 | 0 | } |
13214 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
13215 | 0 | return fastEmitInst_ri(X86::VPERMPDYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13216 | 0 | } |
13217 | 0 | return 0; |
13218 | 0 | } |
13219 | | |
13220 | 0 | unsigned fastEmit_X86ISD_VPERMI_MVT_v8f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13221 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
13222 | 0 | return 0; |
13223 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13224 | 0 | return fastEmitInst_ri(X86::VPERMPDZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13225 | 0 | } |
13226 | 0 | return 0; |
13227 | 0 | } |
13228 | | |
13229 | | unsigned fastEmit_X86ISD_VPERMI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13230 | | switch (VT.SimpleTy) { |
13231 | | case MVT::v4i64: return fastEmit_X86ISD_VPERMI_MVT_v4i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13232 | | case MVT::v8i64: return fastEmit_X86ISD_VPERMI_MVT_v8i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13233 | | case MVT::v4f64: return fastEmit_X86ISD_VPERMI_MVT_v4f64_ri(RetVT, Op0, Op0IsKill, imm1); |
13234 | | case MVT::v8f64: return fastEmit_X86ISD_VPERMI_MVT_v8f64_ri(RetVT, Op0, Op0IsKill, imm1); |
13235 | | default: return 0; |
13236 | | } |
13237 | | } |
13238 | | |
13239 | | // FastEmit functions for X86ISD::VPERMILPI. |
13240 | | |
13241 | 0 | unsigned fastEmit_X86ISD_VPERMILPI_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13242 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
13243 | 0 | return 0; |
13244 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13245 | 0 | return fastEmitInst_ri(X86::VPERMILPSZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13246 | 0 | } |
13247 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
13248 | 0 | return fastEmitInst_ri(X86::VPERMILPSri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13249 | 0 | } |
13250 | 0 | return 0; |
13251 | 0 | } |
13252 | | |
13253 | 0 | unsigned fastEmit_X86ISD_VPERMILPI_MVT_v8f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13254 | 0 | if (RetVT.SimpleTy != MVT::v8f32) |
13255 | 0 | return 0; |
13256 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13257 | 0 | return fastEmitInst_ri(X86::VPERMILPSZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13258 | 0 | } |
13259 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
13260 | 0 | return fastEmitInst_ri(X86::VPERMILPSYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13261 | 0 | } |
13262 | 0 | return 0; |
13263 | 0 | } |
13264 | | |
13265 | 0 | unsigned fastEmit_X86ISD_VPERMILPI_MVT_v16f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13266 | 0 | if (RetVT.SimpleTy != MVT::v16f32) |
13267 | 0 | return 0; |
13268 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13269 | 0 | return fastEmitInst_ri(X86::VPERMILPSZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13270 | 0 | } |
13271 | 0 | return 0; |
13272 | 0 | } |
13273 | | |
13274 | 0 | unsigned fastEmit_X86ISD_VPERMILPI_MVT_v2f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13275 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
13276 | 0 | return 0; |
13277 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13278 | 0 | return fastEmitInst_ri(X86::VPERMILPDZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13279 | 0 | } |
13280 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
13281 | 0 | return fastEmitInst_ri(X86::VPERMILPDri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13282 | 0 | } |
13283 | 0 | return 0; |
13284 | 0 | } |
13285 | | |
13286 | 0 | unsigned fastEmit_X86ISD_VPERMILPI_MVT_v4f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13287 | 0 | if (RetVT.SimpleTy != MVT::v4f64) |
13288 | 0 | return 0; |
13289 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13290 | 0 | return fastEmitInst_ri(X86::VPERMILPDZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13291 | 0 | } |
13292 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
13293 | 0 | return fastEmitInst_ri(X86::VPERMILPDYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13294 | 0 | } |
13295 | 0 | return 0; |
13296 | 0 | } |
13297 | | |
13298 | 0 | unsigned fastEmit_X86ISD_VPERMILPI_MVT_v8f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13299 | 0 | if (RetVT.SimpleTy != MVT::v8f64) |
13300 | 0 | return 0; |
13301 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13302 | 0 | return fastEmitInst_ri(X86::VPERMILPDZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13303 | 0 | } |
13304 | 0 | return 0; |
13305 | 0 | } |
13306 | | |
13307 | | unsigned fastEmit_X86ISD_VPERMILPI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13308 | | switch (VT.SimpleTy) { |
13309 | | case MVT::v4f32: return fastEmit_X86ISD_VPERMILPI_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1); |
13310 | | case MVT::v8f32: return fastEmit_X86ISD_VPERMILPI_MVT_v8f32_ri(RetVT, Op0, Op0IsKill, imm1); |
13311 | | case MVT::v16f32: return fastEmit_X86ISD_VPERMILPI_MVT_v16f32_ri(RetVT, Op0, Op0IsKill, imm1); |
13312 | | case MVT::v2f64: return fastEmit_X86ISD_VPERMILPI_MVT_v2f64_ri(RetVT, Op0, Op0IsKill, imm1); |
13313 | | case MVT::v4f64: return fastEmit_X86ISD_VPERMILPI_MVT_v4f64_ri(RetVT, Op0, Op0IsKill, imm1); |
13314 | | case MVT::v8f64: return fastEmit_X86ISD_VPERMILPI_MVT_v8f64_ri(RetVT, Op0, Op0IsKill, imm1); |
13315 | | default: return 0; |
13316 | | } |
13317 | | } |
13318 | | |
13319 | | // FastEmit functions for X86ISD::VROTLI. |
13320 | | |
13321 | 0 | unsigned fastEmit_X86ISD_VROTLI_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13322 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
13323 | 0 | return 0; |
13324 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
13325 | 0 | return fastEmitInst_ri(X86::VPROTBri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13326 | 0 | } |
13327 | 0 | return 0; |
13328 | 0 | } |
13329 | | |
13330 | 0 | unsigned fastEmit_X86ISD_VROTLI_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13331 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
13332 | 0 | return 0; |
13333 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
13334 | 0 | return fastEmitInst_ri(X86::VPROTWri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13335 | 0 | } |
13336 | 0 | return 0; |
13337 | 0 | } |
13338 | | |
13339 | 0 | unsigned fastEmit_X86ISD_VROTLI_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13340 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
13341 | 0 | return 0; |
13342 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13343 | 0 | return fastEmitInst_ri(X86::VPROLDZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13344 | 0 | } |
13345 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
13346 | 0 | return fastEmitInst_ri(X86::VPROTDri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13347 | 0 | } |
13348 | 0 | return 0; |
13349 | 0 | } |
13350 | | |
13351 | 0 | unsigned fastEmit_X86ISD_VROTLI_MVT_v8i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13352 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
13353 | 0 | return 0; |
13354 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13355 | 0 | return fastEmitInst_ri(X86::VPROLDZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13356 | 0 | } |
13357 | 0 | return 0; |
13358 | 0 | } |
13359 | | |
13360 | 0 | unsigned fastEmit_X86ISD_VROTLI_MVT_v16i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13361 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
13362 | 0 | return 0; |
13363 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13364 | 0 | return fastEmitInst_ri(X86::VPROLDZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13365 | 0 | } |
13366 | 0 | return 0; |
13367 | 0 | } |
13368 | | |
13369 | 0 | unsigned fastEmit_X86ISD_VROTLI_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13370 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
13371 | 0 | return 0; |
13372 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13373 | 0 | return fastEmitInst_ri(X86::VPROLQZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13374 | 0 | } |
13375 | 0 | if (0 (Subtarget->hasXOP())0 ) { |
13376 | 0 | return fastEmitInst_ri(X86::VPROTQri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13377 | 0 | } |
13378 | 0 | return 0; |
13379 | 0 | } |
13380 | | |
13381 | 0 | unsigned fastEmit_X86ISD_VROTLI_MVT_v4i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13382 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
13383 | 0 | return 0; |
13384 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13385 | 0 | return fastEmitInst_ri(X86::VPROLQZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13386 | 0 | } |
13387 | 0 | return 0; |
13388 | 0 | } |
13389 | | |
13390 | 0 | unsigned fastEmit_X86ISD_VROTLI_MVT_v8i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13391 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
13392 | 0 | return 0; |
13393 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13394 | 0 | return fastEmitInst_ri(X86::VPROLQZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13395 | 0 | } |
13396 | 0 | return 0; |
13397 | 0 | } |
13398 | | |
13399 | | unsigned fastEmit_X86ISD_VROTLI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13400 | | switch (VT.SimpleTy) { |
13401 | | case MVT::v16i8: return fastEmit_X86ISD_VROTLI_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); |
13402 | | case MVT::v8i16: return fastEmit_X86ISD_VROTLI_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); |
13403 | | case MVT::v4i32: return fastEmit_X86ISD_VROTLI_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13404 | | case MVT::v8i32: return fastEmit_X86ISD_VROTLI_MVT_v8i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13405 | | case MVT::v16i32: return fastEmit_X86ISD_VROTLI_MVT_v16i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13406 | | case MVT::v2i64: return fastEmit_X86ISD_VROTLI_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13407 | | case MVT::v4i64: return fastEmit_X86ISD_VROTLI_MVT_v4i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13408 | | case MVT::v8i64: return fastEmit_X86ISD_VROTLI_MVT_v8i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13409 | | default: return 0; |
13410 | | } |
13411 | | } |
13412 | | |
13413 | | // FastEmit functions for X86ISD::VROTRI. |
13414 | | |
13415 | 0 | unsigned fastEmit_X86ISD_VROTRI_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13416 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
13417 | 0 | return 0; |
13418 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13419 | 0 | return fastEmitInst_ri(X86::VPRORDZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13420 | 0 | } |
13421 | 0 | return 0; |
13422 | 0 | } |
13423 | | |
13424 | 0 | unsigned fastEmit_X86ISD_VROTRI_MVT_v8i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13425 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
13426 | 0 | return 0; |
13427 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13428 | 0 | return fastEmitInst_ri(X86::VPRORDZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13429 | 0 | } |
13430 | 0 | return 0; |
13431 | 0 | } |
13432 | | |
13433 | 0 | unsigned fastEmit_X86ISD_VROTRI_MVT_v16i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13434 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
13435 | 0 | return 0; |
13436 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13437 | 0 | return fastEmitInst_ri(X86::VPRORDZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13438 | 0 | } |
13439 | 0 | return 0; |
13440 | 0 | } |
13441 | | |
13442 | 0 | unsigned fastEmit_X86ISD_VROTRI_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13443 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
13444 | 0 | return 0; |
13445 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13446 | 0 | return fastEmitInst_ri(X86::VPRORQZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13447 | 0 | } |
13448 | 0 | return 0; |
13449 | 0 | } |
13450 | | |
13451 | 0 | unsigned fastEmit_X86ISD_VROTRI_MVT_v4i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13452 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
13453 | 0 | return 0; |
13454 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13455 | 0 | return fastEmitInst_ri(X86::VPRORQZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13456 | 0 | } |
13457 | 0 | return 0; |
13458 | 0 | } |
13459 | | |
13460 | 0 | unsigned fastEmit_X86ISD_VROTRI_MVT_v8i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13461 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
13462 | 0 | return 0; |
13463 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13464 | 0 | return fastEmitInst_ri(X86::VPRORQZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13465 | 0 | } |
13466 | 0 | return 0; |
13467 | 0 | } |
13468 | | |
13469 | | unsigned fastEmit_X86ISD_VROTRI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13470 | | switch (VT.SimpleTy) { |
13471 | | case MVT::v4i32: return fastEmit_X86ISD_VROTRI_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13472 | | case MVT::v8i32: return fastEmit_X86ISD_VROTRI_MVT_v8i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13473 | | case MVT::v16i32: return fastEmit_X86ISD_VROTRI_MVT_v16i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13474 | | case MVT::v2i64: return fastEmit_X86ISD_VROTRI_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13475 | | case MVT::v4i64: return fastEmit_X86ISD_VROTRI_MVT_v4i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13476 | | case MVT::v8i64: return fastEmit_X86ISD_VROTRI_MVT_v8i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13477 | | default: return 0; |
13478 | | } |
13479 | | } |
13480 | | |
13481 | | // FastEmit functions for X86ISD::VSHLDQ. |
13482 | | |
13483 | 0 | unsigned fastEmit_X86ISD_VSHLDQ_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13484 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
13485 | 0 | return 0; |
13486 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
13487 | 0 | return fastEmitInst_ri(X86::VPSLLDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13488 | 0 | } |
13489 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
13490 | 0 | return fastEmitInst_ri(X86::PSLLDQri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13491 | 0 | } |
13492 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
13493 | 0 | return fastEmitInst_ri(X86::VPSLLDQri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13494 | 0 | } |
13495 | 0 | return 0; |
13496 | 0 | } |
13497 | | |
13498 | 0 | unsigned fastEmit_X86ISD_VSHLDQ_MVT_v32i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13499 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
13500 | 0 | return 0; |
13501 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
13502 | 0 | return fastEmitInst_ri(X86::VPSLLDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13503 | 0 | } |
13504 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
13505 | 0 | return fastEmitInst_ri(X86::VPSLLDQYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13506 | 0 | } |
13507 | 0 | return 0; |
13508 | 0 | } |
13509 | | |
13510 | 0 | unsigned fastEmit_X86ISD_VSHLDQ_MVT_v64i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13511 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
13512 | 0 | return 0; |
13513 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
13514 | 0 | return fastEmitInst_ri(X86::VPSLLDQZ512rr, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13515 | 0 | } |
13516 | 0 | return 0; |
13517 | 0 | } |
13518 | | |
13519 | | unsigned fastEmit_X86ISD_VSHLDQ_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13520 | | switch (VT.SimpleTy) { |
13521 | | case MVT::v16i8: return fastEmit_X86ISD_VSHLDQ_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); |
13522 | | case MVT::v32i8: return fastEmit_X86ISD_VSHLDQ_MVT_v32i8_ri(RetVT, Op0, Op0IsKill, imm1); |
13523 | | case MVT::v64i8: return fastEmit_X86ISD_VSHLDQ_MVT_v64i8_ri(RetVT, Op0, Op0IsKill, imm1); |
13524 | | default: return 0; |
13525 | | } |
13526 | | } |
13527 | | |
13528 | | // FastEmit functions for X86ISD::VSHLI. |
13529 | | |
13530 | 0 | unsigned fastEmit_X86ISD_VSHLI_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13531 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
13532 | 0 | return 0; |
13533 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
13534 | 0 | return fastEmitInst_ri(X86::VPSLLWZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13535 | 0 | } |
13536 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
13537 | 0 | return fastEmitInst_ri(X86::PSLLWri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13538 | 0 | } |
13539 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
13540 | 0 | return fastEmitInst_ri(X86::VPSLLWri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13541 | 0 | } |
13542 | 0 | return 0; |
13543 | 0 | } |
13544 | | |
13545 | 0 | unsigned fastEmit_X86ISD_VSHLI_MVT_v16i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13546 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
13547 | 0 | return 0; |
13548 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
13549 | 0 | return fastEmitInst_ri(X86::VPSLLWZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13550 | 0 | } |
13551 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
13552 | 0 | return fastEmitInst_ri(X86::VPSLLWYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13553 | 0 | } |
13554 | 0 | return 0; |
13555 | 0 | } |
13556 | | |
13557 | 0 | unsigned fastEmit_X86ISD_VSHLI_MVT_v32i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13558 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
13559 | 0 | return 0; |
13560 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
13561 | 0 | return fastEmitInst_ri(X86::VPSLLWZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13562 | 0 | } |
13563 | 0 | return 0; |
13564 | 0 | } |
13565 | | |
13566 | 0 | unsigned fastEmit_X86ISD_VSHLI_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13567 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
13568 | 0 | return 0; |
13569 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13570 | 0 | return fastEmitInst_ri(X86::VPSLLDZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13571 | 0 | } |
13572 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
13573 | 0 | return fastEmitInst_ri(X86::PSLLDri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13574 | 0 | } |
13575 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
13576 | 0 | return fastEmitInst_ri(X86::VPSLLDri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13577 | 0 | } |
13578 | 0 | return 0; |
13579 | 0 | } |
13580 | | |
13581 | 0 | unsigned fastEmit_X86ISD_VSHLI_MVT_v8i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13582 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
13583 | 0 | return 0; |
13584 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13585 | 0 | return fastEmitInst_ri(X86::VPSLLDZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13586 | 0 | } |
13587 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
13588 | 0 | return fastEmitInst_ri(X86::VPSLLDYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13589 | 0 | } |
13590 | 0 | return 0; |
13591 | 0 | } |
13592 | | |
13593 | 0 | unsigned fastEmit_X86ISD_VSHLI_MVT_v16i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13594 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
13595 | 0 | return 0; |
13596 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13597 | 0 | return fastEmitInst_ri(X86::VPSLLDZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13598 | 0 | } |
13599 | 0 | return 0; |
13600 | 0 | } |
13601 | | |
13602 | 0 | unsigned fastEmit_X86ISD_VSHLI_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13603 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
13604 | 0 | return 0; |
13605 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13606 | 0 | return fastEmitInst_ri(X86::VPSLLQZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13607 | 0 | } |
13608 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
13609 | 0 | return fastEmitInst_ri(X86::PSLLQri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13610 | 0 | } |
13611 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
13612 | 0 | return fastEmitInst_ri(X86::VPSLLQri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13613 | 0 | } |
13614 | 0 | return 0; |
13615 | 0 | } |
13616 | | |
13617 | 0 | unsigned fastEmit_X86ISD_VSHLI_MVT_v4i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13618 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
13619 | 0 | return 0; |
13620 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13621 | 0 | return fastEmitInst_ri(X86::VPSLLQZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13622 | 0 | } |
13623 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
13624 | 0 | return fastEmitInst_ri(X86::VPSLLQYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13625 | 0 | } |
13626 | 0 | return 0; |
13627 | 0 | } |
13628 | | |
13629 | 0 | unsigned fastEmit_X86ISD_VSHLI_MVT_v8i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13630 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
13631 | 0 | return 0; |
13632 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13633 | 0 | return fastEmitInst_ri(X86::VPSLLQZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13634 | 0 | } |
13635 | 0 | return 0; |
13636 | 0 | } |
13637 | | |
13638 | | unsigned fastEmit_X86ISD_VSHLI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13639 | | switch (VT.SimpleTy) { |
13640 | | case MVT::v8i16: return fastEmit_X86ISD_VSHLI_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); |
13641 | | case MVT::v16i16: return fastEmit_X86ISD_VSHLI_MVT_v16i16_ri(RetVT, Op0, Op0IsKill, imm1); |
13642 | | case MVT::v32i16: return fastEmit_X86ISD_VSHLI_MVT_v32i16_ri(RetVT, Op0, Op0IsKill, imm1); |
13643 | | case MVT::v4i32: return fastEmit_X86ISD_VSHLI_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13644 | | case MVT::v8i32: return fastEmit_X86ISD_VSHLI_MVT_v8i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13645 | | case MVT::v16i32: return fastEmit_X86ISD_VSHLI_MVT_v16i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13646 | | case MVT::v2i64: return fastEmit_X86ISD_VSHLI_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13647 | | case MVT::v4i64: return fastEmit_X86ISD_VSHLI_MVT_v4i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13648 | | case MVT::v8i64: return fastEmit_X86ISD_VSHLI_MVT_v8i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13649 | | default: return 0; |
13650 | | } |
13651 | | } |
13652 | | |
13653 | | // FastEmit functions for X86ISD::VSRAI. |
13654 | | |
13655 | 0 | unsigned fastEmit_X86ISD_VSRAI_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13656 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
13657 | 0 | return 0; |
13658 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
13659 | 0 | return fastEmitInst_ri(X86::VPSRAWZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13660 | 0 | } |
13661 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
13662 | 0 | return fastEmitInst_ri(X86::PSRAWri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13663 | 0 | } |
13664 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
13665 | 0 | return fastEmitInst_ri(X86::VPSRAWri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13666 | 0 | } |
13667 | 0 | return 0; |
13668 | 0 | } |
13669 | | |
13670 | 0 | unsigned fastEmit_X86ISD_VSRAI_MVT_v16i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13671 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
13672 | 0 | return 0; |
13673 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
13674 | 0 | return fastEmitInst_ri(X86::VPSRAWZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13675 | 0 | } |
13676 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
13677 | 0 | return fastEmitInst_ri(X86::VPSRAWYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13678 | 0 | } |
13679 | 0 | return 0; |
13680 | 0 | } |
13681 | | |
13682 | 0 | unsigned fastEmit_X86ISD_VSRAI_MVT_v32i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13683 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
13684 | 0 | return 0; |
13685 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
13686 | 0 | return fastEmitInst_ri(X86::VPSRAWZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13687 | 0 | } |
13688 | 0 | return 0; |
13689 | 0 | } |
13690 | | |
13691 | 0 | unsigned fastEmit_X86ISD_VSRAI_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13692 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
13693 | 0 | return 0; |
13694 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13695 | 0 | return fastEmitInst_ri(X86::VPSRADZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13696 | 0 | } |
13697 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
13698 | 0 | return fastEmitInst_ri(X86::PSRADri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13699 | 0 | } |
13700 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
13701 | 0 | return fastEmitInst_ri(X86::VPSRADri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13702 | 0 | } |
13703 | 0 | return 0; |
13704 | 0 | } |
13705 | | |
13706 | 0 | unsigned fastEmit_X86ISD_VSRAI_MVT_v8i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13707 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
13708 | 0 | return 0; |
13709 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13710 | 0 | return fastEmitInst_ri(X86::VPSRADZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13711 | 0 | } |
13712 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
13713 | 0 | return fastEmitInst_ri(X86::VPSRADYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13714 | 0 | } |
13715 | 0 | return 0; |
13716 | 0 | } |
13717 | | |
13718 | 0 | unsigned fastEmit_X86ISD_VSRAI_MVT_v16i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13719 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
13720 | 0 | return 0; |
13721 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13722 | 0 | return fastEmitInst_ri(X86::VPSRADZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13723 | 0 | } |
13724 | 0 | return 0; |
13725 | 0 | } |
13726 | | |
13727 | 0 | unsigned fastEmit_X86ISD_VSRAI_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13728 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
13729 | 0 | return 0; |
13730 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13731 | 0 | return fastEmitInst_ri(X86::VPSRAQZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13732 | 0 | } |
13733 | 0 | return 0; |
13734 | 0 | } |
13735 | | |
13736 | 0 | unsigned fastEmit_X86ISD_VSRAI_MVT_v4i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13737 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
13738 | 0 | return 0; |
13739 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13740 | 0 | return fastEmitInst_ri(X86::VPSRAQZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13741 | 0 | } |
13742 | 0 | return 0; |
13743 | 0 | } |
13744 | | |
13745 | 0 | unsigned fastEmit_X86ISD_VSRAI_MVT_v8i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13746 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
13747 | 0 | return 0; |
13748 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13749 | 0 | return fastEmitInst_ri(X86::VPSRAQZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13750 | 0 | } |
13751 | 0 | return 0; |
13752 | 0 | } |
13753 | | |
13754 | | unsigned fastEmit_X86ISD_VSRAI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13755 | | switch (VT.SimpleTy) { |
13756 | | case MVT::v8i16: return fastEmit_X86ISD_VSRAI_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); |
13757 | | case MVT::v16i16: return fastEmit_X86ISD_VSRAI_MVT_v16i16_ri(RetVT, Op0, Op0IsKill, imm1); |
13758 | | case MVT::v32i16: return fastEmit_X86ISD_VSRAI_MVT_v32i16_ri(RetVT, Op0, Op0IsKill, imm1); |
13759 | | case MVT::v4i32: return fastEmit_X86ISD_VSRAI_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13760 | | case MVT::v8i32: return fastEmit_X86ISD_VSRAI_MVT_v8i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13761 | | case MVT::v16i32: return fastEmit_X86ISD_VSRAI_MVT_v16i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13762 | | case MVT::v2i64: return fastEmit_X86ISD_VSRAI_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13763 | | case MVT::v4i64: return fastEmit_X86ISD_VSRAI_MVT_v4i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13764 | | case MVT::v8i64: return fastEmit_X86ISD_VSRAI_MVT_v8i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13765 | | default: return 0; |
13766 | | } |
13767 | | } |
13768 | | |
13769 | | // FastEmit functions for X86ISD::VSRLDQ. |
13770 | | |
13771 | 0 | unsigned fastEmit_X86ISD_VSRLDQ_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13772 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
13773 | 0 | return 0; |
13774 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
13775 | 0 | return fastEmitInst_ri(X86::VPSRLDQZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13776 | 0 | } |
13777 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
13778 | 0 | return fastEmitInst_ri(X86::PSRLDQri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13779 | 0 | } |
13780 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
13781 | 0 | return fastEmitInst_ri(X86::VPSRLDQri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13782 | 0 | } |
13783 | 0 | return 0; |
13784 | 0 | } |
13785 | | |
13786 | 0 | unsigned fastEmit_X86ISD_VSRLDQ_MVT_v32i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13787 | 0 | if (RetVT.SimpleTy != MVT::v32i8) |
13788 | 0 | return 0; |
13789 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
13790 | 0 | return fastEmitInst_ri(X86::VPSRLDQZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13791 | 0 | } |
13792 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
13793 | 0 | return fastEmitInst_ri(X86::VPSRLDQYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13794 | 0 | } |
13795 | 0 | return 0; |
13796 | 0 | } |
13797 | | |
13798 | 0 | unsigned fastEmit_X86ISD_VSRLDQ_MVT_v64i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13799 | 0 | if (RetVT.SimpleTy != MVT::v64i8) |
13800 | 0 | return 0; |
13801 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
13802 | 0 | return fastEmitInst_ri(X86::VPSRLDQZ512rr, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13803 | 0 | } |
13804 | 0 | return 0; |
13805 | 0 | } |
13806 | | |
13807 | | unsigned fastEmit_X86ISD_VSRLDQ_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13808 | | switch (VT.SimpleTy) { |
13809 | | case MVT::v16i8: return fastEmit_X86ISD_VSRLDQ_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); |
13810 | | case MVT::v32i8: return fastEmit_X86ISD_VSRLDQ_MVT_v32i8_ri(RetVT, Op0, Op0IsKill, imm1); |
13811 | | case MVT::v64i8: return fastEmit_X86ISD_VSRLDQ_MVT_v64i8_ri(RetVT, Op0, Op0IsKill, imm1); |
13812 | | default: return 0; |
13813 | | } |
13814 | | } |
13815 | | |
13816 | | // FastEmit functions for X86ISD::VSRLI. |
13817 | | |
13818 | 0 | unsigned fastEmit_X86ISD_VSRLI_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13819 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
13820 | 0 | return 0; |
13821 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
13822 | 0 | return fastEmitInst_ri(X86::VPSRLWZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13823 | 0 | } |
13824 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
13825 | 0 | return fastEmitInst_ri(X86::PSRLWri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13826 | 0 | } |
13827 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
13828 | 0 | return fastEmitInst_ri(X86::VPSRLWri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13829 | 0 | } |
13830 | 0 | return 0; |
13831 | 0 | } |
13832 | | |
13833 | 0 | unsigned fastEmit_X86ISD_VSRLI_MVT_v16i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13834 | 0 | if (RetVT.SimpleTy != MVT::v16i16) |
13835 | 0 | return 0; |
13836 | 0 | if (0 (Subtarget->hasBWI()) && 0 (Subtarget->hasVLX())0 ) { |
13837 | 0 | return fastEmitInst_ri(X86::VPSRLWZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13838 | 0 | } |
13839 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX() || 0 !Subtarget->hasBWI()0 )) { |
13840 | 0 | return fastEmitInst_ri(X86::VPSRLWYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13841 | 0 | } |
13842 | 0 | return 0; |
13843 | 0 | } |
13844 | | |
13845 | 0 | unsigned fastEmit_X86ISD_VSRLI_MVT_v32i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13846 | 0 | if (RetVT.SimpleTy != MVT::v32i16) |
13847 | 0 | return 0; |
13848 | 0 | if (0 (Subtarget->hasBWI())0 ) { |
13849 | 0 | return fastEmitInst_ri(X86::VPSRLWZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13850 | 0 | } |
13851 | 0 | return 0; |
13852 | 0 | } |
13853 | | |
13854 | 0 | unsigned fastEmit_X86ISD_VSRLI_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13855 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
13856 | 0 | return 0; |
13857 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13858 | 0 | return fastEmitInst_ri(X86::VPSRLDZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13859 | 0 | } |
13860 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
13861 | 0 | return fastEmitInst_ri(X86::PSRLDri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13862 | 0 | } |
13863 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
13864 | 0 | return fastEmitInst_ri(X86::VPSRLDri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13865 | 0 | } |
13866 | 0 | return 0; |
13867 | 0 | } |
13868 | | |
13869 | 0 | unsigned fastEmit_X86ISD_VSRLI_MVT_v8i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13870 | 0 | if (RetVT.SimpleTy != MVT::v8i32) |
13871 | 0 | return 0; |
13872 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13873 | 0 | return fastEmitInst_ri(X86::VPSRLDZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13874 | 0 | } |
13875 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
13876 | 0 | return fastEmitInst_ri(X86::VPSRLDYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13877 | 0 | } |
13878 | 0 | return 0; |
13879 | 0 | } |
13880 | | |
13881 | 0 | unsigned fastEmit_X86ISD_VSRLI_MVT_v16i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13882 | 0 | if (RetVT.SimpleTy != MVT::v16i32) |
13883 | 0 | return 0; |
13884 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13885 | 0 | return fastEmitInst_ri(X86::VPSRLDZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13886 | 0 | } |
13887 | 0 | return 0; |
13888 | 0 | } |
13889 | | |
13890 | 0 | unsigned fastEmit_X86ISD_VSRLI_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13891 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
13892 | 0 | return 0; |
13893 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13894 | 0 | return fastEmitInst_ri(X86::VPSRLQZ128ri, &X86::VR128XRegClass, Op0, Op0IsKill, imm1); |
13895 | 0 | } |
13896 | 0 | if (0 (Subtarget->hasSSE2() && 0 !Subtarget->hasAVX()0 )) { |
13897 | 0 | return fastEmitInst_ri(X86::PSRLQri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13898 | 0 | } |
13899 | 0 | if (0 (Subtarget->hasAVX()) && 0 (!Subtarget->hasVLX())0 ) { |
13900 | 0 | return fastEmitInst_ri(X86::VPSRLQri, &X86::VR128RegClass, Op0, Op0IsKill, imm1); |
13901 | 0 | } |
13902 | 0 | return 0; |
13903 | 0 | } |
13904 | | |
13905 | 0 | unsigned fastEmit_X86ISD_VSRLI_MVT_v4i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13906 | 0 | if (RetVT.SimpleTy != MVT::v4i64) |
13907 | 0 | return 0; |
13908 | 0 | if (0 (Subtarget->hasAVX512()) && 0 (Subtarget->hasVLX())0 ) { |
13909 | 0 | return fastEmitInst_ri(X86::VPSRLQZ256ri, &X86::VR256XRegClass, Op0, Op0IsKill, imm1); |
13910 | 0 | } |
13911 | 0 | if (0 (Subtarget->hasAVX2()) && 0 (!Subtarget->hasVLX())0 ) { |
13912 | 0 | return fastEmitInst_ri(X86::VPSRLQYri, &X86::VR256RegClass, Op0, Op0IsKill, imm1); |
13913 | 0 | } |
13914 | 0 | return 0; |
13915 | 0 | } |
13916 | | |
13917 | 0 | unsigned fastEmit_X86ISD_VSRLI_MVT_v8i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13918 | 0 | if (RetVT.SimpleTy != MVT::v8i64) |
13919 | 0 | return 0; |
13920 | 0 | if (0 (Subtarget->hasAVX512())0 ) { |
13921 | 0 | return fastEmitInst_ri(X86::VPSRLQZri, &X86::VR512RegClass, Op0, Op0IsKill, imm1); |
13922 | 0 | } |
13923 | 0 | return 0; |
13924 | 0 | } |
13925 | | |
13926 | | unsigned fastEmit_X86ISD_VSRLI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
13927 | | switch (VT.SimpleTy) { |
13928 | | case MVT::v8i16: return fastEmit_X86ISD_VSRLI_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); |
13929 | | case MVT::v16i16: return fastEmit_X86ISD_VSRLI_MVT_v16i16_ri(RetVT, Op0, Op0IsKill, imm1); |
13930 | | case MVT::v32i16: return fastEmit_X86ISD_VSRLI_MVT_v32i16_ri(RetVT, Op0, Op0IsKill, imm1); |
13931 | | case MVT::v4i32: return fastEmit_X86ISD_VSRLI_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13932 | | case MVT::v8i32: return fastEmit_X86ISD_VSRLI_MVT_v8i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13933 | | case MVT::v16i32: return fastEmit_X86ISD_VSRLI_MVT_v16i32_ri(RetVT, Op0, Op0IsKill, imm1); |
13934 | | case MVT::v2i64: return fastEmit_X86ISD_VSRLI_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13935 | | case MVT::v4i64: return fastEmit_X86ISD_VSRLI_MVT_v4i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13936 | | case MVT::v8i64: return fastEmit_X86ISD_VSRLI_MVT_v8i64_ri(RetVT, Op0, Op0IsKill, imm1); |
13937 | | default: return 0; |
13938 | | } |
13939 | | } |
13940 | | |
13941 | | // Top-level FastEmit function. |
13942 | | |
13943 | 575 | unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override { |
13944 | 575 | if (VT == MVT::i16 && 575 Predicate_i16immSExt8(imm1)10 ) |
13945 | 4 | if (unsigned 4 Reg4 = fastEmit_ri_Predicate_i16immSExt8(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) |
13946 | 1 | return Reg; |
13947 | 575 | |
13948 | 574 | if (574 VT == MVT::i32 && 574 Predicate_i32immSExt8(imm1)224 ) |
13949 | 198 | if (unsigned 198 Reg198 = fastEmit_ri_Predicate_i32immSExt8(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) |
13950 | 166 | return Reg; |
13951 | 574 | |
13952 | 408 | if (408 VT == MVT::i64 && 408 Predicate_i64immSExt8(imm1)152 ) |
13953 | 127 | if (unsigned 127 Reg127 = fastEmit_ri_Predicate_i64immSExt8(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) |
13954 | 99 | return Reg; |
13955 | 408 | |
13956 | 309 | if (309 VT == MVT::i64 && 309 Predicate_i64immSExt32(imm1)53 ) |
13957 | 36 | if (unsigned 36 Reg36 = fastEmit_ri_Predicate_i64immSExt32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) |
13958 | 8 | return Reg; |
13959 | 309 | |
13960 | 301 | switch (Opcode) { |
13961 | 7 | case ISD::ADD: return fastEmit_ISD_ADD_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13962 | 205 | case ISD::AND: return fastEmit_ISD_AND_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13963 | 0 | case ISD::EXTRACT_SUBVECTOR: return fastEmit_ISD_EXTRACT_SUBVECTOR_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13964 | 0 | case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13965 | 2 | case ISD::MUL: return fastEmit_ISD_MUL_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13966 | 13 | case ISD::OR: return fastEmit_ISD_OR_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13967 | 0 | case ISD::ROTL: return fastEmit_ISD_ROTL_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13968 | 31 | case ISD::SHL: return fastEmit_ISD_SHL_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13969 | 4 | case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13970 | 27 | case ISD::SRL: return fastEmit_ISD_SRL_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13971 | 1 | case ISD::SUB: return fastEmit_ISD_SUB_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13972 | 10 | case ISD::XOR: return fastEmit_ISD_XOR_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13973 | 0 | case X86ISD::CVTP2SI_RND: return fastEmit_X86ISD_CVTP2SI_RND_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13974 | 0 | case X86ISD::CVTP2UI_RND: return fastEmit_X86ISD_CVTP2UI_RND_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13975 | 0 | case X86ISD::CVTPS2PH: return fastEmit_X86ISD_CVTPS2PH_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13976 | 0 | case X86ISD::CVTS2SI_RND: return fastEmit_X86ISD_CVTS2SI_RND_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13977 | 0 | case X86ISD::CVTS2UI_RND: return fastEmit_X86ISD_CVTS2UI_RND_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13978 | 0 | case X86ISD::FSQRT_RND: return fastEmit_X86ISD_FSQRT_RND_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13979 | 0 | case X86ISD::KSHIFTL: return fastEmit_X86ISD_KSHIFTL_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13980 | 0 | case X86ISD::KSHIFTR: return fastEmit_X86ISD_KSHIFTR_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13981 | 0 | case X86ISD::PEXTRB: return fastEmit_X86ISD_PEXTRB_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13982 | 0 | case X86ISD::PEXTRW: return fastEmit_X86ISD_PEXTRW_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13983 | 0 | case X86ISD::PSHUFD: return fastEmit_X86ISD_PSHUFD_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13984 | 0 | case X86ISD::PSHUFHW: return fastEmit_X86ISD_PSHUFHW_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13985 | 0 | case X86ISD::PSHUFLW: return fastEmit_X86ISD_PSHUFLW_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13986 | 0 | case X86ISD::SINT_TO_FP_RND: return fastEmit_X86ISD_SINT_TO_FP_RND_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13987 | 0 | case X86ISD::UINT_TO_FP_RND: return fastEmit_X86ISD_UINT_TO_FP_RND_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13988 | 0 | case X86ISD::VFPCLASS: return fastEmit_X86ISD_VFPCLASS_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13989 | 0 | case X86ISD::VFPCLASSS: return fastEmit_X86ISD_VFPCLASSS_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13990 | 0 | case X86ISD::VFPROUND_RND: return fastEmit_X86ISD_VFPROUND_RND_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13991 | 0 | case X86ISD::VPERMI: return fastEmit_X86ISD_VPERMI_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13992 | 0 | case X86ISD::VPERMILPI: return fastEmit_X86ISD_VPERMILPI_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13993 | 0 | case X86ISD::VROTLI: return fastEmit_X86ISD_VROTLI_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13994 | 0 | case X86ISD::VROTRI: return fastEmit_X86ISD_VROTRI_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13995 | 0 | case X86ISD::VSHLDQ: return fastEmit_X86ISD_VSHLDQ_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13996 | 0 | case X86ISD::VSHLI: return fastEmit_X86ISD_VSHLI_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13997 | 0 | case X86ISD::VSRAI: return fastEmit_X86ISD_VSRAI_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13998 | 0 | case X86ISD::VSRLDQ: return fastEmit_X86ISD_VSRLDQ_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
13999 | 0 | case X86ISD::VSRLI: return fastEmit_X86ISD_VSRLI_ri(VT, RetVT, Op0, Op0IsKill, imm1); |
14000 | 1 | default: return 0; |
14001 | 575 | } |
14002 | 575 | } |
14003 | | |
14004 | | // FastEmit functions for ISD::ADD. |
14005 | | |
14006 | 1 | unsigned fastEmit_ISD_ADD_MVT_i16_ri_Predicate_i16immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14007 | 1 | if (RetVT.SimpleTy != MVT::i16) |
14008 | 0 | return 0; |
14009 | 1 | return fastEmitInst_ri(X86::ADD16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
14010 | 1 | } |
14011 | | |
14012 | 1 | unsigned fastEmit_ISD_ADD_ri_Predicate_i16immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14013 | 1 | switch (VT.SimpleTy) { |
14014 | 1 | case MVT::i16: return fastEmit_ISD_ADD_MVT_i16_ri_Predicate_i16immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14015 | 0 | default: return 0; |
14016 | 1 | } |
14017 | 1 | } |
14018 | | |
14019 | | // FastEmit functions for ISD::AND. |
14020 | | |
14021 | 0 | unsigned fastEmit_ISD_AND_MVT_i16_ri_Predicate_i16immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14022 | 0 | if (RetVT.SimpleTy != MVT::i16) |
14023 | 0 | return 0; |
14024 | 0 | return fastEmitInst_ri(X86::AND16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
14025 | 0 | } |
14026 | | |
14027 | | unsigned fastEmit_ISD_AND_ri_Predicate_i16immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14028 | | switch (VT.SimpleTy) { |
14029 | | case MVT::i16: return fastEmit_ISD_AND_MVT_i16_ri_Predicate_i16immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14030 | | default: return 0; |
14031 | | } |
14032 | | } |
14033 | | |
14034 | | // FastEmit functions for ISD::MUL. |
14035 | | |
14036 | 0 | unsigned fastEmit_ISD_MUL_MVT_i16_ri_Predicate_i16immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14037 | 0 | if (RetVT.SimpleTy != MVT::i16) |
14038 | 0 | return 0; |
14039 | 0 | return fastEmitInst_ri(X86::IMUL16rri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
14040 | 0 | } |
14041 | | |
14042 | | unsigned fastEmit_ISD_MUL_ri_Predicate_i16immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14043 | | switch (VT.SimpleTy) { |
14044 | | case MVT::i16: return fastEmit_ISD_MUL_MVT_i16_ri_Predicate_i16immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14045 | | default: return 0; |
14046 | | } |
14047 | | } |
14048 | | |
14049 | | // FastEmit functions for ISD::OR. |
14050 | | |
14051 | 0 | unsigned fastEmit_ISD_OR_MVT_i16_ri_Predicate_i16immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14052 | 0 | if (RetVT.SimpleTy != MVT::i16) |
14053 | 0 | return 0; |
14054 | 0 | return fastEmitInst_ri(X86::OR16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
14055 | 0 | } |
14056 | | |
14057 | | unsigned fastEmit_ISD_OR_ri_Predicate_i16immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14058 | | switch (VT.SimpleTy) { |
14059 | | case MVT::i16: return fastEmit_ISD_OR_MVT_i16_ri_Predicate_i16immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14060 | | default: return 0; |
14061 | | } |
14062 | | } |
14063 | | |
14064 | | // FastEmit functions for ISD::SUB. |
14065 | | |
14066 | 0 | unsigned fastEmit_ISD_SUB_MVT_i16_ri_Predicate_i16immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14067 | 0 | if (RetVT.SimpleTy != MVT::i16) |
14068 | 0 | return 0; |
14069 | 0 | return fastEmitInst_ri(X86::SUB16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
14070 | 0 | } |
14071 | | |
14072 | | unsigned fastEmit_ISD_SUB_ri_Predicate_i16immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14073 | | switch (VT.SimpleTy) { |
14074 | | case MVT::i16: return fastEmit_ISD_SUB_MVT_i16_ri_Predicate_i16immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14075 | | default: return 0; |
14076 | | } |
14077 | | } |
14078 | | |
14079 | | // FastEmit functions for ISD::XOR. |
14080 | | |
14081 | 0 | unsigned fastEmit_ISD_XOR_MVT_i16_ri_Predicate_i16immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14082 | 0 | if (RetVT.SimpleTy != MVT::i16) |
14083 | 0 | return 0; |
14084 | 0 | return fastEmitInst_ri(X86::XOR16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
14085 | 0 | } |
14086 | | |
14087 | | unsigned fastEmit_ISD_XOR_ri_Predicate_i16immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14088 | | switch (VT.SimpleTy) { |
14089 | | case MVT::i16: return fastEmit_ISD_XOR_MVT_i16_ri_Predicate_i16immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14090 | | default: return 0; |
14091 | | } |
14092 | | } |
14093 | | |
14094 | | // FastEmit functions for X86ISD::BT. |
14095 | | |
14096 | 0 | unsigned fastEmit_X86ISD_BT_MVT_i16_ri_Predicate_i16immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14097 | 0 | if (RetVT.SimpleTy != MVT::i32) |
14098 | 0 | return 0; |
14099 | 0 | return fastEmitInst_ri(X86::BT16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1); |
14100 | 0 | } |
14101 | | |
14102 | | unsigned fastEmit_X86ISD_BT_ri_Predicate_i16immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14103 | | switch (VT.SimpleTy) { |
14104 | | case MVT::i16: return fastEmit_X86ISD_BT_MVT_i16_ri_Predicate_i16immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14105 | | default: return 0; |
14106 | | } |
14107 | | } |
14108 | | |
14109 | | // Top-level FastEmit function. |
14110 | | |
14111 | 4 | unsigned fastEmit_ri_Predicate_i16immSExt8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14112 | 4 | switch (Opcode) { |
14113 | 1 | case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_i16immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14114 | 0 | case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_i16immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14115 | 0 | case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_i16immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14116 | 0 | case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_i16immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14117 | 0 | case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_i16immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14118 | 0 | case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_i16immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14119 | 0 | case X86ISD::BT: return fastEmit_X86ISD_BT_ri_Predicate_i16immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14120 | 3 | default: return 0; |
14121 | 4 | } |
14122 | 4 | } |
14123 | | |
14124 | | // FastEmit functions for ISD::ADD. |
14125 | | |
14126 | 87 | unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_i32immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14127 | 87 | if (RetVT.SimpleTy != MVT::i32) |
14128 | 0 | return 0; |
14129 | 87 | return fastEmitInst_ri(X86::ADD32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
14130 | 87 | } |
14131 | | |
14132 | 87 | unsigned fastEmit_ISD_ADD_ri_Predicate_i32immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14133 | 87 | switch (VT.SimpleTy) { |
14134 | 87 | case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_i32immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14135 | 0 | default: return 0; |
14136 | 87 | } |
14137 | 87 | } |
14138 | | |
14139 | | // FastEmit functions for ISD::AND. |
14140 | | |
14141 | 11 | unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_i32immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14142 | 11 | if (RetVT.SimpleTy != MVT::i32) |
14143 | 0 | return 0; |
14144 | 11 | return fastEmitInst_ri(X86::AND32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
14145 | 11 | } |
14146 | | |
14147 | 11 | unsigned fastEmit_ISD_AND_ri_Predicate_i32immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14148 | 11 | switch (VT.SimpleTy) { |
14149 | 11 | case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_i32immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14150 | 0 | default: return 0; |
14151 | 11 | } |
14152 | 11 | } |
14153 | | |
14154 | | // FastEmit functions for ISD::MUL. |
14155 | | |
14156 | 18 | unsigned fastEmit_ISD_MUL_MVT_i32_ri_Predicate_i32immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14157 | 18 | if (RetVT.SimpleTy != MVT::i32) |
14158 | 0 | return 0; |
14159 | 18 | return fastEmitInst_ri(X86::IMUL32rri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
14160 | 18 | } |
14161 | | |
14162 | 18 | unsigned fastEmit_ISD_MUL_ri_Predicate_i32immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14163 | 18 | switch (VT.SimpleTy) { |
14164 | 18 | case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_i32immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14165 | 0 | default: return 0; |
14166 | 18 | } |
14167 | 18 | } |
14168 | | |
14169 | | // FastEmit functions for ISD::OR. |
14170 | | |
14171 | 5 | unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_i32immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14172 | 5 | if (RetVT.SimpleTy != MVT::i32) |
14173 | 0 | return 0; |
14174 | 5 | return fastEmitInst_ri(X86::OR32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
14175 | 5 | } |
14176 | | |
14177 | 5 | unsigned fastEmit_ISD_OR_ri_Predicate_i32immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14178 | 5 | switch (VT.SimpleTy) { |
14179 | 5 | case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_i32immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14180 | 0 | default: return 0; |
14181 | 5 | } |
14182 | 5 | } |
14183 | | |
14184 | | // FastEmit functions for ISD::SUB. |
14185 | | |
14186 | 28 | unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_i32immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14187 | 28 | if (RetVT.SimpleTy != MVT::i32) |
14188 | 0 | return 0; |
14189 | 28 | return fastEmitInst_ri(X86::SUB32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
14190 | 28 | } |
14191 | | |
14192 | 28 | unsigned fastEmit_ISD_SUB_ri_Predicate_i32immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14193 | 28 | switch (VT.SimpleTy) { |
14194 | 28 | case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_i32immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14195 | 0 | default: return 0; |
14196 | 28 | } |
14197 | 28 | } |
14198 | | |
14199 | | // FastEmit functions for ISD::XOR. |
14200 | | |
14201 | 17 | unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_i32immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14202 | 17 | if (RetVT.SimpleTy != MVT::i32) |
14203 | 0 | return 0; |
14204 | 17 | return fastEmitInst_ri(X86::XOR32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
14205 | 17 | } |
14206 | | |
14207 | 17 | unsigned fastEmit_ISD_XOR_ri_Predicate_i32immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14208 | 17 | switch (VT.SimpleTy) { |
14209 | 17 | case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_i32immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14210 | 0 | default: return 0; |
14211 | 17 | } |
14212 | 17 | } |
14213 | | |
14214 | | // FastEmit functions for X86ISD::BT. |
14215 | | |
14216 | 0 | unsigned fastEmit_X86ISD_BT_MVT_i32_ri_Predicate_i32immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14217 | 0 | if (RetVT.SimpleTy != MVT::i32) |
14218 | 0 | return 0; |
14219 | 0 | return fastEmitInst_ri(X86::BT32ri8, &X86::GR32RegClass, Op0, Op0IsKill, imm1); |
14220 | 0 | } |
14221 | | |
14222 | | unsigned fastEmit_X86ISD_BT_ri_Predicate_i32immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14223 | | switch (VT.SimpleTy) { |
14224 | | case MVT::i32: return fastEmit_X86ISD_BT_MVT_i32_ri_Predicate_i32immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14225 | | default: return 0; |
14226 | | } |
14227 | | } |
14228 | | |
14229 | | // Top-level FastEmit function. |
14230 | | |
14231 | 198 | unsigned fastEmit_ri_Predicate_i32immSExt8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14232 | 198 | switch (Opcode) { |
14233 | 87 | case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_i32immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14234 | 11 | case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_i32immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14235 | 18 | case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_i32immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14236 | 5 | case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_i32immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14237 | 28 | case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_i32immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14238 | 17 | case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_i32immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14239 | 0 | case X86ISD::BT: return fastEmit_X86ISD_BT_ri_Predicate_i32immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14240 | 32 | default: return 0; |
14241 | 198 | } |
14242 | 198 | } |
14243 | | |
14244 | | // FastEmit functions for ISD::ADD. |
14245 | | |
14246 | 66 | unsigned fastEmit_ISD_ADD_MVT_i64_ri_Predicate_i64immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14247 | 66 | if (RetVT.SimpleTy != MVT::i64) |
14248 | 0 | return 0; |
14249 | 66 | return fastEmitInst_ri(X86::ADD64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14250 | 66 | } |
14251 | | |
14252 | 66 | unsigned fastEmit_ISD_ADD_ri_Predicate_i64immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14253 | 66 | switch (VT.SimpleTy) { |
14254 | 66 | case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_i64immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14255 | 0 | default: return 0; |
14256 | 66 | } |
14257 | 66 | } |
14258 | | |
14259 | | // FastEmit functions for ISD::AND. |
14260 | | |
14261 | 15 | unsigned fastEmit_ISD_AND_MVT_i64_ri_Predicate_i64immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14262 | 15 | if (RetVT.SimpleTy != MVT::i64) |
14263 | 0 | return 0; |
14264 | 15 | return fastEmitInst_ri(X86::AND64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14265 | 15 | } |
14266 | | |
14267 | 15 | unsigned fastEmit_ISD_AND_ri_Predicate_i64immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14268 | 15 | switch (VT.SimpleTy) { |
14269 | 15 | case MVT::i64: return fastEmit_ISD_AND_MVT_i64_ri_Predicate_i64immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14270 | 0 | default: return 0; |
14271 | 15 | } |
14272 | 15 | } |
14273 | | |
14274 | | // FastEmit functions for ISD::MUL. |
14275 | | |
14276 | 3 | unsigned fastEmit_ISD_MUL_MVT_i64_ri_Predicate_i64immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14277 | 3 | if (RetVT.SimpleTy != MVT::i64) |
14278 | 0 | return 0; |
14279 | 3 | return fastEmitInst_ri(X86::IMUL64rri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14280 | 3 | } |
14281 | | |
14282 | 3 | unsigned fastEmit_ISD_MUL_ri_Predicate_i64immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14283 | 3 | switch (VT.SimpleTy) { |
14284 | 3 | case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_i64immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14285 | 0 | default: return 0; |
14286 | 3 | } |
14287 | 3 | } |
14288 | | |
14289 | | // FastEmit functions for ISD::OR. |
14290 | | |
14291 | 0 | unsigned fastEmit_ISD_OR_MVT_i64_ri_Predicate_i64immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14292 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14293 | 0 | return 0; |
14294 | 0 | return fastEmitInst_ri(X86::OR64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14295 | 0 | } |
14296 | | |
14297 | | unsigned fastEmit_ISD_OR_ri_Predicate_i64immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14298 | | switch (VT.SimpleTy) { |
14299 | | case MVT::i64: return fastEmit_ISD_OR_MVT_i64_ri_Predicate_i64immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14300 | | default: return 0; |
14301 | | } |
14302 | | } |
14303 | | |
14304 | | // FastEmit functions for ISD::SUB. |
14305 | | |
14306 | 7 | unsigned fastEmit_ISD_SUB_MVT_i64_ri_Predicate_i64immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14307 | 7 | if (RetVT.SimpleTy != MVT::i64) |
14308 | 0 | return 0; |
14309 | 7 | return fastEmitInst_ri(X86::SUB64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14310 | 7 | } |
14311 | | |
14312 | 7 | unsigned fastEmit_ISD_SUB_ri_Predicate_i64immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14313 | 7 | switch (VT.SimpleTy) { |
14314 | 7 | case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_ri_Predicate_i64immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14315 | 0 | default: return 0; |
14316 | 7 | } |
14317 | 7 | } |
14318 | | |
14319 | | // FastEmit functions for ISD::XOR. |
14320 | | |
14321 | 8 | unsigned fastEmit_ISD_XOR_MVT_i64_ri_Predicate_i64immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14322 | 8 | if (RetVT.SimpleTy != MVT::i64) |
14323 | 0 | return 0; |
14324 | 8 | return fastEmitInst_ri(X86::XOR64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14325 | 8 | } |
14326 | | |
14327 | 8 | unsigned fastEmit_ISD_XOR_ri_Predicate_i64immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14328 | 8 | switch (VT.SimpleTy) { |
14329 | 8 | case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_ri_Predicate_i64immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14330 | 0 | default: return 0; |
14331 | 8 | } |
14332 | 8 | } |
14333 | | |
14334 | | // FastEmit functions for X86ISD::BT. |
14335 | | |
14336 | 0 | unsigned fastEmit_X86ISD_BT_MVT_i64_ri_Predicate_i64immSExt8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14337 | 0 | if (RetVT.SimpleTy != MVT::i32) |
14338 | 0 | return 0; |
14339 | 0 | return fastEmitInst_ri(X86::BT64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14340 | 0 | } |
14341 | | |
14342 | | unsigned fastEmit_X86ISD_BT_ri_Predicate_i64immSExt8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14343 | | switch (VT.SimpleTy) { |
14344 | | case MVT::i64: return fastEmit_X86ISD_BT_MVT_i64_ri_Predicate_i64immSExt8(RetVT, Op0, Op0IsKill, imm1); |
14345 | | default: return 0; |
14346 | | } |
14347 | | } |
14348 | | |
14349 | | // Top-level FastEmit function. |
14350 | | |
14351 | 127 | unsigned fastEmit_ri_Predicate_i64immSExt8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14352 | 127 | switch (Opcode) { |
14353 | 66 | case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_i64immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14354 | 15 | case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_i64immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14355 | 3 | case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_i64immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14356 | 0 | case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_i64immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14357 | 7 | case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_i64immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14358 | 8 | case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_i64immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14359 | 0 | case X86ISD::BT: return fastEmit_X86ISD_BT_ri_Predicate_i64immSExt8(VT, RetVT, Op0, Op0IsKill, imm1); |
14360 | 28 | default: return 0; |
14361 | 127 | } |
14362 | 127 | } |
14363 | | |
14364 | | // FastEmit functions for ISD::ADD. |
14365 | | |
14366 | 5 | unsigned fastEmit_ISD_ADD_MVT_i64_ri_Predicate_i64immSExt32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14367 | 5 | if (RetVT.SimpleTy != MVT::i64) |
14368 | 0 | return 0; |
14369 | 5 | return fastEmitInst_ri(X86::ADD64ri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14370 | 5 | } |
14371 | | |
14372 | 5 | unsigned fastEmit_ISD_ADD_ri_Predicate_i64immSExt32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14373 | 5 | switch (VT.SimpleTy) { |
14374 | 5 | case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_i64immSExt32(RetVT, Op0, Op0IsKill, imm1); |
14375 | 0 | default: return 0; |
14376 | 5 | } |
14377 | 5 | } |
14378 | | |
14379 | | // FastEmit functions for ISD::AND. |
14380 | | |
14381 | 3 | unsigned fastEmit_ISD_AND_MVT_i64_ri_Predicate_i64immSExt32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14382 | 3 | if (RetVT.SimpleTy != MVT::i64) |
14383 | 0 | return 0; |
14384 | 3 | return fastEmitInst_ri(X86::AND64ri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14385 | 3 | } |
14386 | | |
14387 | 3 | unsigned fastEmit_ISD_AND_ri_Predicate_i64immSExt32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14388 | 3 | switch (VT.SimpleTy) { |
14389 | 3 | case MVT::i64: return fastEmit_ISD_AND_MVT_i64_ri_Predicate_i64immSExt32(RetVT, Op0, Op0IsKill, imm1); |
14390 | 0 | default: return 0; |
14391 | 3 | } |
14392 | 3 | } |
14393 | | |
14394 | | // FastEmit functions for ISD::MUL. |
14395 | | |
14396 | 0 | unsigned fastEmit_ISD_MUL_MVT_i64_ri_Predicate_i64immSExt32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14397 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14398 | 0 | return 0; |
14399 | 0 | return fastEmitInst_ri(X86::IMUL64rri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14400 | 0 | } |
14401 | | |
14402 | | unsigned fastEmit_ISD_MUL_ri_Predicate_i64immSExt32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14403 | | switch (VT.SimpleTy) { |
14404 | | case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_i64immSExt32(RetVT, Op0, Op0IsKill, imm1); |
14405 | | default: return 0; |
14406 | | } |
14407 | | } |
14408 | | |
14409 | | // FastEmit functions for ISD::OR. |
14410 | | |
14411 | 0 | unsigned fastEmit_ISD_OR_MVT_i64_ri_Predicate_i64immSExt32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14412 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14413 | 0 | return 0; |
14414 | 0 | return fastEmitInst_ri(X86::OR64ri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14415 | 0 | } |
14416 | | |
14417 | | unsigned fastEmit_ISD_OR_ri_Predicate_i64immSExt32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14418 | | switch (VT.SimpleTy) { |
14419 | | case MVT::i64: return fastEmit_ISD_OR_MVT_i64_ri_Predicate_i64immSExt32(RetVT, Op0, Op0IsKill, imm1); |
14420 | | default: return 0; |
14421 | | } |
14422 | | } |
14423 | | |
14424 | | // FastEmit functions for ISD::SUB. |
14425 | | |
14426 | 0 | unsigned fastEmit_ISD_SUB_MVT_i64_ri_Predicate_i64immSExt32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14427 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14428 | 0 | return 0; |
14429 | 0 | return fastEmitInst_ri(X86::SUB64ri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14430 | 0 | } |
14431 | | |
14432 | | unsigned fastEmit_ISD_SUB_ri_Predicate_i64immSExt32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14433 | | switch (VT.SimpleTy) { |
14434 | | case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_ri_Predicate_i64immSExt32(RetVT, Op0, Op0IsKill, imm1); |
14435 | | default: return 0; |
14436 | | } |
14437 | | } |
14438 | | |
14439 | | // FastEmit functions for ISD::XOR. |
14440 | | |
14441 | 0 | unsigned fastEmit_ISD_XOR_MVT_i64_ri_Predicate_i64immSExt32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14442 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14443 | 0 | return 0; |
14444 | 0 | return fastEmitInst_ri(X86::XOR64ri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1); |
14445 | 0 | } |
14446 | | |
14447 | | unsigned fastEmit_ISD_XOR_ri_Predicate_i64immSExt32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14448 | | switch (VT.SimpleTy) { |
14449 | | case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_ri_Predicate_i64immSExt32(RetVT, Op0, Op0IsKill, imm1); |
14450 | | default: return 0; |
14451 | | } |
14452 | | } |
14453 | | |
14454 | | // Top-level FastEmit function. |
14455 | | |
14456 | 36 | unsigned fastEmit_ri_Predicate_i64immSExt32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { |
14457 | 36 | switch (Opcode) { |
14458 | 5 | case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_i64immSExt32(VT, RetVT, Op0, Op0IsKill, imm1); |
14459 | 3 | case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_i64immSExt32(VT, RetVT, Op0, Op0IsKill, imm1); |
14460 | 0 | case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_i64immSExt32(VT, RetVT, Op0, Op0IsKill, imm1); |
14461 | 0 | case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_i64immSExt32(VT, RetVT, Op0, Op0IsKill, imm1); |
14462 | 0 | case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_i64immSExt32(VT, RetVT, Op0, Op0IsKill, imm1); |
14463 | 0 | case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_i64immSExt32(VT, RetVT, Op0, Op0IsKill, imm1); |
14464 | 28 | default: return 0; |
14465 | 36 | } |
14466 | 36 | } |
14467 | | |
14468 | | // FastEmit functions for ISD::Constant. |
14469 | | |
14470 | 5 | unsigned fastEmit_ISD_Constant_MVT_i8_i(MVT RetVT, uint64_t imm0) { |
14471 | 5 | if (RetVT.SimpleTy != MVT::i8) |
14472 | 0 | return 0; |
14473 | 5 | return fastEmitInst_i(X86::MOV8ri, &X86::GR8RegClass, imm0); |
14474 | 5 | } |
14475 | | |
14476 | 0 | unsigned fastEmit_ISD_Constant_MVT_i16_i(MVT RetVT, uint64_t imm0) { |
14477 | 0 | if (RetVT.SimpleTy != MVT::i16) |
14478 | 0 | return 0; |
14479 | 0 | return fastEmitInst_i(X86::MOV16ri, &X86::GR16RegClass, imm0); |
14480 | 0 | } |
14481 | | |
14482 | 21 | unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) { |
14483 | 21 | switch (VT.SimpleTy) { |
14484 | 5 | case MVT::i8: return fastEmit_ISD_Constant_MVT_i8_i(RetVT, imm0); |
14485 | 0 | case MVT::i16: return fastEmit_ISD_Constant_MVT_i16_i(RetVT, imm0); |
14486 | 16 | default: return 0; |
14487 | 21 | } |
14488 | 21 | } |
14489 | | |
14490 | | // Top-level FastEmit function. |
14491 | | |
14492 | 21 | unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override { |
14493 | 21 | switch (Opcode) { |
14494 | 21 | case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0); |
14495 | 0 | default: return 0; |
14496 | 21 | } |
14497 | 21 | } |
14498 | | |