Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/include/llvm/CodeGen/MachineInstr.h
Line
Count
Source (jump to first uncovered line)
1
//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This file contains the declaration of the MachineInstr class, which is the
11
// basic representation for all target dependent machine instructions used by
12
// the back end.
13
//
14
//===----------------------------------------------------------------------===//
15
16
#ifndef LLVM_CODEGEN_MACHINEINSTR_H
17
#define LLVM_CODEGEN_MACHINEINSTR_H
18
19
#include "llvm/ADT/DenseMapInfo.h"
20
#include "llvm/ADT/ilist.h"
21
#include "llvm/ADT/ilist_node.h"
22
#include "llvm/ADT/iterator_range.h"
23
#include "llvm/Analysis/AliasAnalysis.h"
24
#include "llvm/CodeGen/MachineOperand.h"
25
#include "llvm/IR/DebugLoc.h"
26
#include "llvm/IR/InlineAsm.h"
27
#include "llvm/MC/MCInstrDesc.h"
28
#include "llvm/Support/ArrayRecycler.h"
29
#include "llvm/Target/TargetOpcodes.h"
30
#include <algorithm>
31
#include <cassert>
32
#include <cstdint>
33
#include <utility>
34
35
namespace llvm {
36
37
template <typename T> class ArrayRef;
38
class DIExpression;
39
class DILocalVariable;
40
class MachineBasicBlock;
41
class MachineFunction;
42
class MachineMemOperand;
43
class MachineRegisterInfo;
44
class ModuleSlotTracker;
45
class raw_ostream;
46
template <typename T> class SmallVectorImpl;
47
class StringRef;
48
class TargetInstrInfo;
49
class TargetRegisterClass;
50
class TargetRegisterInfo;
51
52
//===----------------------------------------------------------------------===//
53
/// Representation of each machine instruction.
54
///
55
/// This class isn't a POD type, but it must have a trivial destructor. When a
56
/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
57
/// without having their destructor called.
58
///
59
class MachineInstr
60
    : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
61
                                    ilist_sentinel_tracking<true>> {
62
public:
63
  using mmo_iterator = MachineMemOperand **;
64
65
  /// Flags to specify different kinds of comments to output in
66
  /// assembly code.  These flags carry semantic information not
67
  /// otherwise easily derivable from the IR text.
68
  ///
69
  enum CommentFlag {
70
    ReloadReuse = 0x1 // higher bits are reserved for target dep comments.
71
  };
72
73
  enum MIFlag {
74
    NoFlags      = 0,
75
    FrameSetup   = 1 << 0,              // Instruction is used as a part of
76
                                        // function frame setup code.
77
    FrameDestroy = 1 << 1,              // Instruction is used as a part of
78
                                        // function frame destruction code.
79
    BundledPred  = 1 << 2,              // Instruction has bundled predecessors.
80
    BundledSucc  = 1 << 3               // Instruction has bundled successors.
81
  };
82
83
private:
84
  const MCInstrDesc *MCID;              // Instruction descriptor.
85
  MachineBasicBlock *Parent = nullptr;  // Pointer to the owning basic block.
86
87
  // Operands are allocated by an ArrayRecycler.
88
  MachineOperand *Operands = nullptr;   // Pointer to the first operand.
89
  unsigned NumOperands = 0;             // Number of operands on instruction.
90
  using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
91
  OperandCapacity CapOperands;          // Capacity of the Operands array.
92
93
  uint8_t Flags = 0;                    // Various bits of additional
94
                                        // information about machine
95
                                        // instruction.
96
97
  uint8_t AsmPrinterFlags = 0;          // Various bits of information used by
98
                                        // the AsmPrinter to emit helpful
99
                                        // comments.  This is *not* semantic
100
                                        // information.  Do not use this for
101
                                        // anything other than to convey comment
102
                                        // information to AsmPrinter.
103
104
  uint8_t NumMemRefs = 0;               // Information on memory references.
105
  // Note that MemRefs == nullptr,  means 'don't know', not 'no memory access'.
106
  // Calling code must treat missing information conservatively.  If the number
107
  // of memory operands required to be precise exceeds the maximum value of
108
  // NumMemRefs - currently 256 - we remove the operands entirely. Note also
109
  // that this is a non-owning reference to a shared copy on write buffer owned
110
  // by the MachineFunction and created via MF.allocateMemRefsArray.
111
  mmo_iterator MemRefs = nullptr;
112
113
  DebugLoc debugLoc;                    // Source line information.
114
115
  // Intrusive list support
116
  friend struct ilist_traits<MachineInstr>;
117
  friend struct ilist_callback_traits<MachineBasicBlock>;
118
150M
  void setParent(MachineBasicBlock *P) { Parent = P; }
119
120
  /// This constructor creates a copy of the given
121
  /// MachineInstr in the given MachineFunction.
122
  MachineInstr(MachineFunction &, const MachineInstr &);
123
124
  /// This constructor create a MachineInstr and add the implicit operands.
125
  /// It reserves space for number of operands specified by
126
  /// MCInstrDesc.  An explicit DebugLoc is supplied.
127
  MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
128
               bool NoImp = false);
129
130
  // MachineInstrs are pool-allocated and owned by MachineFunction.
131
  friend class MachineFunction;
132
133
public:
134
  MachineInstr(const MachineInstr &) = delete;
135
  MachineInstr &operator=(const MachineInstr &) = delete;
136
  // Use MachineFunction::DeleteMachineInstr() instead.
137
  ~MachineInstr() = delete;
138
139
202M
  const MachineBasicBlock* getParent() const { return Parent; }
140
1.06G
  MachineBasicBlock* getParent() { return Parent; }
141
142
  /// Return the asm printer flags bitvector.
143
15.2k
  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
144
145
  /// Clear the AsmPrinter bitvector.
146
0
  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
147
148
  /// Return whether an AsmPrinter flag is set.
149
1.31M
  bool getAsmPrinterFlag(CommentFlag Flag) const {
150
1.31M
    return AsmPrinterFlags & Flag;
151
1.31M
  }
152
153
  /// Set a flag for the AsmPrinter.
154
16.3k
  void setAsmPrinterFlag(uint8_t Flag) {
155
16.3k
    AsmPrinterFlags |= Flag;
156
16.3k
  }
157
158
  /// Clear specific AsmPrinter flags.
159
0
  void clearAsmPrinterFlag(CommentFlag Flag) {
160
0
    AsmPrinterFlags &= ~Flag;
161
0
  }
162
163
  /// Return the MI flags bitvector.
164
643k
  uint8_t getFlags() const {
165
643k
    return Flags;
166
643k
  }
167
168
  /// Return whether an MI flag is set.
169
7.12G
  bool getFlag(MIFlag Flag) const {
170
7.12G
    return Flags & Flag;
171
7.12G
  }
172
173
  /// Set a MI flag.
174
2.95M
  void setFlag(MIFlag Flag) {
175
2.95M
    Flags |= (uint8_t)Flag;
176
2.95M
  }
177
178
3.01M
  void setFlags(unsigned flags) {
179
3.01M
    // Filter out the automatically maintained flags.
180
3.01M
    unsigned Mask = BundledPred | BundledSucc;
181
3.01M
    Flags = (Flags & Mask) | (flags & ~Mask);
182
3.01M
  }
183
184
  /// clearFlag - Clear a MI flag.
185
112k
  void clearFlag(MIFlag Flag) {
186
112k
    Flags &= ~((uint8_t)Flag);
187
112k
  }
188
189
  /// Return true if MI is in a bundle (but not the first MI in a bundle).
190
  ///
191
  /// A bundle looks like this before it's finalized:
192
  ///   ----------------
193
  ///   |      MI      |
194
  ///   ----------------
195
  ///          |
196
  ///   ----------------
197
  ///   |      MI    * |
198
  ///   ----------------
199
  ///          |
200
  ///   ----------------
201
  ///   |      MI    * |
202
  ///   ----------------
203
  /// In this case, the first MI starts a bundle but is not inside a bundle, the
204
  /// next 2 MIs are considered "inside" the bundle.
205
  ///
206
  /// After a bundle is finalized, it looks like this:
207
  ///   ----------------
208
  ///   |    Bundle    |
209
  ///   ----------------
210
  ///          |
211
  ///   ----------------
212
  ///   |      MI    * |
213
  ///   ----------------
214
  ///          |
215
  ///   ----------------
216
  ///   |      MI    * |
217
  ///   ----------------
218
  ///          |
219
  ///   ----------------
220
  ///   |      MI    * |
221
  ///   ----------------
222
  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
223
  /// a bundle, but the next three MIs are.
224
194M
  bool isInsideBundle() const {
225
194M
    return getFlag(BundledPred);
226
194M
  }
227
228
  /// Return true if this instruction part of a bundle. This is true
229
  /// if either itself or its following instruction is marked "InsideBundle".
230
2.38G
  bool isBundled() const {
231
2.38G
    return isBundledWithPred() || isBundledWithSucc();
232
2.38G
  }
233
234
  /// Return true if this instruction is part of a bundle, and it is not the
235
  /// first instruction in the bundle.
236
3.18G
  bool isBundledWithPred() const { return getFlag(BundledPred); }
237
238
  /// Return true if this instruction is part of a bundle, and it is not the
239
  /// last instruction in the bundle.
240
3.73G
  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
241
242
  /// Bundle this instruction with its predecessor. This can be an unbundled
243
  /// instruction, or it can be the first instruction in a bundle.
244
  void bundleWithPred();
245
246
  /// Bundle this instruction with its successor. This can be an unbundled
247
  /// instruction, or it can be the last instruction in a bundle.
248
  void bundleWithSucc();
249
250
  /// Break bundle above this instruction.
251
  void unbundleFromPred();
252
253
  /// Break bundle below this instruction.
254
  void unbundleFromSucc();
255
256
  /// Returns the debug location id of this MachineInstr.
257
48.7M
  const DebugLoc &getDebugLoc() const { return debugLoc; }
258
259
  /// Return the debug variable referenced by
260
  /// this DBG_VALUE instruction.
261
  const DILocalVariable *getDebugVariable() const;
262
263
  /// Return the complex address expression referenced by
264
  /// this DBG_VALUE instruction.
265
  const DIExpression *getDebugExpression() const;
266
267
  /// Emit an error referring to the source location of this instruction.
268
  /// This should only be used for inline assembly that is somehow
269
  /// impossible to compile. Other errors should have been handled much
270
  /// earlier.
271
  ///
272
  /// If this method returns, the caller should try to recover from the error.
273
  void emitError(StringRef Msg) const;
274
275
  /// Returns the target instruction descriptor of this MachineInstr.
276
3.63G
  const MCInstrDesc &getDesc() const { return *MCID; }
277
278
  /// Returns the opcode of this MachineInstr.
279
7.62G
  unsigned getOpcode() const { return MCID->Opcode; }
280
281
  /// Access to explicit operands of the instruction.
282
3.56G
  unsigned getNumOperands() const { return NumOperands; }
283
284
1.92G
  const MachineOperand& getOperand(unsigned i) const {
285
1.92G
    assert(i < getNumOperands() && "getOperand() out of range!");
286
1.92G
    return Operands[i];
287
1.92G
  }
288
2.34G
  MachineOperand& getOperand(unsigned i) {
289
2.34G
    assert(i < getNumOperands() && "getOperand() out of range!");
290
2.34G
    return Operands[i];
291
2.34G
  }
292
293
  /// Returns the number of non-implicit operands.
294
  unsigned getNumExplicitOperands() const;
295
296
  /// iterator/begin/end - Iterate over all operands of a machine instruction.
297
  using mop_iterator = MachineOperand *;
298
  using const_mop_iterator = const MachineOperand *;
299
300
356M
  mop_iterator operands_begin() { return Operands; }
301
347M
  mop_iterator operands_end() { return Operands + NumOperands; }
302
303
330M
  const_mop_iterator operands_begin() const { return Operands; }
304
302M
  const_mop_iterator operands_end() const { return Operands + NumOperands; }
305
306
262M
  iterator_range<mop_iterator> operands() {
307
262M
    return make_range(operands_begin(), operands_end());
308
262M
  }
309
223M
  iterator_range<const_mop_iterator> operands() const {
310
223M
    return make_range(operands_begin(), operands_end());
311
223M
  }
312
7.66M
  iterator_range<mop_iterator> explicit_operands() {
313
7.66M
    return make_range(operands_begin(),
314
7.66M
                      operands_begin() + getNumExplicitOperands());
315
7.66M
  }
316
3.66M
  iterator_range<const_mop_iterator> explicit_operands() const {
317
3.66M
    return make_range(operands_begin(),
318
3.66M
                      operands_begin() + getNumExplicitOperands());
319
3.66M
  }
320
7.64M
  iterator_range<mop_iterator> implicit_operands() {
321
7.64M
    return make_range(explicit_operands().end(), operands_end());
322
7.64M
  }
323
3.28M
  iterator_range<const_mop_iterator> implicit_operands() const {
324
3.28M
    return make_range(explicit_operands().end(), operands_end());
325
3.28M
  }
326
  /// Returns a range over all explicit operands that are register definitions.
327
  /// Implicit definition are not included!
328
257k
  iterator_range<mop_iterator> defs() {
329
257k
    return make_range(operands_begin(),
330
257k
                      operands_begin() + getDesc().getNumDefs());
331
257k
  }
332
  /// \copydoc defs()
333
902k
  iterator_range<const_mop_iterator> defs() const {
334
902k
    return make_range(operands_begin(),
335
902k
                      operands_begin() + getDesc().getNumDefs());
336
902k
  }
337
  /// Returns a range that includes all operands that are register uses.
338
  /// This may include unrelated operands which are not register uses.
339
206k
  iterator_range<mop_iterator> uses() {
340
206k
    return make_range(operands_begin() + getDesc().getNumDefs(),
341
206k
                      operands_end());
342
206k
  }
343
  /// \copydoc uses()
344
56.9M
  iterator_range<const_mop_iterator> uses() const {
345
56.9M
    return make_range(operands_begin() + getDesc().getNumDefs(),
346
56.9M
                      operands_end());
347
56.9M
  }
348
1.06k
  iterator_range<mop_iterator> explicit_uses() {
349
1.06k
    return make_range(operands_begin() + getDesc().getNumDefs(),
350
1.06k
                      operands_begin() + getNumExplicitOperands() );
351
1.06k
  }
352
0
  iterator_range<const_mop_iterator> explicit_uses() const {
353
0
    return make_range(operands_begin() + getDesc().getNumDefs(),
354
0
                      operands_begin() + getNumExplicitOperands() );
355
0
  }
356
357
  /// Returns the number of the operand iterator \p I points to.
358
21.3M
  unsigned getOperandNo(const_mop_iterator I) const {
359
21.3M
    return I - operands_begin();
360
21.3M
  }
361
362
  /// Access to memory operands of the instruction
363
198M
  mmo_iterator memoperands_begin() const { return MemRefs; }
364
179M
  mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
365
  /// Return true if we don't have any memory operands which described the the
366
  /// memory access done by this instruction.  If this is true, calling code
367
  /// must be conservative.
368
96.1M
  bool memoperands_empty() const { return NumMemRefs == 0; }
369
370
22.1M
  iterator_range<mmo_iterator>  memoperands() {
371
22.1M
    return make_range(memoperands_begin(), memoperands_end());
372
22.1M
  }
373
107M
  iterator_range<mmo_iterator> memoperands() const {
374
107M
    return make_range(memoperands_begin(), memoperands_end());
375
107M
  }
376
377
  /// Return true if this instruction has exactly one MachineMemOperand.
378
19.3M
  bool hasOneMemOperand() const {
379
19.3M
    return NumMemRefs == 1;
380
19.3M
  }
381
382
  /// Return the number of memory operands.
383
11.5M
  unsigned getNumMemOperands() const { return NumMemRefs; }
384
385
  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
386
  /// queries but they are bundle aware.
387
388
  enum QueryType {
389
    IgnoreBundle,    // Ignore bundles
390
    AnyInBundle,     // Return true if any instruction in bundle has property
391
    AllInBundle      // Return true if all instructions in bundle have property
392
  };
393
394
  /// Return true if the instruction (or in the case of a bundle,
395
  /// the instructions inside the bundle) has the specified property.
396
  /// The first argument is the property being queried.
397
  /// The second argument indicates whether the query should look inside
398
  /// instruction bundles.
399
2.85G
  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
400
2.85G
    // Inline the fast path for unbundled or bundle-internal instructions.
401
2.85G
    if (
Type == IgnoreBundle || 2.85G
!isBundled()2.38G
||
isBundledWithPred()288k
)
402
2.85G
      return getDesc().getFlags() & (1ULL << MCFlag);
403
2.85G
404
2.85G
    // If this is the first instruction in a bundle, take the slow path.
405
264k
    return hasPropertyInBundle(1ULL << MCFlag, Type);
406
2.85G
  }
407
408
  /// Return true if this instruction can have a variable number of operands.
409
  /// In this case, the variable operands will be after the normal
410
  /// operands but before the implicit definitions and uses (if any are
411
  /// present).
412
25.7M
  bool isVariadic(QueryType Type = IgnoreBundle) const {
413
25.7M
    return hasProperty(MCID::Variadic, Type);
414
25.7M
  }
415
416
  /// Set if this instruction has an optional definition, e.g.
417
  /// ARM instructions which can set condition code if 's' bit is set.
418
12.5k
  bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
419
12.5k
    return hasProperty(MCID::HasOptionalDef, Type);
420
12.5k
  }
421
422
  /// Return true if this is a pseudo instruction that doesn't
423
  /// correspond to a real machine instruction.
424
59.6M
  bool isPseudo(QueryType Type = IgnoreBundle) const {
425
59.6M
    return hasProperty(MCID::Pseudo, Type);
426
59.6M
  }
427
428
15.4M
  bool isReturn(QueryType Type = AnyInBundle) const {
429
15.4M
    return hasProperty(MCID::Return, Type);
430
15.4M
  }
431
432
313M
  bool isCall(QueryType Type = AnyInBundle) const {
433
313M
    return hasProperty(MCID::Call, Type);
434
313M
  }
435
436
  /// Returns true if the specified instruction stops control flow
437
  /// from executing the instruction immediately following it.  Examples include
438
  /// unconditional branches and return instructions.
439
140M
  bool isBarrier(QueryType Type = AnyInBundle) const {
440
140M
    return hasProperty(MCID::Barrier, Type);
441
140M
  }
442
443
  /// Returns true if this instruction part of the terminator for a basic block.
444
  /// Typically this is things like return and branch instructions.
445
  ///
446
  /// Various passes use this to insert code into the bottom of a basic block,
447
  /// but before control flow occurs.
448
540M
  bool isTerminator(QueryType Type = AnyInBundle) const {
449
540M
    return hasProperty(MCID::Terminator, Type);
450
540M
  }
451
452
  /// Returns true if this is a conditional, unconditional, or indirect branch.
453
  /// Predicates below can be used to discriminate between
454
  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
455
  /// get more information.
456
166M
  bool isBranch(QueryType Type = AnyInBundle) const {
457
166M
    return hasProperty(MCID::Branch, Type);
458
166M
  }
459
460
  /// Return true if this is an indirect branch, such as a
461
  /// branch through a register.
462
56.4M
  bool isIndirectBranch(QueryType Type = AnyInBundle) const {
463
56.4M
    return hasProperty(MCID::IndirectBranch, Type);
464
56.4M
  }
465
466
  /// Return true if this is a branch which may fall
467
  /// through to the next instruction or may transfer control flow to some other
468
  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
469
  /// information about this branch.
470
39.3M
  bool isConditionalBranch(QueryType Type = AnyInBundle) const {
471
39.3M
    return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
472
39.3M
  }
473
474
  /// Return true if this is a branch which always
475
  /// transfers control flow to some other block.  The
476
  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
477
  /// about this branch.
478
8.15M
  bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
479
8.15M
    return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
480
8.15M
  }
481
482
  /// Return true if this instruction has a predicate operand that
483
  /// controls execution.  It may be set to 'always', or may be set to other
484
  /// values.   There are various methods in TargetInstrInfo that can be used to
485
  /// control and modify the predicate in this instruction.
486
34.6M
  bool isPredicable(QueryType Type = AllInBundle) const {
487
34.6M
    // If it's a bundle than all bundled instructions must be predicable for this
488
34.6M
    // to return true.
489
34.6M
    return hasProperty(MCID::Predicable, Type);
490
34.6M
  }
491
492
  /// Return true if this instruction is a comparison.
493
36.9M
  bool isCompare(QueryType Type = IgnoreBundle) const {
494
36.9M
    return hasProperty(MCID::Compare, Type);
495
36.9M
  }
496
497
  /// Return true if this instruction is a move immediate
498
  /// (including conditional moves) instruction.
499
38.3M
  bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
500
38.3M
    return hasProperty(MCID::MoveImm, Type);
501
38.3M
  }
502
503
  /// Return true if this instruction is a bitcast instruction.
504
42.8M
  bool isBitcast(QueryType Type = IgnoreBundle) const {
505
42.8M
    return hasProperty(MCID::Bitcast, Type);
506
42.8M
  }
507
508
  /// Return true if this instruction is a select instruction.
509
35.9M
  bool isSelect(QueryType Type = IgnoreBundle) const {
510
35.9M
    return hasProperty(MCID::Select, Type);
511
35.9M
  }
512
513
  /// Return true if this instruction cannot be safely duplicated.
514
  /// For example, if the instruction has a unique labels attached
515
  /// to it, duplicating it would cause multiple definition errors.
516
27.4M
  bool isNotDuplicable(QueryType Type = AnyInBundle) const {
517
27.4M
    return hasProperty(MCID::NotDuplicable, Type);
518
27.4M
  }
519
520
  /// Return true if this instruction is convergent.
521
  /// Convergent instructions can not be made control-dependent on any
522
  /// additional values.
523
47.0M
  bool isConvergent(QueryType Type = AnyInBundle) const {
524
47.0M
    if (
isInlineAsm()47.0M
) {
525
3.43k
      unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
526
3.43k
      if (ExtraInfo & InlineAsm::Extra_IsConvergent)
527
2
        return true;
528
3.43k
    }
529
47.0M
    return hasProperty(MCID::Convergent, Type);
530
47.0M
  }
531
532
  /// Returns true if the specified instruction has a delay slot
533
  /// which must be filled by the code generator.
534
126k
  bool hasDelaySlot(QueryType Type = AnyInBundle) const {
535
126k
    return hasProperty(MCID::DelaySlot, Type);
536
126k
  }
537
538
  /// Return true for instructions that can be folded as
539
  /// memory operands in other instructions. The most common use for this
540
  /// is instructions that are simple loads from memory that don't modify
541
  /// the loaded value in any way, but it can also be used for instructions
542
  /// that can be expressed as constant-pool loads, such as V_SETALLONES
543
  /// on x86, to allow them to be folded when it is beneficial.
544
  /// This should only be set on instructions that return a value in their
545
  /// only virtual register definition.
546
46.0M
  bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
547
46.0M
    return hasProperty(MCID::FoldableAsLoad, Type);
548
46.0M
  }
549
550
  /// \brief Return true if this instruction behaves
551
  /// the same way as the generic REG_SEQUENCE instructions.
552
  /// E.g., on ARM,
553
  /// dX VMOVDRR rY, rZ
554
  /// is equivalent to
555
  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
556
  ///
557
  /// Note that for the optimizers to be able to take advantage of
558
  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
559
  /// override accordingly.
560
42.6M
  bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
561
42.6M
    return hasProperty(MCID::RegSequence, Type);
562
42.6M
  }
563
564
  /// \brief Return true if this instruction behaves
565
  /// the same way as the generic EXTRACT_SUBREG instructions.
566
  /// E.g., on ARM,
567
  /// rX, rY VMOVRRD dZ
568
  /// is equivalent to two EXTRACT_SUBREG:
569
  /// rX = EXTRACT_SUBREG dZ, ssub_0
570
  /// rY = EXTRACT_SUBREG dZ, ssub_1
571
  ///
572
  /// Note that for the optimizers to be able to take advantage of
573
  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
574
  /// override accordingly.
575
42.4M
  bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
576
42.4M
    return hasProperty(MCID::ExtractSubreg, Type);
577
42.4M
  }
578
579
  /// \brief Return true if this instruction behaves
580
  /// the same way as the generic INSERT_SUBREG instructions.
581
  /// E.g., on ARM,
582
  /// dX = VSETLNi32 dY, rZ, Imm
583
  /// is equivalent to a INSERT_SUBREG:
584
  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
585
  ///
586
  /// Note that for the optimizers to be able to take advantage of
587
  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
588
  /// override accordingly.
589
42.4M
  bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
590
42.4M
    return hasProperty(MCID::InsertSubreg, Type);
591
42.4M
  }
592
593
  //===--------------------------------------------------------------------===//
594
  // Side Effect Analysis
595
  //===--------------------------------------------------------------------===//
596
597
  /// Return true if this instruction could possibly read memory.
598
  /// Instructions with this flag set are not necessarily simple load
599
  /// instructions, they may load a value and modify it, for example.
600
359M
  bool mayLoad(QueryType Type = AnyInBundle) const {
601
359M
    if (
isInlineAsm()359M
) {
602
30.1k
      unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
603
30.1k
      if (ExtraInfo & InlineAsm::Extra_MayLoad)
604
7.58k
        return true;
605
30.1k
    }
606
359M
    return hasProperty(MCID::MayLoad, Type);
607
359M
  }
608
609
  /// Return true if this instruction could possibly modify memory.
610
  /// Instructions with this flag set are not necessarily simple store
611
  /// instructions, they may store a modified value based on their operands, or
612
  /// may not actually modify anything, for example.
613
392M
  bool mayStore(QueryType Type = AnyInBundle) const {
614
392M
    if (
isInlineAsm()392M
) {
615
35.9k
      unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
616
35.9k
      if (ExtraInfo & InlineAsm::Extra_MayStore)
617
9.78k
        return true;
618
35.9k
    }
619
392M
    return hasProperty(MCID::MayStore, Type);
620
392M
  }
621
622
  /// Return true if this instruction could possibly read or modify memory.
623
7.67M
  bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
624
5.72M
    return mayLoad(Type) || mayStore(Type);
625
7.67M
  }
626
627
  //===--------------------------------------------------------------------===//
628
  // Flags that indicate whether an instruction can be modified by a method.
629
  //===--------------------------------------------------------------------===//
630
631
  /// Return true if this may be a 2- or 3-address
632
  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
633
  /// result if Y and Z are exchanged.  If this flag is set, then the
634
  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
635
  /// instruction.
636
  ///
637
  /// Note that this flag may be set on instructions that are only commutable
638
  /// sometimes.  In these cases, the call to commuteInstruction will fail.
639
  /// Also note that some instructions require non-trivial modification to
640
  /// commute them.
641
25.6M
  bool isCommutable(QueryType Type = IgnoreBundle) const {
642
25.6M
    return hasProperty(MCID::Commutable, Type);
643
25.6M
  }
644
645
  /// Return true if this is a 2-address instruction
646
  /// which can be changed into a 3-address instruction if needed.  Doing this
647
  /// transformation can be profitable in the register allocator, because it
648
  /// means that the instruction can use a 2-address form if possible, but
649
  /// degrade into a less efficient form if the source and dest register cannot
650
  /// be assigned to the same register.  For example, this allows the x86
651
  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
652
  /// is the same speed as the shift but has bigger code size.
653
  ///
654
  /// If this returns true, then the target must implement the
655
  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
656
  /// is allowed to fail if the transformation isn't valid for this specific
657
  /// instruction (e.g. shl reg, 4 on x86).
658
  ///
659
273k
  bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
660
273k
    return hasProperty(MCID::ConvertibleTo3Addr, Type);
661
273k
  }
662
663
  /// Return true if this instruction requires
664
  /// custom insertion support when the DAG scheduler is inserting it into a
665
  /// machine basic block.  If this is true for the instruction, it basically
666
  /// means that it is a pseudo instruction used at SelectionDAG time that is
667
  /// expanded out into magic code by the target when MachineInstrs are formed.
668
  ///
669
  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
670
  /// is used to insert this into the MachineBasicBlock.
671
38.1M
  bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
672
38.1M
    return hasProperty(MCID::UsesCustomInserter, Type);
673
38.1M
  }
674
675
  /// Return true if this instruction requires *adjustment*
676
  /// after instruction selection by calling a target hook. For example, this
677
  /// can be used to fill in ARM 's' optional operand depending on whether
678
  /// the conditional flag register is used.
679
0
  bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
680
0
    return hasProperty(MCID::HasPostISelHook, Type);
681
0
  }
682
683
  /// Returns true if this instruction is a candidate for remat.
684
  /// This flag is deprecated, please don't use it anymore.  If this
685
  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
686
  /// verify the instruction is really rematable.
687
0
  bool isRematerializable(QueryType Type = AllInBundle) const {
688
0
    // It's only possible to re-mat a bundle if all bundled instructions are
689
0
    // re-materializable.
690
0
    return hasProperty(MCID::Rematerializable, Type);
691
0
  }
692
693
  /// Returns true if this instruction has the same cost (or less) than a move
694
  /// instruction. This is useful during certain types of optimizations
695
  /// (e.g., remat during two-address conversion or machine licm)
696
  /// where we would like to remat or hoist the instruction, but not if it costs
697
  /// more than moving the instruction into the appropriate register. Note, we
698
  /// are not marking copies from and to the same register class with this flag.
699
5.05M
  bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
700
5.05M
    // Only returns true for a bundle if all bundled instructions are cheap.
701
5.05M
    return hasProperty(MCID::CheapAsAMove, Type);
702
5.05M
  }
703
704
  /// Returns true if this instruction source operands
705
  /// have special register allocation requirements that are not captured by the
706
  /// operand register classes. e.g. ARM::STRD's two source registers must be an
707
  /// even / odd pair, ARM::STM registers have to be in ascending order.
708
  /// Post-register allocation passes should not attempt to change allocations
709
  /// for sources of instructions with this flag.
710
75.8k
  bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
711
75.8k
    return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
712
75.8k
  }
713
714
  /// Returns true if this instruction def operands
715
  /// have special register allocation requirements that are not captured by the
716
  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
717
  /// even / odd pair, ARM::LDM registers have to be in ascending order.
718
  /// Post-register allocation passes should not attempt to change allocations
719
  /// for definitions of instructions with this flag.
720
57.7k
  bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
721
57.7k
    return hasProperty(MCID::ExtraDefRegAllocReq, Type);
722
57.7k
  }
723
724
  enum MICheckType {
725
    CheckDefs,      // Check all operands for equality
726
    CheckKillDead,  // Check all operands including kill / dead markers
727
    IgnoreDefs,     // Ignore all definitions
728
    IgnoreVRegDefs  // Ignore virtual register definitions
729
  };
730
731
  /// Return true if this instruction is identical to \p Other.
732
  /// Two instructions are identical if they have the same opcode and all their
733
  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
734
  /// Note that this means liveness related flags (dead, undef, kill) do not
735
  /// affect the notion of identical.
736
  bool isIdenticalTo(const MachineInstr &Other,
737
                     MICheckType Check = CheckDefs) const;
738
739
  /// Unlink 'this' from the containing basic block, and return it without
740
  /// deleting it.
741
  ///
742
  /// This function can not be used on bundled instructions, use
743
  /// removeFromBundle() to remove individual instructions from a bundle.
744
  MachineInstr *removeFromParent();
745
746
  /// Unlink this instruction from its basic block and return it without
747
  /// deleting it.
748
  ///
749
  /// If the instruction is part of a bundle, the other instructions in the
750
  /// bundle remain bundled.
751
  MachineInstr *removeFromBundle();
752
753
  /// Unlink 'this' from the containing basic block and delete it.
754
  ///
755
  /// If this instruction is the header of a bundle, the whole bundle is erased.
756
  /// This function can not be used for instructions inside a bundle, use
757
  /// eraseFromBundle() to erase individual bundled instructions.
758
  void eraseFromParent();
759
760
  /// Unlink 'this' from the containing basic block and delete it.
761
  ///
762
  /// For all definitions mark their uses in DBG_VALUE nodes
763
  /// as undefined. Otherwise like eraseFromParent().
764
  void eraseFromParentAndMarkDBGValuesForRemoval();
765
766
  /// Unlink 'this' form its basic block and delete it.
767
  ///
768
  /// If the instruction is part of a bundle, the other instructions in the
769
  /// bundle remain bundled.
770
  void eraseFromBundle();
771
772
254M
  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
773
253M
  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
774
775
  /// Returns true if the MachineInstr represents a label.
776
253M
  bool isLabel() const 
{ return isEHLabel() || 253M
isGCLabel()253M
; }
777
778
253M
  bool isCFIInstruction() const {
779
253M
    return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
780
253M
  }
781
782
  // True if the instruction represents a position in the function.
783
253M
  bool isPosition() const 
{ return isLabel() || 253M
isCFIInstruction()253M
; }
784
785
1.03G
  bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
786
787
  /// A DBG_VALUE is indirect iff the first operand is a register and
788
  /// the second operand is an immediate.
789
1.84k
  bool isIndirectDebugValue() const {
790
1.84k
    return isDebugValue()
791
1.63k
      && getOperand(0).isReg()
792
1.63k
      && getOperand(1).isImm();
793
1.84k
  }
794
795
294M
  bool isPHI() const {
796
294M
    return getOpcode() == TargetOpcode::PHI ||
797
272M
           getOpcode() == TargetOpcode::G_PHI;
798
294M
  }
799
98.9M
  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
800
219M
  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
801
1.56G
  bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
802
803
0
  bool isMSInlineAsm() const {
804
0
    return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
805
0
  }
806
807
  bool isStackAligningInlineAsm() const;
808
  InlineAsm::AsmDialect getInlineAsmDialect() const;
809
810
51.1M
  bool isInsertSubreg() const {
811
51.1M
    return getOpcode() == TargetOpcode::INSERT_SUBREG;
812
51.1M
  }
813
814
83.3M
  bool isSubregToReg() const {
815
83.3M
    return getOpcode() == TargetOpcode::SUBREG_TO_REG;
816
83.3M
  }
817
818
64.7M
  bool isRegSequence() const {
819
64.7M
    return getOpcode() == TargetOpcode::REG_SEQUENCE;
820
64.7M
  }
821
822
60.9M
  bool isBundle() const {
823
60.9M
    return getOpcode() == TargetOpcode::BUNDLE;
824
60.9M
  }
825
826
727M
  bool isCopy() const {
827
727M
    return getOpcode() == TargetOpcode::COPY;
828
727M
  }
829
830
17.4M
  bool isFullCopy() const {
831
17.4M
    return isCopy() && 
!getOperand(0).getSubReg()8.38M
&&
!getOperand(1).getSubReg()8.14M
;
832
17.4M
  }
833
834
24.4M
  bool isExtractSubreg() const {
835
24.4M
    return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
836
24.4M
  }
837
838
  /// Return true if the instruction behaves like a copy.
839
  /// This does not include native copy instructions.
840
86.3M
  bool isCopyLike() const {
841
53.8M
    return isCopy() || isSubregToReg();
842
86.3M
  }
843
844
  /// Return true is the instruction is an identity copy.
845
62.6M
  bool isIdentityCopy() const {
846
16.7M
    return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
847
3.87M
      getOperand(0).getSubReg() == getOperand(1).getSubReg();
848
62.6M
  }
849
850
  /// Return true if this instruction doesn't produce any output in the form of
851
  /// executable instructions.
852
58.4M
  bool isMetaInstruction() const {
853
58.4M
    switch (getOpcode()) {
854
56.5M
    default:
855
56.5M
      return false;
856
1.81M
    case TargetOpcode::IMPLICIT_DEF:
857
1.81M
    case TargetOpcode::KILL:
858
1.81M
    case TargetOpcode::CFI_INSTRUCTION:
859
1.81M
    case TargetOpcode::EH_LABEL:
860
1.81M
    case TargetOpcode::GC_LABEL:
861
1.81M
    case TargetOpcode::DBG_VALUE:
862
1.81M
      return true;
863
58.4M
    }
864
58.4M
  }
865
866
  /// Return true if this is a transient instruction that is either very likely
867
  /// to be eliminated during register allocation (such as copy-like
868
  /// instructions), or if this instruction doesn't have an execution-time cost.
869
71.6M
  bool isTransient() const {
870
71.6M
    switch (getOpcode()) {
871
56.8M
    default:
872
56.8M
      return isMetaInstruction();
873
71.6M
    // Copy-like instructions are usually eliminated during register allocation.
874
14.7M
    case TargetOpcode::PHI:
875
14.7M
    case TargetOpcode::G_PHI:
876
14.7M
    case TargetOpcode::COPY:
877
14.7M
    case TargetOpcode::INSERT_SUBREG:
878
14.7M
    case TargetOpcode::SUBREG_TO_REG:
879
14.7M
    case TargetOpcode::REG_SEQUENCE:
880
14.7M
      return true;
881
71.6M
    }
882
71.6M
  }
883
884
  /// Return the number of instructions inside the MI bundle, excluding the
885
  /// bundle header.
886
  ///
887
  /// This is the number of instructions that MachineBasicBlock::iterator
888
  /// skips, 0 for unbundled instructions.
889
  unsigned getBundleSize() const;
890
891
  /// Return true if the MachineInstr reads the specified register.
892
  /// If TargetRegisterInfo is passed, then it also checks if there
893
  /// is a read of a super-register.
894
  /// This does not count partial redefines of virtual registers as reads:
895
  ///   %reg1024:6 = OP.
896
  bool readsRegister(unsigned Reg,
897
3.66M
                     const TargetRegisterInfo *TRI = nullptr) const {
898
3.66M
    return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
899
3.66M
  }
900
901
  /// Return true if the MachineInstr reads the specified virtual register.
902
  /// Take into account that a partial define is a
903
  /// read-modify-write operation.
904
3.57M
  bool readsVirtualRegister(unsigned Reg) const {
905
3.57M
    return readsWritesVirtualRegister(Reg).first;
906
3.57M
  }
907
908
  /// Return a pair of bools (reads, writes) indicating if this instruction
909
  /// reads or writes Reg. This also considers partial defines.
910
  /// If Ops is not null, all operand indices for Reg are added.
911
  std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
912
                                SmallVectorImpl<unsigned> *Ops = nullptr) const;
913
914
  /// Return true if the MachineInstr kills the specified register.
915
  /// If TargetRegisterInfo is passed, then it also checks if there is
916
  /// a kill of a super-register.
917
  bool killsRegister(unsigned Reg,
918
487k
                     const TargetRegisterInfo *TRI = nullptr) const {
919
487k
    return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
920
487k
  }
921
922
  /// Return true if the MachineInstr fully defines the specified register.
923
  /// If TargetRegisterInfo is passed, then it also checks
924
  /// if there is a def of a super-register.
925
  /// NOTE: It's ignoring subreg indices on virtual registers.
926
  bool definesRegister(unsigned Reg,
927
68.7M
                       const TargetRegisterInfo *TRI = nullptr) const {
928
68.7M
    return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
929
68.7M
  }
930
931
  /// Return true if the MachineInstr modifies (fully define or partially
932
  /// define) the specified register.
933
  /// NOTE: It's ignoring subreg indices on virtual registers.
934
31.4M
  bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
935
31.4M
    return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
936
31.4M
  }
937
938
  /// Returns true if the register is dead in this machine instruction.
939
  /// If TargetRegisterInfo is passed, then it also checks
940
  /// if there is a dead def of a super-register.
941
  bool registerDefIsDead(unsigned Reg,
942
1.11M
                         const TargetRegisterInfo *TRI = nullptr) const {
943
1.11M
    return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
944
1.11M
  }
945
946
  /// Returns true if the MachineInstr has an implicit-use operand of exactly
947
  /// the given register (not considering sub/super-registers).
948
  bool hasRegisterImplicitUseOperand(unsigned Reg) const;
949
950
  /// Returns the operand index that is a use of the specific register or -1
951
  /// if it is not found. It further tightens the search criteria to a use
952
  /// that kills the register if isKill is true.
953
  int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
954
                                const TargetRegisterInfo *TRI = nullptr) const;
955
956
  /// Wrapper for findRegisterUseOperandIdx, it returns
957
  /// a pointer to the MachineOperand rather than an index.
958
  MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
959
39.1k
                                      const TargetRegisterInfo *TRI = nullptr) {
960
39.1k
    int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
961
39.1k
    return (Idx == -1) ? 
nullptr18.3k
:
&getOperand(Idx)20.7k
;
962
39.1k
  }
963
964
  const MachineOperand *findRegisterUseOperand(
965
    unsigned Reg, bool isKill = false,
966
0
    const TargetRegisterInfo *TRI = nullptr) const {
967
0
    return const_cast<MachineInstr *>(this)->
968
0
      findRegisterUseOperand(Reg, isKill, TRI);
969
0
  }
970
971
  /// Returns the operand index that is a def of the specified register or
972
  /// -1 if it is not found. If isDead is true, defs that are not dead are
973
  /// skipped. If Overlap is true, then it also looks for defs that merely
974
  /// overlap the specified register. If TargetRegisterInfo is non-null,
975
  /// then it also checks if there is a def of a super-register.
976
  /// This may also return a register mask operand when Overlap is true.
977
  int findRegisterDefOperandIdx(unsigned Reg,
978
                                bool isDead = false, bool Overlap = false,
979
                                const TargetRegisterInfo *TRI = nullptr) const;
980
981
  /// Wrapper for findRegisterDefOperandIdx, it returns
982
  /// a pointer to the MachineOperand rather than an index.
983
  MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
984
11.4M
                                      const TargetRegisterInfo *TRI = nullptr) {
985
11.4M
    int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
986
11.4M
    return (Idx == -1) ? 
nullptr3.29M
:
&getOperand(Idx)8.15M
;
987
11.4M
  }
988
989
  /// Find the index of the first operand in the
990
  /// operand list that is used to represent the predicate. It returns -1 if
991
  /// none is found.
992
  int findFirstPredOperandIdx() const;
993
994
  /// Find the index of the flag word operand that
995
  /// corresponds to operand OpIdx on an inline asm instruction.  Returns -1 if
996
  /// getOperand(OpIdx) does not belong to an inline asm operand group.
997
  ///
998
  /// If GroupNo is not NULL, it will receive the number of the operand group
999
  /// containing OpIdx.
1000
  ///
1001
  /// The flag operand is an immediate that can be decoded with methods like
1002
  /// InlineAsm::hasRegClassConstraint().
1003
  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1004
1005
  /// Compute the static register class constraint for operand OpIdx.
1006
  /// For normal instructions, this is derived from the MCInstrDesc.
1007
  /// For inline assembly it is derived from the flag words.
1008
  ///
1009
  /// Returns NULL if the static register class constraint cannot be
1010
  /// determined.
1011
  const TargetRegisterClass*
1012
  getRegClassConstraint(unsigned OpIdx,
1013
                        const TargetInstrInfo *TII,
1014
                        const TargetRegisterInfo *TRI) const;
1015
1016
  /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
1017
  /// the given \p CurRC.
1018
  /// If \p ExploreBundle is set and MI is part of a bundle, all the
1019
  /// instructions inside the bundle will be taken into account. In other words,
1020
  /// this method accumulates all the constraints of the operand of this MI and
1021
  /// the related bundle if MI is a bundle or inside a bundle.
1022
  ///
1023
  /// Returns the register class that satisfies both \p CurRC and the
1024
  /// constraints set by MI. Returns NULL if such a register class does not
1025
  /// exist.
1026
  ///
1027
  /// \pre CurRC must not be NULL.
1028
  const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1029
      unsigned Reg, const TargetRegisterClass *CurRC,
1030
      const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1031
      bool ExploreBundle = false) const;
1032
1033
  /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
1034
  /// to the given \p CurRC.
1035
  ///
1036
  /// Returns the register class that satisfies both \p CurRC and the
1037
  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1038
  /// does not exist.
1039
  ///
1040
  /// \pre CurRC must not be NULL.
1041
  /// \pre The operand at \p OpIdx must be a register.
1042
  const TargetRegisterClass *
1043
  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1044
                              const TargetInstrInfo *TII,
1045
                              const TargetRegisterInfo *TRI) const;
1046
1047
  /// Add a tie between the register operands at DefIdx and UseIdx.
1048
  /// The tie will cause the register allocator to ensure that the two
1049
  /// operands are assigned the same physical register.
1050
  ///
1051
  /// Tied operands are managed automatically for explicit operands in the
1052
  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1053
  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1054
1055
  /// Given the index of a tied register operand, find the
1056
  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1057
  /// index of the tied operand which must exist.
1058
  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1059
1060
  /// Given the index of a register def operand,
1061
  /// check if the register def is tied to a source operand, due to either
1062
  /// two-address elimination or inline assembly constraints. Returns the
1063
  /// first tied use operand index by reference if UseOpIdx is not null.
1064
  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1065
1.13M
                             unsigned *UseOpIdx = nullptr) const {
1066
1.13M
    const MachineOperand &MO = getOperand(DefOpIdx);
1067
1.13M
    if (
!MO.isReg() || 1.13M
!MO.isDef()1.13M
||
!MO.isTied()1.12M
)
1068
1.10M
      return false;
1069
30.0k
    
if (30.0k
UseOpIdx30.0k
)
1070
24.3k
      *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1071
30.0k
    return true;
1072
1.13M
  }
1073
1074
  /// Return true if the use operand of the specified index is tied to a def
1075
  /// operand. It also returns the def operand index by reference if DefOpIdx
1076
  /// is not null.
1077
  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1078
177M
                             unsigned *DefOpIdx = nullptr) const {
1079
177M
    const MachineOperand &MO = getOperand(UseOpIdx);
1080
177M
    if (
!MO.isReg() || 177M
!MO.isUse()143M
||
!MO.isTied()107M
)
1081
176M
      return false;
1082
1.20M
    
if (1.20M
DefOpIdx1.20M
)
1083
1.20M
      *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1084
1.20M
    return true;
1085
177M
  }
1086
1087
  /// Clears kill flags on all operands.
1088
  void clearKillInfo();
1089
1090
  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1091
  /// properly composing subreg indices where necessary.
1092
  void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1093
                          const TargetRegisterInfo &RegInfo);
1094
1095
  /// We have determined MI kills a register. Look for the
1096
  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1097
  /// add a implicit operand if it's not found. Returns true if the operand
1098
  /// exists / is added.
1099
  bool addRegisterKilled(unsigned IncomingReg,
1100
                         const TargetRegisterInfo *RegInfo,
1101
                         bool AddIfNotFound = false);
1102
1103
  /// Clear all kill flags affecting Reg.  If RegInfo is provided, this includes
1104
  /// all aliasing registers.
1105
  void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1106
1107
  /// We have determined MI defined a register without a use.
1108
  /// Look for the operand that defines it and mark it as IsDead. If
1109
  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1110
  /// true if the operand exists / is added.
1111
  bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1112
                       bool AddIfNotFound = false);
1113
1114
  /// Clear all dead flags on operands defining register @p Reg.
1115
  void clearRegisterDeads(unsigned Reg);
1116
1117
  /// Mark all subregister defs of register @p Reg with the undef flag.
1118
  /// This function is used when we determined to have a subregister def in an
1119
  /// otherwise undefined super register.
1120
  void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
1121
1122
  /// We have determined MI defines a register. Make sure there is an operand
1123
  /// defining Reg.
1124
  void addRegisterDefined(unsigned Reg,
1125
                          const TargetRegisterInfo *RegInfo = nullptr);
1126
1127
  /// Mark every physreg used by this instruction as
1128
  /// dead except those in the UsedRegs list.
1129
  ///
1130
  /// On instructions with register mask operands, also add implicit-def
1131
  /// operands for all registers in UsedRegs.
1132
  void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1133
                             const TargetRegisterInfo &TRI);
1134
1135
  /// Return true if it is safe to move this instruction. If
1136
  /// SawStore is set to true, it means that there is a store (or call) between
1137
  /// the instruction's location and its intended destination.
1138
  bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1139
1140
  /// Returns true if this instruction's memory access aliases the memory
1141
  /// access of Other.
1142
  //
1143
  /// Assumes any physical registers used to compute addresses
1144
  /// have the same value for both instructions.  Returns false if neither
1145
  /// instruction writes to memory.
1146
  ///
1147
  /// @param AA Optional alias analysis, used to compare memory operands.
1148
  /// @param Other MachineInstr to check aliasing against.
1149
  /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1150
  bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA);
1151
1152
  /// Return true if this instruction may have an ordered
1153
  /// or volatile memory reference, or if the information describing the memory
1154
  /// reference is not available. Return false if it is known to have no
1155
  /// ordered or volatile memory references.
1156
  bool hasOrderedMemoryRef() const;
1157
1158
  /// Return true if this load instruction never traps and points to a memory
1159
  /// location whose value doesn't change during the execution of this function.
1160
  ///
1161
  /// Examples include loading a value from the constant pool or from the
1162
  /// argument area of a function (if it does not change).  If the instruction
1163
  /// does multiple loads, this returns true only if all of the loads are
1164
  /// dereferenceable and invariant.
1165
  bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const;
1166
1167
  /// If the specified instruction is a PHI that always merges together the
1168
  /// same virtual register, return the register, otherwise return 0.
1169
  unsigned isConstantValuePHI() const;
1170
1171
  /// Return true if this instruction has side effects that are not modeled
1172
  /// by mayLoad / mayStore, etc.
1173
  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1174
  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1175
  /// INLINEASM instruction, in which case the side effect property is encoded
1176
  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1177
  ///
1178
  bool hasUnmodeledSideEffects() const;
1179
1180
  /// Returns true if it is illegal to fold a load across this instruction.
1181
  bool isLoadFoldBarrier() const;
1182
1183
  /// Return true if all the defs of this instruction are dead.
1184
  bool allDefsAreDead() const;
1185
1186
  /// Copy implicit register operands from specified
1187
  /// instruction to this instruction.
1188
  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1189
1190
  /// Debugging support
1191
  /// @{
1192
  /// Print this MI to \p OS.
1193
  /// Only print the defs and the opcode if \p SkipOpers is true.
1194
  /// Otherwise, also print operands if \p SkipDebugLoc is true.
1195
  /// Otherwise, also print the debug loc, with a terminating newline.
1196
  /// \p TII is used to print the opcode name.  If it's not present, but the
1197
  /// MI is in a function, the opcode will be printed using the function's TII.
1198
  void print(raw_ostream &OS, bool SkipOpers = false, bool SkipDebugLoc = false,
1199
             const TargetInstrInfo *TII = nullptr) const;
1200
  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool SkipOpers = false,
1201
             bool SkipDebugLoc = false,
1202
             const TargetInstrInfo *TII = nullptr) const;
1203
  void dump() const;
1204
  /// @}
1205
1206
  //===--------------------------------------------------------------------===//
1207
  // Accessors used to build up machine instructions.
1208
1209
  /// Add the specified operand to the instruction.  If it is an implicit
1210
  /// operand, it is added to the end of the operand list.  If it is an
1211
  /// explicit operand it is added at the end of the explicit operand list
1212
  /// (before the first implicit operand).
1213
  ///
1214
  /// MF must be the machine function that was used to allocate this
1215
  /// instruction.
1216
  ///
1217
  /// MachineInstrBuilder provides a more convenient interface for creating
1218
  /// instructions and adding operands.
1219
  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1220
1221
  /// Add an operand without providing an MF reference. This only works for
1222
  /// instructions that are inserted in a basic block.
1223
  ///
1224
  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1225
  /// preferred.
1226
  void addOperand(const MachineOperand &Op);
1227
1228
  /// Replace the instruction descriptor (thus opcode) of
1229
  /// the current instruction with a new one.
1230
3.25M
  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1231
1232
  /// Replace current source information with new such.
1233
  /// Avoid using this, the constructor argument is preferable.
1234
1.76M
  void setDebugLoc(DebugLoc dl) {
1235
1.76M
    debugLoc = std::move(dl);
1236
1.76M
    assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1237
1.76M
  }
1238
1239
  /// Erase an operand from an instruction, leaving it with one
1240
  /// fewer operand than it started with.
1241
  void RemoveOperand(unsigned i);
1242
1243
  /// Add a MachineMemOperand to the machine instruction.
1244
  /// This function should be used only occasionally. The setMemRefs function
1245
  /// is the primary method for setting up a MachineInstr's MemRefs list.
1246
  void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1247
1248
  /// Assign this MachineInstr's memory reference descriptor list.
1249
  /// This does not transfer ownership.
1250
27.3M
  void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1251
27.3M
    setMemRefs(std::make_pair(NewMemRefs, NewMemRefsEnd-NewMemRefs));
1252
27.3M
  }
1253
1254
  /// Assign this MachineInstr's memory reference descriptor list.  First
1255
  /// element in the pair is the begin iterator/pointer to the array; the
1256
  /// second is the number of MemoryOperands.  This does not transfer ownership
1257
  /// of the underlying memory.
1258
28.5M
  void setMemRefs(std::pair<mmo_iterator, unsigned> NewMemRefs) {
1259
28.5M
    MemRefs = NewMemRefs.first;
1260
28.5M
    NumMemRefs = uint8_t(NewMemRefs.second);
1261
28.5M
    assert(NumMemRefs == NewMemRefs.second &&
1262
28.5M
           "Too many memrefs - must drop memory operands");
1263
28.5M
  }
1264
1265
  /// Return a set of memrefs (begin iterator, size) which conservatively
1266
  /// describe the memory behavior of both MachineInstrs.  This is appropriate
1267
  /// for use when merging two MachineInstrs into one. This routine does not
1268
  /// modify the memrefs of the this MachineInstr.
1269
  std::pair<mmo_iterator, unsigned> mergeMemRefsWith(const MachineInstr& Other);
1270
1271
  /// Clear this MachineInstr's memory reference descriptor list.  This resets
1272
  /// the memrefs to their most conservative state.  This should be used only
1273
  /// as a last resort since it greatly pessimizes our knowledge of the memory
1274
  /// access performed by the instruction.
1275
32
  void dropMemRefs() {
1276
32
    MemRefs = nullptr;
1277
32
    NumMemRefs = 0;
1278
32
  }
1279
1280
  /// Break any tie involving OpIdx.
1281
1.79M
  void untieRegOperand(unsigned OpIdx) {
1282
1.79M
    MachineOperand &MO = getOperand(OpIdx);
1283
1.79M
    if (
MO.isReg() && 1.79M
MO.isTied()1.57M
) {
1284
209k
      getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1285
209k
      MO.TiedTo = 0;
1286
209k
    }
1287
1.79M
  }
1288
1289
  /// Add all implicit def and use operands to this instruction.
1290
  void addImplicitDefUseOperands(MachineFunction &MF);
1291
1292
private:
1293
  /// If this instruction is embedded into a MachineFunction, return the
1294
  /// MachineRegisterInfo object for the current function, otherwise
1295
  /// return null.
1296
  MachineRegisterInfo *getRegInfo();
1297
1298
  /// Unlink all of the register operands in this instruction from their
1299
  /// respective use lists.  This requires that the operands already be on their
1300
  /// use lists.
1301
  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1302
1303
  /// Add all of the register operands in this instruction from their
1304
  /// respective use lists.  This requires that the operands not be on their
1305
  /// use lists yet.
1306
  void AddRegOperandsToUseLists(MachineRegisterInfo&);
1307
1308
  /// Slow path for hasProperty when we're dealing with a bundle.
1309
  bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1310
1311
  /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1312
  /// this MI and the given operand index \p OpIdx.
1313
  /// If the related operand does not constrained Reg, this returns CurRC.
1314
  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1315
      unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1316
      const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1317
};
1318
1319
/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1320
/// instruction rather than by pointer value.
1321
/// The hashing and equality testing functions ignore definitions so this is
1322
/// useful for CSE, etc.
1323
struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1324
261M
  static inline MachineInstr *getEmptyKey() {
1325
261M
    return nullptr;
1326
261M
  }
1327
1328
153M
  static inline MachineInstr *getTombstoneKey() {
1329
153M
    return reinterpret_cast<MachineInstr*>(-1);
1330
153M
  }
1331
1332
  static unsigned getHashValue(const MachineInstr* const &MI);
1333
1334
  static bool isEqual(const MachineInstr* const &LHS,
1335
202M
                      const MachineInstr* const &RHS) {
1336
202M
    if (
RHS == getEmptyKey() || 202M
RHS == getTombstoneKey()95.7M
||
1337
202M
        
LHS == getEmptyKey()21.1M
||
LHS == getTombstoneKey()21.1M
)
1338
181M
      return LHS == RHS;
1339
21.1M
    return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1340
202M
  }
1341
};
1342
1343
//===----------------------------------------------------------------------===//
1344
// Debugging Support
1345
1346
1
inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1347
1
  MI.print(OS);
1348
1
  return OS;
1349
1
}
1350
1351
} // end namespace llvm
1352
1353
#endif // LLVM_CODEGEN_MACHINEINSTR_H