/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/AMDGPU/R600MachineScheduler.h
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1 | | //===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | /// \file |
11 | | /// \brief R600 Machine Scheduler interface |
12 | | // |
13 | | //===----------------------------------------------------------------------===// |
14 | | |
15 | | #ifndef LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H |
16 | | #define LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H |
17 | | |
18 | | #include "llvm/CodeGen/MachineScheduler.h" |
19 | | #include <vector> |
20 | | |
21 | | using namespace llvm; |
22 | | |
23 | | namespace llvm { |
24 | | |
25 | | class R600InstrInfo; |
26 | | struct R600RegisterInfo; |
27 | | |
28 | | class R600SchedStrategy final : public MachineSchedStrategy { |
29 | | const ScheduleDAGMILive *DAG = nullptr; |
30 | | const R600InstrInfo *TII = nullptr; |
31 | | const R600RegisterInfo *TRI = nullptr; |
32 | | MachineRegisterInfo *MRI = nullptr; |
33 | | |
34 | | enum InstKind { |
35 | | IDAlu, |
36 | | IDFetch, |
37 | | IDOther, |
38 | | IDLast |
39 | | }; |
40 | | |
41 | | enum AluKind { |
42 | | AluAny, |
43 | | AluT_X, |
44 | | AluT_Y, |
45 | | AluT_Z, |
46 | | AluT_W, |
47 | | AluT_XYZW, |
48 | | AluPredX, |
49 | | AluTrans, |
50 | | AluDiscarded, // LLVM Instructions that are going to be eliminated |
51 | | AluLast |
52 | | }; |
53 | | |
54 | | std::vector<SUnit *> Available[IDLast], Pending[IDLast]; |
55 | | std::vector<SUnit *> AvailableAlus[AluLast]; |
56 | | std::vector<SUnit *> PhysicalRegCopy; |
57 | | |
58 | | InstKind CurInstKind; |
59 | | int CurEmitted; |
60 | | InstKind NextInstKind; |
61 | | |
62 | | unsigned AluInstCount; |
63 | | unsigned FetchInstCount; |
64 | | |
65 | | int InstKindLimit[IDLast]; |
66 | | |
67 | | int OccupedSlotsMask; |
68 | | |
69 | | public: |
70 | 2.05k | R600SchedStrategy() = default; |
71 | 2.05k | ~R600SchedStrategy() override = default; |
72 | | |
73 | | void initialize(ScheduleDAGMI *dag) override; |
74 | | SUnit *pickNode(bool &IsTopNode) override; |
75 | | void schedNode(SUnit *SU, bool IsTopNode) override; |
76 | | void releaseTopNode(SUnit *SU) override; |
77 | | void releaseBottomNode(SUnit *SU) override; |
78 | | |
79 | | private: |
80 | | std::vector<MachineInstr *> InstructionsGroupCandidate; |
81 | | bool VLIW5; |
82 | | |
83 | | int getInstKind(SUnit *SU); |
84 | | bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const; |
85 | | AluKind getAluKind(SUnit *SU) const; |
86 | | void LoadAlu(); |
87 | | unsigned AvailablesAluCount() const; |
88 | | SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu); |
89 | | void PrepareNextSlot(); |
90 | | SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU); |
91 | | |
92 | | void AssignSlot(MachineInstr *MI, unsigned Slot); |
93 | | SUnit* pickAlu(); |
94 | | SUnit* pickOther(int QID); |
95 | | void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst); |
96 | | }; |
97 | | |
98 | | } // end namespace llvm |
99 | | |
100 | | #endif // LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H |