Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
Line
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Source (jump to first uncovered line)
1
//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
7
//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the ARM target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
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#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
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20
#include "ARMMCTargetDesc.h"
21
#include "llvm/Support/ErrorHandling.h"
22
#include "Utils/ARMBaseInfo.h"
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24
namespace llvm {
25
26
namespace ARM_PROC {
27
  enum IMod {
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    IE = 2,
29
    ID = 3
30
  };
31
32
  enum IFlags {
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    F = 1,
34
    I = 2,
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    A = 4
36
  };
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38
69
  inline static const char *IFlagsToString(unsigned val) {
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69
    switch (val) {
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0
    
default: 0
llvm_unreachable0
("Unknown iflags operand");
41
32
    case F: return "f";
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21
    case I: return "i";
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16
    case A: return "a";
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69
    }
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69
  }
Unexecuted instantiation: ARMDisassembler.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMTargetStreamer.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMAsmBackend.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
ARMInstPrinter.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
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Count
Source
38
69
  inline static const char *IFlagsToString(unsigned val) {
39
69
    switch (val) {
40
0
    
default: 0
llvm_unreachable0
("Unknown iflags operand");
41
32
    case F: return "f";
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21
    case I: return "i";
43
16
    case A: return "a";
44
69
    }
45
69
  }
Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMComputeBlockSize.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int)
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47
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  inline static const char *IModToString(unsigned val) {
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50
    switch (val) {
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0
    
default: 0
llvm_unreachable0
("Unknown imod operand");
50
34
    case IE: return "ie";
51
16
    case ID: return "id";
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50
    }
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50
  }
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMDisassembler.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMTargetStreamer.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMAsmBackend.cpp:llvm::ARM_PROC::IModToString(unsigned int)
ARMInstPrinter.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Line
Count
Source
47
50
  inline static const char *IModToString(unsigned val) {
48
50
    switch (val) {
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0
    
default: 0
llvm_unreachable0
("Unknown imod operand");
50
34
    case IE: return "ie";
51
16
    case ID: return "id";
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50
    }
53
50
  }
Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMComputeBlockSize.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARM_PROC::IModToString(unsigned int)
54
}
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56
namespace ARM_MB {
57
  // The Memory Barrier Option constants map directly to the 4-bit encoding of
58
  // the option field for memory barrier operations.
59
  enum MemBOpt {
60
    RESERVED_0 = 0,
61
    OSHLD = 1,
62
    OSHST = 2,
63
    OSH   = 3,
64
    RESERVED_4 = 4,
65
    NSHLD = 5,
66
    NSHST = 6,
67
    NSH   = 7,
68
    RESERVED_8 = 8,
69
    ISHLD = 9,
70
    ISHST = 10,
71
    ISH   = 11,
72
    RESERVED_12 = 12,
73
    LD = 13,
74
    ST    = 14,
75
    SY    = 15
76
  };
77
78
644
  inline static const char *MemBOptToString(unsigned val, bool HasV8) {
79
644
    switch (val) {
80
0
    
default: 0
llvm_unreachable0
("Unknown memory operation");
81
114
    case SY:    return "sy";
82
21
    case ST:    return "st";
83
19
    
case LD: return HasV8 ? 19
"ld"7
:
"#0xd"12
;
84
12
    case RESERVED_12: return "#0xc";
85
243
    case ISH:   return "ish";
86
33
    case ISHST: return "ishst";
87
20
    
case ISHLD: return HasV8 ? 20
"ishld"7
:
"#0x9"13
;
88
14
    case RESERVED_8: return "#0x8";
89
34
    case NSH:   return "nsh";
90
29
    case NSHST: return "nshst";
91
18
    
case NSHLD: return HasV8 ? 18
"nshld"6
:
"#0x5"12
;
92
12
    case RESERVED_4: return "#0x4";
93
23
    case OSH:   return "osh";
94
22
    case OSHST: return "oshst";
95
18
    
case OSHLD: return HasV8 ? 18
"oshld"6
:
"#0x1"12
;
96
12
    case RESERVED_0: return "#0x0";
97
644
    }
98
644
  }
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMFastISel.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMComputeBlockSize.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
ARMInstPrinter.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Line
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Source
78
644
  inline static const char *MemBOptToString(unsigned val, bool HasV8) {
79
644
    switch (val) {
80
0
    
default: 0
llvm_unreachable0
("Unknown memory operation");
81
114
    case SY:    return "sy";
82
21
    case ST:    return "st";
83
19
    
case LD: return HasV8 ? 19
"ld"7
:
"#0xd"12
;
84
12
    case RESERVED_12: return "#0xc";
85
243
    case ISH:   return "ish";
86
33
    case ISHST: return "ishst";
87
20
    
case ISHLD: return HasV8 ? 20
"ishld"7
:
"#0x9"13
;
88
14
    case RESERVED_8: return "#0x8";
89
34
    case NSH:   return "nsh";
90
29
    case NSHST: return "nshst";
91
18
    
case NSHLD: return HasV8 ? 18
"nshld"6
:
"#0x5"12
;
92
12
    case RESERVED_4: return "#0x4";
93
23
    case OSH:   return "osh";
94
22
    case OSHST: return "oshst";
95
18
    
case OSHLD: return HasV8 ? 18
"oshld"6
:
"#0x1"12
;
96
12
    case RESERVED_0: return "#0x0";
97
644
    }
98
644
  }
Unexecuted instantiation: ARMAsmBackend.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMTargetStreamer.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMDisassembler.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool)
99
} // namespace ARM_MB
100
101
namespace ARM_ISB {
102
  enum InstSyncBOpt {
103
    RESERVED_0 = 0,
104
    RESERVED_1 = 1,
105
    RESERVED_2 = 2,
106
    RESERVED_3 = 3,
107
    RESERVED_4 = 4,
108
    RESERVED_5 = 5,
109
    RESERVED_6 = 6,
110
    RESERVED_7 = 7,
111
    RESERVED_8 = 8,
112
    RESERVED_9 = 9,
113
    RESERVED_10 = 10,
114
    RESERVED_11 = 11,
115
    RESERVED_12 = 12,
116
    RESERVED_13 = 13,
117
    RESERVED_14 = 14,
118
    SY = 15
119
  };
120
121
35
  inline static const char *InstSyncBOptToString(unsigned val) {
122
35
    switch (val) {
123
0
    default:
124
0
      llvm_unreachable("Unknown memory operation");
125
0
      case RESERVED_0:  return "#0x0";
126
4
      case RESERVED_1:  return "#0x1";
127
0
      case RESERVED_2:  return "#0x2";
128
0
      case RESERVED_3:  return "#0x3";
129
0
      case RESERVED_4:  return "#0x4";
130
0
      case RESERVED_5:  return "#0x5";
131
0
      case RESERVED_6:  return "#0x6";
132
0
      case RESERVED_7:  return "#0x7";
133
0
      case RESERVED_8:  return "#0x8";
134
0
      case RESERVED_9:  return "#0x9";
135
2
      case RESERVED_10: return "#0xa";
136
0
      case RESERVED_11: return "#0xb";
137
0
      case RESERVED_12: return "#0xc";
138
0
      case RESERVED_13: return "#0xd";
139
0
      case RESERVED_14: return "#0xe";
140
29
      case SY:          return "sy";
141
35
    }
142
35
  }
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMComputeBlockSize.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
ARMInstPrinter.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Line
Count
Source
121
35
  inline static const char *InstSyncBOptToString(unsigned val) {
122
35
    switch (val) {
123
0
    default:
124
0
      llvm_unreachable("Unknown memory operation");
125
0
      case RESERVED_0:  return "#0x0";
126
4
      case RESERVED_1:  return "#0x1";
127
0
      case RESERVED_2:  return "#0x2";
128
0
      case RESERVED_3:  return "#0x3";
129
0
      case RESERVED_4:  return "#0x4";
130
0
      case RESERVED_5:  return "#0x5";
131
0
      case RESERVED_6:  return "#0x6";
132
0
      case RESERVED_7:  return "#0x7";
133
0
      case RESERVED_8:  return "#0x8";
134
0
      case RESERVED_9:  return "#0x9";
135
2
      case RESERVED_10: return "#0xa";
136
0
      case RESERVED_11: return "#0xb";
137
0
      case RESERVED_12: return "#0xc";
138
0
      case RESERVED_13: return "#0xd";
139
0
      case RESERVED_14: return "#0xe";
140
29
      case SY:          return "sy";
141
35
    }
142
35
  }
Unexecuted instantiation: ARMAsmBackend.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMTargetStreamer.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMDisassembler.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int)
143
} // namespace ARM_ISB
144
145
/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
146
///
147
190k
static inline bool isARMLowRegister(unsigned Reg) {
148
190k
  using namespace ARM;
149
190k
  switch (Reg) {
150
166k
  
case R0: 166k
case R1: 166k
case R2: 166k
case R3:
151
166k
  
case R4: 166k
case R5: 166k
case R6: 166k
case R7:
152
166k
    return true;
153
23.6k
  default:
154
23.6k
    return false;
155
190k
  }
156
190k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMDisassembler.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isARMLowRegister(unsigned int)
ARMBaseInstrInfo.cpp:llvm::isARMLowRegister(unsigned int)
Line
Count
Source
147
643
static inline bool isARMLowRegister(unsigned Reg) {
148
643
  using namespace ARM;
149
643
  switch (Reg) {
150
567
  
case R0: 567
case R1: 567
case R2: 567
case R3:
151
567
  
case R4: 567
case R5: 567
case R6: 567
case R7:
152
567
    return true;
153
76
  default:
154
76
    return false;
155
643
  }
156
643
}
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isARMLowRegister(unsigned int)
ARMConstantIslandPass.cpp:llvm::isARMLowRegister(unsigned int)
Line
Count
Source
147
3.53k
static inline bool isARMLowRegister(unsigned Reg) {
148
3.53k
  using namespace ARM;
149
3.53k
  switch (Reg) {
150
3.52k
  
case R0: 3.52k
case R1: 3.52k
case R2: 3.52k
case R3:
151
3.52k
  
case R4: 3.52k
case R5: 3.52k
case R6: 3.52k
case R7:
152
3.52k
    return true;
153
9
  default:
154
9
    return false;
155
3.53k
  }
156
3.53k
}
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isARMLowRegister(unsigned int)
ARMFrameLowering.cpp:llvm::isARMLowRegister(unsigned int)
Line
Count
Source
147
3.11k
static inline bool isARMLowRegister(unsigned Reg) {
148
3.11k
  using namespace ARM;
149
3.11k
  switch (Reg) {
150
985
  
case R0: 985
case R1: 985
case R2: 985
case R3:
151
985
  
case R4: 985
case R5: 985
case R6: 985
case R7:
152
985
    return true;
153
2.12k
  default:
154
2.12k
    return false;
155
3.11k
  }
156
3.11k
}
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isARMLowRegister(unsigned int)
ARMLoadStoreOptimizer.cpp:llvm::isARMLowRegister(unsigned int)
Line
Count
Source
147
6
static inline bool isARMLowRegister(unsigned Reg) {
148
6
  using namespace ARM;
149
6
  switch (Reg) {
150
6
  
case R0: 6
case R1: 6
case R2: 6
case R3:
151
6
  
case R4: 6
case R5: 6
case R6: 6
case R7:
152
6
    return true;
153
0
  default:
154
0
    return false;
155
6
  }
156
6
}
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isARMLowRegister(unsigned int)
ThumbRegisterInfo.cpp:llvm::isARMLowRegister(unsigned int)
Line
Count
Source
147
543
static inline bool isARMLowRegister(unsigned Reg) {
148
543
  using namespace ARM;
149
543
  switch (Reg) {
150
389
  
case R0: 389
case R1: 389
case R2: 389
case R3:
151
389
  
case R4: 389
case R5: 389
case R6: 389
case R7:
152
389
    return true;
153
154
  default:
154
154
    return false;
155
543
  }
156
543
}
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isARMLowRegister(unsigned int)
Thumb2SizeReduction.cpp:llvm::isARMLowRegister(unsigned int)
Line
Count
Source
147
176k
static inline bool isARMLowRegister(unsigned Reg) {
148
176k
  using namespace ARM;
149
176k
  switch (Reg) {
150
156k
  
case R0: 156k
case R1: 156k
case R2: 156k
case R3:
151
156k
  
case R4: 156k
case R5: 156k
case R6: 156k
case R7:
152
156k
    return true;
153
20.0k
  default:
154
20.0k
    return false;
155
176k
  }
156
176k
}
Unexecuted instantiation: ARMComputeBlockSize.cpp:llvm::isARMLowRegister(unsigned int)
ARMAsmParser.cpp:llvm::isARMLowRegister(unsigned int)
Line
Count
Source
147
6.45k
static inline bool isARMLowRegister(unsigned Reg) {
148
6.45k
  using namespace ARM;
149
6.45k
  switch (Reg) {
150
5.15k
  
case R0: 5.15k
case R1: 5.15k
case R2: 5.15k
case R3:
151
5.15k
  
case R4: 5.15k
case R5: 5.15k
case R6: 5.15k
case R7:
152
5.15k
    return true;
153
1.29k
  default:
154
1.29k
    return false;
155
6.45k
  }
156
6.45k
}
Unexecuted instantiation: ARMInstPrinter.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMAsmBackend.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::isARMLowRegister(unsigned int)
Unexecuted instantiation: ARMTargetStreamer.cpp:llvm::isARMLowRegister(unsigned int)
157
158
/// ARMII - This namespace holds all of the target specific flags that
159
/// instruction info tracks.
160
///
161
namespace ARMII {
162
163
  /// ARM Index Modes
164
  enum IndexMode {
165
    IndexModeNone  = 0,
166
    IndexModePre   = 1,
167
    IndexModePost  = 2,
168
    IndexModeUpd   = 3
169
  };
170
171
  /// ARM Addressing Modes
172
  enum AddrMode {
173
    AddrModeNone    = 0,
174
    AddrMode1       = 1,
175
    AddrMode2       = 2,
176
    AddrMode3       = 3,
177
    AddrMode4       = 4,
178
    AddrMode5       = 5,
179
    AddrMode6       = 6,
180
    AddrModeT1_1    = 7,
181
    AddrModeT1_2    = 8,
182
    AddrModeT1_4    = 9,
183
    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
184
    AddrModeT2_i12  = 11,
185
    AddrModeT2_i8   = 12,
186
    AddrModeT2_so   = 13,
187
    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
188
    AddrModeT2_i8s4 = 15, // i8 * 4
189
    AddrMode_i12    = 16
190
  };
191
192
0
  inline static const char *AddrModeToString(AddrMode addrmode) {
193
0
    switch (addrmode) {
194
0
    case AddrModeNone:    return "AddrModeNone";
195
0
    case AddrMode1:       return "AddrMode1";
196
0
    case AddrMode2:       return "AddrMode2";
197
0
    case AddrMode3:       return "AddrMode3";
198
0
    case AddrMode4:       return "AddrMode4";
199
0
    case AddrMode5:       return "AddrMode5";
200
0
    case AddrMode6:       return "AddrMode6";
201
0
    case AddrModeT1_1:    return "AddrModeT1_1";
202
0
    case AddrModeT1_2:    return "AddrModeT1_2";
203
0
    case AddrModeT1_4:    return "AddrModeT1_4";
204
0
    case AddrModeT1_s:    return "AddrModeT1_s";
205
0
    case AddrModeT2_i12:  return "AddrModeT2_i12";
206
0
    case AddrModeT2_i8:   return "AddrModeT2_i8";
207
0
    case AddrModeT2_so:   return "AddrModeT2_so";
208
0
    case AddrModeT2_pc:   return "AddrModeT2_pc";
209
0
    case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
210
0
    case AddrMode_i12:    return "AddrMode_i12";
211
0
    }
212
0
  }
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMFastISel.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMComputeBlockSize.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMInstPrinter.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMAsmBackend.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMTargetStreamer.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMDisassembler.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode)
213
214
  /// Target Operand Flag enum.
215
  enum TOF {
216
    //===------------------------------------------------------------------===//
217
    // ARM Specific MachineOperand flags.
218
219
    MO_NO_FLAG = 0,
220
221
    /// MO_LO16 - On a symbol operand, this represents a relocation containing
222
    /// lower 16 bit of the address. Used only via movw instruction.
223
    MO_LO16 = 0x1,
224
225
    /// MO_HI16 - On a symbol operand, this represents a relocation containing
226
    /// higher 16 bit of the address. Used only via movt instruction.
227
    MO_HI16 = 0x2,
228
229
    /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
230
    /// just that part of the flag set.
231
    MO_OPTION_MASK = 0x0f,
232
233
    /// MO_SBREL - On a symbol operand, this represents a static base relative
234
    /// relocation. Used in movw and movt instructions.
235
    MO_SBREL = 0x10,
236
237
    /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
238
    /// to the symbol is for an import stub.  This is used for DLL import
239
    /// storage class indication on Windows.
240
    MO_DLLIMPORT = 0x20,
241
242
    /// MO_SECREL - On a symbol operand this indicates that the immediate is
243
    /// the offset from beginning of section.
244
    ///
245
    /// This is the TLS offset for the COFF/Windows TLS mechanism.
246
    MO_SECREL = 0x40,
247
248
    /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
249
    /// represents a symbol which, if indirect, will get special Darwin mangling
250
    /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
251
    /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
252
    /// example).
253
    MO_NONLAZY = 0x80,
254
255
    // It's undefined behaviour if an enum overflows the range between its
256
    // smallest and largest values, but since these are |ed together, it can
257
    // happen. Put a sentinel in (values of this enum are stored as "unsigned
258
    // char").
259
    MO_UNUSED_MAXIMUM = 0xff
260
  };
261
262
  enum {
263
    //===------------------------------------------------------------------===//
264
    // Instruction Flags.
265
266
    //===------------------------------------------------------------------===//
267
    // This four-bit field describes the addressing mode used.
268
    AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
269
270
    // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
271
    // and store ops only.  Generic "updating" flag is used for ld/st multiple.
272
    // The index mode enums are declared in ARMBaseInfo.h
273
    IndexModeShift = 5,
274
    IndexModeMask  = 3 << IndexModeShift,
275
276
    //===------------------------------------------------------------------===//
277
    // Instruction encoding formats.
278
    //
279
    FormShift     = 7,
280
    FormMask      = 0x3f << FormShift,
281
282
    // Pseudo instructions
283
    Pseudo        = 0  << FormShift,
284
285
    // Multiply instructions
286
    MulFrm        = 1  << FormShift,
287
288
    // Branch instructions
289
    BrFrm         = 2  << FormShift,
290
    BrMiscFrm     = 3  << FormShift,
291
292
    // Data Processing instructions
293
    DPFrm         = 4  << FormShift,
294
    DPSoRegFrm    = 5  << FormShift,
295
296
    // Load and Store
297
    LdFrm         = 6  << FormShift,
298
    StFrm         = 7  << FormShift,
299
    LdMiscFrm     = 8  << FormShift,
300
    StMiscFrm     = 9  << FormShift,
301
    LdStMulFrm    = 10 << FormShift,
302
303
    LdStExFrm     = 11 << FormShift,
304
305
    // Miscellaneous arithmetic instructions
306
    ArithMiscFrm  = 12 << FormShift,
307
    SatFrm        = 13 << FormShift,
308
309
    // Extend instructions
310
    ExtFrm        = 14 << FormShift,
311
312
    // VFP formats
313
    VFPUnaryFrm   = 15 << FormShift,
314
    VFPBinaryFrm  = 16 << FormShift,
315
    VFPConv1Frm   = 17 << FormShift,
316
    VFPConv2Frm   = 18 << FormShift,
317
    VFPConv3Frm   = 19 << FormShift,
318
    VFPConv4Frm   = 20 << FormShift,
319
    VFPConv5Frm   = 21 << FormShift,
320
    VFPLdStFrm    = 22 << FormShift,
321
    VFPLdStMulFrm = 23 << FormShift,
322
    VFPMiscFrm    = 24 << FormShift,
323
324
    // Thumb format
325
    ThumbFrm      = 25 << FormShift,
326
327
    // Miscelleaneous format
328
    MiscFrm       = 26 << FormShift,
329
330
    // NEON formats
331
    NGetLnFrm     = 27 << FormShift,
332
    NSetLnFrm     = 28 << FormShift,
333
    NDupFrm       = 29 << FormShift,
334
    NLdStFrm      = 30 << FormShift,
335
    N1RegModImmFrm= 31 << FormShift,
336
    N2RegFrm      = 32 << FormShift,
337
    NVCVTFrm      = 33 << FormShift,
338
    NVDupLnFrm    = 34 << FormShift,
339
    N2RegVShLFrm  = 35 << FormShift,
340
    N2RegVShRFrm  = 36 << FormShift,
341
    N3RegFrm      = 37 << FormShift,
342
    N3RegVShFrm   = 38 << FormShift,
343
    NVExtFrm      = 39 << FormShift,
344
    NVMulSLFrm    = 40 << FormShift,
345
    NVTBLFrm      = 41 << FormShift,
346
347
    //===------------------------------------------------------------------===//
348
    // Misc flags.
349
350
    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
351
    // it doesn't have a Rn operand.
352
    UnaryDP       = 1 << 13,
353
354
    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
355
    // a 16-bit Thumb instruction if certain conditions are met.
356
    Xform16Bit    = 1 << 14,
357
358
    // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
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    // instruction. Used by the parser to determine whether to require the 'S'
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    // suffix on the mnemonic (when not in an IT block) or preclude it (when
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    // in an IT block).
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    ThumbArithFlagSetting = 1 << 18,
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    //===------------------------------------------------------------------===//
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    // Code domain.
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    DomainShift   = 15,
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    DomainMask    = 7 << DomainShift,
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    DomainGeneral = 0 << DomainShift,
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    DomainVFP     = 1 << DomainShift,
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    DomainNEON    = 2 << DomainShift,
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    DomainNEONA8  = 4 << DomainShift,
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    //===------------------------------------------------------------------===//
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    // Field shifts - such shifts are used to set field while generating
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    // machine instructions.
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    //
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    // FIXME: This list will need adjusting/fixing as the MC code emitter
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    // takes shape and the ARMCodeEmitter.cpp bits go away.
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    ShiftTypeShift = 4,
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    M_BitShift     = 5,
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    ShiftImmShift  = 5,
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    ShiftShift     = 7,
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    N_BitShift     = 7,
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    ImmHiShift     = 8,
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    SoRotImmShift  = 8,
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    RegRsShift     = 8,
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    ExtRotImmShift = 10,
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    RegRdLoShift   = 12,
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    RegRdShift     = 12,
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    RegRdHiShift   = 16,
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    RegRnShift     = 16,
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    S_BitShift     = 20,
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    W_BitShift     = 21,
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    AM3_I_BitShift = 22,
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    D_BitShift     = 22,
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    U_BitShift     = 23,
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    P_BitShift     = 24,
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    I_BitShift     = 25,
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    CondShift      = 28
401
  };
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} // end namespace ARMII
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} // end namespace llvm;
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#endif