/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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1 | | //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file implements the ARMMCCodeEmitter class. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "MCTargetDesc/ARMAddressingModes.h" |
15 | | #include "MCTargetDesc/ARMBaseInfo.h" |
16 | | #include "MCTargetDesc/ARMFixupKinds.h" |
17 | | #include "MCTargetDesc/ARMMCExpr.h" |
18 | | #include "llvm/ADT/APFloat.h" |
19 | | #include "llvm/ADT/APInt.h" |
20 | | #include "llvm/ADT/SmallVector.h" |
21 | | #include "llvm/ADT/Statistic.h" |
22 | | #include "llvm/ADT/Triple.h" |
23 | | #include "llvm/MC/MCCodeEmitter.h" |
24 | | #include "llvm/MC/MCContext.h" |
25 | | #include "llvm/MC/MCExpr.h" |
26 | | #include "llvm/MC/MCFixup.h" |
27 | | #include "llvm/MC/MCInst.h" |
28 | | #include "llvm/MC/MCInstrDesc.h" |
29 | | #include "llvm/MC/MCInstrInfo.h" |
30 | | #include "llvm/MC/MCRegisterInfo.h" |
31 | | #include "llvm/MC/MCSubtargetInfo.h" |
32 | | #include "llvm/Support/Casting.h" |
33 | | #include "llvm/Support/Compiler.h" |
34 | | #include "llvm/Support/ErrorHandling.h" |
35 | | #include "llvm/Support/MathExtras.h" |
36 | | #include "llvm/Support/raw_ostream.h" |
37 | | #include <algorithm> |
38 | | #include <cassert> |
39 | | #include <cstdint> |
40 | | #include <cstdlib> |
41 | | |
42 | | using namespace llvm; |
43 | | |
44 | | #define DEBUG_TYPE "mccodeemitter" |
45 | | |
46 | | STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); |
47 | | STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); |
48 | | |
49 | | namespace { |
50 | | |
51 | | class ARMMCCodeEmitter : public MCCodeEmitter { |
52 | | const MCInstrInfo &MCII; |
53 | | const MCContext &CTX; |
54 | | bool IsLittleEndian; |
55 | | |
56 | | public: |
57 | | ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle) |
58 | 3.27k | : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) { |
59 | 3.27k | } |
60 | | ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete; |
61 | | ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete; |
62 | 3.27k | ~ARMMCCodeEmitter() override = default; |
63 | | |
64 | 333k | bool isThumb(const MCSubtargetInfo &STI) const { |
65 | 333k | return STI.getFeatureBits()[ARM::ModeThumb]; |
66 | 333k | } |
67 | | |
68 | 17.5k | bool isThumb2(const MCSubtargetInfo &STI) const { |
69 | 14.0k | return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; |
70 | 17.5k | } |
71 | | |
72 | 0 | bool isTargetMachO(const MCSubtargetInfo &STI) const { |
73 | 0 | const Triple &TT = STI.getTargetTriple(); |
74 | 0 | return TT.isOSBinFormatMachO(); |
75 | 0 | } |
76 | | |
77 | | unsigned getMachineSoImmOpValue(unsigned SoImm) const; |
78 | | |
79 | | // getBinaryCodeForInstr - TableGen'erated function for getting the |
80 | | // binary encoding for an instruction. |
81 | | uint64_t getBinaryCodeForInstr(const MCInst &MI, |
82 | | SmallVectorImpl<MCFixup> &Fixups, |
83 | | const MCSubtargetInfo &STI) const; |
84 | | |
85 | | /// getMachineOpValue - Return binary encoding of operand. If the machine |
86 | | /// operand requires relocation, record the relocation and return zero. |
87 | | unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, |
88 | | SmallVectorImpl<MCFixup> &Fixups, |
89 | | const MCSubtargetInfo &STI) const; |
90 | | |
91 | | /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of |
92 | | /// the specified operand. This is used for operands with :lower16: and |
93 | | /// :upper16: prefixes. |
94 | | uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, |
95 | | SmallVectorImpl<MCFixup> &Fixups, |
96 | | const MCSubtargetInfo &STI) const; |
97 | | |
98 | | bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, |
99 | | unsigned &Reg, unsigned &Imm, |
100 | | SmallVectorImpl<MCFixup> &Fixups, |
101 | | const MCSubtargetInfo &STI) const; |
102 | | |
103 | | /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate |
104 | | /// BL branch target. |
105 | | uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, |
106 | | SmallVectorImpl<MCFixup> &Fixups, |
107 | | const MCSubtargetInfo &STI) const; |
108 | | |
109 | | /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate |
110 | | /// BLX branch target. |
111 | | uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, |
112 | | SmallVectorImpl<MCFixup> &Fixups, |
113 | | const MCSubtargetInfo &STI) const; |
114 | | |
115 | | /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. |
116 | | uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, |
117 | | SmallVectorImpl<MCFixup> &Fixups, |
118 | | const MCSubtargetInfo &STI) const; |
119 | | |
120 | | /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. |
121 | | uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, |
122 | | SmallVectorImpl<MCFixup> &Fixups, |
123 | | const MCSubtargetInfo &STI) const; |
124 | | |
125 | | /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. |
126 | | uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, |
127 | | SmallVectorImpl<MCFixup> &Fixups, |
128 | | const MCSubtargetInfo &STI) const; |
129 | | |
130 | | /// getBranchTargetOpValue - Return encoding info for 24-bit immediate |
131 | | /// branch target. |
132 | | uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, |
133 | | SmallVectorImpl<MCFixup> &Fixups, |
134 | | const MCSubtargetInfo &STI) const; |
135 | | |
136 | | /// getThumbBranchTargetOpValue - Return encoding info for 24-bit |
137 | | /// immediate Thumb2 direct branch target. |
138 | | uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, |
139 | | SmallVectorImpl<MCFixup> &Fixups, |
140 | | const MCSubtargetInfo &STI) const; |
141 | | |
142 | | /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate |
143 | | /// branch target. |
144 | | uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, |
145 | | SmallVectorImpl<MCFixup> &Fixups, |
146 | | const MCSubtargetInfo &STI) const; |
147 | | uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, |
148 | | SmallVectorImpl<MCFixup> &Fixups, |
149 | | const MCSubtargetInfo &STI) const; |
150 | | uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, |
151 | | SmallVectorImpl<MCFixup> &Fixups, |
152 | | const MCSubtargetInfo &STI) const; |
153 | | |
154 | | /// getAdrLabelOpValue - Return encoding info for 12-bit immediate |
155 | | /// ADR label target. |
156 | | uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, |
157 | | SmallVectorImpl<MCFixup> &Fixups, |
158 | | const MCSubtargetInfo &STI) const; |
159 | | uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, |
160 | | SmallVectorImpl<MCFixup> &Fixups, |
161 | | const MCSubtargetInfo &STI) const; |
162 | | uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, |
163 | | SmallVectorImpl<MCFixup> &Fixups, |
164 | | const MCSubtargetInfo &STI) const; |
165 | | |
166 | | |
167 | | /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' |
168 | | /// operand. |
169 | | uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, |
170 | | SmallVectorImpl<MCFixup> &Fixups, |
171 | | const MCSubtargetInfo &STI) const; |
172 | | |
173 | | /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. |
174 | | uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, |
175 | | SmallVectorImpl<MCFixup> &Fixups, |
176 | | const MCSubtargetInfo &STI) const; |
177 | | |
178 | | /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' |
179 | | /// operand. |
180 | | uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, |
181 | | SmallVectorImpl<MCFixup> &Fixups, |
182 | | const MCSubtargetInfo &STI) const; |
183 | | |
184 | | /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' |
185 | | /// operand. |
186 | | uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, |
187 | | SmallVectorImpl<MCFixup> &Fixups, |
188 | | const MCSubtargetInfo &STI) const; |
189 | | |
190 | | /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2' |
191 | | /// operand. |
192 | | uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, |
193 | | SmallVectorImpl<MCFixup> &Fixups, |
194 | | const MCSubtargetInfo &STI) const; |
195 | | |
196 | | |
197 | | /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' |
198 | | /// operand as needed by load/store instructions. |
199 | | uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, |
200 | | SmallVectorImpl<MCFixup> &Fixups, |
201 | | const MCSubtargetInfo &STI) const; |
202 | | |
203 | | /// getLdStmModeOpValue - Return encoding for load/store multiple mode. |
204 | | uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, |
205 | | SmallVectorImpl<MCFixup> &Fixups, |
206 | 0 | const MCSubtargetInfo &STI) const { |
207 | 0 | ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); |
208 | 0 | switch (Mode) { |
209 | 0 | default: llvm_unreachable("Unknown addressing sub-mode!"); |
210 | 0 | case ARM_AM::da: return 0; |
211 | 0 | case ARM_AM::ia: return 1; |
212 | 0 | case ARM_AM::db: return 2; |
213 | 0 | case ARM_AM::ib: return 3; |
214 | 0 | } |
215 | 0 | } |
216 | | |
217 | | /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. |
218 | | /// |
219 | 114 | unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { |
220 | 114 | switch (ShOpc) { |
221 | 84 | case ARM_AM::no_shift: |
222 | 84 | case ARM_AM::lsl: return 0; |
223 | 13 | case ARM_AM::lsr: return 1; |
224 | 10 | case ARM_AM::asr: return 2; |
225 | 7 | case ARM_AM::ror: |
226 | 7 | case ARM_AM::rrx: return 3; |
227 | 0 | } |
228 | 0 | llvm_unreachable0 ("Invalid ShiftOpc!"); |
229 | 0 | } |
230 | | |
231 | | /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. |
232 | | uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, |
233 | | SmallVectorImpl<MCFixup> &Fixups, |
234 | | const MCSubtargetInfo &STI) const; |
235 | | |
236 | | /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. |
237 | | uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, |
238 | | SmallVectorImpl<MCFixup> &Fixups, |
239 | | const MCSubtargetInfo &STI) const; |
240 | | |
241 | | /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. |
242 | | uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, |
243 | | SmallVectorImpl<MCFixup> &Fixups, |
244 | | const MCSubtargetInfo &STI) const; |
245 | | |
246 | | /// getAddrMode3OpValue - Return encoding for addrmode3 operands. |
247 | | uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, |
248 | | SmallVectorImpl<MCFixup> &Fixups, |
249 | | const MCSubtargetInfo &STI) const; |
250 | | |
251 | | /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' |
252 | | /// operand. |
253 | | uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, |
254 | | SmallVectorImpl<MCFixup> &Fixups, |
255 | | const MCSubtargetInfo &STI) const; |
256 | | |
257 | | /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. |
258 | | uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, |
259 | | SmallVectorImpl<MCFixup> &Fixups, |
260 | | const MCSubtargetInfo &STI) const; |
261 | | |
262 | | /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. |
263 | | uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, |
264 | | SmallVectorImpl<MCFixup> &Fixups, |
265 | | const MCSubtargetInfo &STI) const; |
266 | | |
267 | | /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. |
268 | | uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, |
269 | | SmallVectorImpl<MCFixup> &Fixups, |
270 | | const MCSubtargetInfo &STI) const; |
271 | | |
272 | | /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. |
273 | | uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, |
274 | | SmallVectorImpl<MCFixup> &Fixups, |
275 | | const MCSubtargetInfo &STI) const; |
276 | | |
277 | | /// getCCOutOpValue - Return encoding of the 's' bit. |
278 | | unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, |
279 | | SmallVectorImpl<MCFixup> &Fixups, |
280 | 34.5k | const MCSubtargetInfo &STI) const { |
281 | 34.5k | // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or |
282 | 34.5k | // '1' respectively. |
283 | 34.5k | return MI.getOperand(Op).getReg() == ARM::CPSR; |
284 | 34.5k | } |
285 | | |
286 | | /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. |
287 | | unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, |
288 | | SmallVectorImpl<MCFixup> &Fixups, |
289 | 0 | const MCSubtargetInfo &STI) const { |
290 | 0 | const MCOperand &MO = MI.getOperand(Op); |
291 | 0 |
|
292 | 0 | // We expect MO to be an immediate or an expression, |
293 | 0 | // if it is an immediate - that's fine, just encode the value. |
294 | 0 | // Otherwise - create a Fixup. |
295 | 0 | if (MO.isExpr()) { |
296 | 0 | const MCExpr *Expr = MO.getExpr(); |
297 | 0 | // In instruction code this value always encoded as lowest 12 bits, |
298 | 0 | // so we don't have to perform any specific adjustments. |
299 | 0 | // Due to requirements of relocatable records we have to use FK_Data_4. |
300 | 0 | // See ARMELFObjectWriter::ExplicitRelSym and |
301 | 0 | // ARMELFObjectWriter::GetRelocTypeInner for more details. |
302 | 0 | MCFixupKind Kind = MCFixupKind(FK_Data_4); |
303 | 0 | Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); |
304 | 0 | return 0; |
305 | 0 | } |
306 | 0 |
|
307 | 0 | unsigned SoImm = MO.getImm(); |
308 | 0 | int SoImmVal = ARM_AM::getSOImmVal(SoImm); |
309 | 0 | assert(SoImmVal != -1 && "Not a valid so_imm value!"); |
310 | 0 |
|
311 | 0 | // Encode rotate_imm. |
312 | 0 | unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) |
313 | 0 | << ARMII::SoRotImmShift; |
314 | 0 |
|
315 | 0 | // Encode immed_8. |
316 | 0 | Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); |
317 | 0 | return Binary; |
318 | 0 | } |
319 | | |
320 | | unsigned getModImmOpValue(const MCInst &MI, unsigned Op, |
321 | | SmallVectorImpl<MCFixup> &Fixups, |
322 | 3.18k | const MCSubtargetInfo &ST) const { |
323 | 3.18k | const MCOperand &MO = MI.getOperand(Op); |
324 | 3.18k | |
325 | 3.18k | // Support for fixups (MCFixup) |
326 | 3.18k | if (MO.isExpr()3.18k ) { |
327 | 9 | const MCExpr *Expr = MO.getExpr(); |
328 | 9 | // Fixups resolve to plain values that need to be encoded. |
329 | 9 | MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm); |
330 | 9 | Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); |
331 | 9 | return 0; |
332 | 9 | } |
333 | 3.17k | |
334 | 3.17k | // Immediate is already in its encoded format |
335 | 3.17k | return MO.getImm(); |
336 | 3.17k | } |
337 | | |
338 | | /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. |
339 | | unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, |
340 | | SmallVectorImpl<MCFixup> &Fixups, |
341 | 18.4k | const MCSubtargetInfo &STI) const { |
342 | 18.4k | const MCOperand &MO = MI.getOperand(Op); |
343 | 18.4k | |
344 | 18.4k | // Support for fixups (MCFixup) |
345 | 18.4k | if (MO.isExpr()18.4k ) { |
346 | 14 | const MCExpr *Expr = MO.getExpr(); |
347 | 14 | // Fixups resolve to plain values that need to be encoded. |
348 | 14 | MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm); |
349 | 14 | Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); |
350 | 14 | return 0; |
351 | 14 | } |
352 | 18.4k | unsigned SoImm = MO.getImm(); |
353 | 18.4k | unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); |
354 | 18.4k | assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); |
355 | 18.4k | return Encoded; |
356 | 18.4k | } |
357 | | |
358 | | unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, |
359 | | SmallVectorImpl<MCFixup> &Fixups, |
360 | | const MCSubtargetInfo &STI) const; |
361 | | unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, |
362 | | SmallVectorImpl<MCFixup> &Fixups, |
363 | | const MCSubtargetInfo &STI) const; |
364 | | unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, |
365 | | SmallVectorImpl<MCFixup> &Fixups, |
366 | | const MCSubtargetInfo &STI) const; |
367 | | |
368 | | /// getSORegOpValue - Return an encoded so_reg shifted register value. |
369 | | unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, |
370 | | SmallVectorImpl<MCFixup> &Fixups, |
371 | | const MCSubtargetInfo &STI) const; |
372 | | unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, |
373 | | SmallVectorImpl<MCFixup> &Fixups, |
374 | | const MCSubtargetInfo &STI) const; |
375 | | unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, |
376 | | SmallVectorImpl<MCFixup> &Fixups, |
377 | | const MCSubtargetInfo &STI) const; |
378 | | |
379 | | unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, |
380 | | SmallVectorImpl<MCFixup> &Fixups, |
381 | 56 | const MCSubtargetInfo &STI) const { |
382 | 56 | return 64 - MI.getOperand(Op).getImm(); |
383 | 56 | } |
384 | | |
385 | | unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, |
386 | | SmallVectorImpl<MCFixup> &Fixups, |
387 | | const MCSubtargetInfo &STI) const; |
388 | | |
389 | | unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, |
390 | | SmallVectorImpl<MCFixup> &Fixups, |
391 | | const MCSubtargetInfo &STI) const; |
392 | | unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, |
393 | | SmallVectorImpl<MCFixup> &Fixups, |
394 | | const MCSubtargetInfo &STI) const; |
395 | | unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, |
396 | | SmallVectorImpl<MCFixup> &Fixups, |
397 | | const MCSubtargetInfo &STI) const; |
398 | | unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, |
399 | | SmallVectorImpl<MCFixup> &Fixups, |
400 | | const MCSubtargetInfo &STI) const; |
401 | | unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, |
402 | | SmallVectorImpl<MCFixup> &Fixups, |
403 | | const MCSubtargetInfo &STI) const; |
404 | | |
405 | | unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, |
406 | | SmallVectorImpl<MCFixup> &Fixups, |
407 | | const MCSubtargetInfo &STI) const; |
408 | | unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, |
409 | | SmallVectorImpl<MCFixup> &Fixups, |
410 | | const MCSubtargetInfo &STI) const; |
411 | | unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, |
412 | | SmallVectorImpl<MCFixup> &Fixups, |
413 | | const MCSubtargetInfo &STI) const; |
414 | | unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, |
415 | | SmallVectorImpl<MCFixup> &Fixups, |
416 | | const MCSubtargetInfo &STI) const; |
417 | | |
418 | | unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, |
419 | | SmallVectorImpl<MCFixup> &Fixups, |
420 | | const MCSubtargetInfo &STI) const; |
421 | | |
422 | | unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, |
423 | | unsigned EncodedValue, |
424 | | const MCSubtargetInfo &STI) const; |
425 | | unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, |
426 | | unsigned EncodedValue, |
427 | | const MCSubtargetInfo &STI) const; |
428 | | unsigned NEONThumb2DupPostEncoder(const MCInst &MI, |
429 | | unsigned EncodedValue, |
430 | | const MCSubtargetInfo &STI) const; |
431 | | unsigned NEONThumb2V8PostEncoder(const MCInst &MI, |
432 | | unsigned EncodedValue, |
433 | | const MCSubtargetInfo &STI) const; |
434 | | |
435 | | unsigned VFPThumb2PostEncoder(const MCInst &MI, |
436 | | unsigned EncodedValue, |
437 | | const MCSubtargetInfo &STI) const; |
438 | | |
439 | 862k | void EmitByte(unsigned char C, raw_ostream &OS) const { |
440 | 862k | OS << (char)C; |
441 | 862k | } |
442 | | |
443 | 414k | void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { |
444 | 414k | // Output the constant in little endian byte order. |
445 | 1.27M | for (unsigned i = 0; i != Size1.27M ; ++i862k ) { |
446 | 862k | unsigned Shift = IsLittleEndian ? i * 8851k : (Size - 1 - i) * 810.6k ; |
447 | 862k | EmitByte((Val >> Shift) & 0xff, OS); |
448 | 862k | } |
449 | 414k | } |
450 | | |
451 | | void encodeInstruction(const MCInst &MI, raw_ostream &OS, |
452 | | SmallVectorImpl<MCFixup> &Fixups, |
453 | | const MCSubtargetInfo &STI) const override; |
454 | | }; |
455 | | |
456 | | } // end anonymous namespace |
457 | | |
458 | | /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing |
459 | | /// instructions, and rewrite them to their Thumb2 form if we are currently in |
460 | | /// Thumb2 mode. |
461 | | unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, |
462 | | unsigned EncodedValue, |
463 | 4.05k | const MCSubtargetInfo &STI) const { |
464 | 4.05k | if (isThumb2(STI)4.05k ) { |
465 | 2.45k | // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved |
466 | 2.45k | // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are |
467 | 2.45k | // set to 1111. |
468 | 2.45k | unsigned Bit24 = EncodedValue & 0x01000000; |
469 | 2.45k | unsigned Bit28 = Bit24 << 4; |
470 | 2.45k | EncodedValue &= 0xEFFFFFFF; |
471 | 2.45k | EncodedValue |= Bit28; |
472 | 2.45k | EncodedValue |= 0x0F000000; |
473 | 2.45k | } |
474 | 4.05k | |
475 | 4.05k | return EncodedValue; |
476 | 4.05k | } |
477 | | |
478 | | /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store |
479 | | /// instructions, and rewrite them to their Thumb2 form if we are currently in |
480 | | /// Thumb2 mode. |
481 | | unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, |
482 | | unsigned EncodedValue, |
483 | 2.49k | const MCSubtargetInfo &STI) const { |
484 | 2.49k | if (isThumb2(STI)2.49k ) { |
485 | 2.07k | EncodedValue &= 0xF0FFFFFF; |
486 | 2.07k | EncodedValue |= 0x09000000; |
487 | 2.07k | } |
488 | 2.49k | |
489 | 2.49k | return EncodedValue; |
490 | 2.49k | } |
491 | | |
492 | | /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup |
493 | | /// instructions, and rewrite them to their Thumb2 form if we are currently in |
494 | | /// Thumb2 mode. |
495 | | unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, |
496 | | unsigned EncodedValue, |
497 | 105 | const MCSubtargetInfo &STI) const { |
498 | 105 | if (isThumb2(STI)105 ) { |
499 | 76 | EncodedValue &= 0x00FFFFFF; |
500 | 76 | EncodedValue |= 0xEE000000; |
501 | 76 | } |
502 | 105 | |
503 | 105 | return EncodedValue; |
504 | 105 | } |
505 | | |
506 | | /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form |
507 | | /// if we are in Thumb2. |
508 | | unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI, |
509 | | unsigned EncodedValue, |
510 | 202 | const MCSubtargetInfo &STI) const { |
511 | 202 | if (isThumb2(STI)202 ) { |
512 | 101 | EncodedValue |= 0xC000000; // Set bits 27-26 |
513 | 101 | } |
514 | 202 | |
515 | 202 | return EncodedValue; |
516 | 202 | } |
517 | | |
518 | | /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite |
519 | | /// them to their Thumb2 form if we are currently in Thumb2 mode. |
520 | | unsigned ARMMCCodeEmitter:: |
521 | | VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue, |
522 | 7.98k | const MCSubtargetInfo &STI) const { |
523 | 7.98k | if (isThumb2(STI)7.98k ) { |
524 | 6.74k | EncodedValue &= 0x0FFFFFFF; |
525 | 6.74k | EncodedValue |= 0xE0000000; |
526 | 6.74k | } |
527 | 7.98k | return EncodedValue; |
528 | 7.98k | } |
529 | | |
530 | | /// getMachineOpValue - Return binary encoding of operand. If the machine |
531 | | /// operand requires relocation, record the relocation and return zero. |
532 | | unsigned ARMMCCodeEmitter:: |
533 | | getMachineOpValue(const MCInst &MI, const MCOperand &MO, |
534 | | SmallVectorImpl<MCFixup> &Fixups, |
535 | 478k | const MCSubtargetInfo &STI) const { |
536 | 478k | if (MO.isReg()478k ) { |
537 | 365k | unsigned Reg = MO.getReg(); |
538 | 365k | unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); |
539 | 365k | |
540 | 365k | // Q registers are encoded as 2x their register number. |
541 | 365k | switch (Reg) { |
542 | 360k | default: |
543 | 360k | return RegNo; |
544 | 4.91k | case ARM::Q0: 4.91k case ARM::Q1: 4.91k case ARM::Q2: 4.91k case ARM::Q3: |
545 | 4.91k | case ARM::Q4: 4.91k case ARM::Q5: 4.91k case ARM::Q6: 4.91k case ARM::Q7: |
546 | 4.91k | case ARM::Q8: 4.91k case ARM::Q9: 4.91k case ARM::Q10: 4.91k case ARM::Q11: |
547 | 4.91k | case ARM::Q12: 4.91k case ARM::Q13: 4.91k case ARM::Q14: 4.91k case ARM::Q15: |
548 | 4.91k | return 2 * RegNo; |
549 | 478k | } |
550 | 113k | } else if (113k MO.isImm()113k ) { |
551 | 113k | return static_cast<unsigned>(MO.getImm()); |
552 | 0 | } else if (0 MO.isFPImm()0 ) { |
553 | 0 | return static_cast<unsigned>(APFloat(MO.getFPImm()) |
554 | 0 | .bitcastToAPInt().getHiBits(32).getLimitedValue()); |
555 | 0 | } |
556 | 0 |
|
557 | 0 | llvm_unreachable0 ("Unable to encode MCOperand!"); |
558 | 0 | } |
559 | | |
560 | | /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. |
561 | | bool ARMMCCodeEmitter:: |
562 | | EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, |
563 | | unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, |
564 | 14.4k | const MCSubtargetInfo &STI) const { |
565 | 14.4k | const MCOperand &MO = MI.getOperand(OpIdx); |
566 | 14.4k | const MCOperand &MO1 = MI.getOperand(OpIdx + 1); |
567 | 14.4k | |
568 | 14.4k | Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); |
569 | 14.4k | |
570 | 14.4k | int32_t SImm = MO1.getImm(); |
571 | 14.4k | bool isAdd = true; |
572 | 14.4k | |
573 | 14.4k | // Special value for #-0 |
574 | 14.4k | if (SImm == INT32_MIN14.4k ) { |
575 | 42 | SImm = 0; |
576 | 42 | isAdd = false; |
577 | 42 | } |
578 | 14.4k | |
579 | 14.4k | // Immediate is always encoded as positive. The 'U' bit controls add vs sub. |
580 | 14.4k | if (SImm < 014.4k ) { |
581 | 69 | SImm = -SImm; |
582 | 69 | isAdd = false; |
583 | 69 | } |
584 | 14.4k | |
585 | 14.4k | Imm = SImm; |
586 | 14.4k | return isAdd; |
587 | 14.4k | } |
588 | | |
589 | | /// getBranchTargetOpValue - Helper function to get the branch target operand, |
590 | | /// which is either an immediate or requires a fixup. |
591 | | static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, |
592 | | unsigned FixupKind, |
593 | | SmallVectorImpl<MCFixup> &Fixups, |
594 | 44.0k | const MCSubtargetInfo &STI) { |
595 | 44.0k | const MCOperand &MO = MI.getOperand(OpIdx); |
596 | 44.0k | |
597 | 44.0k | // If the destination is an immediate, we have nothing to do. |
598 | 44.0k | if (MO.isImm()44.0k ) return MO.getImm()36 ; |
599 | 44.0k | assert(MO.isExpr() && "Unexpected branch target type!"); |
600 | 43.9k | const MCExpr *Expr = MO.getExpr(); |
601 | 43.9k | MCFixupKind Kind = MCFixupKind(FixupKind); |
602 | 43.9k | Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); |
603 | 43.9k | |
604 | 43.9k | // All of the information is in the fixup. |
605 | 43.9k | return 0; |
606 | 43.9k | } |
607 | | |
608 | | // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are |
609 | | // determined by negating them and XOR'ing them with bit 23. |
610 | 12 | static int32_t encodeThumbBLOffset(int32_t offset) { |
611 | 12 | offset >>= 1; |
612 | 12 | uint32_t S = (offset & 0x800000) >> 23; |
613 | 12 | uint32_t J1 = (offset & 0x400000) >> 22; |
614 | 12 | uint32_t J2 = (offset & 0x200000) >> 21; |
615 | 12 | J1 = (~J1 & 0x1); |
616 | 12 | J2 = (~J2 & 0x1); |
617 | 12 | J1 ^= S; |
618 | 12 | J2 ^= S; |
619 | 12 | |
620 | 12 | offset &= ~0x600000; |
621 | 12 | offset |= J1 << 22; |
622 | 12 | offset |= J2 << 21; |
623 | 12 | |
624 | 12 | return offset; |
625 | 12 | } |
626 | | |
627 | | /// getThumbBLTargetOpValue - Return encoding info for immediate branch target. |
628 | | uint32_t ARMMCCodeEmitter:: |
629 | | getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, |
630 | | SmallVectorImpl<MCFixup> &Fixups, |
631 | 14.0k | const MCSubtargetInfo &STI) const { |
632 | 14.0k | const MCOperand MO = MI.getOperand(OpIdx); |
633 | 14.0k | if (MO.isExpr()) |
634 | 14.0k | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, |
635 | 14.0k | Fixups, STI); |
636 | 3 | return encodeThumbBLOffset(MO.getImm()); |
637 | 3 | } |
638 | | |
639 | | /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate |
640 | | /// BLX branch target. |
641 | | uint32_t ARMMCCodeEmitter:: |
642 | | getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, |
643 | | SmallVectorImpl<MCFixup> &Fixups, |
644 | 31 | const MCSubtargetInfo &STI) const { |
645 | 31 | const MCOperand MO = MI.getOperand(OpIdx); |
646 | 31 | if (MO.isExpr()) |
647 | 22 | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, |
648 | 22 | Fixups, STI); |
649 | 9 | return encodeThumbBLOffset(MO.getImm()); |
650 | 9 | } |
651 | | |
652 | | /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. |
653 | | uint32_t ARMMCCodeEmitter:: |
654 | | getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, |
655 | | SmallVectorImpl<MCFixup> &Fixups, |
656 | 5.25k | const MCSubtargetInfo &STI) const { |
657 | 5.25k | const MCOperand MO = MI.getOperand(OpIdx); |
658 | 5.25k | if (MO.isExpr()) |
659 | 5.21k | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, |
660 | 5.21k | Fixups, STI); |
661 | 40 | return (MO.getImm() >> 1); |
662 | 40 | } |
663 | | |
664 | | /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. |
665 | | uint32_t ARMMCCodeEmitter:: |
666 | | getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, |
667 | | SmallVectorImpl<MCFixup> &Fixups, |
668 | 15.1k | const MCSubtargetInfo &STI) const { |
669 | 15.1k | const MCOperand MO = MI.getOperand(OpIdx); |
670 | 15.1k | if (MO.isExpr()) |
671 | 15.1k | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, |
672 | 15.1k | Fixups, STI); |
673 | 32 | return (MO.getImm() >> 1); |
674 | 32 | } |
675 | | |
676 | | /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. |
677 | | uint32_t ARMMCCodeEmitter:: |
678 | | getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, |
679 | | SmallVectorImpl<MCFixup> &Fixups, |
680 | 3.11k | const MCSubtargetInfo &STI) const { |
681 | 3.11k | const MCOperand MO = MI.getOperand(OpIdx); |
682 | 3.11k | if (MO.isExpr()) |
683 | 3.10k | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI); |
684 | 6 | return (MO.getImm() >> 1); |
685 | 6 | } |
686 | | |
687 | | /// Return true if this branch has a non-always predication |
688 | 1.07k | static bool HasConditionalBranch(const MCInst &MI) { |
689 | 1.07k | int NumOp = MI.getNumOperands(); |
690 | 1.07k | if (NumOp >= 21.07k ) { |
691 | 970 | for (int i = 0; i < NumOp-1970 ; ++i604 ) { |
692 | 731 | const MCOperand &MCOp1 = MI.getOperand(i); |
693 | 731 | const MCOperand &MCOp2 = MI.getOperand(i + 1); |
694 | 731 | if (MCOp1.isImm() && 731 MCOp2.isReg()365 && |
695 | 731 | (MCOp2.getReg() == 0 || 365 MCOp2.getReg() == ARM::CPSR127 )) { |
696 | 365 | if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) |
697 | 127 | return true; |
698 | 365 | } |
699 | 731 | } |
700 | 366 | } |
701 | 948 | return false; |
702 | 1.07k | } |
703 | | |
704 | | /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch |
705 | | /// target. |
706 | | uint32_t ARMMCCodeEmitter:: |
707 | | getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, |
708 | | SmallVectorImpl<MCFixup> &Fixups, |
709 | 2.21k | const MCSubtargetInfo &STI) const { |
710 | 2.21k | // FIXME: This really, really shouldn't use TargetMachine. We don't want |
711 | 2.21k | // coupling between MC and TM anywhere we can help it. |
712 | 2.21k | if (isThumb2(STI)) |
713 | 2.21k | return |
714 | 2.21k | ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI); |
715 | 0 | return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI); |
716 | 0 | } |
717 | | |
718 | | /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch |
719 | | /// target. |
720 | | uint32_t ARMMCCodeEmitter:: |
721 | | getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, |
722 | | SmallVectorImpl<MCFixup> &Fixups, |
723 | 256 | const MCSubtargetInfo &STI) const { |
724 | 256 | const MCOperand MO = MI.getOperand(OpIdx); |
725 | 256 | if (MO.isExpr()256 ) { |
726 | 254 | if (HasConditionalBranch(MI)) |
727 | 123 | return ::getBranchTargetOpValue(MI, OpIdx, |
728 | 123 | ARM::fixup_arm_condbranch, Fixups, STI); |
729 | 131 | return ::getBranchTargetOpValue(MI, OpIdx, |
730 | 131 | ARM::fixup_arm_uncondbranch, Fixups, STI); |
731 | 131 | } |
732 | 2 | |
733 | 2 | return MO.getImm() >> 2; |
734 | 2 | } |
735 | | |
736 | | uint32_t ARMMCCodeEmitter:: |
737 | | getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, |
738 | | SmallVectorImpl<MCFixup> &Fixups, |
739 | 824 | const MCSubtargetInfo &STI) const { |
740 | 824 | const MCOperand MO = MI.getOperand(OpIdx); |
741 | 824 | if (MO.isExpr()824 ) { |
742 | 821 | if (HasConditionalBranch(MI)) |
743 | 4 | return ::getBranchTargetOpValue(MI, OpIdx, |
744 | 4 | ARM::fixup_arm_condbl, Fixups, STI); |
745 | 817 | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI); |
746 | 817 | } |
747 | 3 | |
748 | 3 | return MO.getImm() >> 2; |
749 | 3 | } |
750 | | |
751 | | uint32_t ARMMCCodeEmitter:: |
752 | | getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, |
753 | | SmallVectorImpl<MCFixup> &Fixups, |
754 | 19 | const MCSubtargetInfo &STI) const { |
755 | 19 | const MCOperand MO = MI.getOperand(OpIdx); |
756 | 19 | if (MO.isExpr()) |
757 | 14 | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI); |
758 | 5 | |
759 | 5 | return MO.getImm() >> 1; |
760 | 5 | } |
761 | | |
762 | | /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit |
763 | | /// immediate branch target. |
764 | | uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue( |
765 | | const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, |
766 | 883 | const MCSubtargetInfo &STI) const { |
767 | 883 | unsigned Val = 0; |
768 | 883 | const MCOperand MO = MI.getOperand(OpIdx); |
769 | 883 | |
770 | 883 | if(MO.isExpr()) |
771 | 832 | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI); |
772 | 883 | else |
773 | 51 | Val = MO.getImm() >> 1; |
774 | 883 | |
775 | 51 | bool I = (Val & 0x800000); |
776 | 51 | bool J1 = (Val & 0x400000); |
777 | 51 | bool J2 = (Val & 0x200000); |
778 | 51 | if (I ^ J1) |
779 | 0 | Val &= ~0x400000; |
780 | 51 | else |
781 | 51 | Val |= 0x400000; |
782 | 51 | |
783 | 51 | if (I ^ J2) |
784 | 0 | Val &= ~0x200000; |
785 | 51 | else |
786 | 51 | Val |= 0x200000; |
787 | 51 | |
788 | 51 | return Val; |
789 | 883 | } |
790 | | |
791 | | /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate |
792 | | /// ADR label target. |
793 | | uint32_t ARMMCCodeEmitter:: |
794 | | getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, |
795 | | SmallVectorImpl<MCFixup> &Fixups, |
796 | 30 | const MCSubtargetInfo &STI) const { |
797 | 30 | const MCOperand MO = MI.getOperand(OpIdx); |
798 | 30 | if (MO.isExpr()) |
799 | 13 | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, |
800 | 13 | Fixups, STI); |
801 | 17 | int64_t offset = MO.getImm(); |
802 | 17 | uint32_t Val = 0x2000; |
803 | 17 | |
804 | 17 | int SoImmVal; |
805 | 17 | if (offset == INT32_MIN17 ) { |
806 | 2 | Val = 0x1000; |
807 | 2 | SoImmVal = 0; |
808 | 17 | } else if (15 offset < 015 ) { |
809 | 6 | Val = 0x1000; |
810 | 6 | offset *= -1; |
811 | 6 | SoImmVal = ARM_AM::getSOImmVal(offset); |
812 | 6 | if(SoImmVal == -16 ) { |
813 | 2 | Val = 0x2000; |
814 | 2 | offset *= -1; |
815 | 2 | SoImmVal = ARM_AM::getSOImmVal(offset); |
816 | 2 | } |
817 | 15 | } else { |
818 | 9 | SoImmVal = ARM_AM::getSOImmVal(offset); |
819 | 9 | if(SoImmVal == -19 ) { |
820 | 2 | Val = 0x1000; |
821 | 2 | offset *= -1; |
822 | 2 | SoImmVal = ARM_AM::getSOImmVal(offset); |
823 | 2 | } |
824 | 15 | } |
825 | 30 | |
826 | 30 | assert(SoImmVal != -1 && "Not a valid so_imm value!"); |
827 | 30 | |
828 | 30 | Val |= SoImmVal; |
829 | 30 | return Val; |
830 | 30 | } |
831 | | |
832 | | /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label |
833 | | /// target. |
834 | | uint32_t ARMMCCodeEmitter:: |
835 | | getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, |
836 | | SmallVectorImpl<MCFixup> &Fixups, |
837 | 27 | const MCSubtargetInfo &STI) const { |
838 | 27 | const MCOperand MO = MI.getOperand(OpIdx); |
839 | 27 | if (MO.isExpr()) |
840 | 19 | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, |
841 | 19 | Fixups, STI); |
842 | 8 | int32_t Val = MO.getImm(); |
843 | 8 | if (Val == INT32_MIN) |
844 | 2 | Val = 0x1000; |
845 | 6 | else if (6 Val < 06 ) { |
846 | 3 | Val *= -1; |
847 | 3 | Val |= 0x1000; |
848 | 3 | } |
849 | 27 | return Val; |
850 | 27 | } |
851 | | |
852 | | /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label |
853 | | /// target. |
854 | | uint32_t ARMMCCodeEmitter:: |
855 | | getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, |
856 | | SmallVectorImpl<MCFixup> &Fixups, |
857 | 47 | const MCSubtargetInfo &STI) const { |
858 | 47 | const MCOperand MO = MI.getOperand(OpIdx); |
859 | 47 | if (MO.isExpr()) |
860 | 34 | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, |
861 | 34 | Fixups, STI); |
862 | 13 | return MO.getImm(); |
863 | 13 | } |
864 | | |
865 | | /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' |
866 | | /// operand. |
867 | | uint32_t ARMMCCodeEmitter:: |
868 | | getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, |
869 | | SmallVectorImpl<MCFixup> &, |
870 | 908 | const MCSubtargetInfo &STI) const { |
871 | 908 | // [Rn, Rm] |
872 | 908 | // {5-3} = Rm |
873 | 908 | // {2-0} = Rn |
874 | 908 | const MCOperand &MO1 = MI.getOperand(OpIdx); |
875 | 908 | const MCOperand &MO2 = MI.getOperand(OpIdx + 1); |
876 | 908 | unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); |
877 | 908 | unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); |
878 | 908 | return (Rm << 3) | Rn; |
879 | 908 | } |
880 | | |
881 | | /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. |
882 | | uint32_t ARMMCCodeEmitter:: |
883 | | getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, |
884 | | SmallVectorImpl<MCFixup> &Fixups, |
885 | 8.40k | const MCSubtargetInfo &STI) const { |
886 | 8.40k | // {17-13} = reg |
887 | 8.40k | // {12} = (U)nsigned (add == '1', sub == '0') |
888 | 8.40k | // {11-0} = imm12 |
889 | 8.40k | unsigned Reg, Imm12; |
890 | 8.40k | bool isAdd = true; |
891 | 8.40k | // If The first operand isn't a register, we have a label reference. |
892 | 8.40k | const MCOperand &MO = MI.getOperand(OpIdx); |
893 | 8.40k | if (!MO.isReg()8.40k ) { |
894 | 105 | Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. |
895 | 105 | Imm12 = 0; |
896 | 105 | |
897 | 105 | if (MO.isExpr()105 ) { |
898 | 57 | const MCExpr *Expr = MO.getExpr(); |
899 | 57 | isAdd = false ; // 'U' bit is set as part of the fixup. |
900 | 57 | |
901 | 57 | MCFixupKind Kind; |
902 | 57 | if (isThumb2(STI)) |
903 | 27 | Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); |
904 | 57 | else |
905 | 30 | Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); |
906 | 57 | Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); |
907 | 57 | |
908 | 57 | ++MCNumCPRelocations; |
909 | 105 | } else { |
910 | 48 | Reg = ARM::PC; |
911 | 48 | int32_t Offset = MO.getImm(); |
912 | 48 | if (Offset == INT32_MIN48 ) { |
913 | 16 | Offset = 0; |
914 | 16 | isAdd = false; |
915 | 48 | } else if (32 Offset < 032 ) { |
916 | 32 | Offset *= -1; |
917 | 32 | isAdd = false; |
918 | 32 | } |
919 | 48 | Imm12 = Offset; |
920 | 48 | } |
921 | 105 | } else |
922 | 8.29k | isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); |
923 | 8.40k | |
924 | 8.40k | uint32_t Binary = Imm12 & 0xfff; |
925 | 8.40k | // Immediate is always encoded as positive. The 'U' bit controls add vs sub. |
926 | 8.40k | if (isAdd) |
927 | 8.25k | Binary |= (1 << 12); |
928 | 8.40k | Binary |= (Reg << 13); |
929 | 8.40k | return Binary; |
930 | 8.40k | } |
931 | | |
932 | | /// getT2Imm8s4OpValue - Return encoding info for |
933 | | /// '+/- imm8<<2' operand. |
934 | | uint32_t ARMMCCodeEmitter:: |
935 | | getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, |
936 | | SmallVectorImpl<MCFixup> &Fixups, |
937 | 66 | const MCSubtargetInfo &STI) const { |
938 | 66 | // FIXME: The immediate operand should have already been encoded like this |
939 | 66 | // before ever getting here. The encoder method should just need to combine |
940 | 66 | // the MI operands for the register and the offset into a single |
941 | 66 | // representation for the complex operand in the .td file. This isn't just |
942 | 66 | // style, unfortunately. As-is, we can't represent the distinct encoding |
943 | 66 | // for #-0. |
944 | 66 | |
945 | 66 | // {8} = (U)nsigned (add == '1', sub == '0') |
946 | 66 | // {7-0} = imm8 |
947 | 66 | int32_t Imm8 = MI.getOperand(OpIdx).getImm(); |
948 | 66 | bool isAdd = Imm8 >= 0; |
949 | 66 | |
950 | 66 | // Immediate is always encoded as positive. The 'U' bit controls add vs sub. |
951 | 66 | if (Imm8 < 0) |
952 | 24 | Imm8 = -(uint32_t)Imm8; |
953 | 66 | |
954 | 66 | // Scaled by 4. |
955 | 66 | Imm8 /= 4; |
956 | 66 | |
957 | 66 | uint32_t Binary = Imm8 & 0xff; |
958 | 66 | // Immediate is always encoded as positive. The 'U' bit controls add vs sub. |
959 | 66 | if (isAdd) |
960 | 42 | Binary |= (1 << 8); |
961 | 66 | return Binary; |
962 | 66 | } |
963 | | |
964 | | /// getT2AddrModeImm8s4OpValue - Return encoding info for |
965 | | /// 'reg +/- imm8<<2' operand. |
966 | | uint32_t ARMMCCodeEmitter:: |
967 | | getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, |
968 | | SmallVectorImpl<MCFixup> &Fixups, |
969 | 5.48k | const MCSubtargetInfo &STI) const { |
970 | 5.48k | // {12-9} = reg |
971 | 5.48k | // {8} = (U)nsigned (add == '1', sub == '0') |
972 | 5.48k | // {7-0} = imm8 |
973 | 5.48k | unsigned Reg, Imm8; |
974 | 5.48k | bool isAdd = true; |
975 | 5.48k | // If The first operand isn't a register, we have a label reference. |
976 | 5.48k | const MCOperand &MO = MI.getOperand(OpIdx); |
977 | 5.48k | if (!MO.isReg()5.48k ) { |
978 | 0 | Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. |
979 | 0 | Imm8 = 0; |
980 | 0 | isAdd = false ; // 'U' bit is set as part of the fixup. |
981 | 0 |
|
982 | 0 | assert(MO.isExpr() && "Unexpected machine operand type!"); |
983 | 0 | const MCExpr *Expr = MO.getExpr(); |
984 | 0 | MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); |
985 | 0 | Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); |
986 | 0 |
|
987 | 0 | ++MCNumCPRelocations; |
988 | 0 | } else |
989 | 5.48k | isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); |
990 | 5.48k | |
991 | 5.48k | // FIXME: The immediate operand should have already been encoded like this |
992 | 5.48k | // before ever getting here. The encoder method should just need to combine |
993 | 5.48k | // the MI operands for the register and the offset into a single |
994 | 5.48k | // representation for the complex operand in the .td file. This isn't just |
995 | 5.48k | // style, unfortunately. As-is, we can't represent the distinct encoding |
996 | 5.48k | // for #-0. |
997 | 5.48k | uint32_t Binary = (Imm8 >> 2) & 0xff; |
998 | 5.48k | // Immediate is always encoded as positive. The 'U' bit controls add vs sub. |
999 | 5.48k | if (isAdd) |
1000 | 5.41k | Binary |= (1 << 8); |
1001 | 5.48k | Binary |= (Reg << 9); |
1002 | 5.48k | return Binary; |
1003 | 5.48k | } |
1004 | | |
1005 | | /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for |
1006 | | /// 'reg + imm8<<2' operand. |
1007 | | uint32_t ARMMCCodeEmitter:: |
1008 | | getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, |
1009 | | SmallVectorImpl<MCFixup> &Fixups, |
1010 | 1.22k | const MCSubtargetInfo &STI) const { |
1011 | 1.22k | // {11-8} = reg |
1012 | 1.22k | // {7-0} = imm8 |
1013 | 1.22k | const MCOperand &MO = MI.getOperand(OpIdx); |
1014 | 1.22k | const MCOperand &MO1 = MI.getOperand(OpIdx + 1); |
1015 | 1.22k | unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); |
1016 | 1.22k | unsigned Imm8 = MO1.getImm(); |
1017 | 1.22k | return (Reg << 8) | Imm8; |
1018 | 1.22k | } |
1019 | | |
1020 | | uint32_t |
1021 | | ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, |
1022 | | SmallVectorImpl<MCFixup> &Fixups, |
1023 | 20.5k | const MCSubtargetInfo &STI) const { |
1024 | 20.5k | // {20-16} = imm{15-12} |
1025 | 20.5k | // {11-0} = imm{11-0} |
1026 | 20.5k | const MCOperand &MO = MI.getOperand(OpIdx); |
1027 | 20.5k | if (MO.isImm()) |
1028 | 20.5k | // Hi / lo 16 bits already extracted during earlier passes. |
1029 | 3.12k | return static_cast<unsigned>(MO.getImm()); |
1030 | 17.4k | |
1031 | 17.4k | // Handle :upper16: and :lower16: assembly prefixes. |
1032 | 17.4k | const MCExpr *E = MO.getExpr(); |
1033 | 17.4k | MCFixupKind Kind; |
1034 | 17.4k | if (E->getKind() == MCExpr::Target17.4k ) { |
1035 | 17.4k | const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); |
1036 | 17.4k | E = ARM16Expr->getSubExpr(); |
1037 | 17.4k | |
1038 | 17.4k | if (const MCConstantExpr *MCE17.4k = dyn_cast<MCConstantExpr>(E)) { |
1039 | 12 | const int64_t Value = MCE->getValue(); |
1040 | 12 | if (Value > UINT32_MAX) |
1041 | 0 | report_fatal_error("constant value truncated (limited to 32-bit)"); |
1042 | 12 | |
1043 | 12 | switch (ARM16Expr->getKind()) { |
1044 | 6 | case ARMMCExpr::VK_ARM_HI16: |
1045 | 6 | return (int32_t(Value) & 0xffff0000) >> 16; |
1046 | 6 | case ARMMCExpr::VK_ARM_LO16: |
1047 | 6 | return (int32_t(Value) & 0x0000ffff); |
1048 | 0 | default: 0 llvm_unreachable0 ("Unsupported ARMFixup"); |
1049 | 17.3k | } |
1050 | 17.3k | } |
1051 | 17.3k | |
1052 | 17.3k | switch (ARM16Expr->getKind()) { |
1053 | 0 | default: 0 llvm_unreachable0 ("Unsupported ARMFixup"); |
1054 | 8.69k | case ARMMCExpr::VK_ARM_HI16: |
1055 | 8.65k | Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16 |
1056 | 38 | : ARM::fixup_arm_movt_hi16); |
1057 | 8.69k | break; |
1058 | 8.70k | case ARMMCExpr::VK_ARM_LO16: |
1059 | 8.65k | Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16 |
1060 | 44 | : ARM::fixup_arm_movw_lo16); |
1061 | 8.70k | break; |
1062 | 17.3k | } |
1063 | 17.3k | |
1064 | 17.3k | Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc())); |
1065 | 17.3k | return 0; |
1066 | 17.3k | } |
1067 | 0 | // If the expression doesn't have :upper16: or :lower16: on it, |
1068 | 0 | // it's just a plain immediate expression, previously those evaluated to |
1069 | 0 | // the lower 16 bits of the expression regardless of whether |
1070 | 0 | // we have a movt or a movw, but that led to misleadingly results. |
1071 | 0 | // This is disallowed in the AsmParser in validateInstruction() |
1072 | 0 | // so this should never happen. |
1073 | 0 | llvm_unreachable0 ("expression without :upper16: or :lower16:"); |
1074 | 0 | } |
1075 | | |
1076 | | uint32_t ARMMCCodeEmitter:: |
1077 | | getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, |
1078 | | SmallVectorImpl<MCFixup> &Fixups, |
1079 | 86 | const MCSubtargetInfo &STI) const { |
1080 | 86 | const MCOperand &MO = MI.getOperand(OpIdx); |
1081 | 86 | const MCOperand &MO1 = MI.getOperand(OpIdx+1); |
1082 | 86 | const MCOperand &MO2 = MI.getOperand(OpIdx+2); |
1083 | 86 | unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); |
1084 | 86 | unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); |
1085 | 86 | unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); |
1086 | 86 | bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; |
1087 | 86 | ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); |
1088 | 86 | unsigned SBits = getShiftOp(ShOp); |
1089 | 86 | |
1090 | 86 | // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift |
1091 | 86 | // amount. However, it would be an easy mistake to make so check here. |
1092 | 86 | assert((ShImm & ~0x1f) == 0 && "Out of range shift amount"); |
1093 | 86 | |
1094 | 86 | // {16-13} = Rn |
1095 | 86 | // {12} = isAdd |
1096 | 86 | // {11-0} = shifter |
1097 | 86 | // {3-0} = Rm |
1098 | 86 | // {4} = 0 |
1099 | 86 | // {6-5} = type |
1100 | 86 | // {11-7} = imm |
1101 | 86 | uint32_t Binary = Rm; |
1102 | 86 | Binary |= Rn << 13; |
1103 | 86 | Binary |= SBits << 5; |
1104 | 86 | Binary |= ShImm << 7; |
1105 | 86 | if (isAdd) |
1106 | 74 | Binary |= 1 << 12; |
1107 | 86 | return Binary; |
1108 | 86 | } |
1109 | | |
1110 | | uint32_t ARMMCCodeEmitter:: |
1111 | | getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, |
1112 | | SmallVectorImpl<MCFixup> &Fixups, |
1113 | 1.53k | const MCSubtargetInfo &STI) const { |
1114 | 1.53k | // {13} 1 == imm12, 0 == Rm |
1115 | 1.53k | // {12} isAdd |
1116 | 1.53k | // {11-0} imm12/Rm |
1117 | 1.53k | const MCOperand &MO = MI.getOperand(OpIdx); |
1118 | 1.53k | const MCOperand &MO1 = MI.getOperand(OpIdx+1); |
1119 | 1.53k | unsigned Imm = MO1.getImm(); |
1120 | 1.53k | bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; |
1121 | 1.53k | bool isReg = MO.getReg() != 0; |
1122 | 1.53k | uint32_t Binary = ARM_AM::getAM2Offset(Imm); |
1123 | 1.53k | // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 |
1124 | 1.53k | if (isReg1.53k ) { |
1125 | 28 | ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); |
1126 | 28 | Binary <<= 7; // Shift amount is bits [11:7] |
1127 | 28 | Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] |
1128 | 28 | Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0] |
1129 | 28 | } |
1130 | 1.53k | return Binary | (isAdd << 12) | (isReg << 13); |
1131 | 1.53k | } |
1132 | | |
1133 | | uint32_t ARMMCCodeEmitter:: |
1134 | | getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, |
1135 | | SmallVectorImpl<MCFixup> &Fixups, |
1136 | 12 | const MCSubtargetInfo &STI) const { |
1137 | 12 | // {4} isAdd |
1138 | 12 | // {3-0} Rm |
1139 | 12 | const MCOperand &MO = MI.getOperand(OpIdx); |
1140 | 12 | const MCOperand &MO1 = MI.getOperand(OpIdx+1); |
1141 | 12 | bool isAdd = MO1.getImm() != 0; |
1142 | 12 | return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4); |
1143 | 12 | } |
1144 | | |
1145 | | uint32_t ARMMCCodeEmitter:: |
1146 | | getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, |
1147 | | SmallVectorImpl<MCFixup> &Fixups, |
1148 | 358 | const MCSubtargetInfo &STI) const { |
1149 | 358 | // {9} 1 == imm8, 0 == Rm |
1150 | 358 | // {8} isAdd |
1151 | 358 | // {7-4} imm7_4/zero |
1152 | 358 | // {3-0} imm3_0/Rm |
1153 | 358 | const MCOperand &MO = MI.getOperand(OpIdx); |
1154 | 358 | const MCOperand &MO1 = MI.getOperand(OpIdx+1); |
1155 | 358 | unsigned Imm = MO1.getImm(); |
1156 | 358 | bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; |
1157 | 358 | bool isImm = MO.getReg() == 0; |
1158 | 358 | uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); |
1159 | 358 | // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 |
1160 | 358 | if (!isImm) |
1161 | 12 | Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); |
1162 | 358 | return Imm8 | (isAdd << 8) | (isImm << 9); |
1163 | 358 | } |
1164 | | |
1165 | | uint32_t ARMMCCodeEmitter:: |
1166 | | getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, |
1167 | | SmallVectorImpl<MCFixup> &Fixups, |
1168 | 105 | const MCSubtargetInfo &STI) const { |
1169 | 105 | // {13} 1 == imm8, 0 == Rm |
1170 | 105 | // {12-9} Rn |
1171 | 105 | // {8} isAdd |
1172 | 105 | // {7-4} imm7_4/zero |
1173 | 105 | // {3-0} imm3_0/Rm |
1174 | 105 | const MCOperand &MO = MI.getOperand(OpIdx); |
1175 | 105 | const MCOperand &MO1 = MI.getOperand(OpIdx+1); |
1176 | 105 | const MCOperand &MO2 = MI.getOperand(OpIdx+2); |
1177 | 105 | |
1178 | 105 | // If The first operand isn't a register, we have a label reference. |
1179 | 105 | if (!MO.isReg()105 ) { |
1180 | 2 | unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. |
1181 | 2 | |
1182 | 2 | assert(MO.isExpr() && "Unexpected machine operand type!"); |
1183 | 2 | const MCExpr *Expr = MO.getExpr(); |
1184 | 2 | MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled); |
1185 | 2 | Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); |
1186 | 2 | |
1187 | 2 | ++MCNumCPRelocations; |
1188 | 2 | return (Rn << 9) | (1 << 13); |
1189 | 2 | } |
1190 | 103 | unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); |
1191 | 103 | unsigned Imm = MO2.getImm(); |
1192 | 103 | bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; |
1193 | 103 | bool isImm = MO1.getReg() == 0; |
1194 | 103 | uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); |
1195 | 103 | // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 |
1196 | 103 | if (!isImm) |
1197 | 37 | Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); |
1198 | 105 | return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); |
1199 | 105 | } |
1200 | | |
1201 | | /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. |
1202 | | uint32_t ARMMCCodeEmitter:: |
1203 | | getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, |
1204 | | SmallVectorImpl<MCFixup> &Fixups, |
1205 | 10.3k | const MCSubtargetInfo &STI) const { |
1206 | 10.3k | // [SP, #imm] |
1207 | 10.3k | // {7-0} = imm8 |
1208 | 10.3k | const MCOperand &MO1 = MI.getOperand(OpIdx + 1); |
1209 | 10.3k | assert(MI.getOperand(OpIdx).getReg() == ARM::SP && |
1210 | 10.3k | "Unexpected base register!"); |
1211 | 10.3k | |
1212 | 10.3k | // The immediate is already shifted for the implicit zeroes, so no change |
1213 | 10.3k | // here. |
1214 | 10.3k | return MO1.getImm() & 0xff; |
1215 | 10.3k | } |
1216 | | |
1217 | | /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. |
1218 | | uint32_t ARMMCCodeEmitter:: |
1219 | | getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, |
1220 | | SmallVectorImpl<MCFixup> &Fixups, |
1221 | 12.1k | const MCSubtargetInfo &STI) const { |
1222 | 12.1k | // [Rn, #imm] |
1223 | 12.1k | // {7-3} = imm5 |
1224 | 12.1k | // {2-0} = Rn |
1225 | 12.1k | const MCOperand &MO = MI.getOperand(OpIdx); |
1226 | 12.1k | const MCOperand &MO1 = MI.getOperand(OpIdx + 1); |
1227 | 12.1k | unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); |
1228 | 12.1k | unsigned Imm5 = MO1.getImm(); |
1229 | 12.1k | return ((Imm5 & 0x1f) << 3) | Rn; |
1230 | 12.1k | } |
1231 | | |
1232 | | /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. |
1233 | | uint32_t ARMMCCodeEmitter:: |
1234 | | getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, |
1235 | | SmallVectorImpl<MCFixup> &Fixups, |
1236 | 2.31k | const MCSubtargetInfo &STI) const { |
1237 | 2.31k | const MCOperand MO = MI.getOperand(OpIdx); |
1238 | 2.31k | if (MO.isExpr()) |
1239 | 2.30k | return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI); |
1240 | 16 | return (MO.getImm() >> 2); |
1241 | 16 | } |
1242 | | |
1243 | | /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. |
1244 | | uint32_t ARMMCCodeEmitter:: |
1245 | | getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, |
1246 | | SmallVectorImpl<MCFixup> &Fixups, |
1247 | 1.09k | const MCSubtargetInfo &STI) const { |
1248 | 1.09k | // {12-9} = reg |
1249 | 1.09k | // {8} = (U)nsigned (add == '1', sub == '0') |
1250 | 1.09k | // {7-0} = imm8 |
1251 | 1.09k | unsigned Reg, Imm8; |
1252 | 1.09k | bool isAdd; |
1253 | 1.09k | // If The first operand isn't a register, we have a label reference. |
1254 | 1.09k | const MCOperand &MO = MI.getOperand(OpIdx); |
1255 | 1.09k | if (!MO.isReg()1.09k ) { |
1256 | 447 | Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. |
1257 | 447 | Imm8 = 0; |
1258 | 447 | isAdd = false; // 'U' bit is handled as part of the fixup. |
1259 | 447 | |
1260 | 447 | assert(MO.isExpr() && "Unexpected machine operand type!"); |
1261 | 447 | const MCExpr *Expr = MO.getExpr(); |
1262 | 447 | MCFixupKind Kind; |
1263 | 447 | if (isThumb2(STI)) |
1264 | 374 | Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); |
1265 | 447 | else |
1266 | 73 | Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); |
1267 | 447 | Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); |
1268 | 447 | |
1269 | 447 | ++MCNumCPRelocations; |
1270 | 1.09k | } else { |
1271 | 650 | EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); |
1272 | 650 | isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; |
1273 | 650 | } |
1274 | 1.09k | |
1275 | 1.09k | uint32_t Binary = ARM_AM::getAM5Offset(Imm8); |
1276 | 1.09k | // Immediate is always encoded as positive. The 'U' bit controls add vs sub. |
1277 | 1.09k | if (isAdd) |
1278 | 432 | Binary |= (1 << 8); |
1279 | 1.09k | Binary |= (Reg << 9); |
1280 | 1.09k | return Binary; |
1281 | 1.09k | } |
1282 | | |
1283 | | /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. |
1284 | | uint32_t ARMMCCodeEmitter:: |
1285 | | getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, |
1286 | | SmallVectorImpl<MCFixup> &Fixups, |
1287 | 32 | const MCSubtargetInfo &STI) const { |
1288 | 32 | // {12-9} = reg |
1289 | 32 | // {8} = (U)nsigned (add == '1', sub == '0') |
1290 | 32 | // {7-0} = imm8 |
1291 | 32 | unsigned Reg, Imm8; |
1292 | 32 | bool isAdd; |
1293 | 32 | // If The first operand isn't a register, we have a label reference. |
1294 | 32 | const MCOperand &MO = MI.getOperand(OpIdx); |
1295 | 32 | if (!MO.isReg()32 ) { |
1296 | 0 | Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. |
1297 | 0 | Imm8 = 0; |
1298 | 0 | isAdd = false; // 'U' bit is handled as part of the fixup. |
1299 | 0 |
|
1300 | 0 | assert(MO.isExpr() && "Unexpected machine operand type!"); |
1301 | 0 | const MCExpr *Expr = MO.getExpr(); |
1302 | 0 | MCFixupKind Kind; |
1303 | 0 | if (isThumb2(STI)) |
1304 | 0 | Kind = MCFixupKind(ARM::fixup_t2_pcrel_9); |
1305 | 0 | else |
1306 | 0 | Kind = MCFixupKind(ARM::fixup_arm_pcrel_9); |
1307 | 0 | Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); |
1308 | 0 |
|
1309 | 0 | ++MCNumCPRelocations; |
1310 | 32 | } else { |
1311 | 32 | EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); |
1312 | 32 | isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; |
1313 | 32 | } |
1314 | 32 | |
1315 | 32 | uint32_t Binary = ARM_AM::getAM5Offset(Imm8); |
1316 | 32 | // Immediate is always encoded as positive. The 'U' bit controls add vs sub. |
1317 | 32 | if (isAdd) |
1318 | 16 | Binary |= (1 << 8); |
1319 | 32 | Binary |= (Reg << 9); |
1320 | 32 | return Binary; |
1321 | 32 | } |
1322 | | |
1323 | | unsigned ARMMCCodeEmitter:: |
1324 | | getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, |
1325 | | SmallVectorImpl<MCFixup> &Fixups, |
1326 | 211 | const MCSubtargetInfo &STI) const { |
1327 | 211 | // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be |
1328 | 211 | // shifted. The second is Rs, the amount to shift by, and the third specifies |
1329 | 211 | // the type of the shift. |
1330 | 211 | // |
1331 | 211 | // {3-0} = Rm. |
1332 | 211 | // {4} = 1 |
1333 | 211 | // {6-5} = type |
1334 | 211 | // {11-8} = Rs |
1335 | 211 | // {7} = 0 |
1336 | 211 | |
1337 | 211 | const MCOperand &MO = MI.getOperand(OpIdx); |
1338 | 211 | const MCOperand &MO1 = MI.getOperand(OpIdx + 1); |
1339 | 211 | const MCOperand &MO2 = MI.getOperand(OpIdx + 2); |
1340 | 211 | ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); |
1341 | 211 | |
1342 | 211 | // Encode Rm. |
1343 | 211 | unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); |
1344 | 211 | |
1345 | 211 | // Encode the shift opcode. |
1346 | 211 | unsigned SBits = 0; |
1347 | 211 | unsigned Rs = MO1.getReg(); |
1348 | 211 | if (Rs211 ) { |
1349 | 211 | // Set shift operand (bit[7:4]). |
1350 | 211 | // LSL - 0001 |
1351 | 211 | // LSR - 0011 |
1352 | 211 | // ASR - 0101 |
1353 | 211 | // ROR - 0111 |
1354 | 211 | switch (SOpc) { |
1355 | 0 | default: 0 llvm_unreachable0 ("Unknown shift opc!"); |
1356 | 55 | case ARM_AM::lsl: SBits = 0x1; break; |
1357 | 50 | case ARM_AM::lsr: SBits = 0x3; break; |
1358 | 52 | case ARM_AM::asr: SBits = 0x5; break; |
1359 | 54 | case ARM_AM::ror: SBits = 0x7; break; |
1360 | 211 | } |
1361 | 211 | } |
1362 | 211 | |
1363 | 211 | Binary |= SBits << 4; |
1364 | 211 | |
1365 | 211 | // Encode the shift operation Rs. |
1366 | 211 | // Encode Rs bit[11:8]. |
1367 | 211 | assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); |
1368 | 211 | return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift); |
1369 | 211 | } |
1370 | | |
1371 | | unsigned ARMMCCodeEmitter:: |
1372 | | getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, |
1373 | | SmallVectorImpl<MCFixup> &Fixups, |
1374 | 468 | const MCSubtargetInfo &STI) const { |
1375 | 468 | // Sub-operands are [reg, imm]. The first register is Rm, the reg to be |
1376 | 468 | // shifted. The second is the amount to shift by. |
1377 | 468 | // |
1378 | 468 | // {3-0} = Rm. |
1379 | 468 | // {4} = 0 |
1380 | 468 | // {6-5} = type |
1381 | 468 | // {11-7} = imm |
1382 | 468 | |
1383 | 468 | const MCOperand &MO = MI.getOperand(OpIdx); |
1384 | 468 | const MCOperand &MO1 = MI.getOperand(OpIdx + 1); |
1385 | 468 | ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); |
1386 | 468 | |
1387 | 468 | // Encode Rm. |
1388 | 468 | unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); |
1389 | 468 | |
1390 | 468 | // Encode the shift opcode. |
1391 | 468 | unsigned SBits = 0; |
1392 | 468 | |
1393 | 468 | // Set shift operand (bit[6:4]). |
1394 | 468 | // LSL - 000 |
1395 | 468 | // LSR - 010 |
1396 | 468 | // ASR - 100 |
1397 | 468 | // ROR - 110 |
1398 | 468 | // RRX - 110 and bit[11:8] clear. |
1399 | 468 | switch (SOpc) { |
1400 | 0 | default: 0 llvm_unreachable0 ("Unknown shift opc!"); |
1401 | 144 | case ARM_AM::lsl: SBits = 0x0; break; |
1402 | 124 | case ARM_AM::lsr: SBits = 0x2; break; |
1403 | 80 | case ARM_AM::asr: SBits = 0x4; break; |
1404 | 62 | case ARM_AM::ror: SBits = 0x6; break; |
1405 | 58 | case ARM_AM::rrx: |
1406 | 58 | Binary |= 0x60; |
1407 | 58 | return Binary; |
1408 | 410 | } |
1409 | 410 | |
1410 | 410 | // Encode shift_imm bit[11:7]. |
1411 | 410 | Binary |= SBits << 4; |
1412 | 410 | unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); |
1413 | 410 | assert(Offset < 32 && "Offset must be in range 0-31!"); |
1414 | 410 | return Binary | (Offset << 7); |
1415 | 410 | } |
1416 | | |
1417 | | |
1418 | | unsigned ARMMCCodeEmitter:: |
1419 | | getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, |
1420 | | SmallVectorImpl<MCFixup> &Fixups, |
1421 | 1.41k | const MCSubtargetInfo &STI) const { |
1422 | 1.41k | const MCOperand &MO1 = MI.getOperand(OpNum); |
1423 | 1.41k | const MCOperand &MO2 = MI.getOperand(OpNum+1); |
1424 | 1.41k | const MCOperand &MO3 = MI.getOperand(OpNum+2); |
1425 | 1.41k | |
1426 | 1.41k | // Encoded as [Rn, Rm, imm]. |
1427 | 1.41k | // FIXME: Needs fixup support. |
1428 | 1.41k | unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); |
1429 | 1.41k | Value <<= 4; |
1430 | 1.41k | Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); |
1431 | 1.41k | Value <<= 2; |
1432 | 1.41k | Value |= MO3.getImm(); |
1433 | 1.41k | |
1434 | 1.41k | return Value; |
1435 | 1.41k | } |
1436 | | |
1437 | | unsigned ARMMCCodeEmitter:: |
1438 | | getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, |
1439 | | SmallVectorImpl<MCFixup> &Fixups, |
1440 | 1.32k | const MCSubtargetInfo &STI) const { |
1441 | 1.32k | const MCOperand &MO1 = MI.getOperand(OpNum); |
1442 | 1.32k | const MCOperand &MO2 = MI.getOperand(OpNum+1); |
1443 | 1.32k | |
1444 | 1.32k | // FIXME: Needs fixup support. |
1445 | 1.32k | unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); |
1446 | 1.32k | |
1447 | 1.32k | // Even though the immediate is 8 bits long, we need 9 bits in order |
1448 | 1.32k | // to represent the (inverse of the) sign bit. |
1449 | 1.32k | Value <<= 9; |
1450 | 1.32k | int32_t tmp = (int32_t)MO2.getImm(); |
1451 | 1.32k | if (tmp < 0) |
1452 | 917 | tmp = abs(tmp); |
1453 | 1.32k | else |
1454 | 408 | Value |= 256; // Set the ADD bit |
1455 | 1.32k | Value |= tmp & 255; |
1456 | 1.32k | return Value; |
1457 | 1.32k | } |
1458 | | |
1459 | | unsigned ARMMCCodeEmitter:: |
1460 | | getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, |
1461 | | SmallVectorImpl<MCFixup> &Fixups, |
1462 | 2.02k | const MCSubtargetInfo &STI) const { |
1463 | 2.02k | const MCOperand &MO1 = MI.getOperand(OpNum); |
1464 | 2.02k | |
1465 | 2.02k | // FIXME: Needs fixup support. |
1466 | 2.02k | unsigned Value = 0; |
1467 | 2.02k | int32_t tmp = (int32_t)MO1.getImm(); |
1468 | 2.02k | if (tmp < 0) |
1469 | 21 | tmp = abs(tmp); |
1470 | 2.02k | else |
1471 | 2.00k | Value |= 256; // Set the ADD bit |
1472 | 2.02k | Value |= tmp & 255; |
1473 | 2.02k | return Value; |
1474 | 2.02k | } |
1475 | | |
1476 | | unsigned ARMMCCodeEmitter:: |
1477 | | getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, |
1478 | | SmallVectorImpl<MCFixup> &Fixups, |
1479 | 5.36k | const MCSubtargetInfo &STI) const { |
1480 | 5.36k | // Sub-operands are [reg, imm]. The first register is Rm, the reg to be |
1481 | 5.36k | // shifted. The second is the amount to shift by. |
1482 | 5.36k | // |
1483 | 5.36k | // {3-0} = Rm. |
1484 | 5.36k | // {4} = 0 |
1485 | 5.36k | // {6-5} = type |
1486 | 5.36k | // {11-7} = imm |
1487 | 5.36k | |
1488 | 5.36k | const MCOperand &MO = MI.getOperand(OpIdx); |
1489 | 5.36k | const MCOperand &MO1 = MI.getOperand(OpIdx + 1); |
1490 | 5.36k | ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); |
1491 | 5.36k | |
1492 | 5.36k | // Encode Rm. |
1493 | 5.36k | unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); |
1494 | 5.36k | |
1495 | 5.36k | // Encode the shift opcode. |
1496 | 5.36k | unsigned SBits = 0; |
1497 | 5.36k | // Set shift operand (bit[6:4]). |
1498 | 5.36k | // LSL - 000 |
1499 | 5.36k | // LSR - 010 |
1500 | 5.36k | // ASR - 100 |
1501 | 5.36k | // ROR - 110 |
1502 | 5.36k | switch (SOpc) { |
1503 | 0 | default: 0 llvm_unreachable0 ("Unknown shift opc!"); |
1504 | 3.30k | case ARM_AM::lsl: SBits = 0x0; break; |
1505 | 990 | case ARM_AM::lsr: SBits = 0x2; break; |
1506 | 1.02k | case ARM_AM::asr: SBits = 0x4; break; |
1507 | 6 | case ARM_AM::rrx: 6 LLVM_FALLTHROUGH6 ; |
1508 | 38 | case ARM_AM::ror: SBits = 0x6; break; |
1509 | 5.36k | } |
1510 | 5.36k | |
1511 | 5.36k | Binary |= SBits << 4; |
1512 | 5.36k | if (SOpc == ARM_AM::rrx) |
1513 | 6 | return Binary; |
1514 | 5.35k | |
1515 | 5.35k | // Encode shift_imm bit[11:7]. |
1516 | 5.35k | return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; |
1517 | 5.35k | } |
1518 | | |
1519 | | unsigned ARMMCCodeEmitter:: |
1520 | | getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, |
1521 | | SmallVectorImpl<MCFixup> &Fixups, |
1522 | 845 | const MCSubtargetInfo &STI) const { |
1523 | 845 | // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the |
1524 | 845 | // msb of the mask. |
1525 | 845 | const MCOperand &MO = MI.getOperand(Op); |
1526 | 845 | uint32_t v = ~MO.getImm(); |
1527 | 845 | uint32_t lsb = countTrailingZeros(v); |
1528 | 845 | uint32_t msb = (32 - countLeadingZeros (v)) - 1; |
1529 | 845 | assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); |
1530 | 845 | return lsb | (msb << 5); |
1531 | 845 | } |
1532 | | |
1533 | | unsigned ARMMCCodeEmitter:: |
1534 | | getRegisterListOpValue(const MCInst &MI, unsigned Op, |
1535 | | SmallVectorImpl<MCFixup> &Fixups, |
1536 | 12.0k | const MCSubtargetInfo &STI) const { |
1537 | 12.0k | // VLDM/VSTM: |
1538 | 12.0k | // {12-8} = Vd |
1539 | 12.0k | // {7-0} = Number of registers |
1540 | 12.0k | // |
1541 | 12.0k | // LDM/STM: |
1542 | 12.0k | // {15-0} = Bitfield of GPRs. |
1543 | 12.0k | unsigned Reg = MI.getOperand(Op).getReg(); |
1544 | 12.0k | bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); |
1545 | 12.0k | bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); |
1546 | 12.0k | |
1547 | 12.0k | unsigned Binary = 0; |
1548 | 12.0k | |
1549 | 12.0k | if (SPRRegs || 12.0k DPRRegs12.0k ) { |
1550 | 152 | // VLDM/VSTM |
1551 | 152 | unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); |
1552 | 152 | unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; |
1553 | 152 | Binary |= (RegNo & 0x1f) << 8; |
1554 | 152 | if (SPRRegs) |
1555 | 10 | Binary |= NumRegs; |
1556 | 152 | else |
1557 | 142 | Binary |= NumRegs * 2; |
1558 | 12.0k | } else { |
1559 | 11.8k | const MCRegisterInfo &MRI = *CTX.getRegisterInfo(); |
1560 | 11.8k | assert(std::is_sorted(MI.begin() + Op, MI.end(), |
1561 | 11.8k | [&](const MCOperand &LHS, const MCOperand &RHS) { |
1562 | 11.8k | return MRI.getEncodingValue(LHS.getReg()) < |
1563 | 11.8k | MRI.getEncodingValue(RHS.getReg()); |
1564 | 11.8k | })); |
1565 | 11.8k | |
1566 | 56.6k | for (unsigned I = Op, E = MI.getNumOperands(); I < E56.6k ; ++I44.8k ) { |
1567 | 44.8k | unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg()); |
1568 | 44.8k | Binary |= 1 << RegNo; |
1569 | 44.8k | } |
1570 | 11.8k | } |
1571 | 12.0k | |
1572 | 12.0k | return Binary; |
1573 | 12.0k | } |
1574 | | |
1575 | | /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along |
1576 | | /// with the alignment operand. |
1577 | | unsigned ARMMCCodeEmitter:: |
1578 | | getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, |
1579 | | SmallVectorImpl<MCFixup> &Fixups, |
1580 | 2.26k | const MCSubtargetInfo &STI) const { |
1581 | 2.26k | const MCOperand &Reg = MI.getOperand(Op); |
1582 | 2.26k | const MCOperand &Imm = MI.getOperand(Op + 1); |
1583 | 2.26k | |
1584 | 2.26k | unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); |
1585 | 2.26k | unsigned Align = 0; |
1586 | 2.26k | |
1587 | 2.26k | switch (Imm.getImm()) { |
1588 | 1.44k | default: break; |
1589 | 398 | case 2: |
1590 | 398 | case 4: |
1591 | 398 | case 8: Align = 0x01; break; |
1592 | 326 | case 16: Align = 0x02; break; |
1593 | 97 | case 32: Align = 0x03; break; |
1594 | 2.26k | } |
1595 | 2.26k | |
1596 | 2.26k | return RegNo | (Align << 4); |
1597 | 2.26k | } |
1598 | | |
1599 | | /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number |
1600 | | /// along with the alignment operand for use in VST1 and VLD1 with size 32. |
1601 | | unsigned ARMMCCodeEmitter:: |
1602 | | getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, |
1603 | | SmallVectorImpl<MCFixup> &Fixups, |
1604 | 51 | const MCSubtargetInfo &STI) const { |
1605 | 51 | const MCOperand &Reg = MI.getOperand(Op); |
1606 | 51 | const MCOperand &Imm = MI.getOperand(Op + 1); |
1607 | 51 | |
1608 | 51 | unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); |
1609 | 51 | unsigned Align = 0; |
1610 | 51 | |
1611 | 51 | switch (Imm.getImm()) { |
1612 | 7 | default: break; |
1613 | 0 | case 8: |
1614 | 0 | case 16: |
1615 | 0 | case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes. |
1616 | 0 | case 2: Align = 0x00; break; |
1617 | 44 | case 4: Align = 0x03; break; |
1618 | 51 | } |
1619 | 51 | |
1620 | 51 | return RegNo | (Align << 4); |
1621 | 51 | } |
1622 | | |
1623 | | |
1624 | | /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and |
1625 | | /// alignment operand for use in VLD-dup instructions. This is the same as |
1626 | | /// getAddrMode6AddressOpValue except for the alignment encoding, which is |
1627 | | /// different for VLD4-dup. |
1628 | | unsigned ARMMCCodeEmitter:: |
1629 | | getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, |
1630 | | SmallVectorImpl<MCFixup> &Fixups, |
1631 | 174 | const MCSubtargetInfo &STI) const { |
1632 | 174 | const MCOperand &Reg = MI.getOperand(Op); |
1633 | 174 | const MCOperand &Imm = MI.getOperand(Op + 1); |
1634 | 174 | |
1635 | 174 | unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); |
1636 | 174 | unsigned Align = 0; |
1637 | 174 | |
1638 | 174 | switch (Imm.getImm()) { |
1639 | 120 | default: break; |
1640 | 48 | case 2: |
1641 | 48 | case 4: |
1642 | 48 | case 8: Align = 0x01; break; |
1643 | 6 | case 16: Align = 0x03; break; |
1644 | 174 | } |
1645 | 174 | |
1646 | 174 | return RegNo | (Align << 4); |
1647 | 174 | } |
1648 | | |
1649 | | unsigned ARMMCCodeEmitter:: |
1650 | | getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, |
1651 | | SmallVectorImpl<MCFixup> &Fixups, |
1652 | 529 | const MCSubtargetInfo &STI) const { |
1653 | 529 | const MCOperand &MO = MI.getOperand(Op); |
1654 | 529 | if (MO.getReg() == 0529 ) return 0x0D252 ; |
1655 | 277 | return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); |
1656 | 277 | } |
1657 | | |
1658 | | unsigned ARMMCCodeEmitter:: |
1659 | | getShiftRight8Imm(const MCInst &MI, unsigned Op, |
1660 | | SmallVectorImpl<MCFixup> &Fixups, |
1661 | 98 | const MCSubtargetInfo &STI) const { |
1662 | 98 | return 8 - MI.getOperand(Op).getImm(); |
1663 | 98 | } |
1664 | | |
1665 | | unsigned ARMMCCodeEmitter:: |
1666 | | getShiftRight16Imm(const MCInst &MI, unsigned Op, |
1667 | | SmallVectorImpl<MCFixup> &Fixups, |
1668 | 98 | const MCSubtargetInfo &STI) const { |
1669 | 98 | return 16 - MI.getOperand(Op).getImm(); |
1670 | 98 | } |
1671 | | |
1672 | | unsigned ARMMCCodeEmitter:: |
1673 | | getShiftRight32Imm(const MCInst &MI, unsigned Op, |
1674 | | SmallVectorImpl<MCFixup> &Fixups, |
1675 | 98 | const MCSubtargetInfo &STI) const { |
1676 | 98 | return 32 - MI.getOperand(Op).getImm(); |
1677 | 98 | } |
1678 | | |
1679 | | unsigned ARMMCCodeEmitter:: |
1680 | | getShiftRight64Imm(const MCInst &MI, unsigned Op, |
1681 | | SmallVectorImpl<MCFixup> &Fixups, |
1682 | 80 | const MCSubtargetInfo &STI) const { |
1683 | 80 | return 64 - MI.getOperand(Op).getImm(); |
1684 | 80 | } |
1685 | | |
1686 | | void ARMMCCodeEmitter:: |
1687 | | encodeInstruction(const MCInst &MI, raw_ostream &OS, |
1688 | | SmallVectorImpl<MCFixup> &Fixups, |
1689 | 298k | const MCSubtargetInfo &STI) const { |
1690 | 298k | // Pseudo instructions don't get encoded. |
1691 | 298k | const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); |
1692 | 298k | uint64_t TSFlags = Desc.TSFlags; |
1693 | 298k | if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) |
1694 | 73 | return; |
1695 | 298k | |
1696 | 298k | int Size; |
1697 | 298k | if (Desc.getSize() == 2 || 298k Desc.getSize() == 4132k ) |
1698 | 298k | Size = Desc.getSize(); |
1699 | 298k | else |
1700 | 0 | llvm_unreachable("Unexpected instruction size!"); |
1701 | 298k | |
1702 | 298k | uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI); |
1703 | 298k | // Thumb 32-bit wide instructions need to emit the high order halfword |
1704 | 298k | // first. |
1705 | 298k | if (isThumb(STI) && 298k Size == 4282k ) { |
1706 | 115k | EmitConstant(Binary >> 16, 2, OS); |
1707 | 115k | EmitConstant(Binary & 0xffff, 2, OS); |
1708 | 115k | } else |
1709 | 183k | EmitConstant(Binary, Size, OS); |
1710 | 298k | ++MCNumEmitted; // Keep track of the # of mi's emitted. |
1711 | 298k | } |
1712 | | |
1713 | | #include "ARMGenMCCodeEmitter.inc" |
1714 | | |
1715 | | MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII, |
1716 | | const MCRegisterInfo &MRI, |
1717 | 3.25k | MCContext &Ctx) { |
1718 | 3.25k | return new ARMMCCodeEmitter(MCII, Ctx, true); |
1719 | 3.25k | } |
1720 | | |
1721 | | MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII, |
1722 | | const MCRegisterInfo &MRI, |
1723 | 17 | MCContext &Ctx) { |
1724 | 17 | return new ARMMCCodeEmitter(MCII, Ctx, false); |
1725 | 17 | } |