/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
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1 | | //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file contains the Thumb-1 implementation of the TargetInstrInfo class. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "Thumb1InstrInfo.h" |
15 | | #include "ARMSubtarget.h" |
16 | | #include "llvm/CodeGen/MachineFrameInfo.h" |
17 | | #include "llvm/CodeGen/MachineInstrBuilder.h" |
18 | | #include "llvm/CodeGen/MachineMemOperand.h" |
19 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
20 | | #include "llvm/MC/MCInst.h" |
21 | | |
22 | | using namespace llvm; |
23 | | |
24 | | Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) |
25 | 590 | : ARMBaseInstrInfo(STI), RI() {} |
26 | | |
27 | | /// Return the noop instruction to use for a noop. |
28 | 1 | void Thumb1InstrInfo::getNoop(MCInst &NopInst) const { |
29 | 1 | NopInst.setOpcode(ARM::tMOVr); |
30 | 1 | NopInst.addOperand(MCOperand::createReg(ARM::R8)); |
31 | 1 | NopInst.addOperand(MCOperand::createReg(ARM::R8)); |
32 | 1 | NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); |
33 | 1 | NopInst.addOperand(MCOperand::createReg(0)); |
34 | 1 | } |
35 | | |
36 | 0 | unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { |
37 | 0 | return 0; |
38 | 0 | } |
39 | | |
40 | | void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, |
41 | | MachineBasicBlock::iterator I, |
42 | | const DebugLoc &DL, unsigned DestReg, |
43 | 3.47k | unsigned SrcReg, bool KillSrc) const { |
44 | 3.47k | // Need to check the arch. |
45 | 3.47k | MachineFunction &MF = *MBB.getParent(); |
46 | 3.47k | const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>(); |
47 | 3.47k | |
48 | 3.47k | assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && |
49 | 3.47k | "Thumb1 can only copy GPR registers"); |
50 | 3.47k | |
51 | 3.47k | if (st.hasV6Ops() || 3.47k ARM::hGPRRegClass.contains(SrcReg)327 |
52 | 239 | || !ARM::tGPRRegClass.contains(DestReg)) |
53 | 3.24k | BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) |
54 | 3.24k | .addReg(SrcReg, getKillRegState(KillSrc)) |
55 | 3.24k | .add(predOps(ARMCC::AL)); |
56 | 230 | else { |
57 | 230 | // FIXME: Can also use 'mov hi, $src; mov $dst, hi', |
58 | 230 | // with hi as either r10 or r11. |
59 | 230 | |
60 | 230 | const TargetRegisterInfo *RegInfo = st.getRegisterInfo(); |
61 | 230 | if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) |
62 | 230 | == MachineBasicBlock::LQR_Dead) { |
63 | 221 | BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) |
64 | 221 | .addReg(SrcReg, getKillRegState(KillSrc)) |
65 | 221 | ->addRegisterDead(ARM::CPSR, RegInfo); |
66 | 221 | return; |
67 | 221 | } |
68 | 9 | |
69 | 9 | // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it |
70 | 9 | BuildMI(MBB, I, DL, get(ARM::tPUSH)) |
71 | 9 | .add(predOps(ARMCC::AL)) |
72 | 9 | .addReg(SrcReg, getKillRegState(KillSrc)); |
73 | 9 | BuildMI(MBB, I, DL, get(ARM::tPOP)) |
74 | 9 | .add(predOps(ARMCC::AL)) |
75 | 9 | .addReg(DestReg, getDefRegState(true)); |
76 | 9 | } |
77 | 3.47k | } |
78 | | |
79 | | void Thumb1InstrInfo:: |
80 | | storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
81 | | unsigned SrcReg, bool isKill, int FI, |
82 | | const TargetRegisterClass *RC, |
83 | 1.10k | const TargetRegisterInfo *TRI) const { |
84 | 1.10k | assert((RC == &ARM::tGPRRegClass || |
85 | 1.10k | (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
86 | 1.10k | isARMLowRegister(SrcReg))) && "Unknown regclass!"); |
87 | 1.10k | |
88 | 1.10k | if (RC == &ARM::tGPRRegClass || |
89 | 0 | (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
90 | 1.10k | isARMLowRegister(SrcReg)0 )) { |
91 | 1.10k | DebugLoc DL; |
92 | 1.10k | if (I != MBB.end()1.10k ) DL = I->getDebugLoc()1.09k ; |
93 | 1.10k | |
94 | 1.10k | MachineFunction &MF = *MBB.getParent(); |
95 | 1.10k | MachineFrameInfo &MFI = MF.getFrameInfo(); |
96 | 1.10k | MachineMemOperand *MMO = MF.getMachineMemOperand( |
97 | 1.10k | MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore, |
98 | 1.10k | MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); |
99 | 1.10k | BuildMI(MBB, I, DL, get(ARM::tSTRspi)) |
100 | 1.10k | .addReg(SrcReg, getKillRegState(isKill)) |
101 | 1.10k | .addFrameIndex(FI) |
102 | 1.10k | .addImm(0) |
103 | 1.10k | .addMemOperand(MMO) |
104 | 1.10k | .add(predOps(ARMCC::AL)); |
105 | 1.10k | } |
106 | 1.10k | } |
107 | | |
108 | | void Thumb1InstrInfo:: |
109 | | loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
110 | | unsigned DestReg, int FI, |
111 | | const TargetRegisterClass *RC, |
112 | 1.75k | const TargetRegisterInfo *TRI) const { |
113 | 1.75k | assert((RC == &ARM::tGPRRegClass || |
114 | 1.75k | (TargetRegisterInfo::isPhysicalRegister(DestReg) && |
115 | 1.75k | isARMLowRegister(DestReg))) && "Unknown regclass!"); |
116 | 1.75k | |
117 | 1.75k | if (RC == &ARM::tGPRRegClass || |
118 | 0 | (TargetRegisterInfo::isPhysicalRegister(DestReg) && |
119 | 1.75k | isARMLowRegister(DestReg)0 )) { |
120 | 1.75k | DebugLoc DL; |
121 | 1.75k | if (I != MBB.end()1.75k ) DL = I->getDebugLoc()1.75k ; |
122 | 1.75k | |
123 | 1.75k | MachineFunction &MF = *MBB.getParent(); |
124 | 1.75k | MachineFrameInfo &MFI = MF.getFrameInfo(); |
125 | 1.75k | MachineMemOperand *MMO = MF.getMachineMemOperand( |
126 | 1.75k | MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad, |
127 | 1.75k | MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); |
128 | 1.75k | BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) |
129 | 1.75k | .addFrameIndex(FI) |
130 | 1.75k | .addImm(0) |
131 | 1.75k | .addMemOperand(MMO) |
132 | 1.75k | .add(predOps(ARMCC::AL)); |
133 | 1.75k | } |
134 | 1.75k | } |
135 | | |
136 | | void Thumb1InstrInfo::expandLoadStackGuard( |
137 | 6 | MachineBasicBlock::iterator MI) const { |
138 | 6 | MachineFunction &MF = *MI->getParent()->getParent(); |
139 | 6 | const TargetMachine &TM = MF.getTarget(); |
140 | 6 | if (TM.isPositionIndependent()) |
141 | 2 | expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi); |
142 | 6 | else |
143 | 4 | expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi); |
144 | 6 | } |