/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
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1 | | //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file provides Mips specific target descriptions. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "MipsMCTargetDesc.h" |
15 | | #include "InstPrinter/MipsInstPrinter.h" |
16 | | #include "MipsAsmBackend.h" |
17 | | #include "MipsELFStreamer.h" |
18 | | #include "MipsMCAsmInfo.h" |
19 | | #include "MipsMCNaCl.h" |
20 | | #include "MipsTargetStreamer.h" |
21 | | #include "llvm/ADT/Triple.h" |
22 | | #include "llvm/MC/MCELFStreamer.h" |
23 | | #include "llvm/MC/MCInstrAnalysis.h" |
24 | | #include "llvm/MC/MCInstrInfo.h" |
25 | | #include "llvm/MC/MCRegisterInfo.h" |
26 | | #include "llvm/MC/MCSubtargetInfo.h" |
27 | | #include "llvm/MC/MCSymbol.h" |
28 | | #include "llvm/MC/MachineLocation.h" |
29 | | #include "llvm/Support/ErrorHandling.h" |
30 | | #include "llvm/Support/FormattedStream.h" |
31 | | #include "llvm/Support/TargetRegistry.h" |
32 | | |
33 | | using namespace llvm; |
34 | | |
35 | | #define GET_INSTRINFO_MC_DESC |
36 | | #include "MipsGenInstrInfo.inc" |
37 | | |
38 | | #define GET_SUBTARGETINFO_MC_DESC |
39 | | #include "MipsGenSubtargetInfo.inc" |
40 | | |
41 | | #define GET_REGINFO_MC_DESC |
42 | | #include "MipsGenRegisterInfo.inc" |
43 | | |
44 | | /// Select the Mips CPU for the given triple and cpu name. |
45 | | /// FIXME: Merge with the copy in MipsSubtarget.cpp |
46 | 13.7k | StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) { |
47 | 13.7k | if (CPU.empty() || 13.7k CPU == "generic"8.66k ) { |
48 | 5.03k | if (TT.getArch() == Triple::mips || 5.03k TT.getArch() == Triple::mipsel3.63k ) |
49 | 4.02k | CPU = "mips32"; |
50 | 5.03k | else |
51 | 1.01k | CPU = "mips64"; |
52 | 5.03k | } |
53 | 13.7k | return CPU; |
54 | 13.7k | } |
55 | | |
56 | 3.19k | static MCInstrInfo *createMipsMCInstrInfo() { |
57 | 3.19k | MCInstrInfo *X = new MCInstrInfo(); |
58 | 3.19k | InitMipsMCInstrInfo(X); |
59 | 3.19k | return X; |
60 | 3.19k | } |
61 | | |
62 | 3.05k | static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) { |
63 | 3.05k | MCRegisterInfo *X = new MCRegisterInfo(); |
64 | 3.05k | InitMipsMCRegisterInfo(X, Mips::RA); |
65 | 3.05k | return X; |
66 | 3.05k | } |
67 | | |
68 | | static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, |
69 | 3.03k | StringRef CPU, StringRef FS) { |
70 | 3.03k | CPU = MIPS_MC::selectMipsCPU(TT, CPU); |
71 | 3.03k | return createMipsMCSubtargetInfoImpl(TT, CPU, FS); |
72 | 3.03k | } |
73 | | |
74 | | static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, |
75 | 3.04k | const Triple &TT) { |
76 | 3.04k | MCAsmInfo *MAI = new MipsMCAsmInfo(TT); |
77 | 3.04k | |
78 | 3.04k | unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); |
79 | 3.04k | MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0); |
80 | 3.04k | MAI->addInitialFrameState(Inst); |
81 | 3.04k | |
82 | 3.04k | return MAI; |
83 | 3.04k | } |
84 | | |
85 | | static MCInstPrinter *createMipsMCInstPrinter(const Triple &T, |
86 | | unsigned SyntaxVariant, |
87 | | const MCAsmInfo &MAI, |
88 | | const MCInstrInfo &MII, |
89 | 2.33k | const MCRegisterInfo &MRI) { |
90 | 2.33k | return new MipsInstPrinter(MAI, MII, MRI); |
91 | 2.33k | } |
92 | | |
93 | | static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, |
94 | | MCAsmBackend &MAB, raw_pwrite_stream &OS, |
95 | 462 | MCCodeEmitter *Emitter, bool RelaxAll) { |
96 | 462 | MCStreamer *S; |
97 | 462 | if (!T.isOSNaCl()) |
98 | 461 | S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll); |
99 | 462 | else |
100 | 1 | S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll); |
101 | 462 | return S; |
102 | 462 | } |
103 | | |
104 | | static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S, |
105 | | formatted_raw_ostream &OS, |
106 | | MCInstPrinter *InstPrint, |
107 | 2.23k | bool isVerboseAsm) { |
108 | 2.23k | return new MipsTargetAsmStreamer(S, OS); |
109 | 2.23k | } |
110 | | |
111 | 1 | static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) { |
112 | 1 | return new MipsTargetStreamer(S); |
113 | 1 | } |
114 | | |
115 | | static MCTargetStreamer * |
116 | 462 | createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { |
117 | 462 | return new MipsTargetELFStreamer(S, STI); |
118 | 462 | } |
119 | | |
120 | | namespace { |
121 | | |
122 | | class MipsMCInstrAnalysis : public MCInstrAnalysis { |
123 | | public: |
124 | 98 | MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} |
125 | | |
126 | | bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, |
127 | 202 | uint64_t &Target) const override { |
128 | 202 | unsigned NumOps = Inst.getNumOperands(); |
129 | 202 | if (NumOps == 0) |
130 | 0 | return false; |
131 | 202 | switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) { |
132 | 94 | case MCOI::OPERAND_UNKNOWN: |
133 | 94 | case MCOI::OPERAND_IMMEDIATE: |
134 | 94 | // jal, bal ... |
135 | 94 | Target = Inst.getOperand(NumOps - 1).getImm(); |
136 | 94 | return true; |
137 | 61 | case MCOI::OPERAND_PCREL: |
138 | 61 | // b, j, beq ... |
139 | 61 | Target = Addr + Inst.getOperand(NumOps - 1).getImm(); |
140 | 61 | return true; |
141 | 47 | default: |
142 | 47 | return false; |
143 | 0 | } |
144 | 0 | } |
145 | | }; |
146 | | } |
147 | | |
148 | 98 | static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) { |
149 | 98 | return new MipsMCInstrAnalysis(Info); |
150 | 98 | } |
151 | | |
152 | 70.1k | extern "C" void LLVMInitializeMipsTargetMC() { |
153 | 70.1k | for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(), |
154 | 280k | &getTheMips64Target(), &getTheMips64elTarget()}) { |
155 | 280k | // Register the MC asm info. |
156 | 280k | RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); |
157 | 280k | |
158 | 280k | // Register the MC instruction info. |
159 | 280k | TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo); |
160 | 280k | |
161 | 280k | // Register the MC register info. |
162 | 280k | TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo); |
163 | 280k | |
164 | 280k | // Register the elf streamer. |
165 | 280k | TargetRegistry::RegisterELFStreamer(*T, createMCStreamer); |
166 | 280k | |
167 | 280k | // Register the asm target streamer. |
168 | 280k | TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer); |
169 | 280k | |
170 | 280k | TargetRegistry::RegisterNullTargetStreamer(*T, |
171 | 280k | createMipsNullTargetStreamer); |
172 | 280k | |
173 | 280k | // Register the MC subtarget info. |
174 | 280k | TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo); |
175 | 280k | |
176 | 280k | // Register the MC instruction analyzer. |
177 | 280k | TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis); |
178 | 280k | |
179 | 280k | // Register the MCInstPrinter. |
180 | 280k | TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter); |
181 | 280k | |
182 | 280k | TargetRegistry::RegisterObjectTargetStreamer( |
183 | 280k | *T, createMipsObjectTargetStreamer); |
184 | 280k | |
185 | 280k | // Register the asm backend. |
186 | 280k | TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend); |
187 | 280k | } |
188 | 70.1k | |
189 | 70.1k | // Register the MC Code Emitter |
190 | 70.1k | for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()}) |
191 | 140k | TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB); |
192 | 70.1k | |
193 | 70.1k | for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()}) |
194 | 140k | TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL); |
195 | 70.1k | } |