/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Mips/MipsInstrInfo.h
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1 | | //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file contains the Mips implementation of the TargetInstrInfo class. |
11 | | // |
12 | | // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in |
13 | | // order for MipsLongBranch pass to work correctly when the code has inline |
14 | | // assembly. The returned value doesn't have to be the asm instruction's exact |
15 | | // size in bytes; MipsLongBranch only expects it to be the correct upper bound. |
16 | | //===----------------------------------------------------------------------===// |
17 | | |
18 | | #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H |
19 | | #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H |
20 | | |
21 | | #include "MCTargetDesc/MipsMCTargetDesc.h" |
22 | | #include "Mips.h" |
23 | | #include "MipsRegisterInfo.h" |
24 | | #include "llvm/ADT/ArrayRef.h" |
25 | | #include "llvm/CodeGen/MachineBasicBlock.h" |
26 | | #include "llvm/CodeGen/MachineInstrBuilder.h" |
27 | | #include "llvm/CodeGen/MachineMemOperand.h" |
28 | | #include "llvm/Target/TargetInstrInfo.h" |
29 | | #include <cstdint> |
30 | | |
31 | | #define GET_INSTRINFO_HEADER |
32 | | #include "MipsGenInstrInfo.inc" |
33 | | |
34 | | namespace llvm { |
35 | | |
36 | | class MachineInstr; |
37 | | class MachineOperand; |
38 | | class MipsSubtarget; |
39 | | class TargetRegisterClass; |
40 | | class TargetRegisterInfo; |
41 | | |
42 | | class MipsInstrInfo : public MipsGenInstrInfo { |
43 | | virtual void anchor(); |
44 | | |
45 | | protected: |
46 | | const MipsSubtarget &Subtarget; |
47 | | unsigned UncondBrOpc; |
48 | | |
49 | | public: |
50 | | enum BranchType { |
51 | | BT_None, // Couldn't analyze branch. |
52 | | BT_NoBranch, // No branches found. |
53 | | BT_Uncond, // One unconditional branch. |
54 | | BT_Cond, // One conditional branch. |
55 | | BT_CondUncond, // A conditional branch followed by an unconditional branch. |
56 | | BT_Indirect // One indirct branch. |
57 | | }; |
58 | | |
59 | | explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc); |
60 | | |
61 | | static const MipsInstrInfo *create(MipsSubtarget &STI); |
62 | | |
63 | | /// Branch Analysis |
64 | | bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
65 | | MachineBasicBlock *&FBB, |
66 | | SmallVectorImpl<MachineOperand> &Cond, |
67 | | bool AllowModify) const override; |
68 | | |
69 | | unsigned removeBranch(MachineBasicBlock &MBB, |
70 | | int *BytesRemoved = nullptr) const override; |
71 | | |
72 | | unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
73 | | MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, |
74 | | const DebugLoc &DL, |
75 | | int *BytesAdded = nullptr) const override; |
76 | | |
77 | | bool |
78 | | reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; |
79 | | |
80 | | BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
81 | | MachineBasicBlock *&FBB, |
82 | | SmallVectorImpl<MachineOperand> &Cond, |
83 | | bool AllowModify, |
84 | | SmallVectorImpl<MachineInstr *> &BranchInstrs) const; |
85 | | |
86 | | /// Determine the opcode of a non-delay slot form for a branch if one exists. |
87 | | unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const; |
88 | | |
89 | | /// Predicate to determine if an instruction can go in a forbidden slot. |
90 | | bool SafeInForbiddenSlot(const MachineInstr &MI) const; |
91 | | |
92 | | /// Predicate to determine if an instruction has a forbidden slot. |
93 | | bool HasForbiddenSlot(const MachineInstr &MI) const; |
94 | | |
95 | | /// Insert nop instruction when hazard condition is found |
96 | | void insertNoop(MachineBasicBlock &MBB, |
97 | | MachineBasicBlock::iterator MI) const override; |
98 | | |
99 | | /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As |
100 | | /// such, whenever a client has an instance of instruction info, it should |
101 | | /// always be able to get register info as well (through this method). |
102 | | virtual const MipsRegisterInfo &getRegisterInfo() const = 0; |
103 | | |
104 | | virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; |
105 | | |
106 | | /// Return the number of bytes of code the specified instruction may be. |
107 | | unsigned getInstSizeInBytes(const MachineInstr &MI) const override; |
108 | | |
109 | | void storeRegToStackSlot(MachineBasicBlock &MBB, |
110 | | MachineBasicBlock::iterator MBBI, |
111 | | unsigned SrcReg, bool isKill, int FrameIndex, |
112 | | const TargetRegisterClass *RC, |
113 | 4.55k | const TargetRegisterInfo *TRI) const override { |
114 | 4.55k | storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); |
115 | 4.55k | } |
116 | | |
117 | | void loadRegFromStackSlot(MachineBasicBlock &MBB, |
118 | | MachineBasicBlock::iterator MBBI, |
119 | | unsigned DestReg, int FrameIndex, |
120 | | const TargetRegisterClass *RC, |
121 | 4.60k | const TargetRegisterInfo *TRI) const override { |
122 | 4.60k | loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); |
123 | 4.60k | } |
124 | | |
125 | | virtual void storeRegToStack(MachineBasicBlock &MBB, |
126 | | MachineBasicBlock::iterator MI, |
127 | | unsigned SrcReg, bool isKill, int FrameIndex, |
128 | | const TargetRegisterClass *RC, |
129 | | const TargetRegisterInfo *TRI, |
130 | | int64_t Offset) const = 0; |
131 | | |
132 | | virtual void loadRegFromStack(MachineBasicBlock &MBB, |
133 | | MachineBasicBlock::iterator MI, |
134 | | unsigned DestReg, int FrameIndex, |
135 | | const TargetRegisterClass *RC, |
136 | | const TargetRegisterInfo *TRI, |
137 | | int64_t Offset) const = 0; |
138 | | |
139 | | virtual void adjustStackPtr(unsigned SP, int64_t Amount, |
140 | | MachineBasicBlock &MBB, |
141 | | MachineBasicBlock::iterator I) const = 0; |
142 | | |
143 | | /// Create an instruction which has the same operands and memory operands |
144 | | /// as MI but has a new opcode. |
145 | | MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, |
146 | | MachineBasicBlock::iterator I) const; |
147 | | |
148 | | bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, |
149 | | unsigned &SrcOpIdx2) const override; |
150 | | |
151 | | /// Perform target specific instruction verification. |
152 | | bool verifyInstruction(const MachineInstr &MI, |
153 | | StringRef &ErrInfo) const override; |
154 | | |
155 | | protected: |
156 | | bool isZeroImm(const MachineOperand &op) const; |
157 | | |
158 | | MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI, |
159 | | MachineMemOperand::Flags Flags) const; |
160 | | |
161 | | private: |
162 | | virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0; |
163 | | |
164 | | void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, |
165 | | MachineBasicBlock *&BB, |
166 | | SmallVectorImpl<MachineOperand> &Cond) const; |
167 | | |
168 | | void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
169 | | const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const; |
170 | | }; |
171 | | |
172 | | /// Create MipsInstrInfo objects. |
173 | | const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI); |
174 | | const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI); |
175 | | |
176 | | } // end namespace llvm |
177 | | |
178 | | #endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H |