Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- X86DisassemblerDecoder.cpp - Disassembler decoder -----------------===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This file is part of the X86 Disassembler.
11
// It contains the implementation of the instruction decoder.
12
// Documentation for the disassembler can be found in X86Disassembler.h.
13
//
14
//===----------------------------------------------------------------------===//
15
16
#include <cstdarg> /* for va_*()       */
17
#include <cstdio>  /* for vsnprintf()  */
18
#include <cstdlib> /* for exit()       */
19
#include <cstring> /* for memset()     */
20
21
#include "X86DisassemblerDecoder.h"
22
23
using namespace llvm::X86Disassembler;
24
25
/// Specifies whether a ModR/M byte is needed and (if so) which
26
/// instruction each possible value of the ModR/M byte corresponds to.  Once
27
/// this information is known, we have narrowed down to a single instruction.
28
struct ModRMDecision {
29
  uint8_t modrm_type;
30
  uint16_t instructionIDs;
31
};
32
33
/// Specifies which set of ModR/M->instruction tables to look at
34
/// given a particular opcode.
35
struct OpcodeDecision {
36
  ModRMDecision modRMDecisions[256];
37
};
38
39
/// Specifies which opcode->instruction tables to look at given
40
/// a particular context (set of attributes).  Since there are many possible
41
/// contexts, the decoder first uses CONTEXTS_SYM to determine which context
42
/// applies given a specific set of attributes.  Hence there are only IC_max
43
/// entries in this table, rather than 2^(ATTR_max).
44
struct ContextDecision {
45
  OpcodeDecision opcodeDecisions[IC_max];
46
};
47
48
#include "X86GenDisassemblerTables.inc"
49
50
#ifndef NDEBUG
51
#define debug(s) do { Debug(__FILE__, __LINE__, s); } while (0)
52
#else
53
0
#define debug(s) 
do 0
{ }0
while (
00
)
54
#endif
55
56
/*
57
 * contextForAttrs - Client for the instruction context table.  Takes a set of
58
 *   attributes and returns the appropriate decode context.
59
 *
60
 * @param attrMask  - Attributes, from the enumeration attributeBits.
61
 * @return          - The InstructionContext to use when looking up an
62
 *                    an instruction with these attributes.
63
 */
64
509k
static InstructionContext contextForAttrs(uint16_t attrMask) {
65
509k
  return static_cast<InstructionContext>(CONTEXTS_SYM[attrMask]);
66
509k
}
67
68
/*
69
 * modRMRequired - Reads the appropriate instruction table to determine whether
70
 *   the ModR/M byte is required to decode a particular instruction.
71
 *
72
 * @param type        - The opcode type (i.e., how many bytes it has).
73
 * @param insnContext - The context for the instruction, as returned by
74
 *                      contextForAttrs.
75
 * @param opcode      - The last byte of the instruction's opcode, not counting
76
 *                      ModR/M extensions and escapes.
77
 * @return            - true if the ModR/M byte is required, false otherwise.
78
 */
79
static int modRMRequired(OpcodeType type,
80
                         InstructionContext insnContext,
81
509k
                         uint16_t opcode) {
82
509k
  const struct ContextDecision* decision = nullptr;
83
509k
84
509k
  switch (type) {
85
468k
  case ONEBYTE:
86
468k
    decision = &ONEBYTE_SYM;
87
468k
    break;
88
40.1k
  case TWOBYTE:
89
40.1k
    decision = &TWOBYTE_SYM;
90
40.1k
    break;
91
322
  case THREEBYTE_38:
92
322
    decision = &THREEBYTE38_SYM;
93
322
    break;
94
153
  case THREEBYTE_3A:
95
153
    decision = &THREEBYTE3A_SYM;
96
153
    break;
97
16
  case XOP8_MAP:
98
16
    decision = &XOP8_MAP_SYM;
99
16
    break;
100
12
  case XOP9_MAP:
101
12
    decision = &XOP9_MAP_SYM;
102
12
    break;
103
11
  case XOPA_MAP:
104
11
    decision = &XOPA_MAP_SYM;
105
11
    break;
106
509k
  }
107
509k
108
509k
  return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
109
509k
    modrm_type != MODRM_ONEENTRY;
110
509k
}
111
112
/*
113
 * decode - Reads the appropriate instruction table to obtain the unique ID of
114
 *   an instruction.
115
 *
116
 * @param type        - See modRMRequired().
117
 * @param insnContext - See modRMRequired().
118
 * @param opcode      - See modRMRequired().
119
 * @param modRM       - The ModR/M byte if required, or any value if not.
120
 * @return            - The UID of the instruction, or 0 on failure.
121
 */
122
static InstrUID decode(OpcodeType type,
123
                       InstructionContext insnContext,
124
                       uint8_t opcode,
125
509k
                       uint8_t modRM) {
126
509k
  const struct ModRMDecision* dec = nullptr;
127
509k
128
509k
  switch (type) {
129
468k
  case ONEBYTE:
130
468k
    dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
131
468k
    break;
132
40.1k
  case TWOBYTE:
133
40.1k
    dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
134
40.1k
    break;
135
322
  case THREEBYTE_38:
136
322
    dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
137
322
    break;
138
153
  case THREEBYTE_3A:
139
153
    dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
140
153
    break;
141
16
  case XOP8_MAP:
142
16
    dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
143
16
    break;
144
12
  case XOP9_MAP:
145
12
    dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
146
12
    break;
147
11
  case XOPA_MAP:
148
11
    dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
149
11
    break;
150
509k
  }
151
509k
152
509k
  switch (dec->modrm_type) {
153
0
  default:
154
0
    debug("Corrupt table!  Unknown modrm_type");
155
0
    return 0;
156
188k
  case MODRM_ONEENTRY:
157
188k
    return modRMTable[dec->instructionIDs];
158
241k
  case MODRM_SPLITRM:
159
241k
    if (
modFromModRM241k
(modRM) == 0x3241k
)
160
114k
      return modRMTable[dec->instructionIDs+1];
161
126k
    return modRMTable[dec->instructionIDs];
162
57.8k
  case MODRM_SPLITREG:
163
57.8k
    if (
modFromModRM57.8k
(modRM) == 0x357.8k
)
164
42.9k
      return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
165
14.9k
    return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
166
21.0k
  case MODRM_SPLITMISC:
167
21.0k
    if (
modFromModRM21.0k
(modRM) == 0x321.0k
)
168
725
      return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
169
20.2k
    return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
170
0
  case MODRM_FULL:
171
0
    return modRMTable[dec->instructionIDs+modRM];
172
0
  }
173
0
}
174
175
/*
176
 * specifierForUID - Given a UID, returns the name and operand specification for
177
 *   that instruction.
178
 *
179
 * @param uid - The unique ID for the instruction.  This should be returned by
180
 *              decode(); specifierForUID will not check bounds.
181
 * @return    - A pointer to the specification for that instruction.
182
 */
183
508k
static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
184
508k
  return &INSTRUCTIONS_SYM[uid];
185
508k
}
186
187
/*
188
 * consumeByte - Uses the reader function provided by the user to consume one
189
 *   byte from the instruction's memory and advance the cursor.
190
 *
191
 * @param insn  - The instruction with the reader function to use.  The cursor
192
 *                for this instruction is advanced.
193
 * @param byte  - A pointer to a pre-allocated memory buffer to be populated
194
 *                with the data read.
195
 * @return      - 0 if the read was successful; nonzero otherwise.
196
 */
197
1.52M
static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
198
1.52M
  int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
199
1.52M
200
1.52M
  if (!ret)
201
1.52M
    ++(insn->readerCursor);
202
1.52M
203
1.52M
  return ret;
204
1.52M
}
205
206
/*
207
 * lookAtByte - Like consumeByte, but does not advance the cursor.
208
 *
209
 * @param insn  - See consumeByte().
210
 * @param byte  - See consumeByte().
211
 * @return      - See consumeByte().
212
 */
213
237k
static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
214
237k
  return insn->reader(insn->readerArg, byte, insn->readerCursor);
215
237k
}
216
217
270k
static void unconsumeByte(struct InternalInstruction* insn) {
218
270k
  insn->readerCursor--;
219
270k
}
220
221
#define CONSUME_FUNC(name, type)                                  \
222
220k
  static int name(struct InternalInstruction* insn, type* ptr) {  \
223
220k
    type combined = 0;                                            \
224
220k
    unsigned offset;                                              \
225
884k
    for (offset = 0; 
offset < sizeof(type)884k
;
++offset663k
) { \
226
663k
      uint8_t byte;                                               \
227
663k
      int ret = insn->reader(insn->readerArg,                     \
228
663k
                             &byte,                               \
229
663k
                             insn->readerCursor + offset);        \
230
663k
      if (ret)                                                    \
231
3
        return ret;                                               \
232
663k
      combined = combined | ((uint64_t)byte << (offset * 8));     \
233
663k
    }                                                             \
234
220k
    *ptr = combined;                                              \
235
220k
    insn->readerCursor += sizeof(type);                           \
236
220k
    return 0;                                                     \
237
220k
  }
X86DisassemblerDecoder.cpp:consumeInt8(llvm::X86Disassembler::InternalInstruction*, signed char*)
Line
Count
Source
222
74.4k
  static int name(struct InternalInstruction* insn, type* ptr) {  \
223
74.4k
    type combined = 0;                                            \
224
74.4k
    unsigned offset;                                              \
225
148k
    for (offset = 0; 
offset < sizeof(type)148k
;
++offset74.4k
) { \
226
74.4k
      uint8_t byte;                                               \
227
74.4k
      int ret = insn->reader(insn->readerArg,                     \
228
74.4k
                             &byte,                               \
229
74.4k
                             insn->readerCursor + offset);        \
230
74.4k
      if (ret)                                                    \
231
0
        return ret;                                               \
232
74.4k
      combined = combined | ((uint64_t)byte << (offset * 8));     \
233
74.4k
    }                                                             \
234
74.4k
    *ptr = combined;                                              \
235
74.4k
    insn->readerCursor += sizeof(type);                           \
236
74.4k
    return 0;                                                     \
237
74.4k
  }
X86DisassemblerDecoder.cpp:consumeInt16(llvm::X86Disassembler::InternalInstruction*, short*)
Line
Count
Source
222
14
  static int name(struct InternalInstruction* insn, type* ptr) {  \
223
14
    type combined = 0;                                            \
224
14
    unsigned offset;                                              \
225
42
    for (offset = 0; 
offset < sizeof(type)42
;
++offset28
) { \
226
28
      uint8_t byte;                                               \
227
28
      int ret = insn->reader(insn->readerArg,                     \
228
28
                             &byte,                               \
229
28
                             insn->readerCursor + offset);        \
230
28
      if (ret)                                                    \
231
0
        return ret;                                               \
232
28
      combined = combined | ((uint64_t)byte << (offset * 8));     \
233
28
    }                                                             \
234
14
    *ptr = combined;                                              \
235
14
    insn->readerCursor += sizeof(type);                           \
236
14
    return 0;                                                     \
237
14
  }
X86DisassemblerDecoder.cpp:consumeInt32(llvm::X86Disassembler::InternalInstruction*, int*)
Line
Count
Source
222
58.8k
  static int name(struct InternalInstruction* insn, type* ptr) {  \
223
58.8k
    type combined = 0;                                            \
224
58.8k
    unsigned offset;                                              \
225
294k
    for (offset = 0; 
offset < sizeof(type)294k
;
++offset235k
) { \
226
235k
      uint8_t byte;                                               \
227
235k
      int ret = insn->reader(insn->readerArg,                     \
228
235k
                             &byte,                               \
229
235k
                             insn->readerCursor + offset);        \
230
235k
      if (ret)                                                    \
231
1
        return ret;                                               \
232
235k
      combined = combined | ((uint64_t)byte << (offset * 8));     \
233
235k
    }                                                             \
234
58.8k
    *ptr = combined;                                              \
235
58.8k
    insn->readerCursor += sizeof(type);                           \
236
58.8k
    return 0;                                                     \
237
58.8k
  }
X86DisassemblerDecoder.cpp:consumeUInt16(llvm::X86Disassembler::InternalInstruction*, unsigned short*)
Line
Count
Source
222
183
  static int name(struct InternalInstruction* insn, type* ptr) {  \
223
183
    type combined = 0;                                            \
224
183
    unsigned offset;                                              \
225
549
    for (offset = 0; 
offset < sizeof(type)549
;
++offset366
) { \
226
366
      uint8_t byte;                                               \
227
366
      int ret = insn->reader(insn->readerArg,                     \
228
366
                             &byte,                               \
229
366
                             insn->readerCursor + offset);        \
230
366
      if (ret)                                                    \
231
0
        return ret;                                               \
232
366
      combined = combined | ((uint64_t)byte << (offset * 8));     \
233
366
    }                                                             \
234
183
    *ptr = combined;                                              \
235
183
    insn->readerCursor += sizeof(type);                           \
236
183
    return 0;                                                     \
237
183
  }
X86DisassemblerDecoder.cpp:consumeUInt32(llvm::X86Disassembler::InternalInstruction*, unsigned int*)
Line
Count
Source
222
86.1k
  static int name(struct InternalInstruction* insn, type* ptr) {  \
223
86.1k
    type combined = 0;                                            \
224
86.1k
    unsigned offset;                                              \
225
430k
    for (offset = 0; 
offset < sizeof(type)430k
;
++offset344k
) { \
226
344k
      uint8_t byte;                                               \
227
344k
      int ret = insn->reader(insn->readerArg,                     \
228
344k
                             &byte,                               \
229
344k
                             insn->readerCursor + offset);        \
230
344k
      if (ret)                                                    \
231
2
        return ret;                                               \
232
344k
      combined = combined | ((uint64_t)byte << (offset * 8));     \
233
344k
    }                                                             \
234
86.1k
    *ptr = combined;                                              \
235
86.1k
    insn->readerCursor += sizeof(type);                           \
236
86.1k
    return 0;                                                     \
237
86.1k
  }
X86DisassemblerDecoder.cpp:consumeUInt64(llvm::X86Disassembler::InternalInstruction*, unsigned long long*)
Line
Count
Source
222
1.18k
  static int name(struct InternalInstruction* insn, type* ptr) {  \
223
1.18k
    type combined = 0;                                            \
224
1.18k
    unsigned offset;                                              \
225
10.6k
    for (offset = 0; 
offset < sizeof(type)10.6k
;
++offset9.48k
) { \
226
9.48k
      uint8_t byte;                                               \
227
9.48k
      int ret = insn->reader(insn->readerArg,                     \
228
9.48k
                             &byte,                               \
229
9.48k
                             insn->readerCursor + offset);        \
230
9.48k
      if (ret)                                                    \
231
0
        return ret;                                               \
232
9.48k
      combined = combined | ((uint64_t)byte << (offset * 8));     \
233
9.48k
    }                                                             \
234
1.18k
    *ptr = combined;                                              \
235
1.18k
    insn->readerCursor += sizeof(type);                           \
236
1.18k
    return 0;                                                     \
237
1.18k
  }
238
239
/*
240
 * consume* - Use the reader function provided by the user to consume data
241
 *   values of various sizes from the instruction's memory and advance the
242
 *   cursor appropriately.  These readers perform endian conversion.
243
 *
244
 * @param insn    - See consumeByte().
245
 * @param ptr     - A pointer to a pre-allocated memory of appropriate size to
246
 *                  be populated with the data read.
247
 * @return        - See consumeByte().
248
 */
249
CONSUME_FUNC(consumeInt8, int8_t)
250
CONSUME_FUNC(consumeInt16, int16_t)
251
CONSUME_FUNC(consumeInt32, int32_t)
252
CONSUME_FUNC(consumeUInt16, uint16_t)
253
CONSUME_FUNC(consumeUInt32, uint32_t)
254
CONSUME_FUNC(consumeUInt64, uint64_t)
255
256
/*
257
 * dbgprintf - Uses the logging function provided by the user to log a single
258
 *   message, typically without a carriage-return.
259
 *
260
 * @param insn    - The instruction containing the logging function.
261
 * @param format  - See printf().
262
 * @param ...     - See printf().
263
 */
264
static void dbgprintf(struct InternalInstruction* insn,
265
                      const char* format,
266
5.20M
                      ...) {
267
5.20M
  char buffer[256];
268
5.20M
  va_list ap;
269
5.20M
270
5.20M
  if (!insn->dlog)
271
5.20M
    return;
272
0
273
5.20M
  va_start(ap, format);
274
0
  (void)vsnprintf(buffer, sizeof(buffer), format, ap);
275
0
  va_end(ap);
276
0
277
0
  insn->dlog(insn->dlogArg, buffer);
278
0
}
279
280
/*
281
 * setPrefixPresent - Marks that a particular prefix is present at a particular
282
 *   location.
283
 *
284
 * @param insn      - The instruction to be marked as having the prefix.
285
 * @param prefix    - The prefix that is present.
286
 * @param location  - The location where the prefix is located (in the address
287
 *                    space of the instruction's reader).
288
 */
289
static void setPrefixPresent(struct InternalInstruction* insn,
290
                                    uint8_t prefix,
291
                                    uint64_t location)
292
19.4k
{
293
19.4k
  insn->prefixPresent[prefix] = 1;
294
19.4k
  insn->prefixLocations[prefix] = location;
295
19.4k
}
296
297
/*
298
 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is
299
 *   present at a given location.
300
 *
301
 * @param insn      - The instruction to be queried.
302
 * @param prefix    - The prefix.
303
 * @param location  - The location to query.
304
 * @return          - Whether the prefix is at that location.
305
 */
306
static bool isPrefixAtLocation(struct InternalInstruction* insn,
307
                               uint8_t prefix,
308
                               uint64_t location)
309
2.49M
{
310
2.49M
  return insn->prefixPresent[prefix] == 1 &&
311
17.0k
     insn->prefixLocations[prefix] == location;
312
2.49M
}
313
314
/*
315
 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
316
 *   instruction as having them.  Also sets the instruction's default operand,
317
 *   address, and other relevant data sizes to report operands correctly.
318
 *
319
 * @param insn  - The instruction whose prefixes are to be read.
320
 * @return      - 0 if the instruction could be read until the end of the prefix
321
 *                bytes, and no prefixes conflicted; nonzero otherwise.
322
 */
323
506k
static int readPrefixes(struct InternalInstruction* insn) {
324
506k
  bool isPrefix = true;
325
506k
  bool prefixGroups[4] = { false };
326
506k
  uint64_t prefixLocation;
327
506k
  uint8_t byte = 0;
328
506k
  uint8_t nextByte;
329
506k
330
506k
  bool hasAdSize = false;
331
506k
  bool hasOpSize = false;
332
506k
333
506k
  dbgprintf(insn, "readPrefixes()");
334
506k
335
1.03M
  while (
isPrefix1.03M
) {
336
525k
    prefixLocation = insn->readerCursor;
337
525k
338
525k
    /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */
339
525k
    if (consumeByte(insn, &byte))
340
4
      break;
341
525k
342
525k
    /*
343
525k
     * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
344
525k
     * break and let it be disassembled as a normal "instruction".
345
525k
     */
346
525k
    
if (525k
insn->readerCursor - 1 == insn->startLocation && 525k
byte == 0xf0506k
)
347
289
      break;
348
525k
349
525k
    
if (525k
insn->readerCursor - 1 == insn->startLocation
350
506k
        && 
(byte == 0xf2 || 506k
byte == 0xf3505k
)
351
1.36k
        && !lookAtByte(insn, &nextByte))
352
1.36k
    {
353
1.36k
      /*
354
1.36k
       * If the byte is 0xf2 or 0xf3, and any of the following conditions are
355
1.36k
       * met:
356
1.36k
       * - it is followed by a LOCK (0xf0) prefix
357
1.36k
       * - it is followed by an xchg instruction
358
1.36k
       * then it should be disassembled as a xacquire/xrelease not repne/rep.
359
1.36k
       */
360
1.36k
      if (
(byte == 0xf2 || 1.36k
byte == 0xf3837
) &&
361
1.36k
          ((nextByte == 0xf0) ||
362
1.36k
          
((nextByte & 0xfe) == 0x86 || 1.36k
(nextByte & 0xf8) == 0x901.36k
)))
363
119
        insn->xAcquireRelease = true;
364
1.36k
      /*
365
1.36k
       * Also if the byte is 0xf3, and the following condition is met:
366
1.36k
       * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
367
1.36k
       *                       "mov mem, imm" (opcode 0xc6/0xc7) instructions.
368
1.36k
       * then it should be disassembled as an xrelease not rep.
369
1.36k
       */
370
1.36k
      if (byte == 0xf3 &&
371
837
          
(nextByte == 0x88 || 837
nextByte == 0x89836
||
372
837
           
nextByte == 0xc6835
||
nextByte == 0xc7834
))
373
4
        insn->xAcquireRelease = true;
374
1.36k
      if (
insn->mode == MODE_64BIT && 1.36k
(nextByte & 0xf0) == 0x401.34k
) {
375
79
        if (consumeByte(insn, &nextByte))
376
0
          return -1;
377
79
        
if (79
lookAtByte(insn, &nextByte)79
)
378
0
          return -1;
379
79
        unconsumeByte(insn);
380
79
      }
381
1.36k
      
if (1.36k
nextByte != 0x0f && 1.36k
nextByte != 0x90165
)
382
51
        break;
383
525k
    }
384
525k
385
525k
    switch (byte) {
386
1.32k
    case 0xf0:  /* LOCK */
387
1.32k
    case 0xf2:  /* REPNE/REPNZ */
388
1.32k
    case 0xf3:  /* REP or REPE/REPZ */
389
1.32k
      if (prefixGroups[0])
390
0
        dbgprintf(insn, "Redundant Group 1 prefix");
391
1.32k
      prefixGroups[0] = true;
392
1.32k
      setPrefixPresent(insn, byte, prefixLocation);
393
1.32k
      break;
394
2.31k
    case 0x2e:  /* CS segment override -OR- Branch not taken */
395
2.31k
    case 0x36:  /* SS segment override -OR- Branch taken */
396
2.31k
    case 0x3e:  /* DS segment override */
397
2.31k
    case 0x26:  /* ES segment override */
398
2.31k
    case 0x64:  /* FS segment override */
399
2.31k
    case 0x65:  /* GS segment override */
400
2.31k
      switch (byte) {
401
2.17k
      case 0x2e:
402
2.17k
        insn->segmentOverride = SEG_OVERRIDE_CS;
403
2.17k
        break;
404
0
      case 0x36:
405
0
        insn->segmentOverride = SEG_OVERRIDE_SS;
406
0
        break;
407
0
      case 0x3e:
408
0
        insn->segmentOverride = SEG_OVERRIDE_DS;
409
0
        break;
410
9
      case 0x26:
411
9
        insn->segmentOverride = SEG_OVERRIDE_ES;
412
9
        break;
413
74
      case 0x64:
414
74
        insn->segmentOverride = SEG_OVERRIDE_FS;
415
74
        break;
416
57
      case 0x65:
417
57
        insn->segmentOverride = SEG_OVERRIDE_GS;
418
57
        break;
419
0
      default:
420
0
        debug("Unhandled override");
421
0
        return -1;
422
2.31k
      }
423
2.31k
      
if (2.31k
prefixGroups[1]2.31k
)
424
3
        dbgprintf(insn, "Redundant Group 2 prefix");
425
2.31k
      prefixGroups[1] = true;
426
2.31k
      setPrefixPresent(insn, byte, prefixLocation);
427
2.31k
      break;
428
15.6k
    case 0x66:  /* Operand-size override */
429
15.6k
      if (prefixGroups[2])
430
7.40k
        dbgprintf(insn, "Redundant Group 3 prefix");
431
15.6k
      prefixGroups[2] = true;
432
15.6k
      hasOpSize = true;
433
15.6k
      setPrefixPresent(insn, byte, prefixLocation);
434
15.6k
      break;
435
79
    case 0x67:  /* Address-size override */
436
79
      if (prefixGroups[3])
437
0
        dbgprintf(insn, "Redundant Group 4 prefix");
438
79
      prefixGroups[3] = true;
439
79
      hasAdSize = true;
440
79
      setPrefixPresent(insn, byte, prefixLocation);
441
79
      break;
442
505k
    default:    /* Not a prefix byte */
443
505k
      isPrefix = false;
444
505k
      break;
445
525k
    }
446
525k
447
525k
    
if (525k
isPrefix525k
)
448
19.4k
      dbgprintf(insn, "Found prefix 0x%hhx", byte);
449
525k
  }
450
506k
451
506k
  insn->vectorExtensionType = TYPE_NO_VEX_XOP;
452
506k
453
506k
  if (
byte == 0x62506k
) {
454
265
    uint8_t byte1, byte2;
455
265
456
265
    if (
consumeByte(insn, &byte1)265
) {
457
0
      dbgprintf(insn, "Couldn't read second byte of EVEX prefix");
458
0
      return -1;
459
0
    }
460
265
461
265
    
if (265
lookAtByte(insn, &byte2)265
) {
462
0
      dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
463
0
      return -1;
464
0
    }
465
265
466
265
    
if (265
(insn->mode == MODE_64BIT || 265
(byte1 & 0xc0) == 0xc02
) &&
467
265
       
((~byte1 & 0xc) == 0xc)263
&&
((byte2 & 0x4) == 0x4)263
) {
468
262
      insn->vectorExtensionType = TYPE_EVEX;
469
265
    } else {
470
3
      unconsumeByte(insn); /* unconsume byte1 */
471
3
      unconsumeByte(insn); /* unconsume byte  */
472
3
      insn->necessaryPrefixLocation = insn->readerCursor - 2;
473
3
    }
474
265
475
265
    if (
insn->vectorExtensionType == TYPE_EVEX265
) {
476
262
      insn->vectorExtensionPrefix[0] = byte;
477
262
      insn->vectorExtensionPrefix[1] = byte1;
478
262
      if (
consumeByte(insn, &insn->vectorExtensionPrefix[2])262
) {
479
0
        dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
480
0
        return -1;
481
0
      }
482
262
      
if (262
consumeByte(insn, &insn->vectorExtensionPrefix[3])262
) {
483
0
        dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix");
484
0
        return -1;
485
0
      }
486
262
487
262
      /* We simulate the REX prefix for simplicity's sake */
488
262
      
if (262
insn->mode == MODE_64BIT262
) {
489
262
        insn->rexPrefix = 0x40
490
262
                        | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3)
491
262
                        | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2)
492
262
                        | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1)
493
262
                        | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
494
262
      }
495
262
496
262
      dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
497
262
              insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
498
262
              insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]);
499
262
    }
500
506k
  } else 
if (506k
byte == 0xc4506k
) {
501
218
    uint8_t byte1;
502
218
503
218
    if (
lookAtByte(insn, &byte1)218
) {
504
0
      dbgprintf(insn, "Couldn't read second byte of VEX");
505
0
      return -1;
506
0
    }
507
218
508
218
    
if (218
insn->mode == MODE_64BIT || 218
(byte1 & 0xc0) == 0xc062
) {
509
218
      insn->vectorExtensionType = TYPE_VEX_3B;
510
218
      insn->necessaryPrefixLocation = insn->readerCursor - 1;
511
218
    } else {
512
0
      unconsumeByte(insn);
513
0
      insn->necessaryPrefixLocation = insn->readerCursor - 1;
514
0
    }
515
218
516
218
    if (
insn->vectorExtensionType == TYPE_VEX_3B218
) {
517
218
      insn->vectorExtensionPrefix[0] = byte;
518
218
      consumeByte(insn, &insn->vectorExtensionPrefix[1]);
519
218
      consumeByte(insn, &insn->vectorExtensionPrefix[2]);
520
218
521
218
      /* We simulate the REX prefix for simplicity's sake */
522
218
523
218
      if (
insn->mode == MODE_64BIT218
) {
524
156
        insn->rexPrefix = 0x40
525
156
                        | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3)
526
156
                        | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2)
527
156
                        | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1)
528
156
                        | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
529
156
      }
530
218
531
218
      dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
532
218
                insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
533
218
                insn->vectorExtensionPrefix[2]);
534
218
    }
535
506k
  } else 
if (505k
byte == 0xc5505k
) {
536
292
    uint8_t byte1;
537
292
538
292
    if (
lookAtByte(insn, &byte1)292
) {
539
0
      dbgprintf(insn, "Couldn't read second byte of VEX");
540
0
      return -1;
541
0
    }
542
292
543
292
    
if (292
insn->mode == MODE_64BIT || 292
(byte1 & 0xc0) == 0xc034
) {
544
292
      insn->vectorExtensionType = TYPE_VEX_2B;
545
292
    } else {
546
0
      unconsumeByte(insn);
547
0
    }
548
292
549
292
    if (
insn->vectorExtensionType == TYPE_VEX_2B292
) {
550
292
      insn->vectorExtensionPrefix[0] = byte;
551
292
      consumeByte(insn, &insn->vectorExtensionPrefix[1]);
552
292
553
292
      if (
insn->mode == MODE_64BIT292
) {
554
258
        insn->rexPrefix = 0x40
555
258
                        | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
556
258
      }
557
292
558
292
      switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
559
182
      default:
560
182
        break;
561
110
      case VEX_PREFIX_66:
562
110
        hasOpSize = true;
563
110
        break;
564
292
      }
565
292
566
292
      dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx",
567
292
                insn->vectorExtensionPrefix[0],
568
292
                insn->vectorExtensionPrefix[1]);
569
292
    }
570
505k
  } else 
if (505k
byte == 0x8f505k
) {
571
41
    uint8_t byte1;
572
41
573
41
    if (
lookAtByte(insn, &byte1)41
) {
574
0
      dbgprintf(insn, "Couldn't read second byte of XOP");
575
0
      return -1;
576
0
    }
577
41
578
41
    
if (41
(byte1 & 0x38) != 0x041
) { /* 0 in these 3 bits is a POP instruction. */
579
41
      insn->vectorExtensionType = TYPE_XOP;
580
41
      insn->necessaryPrefixLocation = insn->readerCursor - 1;
581
41
    } else {
582
0
      unconsumeByte(insn);
583
0
      insn->necessaryPrefixLocation = insn->readerCursor - 1;
584
0
    }
585
41
586
41
    if (
insn->vectorExtensionType == TYPE_XOP41
) {
587
41
      insn->vectorExtensionPrefix[0] = byte;
588
41
      consumeByte(insn, &insn->vectorExtensionPrefix[1]);
589
41
      consumeByte(insn, &insn->vectorExtensionPrefix[2]);
590
41
591
41
      /* We simulate the REX prefix for simplicity's sake */
592
41
593
41
      if (
insn->mode == MODE_64BIT41
) {
594
35
        insn->rexPrefix = 0x40
595
35
                        | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3)
596
35
                        | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2)
597
35
                        | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1)
598
35
                        | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
599
35
      }
600
41
601
41
      switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
602
41
      default:
603
41
        break;
604
0
      case VEX_PREFIX_66:
605
0
        hasOpSize = true;
606
0
        break;
607
41
      }
608
41
609
41
      dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
610
41
                insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
611
41
                insn->vectorExtensionPrefix[2]);
612
41
    }
613
505k
  } else {
614
505k
    if (
insn->mode == MODE_64BIT505k
) {
615
494k
      if (
(byte & 0xf0) == 0x40494k
) {
616
234k
        uint8_t opcodeByte;
617
234k
618
234k
        if (
lookAtByte(insn, &opcodeByte) || 234k
((opcodeByte & 0xf0) == 0x40)234k
) {
619
1
          dbgprintf(insn, "Redundant REX prefix");
620
1
          return -1;
621
1
        }
622
234k
623
234k
        insn->rexPrefix = byte;
624
234k
        insn->necessaryPrefixLocation = insn->readerCursor - 2;
625
234k
626
234k
        dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
627
494k
      } else {
628
259k
        unconsumeByte(insn);
629
259k
        insn->necessaryPrefixLocation = insn->readerCursor - 1;
630
259k
      }
631
505k
    } else {
632
11.1k
      unconsumeByte(insn);
633
11.1k
      insn->necessaryPrefixLocation = insn->readerCursor - 1;
634
11.1k
    }
635
506k
  }
636
506k
637
506k
  
if (506k
insn->mode == MODE_16BIT506k
) {
638
363
    insn->registerSize       = (hasOpSize ? 
4103
:
2260
);
639
363
    insn->addressSize        = (hasAdSize ? 
436
:
2327
);
640
363
    insn->displacementSize   = (hasAdSize ? 
436
:
2327
);
641
363
    insn->immediateSize      = (hasOpSize ? 
4103
:
2260
);
642
506k
  } else 
if (505k
insn->mode == MODE_32BIT505k
) {
643
10.8k
    insn->registerSize       = (hasOpSize ? 
2681
:
410.1k
);
644
10.8k
    insn->addressSize        = (hasAdSize ? 
213
:
410.8k
);
645
10.8k
    insn->displacementSize   = (hasAdSize ? 
213
:
410.8k
);
646
10.8k
    insn->immediateSize      = (hasOpSize ? 
2681
:
410.1k
);
647
505k
  } else 
if (495k
insn->mode == MODE_64BIT495k
) {
648
495k
    if (
insn->rexPrefix && 495k
wFromREX235k
(insn->rexPrefix)) {
649
190k
      insn->registerSize       = 8;
650
190k
      insn->addressSize        = (hasAdSize ? 
45
:
8190k
);
651
190k
      insn->displacementSize   = 4;
652
190k
      insn->immediateSize      = 4;
653
495k
    } else {
654
304k
      insn->registerSize       = (hasOpSize ? 
27.39k
:
4296k
);
655
304k
      insn->addressSize        = (hasAdSize ? 
425
:
8304k
);
656
304k
      insn->displacementSize   = (hasOpSize ? 
27.39k
:
4296k
);
657
304k
      insn->immediateSize      = (hasOpSize ? 
27.39k
:
4296k
);
658
304k
    }
659
505k
  }
660
506k
661
506k
  return 0;
662
506k
}
663
664
/*
665
 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
666
 *   extended or escape opcodes).
667
 *
668
 * @param insn  - The instruction whose opcode is to be read.
669
 * @return      - 0 if the opcode could be read successfully; nonzero otherwise.
670
 */
671
506k
static int readOpcode(struct InternalInstruction* insn) {
672
506k
  /* Determine the length of the primary opcode */
673
506k
674
506k
  uint8_t current;
675
506k
676
506k
  dbgprintf(insn, "readOpcode()");
677
506k
678
506k
  insn->opcodeType = ONEBYTE;
679
506k
680
506k
  if (
insn->vectorExtensionType == TYPE_EVEX506k
) {
681
262
    switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
682
2
    default:
683
2
      dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)",
684
2
                mmFromEVEX2of4(insn->vectorExtensionPrefix[1]));
685
2
      return -1;
686
74
    case VEX_LOB_0F:
687
74
      insn->opcodeType = TWOBYTE;
688
74
      return consumeByte(insn, &insn->opcode);
689
150
    case VEX_LOB_0F38:
690
150
      insn->opcodeType = THREEBYTE_38;
691
150
      return consumeByte(insn, &insn->opcode);
692
36
    case VEX_LOB_0F3A:
693
36
      insn->opcodeType = THREEBYTE_3A;
694
36
      return consumeByte(insn, &insn->opcode);
695
506k
    }
696
506k
  } else 
if (506k
insn->vectorExtensionType == TYPE_VEX_3B506k
) {
697
218
    switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
698
0
    default:
699
0
      dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
700
0
                mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
701
0
      return -1;
702
21
    case VEX_LOB_0F:
703
21
      insn->opcodeType = TWOBYTE;
704
21
      return consumeByte(insn, &insn->opcode);
705
117
    case VEX_LOB_0F38:
706
117
      insn->opcodeType = THREEBYTE_38;
707
117
      return consumeByte(insn, &insn->opcode);
708
80
    case VEX_LOB_0F3A:
709
80
      insn->opcodeType = THREEBYTE_3A;
710
80
      return consumeByte(insn, &insn->opcode);
711
506k
    }
712
505k
  } else 
if (505k
insn->vectorExtensionType == TYPE_VEX_2B505k
) {
713
292
    insn->opcodeType = TWOBYTE;
714
292
    return consumeByte(insn, &insn->opcode);
715
505k
  } else 
if (505k
insn->vectorExtensionType == TYPE_XOP505k
) {
716
41
    switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
717
2
    default:
718
2
      dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
719
2
                mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
720
2
      return -1;
721
16
    case XOP_MAP_SELECT_8:
722
16
      insn->opcodeType = XOP8_MAP;
723
16
      return consumeByte(insn, &insn->opcode);
724
12
    case XOP_MAP_SELECT_9:
725
12
      insn->opcodeType = XOP9_MAP;
726
12
      return consumeByte(insn, &insn->opcode);
727
11
    case XOP_MAP_SELECT_A:
728
11
      insn->opcodeType = XOPA_MAP;
729
11
      return consumeByte(insn, &insn->opcode);
730
505k
    }
731
505k
  }
732
505k
733
505k
  
if (505k
consumeByte(insn, &current)505k
)
734
0
    return -1;
735
505k
736
505k
  
if (505k
current == 0x0f505k
) {
737
37.5k
    dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
738
37.5k
739
37.5k
    if (consumeByte(insn, &current))
740
0
      return -1;
741
37.5k
742
37.5k
    
if (37.5k
current == 0x3837.5k
) {
743
49
      dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
744
49
745
49
      if (consumeByte(insn, &current))
746
0
        return -1;
747
49
748
49
      insn->opcodeType = THREEBYTE_38;
749
37.5k
    } else 
if (37.5k
current == 0x3a37.5k
) {
750
36
      dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
751
36
752
36
      if (consumeByte(insn, &current))
753
0
        return -1;
754
36
755
36
      insn->opcodeType = THREEBYTE_3A;
756
37.5k
    } else {
757
37.4k
      dbgprintf(insn, "Didn't find a three-byte escape prefix");
758
37.4k
759
37.4k
      insn->opcodeType = TWOBYTE;
760
37.4k
    }
761
37.5k
  }
762
505k
763
505k
  /*
764
505k
   * At this point we have consumed the full opcode.
765
505k
   * Anything we consume from here on must be unconsumed.
766
505k
   */
767
505k
768
505k
  insn->opcode = current;
769
505k
770
505k
  return 0;
771
506k
}
772
773
static int readModRM(struct InternalInstruction* insn);
774
775
/*
776
 * getIDWithAttrMask - Determines the ID of an instruction, consuming
777
 *   the ModR/M byte as appropriate for extended and escape opcodes,
778
 *   and using a supplied attribute mask.
779
 *
780
 * @param instructionID - A pointer whose target is filled in with the ID of the
781
 *                        instruction.
782
 * @param insn          - The instruction whose ID is to be determined.
783
 * @param attrMask      - The attribute mask to search.
784
 * @return              - 0 if the ModR/M could be read when needed or was not
785
 *                        needed; nonzero otherwise.
786
 */
787
static int getIDWithAttrMask(uint16_t* instructionID,
788
                             struct InternalInstruction* insn,
789
509k
                             uint16_t attrMask) {
790
509k
  bool hasModRMExtension;
791
509k
792
509k
  InstructionContext instructionClass = contextForAttrs(attrMask);
793
509k
794
509k
  hasModRMExtension = modRMRequired(insn->opcodeType,
795
509k
                                    instructionClass,
796
509k
                                    insn->opcode);
797
509k
798
509k
  if (
hasModRMExtension509k
) {
799
320k
    if (readModRM(insn))
800
9
      return -1;
801
320k
802
320k
    *instructionID = decode(insn->opcodeType,
803
320k
                            instructionClass,
804
320k
                            insn->opcode,
805
320k
                            insn->modRM);
806
509k
  } else {
807
188k
    *instructionID = decode(insn->opcodeType,
808
188k
                            instructionClass,
809
188k
                            insn->opcode,
810
188k
                            0);
811
188k
  }
812
509k
813
509k
  return 0;
814
509k
}
815
816
/*
817
 * is16BitEquivalent - Determines whether two instruction names refer to
818
 * equivalent instructions but one is 16-bit whereas the other is not.
819
 *
820
 * @param orig  - The instruction that is not 16-bit
821
 * @param equiv - The instruction that is 16-bit
822
 */
823
2.56k
static bool is16BitEquivalent(const char *orig, const char *equiv) {
824
2.56k
  off_t i;
825
2.56k
826
13.4k
  for (i = 0;; 
i++13.4k
) {
827
16.0k
    if (
orig[i] == '\0' && 16.0k
equiv[i] == '\0'2.53k
)
828
2.53k
      return true;
829
13.5k
    
if (13.5k
orig[i] == '\0' || 13.5k
equiv[i] == '\0'13.5k
)
830
0
      return false;
831
13.5k
    
if (13.5k
orig[i] != equiv[i]13.5k
) {
832
2.63k
      if (
(orig[i] == 'Q' || 2.63k
orig[i] == 'L'2.63k
) &&
equiv[i] == 'W'2.17k
)
833
2.17k
        continue;
834
462
      
if (462
(orig[i] == '6' || 462
orig[i] == '3'460
) &&
equiv[i] == '1'219
)
835
217
        continue;
836
245
      
if (245
(orig[i] == '4' || 245
orig[i] == '2'226
) &&
equiv[i] == '6'236
)
837
217
        continue;
838
28
      return false;
839
28
    }
840
16.0k
  }
841
2.56k
}
842
843
/*
844
 * is64Bit - Determines whether this instruction is a 64-bit instruction.
845
 *
846
 * @param name - The instruction that is not 16-bit
847
 */
848
6
static bool is64Bit(const char *name) {
849
6
  off_t i;
850
6
851
34
  for (i = 0;; 
++i34
) {
852
40
    if (name[i] == '\0')
853
1
      return false;
854
39
    
if (39
name[i] == '6' && 39
name[i+1] == '4'5
)
855
5
      return true;
856
40
  }
857
6
}
858
859
/*
860
 * getID - Determines the ID of an instruction, consuming the ModR/M byte as
861
 *   appropriate for extended and escape opcodes.  Determines the attributes and
862
 *   context for the instruction before doing so.
863
 *
864
 * @param insn  - The instruction whose ID is to be determined.
865
 * @return      - 0 if the ModR/M could be read when needed or was not needed;
866
 *                nonzero otherwise.
867
 */
868
506k
static int getID(struct InternalInstruction* insn, const void *miiArg) {
869
506k
  uint16_t attrMask;
870
506k
  uint16_t instructionID;
871
506k
872
506k
  dbgprintf(insn, "getID()");
873
506k
874
506k
  attrMask = ATTR_NONE;
875
506k
876
506k
  if (insn->mode == MODE_64BIT)
877
495k
    attrMask |= ATTR_64BIT;
878
506k
879
506k
  if (
insn->vectorExtensionType != TYPE_NO_VEX_XOP506k
) {
880
809
    attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? 
ATTR_EVEX260
:
ATTR_VEX549
;
881
809
882
809
    if (
insn->vectorExtensionType == TYPE_EVEX809
) {
883
260
      switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
884
198
      case VEX_PREFIX_66:
885
198
        attrMask |= ATTR_OPSIZE;
886
198
        break;
887
30
      case VEX_PREFIX_F3:
888
30
        attrMask |= ATTR_XS;
889
30
        break;
890
12
      case VEX_PREFIX_F2:
891
12
        attrMask |= ATTR_XD;
892
12
        break;
893
260
      }
894
260
895
260
      
if (260
zFromEVEX4of4260
(insn->vectorExtensionPrefix[3]))
896
9
        attrMask |= ATTR_EVEXKZ;
897
260
      if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
898
15
        attrMask |= ATTR_EVEXB;
899
260
      if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
900
123
        attrMask |= ATTR_EVEXK;
901
260
      if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
902
57
        attrMask |= ATTR_EVEXL;
903
260
      if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
904
116
        attrMask |= ATTR_EVEXL2;
905
809
    } else 
if (549
insn->vectorExtensionType == TYPE_VEX_3B549
) {
906
218
      switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
907
139
      case VEX_PREFIX_66:
908
139
        attrMask |= ATTR_OPSIZE;
909
139
        break;
910
12
      case VEX_PREFIX_F3:
911
12
        attrMask |= ATTR_XS;
912
12
        break;
913
35
      case VEX_PREFIX_F2:
914
35
        attrMask |= ATTR_XD;
915
35
        break;
916
218
      }
917
218
918
218
      
if (218
lFromVEX3of3218
(insn->vectorExtensionPrefix[2]))
919
59
        attrMask |= ATTR_VEXL;
920
549
    } else 
if (331
insn->vectorExtensionType == TYPE_VEX_2B331
) {
921
292
      switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
922
110
      case VEX_PREFIX_66:
923
110
        attrMask |= ATTR_OPSIZE;
924
110
        break;
925
27
      case VEX_PREFIX_F3:
926
27
        attrMask |= ATTR_XS;
927
27
        break;
928
81
      case VEX_PREFIX_F2:
929
81
        attrMask |= ATTR_XD;
930
81
        break;
931
292
      }
932
292
933
292
      
if (292
lFromVEX2of2292
(insn->vectorExtensionPrefix[1]))
934
99
        attrMask |= ATTR_VEXL;
935
331
    } else 
if (39
insn->vectorExtensionType == TYPE_XOP39
) {
936
39
      switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
937
0
      case VEX_PREFIX_66:
938
0
        attrMask |= ATTR_OPSIZE;
939
0
        break;
940
0
      case VEX_PREFIX_F3:
941
0
        attrMask |= ATTR_XS;
942
0
        break;
943
0
      case VEX_PREFIX_F2:
944
0
        attrMask |= ATTR_XD;
945
0
        break;
946
39
      }
947
39
948
39
      
if (39
lFromXOP3of339
(insn->vectorExtensionPrefix[2]))
949
5
        attrMask |= ATTR_VEXL;
950
0
    } else {
951
0
      return -1;
952
0
    }
953
505k
  } else {
954
505k
    if (
insn->mode != MODE_16BIT && 505k
isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation)505k
)
955
5.97k
      attrMask |= ATTR_OPSIZE;
956
499k
    else 
if (499k
isPrefixAtLocation(insn, 0x67, insn->necessaryPrefixLocation)499k
)
957
50
      attrMask |= ATTR_ADSIZE;
958
499k
    else 
if (499k
isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation)499k
)
959
825
      attrMask |= ATTR_XS;
960
498k
    else 
if (498k
isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation)498k
)
961
502
      attrMask |= ATTR_XD;
962
505k
  }
963
506k
964
506k
  
if (506k
insn->rexPrefix & 0x08506k
)
965
190k
    attrMask |= ATTR_REXW;
966
506k
967
506k
  /*
968
506k
   * JCXZ/JECXZ need special handling for 16-bit mode because the meaning
969
506k
   * of the AdSize prefix is inverted w.r.t. 32-bit mode.
970
506k
   */
971
506k
  if (
insn->mode == MODE_16BIT && 506k
insn->opcodeType == ONEBYTE363
&&
972
265
      insn->opcode == 0xE3)
973
2
    attrMask ^= ATTR_ADSIZE;
974
506k
975
506k
  /*
976
506k
   * In 64-bit mode all f64 superscripted opcodes ignore opcode size prefix
977
506k
   * CALL/JMP/JCC instructions need to ignore 0x66 and consume 4 bytes
978
506k
   */
979
506k
980
506k
  if (insn->mode == MODE_64BIT &&
981
506k
      
isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation)495k
) {
982
5.73k
    switch (insn->opcode) {
983
5
    case 0xE8:
984
5
    case 0xE9:
985
5
      // Take care of psubsb and other mmx instructions.
986
5
      if (
insn->opcodeType == ONEBYTE5
) {
987
4
        attrMask ^= ATTR_OPSIZE;
988
4
        insn->immediateSize = 4;
989
4
        insn->displacementSize = 4;
990
4
      }
991
5
      break;
992
1.62k
    case 0x82:
993
1.62k
    case 0x83:
994
1.62k
    case 0x84:
995
1.62k
    case 0x85:
996
1.62k
    case 0x86:
997
1.62k
    case 0x87:
998
1.62k
    case 0x88:
999
1.62k
    case 0x89:
1000
1.62k
    case 0x8A:
1001
1.62k
    case 0x8B:
1002
1.62k
    case 0x8C:
1003
1.62k
    case 0x8D:
1004
1.62k
    case 0x8E:
1005
1.62k
    case 0x8F:
1006
1.62k
      // Take care of lea and three byte ops.
1007
1.62k
      if (
insn->opcodeType == TWOBYTE1.62k
) {
1008
14
        attrMask ^= ATTR_OPSIZE;
1009
14
        insn->immediateSize = 4;
1010
14
        insn->displacementSize = 4;
1011
14
      }
1012
5
      break;
1013
506k
    }
1014
506k
  }
1015
506k
1016
506k
  
if (506k
getIDWithAttrMask(&instructionID, insn, attrMask)506k
)
1017
9
    return -1;
1018
506k
1019
506k
  /* The following clauses compensate for limitations of the tables. */
1020
506k
1021
506k
  
if (506k
insn->mode != MODE_64BIT &&
1022
506k
      
insn->vectorExtensionType != TYPE_NO_VEX_XOP11.2k
) {
1023
102
    /*
1024
102
     * The tables can't distinquish between cases where the W-bit is used to
1025
102
     * select register size and cases where its a required part of the opcode.
1026
102
     */
1027
102
    if ((insn->vectorExtensionType == TYPE_EVEX &&
1028
0
         wFromEVEX3of4(insn->vectorExtensionPrefix[2])) ||
1029
102
        (insn->vectorExtensionType == TYPE_VEX_3B &&
1030
62
         wFromVEX3of3(insn->vectorExtensionPrefix[2])) ||
1031
96
        (insn->vectorExtensionType == TYPE_XOP &&
1032
102
         
wFromXOP3of36
(insn->vectorExtensionPrefix[2]))) {
1033
6
1034
6
      uint16_t instructionIDWithREXW;
1035
6
      if (getIDWithAttrMask(&instructionIDWithREXW,
1036
6
                            insn, attrMask | ATTR_REXW)) {
1037
0
        insn->instructionID = instructionID;
1038
0
        insn->spec = specifierForUID(instructionID);
1039
0
        return 0;
1040
0
      }
1041
6
1042
6
      auto SpecName = GetInstrName(instructionIDWithREXW, miiArg);
1043
6
      // If not a 64-bit instruction. Switch the opcode.
1044
6
      if (
!is64Bit(SpecName.data())6
) {
1045
1
        insn->instructionID = instructionIDWithREXW;
1046
1
        insn->spec = specifierForUID(instructionIDWithREXW);
1047
1
        return 0;
1048
1
      }
1049
506k
    }
1050
102
  }
1051
506k
1052
506k
  /*
1053
506k
   * Absolute moves need special handling.
1054
506k
   * -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are
1055
506k
   *  inverted w.r.t.
1056
506k
   * -For 32-bit mode we need to ensure the ADSIZE prefix is observed in
1057
506k
   *  any position.
1058
506k
   */
1059
506k
  
if (506k
insn->opcodeType == ONEBYTE && 506k
((insn->opcode & 0xFC) == 0xA0)467k
) {
1060
137
    /* Make sure we observed the prefixes in any position. */
1061
137
    if (insn->prefixPresent[0x67])
1062
32
      attrMask |= ATTR_ADSIZE;
1063
137
    if (insn->prefixPresent[0x66])
1064
35
      attrMask |= ATTR_OPSIZE;
1065
137
1066
137
    /* In 16-bit, invert the attributes. */
1067
137
    if (insn->mode == MODE_16BIT)
1068
19
      attrMask ^= ATTR_ADSIZE | ATTR_OPSIZE;
1069
137
1070
137
    if (getIDWithAttrMask(&instructionID, insn, attrMask))
1071
0
      return -1;
1072
137
1073
137
    insn->instructionID = instructionID;
1074
137
    insn->spec = specifierForUID(instructionID);
1075
137
    return 0;
1076
137
  }
1077
506k
1078
506k
  
if (506k
(insn->mode == MODE_16BIT || 506k
insn->prefixPresent[0x66]505k
) &&
1079
506k
      
!(attrMask & ATTR_OPSIZE)8.49k
) {
1080
2.56k
    /*
1081
2.56k
     * The instruction tables make no distinction between instructions that
1082
2.56k
     * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
1083
2.56k
     * particular spot (i.e., many MMX operations).  In general we're
1084
2.56k
     * conservative, but in the specific case where OpSize is present but not
1085
2.56k
     * in the right place we check if there's a 16-bit operation.
1086
2.56k
     */
1087
2.56k
1088
2.56k
    const struct InstructionSpecifier *spec;
1089
2.56k
    uint16_t instructionIDWithOpsize;
1090
2.56k
    llvm::StringRef specName, specWithOpSizeName;
1091
2.56k
1092
2.56k
    spec = specifierForUID(instructionID);
1093
2.56k
1094
2.56k
    if (getIDWithAttrMask(&instructionIDWithOpsize,
1095
2.56k
                          insn,
1096
2.56k
                          attrMask | ATTR_OPSIZE)) {
1097
0
      /*
1098
0
       * ModRM required with OpSize but not present; give up and return version
1099
0
       * without OpSize set
1100
0
       */
1101
0
1102
0
      insn->instructionID = instructionID;
1103
0
      insn->spec = spec;
1104
0
      return 0;
1105
0
    }
1106
2.56k
1107
2.56k
    specName = GetInstrName(instructionID, miiArg);
1108
2.56k
    specWithOpSizeName = GetInstrName(instructionIDWithOpsize, miiArg);
1109
2.56k
1110
2.56k
    if (is16BitEquivalent(specName.data(), specWithOpSizeName.data()) &&
1111
2.56k
        
(insn->mode == MODE_16BIT) ^ insn->prefixPresent[0x66]2.53k
) {
1112
2.44k
      insn->instructionID = instructionIDWithOpsize;
1113
2.44k
      insn->spec = specifierForUID(instructionIDWithOpsize);
1114
2.56k
    } else {
1115
122
      insn->instructionID = instructionID;
1116
122
      insn->spec = spec;
1117
122
    }
1118
2.56k
    return 0;
1119
2.56k
  }
1120
503k
1121
503k
  
if (503k
insn->opcodeType == ONEBYTE && 503k
insn->opcode == 0x90467k
&&
1122
503k
      
insn->rexPrefix & 0x015.59k
) {
1123
4
    /*
1124
4
     * NOOP shouldn't decode as NOOP if REX.b is set. Instead
1125
4
     * it should decode as XCHG %r8, %eax.
1126
4
     */
1127
4
1128
4
    const struct InstructionSpecifier *spec;
1129
4
    uint16_t instructionIDWithNewOpcode;
1130
4
    const struct InstructionSpecifier *specWithNewOpcode;
1131
4
1132
4
    spec = specifierForUID(instructionID);
1133
4
1134
4
    /* Borrow opcode from one of the other XCHGar opcodes */
1135
4
    insn->opcode = 0x91;
1136
4
1137
4
    if (getIDWithAttrMask(&instructionIDWithNewOpcode,
1138
4
                          insn,
1139
4
                          attrMask)) {
1140
0
      insn->opcode = 0x90;
1141
0
1142
0
      insn->instructionID = instructionID;
1143
0
      insn->spec = spec;
1144
0
      return 0;
1145
0
    }
1146
4
1147
4
    specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
1148
4
1149
4
    /* Change back */
1150
4
    insn->opcode = 0x90;
1151
4
1152
4
    insn->instructionID = instructionIDWithNewOpcode;
1153
4
    insn->spec = specWithNewOpcode;
1154
4
1155
4
    return 0;
1156
4
  }
1157
503k
1158
503k
  insn->instructionID = instructionID;
1159
503k
  insn->spec = specifierForUID(insn->instructionID);
1160
503k
1161
503k
  return 0;
1162
503k
}
1163
1164
/*
1165
 * readSIB - Consumes the SIB byte to determine addressing information for an
1166
 *   instruction.
1167
 *
1168
 * @param insn  - The instruction whose SIB byte is to be read.
1169
 * @return      - 0 if the SIB byte was successfully read; nonzero otherwise.
1170
 */
1171
46.4k
static int readSIB(struct InternalInstruction* insn) {
1172
46.4k
  SIBIndex sibIndexBase = SIB_INDEX_NONE;
1173
46.4k
  SIBBase sibBaseBase = SIB_BASE_NONE;
1174
46.4k
  uint8_t index, base;
1175
46.4k
1176
46.4k
  dbgprintf(insn, "readSIB()");
1177
46.4k
1178
46.4k
  if (insn->consumedSIB)
1179
0
    return 0;
1180
46.4k
1181
46.4k
  insn->consumedSIB = true;
1182
46.4k
1183
46.4k
  switch (insn->addressSize) {
1184
0
  case 2:
1185
0
    dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
1186
0
    return -1;
1187
722
  case 4:
1188
722
    sibIndexBase = SIB_INDEX_EAX;
1189
722
    sibBaseBase = SIB_BASE_EAX;
1190
722
    break;
1191
45.7k
  case 8:
1192
45.7k
    sibIndexBase = SIB_INDEX_RAX;
1193
45.7k
    sibBaseBase = SIB_BASE_RAX;
1194
45.7k
    break;
1195
46.4k
  }
1196
46.4k
1197
46.4k
  
if (46.4k
consumeByte(insn, &insn->sib)46.4k
)
1198
1
    return -1;
1199
46.4k
1200
46.4k
  
index = 46.4k
indexFromSIB46.4k
(insn->sib) | (
xFromREX46.4k
(insn->rexPrefix) << 3);
1201
46.4k
1202
46.4k
  // FIXME: The fifth bit (bit index 4) is only to be used for instructions
1203
46.4k
  // that understand VSIB indexing. ORing the bit in here is mildy dangerous
1204
46.4k
  // because performing math on an 'enum SIBIndex' can produce garbage.
1205
46.4k
  // Excluding the "none" value, it should cover 6 spaces of register names:
1206
46.4k
  //   - 16 possibilities for 16-bit GPR starting at SIB_INDEX_BX_SI
1207
46.4k
  //   - 16 possibilities for 32-bit GPR starting at SIB_INDEX_EAX
1208
46.4k
  //   - 16 possibilities for 64-bit GPR starting at SIB_INDEX_RAX
1209
46.4k
  //   - 32 possibilities for each of XMM, YMM, ZMM registers
1210
46.4k
  // When sibIndexBase gets assigned SIB_INDEX_RAX as it does in 64-bit mode,
1211
46.4k
  // summing in a fully decoded index between 0 and 31 can end up with a value
1212
46.4k
  // that looks like something in the low half of the XMM range.
1213
46.4k
  // translateRMMemory() tries to reverse the damage, with only partial success,
1214
46.4k
  // as evidenced by known bugs in "test/MC/Disassembler/X86/x86-64.txt"
1215
46.4k
  if (insn->vectorExtensionType == TYPE_EVEX)
1216
115
    
index |= 115
v2FromEVEX4of4115
(insn->vectorExtensionPrefix[3]) << 4;
1217
46.4k
1218
46.4k
  if (
index == 0x446.4k
) {
1219
32.8k
    insn->sibIndex = SIB_INDEX_NONE;
1220
46.4k
  } else {
1221
13.6k
    insn->sibIndex = (SIBIndex)(sibIndexBase + index);
1222
13.6k
  }
1223
46.4k
1224
46.4k
  insn->sibScale = 1 << scaleFromSIB(insn->sib);
1225
46.4k
1226
46.4k
  base = 
baseFromSIB46.4k
(insn->sib) | (
bFromREX46.4k
(insn->rexPrefix) << 3);
1227
46.4k
1228
46.4k
  switch (base) {
1229
1.03k
  case 0x5:
1230
1.03k
  case 0xd:
1231
1.03k
    switch (modFromModRM(insn->modRM)) {
1232
550
    case 0x0:
1233
550
      insn->eaDisplacement = EA_DISP_32;
1234
550
      insn->sibBase = SIB_BASE_NONE;
1235
550
      break;
1236
323
    case 0x1:
1237
323
      insn->eaDisplacement = EA_DISP_8;
1238
323
      insn->sibBase = (SIBBase)(sibBaseBase + base);
1239
323
      break;
1240
160
    case 0x2:
1241
160
      insn->eaDisplacement = EA_DISP_32;
1242
160
      insn->sibBase = (SIBBase)(sibBaseBase + base);
1243
160
      break;
1244
0
    case 0x3:
1245
0
      debug("Cannot have Mod = 0b11 and a SIB byte");
1246
0
      return -1;
1247
1.03k
    }
1248
1.03k
    break;
1249
45.4k
  default:
1250
45.4k
    insn->sibBase = (SIBBase)(sibBaseBase + base);
1251
45.4k
    break;
1252
46.4k
  }
1253
46.4k
1254
46.4k
  return 0;
1255
46.4k
}
1256
1257
/*
1258
 * readDisplacement - Consumes the displacement of an instruction.
1259
 *
1260
 * @param insn  - The instruction whose displacement is to be read.
1261
 * @return      - 0 if the displacement byte was successfully read; nonzero
1262
 *                otherwise.
1263
 */
1264
141k
static int readDisplacement(struct InternalInstruction* insn) {
1265
141k
  int8_t d8;
1266
141k
  int16_t d16;
1267
141k
  int32_t d32;
1268
141k
1269
141k
  dbgprintf(insn, "readDisplacement()");
1270
141k
1271
141k
  if (insn->consumedDisplacement)
1272
0
    return 0;
1273
141k
1274
141k
  insn->consumedDisplacement = true;
1275
141k
  insn->displacementOffset = insn->readerCursor - insn->startLocation;
1276
141k
1277
141k
  switch (insn->eaDisplacement) {
1278
8.19k
  case EA_DISP_NONE:
1279
8.19k
    insn->consumedDisplacement = false;
1280
8.19k
    break;
1281
74.4k
  case EA_DISP_8:
1282
74.4k
    if (consumeInt8(insn, &d8))
1283
0
      return -1;
1284
74.4k
    insn->displacement = d8;
1285
74.4k
    break;
1286
14
  case EA_DISP_16:
1287
14
    if (consumeInt16(insn, &d16))
1288
0
      return -1;
1289
14
    insn->displacement = d16;
1290
14
    break;
1291
58.8k
  case EA_DISP_32:
1292
58.8k
    if (consumeInt32(insn, &d32))
1293
1
      return -1;
1294
58.8k
    insn->displacement = d32;
1295
58.8k
    break;
1296
141k
  }
1297
141k
1298
141k
  insn->consumedDisplacement = true;
1299
141k
  return 0;
1300
141k
}
1301
1302
/*
1303
 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1304
 *   displacement) for an instruction and interprets it.
1305
 *
1306
 * @param insn  - The instruction whose addressing information is to be read.
1307
 * @return      - 0 if the information was successfully read; nonzero otherwise.
1308
 */
1309
869k
static int readModRM(struct InternalInstruction* insn) {
1310
869k
  uint8_t mod, rm, reg;
1311
869k
1312
869k
  dbgprintf(insn, "readModRM()");
1313
869k
1314
869k
  if (insn->consumedModRM)
1315
551k
    return 0;
1316
317k
1317
317k
  
if (317k
consumeByte(insn, &insn->modRM)317k
)
1318
7
    return -1;
1319
317k
  insn->consumedModRM = true;
1320
317k
1321
317k
  mod     = modFromModRM(insn->modRM);
1322
317k
  rm      = rmFromModRM(insn->modRM);
1323
317k
  reg     = regFromModRM(insn->modRM);
1324
317k
1325
317k
  /*
1326
317k
   * This goes by insn->registerSize to pick the correct register, which messes
1327
317k
   * up if we're using (say) XMM or 8-bit register operands.  That gets fixed in
1328
317k
   * fixupReg().
1329
317k
   */
1330
317k
  switch (insn->registerSize) {
1331
7.79k
  case 2:
1332
7.79k
    insn->regBase = MODRM_REG_AX;
1333
7.79k
    insn->eaRegBase = EA_REG_AX;
1334
7.79k
    break;
1335
121k
  case 4:
1336
121k
    insn->regBase = MODRM_REG_EAX;
1337
121k
    insn->eaRegBase = EA_REG_EAX;
1338
121k
    break;
1339
188k
  case 8:
1340
188k
    insn->regBase = MODRM_REG_RAX;
1341
188k
    insn->eaRegBase = EA_REG_RAX;
1342
188k
    break;
1343
317k
  }
1344
317k
1345
317k
  
reg |= 317k
rFromREX317k
(insn->rexPrefix) << 3;
1346
317k
  rm  |= bFromREX(insn->rexPrefix) << 3;
1347
317k
  if (
insn->vectorExtensionType == TYPE_EVEX317k
) {
1348
260
    reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1349
260
    rm  |=  xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1350
260
  }
1351
317k
1352
317k
  insn->reg = (Reg)(insn->regBase + reg);
1353
317k
1354
317k
  switch (insn->addressSize) {
1355
116
  case 2:
1356
116
    insn->eaBaseBase = EA_BASE_BX_SI;
1357
116
1358
116
    switch (mod) {
1359
14
    case 0x0:
1360
14
      if (
rm == 0x614
) {
1361
14
        insn->eaBase = EA_BASE_NONE;
1362
14
        insn->eaDisplacement = EA_DISP_16;
1363
14
        if (readDisplacement(insn))
1364
0
          return -1;
1365
0
      } else {
1366
0
        insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1367
0
        insn->eaDisplacement = EA_DISP_NONE;
1368
0
      }
1369
14
      break;
1370
2
    case 0x1:
1371
2
      insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1372
2
      insn->eaDisplacement = EA_DISP_8;
1373
2
      insn->displacementSize = 1;
1374
2
      if (readDisplacement(insn))
1375
0
        return -1;
1376
2
      break;
1377
0
    case 0x2:
1378
0
      insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1379
0
      insn->eaDisplacement = EA_DISP_16;
1380
0
      if (readDisplacement(insn))
1381
0
        return -1;
1382
0
      break;
1383
100
    case 0x3:
1384
100
      insn->eaBase = (EABase)(insn->eaRegBase + rm);
1385
100
      if (readDisplacement(insn))
1386
0
        return -1;
1387
100
      break;
1388
116
    }
1389
116
    break;
1390
317k
  case 4:
1391
317k
  case 8:
1392
317k
    insn->eaBaseBase = (insn->addressSize == 4 ? 
EA_BASE_EAX1.74k
:
EA_BASE_RAX315k
);
1393
317k
1394
317k
    switch (mod) {
1395
55.9k
    case 0x0:
1396
55.9k
      insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1397
55.9k
      // In determining whether RIP-relative mode is used (rm=5),
1398
55.9k
      // or whether a SIB byte is present (rm=4),
1399
55.9k
      // the extension bits (REX.b and EVEX.x) are ignored.
1400
55.9k
      switch (rm & 7) {
1401
8.64k
      case 0x4: // SIB byte is present
1402
8.64k
        insn->eaBase = (insn->addressSize == 4 ?
1403
8.64k
                        
EA_BASE_sib31
:
EA_BASE_sib648.61k
);
1404
8.64k
        if (
readSIB(insn) || 8.64k
readDisplacement(insn)8.64k
)
1405
1
          return -1;
1406
8.64k
        break;
1407
29.3k
      case 0x5: // RIP-relative
1408
29.3k
        insn->eaBase = EA_BASE_NONE;
1409
29.3k
        insn->eaDisplacement = EA_DISP_32;
1410
29.3k
        if (readDisplacement(insn))
1411
0
          return -1;
1412
29.3k
        break;
1413
17.9k
      default:
1414
17.9k
        insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1415
17.9k
        break;
1416
55.9k
      }
1417
55.9k
      break;
1418
74.4k
    case 0x1:
1419
74.4k
      insn->displacementSize = 1;
1420
74.4k
      /* FALLTHROUGH */
1421
103k
    case 0x2:
1422
103k
      insn->eaDisplacement = (mod == 0x1 ? 
EA_DISP_874.4k
:
EA_DISP_3228.8k
);
1423
103k
      switch (rm & 7) {
1424
37.8k
      case 0x4: // SIB byte is present
1425
37.8k
        insn->eaBase = EA_BASE_sib;
1426
37.8k
        if (
readSIB(insn) || 37.8k
readDisplacement(insn)37.8k
)
1427
0
          return -1;
1428
37.8k
        break;
1429
65.5k
      default:
1430
65.5k
        insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1431
65.5k
        if (readDisplacement(insn))
1432
1
          return -1;
1433
65.5k
        break;
1434
103k
      }
1435
103k
      break;
1436
158k
    case 0x3:
1437
158k
      insn->eaDisplacement = EA_DISP_NONE;
1438
158k
      insn->eaBase = (EABase)(insn->eaRegBase + rm);
1439
158k
      break;
1440
317k
    }
1441
317k
    break;
1442
317k
  } /* switch (insn->addressSize) */
1443
317k
1444
317k
  return 0;
1445
317k
}
1446
1447
#define GENERIC_FIXUP_FUNC(name, base, prefix)            \
1448
  static uint16_t name(struct InternalInstruction *insn,  \
1449
                       OperandType type,                  \
1450
                       uint8_t index,                     \
1451
390k
                       uint8_t *valid) {                  \
1452
390k
    *valid = 1;                                           \
1453
390k
    switch (type) {                                       \
1454
0
    default:                                              \
1455
0
      debug("Unhandled register type");                   \
1456
0
      *valid = 0;                                         \
1457
0
      return 0;                                           \
1458
102k
    case TYPE_Rv:                                         \
1459
102k
      return base + index;                                \
1460
28.7k
    case TYPE_R8:                                         \
1461
28.7k
      if (insn->rexPrefix &&                              \
1462
28.7k
         
index >= 48.19k
&&
index <= 76.70k
) { \
1463
1.15k
        return prefix##_SPL + (index - 4);                \
1464
28.7k
      } else {                                            \
1465
27.5k
        return prefix##_AL + index;                       \
1466
27.5k
      }                                                   \
1467
438
    case TYPE_R16:                                        \
1468
438
      return prefix##_AX + index;                         \
1469
938
    case TYPE_R32:                                        \
1470
938
      return prefix##_EAX + index;                        \
1471
247k
    case TYPE_R64:                                        \
1472
247k
      return prefix##_RAX + index;                        \
1473
196
    case TYPE_ZMM:                                        \
1474
196
      return prefix##_ZMM0 + index;                       \
1475
316
    case TYPE_YMM:                                        \
1476
316
      return prefix##_YMM0 + index;                       \
1477
9.23k
    case TYPE_XMM:                                        \
1478
9.23k
      return prefix##_XMM0 + index;                       \
1479
96
    case TYPE_VK:                                         \
1480
96
      if (index > 7)                                      \
1481
0
        *valid = 0;                                       \
1482
96
      return prefix##_K0 + index;                         \
1483
19
    case TYPE_MM64:                                       \
1484
19
      return prefix##_MM0 + (index & 0x7);                \
1485
9
    case TYPE_SEGMENTREG:                                 \
1486
9
      if (index > 5)                                      \
1487
2
        *valid = 0;                                       \
1488
9
      return prefix##_ES + index;                         \
1489
10
    case TYPE_DEBUGREG:                                   \
1490
10
      return prefix##_DR0 + index;                        \
1491
8
    case TYPE_CONTROLREG:                                 \
1492
8
      return prefix##_CR0 + index;                        \
1493
10
    case TYPE_BNDR:                                       \
1494
10
      if (index > 3)                                      \
1495
0
        *valid = 0;                                       \
1496
28.7k
      return prefix##_BND0 + index;                       \
1497
390k
    }                                                     \
1498
390k
  }
X86DisassemblerDecoder.cpp:fixupRegValue(llvm::X86Disassembler::InternalInstruction*, llvm::X86Disassembler::OperandType, unsigned char, unsigned char*)
Line
Count
Source
1451
234k
                       uint8_t *valid) {                  \
1452
234k
    *valid = 1;                                           \
1453
234k
    switch (type) {                                       \
1454
0
    default:                                              \
1455
0
      debug("Unhandled register type");                   \
1456
0
      *valid = 0;                                         \
1457
0
      return 0;                                           \
1458
57.6k
    case TYPE_Rv:                                         \
1459
57.6k
      return base + index;                                \
1460
14.9k
    case TYPE_R8:                                         \
1461
14.9k
      if (insn->rexPrefix &&                              \
1462
14.9k
         
index >= 44.40k
&&
index <= 73.19k
) { \
1463
602
        return prefix##_SPL + (index - 4);                \
1464
14.9k
      } else {                                            \
1465
14.2k
        return prefix##_AL + index;                       \
1466
14.2k
      }                                                   \
1467
2
    case TYPE_R16:                                        \
1468
2
      return prefix##_AX + index;                         \
1469
179
    case TYPE_R32:                                        \
1470
179
      return prefix##_EAX + index;                        \
1471
153k
    case TYPE_R64:                                        \
1472
153k
      return prefix##_RAX + index;                        \
1473
145
    case TYPE_ZMM:                                        \
1474
145
      return prefix##_ZMM0 + index;                       \
1475
232
    case TYPE_YMM:                                        \
1476
232
      return prefix##_YMM0 + index;                       \
1477
7.15k
    case TYPE_XMM:                                        \
1478
7.15k
      return prefix##_XMM0 + index;                       \
1479
75
    case TYPE_VK:                                         \
1480
75
      if (index > 7)                                      \
1481
0
        *valid = 0;                                       \
1482
75
      return prefix##_K0 + index;                         \
1483
12
    case TYPE_MM64:                                       \
1484
12
      return prefix##_MM0 + (index & 0x7);                \
1485
9
    case TYPE_SEGMENTREG:                                 \
1486
9
      if (index > 5)                                      \
1487
2
        *valid = 0;                                       \
1488
9
      return prefix##_ES + index;                         \
1489
10
    case TYPE_DEBUGREG:                                   \
1490
10
      return prefix##_DR0 + index;                        \
1491
8
    case TYPE_CONTROLREG:                                 \
1492
8
      return prefix##_CR0 + index;                        \
1493
9
    case TYPE_BNDR:                                       \
1494
9
      if (index > 3)                                      \
1495
0
        *valid = 0;                                       \
1496
14.9k
      return prefix##_BND0 + index;                       \
1497
234k
    }                                                     \
1498
234k
  }
X86DisassemblerDecoder.cpp:fixupRMValue(llvm::X86Disassembler::InternalInstruction*, llvm::X86Disassembler::OperandType, unsigned char, unsigned char*)
Line
Count
Source
1451
156k
                       uint8_t *valid) {                  \
1452
156k
    *valid = 1;                                           \
1453
156k
    switch (type) {                                       \
1454
0
    default:                                              \
1455
0
      debug("Unhandled register type");                   \
1456
0
      *valid = 0;                                         \
1457
0
      return 0;                                           \
1458
45.0k
    case TYPE_Rv:                                         \
1459
45.0k
      return base + index;                                \
1460
13.8k
    case TYPE_R8:                                         \
1461
13.8k
      if (insn->rexPrefix &&                              \
1462
13.8k
         
index >= 43.79k
&&
index <= 73.51k
) { \
1463
551
        return prefix##_SPL + (index - 4);                \
1464
13.8k
      } else {                                            \
1465
13.2k
        return prefix##_AL + index;                       \
1466
13.2k
      }                                                   \
1467
436
    case TYPE_R16:                                        \
1468
436
      return prefix##_AX + index;                         \
1469
759
    case TYPE_R32:                                        \
1470
759
      return prefix##_EAX + index;                        \
1471
94.0k
    case TYPE_R64:                                        \
1472
94.0k
      return prefix##_RAX + index;                        \
1473
51
    case TYPE_ZMM:                                        \
1474
51
      return prefix##_ZMM0 + index;                       \
1475
84
    case TYPE_YMM:                                        \
1476
84
      return prefix##_YMM0 + index;                       \
1477
2.07k
    case TYPE_XMM:                                        \
1478
2.07k
      return prefix##_XMM0 + index;                       \
1479
21
    case TYPE_VK:                                         \
1480
21
      if (index > 7)                                      \
1481
0
        *valid = 0;                                       \
1482
21
      return prefix##_K0 + index;                         \
1483
7
    case TYPE_MM64:                                       \
1484
7
      return prefix##_MM0 + (index & 0x7);                \
1485
0
    case TYPE_SEGMENTREG:                                 \
1486
0
      if (index > 5)                                      \
1487
0
        *valid = 0;                                       \
1488
0
      return prefix##_ES + index;                         \
1489
0
    case TYPE_DEBUGREG:                                   \
1490
0
      return prefix##_DR0 + index;                        \
1491
0
    case TYPE_CONTROLREG:                                 \
1492
0
      return prefix##_CR0 + index;                        \
1493
1
    case TYPE_BNDR:                                       \
1494
1
      if (index > 3)                                      \
1495
0
        *valid = 0;                                       \
1496
13.8k
      return prefix##_BND0 + index;                       \
1497
156k
    }                                                     \
1498
156k
  }
1499
1500
/*
1501
 * fixup*Value - Consults an operand type to determine the meaning of the
1502
 *   reg or R/M field.  If the operand is an XMM operand, for example, an
1503
 *   operand would be XMM0 instead of AX, which readModRM() would otherwise
1504
 *   misinterpret it as.
1505
 *
1506
 * @param insn  - The instruction containing the operand.
1507
 * @param type  - The operand type.
1508
 * @param index - The existing value of the field as reported by readModRM().
1509
 * @param valid - The address of a uint8_t.  The target is set to 1 if the
1510
 *                field is valid for the register class; 0 if not.
1511
 * @return      - The proper value.
1512
 */
1513
GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase,    MODRM_REG)
1514
GENERIC_FIXUP_FUNC(fixupRMValue,  insn->eaRegBase,  EA_REG)
1515
1516
/*
1517
 * fixupReg - Consults an operand specifier to determine which of the
1518
 *   fixup*Value functions to use in correcting readModRM()'ss interpretation.
1519
 *
1520
 * @param insn  - See fixup*Value().
1521
 * @param op    - The operand specifier.
1522
 * @return      - 0 if fixup was successful; -1 if the register returned was
1523
 *                invalid for its class.
1524
 */
1525
static int fixupReg(struct InternalInstruction *insn,
1526
549k
                    const struct OperandSpecifier *op) {
1527
549k
  uint8_t valid;
1528
549k
1529
549k
  dbgprintf(insn, "fixupReg()");
1530
549k
1531
549k
  switch ((OperandEncoding)op->encoding) {
1532
0
  default:
1533
0
    debug("Expected a REG or R/M encoding in fixupReg");
1534
0
    return -1;
1535
450
  case ENCODING_VVVV:
1536
450
    insn->vvvv = (Reg)fixupRegValue(insn,
1537
450
                                    (OperandType)op->type,
1538
450
                                    insn->vvvv,
1539
450
                                    &valid);
1540
450
    if (!valid)
1541
0
      return -1;
1542
450
    break;
1543
233k
  case ENCODING_REG:
1544
233k
    insn->reg = (Reg)fixupRegValue(insn,
1545
233k
                                   (OperandType)op->type,
1546
233k
                                   insn->reg - insn->regBase,
1547
233k
                                   &valid);
1548
233k
    if (!valid)
1549
2
      return -1;
1550
233k
    break;
1551
315k
  
CASE_ENCODING_RM315k
:
1552
315k
  
CASE_ENCODING_VSIB315k
:
1553
2.20M
    if (
insn->eaBase >= insn->eaRegBase315k
) {
1554
156k
      insn->eaBase = (EABase)fixupRMValue(insn,
1555
156k
                                          (OperandType)op->type,
1556
156k
                                          insn->eaBase - insn->eaRegBase,
1557
156k
                                          &valid);
1558
156k
      if (!valid)
1559
0
        return -1;
1560
315k
    }
1561
315k
    break;
1562
549k
  }
1563
549k
1564
549k
  return 0;
1565
549k
}
1566
1567
/*
1568
 * readOpcodeRegister - Reads an operand from the opcode field of an
1569
 *   instruction and interprets it appropriately given the operand width.
1570
 *   Handles AddRegFrm instructions.
1571
 *
1572
 * @param insn  - the instruction whose opcode field is to be read.
1573
 * @param size  - The width (in bytes) of the register being specified.
1574
 *                1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1575
 *                RAX.
1576
 * @return      - 0 on success; nonzero otherwise.
1577
 */
1578
48.6k
static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1579
48.6k
  dbgprintf(insn, "readOpcodeRegister()");
1580
48.6k
1581
48.6k
  if (size == 0)
1582
18.3k
    size = insn->registerSize;
1583
48.6k
1584
48.6k
  switch (size) {
1585
1.92k
  case 1:
1586
1.92k
    insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1587
1.92k
                                                  | (insn->opcode & 7)));
1588
1.92k
    if (insn->rexPrefix &&
1589
250
        insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1590
1.92k
        
insn->opcodeRegister < MODRM_REG_AL + 0x8250
) {
1591
60
      insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1592
60
                                   + (insn->opcodeRegister - MODRM_REG_AL - 4));
1593
60
    }
1594
1.92k
1595
1.92k
    break;
1596
78
  case 2:
1597
78
    insn->opcodeRegister = (Reg)(MODRM_REG_AX
1598
78
                                 + ((bFromREX(insn->rexPrefix) << 3)
1599
78
                                    | (insn->opcode & 7)));
1600
78
    break;
1601
18.2k
  case 4:
1602
18.2k
    insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1603
18.2k
                                 + ((bFromREX(insn->rexPrefix) << 3)
1604
18.2k
                                    | (insn->opcode & 7)));
1605
18.2k
    break;
1606
28.4k
  case 8:
1607
28.4k
    insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1608
28.4k
                                 + ((bFromREX(insn->rexPrefix) << 3)
1609
28.4k
                                    | (insn->opcode & 7)));
1610
28.4k
    break;
1611
48.6k
  }
1612
48.6k
1613
48.6k
  return 0;
1614
48.6k
}
1615
1616
/*
1617
 * readImmediate - Consumes an immediate operand from an instruction, given the
1618
 *   desired operand size.
1619
 *
1620
 * @param insn  - The instruction whose operand is to be read.
1621
 * @param size  - The width (in bytes) of the operand.
1622
 * @return      - 0 if the immediate was successfully consumed; nonzero
1623
 *                otherwise.
1624
 */
1625
180k
static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1626
180k
  uint8_t imm8;
1627
180k
  uint16_t imm16;
1628
180k
  uint32_t imm32;
1629
180k
  uint64_t imm64;
1630
180k
1631
180k
  dbgprintf(insn, "readImmediate()");
1632
180k
1633
180k
  if (
insn->numImmediatesConsumed == 2180k
) {
1634
0
    debug("Already consumed two immediates");
1635
0
    return -1;
1636
0
  }
1637
180k
1638
180k
  
if (180k
size == 0180k
)
1639
0
    size = insn->immediateSize;
1640
180k
  else
1641
180k
    insn->immediateSize = size;
1642
180k
  insn->immediateOffset = insn->readerCursor - insn->startLocation;
1643
180k
1644
180k
  switch (size) {
1645
93.3k
  case 1:
1646
93.3k
    if (consumeByte(insn, &imm8))
1647
0
      return -1;
1648
93.3k
    insn->immediates[insn->numImmediatesConsumed] = imm8;
1649
93.3k
    break;
1650
183
  case 2:
1651
183
    if (consumeUInt16(insn, &imm16))
1652
0
      return -1;
1653
183
    insn->immediates[insn->numImmediatesConsumed] = imm16;
1654
183
    break;
1655
86.1k
  case 4:
1656
86.1k
    if (consumeUInt32(insn, &imm32))
1657
2
      return -1;
1658
86.1k
    insn->immediates[insn->numImmediatesConsumed] = imm32;
1659
86.1k
    break;
1660
1.18k
  case 8:
1661
1.18k
    if (consumeUInt64(insn, &imm64))
1662
0
      return -1;
1663
1.18k
    insn->immediates[insn->numImmediatesConsumed] = imm64;
1664
1.18k
    break;
1665
180k
  }
1666
180k
1667
180k
  insn->numImmediatesConsumed++;
1668
180k
1669
180k
  return 0;
1670
180k
}
1671
1672
/*
1673
 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1674
 *
1675
 * @param insn  - The instruction whose operand is to be read.
1676
 * @return      - 0 if the vvvv was successfully consumed; nonzero
1677
 *                otherwise.
1678
 */
1679
504k
static int readVVVV(struct InternalInstruction* insn) {
1680
504k
  dbgprintf(insn, "readVVVV()");
1681
504k
1682
504k
  int vvvv;
1683
504k
  if (insn->vectorExtensionType == TYPE_EVEX)
1684
260
    
vvvv = (260
v2FromEVEX4of4260
(insn->vectorExtensionPrefix[3]) << 4 |
1685
260
            vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]));
1686
504k
  else 
if (504k
insn->vectorExtensionType == TYPE_VEX_3B504k
)
1687
218
    
vvvv = 218
vvvvFromVEX3of3218
(insn->vectorExtensionPrefix[2]);
1688
504k
  else 
if (504k
insn->vectorExtensionType == TYPE_VEX_2B504k
)
1689
292
    
vvvv = 292
vvvvFromVEX2of2292
(insn->vectorExtensionPrefix[1]);
1690
504k
  else 
if (504k
insn->vectorExtensionType == TYPE_XOP504k
)
1691
39
    
vvvv = 39
vvvvFromXOP3of339
(insn->vectorExtensionPrefix[2]);
1692
504k
  else
1693
503k
    return -1;
1694
809
1695
809
  
if (809
insn->mode != MODE_64BIT809
)
1696
102
    vvvv &= 0x7;
1697
504k
1698
504k
  insn->vvvv = static_cast<Reg>(vvvv);
1699
504k
  return 0;
1700
504k
}
1701
1702
/*
1703
 * readMaskRegister - Reads an mask register from the opcode field of an
1704
 *   instruction.
1705
 *
1706
 * @param insn    - The instruction whose opcode field is to be read.
1707
 * @return        - 0 on success; nonzero otherwise.
1708
 */
1709
123
static int readMaskRegister(struct InternalInstruction* insn) {
1710
123
  dbgprintf(insn, "readMaskRegister()");
1711
123
1712
123
  if (insn->vectorExtensionType != TYPE_EVEX)
1713
0
    return -1;
1714
123
1715
123
  insn->writemask =
1716
123
      static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]));
1717
123
  return 0;
1718
123
}
1719
1720
/*
1721
 * readOperands - Consults the specifier for an instruction and consumes all
1722
 *   operands for that instruction, interpreting them as it goes.
1723
 *
1724
 * @param insn  - The instruction whose operands are to be read and interpreted.
1725
 * @return      - 0 if all operands could be read; nonzero otherwise.
1726
 */
1727
504k
static int readOperands(struct InternalInstruction* insn) {
1728
504k
  int hasVVVV, needVVVV;
1729
504k
  int sawRegImm = 0;
1730
504k
1731
504k
  dbgprintf(insn, "readOperands()");
1732
504k
1733
504k
  /* If non-zero vvvv specified, need to make sure one of the operands
1734
504k
     uses it. */
1735
504k
  hasVVVV = !readVVVV(insn);
1736
809
  needVVVV = hasVVVV && (insn->vvvv != 0);
1737
504k
1738
3.02M
  for (const auto &Op : x86OperandSets[insn->spec->operands]) {
1739
3.02M
    switch (Op.encoding) {
1740
2.18M
    case ENCODING_NONE:
1741
2.18M
    case ENCODING_SI:
1742
2.18M
    case ENCODING_DI:
1743
2.18M
      break;
1744
112
    
CASE_ENCODING_VSIB112
:
1745
784
      // VSIB can use the V2 bit so check only the other bits.
1746
112
      if (needVVVV)
1747
101
        needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0);
1748
112
      if (readModRM(insn))
1749
0
        return -1;
1750
112
      
if (112
fixupReg(insn, &Op)112
)
1751
0
        return -1;
1752
112
      // Apply the AVX512 compressed displacement scaling factor.
1753
112
      
if (112
Op.encoding != ENCODING_REG && 112
insn->eaDisplacement == EA_DISP_8112
)
1754
96
        insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB);
1755
112
      break;
1756
549k
    case ENCODING_REG:
1757
549k
    
CASE_ENCODING_RM549k
:
1758
549k
      if (readModRM(insn))
1759
0
        return -1;
1760
549k
      
if (549k
fixupReg(insn, &Op)549k
)
1761
2
        return -1;
1762
549k
      // Apply the AVX512 compressed displacement scaling factor.
1763
549k
      
if (549k
Op.encoding != ENCODING_REG && 549k
insn->eaDisplacement == EA_DISP_8315k
)
1764
74.3k
        insn->displacement *= 1 << (Op.encoding - ENCODING_RM);
1765
549k
      break;
1766
93.3k
    case ENCODING_IB:
1767
93.3k
      if (
sawRegImm93.3k
) {
1768
8
        /* Saw a register immediate so don't read again and instead split the
1769
8
           previous immediate.  FIXME: This is a hack. */
1770
8
        insn->immediates[insn->numImmediatesConsumed] =
1771
8
          insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1772
8
        ++insn->numImmediatesConsumed;
1773
8
        break;
1774
8
      }
1775
93.3k
      
if (93.3k
readImmediate(insn, 1)93.3k
)
1776
0
        return -1;
1777
93.3k
      
if (93.3k
Op.type == TYPE_XMM || 93.3k
Op.type == TYPE_YMM93.3k
)
1778
35
        sawRegImm = 1;
1779
93.3k
      break;
1780
41
    case ENCODING_IW:
1781
41
      if (readImmediate(insn, 2))
1782
0
        return -1;
1783
41
      break;
1784
41.2k
    case ENCODING_ID:
1785
41.2k
      if (readImmediate(insn, 4))
1786
0
        return -1;
1787
41.2k
      break;
1788
1.14k
    case ENCODING_IO:
1789
1.14k
      if (readImmediate(insn, 8))
1790
0
        return -1;
1791
1.14k
      break;
1792
44.8k
    case ENCODING_Iv:
1793
44.8k
      if (readImmediate(insn, insn->immediateSize))
1794
2
        return -1;
1795
44.8k
      break;
1796
137
    case ENCODING_Ia:
1797
137
      if (readImmediate(insn, insn->addressSize))
1798
0
        return -1;
1799
137
      break;
1800
1.92k
    case ENCODING_RB:
1801
1.92k
      if (readOpcodeRegister(insn, 1))
1802
0
        return -1;
1803
1.92k
      break;
1804
0
    case ENCODING_RW:
1805
0
      if (readOpcodeRegister(insn, 2))
1806
0
        return -1;
1807
0
      break;
1808
0
    case ENCODING_RD:
1809
0
      if (readOpcodeRegister(insn, 4))
1810
0
        return -1;
1811
0
      break;
1812
28.4k
    case ENCODING_RO:
1813
28.4k
      if (readOpcodeRegister(insn, 8))
1814
0
        return -1;
1815
28.4k
      break;
1816
18.3k
    case ENCODING_Rv:
1817
18.3k
      if (readOpcodeRegister(insn, 0))
1818
0
        return -1;
1819
18.3k
      break;
1820
659
    case ENCODING_FP:
1821
659
      break;
1822
450
    case ENCODING_VVVV:
1823
450
      needVVVV = 0; /* Mark that we have found a VVVV operand. */
1824
450
      if (!hasVVVV)
1825
0
        return -1;
1826
450
      
if (450
fixupReg(insn, &Op)450
)
1827
0
        return -1;
1828
450
      break;
1829
123
    case ENCODING_WRITEMASK:
1830
123
      if (readMaskRegister(insn))
1831
0
        return -1;
1832
123
      break;
1833
62.9k
    case ENCODING_DUP:
1834
62.9k
      break;
1835
0
    default:
1836
0
      dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1837
0
      return -1;
1838
504k
    }
1839
504k
  }
1840
504k
1841
504k
  /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1842
504k
  
if (504k
needVVVV504k
)
return -11
;
1843
504k
1844
504k
  return 0;
1845
504k
}
1846
1847
/*
1848
 * decodeInstruction - Reads and interprets a full instruction provided by the
1849
 *   user.
1850
 *
1851
 * @param insn      - A pointer to the instruction to be populated.  Must be
1852
 *                    pre-allocated.
1853
 * @param reader    - The function to be used to read the instruction's bytes.
1854
 * @param readerArg - A generic argument to be passed to the reader to store
1855
 *                    any internal state.
1856
 * @param logger    - If non-NULL, the function to be used to write log messages
1857
 *                    and warnings.
1858
 * @param loggerArg - A generic argument to be passed to the logger to store
1859
 *                    any internal state.
1860
 * @param startLoc  - The address (in the reader's address space) of the first
1861
 *                    byte in the instruction.
1862
 * @param mode      - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1863
 *                    decode the instruction in.
1864
 * @return          - 0 if the instruction's memory could be read; nonzero if
1865
 *                    not.
1866
 */
1867
int llvm::X86Disassembler::decodeInstruction(
1868
    struct InternalInstruction *insn, byteReader_t reader,
1869
    const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg,
1870
506k
    uint64_t startLoc, DisassemblerMode mode) {
1871
506k
  memset(insn, 0, sizeof(struct InternalInstruction));
1872
506k
1873
506k
  insn->reader = reader;
1874
506k
  insn->readerArg = readerArg;
1875
506k
  insn->dlog = logger;
1876
506k
  insn->dlogArg = loggerArg;
1877
506k
  insn->startLocation = startLoc;
1878
506k
  insn->readerCursor = startLoc;
1879
506k
  insn->mode = mode;
1880
506k
  insn->numImmediatesConsumed = 0;
1881
506k
1882
506k
  if (readPrefixes(insn)       ||
1883
506k
      readOpcode(insn)         ||
1884
506k
      getID(insn, miiArg)      ||
1885
506k
      insn->instructionID == 0 ||
1886
504k
      readOperands(insn))
1887
1.54k
    return -1;
1888
504k
1889
504k
  insn->operands = x86OperandSets[insn->spec->operands];
1890
504k
1891
504k
  insn->length = insn->readerCursor - insn->startLocation;
1892
504k
1893
504k
  dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1894
504k
            startLoc, insn->readerCursor, insn->length);
1895
504k
1896
504k
  if (insn->length > 15)
1897
0
    dbgprintf(insn, "Instruction exceeds 15-byte limit");
1898
506k
1899
506k
  return 0;
1900
506k
}