Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
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//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file includes code for rendering MCInst instances as AT&T-style
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// assembly.
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//
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//===----------------------------------------------------------------------===//
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#include "X86ATTInstPrinter.h"
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86InstComments.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cinttypes>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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// Include the auto-generated portion of the assembly writer.
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#define PRINT_ALIAS_INSTR
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#include "X86GenAsmWriter.inc"
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1.01M
void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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1.01M
  OS << markup("<reg:") << '%' << getRegisterName(RegNo) << markup(">");
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1.01M
}
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void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
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659k
                                  StringRef Annot, const MCSubtargetInfo &STI) {
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659k
  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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659k
  uint64_t TSFlags = Desc.TSFlags;
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659k
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659k
  // If verbose assembly is enabled, we can print some informative comments.
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659k
  if (CommentStream)
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486k
    HasCustomInstComment =
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486k
        EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
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659k
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659k
  if (TSFlags & X86II::LOCK)
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843
    OS << "\tlock\t";
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659k
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659k
  // Output CALLpcrel32 as "callq" in 64-bit mode.
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659k
  // In Intel annotation it's always emitted as "call".
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659k
  //
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659k
  // TODO: Probably this hack should be redesigned via InstAlias in
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659k
  // InstrInfo.td as soon as Requires clause is supported properly
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659k
  // for InstAlias.
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659k
  if (MI->getOpcode() == X86::CALLpcrel32 &&
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659k
      
(STI.getFeatureBits()[X86::Mode64Bit])3.11k
) {
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37
    OS << "\tcallq\t";
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37
    printPCRelImm(MI, 0, OS);
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37
  }
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659k
  // data16 and data32 both have the same encoding of 0x66. While data32 is
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659k
  // valid only in 16 bit systems, data16 is valid in the rest.
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659k
  // There seems to be some lack of support of the Requires clause that causes
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659k
  // 0x66 to be interpreted as "data16" by the asm printer.
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659k
  // Thus we add an adjustment here in order to print the "right" instruction.
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659k
  else 
if (659k
MI->getOpcode() == X86::DATA16_PREFIX &&
73
659k
    
(STI.getFeatureBits()[X86::Mode16Bit])45
) {
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1
    MCInst Data32MI(*MI);
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1
    Data32MI.setOpcode(X86::DATA32_PREFIX);
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1
    printInstruction(&Data32MI, OS);
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1
  }
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659k
  // Try to print any aliases first.
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659k
  else 
if (659k
!printAliasInstr(MI, OS)659k
)
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    printInstruction(MI, OS);
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659k
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659k
  // Next always print the annotation.
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659k
  printAnnotation(OS, Annot);
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}
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void X86ATTInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op,
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3.89k
                                      raw_ostream &O) {
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3.89k
  int64_t Imm = MI->getOperand(Op).getImm();
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3.89k
  switch (Imm) {
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0
  
default: 0
llvm_unreachable0
("Invalid ssecc/avxcc argument!");
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556
  case    0: O << "eq"; break;
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1.07k
  case    1: O << "lt"; break;
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554
  case    2: O << "le"; break;
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131
  case    3: O << "unord"; break;
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487
  case    4: O << "neq"; break;
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275
  case    5: O << "nlt"; break;
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  case    6: O << "nle"; break;
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  case    7: O << "ord"; break;
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20
  case    8: O << "eq_uq"; break;
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  case    9: O << "nge"; break;
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14
  case  0xa: O << "ngt"; break;
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  case  0xb: O << "false"; break;
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14
  case  0xc: O << "neq_oq"; break;
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35
  case  0xd: O << "ge"; break;
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  case  0xe: O << "gt"; break;
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70
  case  0xf: O << "true"; break;
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14
  case 0x10: O << "eq_os"; break;
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14
  case 0x11: O << "lt_oq"; break;
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14
  case 0x12: O << "le_oq"; break;
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14
  case 0x13: O << "unord_s"; break;
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  case 0x14: O << "neq_us"; break;
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  case 0x15: O << "nlt_uq"; break;
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  case 0x16: O << "nle_uq"; break;
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  case 0x17: O << "ord_s"; break;
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  case 0x18: O << "eq_us"; break;
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  case 0x19: O << "nge_uq"; break;
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  case 0x1a: O << "ngt_uq"; break;
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  case 0x1b: O << "false_os"; break;
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  case 0x1c: O << "neq_os"; break;
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  case 0x1d: O << "ge_oq"; break;
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  case 0x1e: O << "gt_oq"; break;
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  case 0x1f: O << "true_us"; break;
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3.89k
  }
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3.89k
}
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void X86ATTInstPrinter::printXOPCC(const MCInst *MI, unsigned Op,
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                                   raw_ostream &O) {
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  int64_t Imm = MI->getOperand(Op).getImm();
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  switch (Imm) {
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0
  
default: 0
llvm_unreachable0
("Invalid xopcc argument!");
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  case 0: O << "lt"; break;
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  case 1: O << "le"; break;
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  case 2: O << "gt"; break;
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  case 3: O << "ge"; break;
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  case 4: O << "eq"; break;
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  case 5: O << "neq"; break;
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12
  case 6: O << "false"; break;
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12
  case 7: O << "true"; break;
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227
  }
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}
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void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
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                                            raw_ostream &O) {
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722
  int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
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722
  switch (Imm) {
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  case 0: O << "{rn-sae}"; break;
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  case 1: O << "{rd-sae}"; break;
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169
  case 2: O << "{ru-sae}"; break;
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  case 3: O << "{rz-sae}"; break;
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722
  }
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722
}
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/// printPCRelImm - This is used to print an immediate value that ends up
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/// being encoded as a pc-relative value (e.g. for jumps and calls).  These
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/// print slightly differently than normal immediates.  For example, a $ is not
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/// emitted.
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void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
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44.4k
                                      raw_ostream &O) {
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44.4k
  const MCOperand &Op = MI->getOperand(OpNo);
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44.4k
  if (Op.isImm())
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28.3k
    O << formatImm(Op.getImm());
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16.1k
  else {
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16.1k
    assert(Op.isExpr() && "unknown pcrel immediate operand");
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16.1k
    // If a symbolic branch target was added as a constant expression then print
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16.1k
    // that address in hex.
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16.1k
    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
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16.1k
    int64_t Address;
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16.1k
    if (
BranchTarget && 16.1k
BranchTarget->evaluateAsAbsolute(Address)102
) {
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      O << formatHex((uint64_t)Address);
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16.1k
    } else {
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16.0k
      // Otherwise, just print the expression.
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16.0k
      Op.getExpr()->print(O, &MAI);
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16.0k
    }
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16.1k
  }
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44.4k
}
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void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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1.07M
                                     raw_ostream &O) {
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1.07M
  const MCOperand &Op = MI->getOperand(OpNo);
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1.07M
  if (
Op.isReg()1.07M
) {
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1.01M
    printRegName(O, Op.getReg());
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1.07M
  } else 
if (58.4k
Op.isImm()58.4k
) {
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57.2k
    // Print immediates as signed values.
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57.2k
    int64_t Imm = Op.getImm();
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57.2k
    O << markup("<imm:") << '$' << formatImm(Imm) << markup(">");
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57.2k
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57.2k
    // TODO: This should be in a helper function in the base class, so it can
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57.2k
    // be used by other printers.
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57.2k
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57.2k
    // If there are no instruction-specific comments, add a comment clarifying
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57.2k
    // the hex value of the immediate operand when it isn't in the range
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57.2k
    // [-256,255].
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57.2k
    if (
CommentStream && 57.2k
!HasCustomInstComment32.4k
&&
(Imm > 255 || 32.4k
Imm < -25629.1k
)) {
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      // Don't print unnecessary hex sign bits. 
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4.05k
      if (Imm == (int16_t)(Imm))
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2.09k
        *CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm);
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1.95k
      else 
if (1.95k
Imm == (int32_t)(Imm)1.95k
)
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1.37k
        *CommentStream << format("imm = 0x%" PRIX32 "\n", (uint32_t)Imm);
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1.95k
      else
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        *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm);
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    }
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58.4k
  } else {
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1.19k
    assert(Op.isExpr() && "unknown operand kind in printOperand");
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1.19k
    O << markup("<imm:") << '$';
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1.19k
    Op.getExpr()->print(O, &MAI);
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1.19k
    O << markup(">");
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1.19k
  }
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1.07M
}
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void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
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183k
                                          raw_ostream &O) {
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183k
  const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
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183k
  const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
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183k
  const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
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183k
  const MCOperand &SegReg = MI->getOperand(Op + X86::AddrSegmentReg);
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183k
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183k
  O << markup("<mem:");
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183k
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183k
  // If this has a segment register, print it.
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183k
  if (
SegReg.getReg()183k
) {
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1.30k
    printOperand(MI, Op + X86::AddrSegmentReg, O);
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1.30k
    O << ':';
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1.30k
  }
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183k
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183k
  if (
DispSpec.isImm()183k
) {
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163k
    int64_t DispVal = DispSpec.getImm();
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163k
    if (
DispVal || 163k
(!IndexReg.getReg() && 47.7k
!BaseReg.getReg()42.0k
))
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115k
      O << formatImm(DispVal);
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183k
  } else {
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20.1k
    assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
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20.1k
    DispSpec.getExpr()->print(O, &MAI);
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20.1k
  }
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183k
234
183k
  if (
IndexReg.getReg() || 183k
BaseReg.getReg()171k
) {
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177k
    O << '(';
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177k
    if (BaseReg.getReg())
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176k
      printOperand(MI, Op + X86::AddrBaseReg, O);
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177k
239
177k
    if (
IndexReg.getReg()177k
) {
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12.0k
      O << ',';
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12.0k
      printOperand(MI, Op + X86::AddrIndexReg, O);
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12.0k
      unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
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12.0k
      if (
ScaleVal != 112.0k
) {
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7.56k
        O << ',' << markup("<imm:") << ScaleVal // never printed in hex.
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7.56k
          << markup(">");
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7.56k
      }
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12.0k
    }
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177k
    O << ')';
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177k
  }
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183k
251
183k
  O << markup(">");
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183k
}
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void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
255
210
                                    raw_ostream &O) {
256
210
  const MCOperand &SegReg = MI->getOperand(Op + 1);
257
210
258
210
  O << markup("<mem:");
259
210
260
210
  // If this has a segment register, print it.
261
210
  if (
SegReg.getReg()210
) {
262
56
    printOperand(MI, Op + 1, O);
263
56
    O << ':';
264
56
  }
265
210
266
210
  O << "(";
267
210
  printOperand(MI, Op, O);
268
210
  O << ")";
269
210
270
210
  O << markup(">");
271
210
}
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273
void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
274
200
                                    raw_ostream &O) {
275
200
  O << markup("<mem:");
276
200
277
200
  O << "%es:(";
278
200
  printOperand(MI, Op, O);
279
200
  O << ")";
280
200
281
200
  O << markup(">");
282
200
}
283
284
void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
285
984
                                       raw_ostream &O) {
286
984
  const MCOperand &DispSpec = MI->getOperand(Op);
287
984
  const MCOperand &SegReg = MI->getOperand(Op + 1);
288
984
289
984
  O << markup("<mem:");
290
984
291
984
  // If this has a segment register, print it.
292
984
  if (
SegReg.getReg()984
) {
293
238
    printOperand(MI, Op + 1, O);
294
238
    O << ':';
295
238
  }
296
984
297
984
  if (
DispSpec.isImm()984
) {
298
375
    O << formatImm(DispSpec.getImm());
299
984
  } else {
300
609
    assert(DispSpec.isExpr() && "non-immediate displacement?");
301
609
    DispSpec.getExpr()->print(O, &MAI);
302
609
  }
303
984
304
984
  O << markup(">");
305
984
}
306
307
void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
308
70.2k
                                   raw_ostream &O) {
309
70.2k
  if (MI->getOperand(Op).isExpr())
310
3
    return printOperand(MI, Op, O);
311
70.2k
312
70.2k
  O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)
313
70.2k
    << markup(">");
314
70.2k
}