Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
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//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file includes code for rendering MCInst instances as Intel-style
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// assembly.
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//
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//===----------------------------------------------------------------------===//
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#include "X86IntelInstPrinter.h"
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86InstComments.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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#include "X86GenAsmWriter1.inc"
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32.6k
void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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32.6k
  OS << getRegisterName(RegNo);
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32.6k
}
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void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
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                                    StringRef Annot,
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13.0k
                                    const MCSubtargetInfo &STI) {
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13.0k
  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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13.0k
  uint64_t TSFlags = Desc.TSFlags;
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13.0k
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  if (TSFlags & X86II::LOCK)
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0
    OS << "\tlock\n";
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13.0k
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13.0k
  printInstruction(MI, OS);
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13.0k
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13.0k
  // Next always print the annotation.
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13.0k
  printAnnotation(OS, Annot);
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13.0k
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13.0k
  // If verbose assembly is enabled, we can print some informative comments.
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13.0k
  if (CommentStream)
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13.0k
    EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
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13.0k
}
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void X86IntelInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op,
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0
                                        raw_ostream &O) {
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0
  int64_t Imm = MI->getOperand(Op).getImm();
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0
  switch (Imm) {
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0
  
default: 0
llvm_unreachable0
("Invalid avxcc argument!");
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0
  case    0: O << "eq"; break;
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0
  case    1: O << "lt"; break;
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0
  case    2: O << "le"; break;
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0
  case    3: O << "unord"; break;
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0
  case    4: O << "neq"; break;
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0
  case    5: O << "nlt"; break;
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0
  case    6: O << "nle"; break;
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0
  case    7: O << "ord"; break;
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0
  case    8: O << "eq_uq"; break;
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0
  case    9: O << "nge"; break;
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0
  case  0xa: O << "ngt"; break;
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0
  case  0xb: O << "false"; break;
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0
  case  0xc: O << "neq_oq"; break;
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0
  case  0xd: O << "ge"; break;
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0
  case  0xe: O << "gt"; break;
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0
  case  0xf: O << "true"; break;
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0
  case 0x10: O << "eq_os"; break;
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0
  case 0x11: O << "lt_oq"; break;
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  case 0x12: O << "le_oq"; break;
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  case 0x13: O << "unord_s"; break;
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  case 0x14: O << "neq_us"; break;
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  case 0x15: O << "nlt_uq"; break;
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  case 0x16: O << "nle_uq"; break;
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  case 0x17: O << "ord_s"; break;
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  case 0x18: O << "eq_us"; break;
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0
  case 0x19: O << "nge_uq"; break;
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  case 0x1a: O << "ngt_uq"; break;
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  case 0x1b: O << "false_os"; break;
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  case 0x1c: O << "neq_os"; break;
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  case 0x1d: O << "ge_oq"; break;
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  case 0x1e: O << "gt_oq"; break;
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  case 0x1f: O << "true_us"; break;
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  }
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0
}
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void X86IntelInstPrinter::printXOPCC(const MCInst *MI, unsigned Op,
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                                     raw_ostream &O) {
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  int64_t Imm = MI->getOperand(Op).getImm();
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  switch (Imm) {
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default: 0
llvm_unreachable0
("Invalid xopcc argument!");
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  case 0: O << "lt"; break;
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  case 1: O << "le"; break;
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0
  case 2: O << "gt"; break;
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  case 3: O << "ge"; break;
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  case 4: O << "eq"; break;
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  case 5: O << "neq"; break;
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  case 6: O << "false"; break;
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  case 7: O << "true"; break;
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  }
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}
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void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
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                                               raw_ostream &O) {
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  int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
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  switch (Imm) {
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  case 0: O << "{rn-sae}"; break;
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  case 1: O << "{rd-sae}"; break;
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  case 2: O << "{ru-sae}"; break;
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  case 3: O << "{rz-sae}"; break;
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  }
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}
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/// printPCRelImm - This is used to print an immediate value that ends up
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/// being encoded as a pc-relative value.
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void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
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                                        raw_ostream &O) {
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  const MCOperand &Op = MI->getOperand(OpNo);
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  if (Op.isImm())
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    O << formatImm(Op.getImm());
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  else {
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    assert(Op.isExpr() && "unknown pcrel immediate operand");
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    // If a symbolic branch target was added as a constant expression then print
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    // that address in hex.
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    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
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    int64_t Address;
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    if (
BranchTarget && 19
BranchTarget->evaluateAsAbsolute(Address)0
) {
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      O << formatHex((uint64_t)Address);
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    }
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    else {
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      // Otherwise, just print the expression.
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      Op.getExpr()->print(O, &MAI);
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    }
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  }
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}
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void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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                                       raw_ostream &O) {
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  const MCOperand &Op = MI->getOperand(OpNo);
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  if (
Op.isReg()32.7k
) {
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    printRegName(O, Op.getReg());
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  } else 
if (314
Op.isImm()314
) {
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    O << formatImm((int64_t)Op.getImm());
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  } else {
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    assert(Op.isExpr() && "unknown operand kind in printOperand");
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    O << "offset ";
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    Op.getExpr()->print(O, &MAI);
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  }
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}
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void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
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                                            raw_ostream &O) {
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  const MCOperand &BaseReg  = MI->getOperand(Op+X86::AddrBaseReg);
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  unsigned ScaleVal         = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
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  const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
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  const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
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  const MCOperand &SegReg   = MI->getOperand(Op+X86::AddrSegmentReg);
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  // If this has a segment register, print it.
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  if (
SegReg.getReg()9.05k
) {
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    printOperand(MI, Op+X86::AddrSegmentReg, O);
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    O << ':';
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  }
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  O << '[';
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  bool NeedPlus = false;
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  if (
BaseReg.getReg()9.05k
) {
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    printOperand(MI, Op+X86::AddrBaseReg, O);
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    NeedPlus = true;
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  }
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9.05k
  if (
IndexReg.getReg()9.05k
) {
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1.56k
    if (
NeedPlus1.56k
)
O << " + "1.56k
;
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1.56k
    if (ScaleVal != 1)
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      O << ScaleVal << '*';
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1.56k
    printOperand(MI, Op+X86::AddrIndexReg, O);
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    NeedPlus = true;
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  }
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9.05k
  if (
!DispSpec.isImm()9.05k
) {
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16
    if (
NeedPlus16
)
O << " + "3
;
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    assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
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    DispSpec.getExpr()->print(O, &MAI);
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  } else {
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    int64_t DispVal = DispSpec.getImm();
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    if (
DispVal || 9.04k
(!IndexReg.getReg() && 1.36k
!BaseReg.getReg()1.33k
)) {
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      if (
NeedPlus7.68k
) {
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        if (DispVal > 0)
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          O << " + ";
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        else {
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          O << " - ";
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          DispVal = -DispVal;
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        }
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      }
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      O << formatImm(DispVal);
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    }
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  }
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  O << ']';
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}
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void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
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                                      raw_ostream &O) {
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  const MCOperand &SegReg   = MI->getOperand(Op+1);
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4
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  // If this has a segment register, print it.
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  if (
SegReg.getReg()4
) {
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0
    printOperand(MI, Op+1, O);
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    O << ':';
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0
  }
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  O << '[';
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  printOperand(MI, Op, O);
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  O << ']';
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}
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void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
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                                      raw_ostream &O) {
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  // DI accesses are always ES-based.
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  O << "es:[";
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  printOperand(MI, Op, O);
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  O << ']';
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}
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void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
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                                         raw_ostream &O) {
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  const MCOperand &DispSpec = MI->getOperand(Op);
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  const MCOperand &SegReg   = MI->getOperand(Op+1);
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17
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  // If this has a segment register, print it.
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  if (
SegReg.getReg()17
) {
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0
    printOperand(MI, Op+1, O);
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0
    O << ':';
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  }
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17
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17
  O << '[';
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17
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17
  if (
DispSpec.isImm()17
) {
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17
    O << formatImm(DispSpec.getImm());
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17
  } else {
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0
    assert(DispSpec.isExpr() && "non-immediate displacement?");
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0
    DispSpec.getExpr()->print(O, &MAI);
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0
  }
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17
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17
  O << ']';
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}
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void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
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1.78k
                                     raw_ostream &O) {
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1.78k
  if (MI->getOperand(Op).isExpr())
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1
    return MI->getOperand(Op).getExpr()->print(O, &MAI);
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1.78k
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1.78k
  O << formatImm(MI->getOperand(Op).getImm() & 0xff);
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1.78k
}