/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
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1 | | //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file includes code for rendering MCInst instances as Intel-style |
11 | | // assembly. |
12 | | // |
13 | | //===----------------------------------------------------------------------===// |
14 | | |
15 | | #include "X86IntelInstPrinter.h" |
16 | | #include "MCTargetDesc/X86BaseInfo.h" |
17 | | #include "X86InstComments.h" |
18 | | #include "llvm/MC/MCExpr.h" |
19 | | #include "llvm/MC/MCInst.h" |
20 | | #include "llvm/MC/MCInstrDesc.h" |
21 | | #include "llvm/MC/MCInstrInfo.h" |
22 | | #include "llvm/Support/Casting.h" |
23 | | #include "llvm/Support/ErrorHandling.h" |
24 | | #include <cassert> |
25 | | #include <cstdint> |
26 | | |
27 | | using namespace llvm; |
28 | | |
29 | | #define DEBUG_TYPE "asm-printer" |
30 | | |
31 | | #include "X86GenAsmWriter1.inc" |
32 | | |
33 | 32.6k | void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { |
34 | 32.6k | OS << getRegisterName(RegNo); |
35 | 32.6k | } |
36 | | |
37 | | void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, |
38 | | StringRef Annot, |
39 | 13.0k | const MCSubtargetInfo &STI) { |
40 | 13.0k | const MCInstrDesc &Desc = MII.get(MI->getOpcode()); |
41 | 13.0k | uint64_t TSFlags = Desc.TSFlags; |
42 | 13.0k | |
43 | 13.0k | if (TSFlags & X86II::LOCK) |
44 | 0 | OS << "\tlock\n"; |
45 | 13.0k | |
46 | 13.0k | printInstruction(MI, OS); |
47 | 13.0k | |
48 | 13.0k | // Next always print the annotation. |
49 | 13.0k | printAnnotation(OS, Annot); |
50 | 13.0k | |
51 | 13.0k | // If verbose assembly is enabled, we can print some informative comments. |
52 | 13.0k | if (CommentStream) |
53 | 13.0k | EmitAnyX86InstComments(MI, *CommentStream, getRegisterName); |
54 | 13.0k | } |
55 | | |
56 | | void X86IntelInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op, |
57 | 0 | raw_ostream &O) { |
58 | 0 | int64_t Imm = MI->getOperand(Op).getImm(); |
59 | 0 | switch (Imm) { |
60 | 0 | default: 0 llvm_unreachable0 ("Invalid avxcc argument!"); |
61 | 0 | case 0: O << "eq"; break; |
62 | 0 | case 1: O << "lt"; break; |
63 | 0 | case 2: O << "le"; break; |
64 | 0 | case 3: O << "unord"; break; |
65 | 0 | case 4: O << "neq"; break; |
66 | 0 | case 5: O << "nlt"; break; |
67 | 0 | case 6: O << "nle"; break; |
68 | 0 | case 7: O << "ord"; break; |
69 | 0 | case 8: O << "eq_uq"; break; |
70 | 0 | case 9: O << "nge"; break; |
71 | 0 | case 0xa: O << "ngt"; break; |
72 | 0 | case 0xb: O << "false"; break; |
73 | 0 | case 0xc: O << "neq_oq"; break; |
74 | 0 | case 0xd: O << "ge"; break; |
75 | 0 | case 0xe: O << "gt"; break; |
76 | 0 | case 0xf: O << "true"; break; |
77 | 0 | case 0x10: O << "eq_os"; break; |
78 | 0 | case 0x11: O << "lt_oq"; break; |
79 | 0 | case 0x12: O << "le_oq"; break; |
80 | 0 | case 0x13: O << "unord_s"; break; |
81 | 0 | case 0x14: O << "neq_us"; break; |
82 | 0 | case 0x15: O << "nlt_uq"; break; |
83 | 0 | case 0x16: O << "nle_uq"; break; |
84 | 0 | case 0x17: O << "ord_s"; break; |
85 | 0 | case 0x18: O << "eq_us"; break; |
86 | 0 | case 0x19: O << "nge_uq"; break; |
87 | 0 | case 0x1a: O << "ngt_uq"; break; |
88 | 0 | case 0x1b: O << "false_os"; break; |
89 | 0 | case 0x1c: O << "neq_os"; break; |
90 | 0 | case 0x1d: O << "ge_oq"; break; |
91 | 0 | case 0x1e: O << "gt_oq"; break; |
92 | 0 | case 0x1f: O << "true_us"; break; |
93 | 0 | } |
94 | 0 | } |
95 | | |
96 | | void X86IntelInstPrinter::printXOPCC(const MCInst *MI, unsigned Op, |
97 | 0 | raw_ostream &O) { |
98 | 0 | int64_t Imm = MI->getOperand(Op).getImm(); |
99 | 0 | switch (Imm) { |
100 | 0 | default: 0 llvm_unreachable0 ("Invalid xopcc argument!"); |
101 | 0 | case 0: O << "lt"; break; |
102 | 0 | case 1: O << "le"; break; |
103 | 0 | case 2: O << "gt"; break; |
104 | 0 | case 3: O << "ge"; break; |
105 | 0 | case 4: O << "eq"; break; |
106 | 0 | case 5: O << "neq"; break; |
107 | 0 | case 6: O << "false"; break; |
108 | 0 | case 7: O << "true"; break; |
109 | 0 | } |
110 | 0 | } |
111 | | |
112 | | void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, |
113 | 1.00k | raw_ostream &O) { |
114 | 1.00k | int64_t Imm = MI->getOperand(Op).getImm() & 0x3; |
115 | 1.00k | switch (Imm) { |
116 | 252 | case 0: O << "{rn-sae}"; break; |
117 | 252 | case 1: O << "{rd-sae}"; break; |
118 | 252 | case 2: O << "{ru-sae}"; break; |
119 | 252 | case 3: O << "{rz-sae}"; break; |
120 | 1.00k | } |
121 | 1.00k | } |
122 | | |
123 | | /// printPCRelImm - This is used to print an immediate value that ends up |
124 | | /// being encoded as a pc-relative value. |
125 | | void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo, |
126 | 98 | raw_ostream &O) { |
127 | 98 | const MCOperand &Op = MI->getOperand(OpNo); |
128 | 98 | if (Op.isImm()) |
129 | 79 | O << formatImm(Op.getImm()); |
130 | 19 | else { |
131 | 19 | assert(Op.isExpr() && "unknown pcrel immediate operand"); |
132 | 19 | // If a symbolic branch target was added as a constant expression then print |
133 | 19 | // that address in hex. |
134 | 19 | const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); |
135 | 19 | int64_t Address; |
136 | 19 | if (BranchTarget && 19 BranchTarget->evaluateAsAbsolute(Address)0 ) { |
137 | 0 | O << formatHex((uint64_t)Address); |
138 | 0 | } |
139 | 19 | else { |
140 | 19 | // Otherwise, just print the expression. |
141 | 19 | Op.getExpr()->print(O, &MAI); |
142 | 19 | } |
143 | 19 | } |
144 | 98 | } |
145 | | |
146 | | void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, |
147 | 32.7k | raw_ostream &O) { |
148 | 32.7k | const MCOperand &Op = MI->getOperand(OpNo); |
149 | 32.7k | if (Op.isReg()32.7k ) { |
150 | 32.4k | printRegName(O, Op.getReg()); |
151 | 32.7k | } else if (314 Op.isImm()314 ) { |
152 | 311 | O << formatImm((int64_t)Op.getImm()); |
153 | 314 | } else { |
154 | 3 | assert(Op.isExpr() && "unknown operand kind in printOperand"); |
155 | 3 | O << "offset "; |
156 | 3 | Op.getExpr()->print(O, &MAI); |
157 | 3 | } |
158 | 32.7k | } |
159 | | |
160 | | void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, |
161 | 9.05k | raw_ostream &O) { |
162 | 9.05k | const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); |
163 | 9.05k | unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); |
164 | 9.05k | const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); |
165 | 9.05k | const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); |
166 | 9.05k | const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg); |
167 | 9.05k | |
168 | 9.05k | // If this has a segment register, print it. |
169 | 9.05k | if (SegReg.getReg()9.05k ) { |
170 | 0 | printOperand(MI, Op+X86::AddrSegmentReg, O); |
171 | 0 | O << ':'; |
172 | 0 | } |
173 | 9.05k | |
174 | 9.05k | O << '['; |
175 | 9.05k | |
176 | 9.05k | bool NeedPlus = false; |
177 | 9.05k | if (BaseReg.getReg()9.05k ) { |
178 | 7.35k | printOperand(MI, Op+X86::AddrBaseReg, O); |
179 | 7.35k | NeedPlus = true; |
180 | 7.35k | } |
181 | 9.05k | |
182 | 9.05k | if (IndexReg.getReg()9.05k ) { |
183 | 1.56k | if (NeedPlus1.56k ) O << " + "1.56k ; |
184 | 1.56k | if (ScaleVal != 1) |
185 | 1.46k | O << ScaleVal << '*'; |
186 | 1.56k | printOperand(MI, Op+X86::AddrIndexReg, O); |
187 | 1.56k | NeedPlus = true; |
188 | 1.56k | } |
189 | 9.05k | |
190 | 9.05k | if (!DispSpec.isImm()9.05k ) { |
191 | 16 | if (NeedPlus16 ) O << " + "3 ; |
192 | 16 | assert(DispSpec.isExpr() && "non-immediate displacement for LEA?"); |
193 | 16 | DispSpec.getExpr()->print(O, &MAI); |
194 | 9.05k | } else { |
195 | 9.04k | int64_t DispVal = DispSpec.getImm(); |
196 | 9.04k | if (DispVal || 9.04k (!IndexReg.getReg() && 1.36k !BaseReg.getReg()1.33k )) { |
197 | 7.68k | if (NeedPlus7.68k ) { |
198 | 6.00k | if (DispVal > 0) |
199 | 3.74k | O << " + "; |
200 | 2.25k | else { |
201 | 2.25k | O << " - "; |
202 | 2.25k | DispVal = -DispVal; |
203 | 2.25k | } |
204 | 6.00k | } |
205 | 7.68k | O << formatImm(DispVal); |
206 | 7.68k | } |
207 | 9.04k | } |
208 | 9.05k | |
209 | 9.05k | O << ']'; |
210 | 9.05k | } |
211 | | |
212 | | void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op, |
213 | 4 | raw_ostream &O) { |
214 | 4 | const MCOperand &SegReg = MI->getOperand(Op+1); |
215 | 4 | |
216 | 4 | // If this has a segment register, print it. |
217 | 4 | if (SegReg.getReg()4 ) { |
218 | 0 | printOperand(MI, Op+1, O); |
219 | 0 | O << ':'; |
220 | 0 | } |
221 | 4 | O << '['; |
222 | 4 | printOperand(MI, Op, O); |
223 | 4 | O << ']'; |
224 | 4 | } |
225 | | |
226 | | void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op, |
227 | 4 | raw_ostream &O) { |
228 | 4 | // DI accesses are always ES-based. |
229 | 4 | O << "es:["; |
230 | 4 | printOperand(MI, Op, O); |
231 | 4 | O << ']'; |
232 | 4 | } |
233 | | |
234 | | void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op, |
235 | 17 | raw_ostream &O) { |
236 | 17 | const MCOperand &DispSpec = MI->getOperand(Op); |
237 | 17 | const MCOperand &SegReg = MI->getOperand(Op+1); |
238 | 17 | |
239 | 17 | // If this has a segment register, print it. |
240 | 17 | if (SegReg.getReg()17 ) { |
241 | 0 | printOperand(MI, Op+1, O); |
242 | 0 | O << ':'; |
243 | 0 | } |
244 | 17 | |
245 | 17 | O << '['; |
246 | 17 | |
247 | 17 | if (DispSpec.isImm()17 ) { |
248 | 17 | O << formatImm(DispSpec.getImm()); |
249 | 17 | } else { |
250 | 0 | assert(DispSpec.isExpr() && "non-immediate displacement?"); |
251 | 0 | DispSpec.getExpr()->print(O, &MAI); |
252 | 0 | } |
253 | 17 | |
254 | 17 | O << ']'; |
255 | 17 | } |
256 | | |
257 | | void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op, |
258 | 1.78k | raw_ostream &O) { |
259 | 1.78k | if (MI->getOperand(Op).isExpr()) |
260 | 1 | return MI->getOperand(Op).getExpr()->print(O, &MAI); |
261 | 1.78k | |
262 | 1.78k | O << formatImm(MI->getOperand(Op).getImm() & 0xff); |
263 | 1.78k | } |