/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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1 | | //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file contains small standalone helper functions and enum definitions for |
11 | | // the X86 target useful for the compiler back-end and the MC libraries. |
12 | | // As such, it deliberately does not include references to LLVM core |
13 | | // code gen types, passes, etc.. |
14 | | // |
15 | | //===----------------------------------------------------------------------===// |
16 | | |
17 | | #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H |
18 | | #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H |
19 | | |
20 | | #include "X86MCTargetDesc.h" |
21 | | #include "llvm/MC/MCInstrDesc.h" |
22 | | #include "llvm/Support/DataTypes.h" |
23 | | #include "llvm/Support/ErrorHandling.h" |
24 | | |
25 | | namespace llvm { |
26 | | |
27 | | namespace X86 { |
28 | | // Enums for memory operand decoding. Each memory operand is represented with |
29 | | // a 5 operand sequence in the form: |
30 | | // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] |
31 | | // These enums help decode this. |
32 | | enum { |
33 | | AddrBaseReg = 0, |
34 | | AddrScaleAmt = 1, |
35 | | AddrIndexReg = 2, |
36 | | AddrDisp = 3, |
37 | | |
38 | | /// AddrSegmentReg - The operand # of the segment in the memory operand. |
39 | | AddrSegmentReg = 4, |
40 | | |
41 | | /// AddrNumOperands - Total number of operands in a memory reference. |
42 | | AddrNumOperands = 5 |
43 | | }; |
44 | | |
45 | | /// AVX512 static rounding constants. These need to match the values in |
46 | | /// avx512fintrin.h. |
47 | | enum STATIC_ROUNDING { |
48 | | TO_NEAREST_INT = 0, |
49 | | TO_NEG_INF = 1, |
50 | | TO_POS_INF = 2, |
51 | | TO_ZERO = 3, |
52 | | CUR_DIRECTION = 4 |
53 | | }; |
54 | | } // end namespace X86; |
55 | | |
56 | | /// X86II - This namespace holds all of the target specific flags that |
57 | | /// instruction info tracks. |
58 | | /// |
59 | | namespace X86II { |
60 | | /// Target Operand Flag enum. |
61 | | enum TOF { |
62 | | //===------------------------------------------------------------------===// |
63 | | // X86 Specific MachineOperand flags. |
64 | | |
65 | | MO_NO_FLAG, |
66 | | |
67 | | /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a |
68 | | /// relocation of: |
69 | | /// SYMBOL_LABEL + [. - PICBASELABEL] |
70 | | MO_GOT_ABSOLUTE_ADDRESS, |
71 | | |
72 | | /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the |
73 | | /// immediate should get the value of the symbol minus the PIC base label: |
74 | | /// SYMBOL_LABEL - PICBASELABEL |
75 | | MO_PIC_BASE_OFFSET, |
76 | | |
77 | | /// MO_GOT - On a symbol operand this indicates that the immediate is the |
78 | | /// offset to the GOT entry for the symbol name from the base of the GOT. |
79 | | /// |
80 | | /// See the X86-64 ELF ABI supplement for more details. |
81 | | /// SYMBOL_LABEL @GOT |
82 | | MO_GOT, |
83 | | |
84 | | /// MO_GOTOFF - On a symbol operand this indicates that the immediate is |
85 | | /// the offset to the location of the symbol name from the base of the GOT. |
86 | | /// |
87 | | /// See the X86-64 ELF ABI supplement for more details. |
88 | | /// SYMBOL_LABEL @GOTOFF |
89 | | MO_GOTOFF, |
90 | | |
91 | | /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is |
92 | | /// offset to the GOT entry for the symbol name from the current code |
93 | | /// location. |
94 | | /// |
95 | | /// See the X86-64 ELF ABI supplement for more details. |
96 | | /// SYMBOL_LABEL @GOTPCREL |
97 | | MO_GOTPCREL, |
98 | | |
99 | | /// MO_PLT - On a symbol operand this indicates that the immediate is |
100 | | /// offset to the PLT entry of symbol name from the current code location. |
101 | | /// |
102 | | /// See the X86-64 ELF ABI supplement for more details. |
103 | | /// SYMBOL_LABEL @PLT |
104 | | MO_PLT, |
105 | | |
106 | | /// MO_TLSGD - On a symbol operand this indicates that the immediate is |
107 | | /// the offset of the GOT entry with the TLS index structure that contains |
108 | | /// the module number and variable offset for the symbol. Used in the |
109 | | /// general dynamic TLS access model. |
110 | | /// |
111 | | /// See 'ELF Handling for Thread-Local Storage' for more details. |
112 | | /// SYMBOL_LABEL @TLSGD |
113 | | MO_TLSGD, |
114 | | |
115 | | /// MO_TLSLD - On a symbol operand this indicates that the immediate is |
116 | | /// the offset of the GOT entry with the TLS index for the module that |
117 | | /// contains the symbol. When this index is passed to a call to |
118 | | /// __tls_get_addr, the function will return the base address of the TLS |
119 | | /// block for the symbol. Used in the x86-64 local dynamic TLS access model. |
120 | | /// |
121 | | /// See 'ELF Handling for Thread-Local Storage' for more details. |
122 | | /// SYMBOL_LABEL @TLSLD |
123 | | MO_TLSLD, |
124 | | |
125 | | /// MO_TLSLDM - On a symbol operand this indicates that the immediate is |
126 | | /// the offset of the GOT entry with the TLS index for the module that |
127 | | /// contains the symbol. When this index is passed to a call to |
128 | | /// ___tls_get_addr, the function will return the base address of the TLS |
129 | | /// block for the symbol. Used in the IA32 local dynamic TLS access model. |
130 | | /// |
131 | | /// See 'ELF Handling for Thread-Local Storage' for more details. |
132 | | /// SYMBOL_LABEL @TLSLDM |
133 | | MO_TLSLDM, |
134 | | |
135 | | /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is |
136 | | /// the offset of the GOT entry with the thread-pointer offset for the |
137 | | /// symbol. Used in the x86-64 initial exec TLS access model. |
138 | | /// |
139 | | /// See 'ELF Handling for Thread-Local Storage' for more details. |
140 | | /// SYMBOL_LABEL @GOTTPOFF |
141 | | MO_GOTTPOFF, |
142 | | |
143 | | /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is |
144 | | /// the absolute address of the GOT entry with the negative thread-pointer |
145 | | /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access |
146 | | /// model. |
147 | | /// |
148 | | /// See 'ELF Handling for Thread-Local Storage' for more details. |
149 | | /// SYMBOL_LABEL @INDNTPOFF |
150 | | MO_INDNTPOFF, |
151 | | |
152 | | /// MO_TPOFF - On a symbol operand this indicates that the immediate is |
153 | | /// the thread-pointer offset for the symbol. Used in the x86-64 local |
154 | | /// exec TLS access model. |
155 | | /// |
156 | | /// See 'ELF Handling for Thread-Local Storage' for more details. |
157 | | /// SYMBOL_LABEL @TPOFF |
158 | | MO_TPOFF, |
159 | | |
160 | | /// MO_DTPOFF - On a symbol operand this indicates that the immediate is |
161 | | /// the offset of the GOT entry with the TLS offset of the symbol. Used |
162 | | /// in the local dynamic TLS access model. |
163 | | /// |
164 | | /// See 'ELF Handling for Thread-Local Storage' for more details. |
165 | | /// SYMBOL_LABEL @DTPOFF |
166 | | MO_DTPOFF, |
167 | | |
168 | | /// MO_NTPOFF - On a symbol operand this indicates that the immediate is |
169 | | /// the negative thread-pointer offset for the symbol. Used in the IA32 |
170 | | /// local exec TLS access model. |
171 | | /// |
172 | | /// See 'ELF Handling for Thread-Local Storage' for more details. |
173 | | /// SYMBOL_LABEL @NTPOFF |
174 | | MO_NTPOFF, |
175 | | |
176 | | /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is |
177 | | /// the offset of the GOT entry with the negative thread-pointer offset for |
178 | | /// the symbol. Used in the PIC IA32 initial exec TLS access model. |
179 | | /// |
180 | | /// See 'ELF Handling for Thread-Local Storage' for more details. |
181 | | /// SYMBOL_LABEL @GOTNTPOFF |
182 | | MO_GOTNTPOFF, |
183 | | |
184 | | /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the |
185 | | /// reference is actually to the "__imp_FOO" symbol. This is used for |
186 | | /// dllimport linkage on windows. |
187 | | MO_DLLIMPORT, |
188 | | |
189 | | /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the |
190 | | /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a |
191 | | /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. |
192 | | MO_DARWIN_NONLAZY, |
193 | | |
194 | | /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates |
195 | | /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is |
196 | | /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. |
197 | | MO_DARWIN_NONLAZY_PIC_BASE, |
198 | | |
199 | | /// MO_TLVP - On a symbol operand this indicates that the immediate is |
200 | | /// some TLS offset. |
201 | | /// |
202 | | /// This is the TLS offset for the Darwin TLS mechanism. |
203 | | MO_TLVP, |
204 | | |
205 | | /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate |
206 | | /// is some TLS offset from the picbase. |
207 | | /// |
208 | | /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. |
209 | | MO_TLVP_PIC_BASE, |
210 | | |
211 | | /// MO_SECREL - On a symbol operand this indicates that the immediate is |
212 | | /// the offset from beginning of section. |
213 | | /// |
214 | | /// This is the TLS offset for the COFF/Windows TLS mechanism. |
215 | | MO_SECREL, |
216 | | |
217 | | /// MO_ABS8 - On a symbol operand this indicates that the symbol is known |
218 | | /// to be an absolute symbol in range [0,128), so we can use the @ABS8 |
219 | | /// symbol modifier. |
220 | | MO_ABS8, |
221 | | }; |
222 | | |
223 | | enum : uint64_t { |
224 | | //===------------------------------------------------------------------===// |
225 | | // Instruction encodings. These are the standard/most common forms for X86 |
226 | | // instructions. |
227 | | // |
228 | | |
229 | | // PseudoFrm - This represents an instruction that is a pseudo instruction |
230 | | // or one that has not been implemented yet. It is illegal to code generate |
231 | | // it, but tolerated for intermediate implementation stages. |
232 | | Pseudo = 0, |
233 | | |
234 | | /// Raw - This form is for instructions that don't have any operands, so |
235 | | /// they are just a fixed opcode value, like 'leave'. |
236 | | RawFrm = 1, |
237 | | |
238 | | /// AddRegFrm - This form is used for instructions like 'push r32' that have |
239 | | /// their one register operand added to their opcode. |
240 | | AddRegFrm = 2, |
241 | | |
242 | | /// RawFrmMemOffs - This form is for instructions that store an absolute |
243 | | /// memory offset as an immediate with a possible segment override. |
244 | | RawFrmMemOffs = 3, |
245 | | |
246 | | /// RawFrmSrc - This form is for instructions that use the source index |
247 | | /// register SI/ESI/RSI with a possible segment override. |
248 | | RawFrmSrc = 4, |
249 | | |
250 | | /// RawFrmDst - This form is for instructions that use the destination index |
251 | | /// register DI/EDI/ESI. |
252 | | RawFrmDst = 5, |
253 | | |
254 | | /// RawFrmSrc - This form is for instructions that use the source index |
255 | | /// register SI/ESI/ERI with a possible segment override, and also the |
256 | | /// destination index register DI/ESI/RDI. |
257 | | RawFrmDstSrc = 6, |
258 | | |
259 | | /// RawFrmImm8 - This is used for the ENTER instruction, which has two |
260 | | /// immediates, the first of which is a 16-bit immediate (specified by |
261 | | /// the imm encoding) and the second is a 8-bit fixed value. |
262 | | RawFrmImm8 = 7, |
263 | | |
264 | | /// RawFrmImm16 - This is used for CALL FAR instructions, which have two |
265 | | /// immediates, the first of which is a 16 or 32-bit immediate (specified by |
266 | | /// the imm encoding) and the second is a 16-bit fixed value. In the AMD |
267 | | /// manual, this operand is described as pntr16:32 and pntr16:16 |
268 | | RawFrmImm16 = 8, |
269 | | |
270 | | /// MRM[0-7][rm] - These forms are used to represent instructions that use |
271 | | /// a Mod/RM byte, and use the middle field to hold extended opcode |
272 | | /// information. In the intel manual these are represented as /0, /1, ... |
273 | | /// |
274 | | |
275 | | /// MRMDestMem - This form is used for instructions that use the Mod/RM byte |
276 | | /// to specify a destination, which in this case is memory. |
277 | | /// |
278 | | MRMDestMem = 32, |
279 | | |
280 | | /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte |
281 | | /// to specify a source, which in this case is memory. |
282 | | /// |
283 | | MRMSrcMem = 33, |
284 | | |
285 | | /// MRMSrcMem4VOp3 - This form is used for instructions that encode |
286 | | /// operand 3 with VEX.VVVV and load from memory. |
287 | | /// |
288 | | MRMSrcMem4VOp3 = 34, |
289 | | |
290 | | /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM |
291 | | /// byte to specify the fourth source, which in this case is memory. |
292 | | /// |
293 | | MRMSrcMemOp4 = 35, |
294 | | |
295 | | /// MRMXm - This form is used for instructions that use the Mod/RM byte |
296 | | /// to specify a memory source, but doesn't use the middle field. |
297 | | /// |
298 | | MRMXm = 39, // Instruction that uses Mod/RM but not the middle field. |
299 | | |
300 | | // Next, instructions that operate on a memory r/m operand... |
301 | | MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43, // Format /0 /1 /2 /3 |
302 | | MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47, // Format /4 /5 /6 /7 |
303 | | |
304 | | /// MRMDestReg - This form is used for instructions that use the Mod/RM byte |
305 | | /// to specify a destination, which in this case is a register. |
306 | | /// |
307 | | MRMDestReg = 48, |
308 | | |
309 | | /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte |
310 | | /// to specify a source, which in this case is a register. |
311 | | /// |
312 | | MRMSrcReg = 49, |
313 | | |
314 | | /// MRMSrcReg4VOp3 - This form is used for instructions that encode |
315 | | /// operand 3 with VEX.VVVV and do not load from memory. |
316 | | /// |
317 | | MRMSrcReg4VOp3 = 50, |
318 | | |
319 | | /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM |
320 | | /// byte to specify the fourth source, which in this case is a register. |
321 | | /// |
322 | | MRMSrcRegOp4 = 51, |
323 | | |
324 | | /// MRMXr - This form is used for instructions that use the Mod/RM byte |
325 | | /// to specify a register source, but doesn't use the middle field. |
326 | | /// |
327 | | MRMXr = 55, // Instruction that uses Mod/RM but not the middle field. |
328 | | |
329 | | // Instructions that operate on a register r/m operand... |
330 | | MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3 |
331 | | MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7 |
332 | | |
333 | | /// MRM_XX - A mod/rm byte of exactly 0xXX. |
334 | | MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67, |
335 | | MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71, |
336 | | MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75, |
337 | | MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79, |
338 | | MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83, |
339 | | MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87, |
340 | | MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91, |
341 | | MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95, |
342 | | MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99, |
343 | | MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103, |
344 | | MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107, |
345 | | MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111, |
346 | | MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115, |
347 | | MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119, |
348 | | MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123, |
349 | | MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127, |
350 | | |
351 | | FormMask = 127, |
352 | | |
353 | | //===------------------------------------------------------------------===// |
354 | | // Actual flags... |
355 | | |
356 | | // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix. |
357 | | // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in |
358 | | // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66 |
359 | | // prefix in 16-bit mode. |
360 | | OpSizeShift = 7, |
361 | | OpSizeMask = 0x3 << OpSizeShift, |
362 | | |
363 | | OpSizeFixed = 0 << OpSizeShift, |
364 | | OpSize16 = 1 << OpSizeShift, |
365 | | OpSize32 = 2 << OpSizeShift, |
366 | | |
367 | | // AsSize - AdSizeX implies this instruction determines its need of 0x67 |
368 | | // prefix from a normal ModRM memory operand. The other types indicate that |
369 | | // an operand is encoded with a specific width and a prefix is needed if |
370 | | // it differs from the current mode. |
371 | | AdSizeShift = OpSizeShift + 2, |
372 | | AdSizeMask = 0x3 << AdSizeShift, |
373 | | |
374 | | AdSizeX = 1 << AdSizeShift, |
375 | | AdSize16 = 1 << AdSizeShift, |
376 | | AdSize32 = 2 << AdSizeShift, |
377 | | AdSize64 = 3 << AdSizeShift, |
378 | | |
379 | | //===------------------------------------------------------------------===// |
380 | | // OpPrefix - There are several prefix bytes that are used as opcode |
381 | | // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is |
382 | | // no prefix. |
383 | | // |
384 | | OpPrefixShift = AdSizeShift + 2, |
385 | | OpPrefixMask = 0x7 << OpPrefixShift, |
386 | | |
387 | | // PS, PD - Prefix code for packed single and double precision vector |
388 | | // floating point operations performed in the SSE registers. |
389 | | PS = 1 << OpPrefixShift, PD = 2 << OpPrefixShift, |
390 | | |
391 | | // XS, XD - These prefix codes are for single and double precision scalar |
392 | | // floating point operations performed in the SSE registers. |
393 | | XS = 3 << OpPrefixShift, XD = 4 << OpPrefixShift, |
394 | | |
395 | | //===------------------------------------------------------------------===// |
396 | | // OpMap - This field determines which opcode map this instruction |
397 | | // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc. |
398 | | // |
399 | | OpMapShift = OpPrefixShift + 3, |
400 | | OpMapMask = 0x7 << OpMapShift, |
401 | | |
402 | | // OB - OneByte - Set if this instruction has a one byte opcode. |
403 | | OB = 0 << OpMapShift, |
404 | | |
405 | | // TB - TwoByte - Set if this instruction has a two byte opcode, which |
406 | | // starts with a 0x0F byte before the real opcode. |
407 | | TB = 1 << OpMapShift, |
408 | | |
409 | | // T8, TA - Prefix after the 0x0F prefix. |
410 | | T8 = 2 << OpMapShift, TA = 3 << OpMapShift, |
411 | | |
412 | | // XOP8 - Prefix to include use of imm byte. |
413 | | XOP8 = 4 << OpMapShift, |
414 | | |
415 | | // XOP9 - Prefix to exclude use of imm byte. |
416 | | XOP9 = 5 << OpMapShift, |
417 | | |
418 | | // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. |
419 | | XOPA = 6 << OpMapShift, |
420 | | |
421 | | //===------------------------------------------------------------------===// |
422 | | // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. |
423 | | // They are used to specify GPRs and SSE registers, 64-bit operand size, |
424 | | // etc. We only cares about REX.W and REX.R bits and only the former is |
425 | | // statically determined. |
426 | | // |
427 | | REXShift = OpMapShift + 3, |
428 | | REX_W = 1 << REXShift, |
429 | | |
430 | | //===------------------------------------------------------------------===// |
431 | | // This three-bit field describes the size of an immediate operand. Zero is |
432 | | // unused so that we can tell if we forgot to set a value. |
433 | | ImmShift = REXShift + 1, |
434 | | ImmMask = 15 << ImmShift, |
435 | | Imm8 = 1 << ImmShift, |
436 | | Imm8PCRel = 2 << ImmShift, |
437 | | Imm8Reg = 3 << ImmShift, |
438 | | Imm16 = 4 << ImmShift, |
439 | | Imm16PCRel = 5 << ImmShift, |
440 | | Imm32 = 6 << ImmShift, |
441 | | Imm32PCRel = 7 << ImmShift, |
442 | | Imm32S = 8 << ImmShift, |
443 | | Imm64 = 9 << ImmShift, |
444 | | |
445 | | //===------------------------------------------------------------------===// |
446 | | // FP Instruction Classification... Zero is non-fp instruction. |
447 | | |
448 | | // FPTypeMask - Mask for all of the FP types... |
449 | | FPTypeShift = ImmShift + 4, |
450 | | FPTypeMask = 7 << FPTypeShift, |
451 | | |
452 | | // NotFP - The default, set for instructions that do not use FP registers. |
453 | | NotFP = 0 << FPTypeShift, |
454 | | |
455 | | // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 |
456 | | ZeroArgFP = 1 << FPTypeShift, |
457 | | |
458 | | // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst |
459 | | OneArgFP = 2 << FPTypeShift, |
460 | | |
461 | | // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a |
462 | | // result back to ST(0). For example, fcos, fsqrt, etc. |
463 | | // |
464 | | OneArgFPRW = 3 << FPTypeShift, |
465 | | |
466 | | // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an |
467 | | // explicit argument, storing the result to either ST(0) or the implicit |
468 | | // argument. For example: fadd, fsub, fmul, etc... |
469 | | TwoArgFP = 4 << FPTypeShift, |
470 | | |
471 | | // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an |
472 | | // explicit argument, but have no destination. Example: fucom, fucomi, ... |
473 | | CompareFP = 5 << FPTypeShift, |
474 | | |
475 | | // CondMovFP - "2 operand" floating point conditional move instructions. |
476 | | CondMovFP = 6 << FPTypeShift, |
477 | | |
478 | | // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. |
479 | | SpecialFP = 7 << FPTypeShift, |
480 | | |
481 | | // Lock prefix |
482 | | LOCKShift = FPTypeShift + 3, |
483 | | LOCK = 1 << LOCKShift, |
484 | | |
485 | | // REP prefix |
486 | | REPShift = LOCKShift + 1, |
487 | | REP = 1 << REPShift, |
488 | | |
489 | | // Execution domain for SSE instructions. |
490 | | // 0 means normal, non-SSE instruction. |
491 | | SSEDomainShift = REPShift + 1, |
492 | | |
493 | | // Encoding |
494 | | EncodingShift = SSEDomainShift + 2, |
495 | | EncodingMask = 0x3 << EncodingShift, |
496 | | |
497 | | // VEX - encoding using 0xC4/0xC5 |
498 | | VEX = 1 << EncodingShift, |
499 | | |
500 | | /// XOP - Opcode prefix used by XOP instructions. |
501 | | XOP = 2 << EncodingShift, |
502 | | |
503 | | // VEX_EVEX - Specifies that this instruction use EVEX form which provides |
504 | | // syntax support up to 32 512-bit register operands and up to 7 16-bit |
505 | | // mask operands as well as source operand data swizzling/memory operand |
506 | | // conversion, eviction hint, and rounding mode. |
507 | | EVEX = 3 << EncodingShift, |
508 | | |
509 | | // Opcode |
510 | | OpcodeShift = EncodingShift + 2, |
511 | | |
512 | | /// VEX_W - Has a opcode specific functionality, but is used in the same |
513 | | /// way as REX_W is for regular SSE instructions. |
514 | | VEX_WShift = OpcodeShift + 8, |
515 | | VEX_W = 1ULL << VEX_WShift, |
516 | | |
517 | | /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 |
518 | | /// address instructions in SSE are represented as 3 address ones in AVX |
519 | | /// and the additional register is encoded in VEX_VVVV prefix. |
520 | | VEX_4VShift = VEX_WShift + 1, |
521 | | VEX_4V = 1ULL << VEX_4VShift, |
522 | | |
523 | | /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current |
524 | | /// instruction uses 256-bit wide registers. This is usually auto detected |
525 | | /// if a VR256 register is used, but some AVX instructions also have this |
526 | | /// field marked when using a f256 memory references. |
527 | | VEX_LShift = VEX_4VShift + 1, |
528 | | VEX_L = 1ULL << VEX_LShift, |
529 | | |
530 | | // EVEX_K - Set if this instruction requires masking |
531 | | EVEX_KShift = VEX_LShift + 1, |
532 | | EVEX_K = 1ULL << EVEX_KShift, |
533 | | |
534 | | // EVEX_Z - Set if this instruction has EVEX.Z field set. |
535 | | EVEX_ZShift = EVEX_KShift + 1, |
536 | | EVEX_Z = 1ULL << EVEX_ZShift, |
537 | | |
538 | | // EVEX_L2 - Set if this instruction has EVEX.L' field set. |
539 | | EVEX_L2Shift = EVEX_ZShift + 1, |
540 | | EVEX_L2 = 1ULL << EVEX_L2Shift, |
541 | | |
542 | | // EVEX_B - Set if this instruction has EVEX.B field set. |
543 | | EVEX_BShift = EVEX_L2Shift + 1, |
544 | | EVEX_B = 1ULL << EVEX_BShift, |
545 | | |
546 | | // The scaling factor for the AVX512's 8-bit compressed displacement. |
547 | | CD8_Scale_Shift = EVEX_BShift + 1, |
548 | | CD8_Scale_Mask = 127ULL << CD8_Scale_Shift, |
549 | | |
550 | | /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the |
551 | | /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents |
552 | | /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction |
553 | | /// storing a classifier in the imm8 field. To simplify our implementation, |
554 | | /// we handle this by storeing the classifier in the opcode field and using |
555 | | /// this flag to indicate that the encoder should do the wacky 3DNow! thing. |
556 | | Has3DNow0F0FOpcodeShift = CD8_Scale_Shift + 7, |
557 | | Has3DNow0F0FOpcode = 1ULL << Has3DNow0F0FOpcodeShift, |
558 | | |
559 | | /// Explicitly specified rounding control |
560 | | EVEX_RCShift = Has3DNow0F0FOpcodeShift + 1, |
561 | | EVEX_RC = 1ULL << EVEX_RCShift |
562 | | }; |
563 | | |
564 | | // getBaseOpcodeFor - This function returns the "base" X86 opcode for the |
565 | | // specified machine instruction. |
566 | | // |
567 | 461k | inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { |
568 | 461k | return TSFlags >> X86II::OpcodeShift; |
569 | 461k | } |
570 | | |
571 | 13.3k | inline bool hasImm(uint64_t TSFlags) { |
572 | 13.3k | return (TSFlags & X86II::ImmMask) != 0; |
573 | 13.3k | } |
574 | | |
575 | | /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field |
576 | | /// of the specified instruction. |
577 | 307k | inline unsigned getSizeOfImm(uint64_t TSFlags) { |
578 | 307k | switch (TSFlags & X86II::ImmMask) { |
579 | 0 | default: 0 llvm_unreachable0 ("Unknown immediate size"); |
580 | 191k | case X86II::Imm8: |
581 | 191k | case X86II::Imm8PCRel: |
582 | 191k | case X86II::Imm8Reg: return 1; |
583 | 788 | case X86II::Imm16: |
584 | 788 | case X86II::Imm16PCRel: return 2; |
585 | 112k | case X86II::Imm32: |
586 | 112k | case X86II::Imm32S: |
587 | 112k | case X86II::Imm32PCRel: return 4; |
588 | 2.78k | case X86II::Imm64: return 8; |
589 | 307k | } |
590 | 307k | } |
591 | | |
592 | | /// isImmPCRel - Return true if the immediate of the specified instruction's |
593 | | /// TSFlags indicates that it is pc relative. |
594 | 153k | inline unsigned isImmPCRel(uint64_t TSFlags) { |
595 | 153k | switch (TSFlags & X86II::ImmMask) { |
596 | 0 | default: 0 llvm_unreachable0 ("Unknown immediate size"); |
597 | 72.7k | case X86II::Imm8PCRel: |
598 | 72.7k | case X86II::Imm16PCRel: |
599 | 72.7k | case X86II::Imm32PCRel: |
600 | 72.7k | return true; |
601 | 80.5k | case X86II::Imm8: |
602 | 80.5k | case X86II::Imm8Reg: |
603 | 80.5k | case X86II::Imm16: |
604 | 80.5k | case X86II::Imm32: |
605 | 80.5k | case X86II::Imm32S: |
606 | 80.5k | case X86II::Imm64: |
607 | 80.5k | return false; |
608 | 153k | } |
609 | 153k | } |
610 | | |
611 | | /// isImmSigned - Return true if the immediate of the specified instruction's |
612 | | /// TSFlags indicates that it is signed. |
613 | 153k | inline unsigned isImmSigned(uint64_t TSFlags) { |
614 | 153k | switch (TSFlags & X86II::ImmMask) { |
615 | 0 | default: 0 llvm_unreachable0 ("Unknown immediate signedness"); |
616 | 3.47k | case X86II::Imm32S: |
617 | 3.47k | return true; |
618 | 149k | case X86II::Imm8: |
619 | 149k | case X86II::Imm8PCRel: |
620 | 149k | case X86II::Imm8Reg: |
621 | 149k | case X86II::Imm16: |
622 | 149k | case X86II::Imm16PCRel: |
623 | 149k | case X86II::Imm32: |
624 | 149k | case X86II::Imm32PCRel: |
625 | 149k | case X86II::Imm64: |
626 | 149k | return false; |
627 | 153k | } |
628 | 153k | } |
629 | | |
630 | | /// getOperandBias - compute any additional adjustment needed to |
631 | | /// the offset to the start of the memory operand |
632 | | /// in this instruction. |
633 | | /// If this is a two-address instruction,skip one of the register operands. |
634 | | /// FIXME: This should be handled during MCInst lowering. |
635 | | inline unsigned getOperandBias(const MCInstrDesc& Desc) |
636 | 732k | { |
637 | 732k | unsigned NumOps = Desc.getNumOperands(); |
638 | 732k | if (NumOps > 1 && 732k Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0493k ) |
639 | 131k | return 1; |
640 | 600k | if (600k NumOps > 3 && 600k Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0204k && |
641 | 564 | Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) |
642 | 600k | // Special case for AVX-512 GATHER with 2 TIED_TO operands |
643 | 600k | // Skip the first 2 operands: dst, mask_wb |
644 | 432 | return 2; |
645 | 600k | if (600k NumOps > 3 && 600k Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0204k && |
646 | 132 | Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1) |
647 | 600k | // Special case for GATHER with 2 TIED_TO operands |
648 | 600k | // Skip the first 2 operands: dst, mask_wb |
649 | 132 | return 2; |
650 | 600k | if (600k NumOps > 2 && 600k Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0219k ) |
651 | 600k | // SCATTER |
652 | 640 | return 1; |
653 | 599k | return 0; |
654 | 732k | } |
655 | | |
656 | | /// getMemoryOperandNo - The function returns the MCInst operand # for the |
657 | | /// first field of the memory operand. If the instruction doesn't have a |
658 | | /// memory operand, this returns -1. |
659 | | /// |
660 | | /// Note that this ignores tied operands. If there is a tied register which |
661 | | /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only |
662 | | /// counted as one operand. |
663 | | /// |
664 | 464k | inline int getMemoryOperandNo(uint64_t TSFlags) { |
665 | 464k | bool HasVEX_4V = TSFlags & X86II::VEX_4V; |
666 | 464k | bool HasEVEX_K = TSFlags & X86II::EVEX_K; |
667 | 464k | |
668 | 464k | switch (TSFlags & X86II::FormMask) { |
669 | 0 | default: 0 llvm_unreachable0 ("Unknown FormMask value in getMemoryOperandNo!"); |
670 | 167k | case X86II::Pseudo: |
671 | 167k | case X86II::RawFrm: |
672 | 167k | case X86II::AddRegFrm: |
673 | 167k | case X86II::RawFrmImm8: |
674 | 167k | case X86II::RawFrmImm16: |
675 | 167k | case X86II::RawFrmMemOffs: |
676 | 167k | case X86II::RawFrmSrc: |
677 | 167k | case X86II::RawFrmDst: |
678 | 167k | case X86II::RawFrmDstSrc: |
679 | 167k | return -1; |
680 | 25.9k | case X86II::MRMDestMem: |
681 | 25.9k | return 0; |
682 | 87.3k | case X86II::MRMSrcMem: |
683 | 87.3k | // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a |
684 | 87.3k | // mask register. |
685 | 87.3k | return 1 + HasVEX_4V + HasEVEX_K; |
686 | 96 | case X86II::MRMSrcMem4VOp3: |
687 | 96 | // Skip registers encoded in reg. |
688 | 96 | return 1 + HasEVEX_K; |
689 | 49 | case X86II::MRMSrcMemOp4: |
690 | 49 | // Skip registers encoded in reg, VEX_VVVV, and I8IMM. |
691 | 49 | return 3; |
692 | 163k | case X86II::MRMDestReg: |
693 | 163k | case X86II::MRMSrcReg: |
694 | 163k | case X86II::MRMSrcReg4VOp3: |
695 | 163k | case X86II::MRMSrcRegOp4: |
696 | 163k | case X86II::MRMXr: |
697 | 163k | case X86II::MRM0r: 163k case X86II::MRM1r: |
698 | 163k | case X86II::MRM2r: 163k case X86II::MRM3r: |
699 | 163k | case X86II::MRM4r: 163k case X86II::MRM5r: |
700 | 163k | case X86II::MRM6r: 163k case X86II::MRM7r: |
701 | 163k | return -1; |
702 | 18.3k | case X86II::MRMXm: |
703 | 18.3k | case X86II::MRM0m: 18.3k case X86II::MRM1m: |
704 | 18.3k | case X86II::MRM2m: 18.3k case X86II::MRM3m: |
705 | 18.3k | case X86II::MRM4m: 18.3k case X86II::MRM5m: |
706 | 18.3k | case X86II::MRM6m: 18.3k case X86II::MRM7m: |
707 | 18.3k | // Start from 0, skip registers encoded in VEX_VVVV or a mask register. |
708 | 18.3k | return 0 + HasVEX_4V + HasEVEX_K; |
709 | 1.59k | case X86II::MRM_C0: 1.59k case X86II::MRM_C1: 1.59k case X86II::MRM_C2: |
710 | 1.59k | case X86II::MRM_C3: 1.59k case X86II::MRM_C4: 1.59k case X86II::MRM_C5: |
711 | 1.59k | case X86II::MRM_C6: 1.59k case X86II::MRM_C7: 1.59k case X86II::MRM_C8: |
712 | 1.59k | case X86II::MRM_C9: 1.59k case X86II::MRM_CA: 1.59k case X86II::MRM_CB: |
713 | 1.59k | case X86II::MRM_CC: 1.59k case X86II::MRM_CD: 1.59k case X86II::MRM_CE: |
714 | 1.59k | case X86II::MRM_CF: 1.59k case X86II::MRM_D0: 1.59k case X86II::MRM_D1: |
715 | 1.59k | case X86II::MRM_D2: 1.59k case X86II::MRM_D3: 1.59k case X86II::MRM_D4: |
716 | 1.59k | case X86II::MRM_D5: 1.59k case X86II::MRM_D6: 1.59k case X86II::MRM_D7: |
717 | 1.59k | case X86II::MRM_D8: 1.59k case X86II::MRM_D9: 1.59k case X86II::MRM_DA: |
718 | 1.59k | case X86II::MRM_DB: 1.59k case X86II::MRM_DC: 1.59k case X86II::MRM_DD: |
719 | 1.59k | case X86II::MRM_DE: 1.59k case X86II::MRM_DF: 1.59k case X86II::MRM_E0: |
720 | 1.59k | case X86II::MRM_E1: 1.59k case X86II::MRM_E2: 1.59k case X86II::MRM_E3: |
721 | 1.59k | case X86II::MRM_E4: 1.59k case X86II::MRM_E5: 1.59k case X86II::MRM_E6: |
722 | 1.59k | case X86II::MRM_E7: 1.59k case X86II::MRM_E8: 1.59k case X86II::MRM_E9: |
723 | 1.59k | case X86II::MRM_EA: 1.59k case X86II::MRM_EB: 1.59k case X86II::MRM_EC: |
724 | 1.59k | case X86II::MRM_ED: 1.59k case X86II::MRM_EE: 1.59k case X86II::MRM_EF: |
725 | 1.59k | case X86II::MRM_F0: 1.59k case X86II::MRM_F1: 1.59k case X86II::MRM_F2: |
726 | 1.59k | case X86II::MRM_F3: 1.59k case X86II::MRM_F4: 1.59k case X86II::MRM_F5: |
727 | 1.59k | case X86II::MRM_F6: 1.59k case X86II::MRM_F7: 1.59k case X86II::MRM_F8: |
728 | 1.59k | case X86II::MRM_F9: 1.59k case X86II::MRM_FA: 1.59k case X86II::MRM_FB: |
729 | 1.59k | case X86II::MRM_FC: 1.59k case X86II::MRM_FD: 1.59k case X86II::MRM_FE: |
730 | 1.59k | case X86II::MRM_FF: |
731 | 1.59k | return -1; |
732 | 464k | } |
733 | 464k | } |
734 | | |
735 | | /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or |
736 | | /// higher) register? e.g. r8, xmm8, xmm13, etc. |
737 | 23.8k | inline bool isX86_64ExtendedReg(unsigned RegNo) { |
738 | 23.8k | if ((RegNo >= X86::XMM8 && 23.8k RegNo <= X86::XMM312.14k ) || |
739 | 23.8k | (RegNo >= X86::YMM8 && 23.8k RegNo <= X86::YMM3111 ) || |
740 | 23.8k | (RegNo >= X86::ZMM8 && 23.8k RegNo <= X86::ZMM310 )) |
741 | 22 | return true; |
742 | 23.8k | |
743 | 23.8k | switch (RegNo) { |
744 | 23.7k | default: break; |
745 | 40 | case X86::R8: 40 case X86::R9: 40 case X86::R10: 40 case X86::R11: |
746 | 40 | case X86::R12: 40 case X86::R13: 40 case X86::R14: 40 case X86::R15: |
747 | 40 | case X86::R8D: 40 case X86::R9D: 40 case X86::R10D: 40 case X86::R11D: |
748 | 40 | case X86::R12D: 40 case X86::R13D: 40 case X86::R14D: 40 case X86::R15D: |
749 | 40 | case X86::R8W: 40 case X86::R9W: 40 case X86::R10W: 40 case X86::R11W: |
750 | 40 | case X86::R12W: 40 case X86::R13W: 40 case X86::R14W: 40 case X86::R15W: |
751 | 40 | case X86::R8B: 40 case X86::R9B: 40 case X86::R10B: 40 case X86::R11B: |
752 | 40 | case X86::R12B: 40 case X86::R13B: 40 case X86::R14B: 40 case X86::R15B: |
753 | 40 | case X86::CR8: 40 case X86::CR9: 40 case X86::CR10: 40 case X86::CR11: |
754 | 40 | case X86::CR12: 40 case X86::CR13: 40 case X86::CR14: 40 case X86::CR15: |
755 | 40 | case X86::DR8: 40 case X86::DR9: 40 case X86::DR10: 40 case X86::DR11: |
756 | 40 | case X86::DR12: 40 case X86::DR13: 40 case X86::DR14: 40 case X86::DR15: |
757 | 40 | return true; |
758 | 23.8k | } |
759 | 23.7k | return false; |
760 | 23.8k | } |
761 | | |
762 | | /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) |
763 | | /// registers? e.g. zmm21, etc. |
764 | 9.94k | static inline bool is32ExtendedReg(unsigned RegNo) { |
765 | 1.11k | return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) || |
766 | 9.94k | (RegNo >= X86::YMM16 && 9.94k RegNo <= X86::YMM3188 ) || |
767 | 9.94k | (RegNo >= X86::ZMM16 && 9.94k RegNo <= X86::ZMM3188 )); |
768 | 9.94k | } Unexecuted instantiation: X86AsmPrinter.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86CallFrameOptimization.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86CallLowering.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86CmovConversion.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86ExpandPseudo.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86FastISel.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86FixupBWInsts.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86FixupLEAs.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86FixupSetCC.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86FloatingPoint.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86FrameLowering.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86InstructionSelector.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86ISelDAGToDAG.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86ISelLowering.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86InterleavedAccess.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86InstrFMA3Info.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86InstrInfo.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86EvexToVex.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86LegalizerInfo.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86MCInstLower.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86MacroFusion.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86OptimizeLEAs.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86PadShortFunction.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86RegisterBankInfo.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86RegisterInfo.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86SelectionDAGInfo.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86Subtarget.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86TargetMachine.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86TargetTransformInfo.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86VZeroUpper.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86WinAllocaExpander.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86CallingConv.cpp:llvm::X86II::is32ExtendedReg(unsigned int) X86AsmParser.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Line | Count | Source | 764 | 9.94k | static inline bool is32ExtendedReg(unsigned RegNo) { | 765 | 1.11k | return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) || | 766 | 9.94k | (RegNo >= X86::YMM16 && 9.94k RegNo <= X86::YMM3188 ) || | 767 | 9.94k | (RegNo >= X86::ZMM16 && 9.94k RegNo <= X86::ZMM3188 )); | 768 | 9.94k | } |
Unexecuted instantiation: X86ATTInstPrinter.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86IntelInstPrinter.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86AsmBackend.cpp:llvm::X86II::is32ExtendedReg(unsigned int) Unexecuted instantiation: X86MCCodeEmitter.cpp:llvm::X86II::is32ExtendedReg(unsigned int) |
769 | | |
770 | | |
771 | 411k | inline bool isX86_64NonExtLowByteReg(unsigned reg) { |
772 | 411k | return (reg == X86::SPL || reg == X86::BPL || |
773 | 411k | reg == X86::SIL411k || reg == X86::DIL410k ); |
774 | 411k | } |
775 | | |
776 | | /// isKMasked - Is this a masked instruction. |
777 | 15.4k | inline bool isKMasked(uint64_t TSFlags) { |
778 | 15.4k | return (TSFlags & X86II::EVEX_K) != 0; |
779 | 15.4k | } |
780 | | |
781 | | /// isKMergedMasked - Is this a merge masked instruction. |
782 | 1.65k | inline bool isKMergeMasked(uint64_t TSFlags) { |
783 | 1.65k | return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0; |
784 | 1.65k | } |
785 | | } |
786 | | |
787 | | } // end namespace llvm; |
788 | | |
789 | | #endif |