Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/X86/X86SelectionDAGInfo.h
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//===-- X86SelectionDAGInfo.h - X86 SelectionDAG Info -----------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86 subclass for SelectionDAGTargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86SELECTIONDAGINFO_H
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#define LLVM_LIB_TARGET_X86_X86SELECTIONDAGINFO_H
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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namespace llvm {
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class X86TargetLowering;
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class X86TargetMachine;
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class X86Subtarget;
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class X86SelectionDAGInfo : public SelectionDAGTargetInfo {
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  /// Returns true if it is possible for the base register to conflict with the
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  /// given set of clobbers for a memory intrinsic.
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  bool isBaseRegConflictPossible(SelectionDAG &DAG,
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                                 ArrayRef<MCPhysReg> ClobberSet) const;
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public:
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  explicit X86SelectionDAGInfo() = default;
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  SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,
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                                  SDValue Chain, SDValue Dst, SDValue Src,
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                                  SDValue Size, unsigned Align, bool isVolatile,
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                                  MachinePointerInfo DstPtrInfo) const override;
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  SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
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                                  SDValue Chain, SDValue Dst, SDValue Src,
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                                  SDValue Size, unsigned Align, bool isVolatile,
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                                  bool AlwaysInline,
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                                  MachinePointerInfo DstPtrInfo,
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                                  MachinePointerInfo SrcPtrInfo) const override;
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};
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}
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#endif