Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/X86/X86Subtarget.h
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//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the X86 specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
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#define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
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#include "X86FrameLowering.h"
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#include "X86ISelLowering.h"
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#include "X86InstrInfo.h"
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#include "X86SelectionDAGInfo.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <memory>
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#define GET_SUBTARGETINFO_HEADER
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#include "X86GenSubtargetInfo.inc"
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namespace llvm {
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class GlobalValue;
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/// The X86 backend supports a number of different styles of PIC.
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///
42
namespace PICStyles {
43
44
enum Style {
45
  StubPIC,          // Used on i386-darwin in pic mode.
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  GOT,              // Used on 32 bit elf on when in pic mode.
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  RIPRel,           // Used on X86-64 when in pic mode.
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  None              // Set when not in pic mode.
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};
50
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} // end namespace PICStyles
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class X86Subtarget final : public X86GenSubtargetInfo {
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protected:
55
  enum X86SSEEnum {
56
    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
57
  };
58
59
  enum X863DNowEnum {
60
    NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
61
  };
62
63
  enum X86ProcFamilyEnum {
64
    Others, 
65
    IntelAtom,
66
    IntelSLM,
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    IntelGLM,
68
    IntelHaswell,
69
    IntelBroadwell,
70
    IntelSkylake,
71
    IntelKNL,
72
    IntelSKX,
73
    IntelCannonlake
74
  };
75
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  /// X86 processor family: Intel Atom, and others
77
  X86ProcFamilyEnum X86ProcFamily;
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  /// Which PIC style to use
80
  PICStyles::Style PICStyle;
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  const TargetMachine &TM;
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84
  /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
85
  X86SSEEnum X86SSELevel;
86
87
  /// MMX, 3DNow, 3DNow Athlon, or none supported.
88
  X863DNowEnum X863DNowLevel;
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90
  /// True if the processor supports X87 instructions.
91
  bool HasX87;
92
93
  /// True if this processor has conditional move instructions
94
  /// (generally pentium pro+).
95
  bool HasCMov;
96
97
  /// True if the processor supports X86-64 instructions.
98
  bool HasX86_64;
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100
  /// True if the processor supports POPCNT.
101
  bool HasPOPCNT;
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103
  /// True if the processor supports SSE4A instructions.
104
  bool HasSSE4A;
105
106
  /// Target has AES instructions
107
  bool HasAES;
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109
  /// Target has FXSAVE/FXRESTOR instructions
110
  bool HasFXSR;
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112
  /// Target has XSAVE instructions
113
  bool HasXSAVE;
114
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  /// Target has XSAVEOPT instructions
116
  bool HasXSAVEOPT;
117
118
  /// Target has XSAVEC instructions
119
  bool HasXSAVEC;
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121
  /// Target has XSAVES instructions
122
  bool HasXSAVES;
123
124
  /// Target has carry-less multiplication
125
  bool HasPCLMUL;
126
127
  /// Target has 3-operand fused multiply-add
128
  bool HasFMA;
129
130
  /// Target has 4-operand fused multiply-add
131
  bool HasFMA4;
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133
  /// Target has XOP instructions
134
  bool HasXOP;
135
136
  /// Target has TBM instructions.
137
  bool HasTBM;
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139
  /// Target has LWP instructions
140
  bool HasLWP;
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142
  /// True if the processor has the MOVBE instruction.
143
  bool HasMOVBE;
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  /// True if the processor has the RDRAND instruction.
146
  bool HasRDRAND;
147
148
  /// Processor has 16-bit floating point conversion instructions.
149
  bool HasF16C;
150
151
  /// Processor has FS/GS base insturctions.
152
  bool HasFSGSBase;
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  /// Processor has LZCNT instruction.
155
  bool HasLZCNT;
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157
  /// Processor has BMI1 instructions.
158
  bool HasBMI;
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160
  /// Processor has BMI2 instructions.
161
  bool HasBMI2;
162
163
  /// Processor has VBMI instructions.
164
  bool HasVBMI;
165
166
  /// Processor has Integer Fused Multiply Add
167
  bool HasIFMA;
168
169
  /// Processor has RTM instructions.
170
  bool HasRTM;
171
172
  /// Processor has ADX instructions.
173
  bool HasADX;
174
175
  /// Processor has SHA instructions.
176
  bool HasSHA;
177
178
  /// Processor has PRFCHW instructions.
179
  bool HasPRFCHW;
180
181
  /// Processor has RDSEED instructions.
182
  bool HasRDSEED;
183
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  /// Processor has LAHF/SAHF instructions.
185
  bool HasLAHFSAHF;
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  /// Processor has MONITORX/MWAITX instructions.
188
  bool HasMWAITX;
189
190
  /// Processor has Cache Line Zero instruction
191
  bool HasCLZERO;
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  /// Processor has Prefetch with intent to Write instruction
194
  bool HasPFPREFETCHWT1;
195
196
  /// True if BT (bit test) of memory instructions are slow.
197
  bool IsBTMemSlow;
198
199
  /// True if SHLD instructions are slow.
200
  bool IsSHLDSlow;
201
202
  /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
203
  //  PMULUDQ.
204
  bool IsPMULLDSlow;
205
206
  /// True if unaligned memory accesses of 16-bytes are slow.
207
  bool IsUAMem16Slow;
208
209
  /// True if unaligned memory accesses of 32-bytes are slow.
210
  bool IsUAMem32Slow;
211
212
  /// True if SSE operations can have unaligned memory operands.
213
  /// This may require setting a configuration bit in the processor.
214
  bool HasSSEUnalignedMem;
215
216
  /// True if this processor has the CMPXCHG16B instruction;
217
  /// this is true for most x86-64 chips, but not the first AMD chips.
218
  bool HasCmpxchg16b;
219
220
  /// True if the LEA instruction should be used for adjusting
221
  /// the stack pointer. This is an optimization for Intel Atom processors.
222
  bool UseLeaForSP;
223
224
  /// True if there is no performance penalty to writing only the lower parts
225
  /// of a YMM or ZMM register without clearing the upper part.
226
  bool HasFastPartialYMMorZMMWrite;
227
228
  /// True if hardware SQRTSS instruction is at least as fast (latency) as
229
  /// RSQRTSS followed by a Newton-Raphson iteration.
230
  bool HasFastScalarFSQRT;
231
232
  /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
233
  /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
234
  bool HasFastVectorFSQRT;
235
236
  /// True if 8-bit divisions are significantly faster than
237
  /// 32-bit divisions and should be used when possible.
238
  bool HasSlowDivide32;
239
240
  /// True if 32-bit divides are significantly faster than
241
  /// 64-bit divisions and should be used when possible.
242
  bool HasSlowDivide64;
243
244
  /// True if LZCNT instruction is fast.
245
  bool HasFastLZCNT;
246
247
  /// True if SHLD based rotate is fast.
248
  bool HasFastSHLDRotate;
249
250
  /// True if the processor supports macrofusion.
251
  bool HasMacroFusion;
252
253
  /// True if the processor has enhanced REP MOVSB/STOSB.
254
  bool HasERMSB;
255
256
  /// True if the short functions should be padded to prevent
257
  /// a stall when returning too early.
258
  bool PadShortFunctions;
259
260
  /// True if two memory operand instructions should use a temporary register
261
  /// instead.
262
  bool SlowTwoMemOps;
263
264
  /// True if the LEA instruction inputs have to be ready at address generation
265
  /// (AG) time.
266
  bool LEAUsesAG;
267
268
  /// True if the LEA instruction with certain arguments is slow
269
  bool SlowLEA;
270
271
  /// True if the LEA instruction has all three source operands: base, index,
272
  /// and offset or if the LEA instruction uses base and index registers where
273
  /// the base is EBP, RBP,or R13
274
  bool Slow3OpsLEA;
275
276
  /// True if INC and DEC instructions are slow when writing to flags
277
  bool SlowIncDec;
278
279
  /// Processor has AVX-512 PreFetch Instructions
280
  bool HasPFI;
281
282
  /// Processor has AVX-512 Exponential and Reciprocal Instructions
283
  bool HasERI;
284
285
  /// Processor has AVX-512 Conflict Detection Instructions
286
  bool HasCDI;
287
288
  /// Processor has AVX-512 population count Instructions
289
  bool HasVPOPCNTDQ;
290
291
  /// Processor has AVX-512 Doubleword and Quadword instructions
292
  bool HasDQI;
293
294
  /// Processor has AVX-512 Byte and Word instructions
295
  bool HasBWI;
296
297
  /// Processor has AVX-512 Vector Length eXtenstions
298
  bool HasVLX;
299
300
  /// Processor has PKU extenstions
301
  bool HasPKU;
302
303
  /// Processor supports MPX - Memory Protection Extensions
304
  bool HasMPX;
305
306
  /// Processor has Software Guard Extensions
307
  bool HasSGX;
308
309
  /// Processor supports Flush Cache Line instruction
310
  bool HasCLFLUSHOPT;
311
312
  /// Processor supports Cache Line Write Back instruction
313
  bool HasCLWB;
314
315
  /// Use software floating point for code generation.
316
  bool UseSoftFloat;
317
318
  /// The minimum alignment known to hold of the stack frame on
319
  /// entry to the function and which must be maintained by every function.
320
  unsigned stackAlignment;
321
322
  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
323
  ///
324
  unsigned MaxInlineSizeThreshold;
325
326
  /// What processor and OS we're targeting.
327
  Triple TargetTriple;
328
329
  /// Instruction itineraries for scheduling
330
  InstrItineraryData InstrItins;
331
332
  /// GlobalISel related APIs.
333
  std::unique_ptr<CallLowering> CallLoweringInfo;
334
  std::unique_ptr<LegalizerInfo> Legalizer;
335
  std::unique_ptr<RegisterBankInfo> RegBankInfo;
336
  std::unique_ptr<InstructionSelector> InstSelector;
337
338
private:
339
  /// Override the stack alignment.
340
  unsigned StackAlignOverride;
341
342
  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
343
  bool In64BitMode;
344
345
  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
346
  bool In32BitMode;
347
348
  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
349
  bool In16BitMode;
350
351
  /// Contains the Overhead of gather\scatter instructions
352
  int GatherOverhead;
353
  int ScatterOverhead;
354
355
  X86SelectionDAGInfo TSInfo;
356
  // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
357
  // X86TargetLowering needs.
358
  X86InstrInfo InstrInfo;
359
  X86TargetLowering TLInfo;
360
  X86FrameLowering FrameLowering;
361
362
public:
363
  /// This constructor initializes the data members to match that
364
  /// of the specified triple.
365
  ///
366
  X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
367
               const X86TargetMachine &TM, unsigned StackAlignOverride);
368
369
4.07M
  const X86TargetLowering *getTargetLowering() const override {
370
4.07M
    return &TLInfo;
371
4.07M
  }
372
373
23.0M
  const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
374
375
4.69M
  const X86FrameLowering *getFrameLowering() const override {
376
4.69M
    return &FrameLowering;
377
4.69M
  }
378
379
73.7k
  const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
380
73.7k
    return &TSInfo;
381
73.7k
  }
382
383
16.9M
  const X86RegisterInfo *getRegisterInfo() const override {
384
16.9M
    return &getInstrInfo()->getRegisterInfo();
385
16.9M
  }
386
387
  /// Returns the minimum alignment known to hold of the
388
  /// stack frame on entry to the function and which must be maintained by every
389
  /// function for this subtarget.
390
9.65k
  unsigned getStackAlignment() const { return stackAlignment; }
391
392
  /// Returns the maximum memset / memcpy size
393
  /// that still makes it profitable to inline the call.
394
63
  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
395
396
  /// ParseSubtargetFeatures - Parses features string setting specified
397
  /// subtarget options.  Definition of function is auto generated by tblgen.
398
  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
399
400
  /// Methods used by Global ISel
401
  const CallLowering *getCallLowering() const override;
402
  const InstructionSelector *getInstructionSelector() const override;
403
  const LegalizerInfo *getLegalizerInfo() const override;
404
  const RegisterBankInfo *getRegBankInfo() const override;
405
406
private:
407
  /// Initialize the full set of dependencies so we can use an initializer
408
  /// list for X86Subtarget.
409
  X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
410
  void initializeEnvironment();
411
  void initSubtargetFeatures(StringRef CPU, StringRef FS);
412
413
public:
414
  /// Is this x86_64? (disregarding specific ABI / programming model)
415
3.53M
  bool is64Bit() const {
416
3.53M
    return In64BitMode;
417
3.53M
  }
418
419
11.0k
  bool is32Bit() const {
420
11.0k
    return In32BitMode;
421
11.0k
  }
422
423
0
  bool is16Bit() const {
424
0
    return In16BitMode;
425
0
  }
426
427
  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
428
149k
  bool isTarget64BitILP32() const {
429
119k
    return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
430
119k
                           TargetTriple.isOSNaCl());
431
149k
  }
432
433
  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
434
435k
  bool isTarget64BitLP64() const {
435
270k
    return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
436
270k
                           !TargetTriple.isOSNaCl());
437
435k
  }
438
439
0
  PICStyles::Style getPICStyle() const { return PICStyle; }
440
9.65k
  void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
441
442
9.80k
  bool hasX87() const { return HasX87; }
443
183k
  bool hasCMov() const { return HasCMov; }
444
1.18M
  bool hasSSE1() const { return X86SSELevel >= SSE1; }
445
773k
  bool hasSSE2() const { return X86SSELevel >= SSE2; }
446
195k
  bool hasSSE3() const { return X86SSELevel >= SSE3; }
447
367k
  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
448
201k
  bool hasSSE41() const { return X86SSELevel >= SSE41; }
449
64.0k
  bool hasSSE42() const { return X86SSELevel >= SSE42; }
450
1.72M
  bool hasAVX() const { return X86SSELevel >= AVX; }
451
745k
  bool hasAVX2() const { return X86SSELevel >= AVX2; }
452
1.68M
  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
453
41.7k
  bool hasFp256() const { return hasAVX(); }
454
375k
  bool hasInt256() const { return hasAVX2(); }
455
66.7k
  bool hasSSE4A() const { return HasSSE4A; }
456
28.1k
  bool hasMMX() const { return X863DNowLevel >= MMX; }
457
9.73k
  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
458
0
  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
459
22.7k
  bool hasPOPCNT() const { return HasPOPCNT; }
460
9.83k
  bool hasAES() const { return HasAES; }
461
9.65k
  bool hasFXSR() const { return HasFXSR; }
462
9.65k
  bool hasXSAVE() const { return HasXSAVE; }
463
9.65k
  bool hasXSAVEOPT() const { return HasXSAVEOPT; }
464
9.64k
  bool hasXSAVEC() const { return HasXSAVEC; }
465
9.65k
  bool hasXSAVES() const { return HasXSAVES; }
466
9.67k
  bool hasPCLMUL() const { return HasPCLMUL; }
467
  // Prefer FMA4 to FMA - its better for commutation/memory folding and
468
  // has equal or better performance on all supported targets.
469
30.4k
  bool hasFMA() const 
{ return (HasFMA || 30.4k
hasAVX512()22.9k
) &&
!HasFMA410.3k
; }
470
22.6k
  bool hasFMA4() const { return HasFMA4; }
471
18.5k
  bool hasAnyFMA() const 
{ return hasFMA() || 18.5k
hasFMA4()11.9k
; }
472
92.3k
  bool hasXOP() const { return HasXOP; }
473
37.3k
  bool hasTBM() const { return HasTBM; }
474
9.72k
  bool hasLWP() const { return HasLWP; }
475
19.5k
  bool hasMOVBE() const { return HasMOVBE; }
476
9.65k
  bool hasRDRAND() const { return HasRDRAND; }
477
29.9k
  bool hasF16C() const { return HasF16C; }
478
9.64k
  bool hasFSGSBase() const { return HasFSGSBase; }
479
25.5k
  bool hasLZCNT() const { return HasLZCNT; }
480
42.9k
  bool hasBMI() const { return HasBMI; }
481
22.6k
  bool hasBMI2() const { return HasBMI2; }
482
17.8k
  bool hasVBMI() const { return HasVBMI; }
483
9.70k
  bool hasIFMA() const { return HasIFMA; }
484
9.65k
  bool hasRTM() const { return HasRTM; }
485
11.8k
  bool hasADX() const { return HasADX; }
486
9.72k
  bool hasSHA() const { return HasSHA; }
487
9.65k
  bool hasPRFCHW() const { return HasPRFCHW; }
488
9.65k
  bool hasRDSEED() const { return HasRDSEED; }
489
10.0k
  bool hasLAHFSAHF() const { return HasLAHFSAHF; }
490
9.65k
  bool hasMWAITX() const { return HasMWAITX; }
491
9.64k
  bool hasCLZERO() const { return HasCLZERO; }
492
0
  bool isBTMemSlow() const { return IsBTMemSlow; }
493
11.0k
  bool isSHLDSlow() const { return IsSHLDSlow; }
494
653
  bool isPMULLDSlow() const { return IsPMULLDSlow; }
495
11.1k
  bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
496
8.22k
  bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
497
0
  int getGatherOverhead() const { return GatherOverhead; }
498
0
  int getScatterOverhead() const { return ScatterOverhead; }
499
4.96k
  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
500
19.3k
  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
501
25.7k
  bool useLeaForSP() const { return UseLeaForSP; }
502
39.8k
  bool hasFastPartialYMMorZMMWrite() const {
503
39.8k
    return HasFastPartialYMMorZMMWrite;
504
39.8k
  }
505
37
  bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
506
39
  bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
507
18.2k
  bool hasFastLZCNT() const { return HasFastLZCNT; }
508
9.68k
  bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
509
127k
  bool hasMacroFusion() const { return HasMacroFusion; }
510
91
  bool hasERMSB() const { return HasERMSB; }
511
8.05k
  bool hasSlowDivide32() const { return HasSlowDivide32; }
512
8.05k
  bool hasSlowDivide64() const { return HasSlowDivide64; }
513
69.3k
  bool padShortFunctions() const { return PadShortFunctions; }
514
97.1k
  bool slowTwoMemOps() const { return SlowTwoMemOps; }
515
70.8k
  bool LEAusesAG() const { return LEAUsesAG; }
516
72.3k
  bool slowLEA() const { return SlowLEA; }
517
187k
  bool slow3OpsLEA() const { return Slow3OpsLEA; }
518
79.7k
  bool slowIncDec() const { return SlowIncDec; }
519
15.1k
  bool hasCDI() const { return HasCDI; }
520
10.6k
  bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
521
0
  bool hasPFI() const { return HasPFI; }
522
9.66k
  bool hasERI() const { return HasERI; }
523
281k
  bool hasDQI() const { return HasDQI; }
524
138k
  bool hasBWI() const { return HasBWI; }
525
540k
  bool hasVLX() const { return HasVLX; }
526
0
  bool hasPKU() const { return HasPKU; }
527
0
  bool hasMPX() const { return HasMPX; }
528
9.64k
  bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
529
0
  bool hasCLWB() const { return HasCLWB; }
530
531
26
  bool isXRaySupported() const override { return is64Bit(); }
532
533
0
  X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
534
535
  /// TODO: to be removed later and replaced with suitable properties
536
26.1k
  bool isAtom() const { return X86ProcFamily == IntelAtom; }
537
147k
  bool isSLM() const { return X86ProcFamily == IntelSLM; }
538
290k
  bool useSoftFloat() const { return UseSoftFloat; }
539
540
  /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
541
  /// no-sse2). There isn't any reason to disable it if the target processor
542
  /// supports it.
543
9.71k
  bool hasMFence() const 
{ return hasSSE2() || 9.71k
is64Bit()1.40k
; }
544
545
59.5k
  const Triple &getTargetTriple() const { return TargetTriple; }
546
547
124k
  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
548
69
  bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
549
78
  bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
550
3.46k
  bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
551
19.2k
  bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
552
553
28.2k
  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
554
116k
  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
555
3.45k
  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
556
557
5.93k
  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
558
3.45k
  bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
559
60
  bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
560
152
  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
561
3.18k
  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
562
0
  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
563
2.60k
  bool isTargetNaCl64() const 
{ return isTargetNaCl() && 2.60k
is64Bit()11
; }
564
100k
  bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
565
540
  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
566
567
0
  bool isTargetWindowsMSVC() const {
568
0
    return TargetTriple.isWindowsMSVCEnvironment();
569
0
  }
570
571
42.7k
  bool isTargetKnownWindowsMSVC() const {
572
42.7k
    return TargetTriple.isKnownWindowsMSVCEnvironment();
573
42.7k
  }
574
575
106
  bool isTargetWindowsCoreCLR() const {
576
106
    return TargetTriple.isWindowsCoreCLREnvironment();
577
106
  }
578
579
0
  bool isTargetWindowsCygwin() const {
580
0
    return TargetTriple.isWindowsCygwinEnvironment();
581
0
  }
582
583
5.62k
  bool isTargetWindowsGNU() const {
584
5.62k
    return TargetTriple.isWindowsGNUEnvironment();
585
5.62k
  }
586
587
11.5k
  bool isTargetWindowsItanium() const {
588
11.5k
    return TargetTriple.isWindowsItaniumEnvironment();
589
11.5k
  }
590
591
75.7k
  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
592
593
73.6k
  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
594
595
545k
  bool isTargetWin64() const {
596
484k
    return In64BitMode && TargetTriple.isOSWindows();
597
545k
  }
598
599
2.67k
  bool isTargetWin32() const {
600
2.63k
    return !In64BitMode && 
(isTargetCygMing() || 2.63k
isTargetKnownWindowsMSVC()2.54k
);
601
2.67k
  }
602
603
64.8k
  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
604
46.7k
  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
605
606
51
  bool isPICStyleStubPIC() const {
607
51
    return PICStyle == PICStyles::StubPIC;
608
51
  }
609
610
32.7k
  bool isPositionIndependent() const { return TM.isPositionIndependent(); }
611
612
184k
  bool isCallingConvWin64(CallingConv::ID CC) const {
613
184k
    switch (CC) {
614
184k
    // On Win64, all these conventions just use the default convention.
615
183k
    case CallingConv::C:
616
183k
    case CallingConv::Fast:
617
183k
    case CallingConv::Swift:
618
183k
    case CallingConv::X86_FastCall:
619
183k
    case CallingConv::X86_StdCall:
620
183k
    case CallingConv::X86_ThisCall:
621
183k
    case CallingConv::X86_VectorCall:
622
183k
    case CallingConv::Intel_OCL_BI:
623
183k
      return isTargetWin64();
624
183k
    // This convention allows using the Win64 convention on other targets.
625
97
    case CallingConv::Win64:
626
97
      return true;
627
183k
    // This convention allows using the SysV convention on Windows targets.
628
10
    case CallingConv::X86_64_SysV:
629
10
      return false;
630
183k
    // Otherwise, who knows what this is.
631
615
    default:
632
615
      return false;
633
184k
    }
634
184k
  }
635
636
  /// Classify a global variable reference for the current subtarget according
637
  /// to how we should reference it in a non-pcrel context.
638
  unsigned char classifyLocalReference(const GlobalValue *GV) const;
639
640
  unsigned char classifyGlobalReference(const GlobalValue *GV,
641
                                        const Module &M) const;
642
  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
643
644
  /// Classify a global function reference for the current subtarget.
645
  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
646
                                                const Module &M) const;
647
  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
648
649
  /// Classify a blockaddress reference for the current subtarget according to
650
  /// how we should reference it in a non-pcrel context.
651
  unsigned char classifyBlockAddressReference() const;
652
653
  /// Return true if the subtarget allows calls to immediate address.
654
  bool isLegalToCallImmediateAddr() const;
655
656
  /// This function returns the name of a function which has an interface
657
  /// like the non-standard bzero function, if such a function exists on
658
  /// the current subtarget and it is considered prefereable over
659
  /// memset with zero passed as the second argument. Otherwise it
660
  /// returns null.
661
  const char *getBZeroEntry() const;
662
663
  /// This function returns true if the target has sincos() routine in its
664
  /// compiler runtime or math libraries.
665
  bool hasSinCos() const;
666
667
  /// Enable the MachineScheduler pass for all X86 subtargets.
668
273k
  bool enableMachineScheduler() const override { return true; }
669
670
  // TODO: Update the regression tests and return true.
671
67.9k
  bool supportPrintSchedInfo() const override { return false; }
672
673
  bool enableEarlyIfConversion() const override;
674
675
  /// Return the instruction itineraries based on the subtarget selection.
676
213k
  const InstrItineraryData *getInstrItineraryData() const override {
677
213k
    return &InstrItins;
678
213k
  }
679
680
70.8k
  AntiDepBreakMode getAntiDepBreakMode() const override {
681
70.8k
    return TargetSubtargetInfo::ANTIDEP_CRITICAL;
682
70.8k
  }
683
};
684
685
} // end namespace llvm
686
687
#endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H