Coverage Report

Created: 2019-03-24 22:13

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AArch64/AArch64GenCallingConv.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Calling Convention Implementation Fragment                                 *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
10
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
11
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
12
bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
13
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
14
                                ISD::ArgFlagsTy ArgFlags, CCState &State);
15
bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
16
                                       MVT LocVT, CCValAssign::LocInfo LocInfo,
17
                                       ISD::ArgFlagsTy ArgFlags, CCState &State);
18
bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
19
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
20
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
21
bool llvm::CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
22
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
23
                                ISD::ArgFlagsTy ArgFlags, CCState &State);
24
bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
25
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
26
                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
27
bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
28
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
29
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
30
bool llvm::RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
31
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
32
                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
33
34
35
bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
36
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
37
26.8k
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
38
26.8k
39
26.8k
  if (LocVT == MVT::iPTR) {
40
0
    LocVT = MVT::i64;
41
0
    LocInfo = CCValAssign::BCvt;
42
0
  }
43
26.8k
44
26.8k
  if (LocVT == MVT::v2f32) {
45
590
    LocVT = MVT::v2i32;
46
590
    LocInfo = CCValAssign::BCvt;
47
590
  }
48
26.8k
49
26.8k
  if (LocVT == MVT::v2f64 ||
50
26.8k
      
LocVT == MVT::v4f3226.2k
) {
51
1.30k
    LocVT = MVT::v2i64;
52
1.30k
    LocInfo = CCValAssign::BCvt;
53
1.30k
  }
54
26.8k
55
26.8k
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
56
1.62k
    if (LocVT == MVT::v2i32 ||
57
1.62k
        
LocVT == MVT::v2f321.56k
||
58
1.62k
        
LocVT == MVT::v4i161.56k
||
59
1.62k
        
LocVT == MVT::v4f161.52k
||
60
1.62k
        
LocVT == MVT::v8i81.52k
) {
61
139
      LocVT = MVT::f64;
62
139
      LocInfo = CCValAssign::BCvt;
63
139
    }
64
1.62k
  }
65
26.8k
66
26.8k
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
67
1.62k
    if (LocVT == MVT::v2i64 ||
68
1.62k
        
LocVT == MVT::v2f641.54k
||
69
1.62k
        
LocVT == MVT::v4i321.54k
||
70
1.62k
        
LocVT == MVT::v4f321.50k
||
71
1.62k
        
LocVT == MVT::v8i161.50k
||
72
1.62k
        
LocVT == MVT::v8f161.46k
||
73
1.62k
        
LocVT == MVT::v16i81.46k
) {
74
196
      LocVT = MVT::f128;
75
196
      LocInfo = CCValAssign::BCvt;
76
196
    }
77
1.62k
  }
78
26.8k
79
26.8k
  if (ArgFlags.isSRet()) {
80
13
    if (LocVT == MVT::i64) {
81
13
      if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
82
13
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
83
13
        return false;
84
13
      }
85
26.8k
    }
86
13
  }
87
26.8k
88
26.8k
  if (ArgFlags.isByVal()) {
89
15
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
90
15
    return false;
91
15
  }
92
26.7k
93
26.7k
  if (ArgFlags.isNest()) {
94
2
    if (unsigned Reg = State.AllocateReg(AArch64::X18)) {
95
2
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
96
2
      return false;
97
2
    }
98
26.7k
  }
99
26.7k
100
26.7k
  if (ArgFlags.isSwiftSelf()) {
101
14
    if (LocVT == MVT::i64) {
102
14
      if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
103
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
104
14
        return false;
105
14
      }
106
26.7k
    }
107
14
  }
108
26.7k
109
26.7k
  if (ArgFlags.isSwiftError()) {
110
6
    if (LocVT == MVT::i64) {
111
6
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
112
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
113
6
        return false;
114
6
      }
115
26.7k
    }
116
6
  }
117
26.7k
118
26.7k
  if (ArgFlags.isInConsecutiveRegs()) {
119
875
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
120
355
        return false;
121
26.4k
  }
122
26.4k
123
26.4k
  if (LocVT == MVT::i1 ||
124
26.4k
      
LocVT == MVT::i826.3k
||
125
26.4k
      
LocVT == MVT::i1625.6k
) {
126
1.36k
    LocVT = MVT::i32;
127
1.36k
    if (ArgFlags.isSExt())
128
12
        LocInfo = CCValAssign::SExt;
129
1.34k
    else if (ArgFlags.isZExt())
130
46
        LocInfo = CCValAssign::ZExt;
131
1.30k
    else
132
1.30k
        LocInfo = CCValAssign::AExt;
133
1.36k
  }
134
26.4k
135
26.4k
  if (LocVT == MVT::i32) {
136
5.16k
    static const MCPhysReg RegList1[] = {
137
5.16k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
138
5.16k
    };
139
5.16k
    static const MCPhysReg RegList2[] = {
140
5.16k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
141
5.16k
    };
142
5.16k
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
143
5.09k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
144
5.09k
      return false;
145
5.09k
    }
146
21.3k
  }
147
21.3k
148
21.3k
  if (LocVT == MVT::i64) {
149
7.55k
    if (ArgFlags.isSplit()) {
150
181
      static const MCPhysReg RegList3[] = {
151
181
        AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
152
181
      };
153
181
      static const MCPhysReg RegList4[] = {
154
181
        AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
155
181
      };
156
181
      if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
157
132
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
158
132
        return false;
159
132
      }
160
21.1k
    }
161
7.55k
  }
162
21.1k
163
21.1k
  if (LocVT == MVT::i64) {
164
7.42k
    if (ArgFlags.isSplit()) {
165
49
      static const MCPhysReg ShadowRegList5[] = {
166
49
        AArch64::X7
167
49
      };
168
49
      unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5);
169
49
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
170
49
      return false;
171
49
    }
172
21.1k
  }
173
21.1k
174
21.1k
  if (LocVT == MVT::i64) {
175
7.37k
    static const MCPhysReg RegList7[] = {
176
7.37k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
177
7.37k
    };
178
7.37k
    static const MCPhysReg RegList8[] = {
179
7.37k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
180
7.37k
    };
181
7.37k
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
182
7.25k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
183
7.25k
      return false;
184
7.25k
    }
185
13.8k
  }
186
13.8k
187
13.8k
  if (LocVT == MVT::f16) {
188
655
    static const MCPhysReg RegList9[] = {
189
655
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
190
655
    };
191
655
    static const MCPhysReg RegList10[] = {
192
655
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
193
655
    };
194
655
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
195
655
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
196
655
      return false;
197
655
    }
198
13.2k
  }
199
13.2k
200
13.2k
  if (LocVT == MVT::f32) {
201
1.74k
    static const MCPhysReg RegList11[] = {
202
1.74k
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
203
1.74k
    };
204
1.74k
    static const MCPhysReg RegList12[] = {
205
1.74k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
206
1.74k
    };
207
1.74k
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
208
1.74k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
209
1.74k
      return false;
210
1.74k
    }
211
11.4k
  }
212
11.4k
213
11.4k
  if (LocVT == MVT::f64) {
214
869
    static const MCPhysReg RegList13[] = {
215
869
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
216
869
    };
217
869
    static const MCPhysReg RegList14[] = {
218
869
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
219
869
    };
220
869
    if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
221
851
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
222
851
      return false;
223
851
    }
224
10.6k
  }
225
10.6k
226
10.6k
  if (LocVT == MVT::v1i64 ||
227
10.6k
      
LocVT == MVT::v2i3210.4k
||
228
10.6k
      
LocVT == MVT::v4i168.90k
||
229
10.6k
      
LocVT == MVT::v8i87.86k
||
230
10.6k
      
LocVT == MVT::v1f647.33k
||
231
10.6k
      
LocVT == MVT::v2f327.18k
||
232
10.6k
      
LocVT == MVT::v4f167.18k
) {
233
3.77k
    static const MCPhysReg RegList15[] = {
234
3.77k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
235
3.77k
    };
236
3.77k
    static const MCPhysReg RegList16[] = {
237
3.77k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
238
3.77k
    };
239
3.77k
    if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
240
3.77k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
241
3.77k
      return false;
242
3.77k
    }
243
6.86k
  }
244
6.86k
245
6.86k
  if (LocVT == MVT::f128 ||
246
6.86k
      
LocVT == MVT::v2i646.28k
||
247
6.86k
      
LocVT == MVT::v4i324.30k
||
248
6.86k
      
LocVT == MVT::v8i162.40k
||
249
6.86k
      
LocVT == MVT::v16i81.26k
||
250
6.86k
      
LocVT == MVT::v4f32544
||
251
6.86k
      
LocVT == MVT::v2f64544
||
252
6.86k
      
LocVT == MVT::v8f16544
) {
253
6.64k
    static const MCPhysReg RegList17[] = {
254
6.64k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
255
6.64k
    };
256
6.64k
    if (unsigned Reg = State.AllocateReg(RegList17)) {
257
6.63k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
258
6.63k
      return false;
259
6.63k
    }
260
230
  }
261
230
262
230
  if (LocVT == MVT::i1 ||
263
230
      LocVT == MVT::i8 ||
264
230
      LocVT == MVT::i16 ||
265
230
      LocVT == MVT::f16) {
266
0
    unsigned Offset18 = State.AllocateStack(8, 8);
267
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
268
0
    return false;
269
0
  }
270
230
271
230
  if (LocVT == MVT::i32 ||
272
230
      
LocVT == MVT::f32158
) {
273
77
    unsigned Offset19 = State.AllocateStack(8, 8);
274
77
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
275
77
    return false;
276
77
  }
277
153
278
153
  if (LocVT == MVT::i64 ||
279
153
      
LocVT == MVT::f6432
||
280
153
      
LocVT == MVT::v1f6414
||
281
153
      
LocVT == MVT::v2f3214
||
282
153
      
LocVT == MVT::v1i6414
||
283
153
      
LocVT == MVT::v2i3214
||
284
153
      
LocVT == MVT::v4i1614
||
285
153
      
LocVT == MVT::v8i814
||
286
153
      
LocVT == MVT::v4f1614
) {
287
140
    unsigned Offset20 = State.AllocateStack(8, 8);
288
140
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo));
289
140
    return false;
290
140
  }
291
13
292
13
  if (LocVT == MVT::f128 ||
293
13
      
LocVT == MVT::v2i6410
||
294
13
      
LocVT == MVT::v4i327
||
295
13
      
LocVT == MVT::v8i167
||
296
13
      
LocVT == MVT::v16i87
||
297
13
      
LocVT == MVT::v4f327
||
298
13
      
LocVT == MVT::v2f647
||
299
13
      
LocVT == MVT::v8f167
) {
300
7
    unsigned Offset21 = State.AllocateStack(16, 16);
301
7
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo));
302
7
    return false;
303
7
  }
304
6
305
6
  return true;  // CC didn't match.
306
6
}
307
308
309
bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
310
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
311
4.21M
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
312
4.21M
313
4.21M
  if (LocVT == MVT::iPTR) {
314
0
    LocVT = MVT::i64;
315
0
    LocInfo = CCValAssign::BCvt;
316
0
  }
317
4.21M
318
4.21M
  if (LocVT == MVT::v2f32) {
319
98
    LocVT = MVT::v2i32;
320
98
    LocInfo = CCValAssign::BCvt;
321
98
  }
322
4.21M
323
4.21M
  if (LocVT == MVT::v2f64 ||
324
4.21M
      
LocVT == MVT::v4f324.21M
||
325
4.21M
      
LocVT == MVT::f1284.21M
) {
326
237
    LocVT = MVT::v2i64;
327
237
    LocInfo = CCValAssign::BCvt;
328
237
  }
329
4.21M
330
4.21M
  if (ArgFlags.isSRet()) {
331
5.99k
    if (LocVT == MVT::i64) {
332
5.99k
      if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
333
5.99k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
334
5.99k
        return false;
335
5.99k
      }
336
4.20M
    }
337
5.99k
  }
338
4.20M
339
4.20M
  if (ArgFlags.isByVal()) {
340
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
341
0
    return false;
342
0
  }
343
4.20M
344
4.20M
  if (ArgFlags.isSwiftSelf()) {
345
43
    if (LocVT == MVT::i64) {
346
43
      if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
347
43
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
348
43
        return false;
349
43
      }
350
4.20M
    }
351
43
  }
352
4.20M
353
4.20M
  if (ArgFlags.isSwiftError()) {
354
46
    if (LocVT == MVT::i64) {
355
46
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
356
46
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
357
46
        return false;
358
46
      }
359
4.20M
    }
360
46
  }
361
4.20M
362
4.20M
  if (ArgFlags.isInConsecutiveRegs()) {
363
2.00k
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
364
2.00k
        return false;
365
4.20M
  }
366
4.20M
367
4.20M
  if (LocVT == MVT::i1 ||
368
4.20M
      
LocVT == MVT::i84.20M
||
369
4.20M
      
LocVT == MVT::i164.17M
) {
370
44.7k
    LocVT = MVT::i32;
371
44.7k
    if (ArgFlags.isSExt())
372
5.20k
        LocInfo = CCValAssign::SExt;
373
39.5k
    else if (ArgFlags.isZExt())
374
17.1k
        LocInfo = CCValAssign::ZExt;
375
22.4k
    else
376
22.4k
        LocInfo = CCValAssign::AExt;
377
44.7k
  }
378
4.20M
379
4.20M
  if (LocVT == MVT::i32) {
380
596k
    static const MCPhysReg RegList1[] = {
381
596k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
382
596k
    };
383
596k
    static const MCPhysReg RegList2[] = {
384
596k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
385
596k
    };
386
596k
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
387
594k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
388
594k
      return false;
389
594k
    }
390
3.61M
  }
391
3.61M
392
3.61M
  if (LocVT == MVT::i64) {
393
3.57M
    if (ArgFlags.isSplit()) {
394
208
      static const MCPhysReg RegList3[] = {
395
208
        AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
396
208
      };
397
208
      static const MCPhysReg RegList4[] = {
398
208
        AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6
399
208
      };
400
208
      if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
401
188
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
402
188
        return false;
403
188
      }
404
3.61M
    }
405
3.57M
  }
406
3.61M
407
3.61M
  if (LocVT == MVT::i64) {
408
3.57M
    if (ArgFlags.isSplit()) {
409
20
      static const MCPhysReg ShadowRegList5[] = {
410
20
        AArch64::X7
411
20
      };
412
20
      unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5);
413
20
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
414
20
      return false;
415
20
    }
416
3.61M
  }
417
3.61M
418
3.61M
  if (LocVT == MVT::i64) {
419
3.57M
    static const MCPhysReg RegList7[] = {
420
3.57M
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
421
3.57M
    };
422
3.57M
    static const MCPhysReg RegList8[] = {
423
3.57M
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
424
3.57M
    };
425
3.57M
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
426
3.52M
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
427
3.52M
      return false;
428
3.52M
    }
429
85.7k
  }
430
85.7k
431
85.7k
  if (LocVT == MVT::f16) {
432
14
    static const MCPhysReg RegList9[] = {
433
14
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
434
14
    };
435
14
    static const MCPhysReg RegList10[] = {
436
14
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
437
14
    };
438
14
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
439
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
440
14
      return false;
441
14
    }
442
85.7k
  }
443
85.7k
444
85.7k
  if (LocVT == MVT::f32) {
445
2.53k
    static const MCPhysReg RegList11[] = {
446
2.53k
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
447
2.53k
    };
448
2.53k
    static const MCPhysReg RegList12[] = {
449
2.53k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
450
2.53k
    };
451
2.53k
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
452
2.52k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
453
2.52k
      return false;
454
2.52k
    }
455
83.2k
  }
456
83.2k
457
83.2k
  if (LocVT == MVT::f64) {
458
35.6k
    static const MCPhysReg RegList13[] = {
459
35.6k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
460
35.6k
    };
461
35.6k
    static const MCPhysReg RegList14[] = {
462
35.6k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
463
35.6k
    };
464
35.6k
    if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
465
35.0k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
466
35.0k
      return false;
467
35.0k
    }
468
48.1k
  }
469
48.1k
470
48.1k
  if (LocVT == MVT::v1i64 ||
471
48.1k
      
LocVT == MVT::v2i3248.0k
||
472
48.1k
      
LocVT == MVT::v4i1647.8k
||
473
48.1k
      
LocVT == MVT::v8i847.7k
||
474
48.1k
      
LocVT == MVT::v1f6447.6k
||
475
48.1k
      
LocVT == MVT::v2f3247.5k
||
476
48.1k
      
LocVT == MVT::v4f1647.5k
) {
477
537
    static const MCPhysReg RegList15[] = {
478
537
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
479
537
    };
480
537
    static const MCPhysReg RegList16[] = {
481
537
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
482
537
    };
483
537
    if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
484
533
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
485
533
      return false;
486
533
    }
487
47.5k
  }
488
47.5k
489
47.5k
  if (LocVT == MVT::v2i64 ||
490
47.5k
      
LocVT == MVT::v4i3247.2k
||
491
47.5k
      
LocVT == MVT::v8i1647.1k
||
492
47.5k
      
LocVT == MVT::v16i847.0k
||
493
47.5k
      
LocVT == MVT::v4f3246.9k
||
494
47.5k
      
LocVT == MVT::v2f6446.9k
||
495
47.5k
      
LocVT == MVT::v8f1646.9k
) {
496
696
    static const MCPhysReg RegList17[] = {
497
696
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
498
696
    };
499
696
    if (unsigned Reg = State.AllocateReg(RegList17)) {
500
692
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
501
692
      return false;
502
692
    }
503
46.9k
  }
504
46.9k
505
46.9k
  if (ValVT == MVT::i1 || 
ValVT == MVT::i846.8k
) {
506
161
    unsigned Offset18 = State.AllocateStack(1, 1);
507
161
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
508
161
    return false;
509
161
  }
510
46.7k
511
46.7k
  if (ValVT == MVT::i16 || 
ValVT == MVT::f1646.7k
) {
512
25
    unsigned Offset19 = State.AllocateStack(2, 2);
513
25
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
514
25
    return false;
515
25
  }
516
46.7k
517
46.7k
  if (LocVT == MVT::i32 ||
518
46.7k
      
LocVT == MVT::f3244.8k
) {
519
1.87k
    unsigned Offset20 = State.AllocateStack(4, 4);
520
1.87k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo));
521
1.87k
    return false;
522
1.87k
  }
523
44.8k
524
44.8k
  if (LocVT == MVT::i64 ||
525
44.8k
      
LocVT == MVT::f64559
||
526
44.8k
      
LocVT == MVT::v1f648
||
527
44.8k
      
LocVT == MVT::v2f328
||
528
44.8k
      
LocVT == MVT::v1i648
||
529
44.8k
      
LocVT == MVT::v2i328
||
530
44.8k
      
LocVT == MVT::v4i164
||
531
44.8k
      
LocVT == MVT::v8i84
||
532
44.8k
      
LocVT == MVT::v4f164
) {
533
44.8k
    unsigned Offset21 = State.AllocateStack(8, 8);
534
44.8k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo));
535
44.8k
    return false;
536
44.8k
  }
537
4
538
4
  if (LocVT == MVT::v2i64 ||
539
4
      LocVT == MVT::v4i32 ||
540
4
      
LocVT == MVT::v8i160
||
541
4
      
LocVT == MVT::v16i80
||
542
4
      
LocVT == MVT::v4f320
||
543
4
      
LocVT == MVT::v2f640
||
544
4
      
LocVT == MVT::v8f160
) {
545
4
    unsigned Offset22 = State.AllocateStack(16, 16);
546
4
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset22, LocVT, LocInfo));
547
4
    return false;
548
4
  }
549
0
550
0
  return true;  // CC didn't match.
551
0
}
552
553
554
bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
555
                                       MVT LocVT, CCValAssign::LocInfo LocInfo,
556
66.5k
                                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
557
66.5k
558
66.5k
  if (LocVT == MVT::iPTR) {
559
0
    LocVT = MVT::i64;
560
0
    LocInfo = CCValAssign::BCvt;
561
0
  }
562
66.5k
563
66.5k
  if (LocVT == MVT::v2f32) {
564
0
    LocVT = MVT::v2i32;
565
0
    LocInfo = CCValAssign::BCvt;
566
0
  }
567
66.5k
568
66.5k
  if (LocVT == MVT::v2f64 ||
569
66.5k
      LocVT == MVT::v4f32 ||
570
66.5k
      LocVT == MVT::f128) {
571
0
    LocVT = MVT::v2i64;
572
0
    LocInfo = CCValAssign::BCvt;
573
0
  }
574
66.5k
575
66.5k
  if (ArgFlags.isInConsecutiveRegs()) {
576
11
    if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
577
11
        return false;
578
66.5k
  }
579
66.5k
580
66.5k
  if (LocVT == MVT::i8 ||
581
66.5k
      
LocVT == MVT::i1666.5k
||
582
66.5k
      
LocVT == MVT::i3266.5k
) {
583
22.0k
    LocVT = MVT::i64;
584
22.0k
    if (ArgFlags.isSExt())
585
0
        LocInfo = CCValAssign::SExt;
586
22.0k
    else if (ArgFlags.isZExt())
587
0
        LocInfo = CCValAssign::ZExt;
588
22.0k
    else
589
22.0k
        LocInfo = CCValAssign::AExt;
590
22.0k
  }
591
66.5k
592
66.5k
  if (LocVT == MVT::f16 ||
593
66.5k
      LocVT == MVT::f32) {
594
2
    LocVT = MVT::f64;
595
2
    LocInfo = CCValAssign::FPExt;
596
2
  }
597
66.5k
598
66.5k
  if (LocVT == MVT::i64) {
599
60.0k
    if (ArgFlags.isSplit()) {
600
1
      unsigned Offset1 = State.AllocateStack(8, 16);
601
1
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
602
1
      return false;
603
1
    }
604
66.5k
  }
605
66.5k
606
66.5k
  if (LocVT == MVT::i64 ||
607
66.5k
      
LocVT == MVT::f646.44k
||
608
66.5k
      
LocVT == MVT::v1i641
||
609
66.5k
      
LocVT == MVT::v2i321
||
610
66.5k
      
LocVT == MVT::v4i161
||
611
66.5k
      
LocVT == MVT::v8i81
||
612
66.5k
      
LocVT == MVT::v1f641
||
613
66.5k
      
LocVT == MVT::v2f321
||
614
66.5k
      
LocVT == MVT::v4f161
) {
615
66.5k
    unsigned Offset2 = State.AllocateStack(8, 8);
616
66.5k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
617
66.5k
    return false;
618
66.5k
  }
619
1
620
1
  if (LocVT == MVT::v2i64 ||
621
1
      LocVT == MVT::v4i32 ||
622
1
      
LocVT == MVT::v8i160
||
623
1
      
LocVT == MVT::v16i80
||
624
1
      
LocVT == MVT::v4f320
||
625
1
      
LocVT == MVT::v2f640
||
626
1
      
LocVT == MVT::v8f160
) {
627
1
    unsigned Offset3 = State.AllocateStack(16, 16);
628
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
629
1
    return false;
630
1
  }
631
0
632
0
  return true;  // CC didn't match.
633
0
}
634
635
636
bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
637
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
638
9
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
639
9
640
9
  if (LocVT == MVT::iPTR) {
641
0
    LocVT = MVT::i64;
642
0
    LocInfo = CCValAssign::BCvt;
643
0
  }
644
9
645
9
  if (LocVT == MVT::v1i64 ||
646
9
      LocVT == MVT::v2i32 ||
647
9
      LocVT == MVT::v4i16 ||
648
9
      LocVT == MVT::v8i8 ||
649
9
      LocVT == MVT::v2f32) {
650
0
    LocVT = MVT::f64;
651
0
    LocInfo = CCValAssign::BCvt;
652
0
  }
653
9
654
9
  if (LocVT == MVT::v2i64 ||
655
9
      LocVT == MVT::v4i32 ||
656
9
      LocVT == MVT::v8i16 ||
657
9
      LocVT == MVT::v16i8 ||
658
9
      LocVT == MVT::v4f32 ||
659
9
      LocVT == MVT::f128) {
660
0
    LocVT = MVT::v2f64;
661
0
    LocInfo = CCValAssign::BCvt;
662
0
  }
663
9
664
9
  if (LocVT == MVT::v2f64) {
665
0
    static const MCPhysReg RegList1[] = {
666
0
      AArch64::Q4, AArch64::Q5
667
0
    };
668
0
    if (unsigned Reg = State.AllocateReg(RegList1)) {
669
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
670
0
      return false;
671
0
    }
672
9
  }
673
9
674
9
  if (LocVT == MVT::f32) {
675
3
    static const MCPhysReg RegList2[] = {
676
3
      AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11
677
3
    };
678
3
    if (unsigned Reg = State.AllocateReg(RegList2)) {
679
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
680
3
      return false;
681
3
    }
682
6
  }
683
6
684
6
  if (LocVT == MVT::f64) {
685
1
    static const MCPhysReg RegList3[] = {
686
1
      AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15
687
1
    };
688
1
    if (unsigned Reg = State.AllocateReg(RegList3)) {
689
1
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
690
1
      return false;
691
1
    }
692
5
  }
693
5
694
5
  if (LocVT == MVT::i8 ||
695
5
      LocVT == MVT::i16 ||
696
5
      LocVT == MVT::i32) {
697
0
    LocVT = MVT::i64;
698
0
    if (ArgFlags.isSExt())
699
0
        LocInfo = CCValAssign::SExt;
700
0
    else if (ArgFlags.isZExt())
701
0
        LocInfo = CCValAssign::ZExt;
702
0
    else
703
0
        LocInfo = CCValAssign::AExt;
704
0
  }
705
5
706
5
  if (LocVT == MVT::i64) {
707
5
    static const MCPhysReg RegList4[] = {
708
5
      AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
709
5
    };
710
5
    if (unsigned Reg = State.AllocateReg(RegList4)) {
711
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
712
5
      return false;
713
5
    }
714
0
  }
715
0
716
0
  return true;  // CC didn't match.
717
0
}
718
719
720
bool llvm::CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
721
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
722
129
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
723
129
724
129
  if (LocVT == MVT::i1 ||
725
129
      LocVT == MVT::i8 ||
726
129
      LocVT == MVT::i16) {
727
6
    LocVT = MVT::i32;
728
6
    if (ArgFlags.isSExt())
729
0
        LocInfo = CCValAssign::SExt;
730
6
    else if (ArgFlags.isZExt())
731
6
        LocInfo = CCValAssign::ZExt;
732
0
    else
733
0
        LocInfo = CCValAssign::AExt;
734
6
  }
735
129
736
129
  if (LocVT == MVT::i32) {
737
27
    if (unsigned Reg = State.AllocateReg(AArch64::W0, AArch64::X0)) {
738
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
739
3
      return false;
740
3
    }
741
126
  }
742
126
743
126
  if (LocVT == MVT::i64) {
744
102
    if (unsigned Reg = State.AllocateReg(AArch64::X0, AArch64::W0)) {
745
17
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
746
17
      return false;
747
17
    }
748
109
  }
749
109
750
109
  if (LocVT == MVT::i32 ||
751
109
      
LocVT == MVT::f3285
) {
752
24
    unsigned Offset1 = State.AllocateStack(4, 4);
753
24
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
754
24
    return false;
755
24
  }
756
85
757
85
  if (LocVT == MVT::i64 ||
758
85
      
LocVT == MVT::f640
) {
759
85
    unsigned Offset2 = State.AllocateStack(8, 8);
760
85
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
761
85
    return false;
762
85
  }
763
0
764
0
  return true;  // CC didn't match.
765
0
}
766
767
768
bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
769
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
770
21
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
771
21
772
21
  if (LocVT == MVT::f16 ||
773
21
      LocVT == MVT::f32) {
774
0
    LocVT = MVT::f64;
775
0
    LocInfo = CCValAssign::FPExt;
776
0
  }
777
21
778
21
  if (LocVT == MVT::f64) {
779
10
    LocVT = MVT::i64;
780
10
    LocInfo = CCValAssign::BCvt;
781
10
  }
782
21
783
21
  if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
784
21
    return false;
785
0
786
0
  return true;  // CC didn't match.
787
0
}
788
789
790
bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
791
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
792
1.44M
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
793
1.44M
794
1.44M
  if (LocVT == MVT::iPTR) {
795
0
    LocVT = MVT::i64;
796
0
    LocInfo = CCValAssign::BCvt;
797
0
  }
798
1.44M
799
1.44M
  if (LocVT == MVT::v2f32) {
800
861
    LocVT = MVT::v2i32;
801
861
    LocInfo = CCValAssign::BCvt;
802
861
  }
803
1.44M
804
1.44M
  if (LocVT == MVT::v2f64 ||
805
1.44M
      
LocVT == MVT::v4f321.44M
) {
806
1.86k
    LocVT = MVT::v2i64;
807
1.86k
    LocInfo = CCValAssign::BCvt;
808
1.86k
  }
809
1.44M
810
1.44M
  if (ArgFlags.isSwiftError()) {
811
54
    if (LocVT == MVT::i64) {
812
54
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
813
54
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
814
54
        return false;
815
54
      }
816
1.44M
    }
817
54
  }
818
1.44M
819
1.44M
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
820
1.89k
    if (LocVT == MVT::v2i32 ||
821
1.89k
        
LocVT == MVT::v2f321.77k
||
822
1.89k
        
LocVT == MVT::v4i161.77k
||
823
1.89k
        
LocVT == MVT::v4f161.71k
||
824
1.89k
        
LocVT == MVT::v8i81.71k
) {
825
240
      LocVT = MVT::f64;
826
240
      LocInfo = CCValAssign::BCvt;
827
240
    }
828
1.89k
  }
829
1.44M
830
1.44M
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
831
1.89k
    if (LocVT == MVT::v2i64 ||
832
1.89k
        
LocVT == MVT::v2f641.71k
||
833
1.89k
        
LocVT == MVT::v4i321.71k
||
834
1.89k
        
LocVT == MVT::v4f321.65k
||
835
1.89k
        
LocVT == MVT::v8i161.65k
||
836
1.89k
        
LocVT == MVT::v8f161.59k
||
837
1.89k
        
LocVT == MVT::v16i81.59k
) {
838
360
      LocVT = MVT::f128;
839
360
      LocInfo = CCValAssign::BCvt;
840
360
    }
841
1.89k
  }
842
1.44M
843
1.44M
  if (LocVT == MVT::i1 ||
844
1.44M
      
LocVT == MVT::i81.42M
||
845
1.44M
      
LocVT == MVT::i161.41M
) {
846
27.7k
    LocVT = MVT::i32;
847
27.7k
    if (ArgFlags.isSExt())
848
1.66k
        LocInfo = CCValAssign::SExt;
849
26.0k
    else if (ArgFlags.isZExt())
850
26.0k
        LocInfo = CCValAssign::ZExt;
851
52
    else
852
52
        LocInfo = CCValAssign::AExt;
853
27.7k
  }
854
1.44M
855
1.44M
  if (LocVT == MVT::i32) {
856
643k
    static const MCPhysReg RegList1[] = {
857
643k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
858
643k
    };
859
643k
    static const MCPhysReg RegList2[] = {
860
643k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
861
643k
    };
862
643k
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
863
643k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
864
643k
      return false;
865
643k
    }
866
802k
  }
867
802k
868
802k
  if (LocVT == MVT::i64) {
869
765k
    static const MCPhysReg RegList3[] = {
870
765k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
871
765k
    };
872
765k
    static const MCPhysReg RegList4[] = {
873
765k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
874
765k
    };
875
765k
    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
876
765k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
877
765k
      return false;
878
765k
    }
879
37.0k
  }
880
37.0k
881
37.0k
  if (LocVT == MVT::f16) {
882
610
    static const MCPhysReg RegList5[] = {
883
610
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
884
610
    };
885
610
    static const MCPhysReg RegList6[] = {
886
610
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
887
610
    };
888
610
    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
889
610
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
890
610
      return false;
891
610
    }
892
36.4k
  }
893
36.4k
894
36.4k
  if (LocVT == MVT::f32) {
895
10.2k
    static const MCPhysReg RegList7[] = {
896
10.2k
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
897
10.2k
    };
898
10.2k
    static const MCPhysReg RegList8[] = {
899
10.2k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
900
10.2k
    };
901
10.2k
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
902
10.2k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
903
10.2k
      return false;
904
10.2k
    }
905
26.1k
  }
906
26.1k
907
26.1k
  if (LocVT == MVT::f64) {
908
10.8k
    static const MCPhysReg RegList9[] = {
909
10.8k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
910
10.8k
    };
911
10.8k
    static const MCPhysReg RegList10[] = {
912
10.8k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
913
10.8k
    };
914
10.8k
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
915
10.8k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
916
10.8k
      return false;
917
10.8k
    }
918
15.3k
  }
919
15.3k
920
15.3k
  if (LocVT == MVT::v1i64 ||
921
15.3k
      
LocVT == MVT::v2i3214.8k
||
922
15.3k
      
LocVT == MVT::v4i1612.8k
||
923
15.3k
      
LocVT == MVT::v8i811.5k
||
924
15.3k
      
LocVT == MVT::v1f6410.4k
||
925
15.3k
      
LocVT == MVT::v2f3210.1k
||
926
15.3k
      
LocVT == MVT::v4f1610.1k
) {
927
5.60k
    static const MCPhysReg RegList11[] = {
928
5.60k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
929
5.60k
    };
930
5.60k
    static const MCPhysReg RegList12[] = {
931
5.60k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
932
5.60k
    };
933
5.60k
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
934
5.60k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
935
5.60k
      return false;
936
5.60k
    }
937
9.76k
  }
938
9.76k
939
9.76k
  if (LocVT == MVT::f128 ||
940
9.76k
      
LocVT == MVT::v2i649.02k
||
941
9.76k
      
LocVT == MVT::v4i325.60k
||
942
9.76k
      
LocVT == MVT::v8i163.05k
||
943
9.76k
      
LocVT == MVT::v16i81.52k
||
944
9.76k
      
LocVT == MVT::v4f32388
||
945
9.76k
      
LocVT == MVT::v2f64388
||
946
9.76k
      
LocVT == MVT::v8f16388
) {
947
9.74k
    static const MCPhysReg RegList13[] = {
948
9.74k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
949
9.74k
    };
950
9.74k
    if (unsigned Reg = State.AllocateReg(RegList13)) {
951
9.74k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
952
9.74k
      return false;
953
9.74k
    }
954
12
  }
955
12
956
12
  return true;  // CC didn't match.
957
12
}
958
959
960
bool llvm::RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
961
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
962
21
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
963
21
964
21
  if (LocVT == MVT::i32) {
965
6
    static const MCPhysReg RegList1[] = {
966
6
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
967
6
    };
968
6
    static const MCPhysReg RegList2[] = {
969
6
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
970
6
    };
971
6
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
972
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
973
6
      return false;
974
6
    }
975
15
  }
976
15
977
15
  if (LocVT == MVT::i64) {
978
15
    static const MCPhysReg RegList3[] = {
979
15
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
980
15
    };
981
15
    static const MCPhysReg RegList4[] = {
982
15
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
983
15
    };
984
15
    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
985
15
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
986
15
      return false;
987
15
    }
988
0
  }
989
0
990
0
  if (LocVT == MVT::f32) {
991
0
    static const MCPhysReg RegList5[] = {
992
0
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
993
0
    };
994
0
    static const MCPhysReg RegList6[] = {
995
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
996
0
    };
997
0
    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
998
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
999
0
      return false;
1000
0
    }
1001
0
  }
1002
0
1003
0
  if (LocVT == MVT::f64) {
1004
0
    static const MCPhysReg RegList7[] = {
1005
0
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1006
0
    };
1007
0
    static const MCPhysReg RegList8[] = {
1008
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1009
0
    };
1010
0
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
1011
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1012
0
      return false;
1013
0
    }
1014
0
  }
1015
0
1016
0
  return true;  // CC didn't match.
1017
0
}