Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AArch64/AArch64GenCallingConv.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Calling Convention Implementation Fragment                                 *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
static bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
10
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
11
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
12
static bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
13
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
14
                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
15
static bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
16
                                        MVT LocVT, CCValAssign::LocInfo LocInfo,
17
                                        ISD::ArgFlagsTy ArgFlags, CCState &State);
18
static bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
19
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
20
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
21
static bool CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
22
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
23
                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
24
static bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
25
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
26
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
27
static bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
28
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
29
                                ISD::ArgFlagsTy ArgFlags, CCState &State);
30
static bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
31
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
32
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
33
34
35
static bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
36
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
37
22.2k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
38
22.2k
39
22.2k
  if (LocVT == MVT::iPTR) {
40
0
    LocVT = MVT::i64;
41
0
    LocInfo = CCValAssign::BCvt;
42
0
  }
43
22.2k
44
22.2k
  if (LocVT == MVT::v2f32) {
45
488
    LocVT = MVT::v2i32;
46
488
    LocInfo = CCValAssign::BCvt;
47
488
  }
48
22.2k
49
22.2k
  if (LocVT == MVT::v2f64 ||
50
22.2k
      
LocVT == MVT::v4f3221.7k
) {
51
1.05k
    LocVT = MVT::v2i64;
52
1.05k
    LocInfo = CCValAssign::BCvt;
53
1.05k
  }
54
22.2k
55
22.2k
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
56
1.61k
    if (LocVT == MVT::v2i32 ||
57
1.61k
        
LocVT == MVT::v2f321.54k
||
58
1.61k
        
LocVT == MVT::v4i161.54k
||
59
1.61k
        
LocVT == MVT::v4f161.51k
||
60
1.61k
        
LocVT == MVT::v8i81.50k
) {
61
139
      LocVT = MVT::f64;
62
139
      LocInfo = CCValAssign::BCvt;
63
139
    }
64
1.61k
  }
65
22.2k
66
22.2k
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
67
1.61k
    if (LocVT == MVT::v2i64 ||
68
1.61k
        
LocVT == MVT::v2f641.52k
||
69
1.61k
        
LocVT == MVT::v4i321.52k
||
70
1.61k
        
LocVT == MVT::v4f321.49k
||
71
1.61k
        
LocVT == MVT::v8i161.49k
||
72
1.61k
        
LocVT == MVT::v8f161.45k
||
73
1.61k
        
LocVT == MVT::v16i81.45k
) {
74
196
      LocVT = MVT::f128;
75
196
      LocInfo = CCValAssign::BCvt;
76
196
    }
77
1.61k
  }
78
22.2k
79
22.2k
  if (ArgFlags.isSRet()) {
80
13
    if (LocVT == MVT::i64) {
81
13
      if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
82
13
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
83
13
        return false;
84
13
      }
85
22.2k
    }
86
13
  }
87
22.2k
88
22.2k
  if (ArgFlags.isByVal()) {
89
15
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
90
15
    return false;
91
15
  }
92
22.2k
93
22.2k
  if (ArgFlags.isNest()) {
94
2
    if (unsigned Reg = State.AllocateReg(AArch64::X18)) {
95
2
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
96
2
      return false;
97
2
    }
98
22.2k
  }
99
22.2k
100
22.2k
  if (ArgFlags.isSwiftSelf()) {
101
14
    if (LocVT == MVT::i64) {
102
14
      if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
103
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
104
14
        return false;
105
14
      }
106
22.1k
    }
107
14
  }
108
22.1k
109
22.1k
  if (ArgFlags.isSwiftError()) {
110
2
    if (LocVT == MVT::i64) {
111
2
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
112
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
113
2
        return false;
114
2
      }
115
22.1k
    }
116
2
  }
117
22.1k
118
22.1k
  if (ArgFlags.isInConsecutiveRegs()) {
119
869
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
120
349
        return false;
121
21.8k
  }
122
21.8k
123
21.8k
  if (LocVT == MVT::i1 ||
124
21.8k
      
LocVT == MVT::i821.8k
||
125
21.8k
      
LocVT == MVT::i1621.2k
) {
126
1.15k
    LocVT = MVT::i32;
127
1.15k
    if (ArgFlags.isSExt())
128
6
        LocInfo = CCValAssign::SExt;
129
1.14k
    else if (ArgFlags.isZExt())
130
26
        LocInfo = CCValAssign::ZExt;
131
1.12k
    else
132
1.12k
        LocInfo = CCValAssign::AExt;
133
1.15k
  }
134
21.8k
135
21.8k
  if (LocVT == MVT::i32) {
136
4.26k
    static const MCPhysReg RegList1[] = {
137
4.26k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
138
4.26k
    };
139
4.26k
    static const MCPhysReg RegList2[] = {
140
4.26k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
141
4.26k
    };
142
4.26k
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
143
4.19k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
144
4.19k
      return false;
145
4.19k
    }
146
17.6k
  }
147
17.6k
148
17.6k
  if (LocVT == MVT::i64) {
149
6.42k
    if (ArgFlags.isSplit()) {
150
158
      static const MCPhysReg RegList3[] = {
151
158
        AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
152
158
      };
153
158
      static const MCPhysReg RegList4[] = {
154
158
        AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
155
158
      };
156
158
      if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
157
109
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
158
109
        return false;
159
109
      }
160
17.5k
    }
161
6.42k
  }
162
17.5k
163
17.5k
  if (LocVT == MVT::i64) {
164
6.31k
    if (ArgFlags.isSplit()) {
165
49
      static const MCPhysReg ShadowRegList5[] = {
166
49
        AArch64::X7
167
49
      };
168
49
      unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5);
169
49
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
170
49
      return false;
171
49
    }
172
17.4k
  }
173
17.4k
174
17.4k
  if (LocVT == MVT::i64) {
175
6.26k
    static const MCPhysReg RegList7[] = {
176
6.26k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
177
6.26k
    };
178
6.26k
    static const MCPhysReg RegList8[] = {
179
6.26k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
180
6.26k
    };
181
6.26k
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
182
6.15k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
183
6.15k
      return false;
184
6.15k
    }
185
11.3k
  }
186
11.3k
187
11.3k
  if (LocVT == MVT::f16) {
188
334
    static const MCPhysReg RegList9[] = {
189
334
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
190
334
    };
191
334
    static const MCPhysReg RegList10[] = {
192
334
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
193
334
    };
194
334
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
195
334
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
196
334
      return false;
197
334
    }
198
10.9k
  }
199
10.9k
200
10.9k
  if (LocVT == MVT::f32) {
201
821
    static const MCPhysReg RegList11[] = {
202
821
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
203
821
    };
204
821
    static const MCPhysReg RegList12[] = {
205
821
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
206
821
    };
207
821
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
208
816
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
209
816
      return false;
210
816
    }
211
10.1k
  }
212
10.1k
213
10.1k
  if (LocVT == MVT::f64) {
214
766
    static const MCPhysReg RegList13[] = {
215
766
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
216
766
    };
217
766
    static const MCPhysReg RegList14[] = {
218
766
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
219
766
    };
220
766
    if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
221
748
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
222
748
      return false;
223
748
    }
224
9.43k
  }
225
9.43k
226
9.43k
  if (LocVT == MVT::v1i64 ||
227
9.43k
      
LocVT == MVT::v2i329.22k
||
228
9.43k
      
LocVT == MVT::v4i167.84k
||
229
9.43k
      
LocVT == MVT::v8i86.81k
||
230
9.43k
      
LocVT == MVT::v1f646.30k
||
231
9.43k
      
LocVT == MVT::v2f326.16k
||
232
9.43k
      
LocVT == MVT::v4f166.16k
) {
233
3.49k
    static const MCPhysReg RegList15[] = {
234
3.49k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
235
3.49k
    };
236
3.49k
    static const MCPhysReg RegList16[] = {
237
3.49k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
238
3.49k
    };
239
3.49k
    if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
240
3.49k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
241
3.49k
      return false;
242
3.49k
    }
243
5.93k
  }
244
5.93k
245
5.93k
  if (LocVT == MVT::f128 ||
246
5.93k
      
LocVT == MVT::v2i645.38k
||
247
5.93k
      
LocVT == MVT::v4i323.75k
||
248
5.93k
      
LocVT == MVT::v8i162.05k
||
249
5.93k
      
LocVT == MVT::v16i81.01k
||
250
5.93k
      
LocVT == MVT::v4f32421
||
251
5.93k
      
LocVT == MVT::v2f64421
||
252
5.93k
      
LocVT == MVT::v8f16421
) {
253
5.73k
    static const MCPhysReg RegList17[] = {
254
5.73k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
255
5.73k
    };
256
5.73k
    if (unsigned Reg = State.AllocateReg(RegList17)) {
257
5.73k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
258
5.73k
      return false;
259
5.73k
    }
260
205
  }
261
205
262
205
  if (LocVT == MVT::i1 ||
263
205
      LocVT == MVT::i8 ||
264
205
      LocVT == MVT::i16 ||
265
205
      LocVT == MVT::f16) {
266
0
    unsigned Offset18 = State.AllocateStack(8, 8);
267
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
268
0
    return false;
269
0
  }
270
205
271
205
  if (LocVT == MVT::i32 ||
272
205
      
LocVT == MVT::f32141
) {
273
69
    unsigned Offset19 = State.AllocateStack(8, 8);
274
69
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
275
69
    return false;
276
69
  }
277
136
278
136
  if (LocVT == MVT::i64 ||
279
136
      
LocVT == MVT::f6429
||
280
136
      
LocVT == MVT::v1f6411
||
281
136
      
LocVT == MVT::v2f3211
||
282
136
      
LocVT == MVT::v1i6411
||
283
136
      
LocVT == MVT::v2i3211
||
284
136
      
LocVT == MVT::v4i1611
||
285
136
      
LocVT == MVT::v8i811
||
286
136
      
LocVT == MVT::v4f1611
) {
287
126
    unsigned Offset20 = State.AllocateStack(8, 8);
288
126
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo));
289
126
    return false;
290
126
  }
291
10
292
10
  if (LocVT == MVT::f128 ||
293
10
      
LocVT == MVT::v2i649
||
294
10
      
LocVT == MVT::v4i326
||
295
10
      
LocVT == MVT::v8i166
||
296
10
      
LocVT == MVT::v16i86
||
297
10
      
LocVT == MVT::v4f326
||
298
10
      
LocVT == MVT::v2f646
||
299
10
      
LocVT == MVT::v8f166
) {
300
5
    unsigned Offset21 = State.AllocateStack(16, 16);
301
5
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo));
302
5
    return false;
303
5
  }
304
5
305
5
  return true;  // CC didn't match.
306
5
}
AArch64FastISel.cpp:CC_AArch64_AAPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
37
63
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
38
63
39
63
  if (LocVT == MVT::iPTR) {
40
0
    LocVT = MVT::i64;
41
0
    LocInfo = CCValAssign::BCvt;
42
0
  }
43
63
44
63
  if (LocVT == MVT::v2f32) {
45
2
    LocVT = MVT::v2i32;
46
2
    LocInfo = CCValAssign::BCvt;
47
2
  }
48
63
49
63
  if (LocVT == MVT::v2f64 ||
50
63
      LocVT == MVT::v4f32) {
51
0
    LocVT = MVT::v2i64;
52
0
    LocInfo = CCValAssign::BCvt;
53
0
  }
54
63
55
63
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
56
57
    if (LocVT == MVT::v2i32 ||
57
57
        
LocVT == MVT::v2f3253
||
58
57
        
LocVT == MVT::v4i1653
||
59
57
        
LocVT == MVT::v4f1651
||
60
57
        
LocVT == MVT::v8i851
) {
61
8
      LocVT = MVT::f64;
62
8
      LocInfo = CCValAssign::BCvt;
63
8
    }
64
57
  }
65
63
66
63
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
67
57
    if (LocVT == MVT::v2i64 ||
68
57
        LocVT == MVT::v2f64 ||
69
57
        LocVT == MVT::v4i32 ||
70
57
        LocVT == MVT::v4f32 ||
71
57
        LocVT == MVT::v8i16 ||
72
57
        LocVT == MVT::v8f16 ||
73
57
        LocVT == MVT::v16i8) {
74
0
      LocVT = MVT::f128;
75
0
      LocInfo = CCValAssign::BCvt;
76
0
    }
77
57
  }
78
63
79
63
  if (ArgFlags.isSRet()) {
80
0
    if (LocVT == MVT::i64) {
81
0
      if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
82
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
83
0
        return false;
84
0
      }
85
63
    }
86
0
  }
87
63
88
63
  if (ArgFlags.isByVal()) {
89
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
90
0
    return false;
91
0
  }
92
63
93
63
  if (ArgFlags.isNest()) {
94
0
    if (unsigned Reg = State.AllocateReg(AArch64::X18)) {
95
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
96
0
      return false;
97
0
    }
98
63
  }
99
63
100
63
  if (ArgFlags.isSwiftSelf()) {
101
0
    if (LocVT == MVT::i64) {
102
0
      if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
103
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
104
0
        return false;
105
0
      }
106
63
    }
107
0
  }
108
63
109
63
  if (ArgFlags.isSwiftError()) {
110
0
    if (LocVT == MVT::i64) {
111
0
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
112
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
113
0
        return false;
114
0
      }
115
63
    }
116
0
  }
117
63
118
63
  if (ArgFlags.isInConsecutiveRegs()) {
119
0
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
120
0
        return false;
121
63
  }
122
63
123
63
  if (LocVT == MVT::i1 ||
124
63
      
LocVT == MVT::i861
||
125
63
      
LocVT == MVT::i1640
) {
126
26
    LocVT = MVT::i32;
127
26
    if (ArgFlags.isSExt())
128
3
        LocInfo = CCValAssign::SExt;
129
23
    else if (ArgFlags.isZExt())
130
14
        LocInfo = CCValAssign::ZExt;
131
9
    else
132
9
        LocInfo = CCValAssign::AExt;
133
26
  }
134
63
135
63
  if (LocVT == MVT::i32) {
136
32
    static const MCPhysReg RegList1[] = {
137
32
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
138
32
    };
139
32
    static const MCPhysReg RegList2[] = {
140
32
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
141
32
    };
142
32
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
143
30
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
144
30
      return false;
145
30
    }
146
33
  }
147
33
148
33
  if (LocVT == MVT::i64) {
149
14
    if (ArgFlags.isSplit()) {
150
0
      static const MCPhysReg RegList3[] = {
151
0
        AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
152
0
      };
153
0
      static const MCPhysReg RegList4[] = {
154
0
        AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
155
0
      };
156
0
      if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
157
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
158
0
        return false;
159
0
      }
160
33
    }
161
14
  }
162
33
163
33
  if (LocVT == MVT::i64) {
164
14
    if (ArgFlags.isSplit()) {
165
0
      static const MCPhysReg ShadowRegList5[] = {
166
0
        AArch64::X7
167
0
      };
168
0
      unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5);
169
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
170
0
      return false;
171
0
    }
172
33
  }
173
33
174
33
  if (LocVT == MVT::i64) {
175
14
    static const MCPhysReg RegList7[] = {
176
14
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
177
14
    };
178
14
    static const MCPhysReg RegList8[] = {
179
14
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
180
14
    };
181
14
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
182
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
183
14
      return false;
184
14
    }
185
19
  }
186
19
187
19
  if (LocVT == MVT::f16) {
188
0
    static const MCPhysReg RegList9[] = {
189
0
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
190
0
    };
191
0
    static const MCPhysReg RegList10[] = {
192
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
193
0
    };
194
0
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
195
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
196
0
      return false;
197
0
    }
198
19
  }
199
19
200
19
  if (LocVT == MVT::f32) {
201
0
    static const MCPhysReg RegList11[] = {
202
0
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
203
0
    };
204
0
    static const MCPhysReg RegList12[] = {
205
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
206
0
    };
207
0
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
208
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
209
0
      return false;
210
0
    }
211
19
  }
212
19
213
19
  if (LocVT == MVT::f64) {
214
15
    static const MCPhysReg RegList13[] = {
215
15
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
216
15
    };
217
15
    static const MCPhysReg RegList14[] = {
218
15
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
219
15
    };
220
15
    if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
221
15
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
222
15
      return false;
223
15
    }
224
4
  }
225
4
226
4
  if (LocVT == MVT::v1i64 ||
227
4
      
LocVT == MVT::v2i322
||
228
4
      
LocVT == MVT::v4i162
||
229
4
      
LocVT == MVT::v8i82
||
230
4
      
LocVT == MVT::v1f642
||
231
4
      
LocVT == MVT::v2f322
||
232
4
      
LocVT == MVT::v4f162
) {
233
2
    static const MCPhysReg RegList15[] = {
234
2
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
235
2
    };
236
2
    static const MCPhysReg RegList16[] = {
237
2
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
238
2
    };
239
2
    if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
240
2
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
241
2
      return false;
242
2
    }
243
2
  }
244
2
245
2
  if (LocVT == MVT::f128 ||
246
2
      LocVT == MVT::v2i64 ||
247
2
      LocVT == MVT::v4i32 ||
248
2
      LocVT == MVT::v8i16 ||
249
2
      LocVT == MVT::v16i8 ||
250
2
      LocVT == MVT::v4f32 ||
251
2
      LocVT == MVT::v2f64 ||
252
2
      LocVT == MVT::v8f16) {
253
0
    static const MCPhysReg RegList17[] = {
254
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
255
0
    };
256
0
    if (unsigned Reg = State.AllocateReg(RegList17)) {
257
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
258
0
      return false;
259
0
    }
260
2
  }
261
2
262
2
  if (LocVT == MVT::i1 ||
263
2
      LocVT == MVT::i8 ||
264
2
      LocVT == MVT::i16 ||
265
2
      LocVT == MVT::f16) {
266
0
    unsigned Offset18 = State.AllocateStack(8, 8);
267
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
268
0
    return false;
269
0
  }
270
2
271
2
  if (LocVT == MVT::i32 ||
272
2
      
LocVT == MVT::f320
) {
273
2
    unsigned Offset19 = State.AllocateStack(8, 8);
274
2
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
275
2
    return false;
276
2
  }
277
0
278
0
  if (LocVT == MVT::i64 ||
279
0
      LocVT == MVT::f64 ||
280
0
      LocVT == MVT::v1f64 ||
281
0
      LocVT == MVT::v2f32 ||
282
0
      LocVT == MVT::v1i64 ||
283
0
      LocVT == MVT::v2i32 ||
284
0
      LocVT == MVT::v4i16 ||
285
0
      LocVT == MVT::v8i8 ||
286
0
      LocVT == MVT::v4f16) {
287
0
    unsigned Offset20 = State.AllocateStack(8, 8);
288
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo));
289
0
    return false;
290
0
  }
291
0
292
0
  if (LocVT == MVT::f128 ||
293
0
      LocVT == MVT::v2i64 ||
294
0
      LocVT == MVT::v4i32 ||
295
0
      LocVT == MVT::v8i16 ||
296
0
      LocVT == MVT::v16i8 ||
297
0
      LocVT == MVT::v4f32 ||
298
0
      LocVT == MVT::v2f64 ||
299
0
      LocVT == MVT::v8f16) {
300
0
    unsigned Offset21 = State.AllocateStack(16, 16);
301
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo));
302
0
    return false;
303
0
  }
304
0
305
0
  return true;  // CC didn't match.
306
0
}
AArch64ISelLowering.cpp:CC_AArch64_AAPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
37
22.1k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
38
22.1k
39
22.1k
  if (LocVT == MVT::iPTR) {
40
0
    LocVT = MVT::i64;
41
0
    LocInfo = CCValAssign::BCvt;
42
0
  }
43
22.1k
44
22.1k
  if (LocVT == MVT::v2f32) {
45
486
    LocVT = MVT::v2i32;
46
486
    LocInfo = CCValAssign::BCvt;
47
486
  }
48
22.1k
49
22.1k
  if (LocVT == MVT::v2f64 ||
50
22.1k
      
LocVT == MVT::v4f3221.6k
) {
51
1.05k
    LocVT = MVT::v2i64;
52
1.05k
    LocInfo = CCValAssign::BCvt;
53
1.05k
  }
54
22.1k
55
22.1k
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
56
1.55k
    if (LocVT == MVT::v2i32 ||
57
1.55k
        
LocVT == MVT::v2f321.49k
||
58
1.55k
        
LocVT == MVT::v4i161.49k
||
59
1.55k
        
LocVT == MVT::v4f161.46k
||
60
1.55k
        
LocVT == MVT::v8i81.45k
) {
61
131
      LocVT = MVT::f64;
62
131
      LocInfo = CCValAssign::BCvt;
63
131
    }
64
1.55k
  }
65
22.1k
66
22.1k
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
67
1.55k
    if (LocVT == MVT::v2i64 ||
68
1.55k
        
LocVT == MVT::v2f641.46k
||
69
1.55k
        
LocVT == MVT::v4i321.46k
||
70
1.55k
        
LocVT == MVT::v4f321.43k
||
71
1.55k
        
LocVT == MVT::v8i161.43k
||
72
1.55k
        
LocVT == MVT::v8f161.39k
||
73
1.55k
        
LocVT == MVT::v16i81.39k
) {
74
196
      LocVT = MVT::f128;
75
196
      LocInfo = CCValAssign::BCvt;
76
196
    }
77
1.55k
  }
78
22.1k
79
22.1k
  if (ArgFlags.isSRet()) {
80
13
    if (LocVT == MVT::i64) {
81
13
      if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
82
13
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
83
13
        return false;
84
13
      }
85
22.1k
    }
86
13
  }
87
22.1k
88
22.1k
  if (ArgFlags.isByVal()) {
89
15
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
90
15
    return false;
91
15
  }
92
22.1k
93
22.1k
  if (ArgFlags.isNest()) {
94
2
    if (unsigned Reg = State.AllocateReg(AArch64::X18)) {
95
2
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
96
2
      return false;
97
2
    }
98
22.1k
  }
99
22.1k
100
22.1k
  if (ArgFlags.isSwiftSelf()) {
101
14
    if (LocVT == MVT::i64) {
102
14
      if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
103
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
104
14
        return false;
105
14
      }
106
22.1k
    }
107
14
  }
108
22.1k
109
22.1k
  if (ArgFlags.isSwiftError()) {
110
2
    if (LocVT == MVT::i64) {
111
2
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
112
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
113
2
        return false;
114
2
      }
115
22.1k
    }
116
2
  }
117
22.1k
118
22.1k
  if (ArgFlags.isInConsecutiveRegs()) {
119
869
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
120
349
        return false;
121
21.7k
  }
122
21.7k
123
21.7k
  if (LocVT == MVT::i1 ||
124
21.7k
      
LocVT == MVT::i821.7k
||
125
21.7k
      
LocVT == MVT::i1621.1k
) {
126
1.12k
    LocVT = MVT::i32;
127
1.12k
    if (ArgFlags.isSExt())
128
3
        LocInfo = CCValAssign::SExt;
129
1.12k
    else if (ArgFlags.isZExt())
130
12
        LocInfo = CCValAssign::ZExt;
131
1.11k
    else
132
1.11k
        LocInfo = CCValAssign::AExt;
133
1.12k
  }
134
21.7k
135
21.7k
  if (LocVT == MVT::i32) {
136
4.22k
    static const MCPhysReg RegList1[] = {
137
4.22k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
138
4.22k
    };
139
4.22k
    static const MCPhysReg RegList2[] = {
140
4.22k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
141
4.22k
    };
142
4.22k
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
143
4.16k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
144
4.16k
      return false;
145
4.16k
    }
146
17.6k
  }
147
17.6k
148
17.6k
  if (LocVT == MVT::i64) {
149
6.40k
    if (ArgFlags.isSplit()) {
150
158
      static const MCPhysReg RegList3[] = {
151
158
        AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
152
158
      };
153
158
      static const MCPhysReg RegList4[] = {
154
158
        AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
155
158
      };
156
158
      if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
157
109
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
158
109
        return false;
159
109
      }
160
17.5k
    }
161
6.40k
  }
162
17.5k
163
17.5k
  if (LocVT == MVT::i64) {
164
6.29k
    if (ArgFlags.isSplit()) {
165
49
      static const MCPhysReg ShadowRegList5[] = {
166
49
        AArch64::X7
167
49
      };
168
49
      unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5);
169
49
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
170
49
      return false;
171
49
    }
172
17.4k
  }
173
17.4k
174
17.4k
  if (LocVT == MVT::i64) {
175
6.24k
    static const MCPhysReg RegList7[] = {
176
6.24k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
177
6.24k
    };
178
6.24k
    static const MCPhysReg RegList8[] = {
179
6.24k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
180
6.24k
    };
181
6.24k
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
182
6.14k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
183
6.14k
      return false;
184
6.14k
    }
185
11.3k
  }
186
11.3k
187
11.3k
  if (LocVT == MVT::f16) {
188
334
    static const MCPhysReg RegList9[] = {
189
334
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
190
334
    };
191
334
    static const MCPhysReg RegList10[] = {
192
334
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
193
334
    };
194
334
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
195
334
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
196
334
      return false;
197
334
    }
198
10.9k
  }
199
10.9k
200
10.9k
  if (LocVT == MVT::f32) {
201
821
    static const MCPhysReg RegList11[] = {
202
821
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
203
821
    };
204
821
    static const MCPhysReg RegList12[] = {
205
821
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
206
821
    };
207
821
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
208
816
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
209
816
      return false;
210
816
    }
211
10.1k
  }
212
10.1k
213
10.1k
  if (LocVT == MVT::f64) {
214
751
    static const MCPhysReg RegList13[] = {
215
751
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
216
751
    };
217
751
    static const MCPhysReg RegList14[] = {
218
751
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
219
751
    };
220
751
    if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
221
733
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
222
733
      return false;
223
733
    }
224
9.42k
  }
225
9.42k
226
9.42k
  if (LocVT == MVT::v1i64 ||
227
9.42k
      
LocVT == MVT::v2i329.22k
||
228
9.42k
      
LocVT == MVT::v4i167.84k
||
229
9.42k
      
LocVT == MVT::v8i86.81k
||
230
9.42k
      
LocVT == MVT::v1f646.30k
||
231
9.42k
      
LocVT == MVT::v2f326.15k
||
232
9.42k
      
LocVT == MVT::v4f166.15k
) {
233
3.49k
    static const MCPhysReg RegList15[] = {
234
3.49k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
235
3.49k
    };
236
3.49k
    static const MCPhysReg RegList16[] = {
237
3.49k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
238
3.49k
    };
239
3.49k
    if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
240
3.49k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
241
3.49k
      return false;
242
3.49k
    }
243
5.93k
  }
244
5.93k
245
5.93k
  if (LocVT == MVT::f128 ||
246
5.93k
      
LocVT == MVT::v2i645.38k
||
247
5.93k
      
LocVT == MVT::v4i323.74k
||
248
5.93k
      
LocVT == MVT::v8i162.05k
||
249
5.93k
      
LocVT == MVT::v16i81.01k
||
250
5.93k
      
LocVT == MVT::v4f32419
||
251
5.93k
      
LocVT == MVT::v2f64419
||
252
5.93k
      
LocVT == MVT::v8f16419
) {
253
5.73k
    static const MCPhysReg RegList17[] = {
254
5.73k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
255
5.73k
    };
256
5.73k
    if (unsigned Reg = State.AllocateReg(RegList17)) {
257
5.73k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
258
5.73k
      return false;
259
5.73k
    }
260
203
  }
261
203
262
203
  if (LocVT == MVT::i1 ||
263
203
      LocVT == MVT::i8 ||
264
203
      LocVT == MVT::i16 ||
265
203
      LocVT == MVT::f16) {
266
0
    unsigned Offset18 = State.AllocateStack(8, 8);
267
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
268
0
    return false;
269
0
  }
270
203
271
203
  if (LocVT == MVT::i32 ||
272
203
      
LocVT == MVT::f32141
) {
273
67
    unsigned Offset19 = State.AllocateStack(8, 8);
274
67
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
275
67
    return false;
276
67
  }
277
136
278
136
  if (LocVT == MVT::i64 ||
279
136
      
LocVT == MVT::f6429
||
280
136
      
LocVT == MVT::v1f6411
||
281
136
      
LocVT == MVT::v2f3211
||
282
136
      
LocVT == MVT::v1i6411
||
283
136
      
LocVT == MVT::v2i3211
||
284
136
      
LocVT == MVT::v4i1611
||
285
136
      
LocVT == MVT::v8i811
||
286
136
      
LocVT == MVT::v4f1611
) {
287
126
    unsigned Offset20 = State.AllocateStack(8, 8);
288
126
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo));
289
126
    return false;
290
126
  }
291
10
292
10
  if (LocVT == MVT::f128 ||
293
10
      
LocVT == MVT::v2i649
||
294
10
      
LocVT == MVT::v4i326
||
295
10
      
LocVT == MVT::v8i166
||
296
10
      
LocVT == MVT::v16i86
||
297
10
      
LocVT == MVT::v4f326
||
298
10
      
LocVT == MVT::v2f646
||
299
10
      
LocVT == MVT::v8f166
) {
300
5
    unsigned Offset21 = State.AllocateStack(16, 16);
301
5
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo));
302
5
    return false;
303
5
  }
304
5
305
5
  return true;  // CC didn't match.
306
5
}
307
308
309
static bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
310
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
311
4.91M
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
312
4.91M
313
4.91M
  if (LocVT == MVT::iPTR) {
314
0
    LocVT = MVT::i64;
315
0
    LocInfo = CCValAssign::BCvt;
316
0
  }
317
4.91M
318
4.91M
  if (LocVT == MVT::v2f32) {
319
98
    LocVT = MVT::v2i32;
320
98
    LocInfo = CCValAssign::BCvt;
321
98
  }
322
4.91M
323
4.91M
  if (LocVT == MVT::v2f64 ||
324
4.91M
      
LocVT == MVT::v4f324.91M
||
325
4.91M
      
LocVT == MVT::f1284.91M
) {
326
249
    LocVT = MVT::v2i64;
327
249
    LocInfo = CCValAssign::BCvt;
328
249
  }
329
4.91M
330
4.91M
  if (ArgFlags.isSRet()) {
331
9.33k
    if (LocVT == MVT::i64) {
332
9.33k
      if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
333
9.33k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
334
9.33k
        return false;
335
9.33k
      }
336
4.90M
    }
337
9.33k
  }
338
4.90M
339
4.90M
  if (ArgFlags.isByVal()) {
340
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
341
0
    return false;
342
0
  }
343
4.90M
344
4.90M
  if (ArgFlags.isSwiftSelf()) {
345
43
    if (LocVT == MVT::i64) {
346
43
      if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
347
43
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
348
43
        return false;
349
43
      }
350
4.90M
    }
351
43
  }
352
4.90M
353
4.90M
  if (ArgFlags.isSwiftError()) {
354
46
    if (LocVT == MVT::i64) {
355
46
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
356
46
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
357
46
        return false;
358
46
      }
359
4.90M
    }
360
46
  }
361
4.90M
362
4.90M
  if (ArgFlags.isInConsecutiveRegs()) {
363
1.16k
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
364
1.16k
        return false;
365
4.90M
  }
366
4.90M
367
4.90M
  if (LocVT == MVT::i1 ||
368
4.90M
      
LocVT == MVT::i84.89M
||
369
4.90M
      
LocVT == MVT::i164.86M
) {
370
45.6k
    LocVT = MVT::i32;
371
45.6k
    if (ArgFlags.isSExt())
372
6.57k
        LocInfo = CCValAssign::SExt;
373
39.0k
    else if (ArgFlags.isZExt())
374
18.3k
        LocInfo = CCValAssign::ZExt;
375
20.6k
    else
376
20.6k
        LocInfo = CCValAssign::AExt;
377
45.6k
  }
378
4.90M
379
4.90M
  if (LocVT == MVT::i32) {
380
698k
    static const MCPhysReg RegList1[] = {
381
698k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
382
698k
    };
383
698k
    static const MCPhysReg RegList2[] = {
384
698k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
385
698k
    };
386
698k
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
387
695k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
388
695k
      return false;
389
695k
    }
390
4.20M
  }
391
4.20M
392
4.20M
  if (LocVT == MVT::i64) {
393
4.15M
    if (ArgFlags.isSplit()) {
394
206
      static const MCPhysReg RegList3[] = {
395
206
        AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
396
206
      };
397
206
      static const MCPhysReg RegList4[] = {
398
206
        AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6
399
206
      };
400
206
      if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
401
186
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
402
186
        return false;
403
186
      }
404
4.20M
    }
405
4.15M
  }
406
4.20M
407
4.20M
  if (LocVT == MVT::i64) {
408
4.15M
    if (ArgFlags.isSplit()) {
409
20
      static const MCPhysReg ShadowRegList5[] = {
410
20
        AArch64::X7
411
20
      };
412
20
      unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5);
413
20
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
414
20
      return false;
415
20
    }
416
4.20M
  }
417
4.20M
418
4.20M
  if (LocVT == MVT::i64) {
419
4.15M
    static const MCPhysReg RegList7[] = {
420
4.15M
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
421
4.15M
    };
422
4.15M
    static const MCPhysReg RegList8[] = {
423
4.15M
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
424
4.15M
    };
425
4.15M
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
426
4.10M
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
427
4.10M
      return false;
428
4.10M
    }
429
100k
  }
430
100k
431
100k
  if (LocVT == MVT::f16) {
432
14
    static const MCPhysReg RegList9[] = {
433
14
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
434
14
    };
435
14
    static const MCPhysReg RegList10[] = {
436
14
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
437
14
    };
438
14
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
439
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
440
14
      return false;
441
14
    }
442
100k
  }
443
100k
444
100k
  if (LocVT == MVT::f32) {
445
3.10k
    static const MCPhysReg RegList11[] = {
446
3.10k
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
447
3.10k
    };
448
3.10k
    static const MCPhysReg RegList12[] = {
449
3.10k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
450
3.10k
    };
451
3.10k
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
452
3.09k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
453
3.09k
      return false;
454
3.09k
    }
455
97.8k
  }
456
97.8k
457
97.8k
  if (LocVT == MVT::f64) {
458
47.3k
    static const MCPhysReg RegList13[] = {
459
47.3k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
460
47.3k
    };
461
47.3k
    static const MCPhysReg RegList14[] = {
462
47.3k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
463
47.3k
    };
464
47.3k
    if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
465
46.5k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
466
46.5k
      return false;
467
46.5k
    }
468
51.3k
  }
469
51.3k
470
51.3k
  if (LocVT == MVT::v1i64 ||
471
51.3k
      
LocVT == MVT::v2i3251.2k
||
472
51.3k
      
LocVT == MVT::v4i1651.0k
||
473
51.3k
      
LocVT == MVT::v8i850.9k
||
474
51.3k
      
LocVT == MVT::v1f6450.8k
||
475
51.3k
      
LocVT == MVT::v2f3250.7k
||
476
51.3k
      
LocVT == MVT::v4f1650.7k
) {
477
540
    static const MCPhysReg RegList15[] = {
478
540
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
479
540
    };
480
540
    static const MCPhysReg RegList16[] = {
481
540
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
482
540
    };
483
540
    if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
484
536
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
485
536
      return false;
486
536
    }
487
50.7k
  }
488
50.7k
489
50.7k
  if (LocVT == MVT::v2i64 ||
490
50.7k
      
LocVT == MVT::v4i3250.4k
||
491
50.7k
      
LocVT == MVT::v8i1650.2k
||
492
50.7k
      
LocVT == MVT::v16i850.1k
||
493
50.7k
      
LocVT == MVT::v4f3250.0k
||
494
50.7k
      
LocVT == MVT::v2f6450.0k
||
495
50.7k
      
LocVT == MVT::v8f1650.0k
) {
496
712
    static const MCPhysReg RegList17[] = {
497
712
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
498
712
    };
499
712
    if (unsigned Reg = State.AllocateReg(RegList17)) {
500
708
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
501
708
      return false;
502
708
    }
503
50.0k
  }
504
50.0k
505
50.0k
  if (ValVT == MVT::i1 || 
ValVT == MVT::i850.0k
) {
506
144
    unsigned Offset18 = State.AllocateStack(1, 1);
507
144
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
508
144
    return false;
509
144
  }
510
49.9k
511
49.9k
  if (ValVT == MVT::i16 || 
ValVT == MVT::f1649.9k
) {
512
32
    unsigned Offset19 = State.AllocateStack(2, 2);
513
32
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
514
32
    return false;
515
32
  }
516
49.9k
517
49.9k
  if (LocVT == MVT::i32 ||
518
49.9k
      
LocVT == MVT::f3247.3k
) {
519
2.58k
    unsigned Offset20 = State.AllocateStack(4, 4);
520
2.58k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo));
521
2.58k
    return false;
522
2.58k
  }
523
47.3k
524
47.3k
  if (LocVT == MVT::i64 ||
525
47.3k
      
LocVT == MVT::f64874
||
526
47.3k
      
LocVT == MVT::v1f648
||
527
47.3k
      
LocVT == MVT::v2f328
||
528
47.3k
      
LocVT == MVT::v1i648
||
529
47.3k
      
LocVT == MVT::v2i328
||
530
47.3k
      
LocVT == MVT::v4i164
||
531
47.3k
      
LocVT == MVT::v8i84
||
532
47.3k
      
LocVT == MVT::v4f164
) {
533
47.3k
    unsigned Offset21 = State.AllocateStack(8, 8);
534
47.3k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo));
535
47.3k
    return false;
536
47.3k
  }
537
4
538
4
  if (LocVT == MVT::v2i64 ||
539
4
      LocVT == MVT::v4i32 ||
540
4
      
LocVT == MVT::v8i160
||
541
4
      
LocVT == MVT::v16i80
||
542
4
      
LocVT == MVT::v4f320
||
543
4
      
LocVT == MVT::v2f640
||
544
4
      
LocVT == MVT::v8f160
) {
545
4
    unsigned Offset22 = State.AllocateStack(16, 16);
546
4
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset22, LocVT, LocInfo));
547
4
    return false;
548
4
  }
549
0
550
0
  return true;  // CC didn't match.
551
0
}
AArch64FastISel.cpp:CC_AArch64_DarwinPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
311
1.29k
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
312
1.29k
313
1.29k
  if (LocVT == MVT::iPTR) {
314
0
    LocVT = MVT::i64;
315
0
    LocInfo = CCValAssign::BCvt;
316
0
  }
317
1.29k
318
1.29k
  if (LocVT == MVT::v2f32) {
319
0
    LocVT = MVT::v2i32;
320
0
    LocInfo = CCValAssign::BCvt;
321
0
  }
322
1.29k
323
1.29k
  if (LocVT == MVT::v2f64 ||
324
1.29k
      LocVT == MVT::v4f32 ||
325
1.29k
      LocVT == MVT::f128) {
326
0
    LocVT = MVT::v2i64;
327
0
    LocInfo = CCValAssign::BCvt;
328
0
  }
329
1.29k
330
1.29k
  if (ArgFlags.isSRet()) {
331
0
    if (LocVT == MVT::i64) {
332
0
      if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
333
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
334
0
        return false;
335
0
      }
336
1.29k
    }
337
0
  }
338
1.29k
339
1.29k
  if (ArgFlags.isByVal()) {
340
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
341
0
    return false;
342
0
  }
343
1.29k
344
1.29k
  if (ArgFlags.isSwiftSelf()) {
345
0
    if (LocVT == MVT::i64) {
346
0
      if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
347
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
348
0
        return false;
349
0
      }
350
1.29k
    }
351
0
  }
352
1.29k
353
1.29k
  if (ArgFlags.isSwiftError()) {
354
0
    if (LocVT == MVT::i64) {
355
0
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
356
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
357
0
        return false;
358
0
      }
359
1.29k
    }
360
0
  }
361
1.29k
362
1.29k
  if (ArgFlags.isInConsecutiveRegs()) {
363
0
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
364
0
        return false;
365
1.29k
  }
366
1.29k
367
1.29k
  if (LocVT == MVT::i1 ||
368
1.29k
      
LocVT == MVT::i81.27k
||
369
1.29k
      
LocVT == MVT::i161.22k
) {
370
73
    LocVT = MVT::i32;
371
73
    if (ArgFlags.isSExt())
372
12
        LocInfo = CCValAssign::SExt;
373
61
    else if (ArgFlags.isZExt())
374
40
        LocInfo = CCValAssign::ZExt;
375
21
    else
376
21
        LocInfo = CCValAssign::AExt;
377
73
  }
378
1.29k
379
1.29k
  if (LocVT == MVT::i32) {
380
109
    static const MCPhysReg RegList1[] = {
381
109
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
382
109
    };
383
109
    static const MCPhysReg RegList2[] = {
384
109
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
385
109
    };
386
109
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
387
93
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
388
93
      return false;
389
93
    }
390
1.19k
  }
391
1.19k
392
1.19k
  if (LocVT == MVT::i64) {
393
1.14k
    if (ArgFlags.isSplit()) {
394
0
      static const MCPhysReg RegList3[] = {
395
0
        AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
396
0
      };
397
0
      static const MCPhysReg RegList4[] = {
398
0
        AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6
399
0
      };
400
0
      if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
401
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
402
0
        return false;
403
0
      }
404
1.19k
    }
405
1.14k
  }
406
1.19k
407
1.19k
  if (LocVT == MVT::i64) {
408
1.14k
    if (ArgFlags.isSplit()) {
409
0
      static const MCPhysReg ShadowRegList5[] = {
410
0
        AArch64::X7
411
0
      };
412
0
      unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5);
413
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
414
0
      return false;
415
0
    }
416
1.19k
  }
417
1.19k
418
1.19k
  if (LocVT == MVT::i64) {
419
1.14k
    static const MCPhysReg RegList7[] = {
420
1.14k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
421
1.14k
    };
422
1.14k
    static const MCPhysReg RegList8[] = {
423
1.14k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
424
1.14k
    };
425
1.14k
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
426
112
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
427
112
      return false;
428
112
    }
429
1.08k
  }
430
1.08k
431
1.08k
  if (LocVT == MVT::f16) {
432
0
    static const MCPhysReg RegList9[] = {
433
0
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
434
0
    };
435
0
    static const MCPhysReg RegList10[] = {
436
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
437
0
    };
438
0
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
439
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
440
0
      return false;
441
0
    }
442
1.08k
  }
443
1.08k
444
1.08k
  if (LocVT == MVT::f32) {
445
20
    static const MCPhysReg RegList11[] = {
446
20
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
447
20
    };
448
20
    static const MCPhysReg RegList12[] = {
449
20
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
450
20
    };
451
20
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
452
20
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
453
20
      return false;
454
20
    }
455
1.06k
  }
456
1.06k
457
1.06k
  if (LocVT == MVT::f64) {
458
20
    static const MCPhysReg RegList13[] = {
459
20
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
460
20
    };
461
20
    static const MCPhysReg RegList14[] = {
462
20
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
463
20
    };
464
20
    if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
465
20
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
466
20
      return false;
467
20
    }
468
1.04k
  }
469
1.04k
470
1.04k
  if (LocVT == MVT::v1i64 ||
471
1.04k
      LocVT == MVT::v2i32 ||
472
1.04k
      LocVT == MVT::v4i16 ||
473
1.04k
      LocVT == MVT::v8i8 ||
474
1.04k
      LocVT == MVT::v1f64 ||
475
1.04k
      LocVT == MVT::v2f32 ||
476
1.04k
      LocVT == MVT::v4f16) {
477
0
    static const MCPhysReg RegList15[] = {
478
0
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
479
0
    };
480
0
    static const MCPhysReg RegList16[] = {
481
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
482
0
    };
483
0
    if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
484
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
485
0
      return false;
486
0
    }
487
1.04k
  }
488
1.04k
489
1.04k
  if (LocVT == MVT::v2i64 ||
490
1.04k
      LocVT == MVT::v4i32 ||
491
1.04k
      LocVT == MVT::v8i16 ||
492
1.04k
      LocVT == MVT::v16i8 ||
493
1.04k
      LocVT == MVT::v4f32 ||
494
1.04k
      LocVT == MVT::v2f64 ||
495
1.04k
      LocVT == MVT::v8f16) {
496
0
    static const MCPhysReg RegList17[] = {
497
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
498
0
    };
499
0
    if (unsigned Reg = State.AllocateReg(RegList17)) {
500
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
501
0
      return false;
502
0
    }
503
1.04k
  }
504
1.04k
505
1.04k
  if (ValVT == MVT::i1 || 
ValVT == MVT::i81.04k
) {
506
13
    unsigned Offset18 = State.AllocateStack(1, 1);
507
13
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
508
13
    return false;
509
13
  }
510
1.03k
511
1.03k
  if (ValVT == MVT::i16 || 
ValVT == MVT::f161.03k
) {
512
1
    unsigned Offset19 = State.AllocateStack(2, 2);
513
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
514
1
    return false;
515
1
  }
516
1.03k
517
1.03k
  if (LocVT == MVT::i32 ||
518
1.03k
      
LocVT == MVT::f321.03k
) {
519
2
    unsigned Offset20 = State.AllocateStack(4, 4);
520
2
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo));
521
2
    return false;
522
2
  }
523
1.03k
524
1.03k
  if (LocVT == MVT::i64 ||
525
1.03k
      
LocVT == MVT::f640
||
526
1.03k
      
LocVT == MVT::v1f640
||
527
1.03k
      
LocVT == MVT::v2f320
||
528
1.03k
      
LocVT == MVT::v1i640
||
529
1.03k
      
LocVT == MVT::v2i320
||
530
1.03k
      
LocVT == MVT::v4i160
||
531
1.03k
      
LocVT == MVT::v8i80
||
532
1.03k
      
LocVT == MVT::v4f160
) {
533
1.03k
    unsigned Offset21 = State.AllocateStack(8, 8);
534
1.03k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo));
535
1.03k
    return false;
536
1.03k
  }
537
0
538
0
  if (LocVT == MVT::v2i64 ||
539
0
      LocVT == MVT::v4i32 ||
540
0
      LocVT == MVT::v8i16 ||
541
0
      LocVT == MVT::v16i8 ||
542
0
      LocVT == MVT::v4f32 ||
543
0
      LocVT == MVT::v2f64 ||
544
0
      LocVT == MVT::v8f16) {
545
0
    unsigned Offset22 = State.AllocateStack(16, 16);
546
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset22, LocVT, LocInfo));
547
0
    return false;
548
0
  }
549
0
550
0
  return true;  // CC didn't match.
551
0
}
AArch64ISelLowering.cpp:CC_AArch64_DarwinPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
311
4.90M
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
312
4.90M
313
4.90M
  if (LocVT == MVT::iPTR) {
314
0
    LocVT = MVT::i64;
315
0
    LocInfo = CCValAssign::BCvt;
316
0
  }
317
4.90M
318
4.90M
  if (LocVT == MVT::v2f32) {
319
98
    LocVT = MVT::v2i32;
320
98
    LocInfo = CCValAssign::BCvt;
321
98
  }
322
4.90M
323
4.90M
  if (LocVT == MVT::v2f64 ||
324
4.90M
      
LocVT == MVT::v4f324.90M
||
325
4.90M
      
LocVT == MVT::f1284.90M
) {
326
249
    LocVT = MVT::v2i64;
327
249
    LocInfo = CCValAssign::BCvt;
328
249
  }
329
4.90M
330
4.90M
  if (ArgFlags.isSRet()) {
331
9.33k
    if (LocVT == MVT::i64) {
332
9.33k
      if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
333
9.33k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
334
9.33k
        return false;
335
9.33k
      }
336
4.90M
    }
337
9.33k
  }
338
4.90M
339
4.90M
  if (ArgFlags.isByVal()) {
340
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
341
0
    return false;
342
0
  }
343
4.90M
344
4.90M
  if (ArgFlags.isSwiftSelf()) {
345
43
    if (LocVT == MVT::i64) {
346
43
      if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
347
43
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
348
43
        return false;
349
43
      }
350
4.90M
    }
351
43
  }
352
4.90M
353
4.90M
  if (ArgFlags.isSwiftError()) {
354
46
    if (LocVT == MVT::i64) {
355
46
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
356
46
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
357
46
        return false;
358
46
      }
359
4.90M
    }
360
46
  }
361
4.90M
362
4.90M
  if (ArgFlags.isInConsecutiveRegs()) {
363
1.16k
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
364
1.16k
        return false;
365
4.89M
  }
366
4.89M
367
4.89M
  if (LocVT == MVT::i1 ||
368
4.89M
      
LocVT == MVT::i84.89M
||
369
4.89M
      
LocVT == MVT::i164.86M
) {
370
45.5k
    LocVT = MVT::i32;
371
45.5k
    if (ArgFlags.isSExt())
372
6.56k
        LocInfo = CCValAssign::SExt;
373
38.9k
    else if (ArgFlags.isZExt())
374
18.3k
        LocInfo = CCValAssign::ZExt;
375
20.6k
    else
376
20.6k
        LocInfo = CCValAssign::AExt;
377
45.5k
  }
378
4.89M
379
4.89M
  if (LocVT == MVT::i32) {
380
698k
    static const MCPhysReg RegList1[] = {
381
698k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
382
698k
    };
383
698k
    static const MCPhysReg RegList2[] = {
384
698k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
385
698k
    };
386
698k
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
387
695k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
388
695k
      return false;
389
695k
    }
390
4.20M
  }
391
4.20M
392
4.20M
  if (LocVT == MVT::i64) {
393
4.14M
    if (ArgFlags.isSplit()) {
394
206
      static const MCPhysReg RegList3[] = {
395
206
        AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
396
206
      };
397
206
      static const MCPhysReg RegList4[] = {
398
206
        AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6
399
206
      };
400
206
      if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
401
186
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
402
186
        return false;
403
186
      }
404
4.20M
    }
405
4.14M
  }
406
4.20M
407
4.20M
  if (LocVT == MVT::i64) {
408
4.14M
    if (ArgFlags.isSplit()) {
409
20
      static const MCPhysReg ShadowRegList5[] = {
410
20
        AArch64::X7
411
20
      };
412
20
      unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5);
413
20
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
414
20
      return false;
415
20
    }
416
4.20M
  }
417
4.20M
418
4.20M
  if (LocVT == MVT::i64) {
419
4.14M
    static const MCPhysReg RegList7[] = {
420
4.14M
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
421
4.14M
    };
422
4.14M
    static const MCPhysReg RegList8[] = {
423
4.14M
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
424
4.14M
    };
425
4.14M
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
426
4.10M
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
427
4.10M
      return false;
428
4.10M
    }
429
99.8k
  }
430
99.8k
431
99.8k
  if (LocVT == MVT::f16) {
432
14
    static const MCPhysReg RegList9[] = {
433
14
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
434
14
    };
435
14
    static const MCPhysReg RegList10[] = {
436
14
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
437
14
    };
438
14
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
439
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
440
14
      return false;
441
14
    }
442
99.8k
  }
443
99.8k
444
99.8k
  if (LocVT == MVT::f32) {
445
3.08k
    static const MCPhysReg RegList11[] = {
446
3.08k
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
447
3.08k
    };
448
3.08k
    static const MCPhysReg RegList12[] = {
449
3.08k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
450
3.08k
    };
451
3.08k
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
452
3.07k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
453
3.07k
      return false;
454
3.07k
    }
455
96.7k
  }
456
96.7k
457
96.7k
  if (LocVT == MVT::f64) {
458
47.3k
    static const MCPhysReg RegList13[] = {
459
47.3k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
460
47.3k
    };
461
47.3k
    static const MCPhysReg RegList14[] = {
462
47.3k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
463
47.3k
    };
464
47.3k
    if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
465
46.5k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
466
46.5k
      return false;
467
46.5k
    }
468
50.2k
  }
469
50.2k
470
50.2k
  if (LocVT == MVT::v1i64 ||
471
50.2k
      
LocVT == MVT::v2i3250.2k
||
472
50.2k
      
LocVT == MVT::v4i1649.9k
||
473
50.2k
      
LocVT == MVT::v8i849.9k
||
474
50.2k
      
LocVT == MVT::v1f6449.8k
||
475
50.2k
      
LocVT == MVT::v2f3249.7k
||
476
50.2k
      
LocVT == MVT::v4f1649.7k
) {
477
540
    static const MCPhysReg RegList15[] = {
478
540
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
479
540
    };
480
540
    static const MCPhysReg RegList16[] = {
481
540
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
482
540
    };
483
540
    if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
484
536
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
485
536
      return false;
486
536
    }
487
49.7k
  }
488
49.7k
489
49.7k
  if (LocVT == MVT::v2i64 ||
490
49.7k
      
LocVT == MVT::v4i3249.4k
||
491
49.7k
      
LocVT == MVT::v8i1649.2k
||
492
49.7k
      
LocVT == MVT::v16i849.1k
||
493
49.7k
      
LocVT == MVT::v4f3249.0k
||
494
49.7k
      
LocVT == MVT::v2f6449.0k
||
495
49.7k
      
LocVT == MVT::v8f1649.0k
) {
496
712
    static const MCPhysReg RegList17[] = {
497
712
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
498
712
    };
499
712
    if (unsigned Reg = State.AllocateReg(RegList17)) {
500
708
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
501
708
      return false;
502
708
    }
503
49.0k
  }
504
49.0k
505
49.0k
  if (ValVT == MVT::i1 || 
ValVT == MVT::i848.9k
) {
506
131
    unsigned Offset18 = State.AllocateStack(1, 1);
507
131
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
508
131
    return false;
509
131
  }
510
48.9k
511
48.9k
  if (ValVT == MVT::i16 || 
ValVT == MVT::f1648.8k
) {
512
31
    unsigned Offset19 = State.AllocateStack(2, 2);
513
31
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
514
31
    return false;
515
31
  }
516
48.8k
517
48.8k
  if (LocVT == MVT::i32 ||
518
48.8k
      
LocVT == MVT::f3246.3k
) {
519
2.58k
    unsigned Offset20 = State.AllocateStack(4, 4);
520
2.58k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo));
521
2.58k
    return false;
522
2.58k
  }
523
46.2k
524
46.2k
  if (LocVT == MVT::i64 ||
525
46.2k
      
LocVT == MVT::f64874
||
526
46.2k
      
LocVT == MVT::v1f648
||
527
46.2k
      
LocVT == MVT::v2f328
||
528
46.2k
      
LocVT == MVT::v1i648
||
529
46.2k
      
LocVT == MVT::v2i328
||
530
46.2k
      
LocVT == MVT::v4i164
||
531
46.2k
      
LocVT == MVT::v8i84
||
532
46.2k
      
LocVT == MVT::v4f164
) {
533
46.2k
    unsigned Offset21 = State.AllocateStack(8, 8);
534
46.2k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo));
535
46.2k
    return false;
536
46.2k
  }
537
4
538
4
  if (LocVT == MVT::v2i64 ||
539
4
      LocVT == MVT::v4i32 ||
540
4
      
LocVT == MVT::v8i160
||
541
4
      
LocVT == MVT::v16i80
||
542
4
      
LocVT == MVT::v4f320
||
543
4
      
LocVT == MVT::v2f640
||
544
4
      
LocVT == MVT::v8f160
) {
545
4
    unsigned Offset22 = State.AllocateStack(16, 16);
546
4
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset22, LocVT, LocInfo));
547
4
    return false;
548
4
  }
549
0
550
0
  return true;  // CC didn't match.
551
0
}
552
553
554
static bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
555
                                        MVT LocVT, CCValAssign::LocInfo LocInfo,
556
80.7k
                                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
557
80.7k
558
80.7k
  if (LocVT == MVT::iPTR) {
559
0
    LocVT = MVT::i64;
560
0
    LocInfo = CCValAssign::BCvt;
561
0
  }
562
80.7k
563
80.7k
  if (LocVT == MVT::v2f32) {
564
0
    LocVT = MVT::v2i32;
565
0
    LocInfo = CCValAssign::BCvt;
566
0
  }
567
80.7k
568
80.7k
  if (LocVT == MVT::v2f64 ||
569
80.7k
      LocVT == MVT::v4f32 ||
570
80.7k
      LocVT == MVT::f128) {
571
0
    LocVT = MVT::v2i64;
572
0
    LocInfo = CCValAssign::BCvt;
573
0
  }
574
80.7k
575
80.7k
  if (ArgFlags.isInConsecutiveRegs()) {
576
17
    if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
577
17
        return false;
578
80.7k
  }
579
80.7k
580
80.7k
  if (LocVT == MVT::i8 ||
581
80.7k
      
LocVT == MVT::i1680.7k
||
582
80.7k
      
LocVT == MVT::i3280.7k
) {
583
26.6k
    LocVT = MVT::i64;
584
26.6k
    if (ArgFlags.isSExt())
585
0
        LocInfo = CCValAssign::SExt;
586
26.6k
    else if (ArgFlags.isZExt())
587
0
        LocInfo = CCValAssign::ZExt;
588
26.6k
    else
589
26.6k
        LocInfo = CCValAssign::AExt;
590
26.6k
  }
591
80.7k
592
80.7k
  if (LocVT == MVT::f16 ||
593
80.7k
      LocVT == MVT::f32) {
594
2
    LocVT = MVT::f64;
595
2
    LocInfo = CCValAssign::FPExt;
596
2
  }
597
80.7k
598
80.7k
  if (LocVT == MVT::i64) {
599
73.1k
    if (ArgFlags.isSplit()) {
600
1
      unsigned Offset1 = State.AllocateStack(8, 16);
601
1
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
602
1
      return false;
603
1
    }
604
80.7k
  }
605
80.7k
606
80.7k
  if (LocVT == MVT::i64 ||
607
80.7k
      
LocVT == MVT::f647.56k
||
608
80.7k
      
LocVT == MVT::v1i641
||
609
80.7k
      
LocVT == MVT::v2i321
||
610
80.7k
      
LocVT == MVT::v4i161
||
611
80.7k
      
LocVT == MVT::v8i81
||
612
80.7k
      
LocVT == MVT::v1f641
||
613
80.7k
      
LocVT == MVT::v2f321
||
614
80.7k
      
LocVT == MVT::v4f161
) {
615
80.7k
    unsigned Offset2 = State.AllocateStack(8, 8);
616
80.7k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
617
80.7k
    return false;
618
80.7k
  }
619
1
620
1
  if (LocVT == MVT::v2i64 ||
621
1
      LocVT == MVT::v4i32 ||
622
1
      
LocVT == MVT::v8i160
||
623
1
      
LocVT == MVT::v16i80
||
624
1
      
LocVT == MVT::v4f320
||
625
1
      
LocVT == MVT::v2f640
||
626
1
      
LocVT == MVT::v8f160
) {
627
1
    unsigned Offset3 = State.AllocateStack(16, 16);
628
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
629
1
    return false;
630
1
  }
631
0
632
0
  return true;  // CC didn't match.
633
0
}
Unexecuted instantiation: AArch64FastISel.cpp:CC_AArch64_DarwinPCS_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
AArch64ISelLowering.cpp:CC_AArch64_DarwinPCS_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
556
80.7k
                                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
557
80.7k
558
80.7k
  if (LocVT == MVT::iPTR) {
559
0
    LocVT = MVT::i64;
560
0
    LocInfo = CCValAssign::BCvt;
561
0
  }
562
80.7k
563
80.7k
  if (LocVT == MVT::v2f32) {
564
0
    LocVT = MVT::v2i32;
565
0
    LocInfo = CCValAssign::BCvt;
566
0
  }
567
80.7k
568
80.7k
  if (LocVT == MVT::v2f64 ||
569
80.7k
      LocVT == MVT::v4f32 ||
570
80.7k
      LocVT == MVT::f128) {
571
0
    LocVT = MVT::v2i64;
572
0
    LocInfo = CCValAssign::BCvt;
573
0
  }
574
80.7k
575
80.7k
  if (ArgFlags.isInConsecutiveRegs()) {
576
17
    if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
577
17
        return false;
578
80.7k
  }
579
80.7k
580
80.7k
  if (LocVT == MVT::i8 ||
581
80.7k
      
LocVT == MVT::i1680.7k
||
582
80.7k
      
LocVT == MVT::i3280.7k
) {
583
26.6k
    LocVT = MVT::i64;
584
26.6k
    if (ArgFlags.isSExt())
585
0
        LocInfo = CCValAssign::SExt;
586
26.6k
    else if (ArgFlags.isZExt())
587
0
        LocInfo = CCValAssign::ZExt;
588
26.6k
    else
589
26.6k
        LocInfo = CCValAssign::AExt;
590
26.6k
  }
591
80.7k
592
80.7k
  if (LocVT == MVT::f16 ||
593
80.7k
      LocVT == MVT::f32) {
594
2
    LocVT = MVT::f64;
595
2
    LocInfo = CCValAssign::FPExt;
596
2
  }
597
80.7k
598
80.7k
  if (LocVT == MVT::i64) {
599
73.1k
    if (ArgFlags.isSplit()) {
600
1
      unsigned Offset1 = State.AllocateStack(8, 16);
601
1
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
602
1
      return false;
603
1
    }
604
80.7k
  }
605
80.7k
606
80.7k
  if (LocVT == MVT::i64 ||
607
80.7k
      
LocVT == MVT::f647.56k
||
608
80.7k
      
LocVT == MVT::v1i641
||
609
80.7k
      
LocVT == MVT::v2i321
||
610
80.7k
      
LocVT == MVT::v4i161
||
611
80.7k
      
LocVT == MVT::v8i81
||
612
80.7k
      
LocVT == MVT::v1f641
||
613
80.7k
      
LocVT == MVT::v2f321
||
614
80.7k
      
LocVT == MVT::v4f161
) {
615
80.7k
    unsigned Offset2 = State.AllocateStack(8, 8);
616
80.7k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
617
80.7k
    return false;
618
80.7k
  }
619
1
620
1
  if (LocVT == MVT::v2i64 ||
621
1
      LocVT == MVT::v4i32 ||
622
1
      
LocVT == MVT::v8i160
||
623
1
      
LocVT == MVT::v16i80
||
624
1
      
LocVT == MVT::v4f320
||
625
1
      
LocVT == MVT::v2f640
||
626
1
      
LocVT == MVT::v8f160
) {
627
1
    unsigned Offset3 = State.AllocateStack(16, 16);
628
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
629
1
    return false;
630
1
  }
631
0
632
0
  return true;  // CC didn't match.
633
0
}
634
635
636
static bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
637
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
638
8
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
639
8
640
8
  if (LocVT == MVT::iPTR) {
641
0
    LocVT = MVT::i64;
642
0
    LocInfo = CCValAssign::BCvt;
643
0
  }
644
8
645
8
  if (LocVT == MVT::v1i64 ||
646
8
      LocVT == MVT::v2i32 ||
647
8
      LocVT == MVT::v4i16 ||
648
8
      LocVT == MVT::v8i8 ||
649
8
      LocVT == MVT::v2f32) {
650
0
    LocVT = MVT::f64;
651
0
    LocInfo = CCValAssign::BCvt;
652
0
  }
653
8
654
8
  if (LocVT == MVT::v2i64 ||
655
8
      LocVT == MVT::v4i32 ||
656
8
      LocVT == MVT::v8i16 ||
657
8
      LocVT == MVT::v16i8 ||
658
8
      LocVT == MVT::v4f32 ||
659
8
      LocVT == MVT::f128) {
660
0
    LocVT = MVT::v2f64;
661
0
    LocInfo = CCValAssign::BCvt;
662
0
  }
663
8
664
8
  if (LocVT == MVT::v2f64) {
665
0
    static const MCPhysReg RegList1[] = {
666
0
      AArch64::Q4, AArch64::Q5
667
0
    };
668
0
    if (unsigned Reg = State.AllocateReg(RegList1)) {
669
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
670
0
      return false;
671
0
    }
672
8
  }
673
8
674
8
  if (LocVT == MVT::f32) {
675
2
    static const MCPhysReg RegList2[] = {
676
2
      AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11
677
2
    };
678
2
    if (unsigned Reg = State.AllocateReg(RegList2)) {
679
2
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
680
2
      return false;
681
2
    }
682
6
  }
683
6
684
6
  if (LocVT == MVT::f64) {
685
1
    static const MCPhysReg RegList3[] = {
686
1
      AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15
687
1
    };
688
1
    if (unsigned Reg = State.AllocateReg(RegList3)) {
689
1
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
690
1
      return false;
691
1
    }
692
5
  }
693
5
694
5
  if (LocVT == MVT::i8 ||
695
5
      LocVT == MVT::i16 ||
696
5
      LocVT == MVT::i32) {
697
0
    LocVT = MVT::i64;
698
0
    if (ArgFlags.isSExt())
699
0
        LocInfo = CCValAssign::SExt;
700
0
    else if (ArgFlags.isZExt())
701
0
        LocInfo = CCValAssign::ZExt;
702
0
    else
703
0
        LocInfo = CCValAssign::AExt;
704
0
  }
705
5
706
5
  if (LocVT == MVT::i64) {
707
5
    static const MCPhysReg RegList4[] = {
708
5
      AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
709
5
    };
710
5
    if (unsigned Reg = State.AllocateReg(RegList4)) {
711
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
712
5
      return false;
713
5
    }
714
0
  }
715
0
716
0
  return true;  // CC didn't match.
717
0
}
Unexecuted instantiation: AArch64FastISel.cpp:CC_AArch64_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
AArch64ISelLowering.cpp:CC_AArch64_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
638
8
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
639
8
640
8
  if (LocVT == MVT::iPTR) {
641
0
    LocVT = MVT::i64;
642
0
    LocInfo = CCValAssign::BCvt;
643
0
  }
644
8
645
8
  if (LocVT == MVT::v1i64 ||
646
8
      LocVT == MVT::v2i32 ||
647
8
      LocVT == MVT::v4i16 ||
648
8
      LocVT == MVT::v8i8 ||
649
8
      LocVT == MVT::v2f32) {
650
0
    LocVT = MVT::f64;
651
0
    LocInfo = CCValAssign::BCvt;
652
0
  }
653
8
654
8
  if (LocVT == MVT::v2i64 ||
655
8
      LocVT == MVT::v4i32 ||
656
8
      LocVT == MVT::v8i16 ||
657
8
      LocVT == MVT::v16i8 ||
658
8
      LocVT == MVT::v4f32 ||
659
8
      LocVT == MVT::f128) {
660
0
    LocVT = MVT::v2f64;
661
0
    LocInfo = CCValAssign::BCvt;
662
0
  }
663
8
664
8
  if (LocVT == MVT::v2f64) {
665
0
    static const MCPhysReg RegList1[] = {
666
0
      AArch64::Q4, AArch64::Q5
667
0
    };
668
0
    if (unsigned Reg = State.AllocateReg(RegList1)) {
669
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
670
0
      return false;
671
0
    }
672
8
  }
673
8
674
8
  if (LocVT == MVT::f32) {
675
2
    static const MCPhysReg RegList2[] = {
676
2
      AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11
677
2
    };
678
2
    if (unsigned Reg = State.AllocateReg(RegList2)) {
679
2
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
680
2
      return false;
681
2
    }
682
6
  }
683
6
684
6
  if (LocVT == MVT::f64) {
685
1
    static const MCPhysReg RegList3[] = {
686
1
      AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15
687
1
    };
688
1
    if (unsigned Reg = State.AllocateReg(RegList3)) {
689
1
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
690
1
      return false;
691
1
    }
692
5
  }
693
5
694
5
  if (LocVT == MVT::i8 ||
695
5
      LocVT == MVT::i16 ||
696
5
      LocVT == MVT::i32) {
697
0
    LocVT = MVT::i64;
698
0
    if (ArgFlags.isSExt())
699
0
        LocInfo = CCValAssign::SExt;
700
0
    else if (ArgFlags.isZExt())
701
0
        LocInfo = CCValAssign::ZExt;
702
0
    else
703
0
        LocInfo = CCValAssign::AExt;
704
0
  }
705
5
706
5
  if (LocVT == MVT::i64) {
707
5
    static const MCPhysReg RegList4[] = {
708
5
      AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
709
5
    };
710
5
    if (unsigned Reg = State.AllocateReg(RegList4)) {
711
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
712
5
      return false;
713
5
    }
714
0
  }
715
0
716
0
  return true;  // CC didn't match.
717
0
}
718
719
720
static bool CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
721
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
722
129
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
723
129
724
129
  if (LocVT == MVT::i1 ||
725
129
      LocVT == MVT::i8 ||
726
129
      LocVT == MVT::i16) {
727
6
    LocVT = MVT::i32;
728
6
    if (ArgFlags.isSExt())
729
0
        LocInfo = CCValAssign::SExt;
730
6
    else if (ArgFlags.isZExt())
731
6
        LocInfo = CCValAssign::ZExt;
732
0
    else
733
0
        LocInfo = CCValAssign::AExt;
734
6
  }
735
129
736
129
  if (LocVT == MVT::i32) {
737
27
    if (unsigned Reg = State.AllocateReg(AArch64::W0, AArch64::X0)) {
738
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
739
3
      return false;
740
3
    }
741
126
  }
742
126
743
126
  if (LocVT == MVT::i64) {
744
102
    if (unsigned Reg = State.AllocateReg(AArch64::X0, AArch64::W0)) {
745
17
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
746
17
      return false;
747
17
    }
748
109
  }
749
109
750
109
  if (LocVT == MVT::i32 ||
751
109
      
LocVT == MVT::f3285
) {
752
24
    unsigned Offset1 = State.AllocateStack(4, 4);
753
24
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
754
24
    return false;
755
24
  }
756
85
757
85
  if (LocVT == MVT::i64 ||
758
85
      
LocVT == MVT::f640
) {
759
85
    unsigned Offset2 = State.AllocateStack(8, 8);
760
85
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
761
85
    return false;
762
85
  }
763
0
764
0
  return true;  // CC didn't match.
765
0
}
AArch64FastISel.cpp:CC_AArch64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
722
23
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
723
23
724
23
  if (LocVT == MVT::i1 ||
725
23
      LocVT == MVT::i8 ||
726
23
      LocVT == MVT::i16) {
727
0
    LocVT = MVT::i32;
728
0
    if (ArgFlags.isSExt())
729
0
        LocInfo = CCValAssign::SExt;
730
0
    else if (ArgFlags.isZExt())
731
0
        LocInfo = CCValAssign::ZExt;
732
0
    else
733
0
        LocInfo = CCValAssign::AExt;
734
0
  }
735
23
736
23
  if (LocVT == MVT::i32) {
737
7
    if (unsigned Reg = State.AllocateReg(AArch64::W0, AArch64::X0)) {
738
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
739
0
      return false;
740
0
    }
741
23
  }
742
23
743
23
  if (LocVT == MVT::i64) {
744
16
    if (unsigned Reg = State.AllocateReg(AArch64::X0, AArch64::W0)) {
745
7
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
746
7
      return false;
747
7
    }
748
16
  }
749
16
750
16
  if (LocVT == MVT::i32 ||
751
16
      
LocVT == MVT::f329
) {
752
7
    unsigned Offset1 = State.AllocateStack(4, 4);
753
7
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
754
7
    return false;
755
7
  }
756
9
757
9
  if (LocVT == MVT::i64 ||
758
9
      
LocVT == MVT::f640
) {
759
9
    unsigned Offset2 = State.AllocateStack(8, 8);
760
9
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
761
9
    return false;
762
9
  }
763
0
764
0
  return true;  // CC didn't match.
765
0
}
AArch64ISelLowering.cpp:CC_AArch64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
722
106
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
723
106
724
106
  if (LocVT == MVT::i1 ||
725
106
      LocVT == MVT::i8 ||
726
106
      LocVT == MVT::i16) {
727
6
    LocVT = MVT::i32;
728
6
    if (ArgFlags.isSExt())
729
0
        LocInfo = CCValAssign::SExt;
730
6
    else if (ArgFlags.isZExt())
731
6
        LocInfo = CCValAssign::ZExt;
732
0
    else
733
0
        LocInfo = CCValAssign::AExt;
734
6
  }
735
106
736
106
  if (LocVT == MVT::i32) {
737
20
    if (unsigned Reg = State.AllocateReg(AArch64::W0, AArch64::X0)) {
738
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
739
3
      return false;
740
3
    }
741
103
  }
742
103
743
103
  if (LocVT == MVT::i64) {
744
86
    if (unsigned Reg = State.AllocateReg(AArch64::X0, AArch64::W0)) {
745
10
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
746
10
      return false;
747
10
    }
748
93
  }
749
93
750
93
  if (LocVT == MVT::i32 ||
751
93
      
LocVT == MVT::f3276
) {
752
17
    unsigned Offset1 = State.AllocateStack(4, 4);
753
17
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
754
17
    return false;
755
17
  }
756
76
757
76
  if (LocVT == MVT::i64 ||
758
76
      
LocVT == MVT::f640
) {
759
76
    unsigned Offset2 = State.AllocateStack(8, 8);
760
76
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
761
76
    return false;
762
76
  }
763
0
764
0
  return true;  // CC didn't match.
765
0
}
766
767
768
static bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
769
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
770
19
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
771
19
772
19
  if (LocVT == MVT::f16 ||
773
19
      LocVT == MVT::f32) {
774
0
    LocVT = MVT::f64;
775
0
    LocInfo = CCValAssign::FPExt;
776
0
  }
777
19
778
19
  if (LocVT == MVT::f64) {
779
10
    LocVT = MVT::i64;
780
10
    LocInfo = CCValAssign::BCvt;
781
10
  }
782
19
783
19
  if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
784
19
    return false;
785
0
786
0
  return true;  // CC didn't match.
787
0
}
Unexecuted instantiation: AArch64FastISel.cpp:CC_AArch64_Win64_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
AArch64ISelLowering.cpp:CC_AArch64_Win64_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
770
19
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
771
19
772
19
  if (LocVT == MVT::f16 ||
773
19
      LocVT == MVT::f32) {
774
0
    LocVT = MVT::f64;
775
0
    LocInfo = CCValAssign::FPExt;
776
0
  }
777
19
778
19
  if (LocVT == MVT::f64) {
779
10
    LocVT = MVT::i64;
780
10
    LocInfo = CCValAssign::BCvt;
781
10
  }
782
19
783
19
  if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
784
19
    return false;
785
0
786
0
  return true;  // CC didn't match.
787
0
}
788
789
790
static bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
791
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
792
1.85M
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
793
1.85M
794
1.85M
  if (LocVT == MVT::iPTR) {
795
0
    LocVT = MVT::i64;
796
0
    LocInfo = CCValAssign::BCvt;
797
0
  }
798
1.85M
799
1.85M
  if (LocVT == MVT::v2f32) {
800
735
    LocVT = MVT::v2i32;
801
735
    LocInfo = CCValAssign::BCvt;
802
735
  }
803
1.85M
804
1.85M
  if (LocVT == MVT::v2f64 ||
805
1.85M
      
LocVT == MVT::v4f321.85M
) {
806
1.63k
    LocVT = MVT::v2i64;
807
1.63k
    LocInfo = CCValAssign::BCvt;
808
1.63k
  }
809
1.85M
810
1.85M
  if (ArgFlags.isSwiftError()) {
811
50
    if (LocVT == MVT::i64) {
812
50
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
813
50
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
814
50
        return false;
815
50
      }
816
1.85M
    }
817
50
  }
818
1.85M
819
1.85M
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
820
1.93k
    if (LocVT == MVT::v2i32 ||
821
1.93k
        
LocVT == MVT::v2f321.81k
||
822
1.93k
        
LocVT == MVT::v4i161.81k
||
823
1.93k
        
LocVT == MVT::v4f161.75k
||
824
1.93k
        
LocVT == MVT::v8i81.75k
) {
825
240
      LocVT = MVT::f64;
826
240
      LocInfo = CCValAssign::BCvt;
827
240
    }
828
1.93k
  }
829
1.85M
830
1.85M
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
831
1.93k
    if (LocVT == MVT::v2i64 ||
832
1.93k
        
LocVT == MVT::v2f641.75k
||
833
1.93k
        
LocVT == MVT::v4i321.75k
||
834
1.93k
        
LocVT == MVT::v4f321.69k
||
835
1.93k
        
LocVT == MVT::v8i161.69k
||
836
1.93k
        
LocVT == MVT::v8f161.63k
||
837
1.93k
        
LocVT == MVT::v16i81.63k
) {
838
360
      LocVT = MVT::f128;
839
360
      LocInfo = CCValAssign::BCvt;
840
360
    }
841
1.93k
  }
842
1.85M
843
1.85M
  if (LocVT == MVT::i1 ||
844
1.85M
      
LocVT == MVT::i81.82M
||
845
1.85M
      
LocVT == MVT::i161.82M
) {
846
27.0k
    LocVT = MVT::i32;
847
27.0k
    if (ArgFlags.isSExt())
848
1.23k
        LocInfo = CCValAssign::SExt;
849
25.8k
    else if (ArgFlags.isZExt())
850
25.8k
        LocInfo = CCValAssign::ZExt;
851
4
    else
852
4
        LocInfo = CCValAssign::AExt;
853
27.0k
  }
854
1.85M
855
1.85M
  if (LocVT == MVT::i32) {
856
749k
    static const MCPhysReg RegList1[] = {
857
749k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
858
749k
    };
859
749k
    static const MCPhysReg RegList2[] = {
860
749k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
861
749k
    };
862
749k
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
863
749k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
864
749k
      return false;
865
749k
    }
866
1.10M
  }
867
1.10M
868
1.10M
  if (LocVT == MVT::i64) {
869
1.06M
    static const MCPhysReg RegList3[] = {
870
1.06M
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
871
1.06M
    };
872
1.06M
    static const MCPhysReg RegList4[] = {
873
1.06M
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
874
1.06M
    };
875
1.06M
    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
876
1.06M
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
877
1.06M
      return false;
878
1.06M
    }
879
36.5k
  }
880
36.5k
881
36.5k
  if (LocVT == MVT::f16) {
882
378
    static const MCPhysReg RegList5[] = {
883
378
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
884
378
    };
885
378
    static const MCPhysReg RegList6[] = {
886
378
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
887
378
    };
888
378
    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
889
378
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
890
378
      return false;
891
378
    }
892
36.1k
  }
893
36.1k
894
36.1k
  if (LocVT == MVT::f32) {
895
10.0k
    static const MCPhysReg RegList7[] = {
896
10.0k
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
897
10.0k
    };
898
10.0k
    static const MCPhysReg RegList8[] = {
899
10.0k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
900
10.0k
    };
901
10.0k
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
902
10.0k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
903
10.0k
      return false;
904
10.0k
    }
905
26.0k
  }
906
26.0k
907
26.0k
  if (LocVT == MVT::f64) {
908
12.2k
    static const MCPhysReg RegList9[] = {
909
12.2k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
910
12.2k
    };
911
12.2k
    static const MCPhysReg RegList10[] = {
912
12.2k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
913
12.2k
    };
914
12.2k
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
915
12.2k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
916
12.2k
      return false;
917
12.2k
    }
918
13.8k
  }
919
13.8k
920
13.8k
  if (LocVT == MVT::v1i64 ||
921
13.8k
      
LocVT == MVT::v2i3213.4k
||
922
13.8k
      
LocVT == MVT::v4i1611.5k
||
923
13.8k
      
LocVT == MVT::v8i810.3k
||
924
13.8k
      
LocVT == MVT::v1f649.28k
||
925
13.8k
      
LocVT == MVT::v2f329.00k
||
926
13.8k
      
LocVT == MVT::v4f169.00k
) {
927
5.14k
    static const MCPhysReg RegList11[] = {
928
5.14k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
929
5.14k
    };
930
5.14k
    static const MCPhysReg RegList12[] = {
931
5.14k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
932
5.14k
    };
933
5.14k
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
934
5.14k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
935
5.14k
      return false;
936
5.14k
    }
937
8.73k
  }
938
8.73k
939
8.73k
  if (LocVT == MVT::f128 ||
940
8.73k
      
LocVT == MVT::v2i648.00k
||
941
8.73k
      
LocVT == MVT::v4i325.02k
||
942
8.73k
      
LocVT == MVT::v8i162.71k
||
943
8.73k
      
LocVT == MVT::v16i81.29k
||
944
8.73k
      
LocVT == MVT::v4f32280
||
945
8.73k
      
LocVT == MVT::v2f64280
||
946
8.73k
      
LocVT == MVT::v8f16280
) {
947
8.71k
    static const MCPhysReg RegList13[] = {
948
8.71k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
949
8.71k
    };
950
8.71k
    if (unsigned Reg = State.AllocateReg(RegList13)) {
951
8.71k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
952
8.71k
      return false;
953
8.71k
    }
954
12
  }
955
12
956
12
  return true;  // CC didn't match.
957
12
}
AArch64FastISel.cpp:RetCC_AArch64_AAPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
792
966
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
793
966
794
966
  if (LocVT == MVT::iPTR) {
795
0
    LocVT = MVT::i64;
796
0
    LocInfo = CCValAssign::BCvt;
797
0
  }
798
966
799
966
  if (LocVT == MVT::v2f32) {
800
9
    LocVT = MVT::v2i32;
801
9
    LocInfo = CCValAssign::BCvt;
802
9
  }
803
966
804
966
  if (LocVT == MVT::v2f64 ||
805
966
      
LocVT == MVT::v4f32956
) {
806
22
    LocVT = MVT::v2i64;
807
22
    LocInfo = CCValAssign::BCvt;
808
22
  }
809
966
810
966
  if (ArgFlags.isSwiftError()) {
811
0
    if (LocVT == MVT::i64) {
812
0
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
813
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
814
0
        return false;
815
0
      }
816
966
    }
817
0
  }
818
966
819
966
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
820
106
    if (LocVT == MVT::v2i32 ||
821
106
        
LocVT == MVT::v2f3294
||
822
106
        
LocVT == MVT::v4i1694
||
823
106
        
LocVT == MVT::v4f1688
||
824
106
        
LocVT == MVT::v8i888
) {
825
24
      LocVT = MVT::f64;
826
24
      LocInfo = CCValAssign::BCvt;
827
24
    }
828
106
  }
829
966
830
966
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
831
106
    if (LocVT == MVT::v2i64 ||
832
106
        
LocVT == MVT::v2f6488
||
833
106
        
LocVT == MVT::v4i3288
||
834
106
        
LocVT == MVT::v4f3282
||
835
106
        
LocVT == MVT::v8i1682
||
836
106
        
LocVT == MVT::v8f1676
||
837
106
        
LocVT == MVT::v16i876
) {
838
36
      LocVT = MVT::f128;
839
36
      LocInfo = CCValAssign::BCvt;
840
36
    }
841
106
  }
842
966
843
966
  if (LocVT == MVT::i1 ||
844
966
      LocVT == MVT::i8 ||
845
966
      LocVT == MVT::i16) {
846
0
    LocVT = MVT::i32;
847
0
    if (ArgFlags.isSExt())
848
0
        LocInfo = CCValAssign::SExt;
849
0
    else if (ArgFlags.isZExt())
850
0
        LocInfo = CCValAssign::ZExt;
851
0
    else
852
0
        LocInfo = CCValAssign::AExt;
853
0
  }
854
966
855
966
  if (LocVT == MVT::i32) {
856
538
    static const MCPhysReg RegList1[] = {
857
538
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
858
538
    };
859
538
    static const MCPhysReg RegList2[] = {
860
538
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
861
538
    };
862
538
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
863
538
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
864
538
      return false;
865
538
    }
866
428
  }
867
428
868
428
  if (LocVT == MVT::i64) {
869
204
    static const MCPhysReg RegList3[] = {
870
204
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
871
204
    };
872
204
    static const MCPhysReg RegList4[] = {
873
204
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
874
204
    };
875
204
    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
876
204
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
877
204
      return false;
878
204
    }
879
224
  }
880
224
881
224
  if (LocVT == MVT::f16) {
882
14
    static const MCPhysReg RegList5[] = {
883
14
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
884
14
    };
885
14
    static const MCPhysReg RegList6[] = {
886
14
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
887
14
    };
888
14
    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
889
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
890
14
      return false;
891
14
    }
892
210
  }
893
210
894
210
  if (LocVT == MVT::f32) {
895
64
    static const MCPhysReg RegList7[] = {
896
64
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
897
64
    };
898
64
    static const MCPhysReg RegList8[] = {
899
64
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
900
64
    };
901
64
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
902
64
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
903
64
      return false;
904
64
    }
905
146
  }
906
146
907
146
  if (LocVT == MVT::f64) {
908
66
    static const MCPhysReg RegList9[] = {
909
66
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
910
66
    };
911
66
    static const MCPhysReg RegList10[] = {
912
66
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
913
66
    };
914
66
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
915
66
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
916
66
      return false;
917
66
    }
918
80
  }
919
80
920
80
  if (LocVT == MVT::v1i64 ||
921
80
      
LocVT == MVT::v2i3274
||
922
80
      
LocVT == MVT::v4i1667
||
923
80
      
LocVT == MVT::v8i866
||
924
80
      
LocVT == MVT::v1f6464
||
925
80
      
LocVT == MVT::v2f3264
||
926
80
      
LocVT == MVT::v4f1664
) {
927
16
    static const MCPhysReg RegList11[] = {
928
16
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
929
16
    };
930
16
    static const MCPhysReg RegList12[] = {
931
16
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
932
16
    };
933
16
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
934
16
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
935
16
      return false;
936
16
    }
937
64
  }
938
64
939
64
  if (LocVT == MVT::f128 ||
940
64
      
LocVT == MVT::v2i6420
||
941
64
      
LocVT == MVT::v4i328
||
942
64
      
LocVT == MVT::v8i165
||
943
64
      
LocVT == MVT::v16i84
||
944
64
      
LocVT == MVT::v4f320
||
945
64
      
LocVT == MVT::v2f640
||
946
64
      
LocVT == MVT::v8f160
) {
947
64
    static const MCPhysReg RegList13[] = {
948
64
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
949
64
    };
950
64
    if (unsigned Reg = State.AllocateReg(RegList13)) {
951
64
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
952
64
      return false;
953
64
    }
954
0
  }
955
0
956
0
  return true;  // CC didn't match.
957
0
}
AArch64ISelLowering.cpp:RetCC_AArch64_AAPCS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
792
1.85M
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
793
1.85M
794
1.85M
  if (LocVT == MVT::iPTR) {
795
0
    LocVT = MVT::i64;
796
0
    LocInfo = CCValAssign::BCvt;
797
0
  }
798
1.85M
799
1.85M
  if (LocVT == MVT::v2f32) {
800
726
    LocVT = MVT::v2i32;
801
726
    LocInfo = CCValAssign::BCvt;
802
726
  }
803
1.85M
804
1.85M
  if (LocVT == MVT::v2f64 ||
805
1.85M
      
LocVT == MVT::v4f321.85M
) {
806
1.61k
    LocVT = MVT::v2i64;
807
1.61k
    LocInfo = CCValAssign::BCvt;
808
1.61k
  }
809
1.85M
810
1.85M
  if (ArgFlags.isSwiftError()) {
811
50
    if (LocVT == MVT::i64) {
812
50
      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
813
50
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
814
50
        return false;
815
50
      }
816
1.85M
    }
817
50
  }
818
1.85M
819
1.85M
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
820
1.82k
    if (LocVT == MVT::v2i32 ||
821
1.82k
        
LocVT == MVT::v2f321.71k
||
822
1.82k
        
LocVT == MVT::v4i161.71k
||
823
1.82k
        
LocVT == MVT::v4f161.66k
||
824
1.82k
        
LocVT == MVT::v8i81.66k
) {
825
216
      LocVT = MVT::f64;
826
216
      LocInfo = CCValAssign::BCvt;
827
216
    }
828
1.82k
  }
829
1.85M
830
1.85M
  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
831
1.82k
    if (LocVT == MVT::v2i64 ||
832
1.82k
        
LocVT == MVT::v2f641.66k
||
833
1.82k
        
LocVT == MVT::v4i321.66k
||
834
1.82k
        
LocVT == MVT::v4f321.61k
||
835
1.82k
        
LocVT == MVT::v8i161.61k
||
836
1.82k
        
LocVT == MVT::v8f161.55k
||
837
1.82k
        
LocVT == MVT::v16i81.55k
) {
838
324
      LocVT = MVT::f128;
839
324
      LocInfo = CCValAssign::BCvt;
840
324
    }
841
1.82k
  }
842
1.85M
843
1.85M
  if (LocVT == MVT::i1 ||
844
1.85M
      
LocVT == MVT::i81.82M
||
845
1.85M
      
LocVT == MVT::i161.82M
) {
846
27.0k
    LocVT = MVT::i32;
847
27.0k
    if (ArgFlags.isSExt())
848
1.23k
        LocInfo = CCValAssign::SExt;
849
25.8k
    else if (ArgFlags.isZExt())
850
25.8k
        LocInfo = CCValAssign::ZExt;
851
4
    else
852
4
        LocInfo = CCValAssign::AExt;
853
27.0k
  }
854
1.85M
855
1.85M
  if (LocVT == MVT::i32) {
856
748k
    static const MCPhysReg RegList1[] = {
857
748k
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
858
748k
    };
859
748k
    static const MCPhysReg RegList2[] = {
860
748k
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
861
748k
    };
862
748k
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
863
748k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
864
748k
      return false;
865
748k
    }
866
1.10M
  }
867
1.10M
868
1.10M
  if (LocVT == MVT::i64) {
869
1.06M
    static const MCPhysReg RegList3[] = {
870
1.06M
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
871
1.06M
    };
872
1.06M
    static const MCPhysReg RegList4[] = {
873
1.06M
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
874
1.06M
    };
875
1.06M
    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
876
1.06M
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
877
1.06M
      return false;
878
1.06M
    }
879
36.3k
  }
880
36.3k
881
36.3k
  if (LocVT == MVT::f16) {
882
364
    static const MCPhysReg RegList5[] = {
883
364
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
884
364
    };
885
364
    static const MCPhysReg RegList6[] = {
886
364
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
887
364
    };
888
364
    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
889
364
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
890
364
      return false;
891
364
    }
892
35.9k
  }
893
35.9k
894
35.9k
  if (LocVT == MVT::f32) {
895
10.0k
    static const MCPhysReg RegList7[] = {
896
10.0k
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
897
10.0k
    };
898
10.0k
    static const MCPhysReg RegList8[] = {
899
10.0k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
900
10.0k
    };
901
10.0k
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
902
10.0k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
903
10.0k
      return false;
904
10.0k
    }
905
25.9k
  }
906
25.9k
907
25.9k
  if (LocVT == MVT::f64) {
908
12.1k
    static const MCPhysReg RegList9[] = {
909
12.1k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
910
12.1k
    };
911
12.1k
    static const MCPhysReg RegList10[] = {
912
12.1k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
913
12.1k
    };
914
12.1k
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
915
12.1k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
916
12.1k
      return false;
917
12.1k
    }
918
13.7k
  }
919
13.7k
920
13.7k
  if (LocVT == MVT::v1i64 ||
921
13.7k
      
LocVT == MVT::v2i3213.3k
||
922
13.7k
      
LocVT == MVT::v4i1611.5k
||
923
13.7k
      
LocVT == MVT::v8i810.2k
||
924
13.7k
      
LocVT == MVT::v1f649.22k
||
925
13.7k
      
LocVT == MVT::v2f328.93k
||
926
13.7k
      
LocVT == MVT::v4f168.93k
) {
927
5.13k
    static const MCPhysReg RegList11[] = {
928
5.13k
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
929
5.13k
    };
930
5.13k
    static const MCPhysReg RegList12[] = {
931
5.13k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
932
5.13k
    };
933
5.13k
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
934
5.13k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
935
5.13k
      return false;
936
5.13k
    }
937
8.66k
  }
938
8.66k
939
8.66k
  if (LocVT == MVT::f128 ||
940
8.66k
      
LocVT == MVT::v2i647.98k
||
941
8.66k
      
LocVT == MVT::v4i325.01k
||
942
8.66k
      
LocVT == MVT::v8i162.70k
||
943
8.66k
      
LocVT == MVT::v16i81.28k
||
944
8.66k
      
LocVT == MVT::v4f32280
||
945
8.66k
      
LocVT == MVT::v2f64280
||
946
8.66k
      
LocVT == MVT::v8f16280
) {
947
8.65k
    static const MCPhysReg RegList13[] = {
948
8.65k
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
949
8.65k
    };
950
8.65k
    if (unsigned Reg = State.AllocateReg(RegList13)) {
951
8.65k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
952
8.65k
      return false;
953
8.65k
    }
954
12
  }
955
12
956
12
  return true;  // CC didn't match.
957
12
}
958
959
960
static bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
961
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
962
21
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
963
21
964
21
  if (LocVT == MVT::i32) {
965
6
    static const MCPhysReg RegList1[] = {
966
6
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
967
6
    };
968
6
    static const MCPhysReg RegList2[] = {
969
6
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
970
6
    };
971
6
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
972
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
973
6
      return false;
974
6
    }
975
15
  }
976
15
977
15
  if (LocVT == MVT::i64) {
978
15
    static const MCPhysReg RegList3[] = {
979
15
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
980
15
    };
981
15
    static const MCPhysReg RegList4[] = {
982
15
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
983
15
    };
984
15
    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
985
15
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
986
15
      return false;
987
15
    }
988
0
  }
989
0
990
0
  if (LocVT == MVT::f32) {
991
0
    static const MCPhysReg RegList5[] = {
992
0
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
993
0
    };
994
0
    static const MCPhysReg RegList6[] = {
995
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
996
0
    };
997
0
    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
998
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
999
0
      return false;
1000
0
    }
1001
0
  }
1002
0
1003
0
  if (LocVT == MVT::f64) {
1004
0
    static const MCPhysReg RegList7[] = {
1005
0
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1006
0
    };
1007
0
    static const MCPhysReg RegList8[] = {
1008
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1009
0
    };
1010
0
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
1011
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1012
0
      return false;
1013
0
    }
1014
0
  }
1015
0
1016
0
  return true;  // CC didn't match.
1017
0
}
AArch64FastISel.cpp:RetCC_AArch64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
962
1
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
963
1
964
1
  if (LocVT == MVT::i32) {
965
1
    static const MCPhysReg RegList1[] = {
966
1
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
967
1
    };
968
1
    static const MCPhysReg RegList2[] = {
969
1
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
970
1
    };
971
1
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
972
1
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
973
1
      return false;
974
1
    }
975
0
  }
976
0
977
0
  if (LocVT == MVT::i64) {
978
0
    static const MCPhysReg RegList3[] = {
979
0
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
980
0
    };
981
0
    static const MCPhysReg RegList4[] = {
982
0
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
983
0
    };
984
0
    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
985
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
986
0
      return false;
987
0
    }
988
0
  }
989
0
990
0
  if (LocVT == MVT::f32) {
991
0
    static const MCPhysReg RegList5[] = {
992
0
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
993
0
    };
994
0
    static const MCPhysReg RegList6[] = {
995
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
996
0
    };
997
0
    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
998
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
999
0
      return false;
1000
0
    }
1001
0
  }
1002
0
1003
0
  if (LocVT == MVT::f64) {
1004
0
    static const MCPhysReg RegList7[] = {
1005
0
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1006
0
    };
1007
0
    static const MCPhysReg RegList8[] = {
1008
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1009
0
    };
1010
0
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
1011
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1012
0
      return false;
1013
0
    }
1014
0
  }
1015
0
1016
0
  return true;  // CC didn't match.
1017
0
}
AArch64ISelLowering.cpp:RetCC_AArch64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
962
20
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
963
20
964
20
  if (LocVT == MVT::i32) {
965
5
    static const MCPhysReg RegList1[] = {
966
5
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
967
5
    };
968
5
    static const MCPhysReg RegList2[] = {
969
5
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
970
5
    };
971
5
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
972
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
973
5
      return false;
974
5
    }
975
15
  }
976
15
977
15
  if (LocVT == MVT::i64) {
978
15
    static const MCPhysReg RegList3[] = {
979
15
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
980
15
    };
981
15
    static const MCPhysReg RegList4[] = {
982
15
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
983
15
    };
984
15
    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
985
15
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
986
15
      return false;
987
15
    }
988
0
  }
989
0
990
0
  if (LocVT == MVT::f32) {
991
0
    static const MCPhysReg RegList5[] = {
992
0
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
993
0
    };
994
0
    static const MCPhysReg RegList6[] = {
995
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
996
0
    };
997
0
    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
998
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
999
0
      return false;
1000
0
    }
1001
0
  }
1002
0
1003
0
  if (LocVT == MVT::f64) {
1004
0
    static const MCPhysReg RegList7[] = {
1005
0
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1006
0
    };
1007
0
    static const MCPhysReg RegList8[] = {
1008
0
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1009
0
    };
1010
0
    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
1011
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1012
0
      return false;
1013
0
    }
1014
0
  }
1015
0
1016
0
  return true;  // CC didn't match.
1017
0
}