Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AArch64/AArch64GenGlobalISel.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the AArch64 target                         *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 15;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
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14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static AArch64InstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(1),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
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33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_HasFPARMv8Bit = 3,
37
  Feature_HasNEONBit = 4,
38
  Feature_HasCryptoBit = 6,
39
  Feature_HasDotProdBit = 0,
40
  Feature_HasCRCBit = 1,
41
  Feature_HasLSEBit = 7,
42
  Feature_HasRDMBit = 5,
43
  Feature_HasPerfMonBit = 8,
44
  Feature_HasFullFP16Bit = 2,
45
  Feature_HasFuseAESBit = 13,
46
  Feature_IsLEBit = 9,
47
  Feature_IsBEBit = 14,
48
  Feature_UseAlternateSExtLoadCVTF32Bit = 12,
49
  Feature_NotForCodeSizeBit = 11,
50
  Feature_UseSTRQroBit = 10,
51
};
52
53
PredicateBitset AArch64InstructionSelector::
54
8.43k
computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const {
55
8.43k
  PredicateBitset Features;
56
8.43k
  if (Subtarget->hasFPARMv8())
57
8.42k
    Features[Feature_HasFPARMv8Bit] = 1;
58
8.43k
  if (Subtarget->hasNEON())
59
8.41k
    Features[Feature_HasNEONBit] = 1;
60
8.43k
  if (Subtarget->hasCrypto())
61
7.24k
    Features[Feature_HasCryptoBit] = 1;
62
8.43k
  if (Subtarget->hasDotProd())
63
5
    Features[Feature_HasDotProdBit] = 1;
64
8.43k
  if (Subtarget->hasCRC())
65
165
    Features[Feature_HasCRCBit] = 1;
66
8.43k
  if (Subtarget->hasLSE())
67
31
    Features[Feature_HasLSEBit] = 1;
68
8.43k
  if (Subtarget->hasRDM())
69
36
    Features[Feature_HasRDMBit] = 1;
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8.43k
  if (Subtarget->hasPerfMon())
71
8.43k
    Features[Feature_HasPerfMonBit] = 1;
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8.43k
  if (Subtarget->hasFullFP16())
73
19
    Features[Feature_HasFullFP16Bit] = 1;
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8.43k
  if (Subtarget->hasFuseAES())
75
8.39k
    Features[Feature_HasFuseAESBit] = 1;
76
8.43k
  if (Subtarget->isLittleEndian())
77
8.41k
    Features[Feature_IsLEBit] = 1;
78
8.43k
  if (!Subtarget->isLittleEndian())
79
28
    Features[Feature_IsBEBit] = 1;
80
8.43k
  if (Subtarget->useAlternateSExtLoadCVTF32Pattern())
81
7.08k
    Features[Feature_UseAlternateSExtLoadCVTF32Bit] = 1;
82
8.43k
  return Features;
83
8.43k
}
84
85
PredicateBitset AArch64InstructionSelector::
86
4.44M
computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const {
87
4.44M
  PredicateBitset Features;
88
4.44M
  if (!MF->getFunction().optForSize())
89
4.44M
    Features[Feature_NotForCodeSizeBit] = 1;
90
4.44M
  if (!Subtarget->isSTRQroSlow() || 
MF->getFunction().optForSize()0
)
91
4.44M
    Features[Feature_UseSTRQroBit] = 1;
92
4.44M
  return Features;
93
4.44M
}
94
95
// LLT Objects.
96
enum {
97
  GILLT_s16,
98
  GILLT_s32,
99
  GILLT_s64,
100
  GILLT_s128,
101
  GILLT_v2s32,
102
  GILLT_v2s64,
103
  GILLT_v4s16,
104
  GILLT_v4s32,
105
  GILLT_v8s8,
106
  GILLT_v8s16,
107
  GILLT_v16s8,
108
};
109
const static size_t NumTypeObjects = 11;
110
const static LLT TypeObjects[] = {
111
  LLT::scalar(16),
112
  LLT::scalar(32),
113
  LLT::scalar(64),
114
  LLT::scalar(128),
115
  LLT::vector(2, 32),
116
  LLT::vector(2, 64),
117
  LLT::vector(4, 16),
118
  LLT::vector(4, 32),
119
  LLT::vector(8, 8),
120
  LLT::vector(8, 16),
121
  LLT::vector(16, 8),
122
};
123
124
// Feature bitsets.
125
enum {
126
  GIFBS_Invalid,
127
  GIFBS_HasCRC,
128
  GIFBS_HasCrypto,
129
  GIFBS_HasDotProd,
130
  GIFBS_HasFPARMv8,
131
  GIFBS_HasFullFP16,
132
  GIFBS_HasFuseAES,
133
  GIFBS_HasLSE,
134
  GIFBS_HasNEON,
135
  GIFBS_HasRDM,
136
  GIFBS_IsBE,
137
  GIFBS_IsLE,
138
  GIFBS_HasFullFP16_HasNEON,
139
  GIFBS_HasNEON_HasRDM,
140
};
141
const static PredicateBitset FeatureBitsets[] {
142
  {}, // GIFBS_Invalid
143
  {Feature_HasCRCBit, },
144
  {Feature_HasCryptoBit, },
145
  {Feature_HasDotProdBit, },
146
  {Feature_HasFPARMv8Bit, },
147
  {Feature_HasFullFP16Bit, },
148
  {Feature_HasFuseAESBit, },
149
  {Feature_HasLSEBit, },
150
  {Feature_HasNEONBit, },
151
  {Feature_HasRDMBit, },
152
  {Feature_IsBEBit, },
153
  {Feature_IsLEBit, },
154
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
155
  {Feature_HasNEONBit, Feature_HasRDMBit, },
156
};
157
158
// ComplexPattern predicates.
159
enum {
160
  GICP_Invalid,
161
  GICP_gi_addsub_shifted_imm32,
162
  GICP_gi_addsub_shifted_imm64,
163
  GICP_gi_am_indexed128,
164
  GICP_gi_am_indexed16,
165
  GICP_gi_am_indexed32,
166
  GICP_gi_am_indexed64,
167
  GICP_gi_am_indexed8,
168
  GICP_gi_am_unscaled128,
169
  GICP_gi_am_unscaled16,
170
  GICP_gi_am_unscaled32,
171
  GICP_gi_am_unscaled64,
172
  GICP_gi_am_unscaled8,
173
};
174
// See constructor for table contents
175
176
// PatFrag predicates.
177
enum {
178
  GIPFP_I64_Predicate_VectorIndex1 = GIPFP_I64_Invalid + 1,
179
  GIPFP_I64_Predicate_VectorIndexB,
180
  GIPFP_I64_Predicate_VectorIndexD,
181
  GIPFP_I64_Predicate_VectorIndexH,
182
  GIPFP_I64_Predicate_VectorIndexS,
183
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16,
184
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32,
185
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64,
186
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8,
187
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16,
188
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32,
189
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64,
190
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8,
191
  GIPFP_I64_Predicate_i64imm_32bit,
192
  GIPFP_I64_Predicate_imm0_1,
193
  GIPFP_I64_Predicate_imm0_127,
194
  GIPFP_I64_Predicate_imm0_15,
195
  GIPFP_I64_Predicate_imm0_255,
196
  GIPFP_I64_Predicate_imm0_31,
197
  GIPFP_I64_Predicate_imm0_63,
198
  GIPFP_I64_Predicate_imm0_65535,
199
  GIPFP_I64_Predicate_imm0_7,
200
  GIPFP_I64_Predicate_imm32_0_15,
201
  GIPFP_I64_Predicate_imm32_0_31,
202
  GIPFP_I64_Predicate_maski16_or_more,
203
  GIPFP_I64_Predicate_maski8_or_more,
204
  GIPFP_I64_Predicate_s64imm_32bit,
205
  GIPFP_I64_Predicate_simm4s1,
206
  GIPFP_I64_Predicate_simm4s16,
207
  GIPFP_I64_Predicate_simm4s2,
208
  GIPFP_I64_Predicate_simm4s3,
209
  GIPFP_I64_Predicate_simm4s4,
210
  GIPFP_I64_Predicate_simm5_32b,
211
  GIPFP_I64_Predicate_simm5_64b,
212
  GIPFP_I64_Predicate_simm6_32b,
213
  GIPFP_I64_Predicate_simm6s1,
214
  GIPFP_I64_Predicate_simm8,
215
  GIPFP_I64_Predicate_simm9,
216
  GIPFP_I64_Predicate_sve_elm_idx_extdup_b,
217
  GIPFP_I64_Predicate_sve_elm_idx_extdup_d,
218
  GIPFP_I64_Predicate_sve_elm_idx_extdup_h,
219
  GIPFP_I64_Predicate_sve_elm_idx_extdup_q,
220
  GIPFP_I64_Predicate_sve_elm_idx_extdup_s,
221
  GIPFP_I64_Predicate_sve_incdec_imm,
222
  GIPFP_I64_Predicate_sve_pred_enum,
223
  GIPFP_I64_Predicate_sve_prfop,
224
  GIPFP_I64_Predicate_tbz_imm0_31_diag,
225
  GIPFP_I64_Predicate_tbz_imm0_31_nodiag,
226
  GIPFP_I64_Predicate_tbz_imm32_63,
227
  GIPFP_I64_Predicate_uimm5s2,
228
  GIPFP_I64_Predicate_uimm5s4,
229
  GIPFP_I64_Predicate_uimm5s8,
230
  GIPFP_I64_Predicate_uimm6,
231
  GIPFP_I64_Predicate_uimm6s1,
232
  GIPFP_I64_Predicate_uimm6s2,
233
  GIPFP_I64_Predicate_uimm6s4,
234
  GIPFP_I64_Predicate_uimm6s8,
235
  GIPFP_I64_Predicate_vecshiftL16,
236
  GIPFP_I64_Predicate_vecshiftL32,
237
  GIPFP_I64_Predicate_vecshiftL64,
238
  GIPFP_I64_Predicate_vecshiftL8,
239
  GIPFP_I64_Predicate_vecshiftR16,
240
  GIPFP_I64_Predicate_vecshiftR16Narrow,
241
  GIPFP_I64_Predicate_vecshiftR32,
242
  GIPFP_I64_Predicate_vecshiftR32Narrow,
243
  GIPFP_I64_Predicate_vecshiftR64,
244
  GIPFP_I64_Predicate_vecshiftR64Narrow,
245
  GIPFP_I64_Predicate_vecshiftR8,
246
};
247
21.1k
bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
248
21.1k
  switch (PredicateID) {
249
21.1k
  case GIPFP_I64_Predicate_VectorIndex1: {
250
0
     return ((uint64_t)Imm) == 1; 
251
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
252
21.1k
    
return false0
;
253
21.1k
  }
254
21.1k
  case GIPFP_I64_Predicate_VectorIndexB: {
255
0
     return ((uint64_t)Imm) < 16; 
256
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
257
21.1k
    
return false0
;
258
21.1k
  }
259
21.1k
  case GIPFP_I64_Predicate_VectorIndexD: {
260
0
     return ((uint64_t)Imm) < 2; 
261
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
262
21.1k
    
return false0
;
263
21.1k
  }
264
21.1k
  case GIPFP_I64_Predicate_VectorIndexH: {
265
0
     return ((uint64_t)Imm) < 8; 
266
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
267
21.1k
    
return false0
;
268
21.1k
  }
269
21.1k
  case GIPFP_I64_Predicate_VectorIndexS: {
270
0
     return ((uint64_t)Imm) < 4; 
271
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
272
21.1k
    
return false0
;
273
21.1k
  }
274
21.1k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16: {
275
0
    
276
0
  return AArch64_AM::isSVEAddSubImm<int16_t>(Imm);
277
21.1k
278
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
279
21.1k
    
return false0
;
280
21.1k
  }
281
21.1k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32: {
282
0
    
283
0
  return AArch64_AM::isSVEAddSubImm<int32_t>(Imm);
284
21.1k
285
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
286
21.1k
    
return false0
;
287
21.1k
  }
288
21.1k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64: {
289
0
    
290
0
  return AArch64_AM::isSVEAddSubImm<int64_t>(Imm);
291
21.1k
292
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
293
21.1k
    
return false0
;
294
21.1k
  }
295
21.1k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8: {
296
0
    
297
0
  return AArch64_AM::isSVEAddSubImm<int8_t>(Imm);
298
21.1k
299
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
300
21.1k
    
return false0
;
301
21.1k
  }
302
21.1k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16: {
303
0
    
304
0
  return AArch64_AM::isSVECpyImm<int16_t>(Imm);
305
21.1k
306
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
307
21.1k
    
return false0
;
308
21.1k
  }
309
21.1k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32: {
310
0
    
311
0
  return AArch64_AM::isSVECpyImm<int32_t>(Imm);
312
21.1k
313
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
314
21.1k
    
return false0
;
315
21.1k
  }
316
21.1k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64: {
317
0
    
318
0
  return AArch64_AM::isSVECpyImm<int64_t>(Imm);
319
21.1k
320
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
321
21.1k
    
return false0
;
322
21.1k
  }
323
21.1k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8: {
324
0
    
325
0
  return AArch64_AM::isSVECpyImm<int8_t>(Imm);
326
21.1k
327
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
328
21.1k
    
return false0
;
329
21.1k
  }
330
21.1k
  case GIPFP_I64_Predicate_i64imm_32bit: {
331
123
    
332
123
  return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
333
21.1k
334
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
335
21.1k
    
return false0
;
336
21.1k
  }
337
21.1k
  case GIPFP_I64_Predicate_imm0_1: {
338
0
    
339
0
  return ((uint64_t)Imm) < 2;
340
21.1k
341
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
342
21.1k
    
return false0
;
343
21.1k
  }
344
21.1k
  case GIPFP_I64_Predicate_imm0_127: {
345
1
    
346
1
  return ((uint32_t)Imm) < 128;
347
21.1k
348
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
349
21.1k
    
return false0
;
350
21.1k
  }
351
21.1k
  case GIPFP_I64_Predicate_imm0_15: {
352
0
    
353
0
  return ((uint64_t)Imm) < 16;
354
21.1k
355
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
356
21.1k
    
return false0
;
357
21.1k
  }
358
21.1k
  case GIPFP_I64_Predicate_imm0_255: {
359
0
    
360
0
  return ((uint32_t)Imm) < 256;
361
21.1k
362
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
363
21.1k
    
return false0
;
364
21.1k
  }
365
21.1k
  case GIPFP_I64_Predicate_imm0_31: {
366
0
    
367
0
  return ((uint64_t)Imm) < 32;
368
21.1k
369
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
370
21.1k
    
return false0
;
371
21.1k
  }
372
21.1k
  case GIPFP_I64_Predicate_imm0_63: {
373
17.2k
    
374
17.2k
  return ((uint64_t)Imm) < 64;
375
21.1k
376
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
377
21.1k
    
return false0
;
378
21.1k
  }
379
21.1k
  case GIPFP_I64_Predicate_imm0_65535: {
380
0
    
381
0
  return ((uint32_t)Imm) < 65536;
382
21.1k
383
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
384
21.1k
    
return false0
;
385
21.1k
  }
386
21.1k
  case GIPFP_I64_Predicate_imm0_7: {
387
0
    
388
0
  return ((uint64_t)Imm) < 8;
389
21.1k
390
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
391
21.1k
    
return false0
;
392
21.1k
  }
393
21.1k
  case GIPFP_I64_Predicate_imm32_0_15: {
394
0
    
395
0
  return ((uint32_t)Imm) < 16;
396
21.1k
397
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
398
21.1k
    
return false0
;
399
21.1k
  }
400
21.1k
  case GIPFP_I64_Predicate_imm32_0_31: {
401
0
    
402
0
  return ((uint64_t)Imm) < 32;
403
21.1k
404
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
405
21.1k
    
return false0
;
406
21.1k
  }
407
21.1k
  case GIPFP_I64_Predicate_maski16_or_more: {
408
0
     return (Imm & 0xffff) == 0xffff; 
409
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
410
21.1k
    
return false0
;
411
21.1k
  }
412
21.1k
  case GIPFP_I64_Predicate_maski8_or_more: {
413
0
     return (Imm & 0xff) == 0xff; 
414
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
415
21.1k
    
return false0
;
416
21.1k
  }
417
21.1k
  case GIPFP_I64_Predicate_s64imm_32bit: {
418
3.70k
    
419
3.70k
  int64_t Imm64 = static_cast<int64_t>(Imm);
420
3.70k
  return Imm64 >= std::numeric_limits<int32_t>::min() &&
421
3.70k
         Imm64 <= std::numeric_limits<int32_t>::max();
422
21.1k
423
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
424
21.1k
    
return false0
;
425
21.1k
  }
426
21.1k
  case GIPFP_I64_Predicate_simm4s1: {
427
0
     return Imm >=-8  && Imm <= 7; 
428
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
429
21.1k
    
return false0
;
430
21.1k
  }
431
21.1k
  case GIPFP_I64_Predicate_simm4s16: {
432
0
     return Imm >=-128  && Imm <= 112 && (Imm % 16) == 0x0; 
433
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
434
21.1k
    
return false0
;
435
21.1k
  }
436
21.1k
  case GIPFP_I64_Predicate_simm4s2: {
437
0
     return Imm >=-16  && Imm <= 14 && (Imm % 2) == 0x0; 
438
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
439
21.1k
    
return false0
;
440
21.1k
  }
441
21.1k
  case GIPFP_I64_Predicate_simm4s3: {
442
0
     return Imm >=-24  && Imm <= 21 && (Imm % 3) == 0x0; 
443
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
444
21.1k
    
return false0
;
445
21.1k
  }
446
21.1k
  case GIPFP_I64_Predicate_simm4s4: {
447
0
     return Imm >=-32  && Imm <= 28 && (Imm % 4) == 0x0; 
448
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
449
21.1k
    
return false0
;
450
21.1k
  }
451
21.1k
  case GIPFP_I64_Predicate_simm5_32b: {
452
0
     return Imm >= -16 && Imm < 16; 
453
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
454
21.1k
    
return false0
;
455
21.1k
  }
456
21.1k
  case GIPFP_I64_Predicate_simm5_64b: {
457
0
     return Imm >= -16 && Imm < 16; 
458
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
459
21.1k
    
return false0
;
460
21.1k
  }
461
21.1k
  case GIPFP_I64_Predicate_simm6_32b: {
462
0
     return Imm >= -32 && Imm < 32; 
463
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
464
21.1k
    
return false0
;
465
21.1k
  }
466
21.1k
  case GIPFP_I64_Predicate_simm6s1: {
467
0
     return Imm >= -32 && Imm < 32; 
468
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
469
21.1k
    
return false0
;
470
21.1k
  }
471
21.1k
  case GIPFP_I64_Predicate_simm8: {
472
0
     return Imm >= -128 && Imm < 127; 
473
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
474
21.1k
    
return false0
;
475
21.1k
  }
476
21.1k
  case GIPFP_I64_Predicate_simm9: {
477
0
     return Imm >= -256 && Imm < 256; 
478
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
479
21.1k
    
return false0
;
480
21.1k
  }
481
21.1k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_b: {
482
0
     return ((uint64_t)Imm) < 64; 
483
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
484
21.1k
    
return false0
;
485
21.1k
  }
486
21.1k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_d: {
487
0
     return ((uint64_t)Imm) < 8; 
488
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
489
21.1k
    
return false0
;
490
21.1k
  }
491
21.1k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_h: {
492
0
     return ((uint64_t)Imm) < 32; 
493
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
494
21.1k
    
return false0
;
495
21.1k
  }
496
21.1k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_q: {
497
0
     return ((uint64_t)Imm) < 4; 
498
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
499
21.1k
    
return false0
;
500
21.1k
  }
501
21.1k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_s: {
502
0
     return ((uint64_t)Imm) < 16; 
503
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
504
21.1k
    
return false0
;
505
21.1k
  }
506
21.1k
  case GIPFP_I64_Predicate_sve_incdec_imm: {
507
0
    
508
0
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
509
21.1k
510
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
511
21.1k
    
return false0
;
512
21.1k
  }
513
21.1k
  case GIPFP_I64_Predicate_sve_pred_enum: {
514
0
    
515
0
  return (((uint32_t)Imm) < 32);
516
21.1k
  
517
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
518
21.1k
    
return false0
;
519
21.1k
  }
520
21.1k
  case GIPFP_I64_Predicate_sve_prfop: {
521
0
    
522
0
    return (((uint32_t)Imm) <= 15);
523
21.1k
  
524
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
525
21.1k
    
return false0
;
526
21.1k
  }
527
21.1k
  case GIPFP_I64_Predicate_tbz_imm0_31_diag: {
528
0
    
529
0
  return (((uint32_t)Imm) < 32);
530
21.1k
531
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
532
21.1k
    
return false0
;
533
21.1k
  }
534
21.1k
  case GIPFP_I64_Predicate_tbz_imm0_31_nodiag: {
535
0
    
536
0
  return (((uint32_t)Imm) < 32);
537
21.1k
538
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
539
21.1k
    
return false0
;
540
21.1k
  }
541
21.1k
  case GIPFP_I64_Predicate_tbz_imm32_63: {
542
0
    
543
0
  return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
544
21.1k
545
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
546
21.1k
    
return false0
;
547
21.1k
  }
548
21.1k
  case GIPFP_I64_Predicate_uimm5s2: {
549
0
     return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); 
550
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
551
21.1k
    
return false0
;
552
21.1k
  }
553
21.1k
  case GIPFP_I64_Predicate_uimm5s4: {
554
0
     return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); 
555
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
556
21.1k
    
return false0
;
557
21.1k
  }
558
21.1k
  case GIPFP_I64_Predicate_uimm5s8: {
559
0
     return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); 
560
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
561
21.1k
    
return false0
;
562
21.1k
  }
563
21.1k
  case GIPFP_I64_Predicate_uimm6: {
564
0
     return Imm >= 0 && Imm < 64; 
565
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
566
21.1k
    
return false0
;
567
21.1k
  }
568
21.1k
  case GIPFP_I64_Predicate_uimm6s1: {
569
0
     return Imm >= 0 && Imm < 64; 
570
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
571
21.1k
    
return false0
;
572
21.1k
  }
573
21.1k
  case GIPFP_I64_Predicate_uimm6s2: {
574
0
     return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); 
575
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
576
21.1k
    
return false0
;
577
21.1k
  }
578
21.1k
  case GIPFP_I64_Predicate_uimm6s4: {
579
0
     return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); 
580
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
581
21.1k
    
return false0
;
582
21.1k
  }
583
21.1k
  case GIPFP_I64_Predicate_uimm6s8: {
584
0
     return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); 
585
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
586
21.1k
    
return false0
;
587
21.1k
  }
588
21.1k
  case GIPFP_I64_Predicate_vecshiftL16: {
589
3
    
590
3
  return (((uint32_t)Imm) < 16);
591
21.1k
592
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
593
21.1k
    
return false0
;
594
21.1k
  }
595
21.1k
  case GIPFP_I64_Predicate_vecshiftL32: {
596
2
    
597
2
  return (((uint32_t)Imm) < 32);
598
21.1k
599
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
600
21.1k
    
return false0
;
601
21.1k
  }
602
21.1k
  case GIPFP_I64_Predicate_vecshiftL64: {
603
0
    
604
0
  return (((uint32_t)Imm) < 64);
605
21.1k
606
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
607
21.1k
    
return false0
;
608
21.1k
  }
609
21.1k
  case GIPFP_I64_Predicate_vecshiftL8: {
610
3
    
611
3
  return (((uint32_t)Imm) < 8);
612
21.1k
613
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
614
21.1k
    
return false0
;
615
21.1k
  }
616
21.1k
  case GIPFP_I64_Predicate_vecshiftR16: {
617
3
    
618
3
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
619
21.1k
620
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
621
21.1k
    
return false0
;
622
21.1k
  }
623
21.1k
  case GIPFP_I64_Predicate_vecshiftR16Narrow: {
624
8
    
625
8
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
626
21.1k
627
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
628
21.1k
    
return false0
;
629
21.1k
  }
630
21.1k
  case GIPFP_I64_Predicate_vecshiftR32: {
631
2
    
632
2
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
633
21.1k
634
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
635
21.1k
    
return false0
;
636
21.1k
  }
637
21.1k
  case GIPFP_I64_Predicate_vecshiftR32Narrow: {
638
8
    
639
8
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
640
21.1k
641
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
642
21.1k
    
return false0
;
643
21.1k
  }
644
21.1k
  case GIPFP_I64_Predicate_vecshiftR64: {
645
1
    
646
1
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
647
21.1k
648
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
649
21.1k
    
return false0
;
650
21.1k
  }
651
21.1k
  case GIPFP_I64_Predicate_vecshiftR64Narrow: {
652
8
    
653
8
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
654
21.1k
655
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
656
21.1k
    
return false0
;
657
21.1k
  }
658
21.1k
  case GIPFP_I64_Predicate_vecshiftR8: {
659
3
    
660
3
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
661
21.1k
662
21.1k
    
llvm_unreachable0
("ImmediateCode should have returned");
663
21.1k
    
return false0
;
664
0
  }
665
0
  }
666
0
  llvm_unreachable("Unknown predicate");
667
0
  return false;
668
0
}
669
// PatFrag predicates.
670
enum {
671
  GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1,
672
  GIPFP_APFloat_Predicate_fpimm16,
673
  GIPFP_APFloat_Predicate_fpimm32,
674
  GIPFP_APFloat_Predicate_fpimm64,
675
  GIPFP_APFloat_Predicate_simdimmtype10,
676
};
677
2.33k
bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
678
2.33k
  switch (PredicateID) {
679
2.33k
  case GIPFP_APFloat_Predicate_fpimm0: {
680
2.33k
    
681
2.33k
  return Imm.isExactlyValue(+0.0);
682
2.33k
683
2.33k
    
llvm_unreachable0
("ImmediateCode should have returned");
684
2.33k
    
return false0
;
685
2.33k
  }
686
2.33k
  case GIPFP_APFloat_Predicate_fpimm16: {
687
0
    
688
0
      return AArch64_AM::getFP16Imm(Imm) != -1;
689
2.33k
    
690
2.33k
    
llvm_unreachable0
("ImmediateCode should have returned");
691
2.33k
    
return false0
;
692
2.33k
  }
693
2.33k
  case GIPFP_APFloat_Predicate_fpimm32: {
694
0
    
695
0
      return AArch64_AM::getFP32Imm(Imm) != -1;
696
2.33k
    
697
2.33k
    
llvm_unreachable0
("ImmediateCode should have returned");
698
2.33k
    
return false0
;
699
2.33k
  }
700
2.33k
  case GIPFP_APFloat_Predicate_fpimm64: {
701
0
    
702
0
      return AArch64_AM::getFP64Imm(Imm) != -1;
703
2.33k
    
704
2.33k
    
llvm_unreachable0
("ImmediateCode should have returned");
705
2.33k
    
return false0
;
706
2.33k
  }
707
2.33k
  case GIPFP_APFloat_Predicate_simdimmtype10: {
708
0
    
709
0
      return AArch64_AM::isAdvSIMDModImmType10(
710
0
                 Imm.bitcastToAPInt().getZExtValue());
711
2.33k
    
712
2.33k
    
llvm_unreachable0
("ImmediateCode should have returned");
713
2.33k
    
return false0
;
714
0
  }
715
0
  }
716
0
  llvm_unreachable("Unknown predicate");
717
0
  return false;
718
0
}
719
// PatFrag predicates.
720
enum {
721
  GIPFP_APInt_Predicate_logical_imm32 = GIPFP_APInt_Invalid + 1,
722
  GIPFP_APInt_Predicate_logical_imm64,
723
};
724
0
bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
725
0
  switch (PredicateID) {
726
0
  case GIPFP_APInt_Predicate_logical_imm32: {
727
0
    
728
0
  return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32);
729
0
730
0
    llvm_unreachable("ImmediateCode should have returned");
731
0
    return false;
732
0
  }
733
0
  case GIPFP_APInt_Predicate_logical_imm64: {
734
0
    
735
0
  return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64);
736
0
737
0
    llvm_unreachable("ImmediateCode should have returned");
738
0
    return false;
739
0
  }
740
0
  }
741
0
  llvm_unreachable("Unknown predicate");
742
0
  return false;
743
0
}
744
0
bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
745
0
  const MachineFunction &MF = *MI.getParent()->getParent();
746
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
747
0
  (void)MRI;
748
0
  llvm_unreachable("Unknown predicate");
749
0
  return false;
750
0
}
751
752
AArch64InstructionSelector::ComplexMatcherMemFn
753
AArch64InstructionSelector::ComplexPredicateFns[] = {
754
  nullptr, // GICP_Invalid
755
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32
756
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64
757
  &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128
758
  &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16
759
  &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32
760
  &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64
761
  &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8
762
  &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128
763
  &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16
764
  &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32
765
  &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64
766
  &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8
767
};
768
769
// Custom renderers.
770
enum {
771
  GICR_Invalid,
772
  GICR_renderTruncImm, 
773
};
774
AArch64InstructionSelector::CustomRendererFn
775
AArch64InstructionSelector::CustomRenderers[] = {
776
  nullptr, // GICP_Invalid
777
  &AArch64InstructionSelector::renderTruncImm, // gi_trunc_imm
778
};
779
780
4.44M
bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
781
4.44M
  MachineFunction &MF = *I.getParent()->getParent();
782
4.44M
  MachineRegisterInfo &MRI = MF.getRegInfo();
783
4.44M
  // FIXME: This should be computed on a per-function basis rather than per-insn.
784
4.44M
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
785
4.44M
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
786
4.44M
  NewMIVector OutMIs;
787
4.44M
  State.MIs.clear();
788
4.44M
  State.MIs.push_back(&I);
789
4.44M
790
4.44M
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
791
1.78M
    return true;
792
1.78M
  }
793
2.66M
794
2.66M
  return false;
795
2.66M
}
796
797
4.44M
const int64_t *AArch64InstructionSelector::getMatchTable() const {
798
4.44M
  constexpr static int64_t MatchTable0[] = {
799
4.44M
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 124, /*)*//*default:*//*Label 49*/ 77510,
800
4.44M
    /*TargetOpcode::G_ADD*//*Label 0*/ 95,
801
4.44M
    /*TargetOpcode::G_SUB*//*Label 1*/ 7370,
802
4.44M
    /*TargetOpcode::G_MUL*//*Label 2*/ 9951,
803
4.44M
    /*TargetOpcode::G_SDIV*//*Label 3*/ 10732,
804
4.44M
    /*TargetOpcode::G_UDIV*//*Label 4*/ 10801, 0, 0,
805
4.44M
    /*TargetOpcode::G_AND*//*Label 5*/ 10870,
806
4.44M
    /*TargetOpcode::G_OR*//*Label 6*/ 11412,
807
4.44M
    /*TargetOpcode::G_XOR*//*Label 7*/ 11954, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
808
4.44M
    /*TargetOpcode::G_BITCAST*//*Label 8*/ 12664,
809
4.44M
    /*TargetOpcode::G_LOAD*//*Label 9*/ 20157,
810
4.44M
    /*TargetOpcode::G_SEXTLOAD*//*Label 10*/ 22213,
811
4.44M
    /*TargetOpcode::G_ZEXTLOAD*//*Label 11*/ 22684,
812
4.44M
    /*TargetOpcode::G_STORE*//*Label 12*/ 23036, 0,
813
4.44M
    /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 13*/ 24935,
814
4.44M
    /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 14*/ 26132,
815
4.44M
    /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 15*/ 27161,
816
4.44M
    /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 16*/ 28190,
817
4.44M
    /*TargetOpcode::G_ATOMICRMW_AND*//*Label 17*/ 29599, 0,
818
4.44M
    /*TargetOpcode::G_ATOMICRMW_OR*//*Label 18*/ 31008,
819
4.44M
    /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 19*/ 32037,
820
4.44M
    /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 20*/ 33066,
821
4.44M
    /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 21*/ 34095,
822
4.44M
    /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 22*/ 35124,
823
4.44M
    /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 23*/ 36153, 0, 0,
824
4.44M
    /*TargetOpcode::G_INTRINSIC*//*Label 24*/ 37182,
825
4.44M
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 25*/ 71113,
826
4.44M
    /*TargetOpcode::G_ANYEXT*//*Label 26*/ 71293,
827
4.44M
    /*TargetOpcode::G_TRUNC*//*Label 27*/ 71407,
828
4.44M
    /*TargetOpcode::G_CONSTANT*//*Label 28*/ 71532,
829
4.44M
    /*TargetOpcode::G_FCONSTANT*//*Label 29*/ 71585, 0, 0,
830
4.44M
    /*TargetOpcode::G_SEXT*//*Label 30*/ 71663,
831
4.44M
    /*TargetOpcode::G_ZEXT*//*Label 31*/ 71777,
832
4.44M
    /*TargetOpcode::G_SHL*//*Label 32*/ 72236,
833
4.44M
    /*TargetOpcode::G_LSHR*//*Label 33*/ 72412,
834
4.44M
    /*TargetOpcode::G_ASHR*//*Label 34*/ 72663, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
835
4.44M
    /*TargetOpcode::G_FADD*//*Label 35*/ 72914,
836
4.44M
    /*TargetOpcode::G_FSUB*//*Label 36*/ 73187,
837
4.44M
    /*TargetOpcode::G_FMUL*//*Label 37*/ 73460,
838
4.44M
    /*TargetOpcode::G_FMA*//*Label 38*/ 73733,
839
4.44M
    /*TargetOpcode::G_FDIV*//*Label 39*/ 75257, 0, 0, 0, 0, 0, 0,
840
4.44M
    /*TargetOpcode::G_FNEG*//*Label 40*/ 75530,
841
4.44M
    /*TargetOpcode::G_FPEXT*//*Label 41*/ 76078,
842
4.44M
    /*TargetOpcode::G_FPTRUNC*//*Label 42*/ 76207,
843
4.44M
    /*TargetOpcode::G_FPTOSI*//*Label 43*/ 76336,
844
4.44M
    /*TargetOpcode::G_FPTOUI*//*Label 44*/ 76612,
845
4.44M
    /*TargetOpcode::G_SITOFP*//*Label 45*/ 76888,
846
4.44M
    /*TargetOpcode::G_UITOFP*//*Label 46*/ 77166, 0, 0, 0,
847
4.44M
    /*TargetOpcode::G_BR*//*Label 47*/ 77444, 0, 0, 0,
848
4.44M
    /*TargetOpcode::G_BSWAP*//*Label 48*/ 77457,
849
4.44M
    // Label 0: @95
850
4.44M
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 59*/ 7369,
851
4.44M
    /*GILLT_s32*//*Label 50*/ 111,
852
4.44M
    /*GILLT_s64*//*Label 51*/ 212, 0,
853
4.44M
    /*GILLT_v2s32*//*Label 52*/ 1284,
854
4.44M
    /*GILLT_v2s64*//*Label 53*/ 1897,
855
4.44M
    /*GILLT_v4s16*//*Label 54*/ 3000,
856
4.44M
    /*GILLT_v4s32*//*Label 55*/ 3613,
857
4.44M
    /*GILLT_v8s8*//*Label 56*/ 5086,
858
4.44M
    /*GILLT_v8s16*//*Label 57*/ 5491,
859
4.44M
    /*GILLT_v16s8*//*Label 58*/ 6964,
860
4.44M
    // Label 50: @111
861
4.44M
    GIM_Try, /*On fail goto*//*Label 60*/ 211,
862
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
863
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
864
4.44M
      GIM_Try, /*On fail goto*//*Label 61*/ 155, // Rule ID 3774 //
865
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
866
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID,
867
4.44M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
868
4.44M
        // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
869
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
870
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
871
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
872
4.44M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
873
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
874
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
875
4.44M
        // GIR_Coverage, 3774,
876
4.44M
        GIR_Done,
877
4.44M
      // Label 61: @155
878
4.44M
      GIM_Try, /*On fail goto*//*Label 62*/ 189, // Rule ID 33 //
879
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
880
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
881
4.44M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
882
4.44M
        // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
883
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
884
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
885
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
886
4.44M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
887
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
888
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
889
4.44M
        // GIR_Coverage, 33,
890
4.44M
        GIR_Done,
891
4.44M
      // Label 62: @189
892
4.44M
      GIM_Try, /*On fail goto*//*Label 63*/ 210, // Rule ID 35 //
893
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
894
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
895
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
896
4.44M
        // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
897
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDWrr,
898
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
899
4.44M
        // GIR_Coverage, 35,
900
4.44M
        GIR_Done,
901
4.44M
      // Label 63: @210
902
4.44M
      GIM_Reject,
903
4.44M
    // Label 60: @211
904
4.44M
    GIM_Reject,
905
4.44M
    // Label 51: @212
906
4.44M
    GIM_Try, /*On fail goto*//*Label 64*/ 1283,
907
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
908
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
909
4.44M
      GIM_Try, /*On fail goto*//*Label 65*/ 256, // Rule ID 3775 //
910
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
911
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID,
912
4.44M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
913
4.44M
        // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
914
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
915
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
916
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
917
4.44M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
918
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
919
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
920
4.44M
        // GIR_Coverage, 3775,
921
4.44M
        GIR_Done,
922
4.44M
      // Label 65: @256
923
4.44M
      GIM_Try, /*On fail goto*//*Label 66*/ 352, // Rule ID 1885 //
924
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
925
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
926
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
927
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
928
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
929
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
930
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
931
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
932
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
933
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
934
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
935
4.44M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
936
4.44M
        // MIs[3] Operand 1
937
4.44M
        // No operand predicates
938
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
939
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
940
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
941
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
942
4.44M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
943
4.44M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
944
4.44M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
945
4.44M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
946
4.44M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
947
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
948
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
949
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
950
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
951
4.44M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
952
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
953
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
954
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
955
4.44M
        // GIR_Coverage, 1885,
956
4.44M
        GIR_Done,
957
4.44M
      // Label 66: @352
958
4.44M
      GIM_Try, /*On fail goto*//*Label 67*/ 448, // Rule ID 1886 //
959
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
960
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
961
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
962
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
963
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
964
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
965
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
966
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
967
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
968
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
969
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
970
4.44M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
971
4.44M
        // MIs[3] Operand 1
972
4.44M
        // No operand predicates
973
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
974
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
975
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
976
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
977
4.44M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
978
4.44M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
979
4.44M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
980
4.44M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
981
4.44M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
982
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
983
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
984
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
985
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
986
4.44M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
987
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
988
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
989
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
990
4.44M
        // GIR_Coverage, 1886,
991
4.44M
        GIR_Done,
992
4.44M
      // Label 67: @448
993
4.44M
      GIM_Try, /*On fail goto*//*Label 68*/ 482, // Rule ID 34 //
994
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
995
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
996
4.44M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
997
4.44M
        // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
998
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
999
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1000
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1001
4.44M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
1002
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1003
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1004
4.44M
        // GIR_Coverage, 34,
1005
4.44M
        GIR_Done,
1006
4.44M
      // Label 68: @482
1007
4.44M
      GIM_Try, /*On fail goto*//*Label 69*/ 578, // Rule ID 4026 //
1008
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1009
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1010
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1011
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1012
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1013
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1014
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1015
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1016
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1017
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1018
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1019
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1020
4.44M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
1021
4.44M
        // MIs[3] Operand 1
1022
4.44M
        // No operand predicates
1023
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1024
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1025
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1026
4.44M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1027
4.44M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1028
4.44M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1029
4.44M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1030
4.44M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1031
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1032
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1033
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1034
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1035
4.44M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1036
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1037
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1038
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1039
4.44M
        // GIR_Coverage, 4026,
1040
4.44M
        GIR_Done,
1041
4.44M
      // Label 69: @578
1042
4.44M
      GIM_Try, /*On fail goto*//*Label 70*/ 674, // Rule ID 4027 //
1043
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1044
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1045
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1046
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1047
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1048
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1049
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1050
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1051
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1052
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1053
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1054
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1055
4.44M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
1056
4.44M
        // MIs[3] Operand 1
1057
4.44M
        // No operand predicates
1058
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1059
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1060
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1061
4.44M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1062
4.44M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1063
4.44M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1064
4.44M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1065
4.44M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1066
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1067
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1068
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1069
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1070
4.44M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1071
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1072
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1073
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1074
4.44M
        // GIR_Coverage, 4027,
1075
4.44M
        GIR_Done,
1076
4.44M
      // Label 70: @674
1077
4.44M
      GIM_Try, /*On fail goto*//*Label 71*/ 759, // Rule ID 3786 //
1078
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1079
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1080
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1081
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1082
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1083
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1084
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1085
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1086
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1087
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1088
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
1089
4.44M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1090
4.44M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1091
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1092
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1093
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1094
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1095
4.44M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1096
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1097
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1098
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1099
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1100
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1101
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1102
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1103
4.44M
        // GIR_Coverage, 3786,
1104
4.44M
        GIR_Done,
1105
4.44M
      // Label 71: @759
1106
4.44M
      GIM_Try, /*On fail goto*//*Label 72*/ 844, // Rule ID 3787 //
1107
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1108
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1109
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1110
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1111
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1112
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1113
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1114
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1115
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1116
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1117
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
1118
4.44M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1119
4.44M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1120
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1121
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1122
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1123
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1124
4.44M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1125
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1126
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1127
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1128
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1129
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1130
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1131
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1132
4.44M
        // GIR_Coverage, 3787,
1133
4.44M
        GIR_Done,
1134
4.44M
      // Label 72: @844
1135
4.44M
      GIM_Try, /*On fail goto*//*Label 73*/ 929, // Rule ID 65 //
1136
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1137
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1138
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1139
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1140
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1141
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1142
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1143
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1144
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1145
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1146
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1147
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
1148
4.44M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1149
4.44M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1150
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1151
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1152
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1153
4.44M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1154
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1155
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1156
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1157
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1158
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1159
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1160
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1161
4.44M
        // GIR_Coverage, 65,
1162
4.44M
        GIR_Done,
1163
4.44M
      // Label 73: @929
1164
4.44M
      GIM_Try, /*On fail goto*//*Label 74*/ 1014, // Rule ID 67 //
1165
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1166
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1167
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1168
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1169
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1170
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1171
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1172
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1173
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1174
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1175
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1176
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
1177
4.44M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1178
4.44M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1179
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1180
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1181
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1182
4.44M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1183
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1184
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1185
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1186
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1187
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1188
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1189
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1190
4.44M
        // GIR_Coverage, 67,
1191
4.44M
        GIR_Done,
1192
4.44M
      // Label 74: @1014
1193
4.44M
      GIM_Try, /*On fail goto*//*Label 75*/ 1070, // Rule ID 3840 //
1194
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1195
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1196
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1197
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1198
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1199
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1200
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1201
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1202
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1203
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1204
4.44M
        // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 269:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1205
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
1206
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1207
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1208
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1209
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1210
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1211
4.44M
        // GIR_Coverage, 3840,
1212
4.44M
        GIR_Done,
1213
4.44M
      // Label 75: @1070
1214
4.44M
      GIM_Try, /*On fail goto*//*Label 76*/ 1126, // Rule ID 3846 //
1215
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1216
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1217
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1218
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1219
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1220
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1221
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1222
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1223
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1224
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1225
4.44M
        // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 327:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1226
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64,
1227
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1228
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1229
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1230
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1231
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1232
4.44M
        // GIR_Coverage, 3846,
1233
4.44M
        GIR_Done,
1234
4.44M
      // Label 76: @1126
1235
4.44M
      GIM_Try, /*On fail goto*//*Label 77*/ 1182, // Rule ID 686 //
1236
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1237
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1238
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1239
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1240
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1241
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1242
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1243
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1244
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1245
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1246
4.44M
        // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 269:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1247
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
1248
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1249
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1250
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1251
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1252
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1253
4.44M
        // GIR_Coverage, 686,
1254
4.44M
        GIR_Done,
1255
4.44M
      // Label 77: @1182
1256
4.44M
      GIM_Try, /*On fail goto*//*Label 78*/ 1238, // Rule ID 730 //
1257
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1258
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1259
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1260
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1261
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1262
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1263
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1264
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1265
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1266
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1267
4.44M
        // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 327:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1268
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64,
1269
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1270
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1271
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1272
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1273
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1274
4.44M
        // GIR_Coverage, 730,
1275
4.44M
        GIR_Done,
1276
4.44M
      // Label 78: @1238
1277
4.44M
      GIM_Try, /*On fail goto*//*Label 79*/ 1259, // Rule ID 36 //
1278
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1279
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1280
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1281
4.44M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ADDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
1282
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDXrr,
1283
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1284
4.44M
        // GIR_Coverage, 36,
1285
4.44M
        GIR_Done,
1286
4.44M
      // Label 79: @1259
1287
4.44M
      GIM_Try, /*On fail goto*//*Label 80*/ 1282, // Rule ID 1185 //
1288
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1289
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1290
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1291
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1292
4.44M
        // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (ADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
1293
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv1i64,
1294
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1295
4.44M
        // GIR_Coverage, 1185,
1296
4.44M
        GIR_Done,
1297
4.44M
      // Label 80: @1282
1298
4.44M
      GIM_Reject,
1299
4.44M
    // Label 64: @1283
1300
4.44M
    GIM_Reject,
1301
4.44M
    // Label 52: @1284
1302
4.44M
    GIM_Try, /*On fail goto*//*Label 81*/ 1896,
1303
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1304
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1305
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1306
4.44M
      GIM_Try, /*On fail goto*//*Label 82*/ 1362, // Rule ID 3858 //
1307
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1308
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1309
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1310
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1311
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1312
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1313
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1314
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1315
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1316
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1317
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1318
4.44M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 268:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1319
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
1320
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1321
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1322
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1323
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1324
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1325
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1326
4.44M
        // GIR_Coverage, 3858,
1327
4.44M
        GIR_Done,
1328
4.44M
      // Label 82: @1362
1329
4.44M
      GIM_Try, /*On fail goto*//*Label 83*/ 1426, // Rule ID 3864 //
1330
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1331
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1332
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1333
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1334
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1335
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1336
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1337
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1338
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1339
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1340
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1341
4.44M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 326:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1342
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
1343
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1344
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1345
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1346
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1347
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1348
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1349
4.44M
        // GIR_Coverage, 3864,
1350
4.44M
        GIR_Done,
1351
4.44M
      // Label 83: @1426
1352
4.44M
      GIM_Try, /*On fail goto*//*Label 84*/ 1478, // Rule ID 3838 //
1353
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1354
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1355
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1356
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1357
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1358
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1359
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1360
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1361
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1362
4.44M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 269:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1363
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
1364
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1365
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1366
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1367
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1368
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1369
4.44M
        // GIR_Coverage, 3838,
1370
4.44M
        GIR_Done,
1371
4.44M
      // Label 84: @1478
1372
4.44M
      GIM_Try, /*On fail goto*//*Label 85*/ 1530, // Rule ID 3844 //
1373
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1374
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1375
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1376
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1377
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1378
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1379
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1380
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1381
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1382
4.44M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 327:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1383
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32,
1384
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1385
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1386
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1387
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1388
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1389
4.44M
        // GIR_Coverage, 3844,
1390
4.44M
        GIR_Done,
1391
4.44M
      // Label 85: @1530
1392
4.44M
      GIM_Try, /*On fail goto*//*Label 86*/ 1594, // Rule ID 960 //
1393
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1394
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1395
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1396
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1397
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1398
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1399
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1400
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1401
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1402
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1403
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1404
4.44M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 268:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1405
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
1406
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1407
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1408
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1409
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1410
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1411
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1412
4.44M
        // GIR_Coverage, 960,
1413
4.44M
        GIR_Done,
1414
4.44M
      // Label 86: @1594
1415
4.44M
      GIM_Try, /*On fail goto*//*Label 87*/ 1658, // Rule ID 1071 //
1416
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1417
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1418
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1419
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1420
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1421
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1422
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1423
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1424
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1425
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1426
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1427
4.44M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 326:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1428
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
1429
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1430
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1431
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1432
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1433
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1434
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1435
4.44M
        // GIR_Coverage, 1071,
1436
4.44M
        GIR_Done,
1437
4.44M
      // Label 87: @1658
1438
4.44M
      GIM_Try, /*On fail goto*//*Label 88*/ 1710, // Rule ID 684 //
1439
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1440
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1441
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1442
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1443
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1444
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1445
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1446
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1447
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1448
4.44M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 269:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1449
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
1450
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1451
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1452
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1453
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1454
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1455
4.44M
        // GIR_Coverage, 684,
1456
4.44M
        GIR_Done,
1457
4.44M
      // Label 88: @1710
1458
4.44M
      GIM_Try, /*On fail goto*//*Label 89*/ 1762, // Rule ID 728 //
1459
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1460
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1461
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1462
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1463
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1464
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1465
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1466
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1467
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1468
4.44M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 327:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1469
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32,
1470
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1471
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1472
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1473
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1474
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1475
4.44M
        // GIR_Coverage, 728,
1476
4.44M
        GIR_Done,
1477
4.44M
      // Label 89: @1762
1478
4.44M
      GIM_Try, /*On fail goto*//*Label 90*/ 1819, // Rule ID 3852 //
1479
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1480
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1481
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1482
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1483
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1484
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1485
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1486
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1487
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1488
4.44M
        // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (MLAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1489
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32,
1490
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1491
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1492
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1493
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1494
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1495
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1496
4.44M
        // GIR_Coverage, 3852,
1497
4.44M
        GIR_Done,
1498
4.44M
      // Label 90: @1819
1499
4.44M
      GIM_Try, /*On fail goto*//*Label 91*/ 1876, // Rule ID 940 //
1500
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1501
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1502
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1503
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1504
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1505
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1506
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1507
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1508
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1509
4.44M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (MLAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1510
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32,
1511
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1512
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1513
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1514
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1515
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1516
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1517
4.44M
        // GIR_Coverage, 940,
1518
4.44M
        GIR_Done,
1519
4.44M
      // Label 91: @1876
1520
4.44M
      GIM_Try, /*On fail goto*//*Label 92*/ 1895, // Rule ID 764 //
1521
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1522
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1523
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1524
4.44M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1525
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i32,
1526
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1527
4.44M
        // GIR_Coverage, 764,
1528
4.44M
        GIR_Done,
1529
4.44M
      // Label 92: @1895
1530
4.44M
      GIM_Reject,
1531
4.44M
    // Label 81: @1896
1532
4.44M
    GIM_Reject,
1533
4.44M
    // Label 53: @1897
1534
4.44M
    GIM_Try, /*On fail goto*//*Label 93*/ 2999,
1535
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1536
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1537
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
1538
4.44M
      GIM_Try, /*On fail goto*//*Label 94*/ 1988, // Rule ID 3912 //
1539
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1540
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1541
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1542
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1543
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1544
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1545
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1546
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1547
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1548
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1549
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1550
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1551
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1552
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1553
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1554
4.44M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 268:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1555
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
1556
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1557
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1558
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1559
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1560
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1561
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1562
4.44M
        // GIR_Coverage, 3912,
1563
4.44M
        GIR_Done,
1564
4.44M
      // Label 94: @1988
1565
4.44M
      GIM_Try, /*On fail goto*//*Label 95*/ 2065, // Rule ID 3930 //
1566
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1567
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1568
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1569
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1570
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1571
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1572
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1573
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1574
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1575
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1576
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1577
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1578
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1579
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1580
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1581
4.44M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 326:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1582
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
1583
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1584
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1585
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1586
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1587
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1588
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1589
4.44M
        // GIR_Coverage, 3930,
1590
4.44M
        GIR_Done,
1591
4.44M
      // Label 95: @2065
1592
4.44M
      GIM_Try, /*On fail goto*//*Label 96*/ 2142, // Rule ID 1267 //
1593
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1594
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1595
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1596
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1597
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1598
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1599
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1600
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1601
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1602
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1603
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1604
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1605
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1606
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1607
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1608
4.44M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 268:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1609
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
1610
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1611
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1612
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1613
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1614
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1615
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1616
4.44M
        // GIR_Coverage, 1267,
1617
4.44M
        GIR_Done,
1618
4.44M
      // Label 96: @2142
1619
4.44M
      GIM_Try, /*On fail goto*//*Label 97*/ 2219, // Rule ID 1333 //
1620
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1621
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1622
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1623
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1624
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1625
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1626
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1627
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1628
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1629
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1630
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1631
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1632
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1633
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1634
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1635
4.44M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 326:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1636
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
1637
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1638
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1639
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1640
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1641
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1642
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1643
4.44M
        // GIR_Coverage, 1333,
1644
4.44M
        GIR_Done,
1645
4.44M
      // Label 97: @2219
1646
4.44M
      GIM_Try, /*On fail goto*//*Label 98*/ 2283, // Rule ID 3924 //
1647
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1648
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1649
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1650
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1651
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
1652
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1653
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1654
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1655
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1656
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1657
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1658
4.44M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 285:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1659
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
1660
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1661
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1662
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1663
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1664
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1665
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1666
4.44M
        // GIR_Coverage, 3924,
1667
4.44M
        GIR_Done,
1668
4.44M
      // Label 98: @2283
1669
4.44M
      GIM_Try, /*On fail goto*//*Label 99*/ 2347, // Rule ID 3942 //
1670
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1671
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1672
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1673
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1674
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
1675
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1676
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1677
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1678
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1679
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1680
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1681
4.44M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 339:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1682
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
1683
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1684
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1685
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1686
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1687
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1688
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1689
4.44M
        // GIR_Coverage, 3942,
1690
4.44M
        GIR_Done,
1691
4.44M
      // Label 99: @2347
1692
4.44M
      GIM_Try, /*On fail goto*//*Label 100*/ 2399, // Rule ID 3841 //
1693
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1694
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1695
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1696
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1697
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1698
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1699
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1700
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1701
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1702
4.44M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 269:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1703
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
1704
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1705
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1706
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1707
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1708
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1709
4.44M
        // GIR_Coverage, 3841,
1710
4.44M
        GIR_Done,
1711
4.44M
      // Label 100: @2399
1712
4.44M
      GIM_Try, /*On fail goto*//*Label 101*/ 2451, // Rule ID 3847 //
1713
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1714
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1715
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1716
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1717
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1718
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1719
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1720
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1721
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1722
4.44M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 327:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1723
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64,
1724
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1725
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1726
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1727
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1728
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1729
4.44M
        // GIR_Coverage, 3847,
1730
4.44M
        GIR_Done,
1731
4.44M
      // Label 101: @2451
1732
4.44M
      GIM_Try, /*On fail goto*//*Label 102*/ 2515, // Rule ID 1291 //
1733
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1734
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1735
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1736
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1737
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1738
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
1739
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1740
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1741
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1742
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1743
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1744
4.44M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 285:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1745
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
1746
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1747
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1748
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1749
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1750
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1751
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1752
4.44M
        // GIR_Coverage, 1291,
1753
4.44M
        GIR_Done,
1754
4.44M
      // Label 102: @2515
1755
4.44M
      GIM_Try, /*On fail goto*//*Label 103*/ 2579, // Rule ID 1351 //
1756
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1757
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1758
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1759
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1760
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1761
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
1762
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1763
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1764
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1765
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1766
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1767
4.44M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 339:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1768
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
1769
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1770
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1771
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1772
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1773
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1774
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1775
4.44M
        // GIR_Coverage, 1351,
1776
4.44M
        GIR_Done,
1777
4.44M
      // Label 103: @2579
1778
4.44M
      GIM_Try, /*On fail goto*//*Label 104*/ 2631, // Rule ID 687 //
1779
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1780
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1781
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1782
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1783
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1784
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1785
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1786
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1787
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1788
4.44M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 269:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1789
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
1790
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1791
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1792
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1793
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1794
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1795
4.44M
        // GIR_Coverage, 687,
1796
4.44M
        GIR_Done,
1797
4.44M
      // Label 104: @2631
1798
4.44M
      GIM_Try, /*On fail goto*//*Label 105*/ 2683, // Rule ID 731 //
1799
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1800
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1801
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1802
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1803
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1804
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1805
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1806
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1807
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1808
4.44M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 327:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1809
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64,
1810
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1811
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1812
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1813
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1814
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1815
4.44M
        // GIR_Coverage, 731,
1816
4.44M
        GIR_Done,
1817
4.44M
      // Label 105: @2683
1818
4.44M
      GIM_Try, /*On fail goto*//*Label 106*/ 2741, // Rule ID 1279 //
1819
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1820
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1821
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1822
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1823
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1824
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1825
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1826
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1827
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1828
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1829
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1830
4.44M
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1831
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv2i32_v2i64,
1832
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1833
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1834
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1835
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1836
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1837
4.44M
        // GIR_Coverage, 1279,
1838
4.44M
        GIR_Done,
1839
4.44M
      // Label 106: @2741
1840
4.44M
      GIM_Try, /*On fail goto*//*Label 107*/ 2799, // Rule ID 1339 //
1841
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1842
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1843
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1844
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1845
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1846
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1847
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1848
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1849
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1850
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1851
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1852
4.44M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1853
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64,
1854
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1855
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1856
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1857
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1858
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1859
4.44M
        // GIR_Coverage, 1339,
1860
4.44M
        GIR_Done,
1861
4.44M
      // Label 107: @2799
1862
4.44M
      GIM_Try, /*On fail goto*//*Label 108*/ 2844, // Rule ID 3918 //
1863
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1864
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1865
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1866
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1867
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1868
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1869
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1870
4.44M
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1871
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64,
1872
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1873
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1874
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1875
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1876
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1877
4.44M
        // GIR_Coverage, 3918,
1878
4.44M
        GIR_Done,
1879
4.44M
      // Label 108: @2844
1880
4.44M
      GIM_Try, /*On fail goto*//*Label 109*/ 2889, // Rule ID 3936 //
1881
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1882
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1883
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1884
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1885
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1886
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1887
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1888
4.44M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1889
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64,
1890
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1891
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1892
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1893
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1894
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1895
4.44M
        // GIR_Coverage, 3936,
1896
4.44M
        GIR_Done,
1897
4.44M
      // Label 109: @2889
1898
4.44M
      GIM_Try, /*On fail goto*//*Label 110*/ 2934, // Rule ID 1285 //
1899
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1900
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1901
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1902
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1903
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1904
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1905
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1906
4.44M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1907
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64,
1908
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1909
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1910
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1911
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1912
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1913
4.44M
        // GIR_Coverage, 1285,
1914
4.44M
        GIR_Done,
1915
4.44M
      // Label 110: @2934
1916
4.44M
      GIM_Try, /*On fail goto*//*Label 111*/ 2979, // Rule ID 1345 //
1917
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1918
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1919
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1920
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1921
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1922
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1923
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1924
4.44M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1925
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64,
1926
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1927
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1928
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1929
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1930
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1931
4.44M
        // GIR_Coverage, 1345,
1932
4.44M
        GIR_Done,
1933
4.44M
      // Label 111: @2979
1934
4.44M
      GIM_Try, /*On fail goto*//*Label 112*/ 2998, // Rule ID 766 //
1935
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1936
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1937
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1938
4.44M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
1939
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i64,
1940
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1941
4.44M
        // GIR_Coverage, 766,
1942
4.44M
        GIR_Done,
1943
4.44M
      // Label 112: @2998
1944
4.44M
      GIM_Reject,
1945
4.44M
    // Label 93: @2999
1946
4.44M
    GIM_Reject,
1947
4.44M
    // Label 54: @3000
1948
4.44M
    GIM_Try, /*On fail goto*//*Label 113*/ 3612,
1949
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1950
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
1951
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1952
4.44M
      GIM_Try, /*On fail goto*//*Label 114*/ 3078, // Rule ID 3856 //
1953
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1954
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1955
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1956
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1957
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1958
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1959
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1960
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1961
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1962
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1963
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1964
4.44M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 268:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
1965
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
1966
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1967
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1968
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1969
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1970
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1971
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1972
4.44M
        // GIR_Coverage, 3856,
1973
4.44M
        GIR_Done,
1974
4.44M
      // Label 114: @3078
1975
4.44M
      GIM_Try, /*On fail goto*//*Label 115*/ 3142, // Rule ID 3862 //
1976
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
1977
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1978
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1979
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1980
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1981
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1982
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1983
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1984
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1985
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1986
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1987
4.44M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 326:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
1988
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
1989
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1990
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1991
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1992
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1993
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
1994
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1995
4.44M
        // GIR_Coverage, 3862,
1996
4.44M
        GIR_Done,
1997
4.44M
      // Label 115: @3142
1998
4.44M
      GIM_Try, /*On fail goto*//*Label 116*/ 3194, // Rule ID 3836 //
1999
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2000
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2001
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2002
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2003
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2004
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2005
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2006
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2007
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2008
4.44M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 269:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2009
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
2010
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2011
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2012
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2013
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2014
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2015
4.44M
        // GIR_Coverage, 3836,
2016
4.44M
        GIR_Done,
2017
4.44M
      // Label 116: @3194
2018
4.44M
      GIM_Try, /*On fail goto*//*Label 117*/ 3246, // Rule ID 3842 //
2019
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2020
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2021
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2022
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2023
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2024
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2025
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2026
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2027
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2028
4.44M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 327:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2029
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
2030
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2031
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2032
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2033
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2034
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2035
4.44M
        // GIR_Coverage, 3842,
2036
4.44M
        GIR_Done,
2037
4.44M
      // Label 117: @3246
2038
4.44M
      GIM_Try, /*On fail goto*//*Label 118*/ 3310, // Rule ID 958 //
2039
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2040
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2041
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2042
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2043
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2044
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2045
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2046
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2047
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2048
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2049
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2050
4.44M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 268:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2051
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
2052
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2053
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2054
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2055
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2056
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2057
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2058
4.44M
        // GIR_Coverage, 958,
2059
4.44M
        GIR_Done,
2060
4.44M
      // Label 118: @3310
2061
4.44M
      GIM_Try, /*On fail goto*//*Label 119*/ 3374, // Rule ID 1069 //
2062
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2063
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2064
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2065
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2066
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2067
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2068
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2069
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2070
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2071
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2072
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2073
4.44M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 326:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2074
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
2075
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2076
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2077
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2078
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2079
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2080
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2081
4.44M
        // GIR_Coverage, 1069,
2082
4.44M
        GIR_Done,
2083
4.44M
      // Label 119: @3374
2084
4.44M
      GIM_Try, /*On fail goto*//*Label 120*/ 3426, // Rule ID 682 //
2085
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2086
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2087
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2088
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2089
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2090
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2091
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2092
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2093
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2094
4.44M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 269:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2095
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
2096
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2097
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2098
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2099
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2100
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2101
4.44M
        // GIR_Coverage, 682,
2102
4.44M
        GIR_Done,
2103
4.44M
      // Label 120: @3426
2104
4.44M
      GIM_Try, /*On fail goto*//*Label 121*/ 3478, // Rule ID 726 //
2105
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2106
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2107
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2108
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2109
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2110
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2111
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2112
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2113
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2114
4.44M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 327:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2115
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
2116
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2117
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2118
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2119
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2120
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2121
4.44M
        // GIR_Coverage, 726,
2122
4.44M
        GIR_Done,
2123
4.44M
      // Label 121: @3478
2124
4.44M
      GIM_Try, /*On fail goto*//*Label 122*/ 3535, // Rule ID 3850 //
2125
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2126
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2127
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2128
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2129
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2130
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2131
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2132
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2133
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2134
4.44M
        // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (MLAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2135
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16,
2136
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2137
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2138
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2139
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2140
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2141
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2142
4.44M
        // GIR_Coverage, 3850,
2143
4.44M
        GIR_Done,
2144
4.44M
      // Label 122: @3535
2145
4.44M
      GIM_Try, /*On fail goto*//*Label 123*/ 3592, // Rule ID 938 //
2146
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2147
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2148
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2149
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2150
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2151
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2152
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2153
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2154
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2155
4.44M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (MLAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2156
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16,
2157
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2158
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2159
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2160
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2161
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2162
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2163
4.44M
        // GIR_Coverage, 938,
2164
4.44M
        GIR_Done,
2165
4.44M
      // Label 123: @3592
2166
4.44M
      GIM_Try, /*On fail goto*//*Label 124*/ 3611, // Rule ID 762 //
2167
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2168
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2169
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2170
4.44M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2171
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i16,
2172
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2173
4.44M
        // GIR_Coverage, 762,
2174
4.44M
        GIR_Done,
2175
4.44M
      // Label 124: @3611
2176
4.44M
      GIM_Reject,
2177
4.44M
    // Label 113: @3612
2178
4.44M
    GIM_Reject,
2179
4.44M
    // Label 55: @3613
2180
4.44M
    GIM_Try, /*On fail goto*//*Label 125*/ 5085,
2181
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2182
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2183
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
2184
4.44M
      GIM_Try, /*On fail goto*//*Label 126*/ 3704, // Rule ID 3910 //
2185
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2186
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2187
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2188
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2189
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2190
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2191
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2192
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2193
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2194
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2195
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2196
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2197
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2198
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2199
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2200
4.44M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 268:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2201
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
2202
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2203
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2204
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2205
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2206
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2207
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2208
4.44M
        // GIR_Coverage, 3910,
2209
4.44M
        GIR_Done,
2210
4.44M
      // Label 126: @3704
2211
4.44M
      GIM_Try, /*On fail goto*//*Label 127*/ 3781, // Rule ID 3928 //
2212
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2213
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2214
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2215
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2216
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2217
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2218
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2219
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2220
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2221
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2222
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2223
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2224
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2225
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2226
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2227
4.44M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 326:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2228
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
2229
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2230
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2231
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2232
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2233
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2234
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2235
4.44M
        // GIR_Coverage, 3928,
2236
4.44M
        GIR_Done,
2237
4.44M
      // Label 127: @3781
2238
4.44M
      GIM_Try, /*On fail goto*//*Label 128*/ 3858, // Rule ID 1265 //
2239
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2240
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2241
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2242
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2243
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2244
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2245
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2246
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2247
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2248
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2249
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2250
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2251
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2252
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2253
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2254
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 268:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2255
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
2256
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2257
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2258
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2259
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2260
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2261
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2262
4.44M
        // GIR_Coverage, 1265,
2263
4.44M
        GIR_Done,
2264
4.44M
      // Label 128: @3858
2265
4.44M
      GIM_Try, /*On fail goto*//*Label 129*/ 3935, // Rule ID 1331 //
2266
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2267
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2268
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2269
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2270
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2271
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2272
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2273
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2274
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2275
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2276
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2277
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2278
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2279
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2280
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2281
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 326:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2282
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
2283
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2284
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2285
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2286
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2287
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2288
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2289
4.44M
        // GIR_Coverage, 1331,
2290
4.44M
        GIR_Done,
2291
4.44M
      // Label 129: @3935
2292
4.44M
      GIM_Try, /*On fail goto*//*Label 130*/ 3999, // Rule ID 3859 //
2293
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2294
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2295
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2296
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2297
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2298
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2299
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2300
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2301
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2302
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2303
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2304
4.44M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 268:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2305
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
2306
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2307
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2308
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2309
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2310
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2311
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2312
4.44M
        // GIR_Coverage, 3859,
2313
4.44M
        GIR_Done,
2314
4.44M
      // Label 130: @3999
2315
4.44M
      GIM_Try, /*On fail goto*//*Label 131*/ 4063, // Rule ID 3865 //
2316
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2317
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2318
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2319
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2320
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2321
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2322
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2323
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2324
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2325
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2326
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2327
4.44M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 326:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2328
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
2329
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2330
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2331
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2332
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2333
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2334
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2335
4.44M
        // GIR_Coverage, 3865,
2336
4.44M
        GIR_Done,
2337
4.44M
      // Label 131: @4063
2338
4.44M
      GIM_Try, /*On fail goto*//*Label 132*/ 4127, // Rule ID 3922 //
2339
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2340
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2341
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2342
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2343
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
2344
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2345
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2346
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2347
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2348
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2349
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2350
4.44M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 285:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2351
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
2352
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2353
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2354
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2355
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2356
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2357
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2358
4.44M
        // GIR_Coverage, 3922,
2359
4.44M
        GIR_Done,
2360
4.44M
      // Label 132: @4127
2361
4.44M
      GIM_Try, /*On fail goto*//*Label 133*/ 4191, // Rule ID 3940 //
2362
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2363
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2364
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2365
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2366
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
2367
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2368
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2369
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2370
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2371
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2372
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2373
4.44M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 339:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2374
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
2375
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2376
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2377
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2378
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2379
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2380
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2381
4.44M
        // GIR_Coverage, 3940,
2382
4.44M
        GIR_Done,
2383
4.44M
      // Label 133: @4191
2384
4.44M
      GIM_Try, /*On fail goto*//*Label 134*/ 4243, // Rule ID 3839 //
2385
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2386
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2387
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2388
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2389
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2390
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2391
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2392
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2393
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2394
4.44M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 269:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2395
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
2396
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2397
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2398
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2399
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2400
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2401
4.44M
        // GIR_Coverage, 3839,
2402
4.44M
        GIR_Done,
2403
4.44M
      // Label 134: @4243
2404
4.44M
      GIM_Try, /*On fail goto*//*Label 135*/ 4295, // Rule ID 3845 //
2405
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2406
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2407
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2408
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2409
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2410
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2411
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2412
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2413
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2414
4.44M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 327:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2415
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32,
2416
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2417
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2418
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2419
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2420
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2421
4.44M
        // GIR_Coverage, 3845,
2422
4.44M
        GIR_Done,
2423
4.44M
      // Label 135: @4295
2424
4.44M
      GIM_Try, /*On fail goto*//*Label 136*/ 4359, // Rule ID 961 //
2425
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2426
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2427
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2428
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2429
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2430
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2431
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2432
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2433
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2434
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2435
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2436
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 268:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2437
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
2438
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2439
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2440
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2441
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2442
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2443
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2444
4.44M
        // GIR_Coverage, 961,
2445
4.44M
        GIR_Done,
2446
4.44M
      // Label 136: @4359
2447
4.44M
      GIM_Try, /*On fail goto*//*Label 137*/ 4423, // Rule ID 1072 //
2448
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2449
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2450
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2451
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2452
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2453
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2454
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2455
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2456
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2457
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2458
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2459
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 326:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2460
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
2461
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2462
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2463
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2464
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2465
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2466
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2467
4.44M
        // GIR_Coverage, 1072,
2468
4.44M
        GIR_Done,
2469
4.44M
      // Label 137: @4423
2470
4.44M
      GIM_Try, /*On fail goto*//*Label 138*/ 4487, // Rule ID 1289 //
2471
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2472
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2473
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2474
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2475
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2476
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
2477
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2478
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2479
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2480
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2481
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2482
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 285:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2483
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
2484
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2485
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2486
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2487
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2488
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2489
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2490
4.44M
        // GIR_Coverage, 1289,
2491
4.44M
        GIR_Done,
2492
4.44M
      // Label 138: @4487
2493
4.44M
      GIM_Try, /*On fail goto*//*Label 139*/ 4551, // Rule ID 1349 //
2494
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2495
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2496
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2497
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2498
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2499
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
2500
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2501
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2502
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2503
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2504
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2505
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 339:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2506
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
2507
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2508
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2509
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2510
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2511
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2512
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2513
4.44M
        // GIR_Coverage, 1349,
2514
4.44M
        GIR_Done,
2515
4.44M
      // Label 139: @4551
2516
4.44M
      GIM_Try, /*On fail goto*//*Label 140*/ 4603, // Rule ID 685 //
2517
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2518
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2519
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2520
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2521
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2522
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2523
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2524
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2525
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2526
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 269:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2527
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
2528
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2529
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2530
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2531
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2532
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2533
4.44M
        // GIR_Coverage, 685,
2534
4.44M
        GIR_Done,
2535
4.44M
      // Label 140: @4603
2536
4.44M
      GIM_Try, /*On fail goto*//*Label 141*/ 4655, // Rule ID 729 //
2537
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2538
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2539
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2540
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2541
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2542
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2543
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2544
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2545
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2546
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 327:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2547
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32,
2548
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2549
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2550
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2551
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2552
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2553
4.44M
        // GIR_Coverage, 729,
2554
4.44M
        GIR_Done,
2555
4.44M
      // Label 141: @4655
2556
4.44M
      GIM_Try, /*On fail goto*//*Label 142*/ 4713, // Rule ID 1277 //
2557
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2558
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2559
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2560
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2561
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2562
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2563
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2564
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2565
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2566
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2567
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2568
4.44M
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2569
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv4i16_v4i32,
2570
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2571
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2572
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
2573
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2574
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2575
4.44M
        // GIR_Coverage, 1277,
2576
4.44M
        GIR_Done,
2577
4.44M
      // Label 142: @4713
2578
4.44M
      GIM_Try, /*On fail goto*//*Label 143*/ 4771, // Rule ID 1337 //
2579
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2580
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2581
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2582
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2583
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2584
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2585
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2586
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2587
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2588
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2589
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2590
4.44M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2591
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32,
2592
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2593
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2594
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
2595
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2596
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2597
4.44M
        // GIR_Coverage, 1337,
2598
4.44M
        GIR_Done,
2599
4.44M
      // Label 143: @4771
2600
4.44M
      GIM_Try, /*On fail goto*//*Label 144*/ 4828, // Rule ID 3853 //
2601
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2602
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2603
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2604
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2605
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2606
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2607
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2608
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2609
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2610
4.44M
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (MLAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2611
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32,
2612
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2613
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2614
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2615
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2616
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2617
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2618
4.44M
        // GIR_Coverage, 3853,
2619
4.44M
        GIR_Done,
2620
4.44M
      // Label 144: @4828
2621
4.44M
      GIM_Try, /*On fail goto*//*Label 145*/ 4873, // Rule ID 3916 //
2622
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2623
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2624
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2625
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2626
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2627
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2628
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2629
4.44M
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2630
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32,
2631
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2632
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
2633
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2634
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2635
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2636
4.44M
        // GIR_Coverage, 3916,
2637
4.44M
        GIR_Done,
2638
4.44M
      // Label 145: @4873
2639
4.44M
      GIM_Try, /*On fail goto*//*Label 146*/ 4918, // Rule ID 3934 //
2640
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2641
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2642
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2643
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2644
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2645
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2646
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2647
4.44M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2648
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32,
2649
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2650
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
2651
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2652
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2653
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2654
4.44M
        // GIR_Coverage, 3934,
2655
4.44M
        GIR_Done,
2656
4.44M
      // Label 146: @4918
2657
4.44M
      GIM_Try, /*On fail goto*//*Label 147*/ 4975, // Rule ID 941 //
2658
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2659
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2660
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2661
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2662
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2663
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2664
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2665
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2666
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2667
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (MLAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2668
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32,
2669
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2670
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2671
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2672
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2673
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2674
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2675
4.44M
        // GIR_Coverage, 941,
2676
4.44M
        GIR_Done,
2677
4.44M
      // Label 147: @4975
2678
4.44M
      GIM_Try, /*On fail goto*//*Label 148*/ 5020, // Rule ID 1283 //
2679
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2680
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2681
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2682
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2683
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2684
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2685
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2686
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2687
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32,
2688
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2689
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
2690
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2691
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2692
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2693
4.44M
        // GIR_Coverage, 1283,
2694
4.44M
        GIR_Done,
2695
4.44M
      // Label 148: @5020
2696
4.44M
      GIM_Try, /*On fail goto*//*Label 149*/ 5065, // Rule ID 1343 //
2697
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2698
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2699
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2700
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2701
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2702
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2703
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2704
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2705
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32,
2706
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2707
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
2708
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2709
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2710
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2711
4.44M
        // GIR_Coverage, 1343,
2712
4.44M
        GIR_Done,
2713
4.44M
      // Label 149: @5065
2714
4.44M
      GIM_Try, /*On fail goto*//*Label 150*/ 5084, // Rule ID 765 //
2715
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2716
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2717
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2718
4.44M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2719
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i32,
2720
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2721
4.44M
        // GIR_Coverage, 765,
2722
4.44M
        GIR_Done,
2723
4.44M
      // Label 150: @5084
2724
4.44M
      GIM_Reject,
2725
4.44M
    // Label 125: @5085
2726
4.44M
    GIM_Reject,
2727
4.44M
    // Label 56: @5086
2728
4.44M
    GIM_Try, /*On fail goto*//*Label 151*/ 5490,
2729
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
2730
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
2731
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
2732
4.44M
      GIM_Try, /*On fail goto*//*Label 152*/ 5164, // Rule ID 3854 //
2733
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2734
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2735
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2736
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2737
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2738
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2739
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2740
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2741
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2742
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2743
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2744
4.44M
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 268:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2745
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
2746
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2747
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2748
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2749
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2750
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2751
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2752
4.44M
        // GIR_Coverage, 3854,
2753
4.44M
        GIR_Done,
2754
4.44M
      // Label 152: @5164
2755
4.44M
      GIM_Try, /*On fail goto*//*Label 153*/ 5228, // Rule ID 3860 //
2756
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2757
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2758
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2759
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2760
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2761
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2762
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2763
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2764
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2765
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2766
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2767
4.44M
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 326:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2768
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
2769
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2770
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2771
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2772
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2773
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2774
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2775
4.44M
        // GIR_Coverage, 3860,
2776
4.44M
        GIR_Done,
2777
4.44M
      // Label 153: @5228
2778
4.44M
      GIM_Try, /*On fail goto*//*Label 154*/ 5292, // Rule ID 956 //
2779
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2780
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2781
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2782
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2783
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2784
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2785
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2786
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2787
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2788
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2789
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2790
4.44M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 268:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2791
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
2792
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2793
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2794
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2795
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2796
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2797
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2798
4.44M
        // GIR_Coverage, 956,
2799
4.44M
        GIR_Done,
2800
4.44M
      // Label 154: @5292
2801
4.44M
      GIM_Try, /*On fail goto*//*Label 155*/ 5356, // Rule ID 1067 //
2802
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2803
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2804
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2805
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2806
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2807
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2808
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2809
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2810
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2811
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2812
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2813
4.44M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 326:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2814
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
2815
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2816
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2817
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2818
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2819
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2820
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2821
4.44M
        // GIR_Coverage, 1067,
2822
4.44M
        GIR_Done,
2823
4.44M
      // Label 155: @5356
2824
4.44M
      GIM_Try, /*On fail goto*//*Label 156*/ 5413, // Rule ID 3848 //
2825
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2826
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2827
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2828
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2829
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2830
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2831
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2832
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2833
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2834
4.44M
        // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (MLAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2835
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8,
2836
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2837
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2838
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2839
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2840
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2841
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2842
4.44M
        // GIR_Coverage, 3848,
2843
4.44M
        GIR_Done,
2844
4.44M
      // Label 156: @5413
2845
4.44M
      GIM_Try, /*On fail goto*//*Label 157*/ 5470, // Rule ID 936 //
2846
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2847
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2848
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2849
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2850
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2851
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2852
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2853
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2854
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2855
4.44M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (MLAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2856
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8,
2857
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2858
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2859
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2860
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2861
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2862
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2863
4.44M
        // GIR_Coverage, 936,
2864
4.44M
        GIR_Done,
2865
4.44M
      // Label 157: @5470
2866
4.44M
      GIM_Try, /*On fail goto*//*Label 158*/ 5489, // Rule ID 760 //
2867
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2868
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2869
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2870
4.44M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2871
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i8,
2872
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2873
4.44M
        // GIR_Coverage, 760,
2874
4.44M
        GIR_Done,
2875
4.44M
      // Label 158: @5489
2876
4.44M
      GIM_Reject,
2877
4.44M
    // Label 151: @5490
2878
4.44M
    GIM_Reject,
2879
4.44M
    // Label 57: @5491
2880
4.44M
    GIM_Try, /*On fail goto*//*Label 159*/ 6963,
2881
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2882
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2883
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
2884
4.44M
      GIM_Try, /*On fail goto*//*Label 160*/ 5582, // Rule ID 3908 //
2885
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2886
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2887
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2888
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2889
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2890
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2891
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2892
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2893
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2894
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2895
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2896
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2897
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2898
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2899
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2900
4.44M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 268:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2901
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
2902
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2903
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2904
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2905
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2906
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2907
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2908
4.44M
        // GIR_Coverage, 3908,
2909
4.44M
        GIR_Done,
2910
4.44M
      // Label 160: @5582
2911
4.44M
      GIM_Try, /*On fail goto*//*Label 161*/ 5659, // Rule ID 3926 //
2912
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2913
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2914
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2915
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2916
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2917
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2918
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2919
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2920
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2921
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2922
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2923
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2924
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2925
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2926
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2927
4.44M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 326:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2928
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
2929
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2930
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2931
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2932
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2933
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2934
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2935
4.44M
        // GIR_Coverage, 3926,
2936
4.44M
        GIR_Done,
2937
4.44M
      // Label 161: @5659
2938
4.44M
      GIM_Try, /*On fail goto*//*Label 162*/ 5736, // Rule ID 1263 //
2939
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2940
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2941
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2942
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2943
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2944
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2945
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2946
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2947
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2948
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2949
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2950
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2951
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2952
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2953
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2954
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 268:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2955
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
2956
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2957
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2958
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2959
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2960
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2961
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2962
4.44M
        // GIR_Coverage, 1263,
2963
4.44M
        GIR_Done,
2964
4.44M
      // Label 162: @5736
2965
4.44M
      GIM_Try, /*On fail goto*//*Label 163*/ 5813, // Rule ID 1329 //
2966
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2967
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2968
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2969
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2970
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2971
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2972
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2973
4.44M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2974
4.44M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2975
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2976
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2977
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2978
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2979
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2980
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2981
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 326:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2982
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
2983
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2984
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2985
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2986
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2987
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
2988
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2989
4.44M
        // GIR_Coverage, 1329,
2990
4.44M
        GIR_Done,
2991
4.44M
      // Label 163: @5813
2992
4.44M
      GIM_Try, /*On fail goto*//*Label 164*/ 5877, // Rule ID 3857 //
2993
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
2994
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2995
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2996
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2997
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2998
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2999
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3000
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3001
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3002
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3003
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3004
4.44M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 268:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3005
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
3006
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3007
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3008
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3009
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3010
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3011
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3012
4.44M
        // GIR_Coverage, 3857,
3013
4.44M
        GIR_Done,
3014
4.44M
      // Label 164: @5877
3015
4.44M
      GIM_Try, /*On fail goto*//*Label 165*/ 5941, // Rule ID 3863 //
3016
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3017
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3018
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3019
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3020
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3021
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3022
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3023
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3024
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3025
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3026
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3027
4.44M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 326:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3028
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
3029
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3030
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3031
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3032
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3033
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3034
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3035
4.44M
        // GIR_Coverage, 3863,
3036
4.44M
        GIR_Done,
3037
4.44M
      // Label 165: @5941
3038
4.44M
      GIM_Try, /*On fail goto*//*Label 166*/ 6005, // Rule ID 3920 //
3039
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3040
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3041
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3042
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3043
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
3044
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3045
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3046
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3047
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3048
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3049
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3050
4.44M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 285:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3051
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
3052
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3053
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3054
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3055
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3056
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3057
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3058
4.44M
        // GIR_Coverage, 3920,
3059
4.44M
        GIR_Done,
3060
4.44M
      // Label 166: @6005
3061
4.44M
      GIM_Try, /*On fail goto*//*Label 167*/ 6069, // Rule ID 3938 //
3062
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3063
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3064
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3065
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3066
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
3067
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3068
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3069
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3070
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3071
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3072
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3073
4.44M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 339:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3074
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
3075
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3076
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3077
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3078
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3079
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3080
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3081
4.44M
        // GIR_Coverage, 3938,
3082
4.44M
        GIR_Done,
3083
4.44M
      // Label 167: @6069
3084
4.44M
      GIM_Try, /*On fail goto*//*Label 168*/ 6121, // Rule ID 3837 //
3085
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3086
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3087
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3088
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3089
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
3090
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3091
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3092
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3093
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3094
4.44M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 269:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3095
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
3096
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3097
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3098
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3099
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3100
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3101
4.44M
        // GIR_Coverage, 3837,
3102
4.44M
        GIR_Done,
3103
4.44M
      // Label 168: @6121
3104
4.44M
      GIM_Try, /*On fail goto*//*Label 169*/ 6173, // Rule ID 3843 //
3105
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3106
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3107
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3108
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3109
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
3110
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3111
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3112
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3113
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3114
4.44M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 327:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3115
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
3116
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3117
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3118
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3119
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3120
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3121
4.44M
        // GIR_Coverage, 3843,
3122
4.44M
        GIR_Done,
3123
4.44M
      // Label 169: @6173
3124
4.44M
      GIM_Try, /*On fail goto*//*Label 170*/ 6237, // Rule ID 959 //
3125
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3126
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3127
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3128
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3129
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3130
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3131
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3132
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3133
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3134
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3135
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3136
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 268:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3137
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
3138
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3139
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3140
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3141
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3142
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3143
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3144
4.44M
        // GIR_Coverage, 959,
3145
4.44M
        GIR_Done,
3146
4.44M
      // Label 170: @6237
3147
4.44M
      GIM_Try, /*On fail goto*//*Label 171*/ 6301, // Rule ID 1070 //
3148
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3149
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3150
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3151
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3152
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3153
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3154
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3155
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3156
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3157
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3158
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3159
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 326:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3160
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
3161
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3162
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3163
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3164
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3165
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3166
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3167
4.44M
        // GIR_Coverage, 1070,
3168
4.44M
        GIR_Done,
3169
4.44M
      // Label 171: @6301
3170
4.44M
      GIM_Try, /*On fail goto*//*Label 172*/ 6365, // Rule ID 1287 //
3171
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3172
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3173
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3174
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3175
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3176
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
3177
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3178
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3179
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3180
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3181
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3182
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 285:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3183
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
3184
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3185
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3186
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3187
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3188
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3189
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3190
4.44M
        // GIR_Coverage, 1287,
3191
4.44M
        GIR_Done,
3192
4.44M
      // Label 172: @6365
3193
4.44M
      GIM_Try, /*On fail goto*//*Label 173*/ 6429, // Rule ID 1347 //
3194
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3195
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3196
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3197
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3198
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3199
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
3200
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3201
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3202
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3203
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3204
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3205
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 339:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3206
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
3207
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3208
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3209
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3210
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3211
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3212
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3213
4.44M
        // GIR_Coverage, 1347,
3214
4.44M
        GIR_Done,
3215
4.44M
      // Label 173: @6429
3216
4.44M
      GIM_Try, /*On fail goto*//*Label 174*/ 6481, // Rule ID 683 //
3217
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3218
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3219
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3220
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3221
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3222
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
3223
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3224
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3225
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3226
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 269:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3227
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
3228
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3229
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3230
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3231
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3232
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3233
4.44M
        // GIR_Coverage, 683,
3234
4.44M
        GIR_Done,
3235
4.44M
      // Label 174: @6481
3236
4.44M
      GIM_Try, /*On fail goto*//*Label 175*/ 6533, // Rule ID 727 //
3237
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3238
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3239
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3240
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3241
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3242
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
3243
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3244
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3245
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3246
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 327:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3247
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
3248
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3249
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3250
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3251
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3252
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3253
4.44M
        // GIR_Coverage, 727,
3254
4.44M
        GIR_Done,
3255
4.44M
      // Label 175: @6533
3256
4.44M
      GIM_Try, /*On fail goto*//*Label 176*/ 6591, // Rule ID 1275 //
3257
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3258
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3259
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3260
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3261
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3262
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3263
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3264
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3265
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3266
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3267
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3268
4.44M
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3269
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv8i8_v8i16,
3270
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3271
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3272
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3273
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3274
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3275
4.44M
        // GIR_Coverage, 1275,
3276
4.44M
        GIR_Done,
3277
4.44M
      // Label 176: @6591
3278
4.44M
      GIM_Try, /*On fail goto*//*Label 177*/ 6649, // Rule ID 1335 //
3279
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3280
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3281
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3282
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3283
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3284
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3285
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3286
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3287
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3288
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3289
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3290
4.44M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3291
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16,
3292
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3293
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3294
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3295
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3296
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3297
4.44M
        // GIR_Coverage, 1335,
3298
4.44M
        GIR_Done,
3299
4.44M
      // Label 177: @6649
3300
4.44M
      GIM_Try, /*On fail goto*//*Label 178*/ 6706, // Rule ID 3851 //
3301
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3302
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3303
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3304
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3305
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3306
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3307
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3308
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3309
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3310
4.44M
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (MLAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3311
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16,
3312
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3313
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3314
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3315
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3316
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3317
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3318
4.44M
        // GIR_Coverage, 3851,
3319
4.44M
        GIR_Done,
3320
4.44M
      // Label 178: @6706
3321
4.44M
      GIM_Try, /*On fail goto*//*Label 179*/ 6751, // Rule ID 3914 //
3322
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3323
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3324
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3325
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3326
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3327
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3328
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3329
4.44M
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3330
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16,
3331
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3332
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3333
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3334
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3335
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3336
4.44M
        // GIR_Coverage, 3914,
3337
4.44M
        GIR_Done,
3338
4.44M
      // Label 179: @6751
3339
4.44M
      GIM_Try, /*On fail goto*//*Label 180*/ 6796, // Rule ID 3932 //
3340
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3341
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3342
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3343
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3344
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3345
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3346
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3347
4.44M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3348
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16,
3349
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3350
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3351
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3352
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3353
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3354
4.44M
        // GIR_Coverage, 3932,
3355
4.44M
        GIR_Done,
3356
4.44M
      // Label 180: @6796
3357
4.44M
      GIM_Try, /*On fail goto*//*Label 181*/ 6853, // Rule ID 939 //
3358
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3359
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3360
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3361
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3362
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3363
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3364
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3365
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3366
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3367
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (MLAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3368
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16,
3369
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3370
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3371
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3372
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3373
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3374
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3375
4.44M
        // GIR_Coverage, 939,
3376
4.44M
        GIR_Done,
3377
4.44M
      // Label 181: @6853
3378
4.44M
      GIM_Try, /*On fail goto*//*Label 182*/ 6898, // Rule ID 1281 //
3379
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3380
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3381
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3382
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3383
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3384
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3385
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3386
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3387
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16,
3388
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3389
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3390
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3391
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3392
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3393
4.44M
        // GIR_Coverage, 1281,
3394
4.44M
        GIR_Done,
3395
4.44M
      // Label 182: @6898
3396
4.44M
      GIM_Try, /*On fail goto*//*Label 183*/ 6943, // Rule ID 1341 //
3397
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3398
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3399
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3400
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3401
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3402
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3403
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3404
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3405
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16,
3406
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3407
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3408
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3409
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3410
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3411
4.44M
        // GIR_Coverage, 1341,
3412
4.44M
        GIR_Done,
3413
4.44M
      // Label 183: @6943
3414
4.44M
      GIM_Try, /*On fail goto*//*Label 184*/ 6962, // Rule ID 763 //
3415
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3416
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3417
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3418
4.44M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3419
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i16,
3420
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3421
4.44M
        // GIR_Coverage, 763,
3422
4.44M
        GIR_Done,
3423
4.44M
      // Label 184: @6962
3424
4.44M
      GIM_Reject,
3425
4.44M
    // Label 159: @6963
3426
4.44M
    GIM_Reject,
3427
4.44M
    // Label 58: @6964
3428
4.44M
    GIM_Try, /*On fail goto*//*Label 185*/ 7368,
3429
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3430
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3431
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
3432
4.44M
      GIM_Try, /*On fail goto*//*Label 186*/ 7042, // Rule ID 3855 //
3433
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3434
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3435
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3436
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3437
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3438
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3439
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3440
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3441
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3442
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3443
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3444
4.44M
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 268:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3445
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
3446
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3447
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3448
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3449
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3450
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3451
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3452
4.44M
        // GIR_Coverage, 3855,
3453
4.44M
        GIR_Done,
3454
4.44M
      // Label 186: @7042
3455
4.44M
      GIM_Try, /*On fail goto*//*Label 187*/ 7106, // Rule ID 3861 //
3456
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3457
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3458
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3459
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3460
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3461
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3462
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3463
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3464
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3465
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3466
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3467
4.44M
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 326:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3468
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
3469
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3470
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3471
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3472
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3473
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3474
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3475
4.44M
        // GIR_Coverage, 3861,
3476
4.44M
        GIR_Done,
3477
4.44M
      // Label 187: @7106
3478
4.44M
      GIM_Try, /*On fail goto*//*Label 188*/ 7170, // Rule ID 957 //
3479
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3480
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3481
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3482
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3483
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3484
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3485
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3486
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3487
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3488
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3489
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3490
4.44M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 268:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3491
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
3492
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3493
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3494
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3495
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3496
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3497
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3498
4.44M
        // GIR_Coverage, 957,
3499
4.44M
        GIR_Done,
3500
4.44M
      // Label 188: @7170
3501
4.44M
      GIM_Try, /*On fail goto*//*Label 189*/ 7234, // Rule ID 1068 //
3502
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3503
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3504
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3505
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3506
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3507
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3508
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3509
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3510
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3511
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3512
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3513
4.44M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 326:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3514
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
3515
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3516
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3517
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3518
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3519
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3520
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3521
4.44M
        // GIR_Coverage, 1068,
3522
4.44M
        GIR_Done,
3523
4.44M
      // Label 189: @7234
3524
4.44M
      GIM_Try, /*On fail goto*//*Label 190*/ 7291, // Rule ID 3849 //
3525
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3526
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3527
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3528
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3529
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3530
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3531
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3532
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3533
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3534
4.44M
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (MLAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3535
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8,
3536
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3537
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3538
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3539
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3540
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3541
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3542
4.44M
        // GIR_Coverage, 3849,
3543
4.44M
        GIR_Done,
3544
4.44M
      // Label 190: @7291
3545
4.44M
      GIM_Try, /*On fail goto*//*Label 191*/ 7348, // Rule ID 937 //
3546
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3547
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3548
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3549
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3550
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3551
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3552
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3553
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3554
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3555
4.44M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (MLAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3556
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8,
3557
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3558
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3559
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3560
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3561
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3562
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3563
4.44M
        // GIR_Coverage, 937,
3564
4.44M
        GIR_Done,
3565
4.44M
      // Label 191: @7348
3566
4.44M
      GIM_Try, /*On fail goto*//*Label 192*/ 7367, // Rule ID 761 //
3567
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3568
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3569
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3570
4.44M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3571
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv16i8,
3572
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3573
4.44M
        // GIR_Coverage, 761,
3574
4.44M
        GIR_Done,
3575
4.44M
      // Label 192: @7367
3576
4.44M
      GIM_Reject,
3577
4.44M
    // Label 185: @7368
3578
4.44M
    GIM_Reject,
3579
4.44M
    // Label 59: @7369
3580
4.44M
    GIM_Reject,
3581
4.44M
    // Label 1: @7370
3582
4.44M
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 202*/ 9950,
3583
4.44M
    /*GILLT_s32*//*Label 193*/ 7386,
3584
4.44M
    /*GILLT_s64*//*Label 194*/ 7506, 0,
3585
4.44M
    /*GILLT_v2s32*//*Label 195*/ 8377,
3586
4.44M
    /*GILLT_v2s64*//*Label 196*/ 8465,
3587
4.44M
    /*GILLT_v4s16*//*Label 197*/ 8834,
3588
4.44M
    /*GILLT_v4s32*//*Label 198*/ 8922,
3589
4.44M
    /*GILLT_v8s8*//*Label 199*/ 9348,
3590
4.44M
    /*GILLT_v8s16*//*Label 200*/ 9436,
3591
4.44M
    /*GILLT_v16s8*//*Label 201*/ 9862,
3592
4.44M
    // Label 193: @7386
3593
4.44M
    GIM_Try, /*On fail goto*//*Label 203*/ 7505,
3594
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3595
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3596
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
3597
4.44M
      GIM_Try, /*On fail goto*//*Label 204*/ 7454, // Rule ID 1871 //
3598
4.44M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3599
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3600
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3601
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3602
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3603
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3604
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
3605
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3606
4.44M
        // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
3607
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
3608
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3609
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3610
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3611
4.44M
        GIR_AddRegister, /*InsnID*/0, AArch64::WZR,
3612
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3613
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3614
4.44M
        // GIR_Coverage, 1871,
3615
4.44M
        GIR_Done,
3616
4.44M
      // Label 204: @7454
3617
4.44M
      GIM_Try, /*On fail goto*//*Label 205*/ 7484, // Rule ID 1837 //
3618
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
3619
4.44M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
3620
4.44M
        // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
3621
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri,
3622
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3623
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3624
4.44M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
3625
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3626
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3627
4.44M
        // GIR_Coverage, 1837,
3628
4.44M
        GIR_Done,
3629
4.44M
      // Label 205: @7484
3630
4.44M
      GIM_Try, /*On fail goto*//*Label 206*/ 7504, // Rule ID 1839 //
3631
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3632
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
3633
4.44M
        // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SUBSWrr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
3634
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSWrr,
3635
4.44M
        GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV,
3636
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3637
4.44M
        // GIR_Coverage, 1839,
3638
4.44M
        GIR_Done,
3639
4.44M
      // Label 206: @7504
3640
4.44M
      GIM_Reject,
3641
4.44M
    // Label 203: @7505
3642
4.44M
    GIM_Reject,
3643
4.44M
    // Label 194: @7506
3644
4.44M
    GIM_Try, /*On fail goto*//*Label 207*/ 8376,
3645
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3646
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3647
4.44M
      GIM_Try, /*On fail goto*//*Label 208*/ 7611, // Rule ID 1882 //
3648
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3649
4.44M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3650
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3651
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3652
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3653
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3654
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3655
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3656
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3657
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3658
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3659
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3660
4.44M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
3661
4.44M
        // MIs[3] Operand 1
3662
4.44M
        // No operand predicates
3663
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3664
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3665
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3666
4.44M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
3667
4.44M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3668
4.44M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3669
4.44M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3670
4.44M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3671
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3672
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3673
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3674
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3675
4.44M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3676
4.44M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3677
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3678
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3679
4.44M
        // GIR_Coverage, 1882,
3680
4.44M
        GIR_Done,
3681
4.44M
      // Label 208: @7611
3682
4.44M
      GIM_Try, /*On fail goto*//*Label 209*/ 7706, // Rule ID 1883 //
3683
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3684
4.44M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3685
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3686
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3687
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3688
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3689
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3690
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3691
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3692
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3693
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3694
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3695
4.44M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
3696
4.44M
        // MIs[3] Operand 1
3697
4.44M
        // No operand predicates
3698
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3699
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3700
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3701
4.44M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
3702
4.44M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3703
4.44M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3704
4.44M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3705
4.44M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3706
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3707
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3708
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3709
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3710
4.44M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3711
4.44M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3712
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3713
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3714
4.44M
        // GIR_Coverage, 1883,
3715
4.44M
        GIR_Done,
3716
4.44M
      // Label 209: @7706
3717
4.44M
      GIM_Try, /*On fail goto*//*Label 210*/ 7790, // Rule ID 1877 //
3718
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3719
4.44M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3720
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3721
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3722
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3723
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3724
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3725
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3726
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3727
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3728
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3729
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
3730
4.44M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3731
4.44M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3732
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3733
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3734
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3735
4.44M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
3736
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3737
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3738
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3739
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3740
4.44M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3741
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3742
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3743
4.44M
        // GIR_Coverage, 1877,
3744
4.44M
        GIR_Done,
3745
4.44M
      // Label 210: @7790
3746
4.44M
      GIM_Try, /*On fail goto*//*Label 211*/ 7874, // Rule ID 1878 //
3747
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3748
4.44M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3749
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3750
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3751
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3752
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3753
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3754
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3755
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3756
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3757
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3758
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
3759
4.44M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3760
4.44M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3761
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3762
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3763
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3764
4.44M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
3765
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3766
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3767
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3768
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3769
4.44M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3770
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3771
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3772
4.44M
        // GIR_Coverage, 1878,
3773
4.44M
        GIR_Done,
3774
4.44M
      // Label 211: @7874
3775
4.44M
      GIM_Try, /*On fail goto*//*Label 212*/ 7970, // Rule ID 1888 //
3776
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3777
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3778
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3779
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3780
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3781
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3782
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3783
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3784
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3785
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3786
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3787
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3788
4.44M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
3789
4.44M
        // MIs[3] Operand 1
3790
4.44M
        // No operand predicates
3791
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3792
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3793
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3794
4.44M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
3795
4.44M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3796
4.44M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3797
4.44M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3798
4.44M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3799
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3800
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3801
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3802
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3803
4.44M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3804
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3805
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3806
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3807
4.44M
        // GIR_Coverage, 1888,
3808
4.44M
        GIR_Done,
3809
4.44M
      // Label 212: @7970
3810
4.44M
      GIM_Try, /*On fail goto*//*Label 213*/ 8066, // Rule ID 1889 //
3811
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3812
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3813
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3814
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3815
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3816
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3817
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3818
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3819
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3820
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3821
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3822
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3823
4.44M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
3824
4.44M
        // MIs[3] Operand 1
3825
4.44M
        // No operand predicates
3826
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3827
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3828
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3829
4.44M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
3830
4.44M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3831
4.44M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3832
4.44M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3833
4.44M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3834
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3835
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3836
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3837
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3838
4.44M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3839
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3840
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3841
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3842
4.44M
        // GIR_Coverage, 1889,
3843
4.44M
        GIR_Done,
3844
4.44M
      // Label 213: @8066
3845
4.44M
      GIM_Try, /*On fail goto*//*Label 214*/ 8151, // Rule ID 66 //
3846
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3847
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3848
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3849
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3850
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3851
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3852
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3853
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3854
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3855
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3856
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3857
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
3858
4.44M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3859
4.44M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3860
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3861
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3862
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3863
4.44M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
3864
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3865
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3866
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3867
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3868
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3869
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3870
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3871
4.44M
        // GIR_Coverage, 66,
3872
4.44M
        GIR_Done,
3873
4.44M
      // Label 214: @8151
3874
4.44M
      GIM_Try, /*On fail goto*//*Label 215*/ 8236, // Rule ID 68 //
3875
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3876
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3877
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3878
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3879
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3880
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3881
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3882
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3883
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3884
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3885
4.44M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3886
4.44M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
3887
4.44M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3888
4.44M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3889
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3890
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3891
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3892
4.44M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
3893
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3894
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3895
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3896
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3897
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3898
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3899
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3900
4.44M
        // GIR_Coverage, 68,
3901
4.44M
        GIR_Done,
3902
4.44M
      // Label 215: @8236
3903
4.44M
      GIM_Try, /*On fail goto*//*Label 216*/ 8294, // Rule ID 1872 //
3904
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3905
4.44M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3906
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3907
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3908
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3909
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3910
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3911
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
3912
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3913
4.44M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
3914
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
3915
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3916
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3917
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3918
4.44M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3919
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3920
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3921
4.44M
        // GIR_Coverage, 1872,
3922
4.44M
        GIR_Done,
3923
4.44M
      // Label 216: @8294
3924
4.44M
      GIM_Try, /*On fail goto*//*Label 217*/ 8328, // Rule ID 1838 //
3925
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3926
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
3927
4.44M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
3928
4.44M
        // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
3929
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri,
3930
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3931
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3932
4.44M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
3933
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3934
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3935
4.44M
        // GIR_Coverage, 1838,
3936
4.44M
        GIR_Done,
3937
4.44M
      // Label 217: @8328
3938
4.44M
      GIM_Try, /*On fail goto*//*Label 218*/ 8351, // Rule ID 1222 //
3939
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3940
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
3941
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3942
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3943
4.44M
        // (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
3944
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv1i64,
3945
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3946
4.44M
        // GIR_Coverage, 1222,
3947
4.44M
        GIR_Done,
3948
4.44M
      // Label 218: @8351
3949
4.44M
      GIM_Try, /*On fail goto*//*Label 219*/ 8375, // Rule ID 1840 //
3950
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3951
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3952
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
3953
4.44M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SUBSXrr:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
3954
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSXrr,
3955
4.44M
        GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV,
3956
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3957
4.44M
        // GIR_Coverage, 1840,
3958
4.44M
        GIR_Done,
3959
4.44M
      // Label 219: @8375
3960
4.44M
      GIM_Reject,
3961
4.44M
    // Label 207: @8376
3962
4.44M
    GIM_Reject,
3963
4.44M
    // Label 195: @8377
3964
4.44M
    GIM_Try, /*On fail goto*//*Label 220*/ 8464,
3965
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
3966
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
3967
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
3968
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3969
4.44M
      GIM_Try, /*On fail goto*//*Label 221*/ 8448, // Rule ID 946 //
3970
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3971
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3972
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3973
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3974
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3975
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3976
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3977
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3978
4.44M
        // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (MLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3979
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv2i32,
3980
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3981
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3982
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3983
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3984
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
3985
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3986
4.44M
        // GIR_Coverage, 946,
3987
4.44M
        GIR_Done,
3988
4.44M
      // Label 221: @8448
3989
4.44M
      GIM_Try, /*On fail goto*//*Label 222*/ 8463, // Rule ID 1064 //
3990
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
3991
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3992
4.44M
        // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3993
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i32,
3994
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3995
4.44M
        // GIR_Coverage, 1064,
3996
4.44M
        GIR_Done,
3997
4.44M
      // Label 222: @8463
3998
4.44M
      GIM_Reject,
3999
4.44M
    // Label 220: @8464
4000
4.44M
    GIM_Reject,
4001
4.44M
    // Label 196: @8465
4002
4.44M
    GIM_Try, /*On fail goto*//*Label 223*/ 8833,
4003
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4004
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4005
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4006
4.44M
      GIM_Try, /*On fail goto*//*Label 224*/ 8543, // Rule ID 1297 //
4007
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4008
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4009
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4010
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4011
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4012
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4013
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4014
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
4015
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4016
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4017
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4018
4.44M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 285:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4019
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv2i32_v2i64,
4020
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4021
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4022
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4023
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4024
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4025
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4026
4.44M
        // GIR_Coverage, 1297,
4027
4.44M
        GIR_Done,
4028
4.44M
      // Label 224: @8543
4029
4.44M
      GIM_Try, /*On fail goto*//*Label 225*/ 8607, // Rule ID 1357 //
4030
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4031
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4032
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4033
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4034
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4035
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4036
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4037
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
4038
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4039
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4040
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4041
4.44M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 339:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4042
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv2i32_v2i64,
4043
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4044
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4045
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4046
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4047
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4048
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4049
4.44M
        // GIR_Coverage, 1357,
4050
4.44M
        GIR_Done,
4051
4.44M
      // Label 225: @8607
4052
4.44M
      GIM_Try, /*On fail goto*//*Label 226*/ 8665, // Rule ID 1321 //
4053
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4054
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4055
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4056
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4057
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4058
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4059
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4060
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4061
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4062
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4063
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4064
4.44M
        // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4065
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv2i32_v2i64,
4066
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4067
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4068
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4069
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4070
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4071
4.44M
        // GIR_Coverage, 1321,
4072
4.44M
        GIR_Done,
4073
4.44M
      // Label 226: @8665
4074
4.44M
      GIM_Try, /*On fail goto*//*Label 227*/ 8723, // Rule ID 1369 //
4075
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4076
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4077
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4078
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4079
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4080
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4081
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4082
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4083
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4084
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4085
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4086
4.44M
        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4087
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64,
4088
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4089
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4090
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4091
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4092
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4093
4.44M
        // GIR_Coverage, 1369,
4094
4.44M
        GIR_Done,
4095
4.44M
      // Label 227: @8723
4096
4.44M
      GIM_Try, /*On fail goto*//*Label 228*/ 8768, // Rule ID 1327 //
4097
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4098
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4099
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4100
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4101
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4102
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4103
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4104
4.44M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4105
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv2i32_v2i64,
4106
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4107
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4108
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4109
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4110
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4111
4.44M
        // GIR_Coverage, 1327,
4112
4.44M
        GIR_Done,
4113
4.44M
      // Label 228: @8768
4114
4.44M
      GIM_Try, /*On fail goto*//*Label 229*/ 8813, // Rule ID 1375 //
4115
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4116
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4117
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4118
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4119
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4120
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4121
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4122
4.44M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4123
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv2i32_v2i64,
4124
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4125
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4126
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4127
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4128
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4129
4.44M
        // GIR_Coverage, 1375,
4130
4.44M
        GIR_Done,
4131
4.44M
      // Label 229: @8813
4132
4.44M
      GIM_Try, /*On fail goto*//*Label 230*/ 8832, // Rule ID 1066 //
4133
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4134
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4135
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4136
4.44M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
4137
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i64,
4138
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4139
4.44M
        // GIR_Coverage, 1066,
4140
4.44M
        GIR_Done,
4141
4.44M
      // Label 230: @8832
4142
4.44M
      GIM_Reject,
4143
4.44M
    // Label 223: @8833
4144
4.44M
    GIM_Reject,
4145
4.44M
    // Label 197: @8834
4146
4.44M
    GIM_Try, /*On fail goto*//*Label 231*/ 8921,
4147
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4148
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4149
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4150
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4151
4.44M
      GIM_Try, /*On fail goto*//*Label 232*/ 8905, // Rule ID 944 //
4152
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4153
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4154
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4155
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4156
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4157
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4158
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4159
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4160
4.44M
        // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (MLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4161
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i16,
4162
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4163
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4164
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4165
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4166
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4167
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4168
4.44M
        // GIR_Coverage, 944,
4169
4.44M
        GIR_Done,
4170
4.44M
      // Label 232: @8905
4171
4.44M
      GIM_Try, /*On fail goto*//*Label 233*/ 8920, // Rule ID 1062 //
4172
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4173
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4174
4.44M
        // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4175
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i16,
4176
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4177
4.44M
        // GIR_Coverage, 1062,
4178
4.44M
        GIR_Done,
4179
4.44M
      // Label 233: @8920
4180
4.44M
      GIM_Reject,
4181
4.44M
    // Label 231: @8921
4182
4.44M
    GIM_Reject,
4183
4.44M
    // Label 198: @8922
4184
4.44M
    GIM_Try, /*On fail goto*//*Label 234*/ 9347,
4185
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4186
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4187
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4188
4.44M
      GIM_Try, /*On fail goto*//*Label 235*/ 9000, // Rule ID 1295 //
4189
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4190
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4191
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4192
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4193
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4194
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4195
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4196
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4197
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4198
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4199
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4200
4.44M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 285:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4201
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv4i16_v4i32,
4202
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4203
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4204
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4205
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4206
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4207
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4208
4.44M
        // GIR_Coverage, 1295,
4209
4.44M
        GIR_Done,
4210
4.44M
      // Label 235: @9000
4211
4.44M
      GIM_Try, /*On fail goto*//*Label 236*/ 9064, // Rule ID 1355 //
4212
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4213
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4214
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4215
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4216
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4217
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4218
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4219
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4220
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4221
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4222
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4223
4.44M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 339:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4224
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv4i16_v4i32,
4225
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4226
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4227
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4228
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4229
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4230
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4231
4.44M
        // GIR_Coverage, 1355,
4232
4.44M
        GIR_Done,
4233
4.44M
      // Label 236: @9064
4234
4.44M
      GIM_Try, /*On fail goto*//*Label 237*/ 9122, // Rule ID 1319 //
4235
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4236
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4237
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4238
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4239
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4240
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4241
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4242
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4243
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4244
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4245
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4246
4.44M
        // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4247
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv4i16_v4i32,
4248
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4249
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4250
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4251
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4252
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4253
4.44M
        // GIR_Coverage, 1319,
4254
4.44M
        GIR_Done,
4255
4.44M
      // Label 237: @9122
4256
4.44M
      GIM_Try, /*On fail goto*//*Label 238*/ 9180, // Rule ID 1367 //
4257
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4258
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4259
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4260
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4261
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4262
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4263
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4264
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4265
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4266
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4267
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4268
4.44M
        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4269
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32,
4270
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4271
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4272
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4273
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4274
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4275
4.44M
        // GIR_Coverage, 1367,
4276
4.44M
        GIR_Done,
4277
4.44M
      // Label 238: @9180
4278
4.44M
      GIM_Try, /*On fail goto*//*Label 239*/ 9237, // Rule ID 947 //
4279
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4280
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4281
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4282
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4283
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4284
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4285
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4286
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4287
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4288
4.44M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (MLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4289
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i32,
4290
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4291
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4292
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4293
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4294
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4295
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4296
4.44M
        // GIR_Coverage, 947,
4297
4.44M
        GIR_Done,
4298
4.44M
      // Label 239: @9237
4299
4.44M
      GIM_Try, /*On fail goto*//*Label 240*/ 9282, // Rule ID 1325 //
4300
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4301
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4302
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4303
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4304
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4305
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4306
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4307
4.44M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4308
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv4i16_v4i32,
4309
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4310
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4311
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4312
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4313
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4314
4.44M
        // GIR_Coverage, 1325,
4315
4.44M
        GIR_Done,
4316
4.44M
      // Label 240: @9282
4317
4.44M
      GIM_Try, /*On fail goto*//*Label 241*/ 9327, // Rule ID 1373 //
4318
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4319
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4320
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4321
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4322
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4323
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4324
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4325
4.44M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4326
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv4i16_v4i32,
4327
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4328
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4329
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4330
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4331
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4332
4.44M
        // GIR_Coverage, 1373,
4333
4.44M
        GIR_Done,
4334
4.44M
      // Label 241: @9327
4335
4.44M
      GIM_Try, /*On fail goto*//*Label 242*/ 9346, // Rule ID 1065 //
4336
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4337
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4338
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4339
4.44M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4340
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i32,
4341
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4342
4.44M
        // GIR_Coverage, 1065,
4343
4.44M
        GIR_Done,
4344
4.44M
      // Label 242: @9346
4345
4.44M
      GIM_Reject,
4346
4.44M
    // Label 234: @9347
4347
4.44M
    GIM_Reject,
4348
4.44M
    // Label 199: @9348
4349
4.44M
    GIM_Try, /*On fail goto*//*Label 243*/ 9435,
4350
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4351
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4352
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4353
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4354
4.44M
      GIM_Try, /*On fail goto*//*Label 244*/ 9419, // Rule ID 942 //
4355
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4356
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4357
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4358
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4359
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4360
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4361
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4362
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4363
4.44M
        // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (MLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4364
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i8,
4365
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4366
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4367
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4368
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4369
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4370
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4371
4.44M
        // GIR_Coverage, 942,
4372
4.44M
        GIR_Done,
4373
4.44M
      // Label 244: @9419
4374
4.44M
      GIM_Try, /*On fail goto*//*Label 245*/ 9434, // Rule ID 1060 //
4375
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4376
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4377
4.44M
        // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4378
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i8,
4379
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4380
4.44M
        // GIR_Coverage, 1060,
4381
4.44M
        GIR_Done,
4382
4.44M
      // Label 245: @9434
4383
4.44M
      GIM_Reject,
4384
4.44M
    // Label 243: @9435
4385
4.44M
    GIM_Reject,
4386
4.44M
    // Label 200: @9436
4387
4.44M
    GIM_Try, /*On fail goto*//*Label 246*/ 9861,
4388
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4389
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4390
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4391
4.44M
      GIM_Try, /*On fail goto*//*Label 247*/ 9514, // Rule ID 1293 //
4392
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4393
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4394
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4395
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4396
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4397
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4398
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4399
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
4400
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4401
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4402
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4403
4.44M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 285:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4404
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv8i8_v8i16,
4405
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4406
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4407
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4408
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4409
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4410
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4411
4.44M
        // GIR_Coverage, 1293,
4412
4.44M
        GIR_Done,
4413
4.44M
      // Label 247: @9514
4414
4.44M
      GIM_Try, /*On fail goto*//*Label 248*/ 9578, // Rule ID 1353 //
4415
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4416
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4417
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4418
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4419
4.44M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4420
4.44M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4421
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4422
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
4423
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4424
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4425
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4426
4.44M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 339:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4427
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv8i8_v8i16,
4428
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4429
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4430
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4431
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4432
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4433
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4434
4.44M
        // GIR_Coverage, 1353,
4435
4.44M
        GIR_Done,
4436
4.44M
      // Label 248: @9578
4437
4.44M
      GIM_Try, /*On fail goto*//*Label 249*/ 9636, // Rule ID 1317 //
4438
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4439
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4440
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4441
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4442
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4443
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4444
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4445
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4446
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4447
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4448
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4449
4.44M
        // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4450
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv8i8_v8i16,
4451
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4452
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4453
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4454
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4455
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4456
4.44M
        // GIR_Coverage, 1317,
4457
4.44M
        GIR_Done,
4458
4.44M
      // Label 249: @9636
4459
4.44M
      GIM_Try, /*On fail goto*//*Label 250*/ 9694, // Rule ID 1365 //
4460
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4461
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4462
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4463
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4464
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4465
4.44M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4466
4.44M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4467
4.44M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4468
4.44M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4469
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4470
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4471
4.44M
        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4472
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16,
4473
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4474
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4475
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4476
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4477
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4478
4.44M
        // GIR_Coverage, 1365,
4479
4.44M
        GIR_Done,
4480
4.44M
      // Label 250: @9694
4481
4.44M
      GIM_Try, /*On fail goto*//*Label 251*/ 9751, // Rule ID 945 //
4482
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4483
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4484
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4485
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4486
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4487
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4488
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4489
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4490
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4491
4.44M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (MLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
4492
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i16,
4493
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4494
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4495
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4496
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4497
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4498
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4499
4.44M
        // GIR_Coverage, 945,
4500
4.44M
        GIR_Done,
4501
4.44M
      // Label 251: @9751
4502
4.44M
      GIM_Try, /*On fail goto*//*Label 252*/ 9796, // Rule ID 1323 //
4503
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4504
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4505
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4506
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4507
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4508
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4509
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4510
4.44M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4511
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv8i8_v8i16,
4512
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4513
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4514
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4515
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4516
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4517
4.44M
        // GIR_Coverage, 1323,
4518
4.44M
        GIR_Done,
4519
4.44M
      // Label 252: @9796
4520
4.44M
      GIM_Try, /*On fail goto*//*Label 253*/ 9841, // Rule ID 1371 //
4521
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4522
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4523
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4524
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4525
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4526
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4527
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4528
4.44M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4529
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv8i8_v8i16,
4530
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4531
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4532
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4533
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4534
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4535
4.44M
        // GIR_Coverage, 1371,
4536
4.44M
        GIR_Done,
4537
4.44M
      // Label 253: @9841
4538
4.44M
      GIM_Try, /*On fail goto*//*Label 254*/ 9860, // Rule ID 1063 //
4539
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4540
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4541
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4542
4.44M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
4543
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i16,
4544
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4545
4.44M
        // GIR_Coverage, 1063,
4546
4.44M
        GIR_Done,
4547
4.44M
      // Label 254: @9860
4548
4.44M
      GIM_Reject,
4549
4.44M
    // Label 246: @9861
4550
4.44M
    GIM_Reject,
4551
4.44M
    // Label 201: @9862
4552
4.44M
    GIM_Try, /*On fail goto*//*Label 255*/ 9949,
4553
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4554
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
4555
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4556
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4557
4.44M
      GIM_Try, /*On fail goto*//*Label 256*/ 9933, // Rule ID 943 //
4558
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4559
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4560
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4561
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
4562
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
4563
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4564
4.44M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4565
4.44M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4566
4.44M
        // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (MLSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
4567
4.44M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv16i8,
4568
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4569
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4570
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4571
4.44M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4572
4.44M
        GIR_EraseFromParent, /*InsnID*/0,
4573
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4574
4.44M
        // GIR_Coverage, 943,
4575
4.44M
        GIR_Done,
4576
4.44M
      // Label 256: @9933
4577
4.44M
      GIM_Try, /*On fail goto*//*Label 257*/ 9948, // Rule ID 1061 //
4578
4.44M
        GIM_CheckFeatures, GIFBS_HasNEON,
4579
4.44M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4580
4.44M
        // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
4581
4.44M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv16i8,
4582
4.44M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4583
4.44M
        // GIR_Coverage, 1061,
4584
4.44M
        GIR_Done,
4585
4.44M
      // Label 257: @9948
4586
4.44M
      GIM_Reject,
4587
4.44M
    // Label 255: @9949
4588
4.44M
    GIM_Reject,
4589
4.44M
    // Label 202: @9950
4590
4.44M
    GIM_Reject,
4591
4.44M
    // Label 2: @9951
4592
4.44M
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 266*/ 10731,
4593
4.44M
    /*GILLT_s32*//*Label 258*/ 9967,
4594
4.44M
    /*GILLT_s64*//*Label 259*/ 10124, 0,
4595
4.44M
    /*GILLT_v2s32*//*Label 260*/ 10539, 0,
4596
4.44M
    /*GILLT_v4s16*//*Label 261*/ 10571,
4597
4.44M
    /*GILLT_v4s32*//*Label 262*/ 10603,
4598
4.44M
    /*GILLT_v8s8*//*Label 263*/ 10635,
4599
4.44M
    /*GILLT_v8s16*//*Label 264*/ 10667,
4600
4.44M
    /*GILLT_v16s8*//*Label 265*/ 10699,
4601
4.44M
    // Label 258: @9967
4602
4.44M
    GIM_Try, /*On fail goto*//*Label 267*/ 10123,
4603
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4604
4.44M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4605
4.44M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
4606
4.44M
      GIM_Try, /*On fail goto*//*Label 268*/ 10035, // Rule ID 1873 //
4607
4.44M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4608
4.44M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4609
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4610
4.44M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4611
4.44M