Coverage Report

Created: 2018-12-14 11:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AArch64/AArch64GenGlobalISel.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the AArch64 target                         *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 19;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static AArch64InstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
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28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(1),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_HasFPARMv8Bit = 5,
37
  Feature_HasNEONBit = 2,
38
  Feature_HasSHA2Bit = 8,
39
  Feature_HasAESBit = 7,
40
  Feature_HasDotProdBit = 0,
41
  Feature_HasCRCBit = 3,
42
  Feature_HasLSEBit = 9,
43
  Feature_HasRDMBit = 6,
44
  Feature_HasPerfMonBit = 10,
45
  Feature_HasFullFP16Bit = 4,
46
  Feature_HasFP16FMLBit = 1,
47
  Feature_HasFuseAESBit = 15,
48
  Feature_IsLEBit = 11,
49
  Feature_IsBEBit = 16,
50
  Feature_UseAlternateSExtLoadCVTF32Bit = 14,
51
  Feature_NotForCodeSizeBit = 13,
52
  Feature_UseSTRQroBit = 12,
53
  Feature_UseBTIBit = 18,
54
  Feature_NotUseBTIBit = 17,
55
};
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57
PredicateBitset AArch64InstructionSelector::
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8.70k
computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const {
59
8.70k
  PredicateBitset Features;
60
8.70k
  if (Subtarget->hasFPARMv8())
61
8.69k
    Features[Feature_HasFPARMv8Bit] = 1;
62
8.70k
  if (Subtarget->hasNEON())
63
8.68k
    Features[Feature_HasNEONBit] = 1;
64
8.70k
  if (Subtarget->hasSHA2())
65
8.70k
    Features[Feature_HasSHA2Bit] = 1;
66
8.70k
  if (Subtarget->hasAES())
67
8.70k
    Features[Feature_HasAESBit] = 1;
68
8.70k
  if (Subtarget->hasDotProd())
69
11
    Features[Feature_HasDotProdBit] = 1;
70
8.70k
  if (Subtarget->hasCRC())
71
173
    Features[Feature_HasCRCBit] = 1;
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8.70k
  if (Subtarget->hasLSE())
73
35
    Features[Feature_HasLSEBit] = 1;
74
8.70k
  if (Subtarget->hasRDM())
75
40
    Features[Feature_HasRDMBit] = 1;
76
8.70k
  if (Subtarget->hasPerfMon())
77
8.69k
    Features[Feature_HasPerfMonBit] = 1;
78
8.70k
  if (Subtarget->hasFullFP16())
79
23
    Features[Feature_HasFullFP16Bit] = 1;
80
8.70k
  if (Subtarget->hasFP16FML())
81
3
    Features[Feature_HasFP16FMLBit] = 1;
82
8.70k
  if (Subtarget->hasFuseAES())
83
8.66k
    Features[Feature_HasFuseAESBit] = 1;
84
8.70k
  if (Subtarget->isLittleEndian())
85
8.67k
    Features[Feature_IsLEBit] = 1;
86
8.70k
  if (!Subtarget->isLittleEndian())
87
30
    Features[Feature_IsBEBit] = 1;
88
8.70k
  if (Subtarget->useAlternateSExtLoadCVTF32Pattern())
89
7.14k
    Features[Feature_UseAlternateSExtLoadCVTF32Bit] = 1;
90
8.70k
  return Features;
91
8.70k
}
92
93
PredicateBitset AArch64InstructionSelector::
94
4.38M
computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const {
95
4.38M
  PredicateBitset Features;
96
4.38M
  if (!MF->getFunction().optForSize())
97
4.38M
    Features[Feature_NotForCodeSizeBit] = 1;
98
4.38M
  if (!Subtarget->isSTRQroSlow() || 
MF->getFunction().optForSize()0
)
99
4.38M
    Features[Feature_UseSTRQroBit] = 1;
100
4.38M
  if ( MF->getFunction().hasFnAttribute("branch-target-enforcement") )
101
0
    Features[Feature_UseBTIBit] = 1;
102
4.38M
  if ( !MF->getFunction().hasFnAttribute("branch-target-enforcement") )
103
4.38M
    Features[Feature_NotUseBTIBit] = 1;
104
4.38M
  return Features;
105
4.38M
}
106
107
// LLT Objects.
108
enum {
109
  GILLT_s16,
110
  GILLT_s32,
111
  GILLT_s64,
112
  GILLT_s128,
113
  GILLT_v2s32,
114
  GILLT_v2s64,
115
  GILLT_v4s16,
116
  GILLT_v4s32,
117
  GILLT_v8s8,
118
  GILLT_v8s16,
119
  GILLT_v16s8,
120
};
121
const static size_t NumTypeObjects = 11;
122
const static LLT TypeObjects[] = {
123
  LLT::scalar(16),
124
  LLT::scalar(32),
125
  LLT::scalar(64),
126
  LLT::scalar(128),
127
  LLT::vector(2, 32),
128
  LLT::vector(2, 64),
129
  LLT::vector(4, 16),
130
  LLT::vector(4, 32),
131
  LLT::vector(8, 8),
132
  LLT::vector(8, 16),
133
  LLT::vector(16, 8),
134
};
135
136
// Feature bitsets.
137
enum {
138
  GIFBS_Invalid,
139
  GIFBS_HasAES,
140
  GIFBS_HasCRC,
141
  GIFBS_HasDotProd,
142
  GIFBS_HasFPARMv8,
143
  GIFBS_HasFullFP16,
144
  GIFBS_HasFuseAES,
145
  GIFBS_HasLSE,
146
  GIFBS_HasNEON,
147
  GIFBS_HasRDM,
148
  GIFBS_HasSHA2,
149
  GIFBS_IsBE,
150
  GIFBS_IsLE,
151
  GIFBS_HasFP16FML_HasNEON,
152
  GIFBS_HasFullFP16_HasNEON,
153
  GIFBS_HasNEON_HasRDM,
154
};
155
const static PredicateBitset FeatureBitsets[] {
156
  {}, // GIFBS_Invalid
157
  {Feature_HasAESBit, },
158
  {Feature_HasCRCBit, },
159
  {Feature_HasDotProdBit, },
160
  {Feature_HasFPARMv8Bit, },
161
  {Feature_HasFullFP16Bit, },
162
  {Feature_HasFuseAESBit, },
163
  {Feature_HasLSEBit, },
164
  {Feature_HasNEONBit, },
165
  {Feature_HasRDMBit, },
166
  {Feature_HasSHA2Bit, },
167
  {Feature_IsBEBit, },
168
  {Feature_IsLEBit, },
169
  {Feature_HasFP16FMLBit, Feature_HasNEONBit, },
170
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
171
  {Feature_HasNEONBit, Feature_HasRDMBit, },
172
};
173
174
// ComplexPattern predicates.
175
enum {
176
  GICP_Invalid,
177
  GICP_gi_addsub_shifted_imm32,
178
  GICP_gi_addsub_shifted_imm64,
179
  GICP_gi_am_indexed128,
180
  GICP_gi_am_indexed16,
181
  GICP_gi_am_indexed32,
182
  GICP_gi_am_indexed64,
183
  GICP_gi_am_indexed8,
184
  GICP_gi_am_unscaled128,
185
  GICP_gi_am_unscaled16,
186
  GICP_gi_am_unscaled32,
187
  GICP_gi_am_unscaled64,
188
  GICP_gi_am_unscaled8,
189
};
190
// See constructor for table contents
191
192
// PatFrag predicates.
193
enum {
194
  GIPFP_I64_Predicate_VectorIndex1 = GIPFP_I64_Invalid + 1,
195
  GIPFP_I64_Predicate_VectorIndexB,
196
  GIPFP_I64_Predicate_VectorIndexD,
197
  GIPFP_I64_Predicate_VectorIndexH,
198
  GIPFP_I64_Predicate_VectorIndexS,
199
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16,
200
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32,
201
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64,
202
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8,
203
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16,
204
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32,
205
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64,
206
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8,
207
  GIPFP_I64_Predicate_i64imm_32bit,
208
  GIPFP_I64_Predicate_imm0_1,
209
  GIPFP_I64_Predicate_imm0_127,
210
  GIPFP_I64_Predicate_imm0_15,
211
  GIPFP_I64_Predicate_imm0_255,
212
  GIPFP_I64_Predicate_imm0_31,
213
  GIPFP_I64_Predicate_imm0_63,
214
  GIPFP_I64_Predicate_imm0_65535,
215
  GIPFP_I64_Predicate_imm0_7,
216
  GIPFP_I64_Predicate_imm32_0_15,
217
  GIPFP_I64_Predicate_imm32_0_31,
218
  GIPFP_I64_Predicate_maski16_or_more,
219
  GIPFP_I64_Predicate_maski8_or_more,
220
  GIPFP_I64_Predicate_s64imm_32bit,
221
  GIPFP_I64_Predicate_simm4s1,
222
  GIPFP_I64_Predicate_simm4s16,
223
  GIPFP_I64_Predicate_simm4s2,
224
  GIPFP_I64_Predicate_simm4s3,
225
  GIPFP_I64_Predicate_simm4s4,
226
  GIPFP_I64_Predicate_simm5_32b,
227
  GIPFP_I64_Predicate_simm5_64b,
228
  GIPFP_I64_Predicate_simm6_32b,
229
  GIPFP_I64_Predicate_simm6s1,
230
  GIPFP_I64_Predicate_simm8,
231
  GIPFP_I64_Predicate_simm9,
232
  GIPFP_I64_Predicate_sve_elm_idx_extdup_b,
233
  GIPFP_I64_Predicate_sve_elm_idx_extdup_d,
234
  GIPFP_I64_Predicate_sve_elm_idx_extdup_h,
235
  GIPFP_I64_Predicate_sve_elm_idx_extdup_q,
236
  GIPFP_I64_Predicate_sve_elm_idx_extdup_s,
237
  GIPFP_I64_Predicate_sve_incdec_imm,
238
  GIPFP_I64_Predicate_sve_pred_enum,
239
  GIPFP_I64_Predicate_sve_prfop,
240
  GIPFP_I64_Predicate_tbz_imm0_31_diag,
241
  GIPFP_I64_Predicate_tbz_imm0_31_nodiag,
242
  GIPFP_I64_Predicate_tbz_imm32_63,
243
  GIPFP_I64_Predicate_uimm16,
244
  GIPFP_I64_Predicate_uimm5s2,
245
  GIPFP_I64_Predicate_uimm5s4,
246
  GIPFP_I64_Predicate_uimm5s8,
247
  GIPFP_I64_Predicate_uimm6,
248
  GIPFP_I64_Predicate_uimm6s1,
249
  GIPFP_I64_Predicate_uimm6s16,
250
  GIPFP_I64_Predicate_uimm6s2,
251
  GIPFP_I64_Predicate_uimm6s4,
252
  GIPFP_I64_Predicate_uimm6s8,
253
  GIPFP_I64_Predicate_vecshiftL16,
254
  GIPFP_I64_Predicate_vecshiftL32,
255
  GIPFP_I64_Predicate_vecshiftL64,
256
  GIPFP_I64_Predicate_vecshiftL8,
257
  GIPFP_I64_Predicate_vecshiftR16,
258
  GIPFP_I64_Predicate_vecshiftR16Narrow,
259
  GIPFP_I64_Predicate_vecshiftR32,
260
  GIPFP_I64_Predicate_vecshiftR32Narrow,
261
  GIPFP_I64_Predicate_vecshiftR64,
262
  GIPFP_I64_Predicate_vecshiftR64Narrow,
263
  GIPFP_I64_Predicate_vecshiftR8,
264
};
265
21.2k
bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
266
21.2k
  switch (PredicateID) {
267
21.2k
  case GIPFP_I64_Predicate_VectorIndex1: {
268
0
     return ((uint64_t)Imm) == 1; 
269
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
270
21.2k
    
return false0
;
271
21.2k
  }
272
21.2k
  case GIPFP_I64_Predicate_VectorIndexB: {
273
0
     return ((uint64_t)Imm) < 16; 
274
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
275
21.2k
    
return false0
;
276
21.2k
  }
277
21.2k
  case GIPFP_I64_Predicate_VectorIndexD: {
278
566
     return ((uint64_t)Imm) < 2; 
279
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
280
21.2k
    
return false0
;
281
21.2k
  }
282
21.2k
  case GIPFP_I64_Predicate_VectorIndexH: {
283
0
     return ((uint64_t)Imm) < 8; 
284
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
285
21.2k
    
return false0
;
286
21.2k
  }
287
21.2k
  case GIPFP_I64_Predicate_VectorIndexS: {
288
88
     return ((uint64_t)Imm) < 4; 
289
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
290
21.2k
    
return false0
;
291
21.2k
  }
292
21.2k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16: {
293
0
    
294
0
  return AArch64_AM::isSVEAddSubImm<int16_t>(Imm);
295
21.2k
296
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
297
21.2k
    
return false0
;
298
21.2k
  }
299
21.2k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32: {
300
0
    
301
0
  return AArch64_AM::isSVEAddSubImm<int32_t>(Imm);
302
21.2k
303
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
304
21.2k
    
return false0
;
305
21.2k
  }
306
21.2k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64: {
307
0
    
308
0
  return AArch64_AM::isSVEAddSubImm<int64_t>(Imm);
309
21.2k
310
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
311
21.2k
    
return false0
;
312
21.2k
  }
313
21.2k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8: {
314
0
    
315
0
  return AArch64_AM::isSVEAddSubImm<int8_t>(Imm);
316
21.2k
317
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
318
21.2k
    
return false0
;
319
21.2k
  }
320
21.2k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16: {
321
0
    
322
0
  return AArch64_AM::isSVECpyImm<int16_t>(Imm);
323
21.2k
324
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
325
21.2k
    
return false0
;
326
21.2k
  }
327
21.2k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32: {
328
0
    
329
0
  return AArch64_AM::isSVECpyImm<int32_t>(Imm);
330
21.2k
331
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
332
21.2k
    
return false0
;
333
21.2k
  }
334
21.2k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64: {
335
0
    
336
0
  return AArch64_AM::isSVECpyImm<int64_t>(Imm);
337
21.2k
338
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
339
21.2k
    
return false0
;
340
21.2k
  }
341
21.2k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8: {
342
0
    
343
0
  return AArch64_AM::isSVECpyImm<int8_t>(Imm);
344
21.2k
345
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
346
21.2k
    
return false0
;
347
21.2k
  }
348
21.2k
  case GIPFP_I64_Predicate_i64imm_32bit: {
349
119
    
350
119
  return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
351
21.2k
352
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
353
21.2k
    
return false0
;
354
21.2k
  }
355
21.2k
  case GIPFP_I64_Predicate_imm0_1: {
356
0
    
357
0
  return ((uint64_t)Imm) < 2;
358
21.2k
359
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
360
21.2k
    
return false0
;
361
21.2k
  }
362
21.2k
  case GIPFP_I64_Predicate_imm0_127: {
363
1
    
364
1
  return ((uint32_t)Imm) < 128;
365
21.2k
366
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
367
21.2k
    
return false0
;
368
21.2k
  }
369
21.2k
  case GIPFP_I64_Predicate_imm0_15: {
370
0
    
371
0
  return ((uint64_t)Imm) < 16;
372
21.2k
373
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
374
21.2k
    
return false0
;
375
21.2k
  }
376
21.2k
  case GIPFP_I64_Predicate_imm0_255: {
377
0
    
378
0
  return ((uint32_t)Imm) < 256;
379
21.2k
380
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
381
21.2k
    
return false0
;
382
21.2k
  }
383
21.2k
  case GIPFP_I64_Predicate_imm0_31: {
384
0
    
385
0
  return ((uint64_t)Imm) < 32;
386
21.2k
387
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
388
21.2k
    
return false0
;
389
21.2k
  }
390
21.2k
  case GIPFP_I64_Predicate_imm0_63: {
391
18.0k
    
392
18.0k
  return ((uint64_t)Imm) < 64;
393
21.2k
394
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
395
21.2k
    
return false0
;
396
21.2k
  }
397
21.2k
  case GIPFP_I64_Predicate_imm0_65535: {
398
0
    
399
0
  return ((uint32_t)Imm) < 65536;
400
21.2k
401
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
402
21.2k
    
return false0
;
403
21.2k
  }
404
21.2k
  case GIPFP_I64_Predicate_imm0_7: {
405
0
    
406
0
  return ((uint64_t)Imm) < 8;
407
21.2k
408
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
409
21.2k
    
return false0
;
410
21.2k
  }
411
21.2k
  case GIPFP_I64_Predicate_imm32_0_15: {
412
0
    
413
0
  return ((uint32_t)Imm) < 16;
414
21.2k
415
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
416
21.2k
    
return false0
;
417
21.2k
  }
418
21.2k
  case GIPFP_I64_Predicate_imm32_0_31: {
419
0
    
420
0
  return ((uint64_t)Imm) < 32;
421
21.2k
422
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
423
21.2k
    
return false0
;
424
21.2k
  }
425
21.2k
  case GIPFP_I64_Predicate_maski16_or_more: {
426
0
     return (Imm & 0xffff) == 0xffff; 
427
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
428
21.2k
    
return false0
;
429
21.2k
  }
430
21.2k
  case GIPFP_I64_Predicate_maski8_or_more: {
431
0
     return (Imm & 0xff) == 0xff; 
432
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
433
21.2k
    
return false0
;
434
21.2k
  }
435
21.2k
  case GIPFP_I64_Predicate_s64imm_32bit: {
436
2.37k
    
437
2.37k
  int64_t Imm64 = static_cast<int64_t>(Imm);
438
2.37k
  return Imm64 >= std::numeric_limits<int32_t>::min() &&
439
2.37k
         Imm64 <= std::numeric_limits<int32_t>::max();
440
21.2k
441
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
442
21.2k
    
return false0
;
443
21.2k
  }
444
21.2k
  case GIPFP_I64_Predicate_simm4s1: {
445
0
     return Imm >=-8  && Imm <= 7; 
446
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
447
21.2k
    
return false0
;
448
21.2k
  }
449
21.2k
  case GIPFP_I64_Predicate_simm4s16: {
450
0
     return Imm >=-128  && Imm <= 112 && (Imm % 16) == 0x0; 
451
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
452
21.2k
    
return false0
;
453
21.2k
  }
454
21.2k
  case GIPFP_I64_Predicate_simm4s2: {
455
0
     return Imm >=-16  && Imm <= 14 && (Imm % 2) == 0x0; 
456
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
457
21.2k
    
return false0
;
458
21.2k
  }
459
21.2k
  case GIPFP_I64_Predicate_simm4s3: {
460
0
     return Imm >=-24  && Imm <= 21 && (Imm % 3) == 0x0; 
461
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
462
21.2k
    
return false0
;
463
21.2k
  }
464
21.2k
  case GIPFP_I64_Predicate_simm4s4: {
465
0
     return Imm >=-32  && Imm <= 28 && (Imm % 4) == 0x0; 
466
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
467
21.2k
    
return false0
;
468
21.2k
  }
469
21.2k
  case GIPFP_I64_Predicate_simm5_32b: {
470
0
     return Imm >= -16 && Imm < 16; 
471
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
472
21.2k
    
return false0
;
473
21.2k
  }
474
21.2k
  case GIPFP_I64_Predicate_simm5_64b: {
475
0
     return Imm >= -16 && Imm < 16; 
476
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
477
21.2k
    
return false0
;
478
21.2k
  }
479
21.2k
  case GIPFP_I64_Predicate_simm6_32b: {
480
0
     return Imm >= -32 && Imm < 32; 
481
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
482
21.2k
    
return false0
;
483
21.2k
  }
484
21.2k
  case GIPFP_I64_Predicate_simm6s1: {
485
0
     return Imm >= -32 && Imm < 32; 
486
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
487
21.2k
    
return false0
;
488
21.2k
  }
489
21.2k
  case GIPFP_I64_Predicate_simm8: {
490
0
     return Imm >= -128 && Imm < 127; 
491
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
492
21.2k
    
return false0
;
493
21.2k
  }
494
21.2k
  case GIPFP_I64_Predicate_simm9: {
495
0
     return Imm >= -256 && Imm < 256; 
496
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
497
21.2k
    
return false0
;
498
21.2k
  }
499
21.2k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_b: {
500
0
     return ((uint64_t)Imm) < 64; 
501
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
502
21.2k
    
return false0
;
503
21.2k
  }
504
21.2k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_d: {
505
0
     return ((uint64_t)Imm) < 8; 
506
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
507
21.2k
    
return false0
;
508
21.2k
  }
509
21.2k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_h: {
510
0
     return ((uint64_t)Imm) < 32; 
511
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
512
21.2k
    
return false0
;
513
21.2k
  }
514
21.2k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_q: {
515
0
     return ((uint64_t)Imm) < 4; 
516
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
517
21.2k
    
return false0
;
518
21.2k
  }
519
21.2k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_s: {
520
0
     return ((uint64_t)Imm) < 16; 
521
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
522
21.2k
    
return false0
;
523
21.2k
  }
524
21.2k
  case GIPFP_I64_Predicate_sve_incdec_imm: {
525
0
    
526
0
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
527
21.2k
528
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
529
21.2k
    
return false0
;
530
21.2k
  }
531
21.2k
  case GIPFP_I64_Predicate_sve_pred_enum: {
532
0
    
533
0
  return (((uint32_t)Imm) < 32);
534
21.2k
  
535
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
536
21.2k
    
return false0
;
537
21.2k
  }
538
21.2k
  case GIPFP_I64_Predicate_sve_prfop: {
539
0
    
540
0
    return (((uint32_t)Imm) <= 15);
541
21.2k
  
542
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
543
21.2k
    
return false0
;
544
21.2k
  }
545
21.2k
  case GIPFP_I64_Predicate_tbz_imm0_31_diag: {
546
0
    
547
0
  return (((uint32_t)Imm) < 32);
548
21.2k
549
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
550
21.2k
    
return false0
;
551
21.2k
  }
552
21.2k
  case GIPFP_I64_Predicate_tbz_imm0_31_nodiag: {
553
0
    
554
0
  return (((uint32_t)Imm) < 32);
555
21.2k
556
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
557
21.2k
    
return false0
;
558
21.2k
  }
559
21.2k
  case GIPFP_I64_Predicate_tbz_imm32_63: {
560
0
    
561
0
  return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
562
21.2k
563
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
564
21.2k
    
return false0
;
565
21.2k
  }
566
21.2k
  case GIPFP_I64_Predicate_uimm16: {
567
0
    return Imm >= 0 && Imm < 65536;
568
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
569
21.2k
    
return false0
;
570
21.2k
  }
571
21.2k
  case GIPFP_I64_Predicate_uimm5s2: {
572
0
     return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); 
573
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
574
21.2k
    
return false0
;
575
21.2k
  }
576
21.2k
  case GIPFP_I64_Predicate_uimm5s4: {
577
0
     return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); 
578
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
579
21.2k
    
return false0
;
580
21.2k
  }
581
21.2k
  case GIPFP_I64_Predicate_uimm5s8: {
582
0
     return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); 
583
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
584
21.2k
    
return false0
;
585
21.2k
  }
586
21.2k
  case GIPFP_I64_Predicate_uimm6: {
587
0
     return Imm >= 0 && Imm < 64; 
588
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
589
21.2k
    
return false0
;
590
21.2k
  }
591
21.2k
  case GIPFP_I64_Predicate_uimm6s1: {
592
0
     return Imm >= 0 && Imm < 64; 
593
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
594
21.2k
    
return false0
;
595
21.2k
  }
596
21.2k
  case GIPFP_I64_Predicate_uimm6s16: {
597
0
     return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0); 
598
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
599
21.2k
    
return false0
;
600
21.2k
  }
601
21.2k
  case GIPFP_I64_Predicate_uimm6s2: {
602
0
     return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); 
603
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
604
21.2k
    
return false0
;
605
21.2k
  }
606
21.2k
  case GIPFP_I64_Predicate_uimm6s4: {
607
0
     return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); 
608
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
609
21.2k
    
return false0
;
610
21.2k
  }
611
21.2k
  case GIPFP_I64_Predicate_uimm6s8: {
612
0
     return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); 
613
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
614
21.2k
    
return false0
;
615
21.2k
  }
616
21.2k
  case GIPFP_I64_Predicate_vecshiftL16: {
617
0
    
618
0
  return (((uint32_t)Imm) < 16);
619
21.2k
620
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
621
21.2k
    
return false0
;
622
21.2k
  }
623
21.2k
  case GIPFP_I64_Predicate_vecshiftL32: {
624
2
    
625
2
  return (((uint32_t)Imm) < 32);
626
21.2k
627
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
628
21.2k
    
return false0
;
629
21.2k
  }
630
21.2k
  case GIPFP_I64_Predicate_vecshiftL64: {
631
2
    
632
2
  return (((uint32_t)Imm) < 64);
633
21.2k
634
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
635
21.2k
    
return false0
;
636
21.2k
  }
637
21.2k
  case GIPFP_I64_Predicate_vecshiftL8: {
638
0
    
639
0
  return (((uint32_t)Imm) < 8);
640
21.2k
641
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
642
21.2k
    
return false0
;
643
21.2k
  }
644
21.2k
  case GIPFP_I64_Predicate_vecshiftR16: {
645
0
    
646
0
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
647
21.2k
648
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
649
21.2k
    
return false0
;
650
21.2k
  }
651
21.2k
  case GIPFP_I64_Predicate_vecshiftR16Narrow: {
652
0
    
653
0
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
654
21.2k
655
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
656
21.2k
    
return false0
;
657
21.2k
  }
658
21.2k
  case GIPFP_I64_Predicate_vecshiftR32: {
659
2
    
660
2
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
661
21.2k
662
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
663
21.2k
    
return false0
;
664
21.2k
  }
665
21.2k
  case GIPFP_I64_Predicate_vecshiftR32Narrow: {
666
8
    
667
8
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
668
21.2k
669
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
670
21.2k
    
return false0
;
671
21.2k
  }
672
21.2k
  case GIPFP_I64_Predicate_vecshiftR64: {
673
3
    
674
3
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
675
21.2k
676
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
677
21.2k
    
return false0
;
678
21.2k
  }
679
21.2k
  case GIPFP_I64_Predicate_vecshiftR64Narrow: {
680
8
    
681
8
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
682
21.2k
683
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
684
21.2k
    
return false0
;
685
21.2k
  }
686
21.2k
  case GIPFP_I64_Predicate_vecshiftR8: {
687
0
    
688
0
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
689
21.2k
690
21.2k
    
llvm_unreachable0
("ImmediateCode should have returned");
691
21.2k
    
return false0
;
692
0
  }
693
0
  }
694
0
  llvm_unreachable("Unknown predicate");
695
0
  return false;
696
0
}
697
// PatFrag predicates.
698
enum {
699
  GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1,
700
  GIPFP_APFloat_Predicate_fpimm16,
701
  GIPFP_APFloat_Predicate_fpimm32,
702
  GIPFP_APFloat_Predicate_fpimm64,
703
  GIPFP_APFloat_Predicate_simdimmtype10,
704
};
705
2.91k
bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
706
2.91k
  switch (PredicateID) {
707
2.91k
  case GIPFP_APFloat_Predicate_fpimm0: {
708
2.91k
    
709
2.91k
  return Imm.isExactlyValue(+0.0);
710
2.91k
711
2.91k
    
llvm_unreachable0
("ImmediateCode should have returned");
712
2.91k
    
return false0
;
713
2.91k
  }
714
2.91k
  case GIPFP_APFloat_Predicate_fpimm16: {
715
0
    
716
0
      return AArch64_AM::getFP16Imm(Imm) != -1;
717
2.91k
    
718
2.91k
    
llvm_unreachable0
("ImmediateCode should have returned");
719
2.91k
    
return false0
;
720
2.91k
  }
721
2.91k
  case GIPFP_APFloat_Predicate_fpimm32: {
722
0
    
723
0
      return AArch64_AM::getFP32Imm(Imm) != -1;
724
2.91k
    
725
2.91k
    
llvm_unreachable0
("ImmediateCode should have returned");
726
2.91k
    
return false0
;
727
2.91k
  }
728
2.91k
  case GIPFP_APFloat_Predicate_fpimm64: {
729
0
    
730
0
      return AArch64_AM::getFP64Imm(Imm) != -1;
731
2.91k
    
732
2.91k
    
llvm_unreachable0
("ImmediateCode should have returned");
733
2.91k
    
return false0
;
734
2.91k
  }
735
2.91k
  case GIPFP_APFloat_Predicate_simdimmtype10: {
736
0
    
737
0
      return AArch64_AM::isAdvSIMDModImmType10(
738
0
                 Imm.bitcastToAPInt().getZExtValue());
739
2.91k
    
740
2.91k
    
llvm_unreachable0
("ImmediateCode should have returned");
741
2.91k
    
return false0
;
742
0
  }
743
0
  }
744
0
  llvm_unreachable("Unknown predicate");
745
0
  return false;
746
0
}
747
// PatFrag predicates.
748
enum {
749
  GIPFP_APInt_Predicate_logical_imm32 = GIPFP_APInt_Invalid + 1,
750
  GIPFP_APInt_Predicate_logical_imm64,
751
};
752
0
bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
753
0
  switch (PredicateID) {
754
0
  case GIPFP_APInt_Predicate_logical_imm32: {
755
0
    
756
0
  return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32);
757
0
758
0
    llvm_unreachable("ImmediateCode should have returned");
759
0
    return false;
760
0
  }
761
0
  case GIPFP_APInt_Predicate_logical_imm64: {
762
0
    
763
0
  return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64);
764
0
765
0
    llvm_unreachable("ImmediateCode should have returned");
766
0
    return false;
767
0
  }
768
0
  }
769
0
  llvm_unreachable("Unknown predicate");
770
0
  return false;
771
0
}
772
0
bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
773
0
  const MachineFunction &MF = *MI.getParent()->getParent();
774
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
775
0
  (void)MRI;
776
0
  llvm_unreachable("Unknown predicate");
777
0
  return false;
778
0
}
779
780
AArch64InstructionSelector::ComplexMatcherMemFn
781
AArch64InstructionSelector::ComplexPredicateFns[] = {
782
  nullptr, // GICP_Invalid
783
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32
784
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64
785
  &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128
786
  &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16
787
  &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32
788
  &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64
789
  &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8
790
  &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128
791
  &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16
792
  &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32
793
  &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64
794
  &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8
795
};
796
797
// Custom renderers.
798
enum {
799
  GICR_Invalid,
800
  GICR_renderTruncImm, 
801
};
802
AArch64InstructionSelector::CustomRendererFn
803
AArch64InstructionSelector::CustomRenderers[] = {
804
  nullptr, // GICP_Invalid
805
  &AArch64InstructionSelector::renderTruncImm, // gi_trunc_imm
806
};
807
808
4.38M
bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
809
4.38M
  MachineFunction &MF = *I.getParent()->getParent();
810
4.38M
  MachineRegisterInfo &MRI = MF.getRegInfo();
811
4.38M
  // FIXME: This should be computed on a per-function basis rather than per-insn.
812
4.38M
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
813
4.38M
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
814
4.38M
  NewMIVector OutMIs;
815
4.38M
  State.MIs.clear();
816
4.38M
  State.MIs.push_back(&I);
817
4.38M
818
4.38M
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
819
1.78M
    return true;
820
1.78M
  }
821
2.59M
822
2.59M
  return false;
823
2.59M
}
824
825
4.38M
const int64_t *AArch64InstructionSelector::getMatchTable() const {
826
4.38M
  constexpr static int64_t MatchTable0[] = {
827
4.38M
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 139, /*)*//*default:*//*Label 53*/ 83121,
828
4.38M
    /*TargetOpcode::G_ADD*//*Label 0*/ 110,
829
4.38M
    /*TargetOpcode::G_SUB*//*Label 1*/ 7523,
830
4.38M
    /*TargetOpcode::G_MUL*//*Label 2*/ 10104,
831
4.38M
    /*TargetOpcode::G_SDIV*//*Label 3*/ 10885,
832
4.38M
    /*TargetOpcode::G_UDIV*//*Label 4*/ 10954, 0, 0,
833
4.38M
    /*TargetOpcode::G_AND*//*Label 5*/ 11023,
834
4.38M
    /*TargetOpcode::G_OR*//*Label 6*/ 11681,
835
4.38M
    /*TargetOpcode::G_XOR*//*Label 7*/ 12223, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
836
4.38M
    /*TargetOpcode::G_BITCAST*//*Label 8*/ 12933, 0, 0,
837
4.38M
    /*TargetOpcode::G_LOAD*//*Label 9*/ 20426,
838
4.38M
    /*TargetOpcode::G_SEXTLOAD*//*Label 10*/ 22482,
839
4.38M
    /*TargetOpcode::G_ZEXTLOAD*//*Label 11*/ 22953,
840
4.38M
    /*TargetOpcode::G_STORE*//*Label 12*/ 23305, 0,
841
4.38M
    /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 13*/ 25552,
842
4.38M
    /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 14*/ 26749,
843
4.38M
    /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 15*/ 27778,
844
4.38M
    /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 16*/ 28807,
845
4.38M
    /*TargetOpcode::G_ATOMICRMW_AND*//*Label 17*/ 30216, 0,
846
4.38M
    /*TargetOpcode::G_ATOMICRMW_OR*//*Label 18*/ 31625,
847
4.38M
    /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 19*/ 32654,
848
4.38M
    /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 20*/ 33683,
849
4.38M
    /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 21*/ 34712,
850
4.38M
    /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 22*/ 35741,
851
4.38M
    /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 23*/ 36770, 0, 0,
852
4.38M
    /*TargetOpcode::G_INTRINSIC*//*Label 24*/ 37799,
853
4.38M
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 25*/ 73460,
854
4.38M
    /*TargetOpcode::G_ANYEXT*//*Label 26*/ 73702,
855
4.38M
    /*TargetOpcode::G_TRUNC*//*Label 27*/ 73816,
856
4.38M
    /*TargetOpcode::G_CONSTANT*//*Label 28*/ 73941,
857
4.38M
    /*TargetOpcode::G_FCONSTANT*//*Label 29*/ 73994, 0, 0,
858
4.38M
    /*TargetOpcode::G_SEXT*//*Label 30*/ 74072,
859
4.38M
    /*TargetOpcode::G_ZEXT*//*Label 31*/ 74252,
860
4.38M
    /*TargetOpcode::G_SHL*//*Label 32*/ 74711,
861
4.38M
    /*TargetOpcode::G_LSHR*//*Label 33*/ 74887,
862
4.38M
    /*TargetOpcode::G_ASHR*//*Label 34*/ 75138, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
863
4.38M
    /*TargetOpcode::G_FADD*//*Label 35*/ 75389,
864
4.38M
    /*TargetOpcode::G_FSUB*//*Label 36*/ 75962,
865
4.38M
    /*TargetOpcode::G_FMUL*//*Label 37*/ 76235,
866
4.38M
    /*TargetOpcode::G_FMA*//*Label 38*/ 76901,
867
4.38M
    /*TargetOpcode::G_FDIV*//*Label 39*/ 79725, 0, 0, 0, 0, 0, 0, 0,
868
4.38M
    /*TargetOpcode::G_FNEG*//*Label 40*/ 79998,
869
4.38M
    /*TargetOpcode::G_FPEXT*//*Label 41*/ 80546,
870
4.38M
    /*TargetOpcode::G_FPTRUNC*//*Label 42*/ 80675,
871
4.38M
    /*TargetOpcode::G_FPTOSI*//*Label 43*/ 80804,
872
4.38M
    /*TargetOpcode::G_FPTOUI*//*Label 44*/ 81080,
873
4.38M
    /*TargetOpcode::G_SITOFP*//*Label 45*/ 81356,
874
4.38M
    /*TargetOpcode::G_UITOFP*//*Label 46*/ 81634, 0, 0, 0,
875
4.38M
    /*TargetOpcode::G_BR*//*Label 47*/ 81912, 0,
876
4.38M
    /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 48*/ 81925, 0,
877
4.38M
    /*TargetOpcode::G_CTTZ*//*Label 49*/ 82284, 0,
878
4.38M
    /*TargetOpcode::G_CTLZ*//*Label 50*/ 82387, 0,
879
4.38M
    /*TargetOpcode::G_CTPOP*//*Label 51*/ 83010,
880
4.38M
    /*TargetOpcode::G_BSWAP*//*Label 52*/ 83068,
881
4.38M
    // Label 0: @110
882
4.38M
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 63*/ 7522,
883
4.38M
    /*GILLT_s32*//*Label 54*/ 126,
884
4.38M
    /*GILLT_s64*//*Label 55*/ 227, 0,
885
4.38M
    /*GILLT_v2s32*//*Label 56*/ 1437,
886
4.38M
    /*GILLT_v2s64*//*Label 57*/ 2050,
887
4.38M
    /*GILLT_v4s16*//*Label 58*/ 3153,
888
4.38M
    /*GILLT_v4s32*//*Label 59*/ 3766,
889
4.38M
    /*GILLT_v8s8*//*Label 60*/ 5239,
890
4.38M
    /*GILLT_v8s16*//*Label 61*/ 5644,
891
4.38M
    /*GILLT_v16s8*//*Label 62*/ 7117,
892
4.38M
    // Label 54: @126
893
4.38M
    GIM_Try, /*On fail goto*//*Label 64*/ 226,
894
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
895
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
896
4.38M
      GIM_Try, /*On fail goto*//*Label 65*/ 170, // Rule ID 3828 //
897
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
898
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID,
899
4.38M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
900
4.38M
        // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
901
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
902
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
903
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
904
4.38M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
905
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
906
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
907
4.38M
        // GIR_Coverage, 3828,
908
4.38M
        GIR_Done,
909
4.38M
      // Label 65: @170
910
4.38M
      GIM_Try, /*On fail goto*//*Label 66*/ 204, // Rule ID 50 //
911
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
912
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
913
4.38M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
914
4.38M
        // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
915
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
916
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
917
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
918
4.38M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
919
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
920
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
921
4.38M
        // GIR_Coverage, 50,
922
4.38M
        GIR_Done,
923
4.38M
      // Label 66: @204
924
4.38M
      GIM_Try, /*On fail goto*//*Label 67*/ 225, // Rule ID 52 //
925
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
926
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
927
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
928
4.38M
        // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
929
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDWrr,
930
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
931
4.38M
        // GIR_Coverage, 52,
932
4.38M
        GIR_Done,
933
4.38M
      // Label 67: @225
934
4.38M
      GIM_Reject,
935
4.38M
    // Label 64: @226
936
4.38M
    GIM_Reject,
937
4.38M
    // Label 55: @227
938
4.38M
    GIM_Try, /*On fail goto*//*Label 68*/ 1436,
939
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
940
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
941
4.38M
      GIM_Try, /*On fail goto*//*Label 69*/ 306, // Rule ID 3500 //
942
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
943
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
944
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT,
945
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
946
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
947
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
948
4.38M
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0,
949
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
950
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT,
951
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
952
4.38M
        // MIs[2] Rn
953
4.38M
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
954
4.38M
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
955
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
956
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
957
4.38M
        // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }))  =>  (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn)
958
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p,
959
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
960
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
961
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
962
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
963
4.38M
        // GIR_Coverage, 3500,
964
4.38M
        GIR_Done,
965
4.38M
      // Label 69: @306
966
4.38M
      GIM_Try, /*On fail goto*//*Label 70*/ 375, // Rule ID 4247 //
967
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
968
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
969
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT,
970
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
971
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
972
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
973
4.38M
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
974
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
975
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT,
976
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
977
4.38M
        // MIs[2] Rn
978
4.38M
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
979
4.38M
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0,
980
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
981
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
982
4.38M
        // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn)
983
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p,
984
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
985
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
986
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
987
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
988
4.38M
        // GIR_Coverage, 4247,
989
4.38M
        GIR_Done,
990
4.38M
      // Label 70: @375
991
4.38M
      GIM_Try, /*On fail goto*//*Label 71*/ 409, // Rule ID 3829 //
992
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
993
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID,
994
4.38M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
995
4.38M
        // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
996
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
997
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
998
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
999
4.38M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
1000
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1001
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1002
4.38M
        // GIR_Coverage, 3829,
1003
4.38M
        GIR_Done,
1004
4.38M
      // Label 71: @409
1005
4.38M
      GIM_Try, /*On fail goto*//*Label 72*/ 505, // Rule ID 1913 //
1006
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1007
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1008
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1009
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1010
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1011
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1012
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1013
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1014
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1015
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1016
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1017
4.38M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
1018
4.38M
        // MIs[3] Operand 1
1019
4.38M
        // No operand predicates
1020
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1021
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1022
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1023
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1024
4.38M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1025
4.38M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1026
4.38M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1027
4.38M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1028
4.38M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1029
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1030
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1031
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1032
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1033
4.38M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1034
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1035
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1036
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1037
4.38M
        // GIR_Coverage, 1913,
1038
4.38M
        GIR_Done,
1039
4.38M
      // Label 72: @505
1040
4.38M
      GIM_Try, /*On fail goto*//*Label 73*/ 601, // Rule ID 1914 //
1041
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1042
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1043
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1044
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1045
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1046
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1047
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1048
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1049
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1050
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1051
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1052
4.38M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
1053
4.38M
        // MIs[3] Operand 1
1054
4.38M
        // No operand predicates
1055
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1056
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1057
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1058
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1059
4.38M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1060
4.38M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1061
4.38M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1062
4.38M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1063
4.38M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1064
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1065
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1066
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1067
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1068
4.38M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1069
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1070
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1071
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1072
4.38M
        // GIR_Coverage, 1914,
1073
4.38M
        GIR_Done,
1074
4.38M
      // Label 73: @601
1075
4.38M
      GIM_Try, /*On fail goto*//*Label 74*/ 635, // Rule ID 51 //
1076
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
1077
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
1078
4.38M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
1079
4.38M
        // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
1080
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
1081
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1082
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1083
4.38M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
1084
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1085
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1086
4.38M
        // GIR_Coverage, 51,
1087
4.38M
        GIR_Done,
1088
4.38M
      // Label 74: @635
1089
4.38M
      GIM_Try, /*On fail goto*//*Label 75*/ 731, // Rule ID 4080 //
1090
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1091
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1092
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1093
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1094
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1095
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1096
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1097
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1098
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1099
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1100
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1101
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1102
4.38M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
1103
4.38M
        // MIs[3] Operand 1
1104
4.38M
        // No operand predicates
1105
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1106
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1107
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1108
4.38M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1109
4.38M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1110
4.38M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1111
4.38M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1112
4.38M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1113
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1114
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1115
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1116
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1117
4.38M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1118
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1119
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1120
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1121
4.38M
        // GIR_Coverage, 4080,
1122
4.38M
        GIR_Done,
1123
4.38M
      // Label 75: @731
1124
4.38M
      GIM_Try, /*On fail goto*//*Label 76*/ 827, // Rule ID 4081 //
1125
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1126
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1127
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1128
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1129
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1130
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1131
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1132
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1133
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1134
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1135
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1136
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1137
4.38M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
1138
4.38M
        // MIs[3] Operand 1
1139
4.38M
        // No operand predicates
1140
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1141
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1142
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1143
4.38M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1144
4.38M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1145
4.38M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1146
4.38M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1147
4.38M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1148
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1149
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1150
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1151
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1152
4.38M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1153
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1154
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1155
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1156
4.38M
        // GIR_Coverage, 4081,
1157
4.38M
        GIR_Done,
1158
4.38M
      // Label 76: @827
1159
4.38M
      GIM_Try, /*On fail goto*//*Label 77*/ 912, // Rule ID 3840 //
1160
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1161
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1162
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1163
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1164
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1165
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1166
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1167
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1168
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1169
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1170
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
1171
4.38M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1172
4.38M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1173
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1174
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1175
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1176
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1177
4.38M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1178
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1179
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1180
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1181
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1182
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1183
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1184
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1185
4.38M
        // GIR_Coverage, 3840,
1186
4.38M
        GIR_Done,
1187
4.38M
      // Label 77: @912
1188
4.38M
      GIM_Try, /*On fail goto*//*Label 78*/ 997, // Rule ID 3841 //
1189
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1190
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1191
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1192
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1193
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1194
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1195
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1196
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1197
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1198
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1199
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
1200
4.38M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1201
4.38M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1202
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1203
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1204
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1205
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1206
4.38M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1207
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1208
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1209
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1210
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1211
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1212
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1213
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1214
4.38M
        // GIR_Coverage, 3841,
1215
4.38M
        GIR_Done,
1216
4.38M
      // Label 78: @997
1217
4.38M
      GIM_Try, /*On fail goto*//*Label 79*/ 1082, // Rule ID 82 //
1218
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1219
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1220
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1221
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1222
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1223
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1224
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1225
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1226
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1227
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1228
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1229
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
1230
4.38M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1231
4.38M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1232
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1233
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1234
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1235
4.38M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1236
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1237
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1238
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1239
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1240
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1241
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1242
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1243
4.38M
        // GIR_Coverage, 82,
1244
4.38M
        GIR_Done,
1245
4.38M
      // Label 79: @1082
1246
4.38M
      GIM_Try, /*On fail goto*//*Label 80*/ 1167, // Rule ID 84 //
1247
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1248
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1249
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1250
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1251
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1252
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1253
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1254
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1255
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1256
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1257
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1258
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
1259
4.38M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1260
4.38M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1261
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1262
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1263
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1264
4.38M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1265
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1266
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1267
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1268
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1269
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1270
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1271
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1272
4.38M
        // GIR_Coverage, 84,
1273
4.38M
        GIR_Done,
1274
4.38M
      // Label 80: @1167
1275
4.38M
      GIM_Try, /*On fail goto*//*Label 81*/ 1223, // Rule ID 3894 //
1276
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1277
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1278
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1279
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1280
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1281
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1282
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1283
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1284
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1285
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1286
4.38M
        // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 321:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1287
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
1288
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1289
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1290
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1291
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1292
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1293
4.38M
        // GIR_Coverage, 3894,
1294
4.38M
        GIR_Done,
1295
4.38M
      // Label 81: @1223
1296
4.38M
      GIM_Try, /*On fail goto*//*Label 82*/ 1279, // Rule ID 3900 //
1297
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1298
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1299
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1300
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1301
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1302
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1303
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1304
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1305
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1306
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1307
4.38M
        // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 379:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1308
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64,
1309
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1310
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1311
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1312
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1313
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1314
4.38M
        // GIR_Coverage, 3900,
1315
4.38M
        GIR_Done,
1316
4.38M
      // Label 82: @1279
1317
4.38M
      GIM_Try, /*On fail goto*//*Label 83*/ 1335, // Rule ID 714 //
1318
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1319
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1320
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1321
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1322
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1323
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1324
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1325
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1326
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1327
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1328
4.38M
        // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 321:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1329
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
1330
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1331
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1332
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1333
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1334
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1335
4.38M
        // GIR_Coverage, 714,
1336
4.38M
        GIR_Done,
1337
4.38M
      // Label 83: @1335
1338
4.38M
      GIM_Try, /*On fail goto*//*Label 84*/ 1391, // Rule ID 758 //
1339
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1340
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1341
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1342
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1343
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1344
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1345
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1346
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1347
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1348
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1349
4.38M
        // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 379:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1350
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64,
1351
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1352
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1353
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1354
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1355
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1356
4.38M
        // GIR_Coverage, 758,
1357
4.38M
        GIR_Done,
1358
4.38M
      // Label 84: @1391
1359
4.38M
      GIM_Try, /*On fail goto*//*Label 85*/ 1412, // Rule ID 53 //
1360
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1361
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1362
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1363
4.38M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ADDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
1364
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDXrr,
1365
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1366
4.38M
        // GIR_Coverage, 53,
1367
4.38M
        GIR_Done,
1368
4.38M
      // Label 85: @1412
1369
4.38M
      GIM_Try, /*On fail goto*//*Label 86*/ 1435, // Rule ID 1213 //
1370
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1371
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1372
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1373
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1374
4.38M
        // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (ADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
1375
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv1i64,
1376
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1377
4.38M
        // GIR_Coverage, 1213,
1378
4.38M
        GIR_Done,
1379
4.38M
      // Label 86: @1435
1380
4.38M
      GIM_Reject,
1381
4.38M
    // Label 68: @1436
1382
4.38M
    GIM_Reject,
1383
4.38M
    // Label 56: @1437
1384
4.38M
    GIM_Try, /*On fail goto*//*Label 87*/ 2049,
1385
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1386
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1387
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1388
4.38M
      GIM_Try, /*On fail goto*//*Label 88*/ 1515, // Rule ID 3912 //
1389
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1390
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1391
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1392
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1393
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1394
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1395
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1396
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1397
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1398
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1399
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1400
4.38M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 320:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1401
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
1402
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1403
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1404
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1405
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1406
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1407
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1408
4.38M
        // GIR_Coverage, 3912,
1409
4.38M
        GIR_Done,
1410
4.38M
      // Label 88: @1515
1411
4.38M
      GIM_Try, /*On fail goto*//*Label 89*/ 1579, // Rule ID 3918 //
1412
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1413
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1414
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1415
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1416
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1417
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1418
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1419
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1420
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1421
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1422
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1423
4.38M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 378:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1424
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
1425
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1426
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1427
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1428
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1429
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1430
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1431
4.38M
        // GIR_Coverage, 3918,
1432
4.38M
        GIR_Done,
1433
4.38M
      // Label 89: @1579
1434
4.38M
      GIM_Try, /*On fail goto*//*Label 90*/ 1631, // Rule ID 3892 //
1435
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1436
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1437
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1438
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1439
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1440
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1441
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1442
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1443
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1444
4.38M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 321:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1445
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
1446
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1447
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1448
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1449
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1450
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1451
4.38M
        // GIR_Coverage, 3892,
1452
4.38M
        GIR_Done,
1453
4.38M
      // Label 90: @1631
1454
4.38M
      GIM_Try, /*On fail goto*//*Label 91*/ 1683, // Rule ID 3898 //
1455
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1456
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1457
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1458
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1459
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1460
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1461
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1462
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1463
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1464
4.38M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 379:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1465
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32,
1466
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1467
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1468
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1469
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1470
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1471
4.38M
        // GIR_Coverage, 3898,
1472
4.38M
        GIR_Done,
1473
4.38M
      // Label 91: @1683
1474
4.38M
      GIM_Try, /*On fail goto*//*Label 92*/ 1747, // Rule ID 988 //
1475
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1476
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1477
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1478
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1479
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1480
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1481
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1482
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1483
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1484
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1485
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1486
4.38M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 320:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1487
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
1488
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1489
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1490
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1491
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1492
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1493
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1494
4.38M
        // GIR_Coverage, 988,
1495
4.38M
        GIR_Done,
1496
4.38M
      // Label 92: @1747
1497
4.38M
      GIM_Try, /*On fail goto*//*Label 93*/ 1811, // Rule ID 1099 //
1498
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1499
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1500
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1501
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1502
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1503
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1504
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1505
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1506
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1507
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1508
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1509
4.38M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 378:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1510
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
1511
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1512
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1513
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1514
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1515
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1516
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1517
4.38M
        // GIR_Coverage, 1099,
1518
4.38M
        GIR_Done,
1519
4.38M
      // Label 93: @1811
1520
4.38M
      GIM_Try, /*On fail goto*//*Label 94*/ 1863, // Rule ID 712 //
1521
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1522
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1523
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1524
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1525
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1526
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1527
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1528
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1529
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1530
4.38M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 321:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1531
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
1532
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1533
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1534
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1535
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1536
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1537
4.38M
        // GIR_Coverage, 712,
1538
4.38M
        GIR_Done,
1539
4.38M
      // Label 94: @1863
1540
4.38M
      GIM_Try, /*On fail goto*//*Label 95*/ 1915, // Rule ID 756 //
1541
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1542
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1543
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1544
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1545
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1546
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1547
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1548
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1549
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1550
4.38M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 379:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1551
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32,
1552
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1553
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1554
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1555
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1556
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1557
4.38M
        // GIR_Coverage, 756,
1558
4.38M
        GIR_Done,
1559
4.38M
      // Label 95: @1915
1560
4.38M
      GIM_Try, /*On fail goto*//*Label 96*/ 1972, // Rule ID 3906 //
1561
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1562
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1563
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1564
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1565
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1566
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1567
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1568
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1569
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1570
4.38M
        // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (MLAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1571
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32,
1572
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1573
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1574
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1575
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1576
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1577
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1578
4.38M
        // GIR_Coverage, 3906,
1579
4.38M
        GIR_Done,
1580
4.38M
      // Label 96: @1972
1581
4.38M
      GIM_Try, /*On fail goto*//*Label 97*/ 2029, // Rule ID 968 //
1582
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1583
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1584
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1585
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1586
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1587
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1588
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1589
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1590
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1591
4.38M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (MLAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1592
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32,
1593
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1594
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1595
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1596
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1597
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1598
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1599
4.38M
        // GIR_Coverage, 968,
1600
4.38M
        GIR_Done,
1601
4.38M
      // Label 97: @2029
1602
4.38M
      GIM_Try, /*On fail goto*//*Label 98*/ 2048, // Rule ID 792 //
1603
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1604
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1605
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1606
4.38M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1607
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i32,
1608
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1609
4.38M
        // GIR_Coverage, 792,
1610
4.38M
        GIR_Done,
1611
4.38M
      // Label 98: @2048
1612
4.38M
      GIM_Reject,
1613
4.38M
    // Label 87: @2049
1614
4.38M
    GIM_Reject,
1615
4.38M
    // Label 57: @2050
1616
4.38M
    GIM_Try, /*On fail goto*//*Label 99*/ 3152,
1617
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1618
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1619
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
1620
4.38M
      GIM_Try, /*On fail goto*//*Label 100*/ 2141, // Rule ID 3966 //
1621
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1622
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1623
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1624
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1625
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1626
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1627
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1628
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1629
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1630
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1631
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1632
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1633
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1634
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1635
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1636
4.38M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 320:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1637
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
1638
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1639
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1640
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1641
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1642
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1643
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1644
4.38M
        // GIR_Coverage, 3966,
1645
4.38M
        GIR_Done,
1646
4.38M
      // Label 100: @2141
1647
4.38M
      GIM_Try, /*On fail goto*//*Label 101*/ 2218, // Rule ID 3984 //
1648
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1649
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1650
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1651
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1652
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1653
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1654
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1655
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1656
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1657
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1658
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1659
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1660
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1661
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1662
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1663
4.38M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 378:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1664
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
1665
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1666
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1667
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1668
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1669
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1670
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1671
4.38M
        // GIR_Coverage, 3984,
1672
4.38M
        GIR_Done,
1673
4.38M
      // Label 101: @2218
1674
4.38M
      GIM_Try, /*On fail goto*//*Label 102*/ 2295, // Rule ID 1295 //
1675
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1676
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1677
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1678
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1679
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1680
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1681
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1682
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1683
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1684
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1685
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1686
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1687
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1688
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1689
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1690
4.38M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 320:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1691
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
1692
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1693
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1694
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1695
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1696
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1697
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1698
4.38M
        // GIR_Coverage, 1295,
1699
4.38M
        GIR_Done,
1700
4.38M
      // Label 102: @2295
1701
4.38M
      GIM_Try, /*On fail goto*//*Label 103*/ 2372, // Rule ID 1361 //
1702
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1703
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1704
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1705
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1706
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1707
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1708
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1709
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1710
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1711
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1712
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1713
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1714
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1715
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1716
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1717
4.38M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 378:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1718
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
1719
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1720
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1721
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1722
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1723
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1724
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1725
4.38M
        // GIR_Coverage, 1361,
1726
4.38M
        GIR_Done,
1727
4.38M
      // Label 103: @2372
1728
4.38M
      GIM_Try, /*On fail goto*//*Label 104*/ 2436, // Rule ID 3978 //
1729
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1730
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1731
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1732
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1733
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
1734
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1735
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1736
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1737
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1738
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1739
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1740
4.38M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 337:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1741
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
1742
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1743
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1744
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1745
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1746
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1747
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1748
4.38M
        // GIR_Coverage, 3978,
1749
4.38M
        GIR_Done,
1750
4.38M
      // Label 104: @2436
1751
4.38M
      GIM_Try, /*On fail goto*//*Label 105*/ 2500, // Rule ID 3996 //
1752
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1753
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1754
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1755
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1756
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
1757
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1758
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1759
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1760
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1761
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1762
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1763
4.38M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 391:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1764
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
1765
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1766
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1767
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1768
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1769
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1770
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1771
4.38M
        // GIR_Coverage, 3996,
1772
4.38M
        GIR_Done,
1773
4.38M
      // Label 105: @2500
1774
4.38M
      GIM_Try, /*On fail goto*//*Label 106*/ 2552, // Rule ID 3895 //
1775
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1776
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1777
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1778
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1779
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1780
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1781
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1782
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1783
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1784
4.38M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 321:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1785
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
1786
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1787
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1788
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1789
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1790
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1791
4.38M
        // GIR_Coverage, 3895,
1792
4.38M
        GIR_Done,
1793
4.38M
      // Label 106: @2552
1794
4.38M
      GIM_Try, /*On fail goto*//*Label 107*/ 2604, // Rule ID 3901 //
1795
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1796
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1797
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1798
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1799
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1800
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1801
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1802
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1803
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1804
4.38M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 379:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1805
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64,
1806
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1807
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1808
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1809
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1810
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1811
4.38M
        // GIR_Coverage, 3901,
1812
4.38M
        GIR_Done,
1813
4.38M
      // Label 107: @2604
1814
4.38M
      GIM_Try, /*On fail goto*//*Label 108*/ 2668, // Rule ID 1319 //
1815
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1816
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1817
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1818
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1819
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1820
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
1821
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1822
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1823
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1824
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1825
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1826
4.38M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 337:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1827
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
1828
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1829
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1830
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1831
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1832
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1833
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1834
4.38M
        // GIR_Coverage, 1319,
1835
4.38M
        GIR_Done,
1836
4.38M
      // Label 108: @2668
1837
4.38M
      GIM_Try, /*On fail goto*//*Label 109*/ 2732, // Rule ID 1379 //
1838
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1839
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1840
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1841
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1842
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1843
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
1844
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1845
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1846
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1847
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1848
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1849
4.38M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 391:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1850
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
1851
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1852
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1853
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1854
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1855
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1856
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1857
4.38M
        // GIR_Coverage, 1379,
1858
4.38M
        GIR_Done,
1859
4.38M
      // Label 109: @2732
1860
4.38M
      GIM_Try, /*On fail goto*//*Label 110*/ 2784, // Rule ID 715 //
1861
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1862
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1863
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1864
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1865
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1866
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1867
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1868
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1869
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1870
4.38M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 321:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1871
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
1872
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1873
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1874
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1875
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1876
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1877
4.38M
        // GIR_Coverage, 715,
1878
4.38M
        GIR_Done,
1879
4.38M
      // Label 110: @2784
1880
4.38M
      GIM_Try, /*On fail goto*//*Label 111*/ 2836, // Rule ID 759 //
1881
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1882
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1883
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1884
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1885
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1886
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1887
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1888
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1889
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1890
4.38M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 379:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1891
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64,
1892
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1893
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1894
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1895
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1896
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1897
4.38M
        // GIR_Coverage, 759,
1898
4.38M
        GIR_Done,
1899
4.38M
      // Label 111: @2836
1900
4.38M
      GIM_Try, /*On fail goto*//*Label 112*/ 2894, // Rule ID 1307 //
1901
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1902
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1903
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1904
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1905
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1906
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1907
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1908
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1909
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1910
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1911
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1912
4.38M
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1913
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv2i32_v2i64,
1914
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1915
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1916
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1917
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1918
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1919
4.38M
        // GIR_Coverage, 1307,
1920
4.38M
        GIR_Done,
1921
4.38M
      // Label 112: @2894
1922
4.38M
      GIM_Try, /*On fail goto*//*Label 113*/ 2952, // Rule ID 1367 //
1923
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1924
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1925
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1926
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1927
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1928
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1929
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1930
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1931
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1932
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1933
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1934
4.38M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1935
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64,
1936
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1937
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1938
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1939
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1940
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1941
4.38M
        // GIR_Coverage, 1367,
1942
4.38M
        GIR_Done,
1943
4.38M
      // Label 113: @2952
1944
4.38M
      GIM_Try, /*On fail goto*//*Label 114*/ 2997, // Rule ID 3972 //
1945
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1946
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1947
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1948
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1949
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1950
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1951
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1952
4.38M
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1953
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64,
1954
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1955
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1956
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1957
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1958
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1959
4.38M
        // GIR_Coverage, 3972,
1960
4.38M
        GIR_Done,
1961
4.38M
      // Label 114: @2997
1962
4.38M
      GIM_Try, /*On fail goto*//*Label 115*/ 3042, // Rule ID 3990 //
1963
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1964
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1965
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1966
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1967
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1968
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1969
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1970
4.38M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1971
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64,
1972
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1973
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1974
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1975
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1976
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1977
4.38M
        // GIR_Coverage, 3990,
1978
4.38M
        GIR_Done,
1979
4.38M
      // Label 115: @3042
1980
4.38M
      GIM_Try, /*On fail goto*//*Label 116*/ 3087, // Rule ID 1313 //
1981
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
1982
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1983
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1984
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1985
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1986
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1987
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1988
4.38M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1989
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64,
1990
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1991
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1992
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1993
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
1994
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1995
4.38M
        // GIR_Coverage, 1313,
1996
4.38M
        GIR_Done,
1997
4.38M
      // Label 116: @3087
1998
4.38M
      GIM_Try, /*On fail goto*//*Label 117*/ 3132, // Rule ID 1373 //
1999
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2000
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2001
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2002
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2003
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2004
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2005
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2006
4.38M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
2007
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64,
2008
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2009
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
2010
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2011
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2012
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2013
4.38M
        // GIR_Coverage, 1373,
2014
4.38M
        GIR_Done,
2015
4.38M
      // Label 117: @3132
2016
4.38M
      GIM_Try, /*On fail goto*//*Label 118*/ 3151, // Rule ID 794 //
2017
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2018
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2019
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2020
4.38M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
2021
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i64,
2022
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2023
4.38M
        // GIR_Coverage, 794,
2024
4.38M
        GIR_Done,
2025
4.38M
      // Label 118: @3151
2026
4.38M
      GIM_Reject,
2027
4.38M
    // Label 99: @3152
2028
4.38M
    GIM_Reject,
2029
4.38M
    // Label 58: @3153
2030
4.38M
    GIM_Try, /*On fail goto*//*Label 119*/ 3765,
2031
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
2032
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
2033
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
2034
4.38M
      GIM_Try, /*On fail goto*//*Label 120*/ 3231, // Rule ID 3910 //
2035
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2036
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2037
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2038
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2039
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2040
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2041
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2042
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2043
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2044
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2045
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2046
4.38M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 320:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2047
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
2048
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2049
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2050
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2051
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2052
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2053
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2054
4.38M
        // GIR_Coverage, 3910,
2055
4.38M
        GIR_Done,
2056
4.38M
      // Label 120: @3231
2057
4.38M
      GIM_Try, /*On fail goto*//*Label 121*/ 3295, // Rule ID 3916 //
2058
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2059
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2060
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2061
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2062
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2063
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2064
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2065
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2066
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2067
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2068
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2069
4.38M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 378:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2070
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
2071
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2072
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2073
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2074
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2075
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2076
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2077
4.38M
        // GIR_Coverage, 3916,
2078
4.38M
        GIR_Done,
2079
4.38M
      // Label 121: @3295
2080
4.38M
      GIM_Try, /*On fail goto*//*Label 122*/ 3347, // Rule ID 3890 //
2081
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2082
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2083
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2084
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2085
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2086
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2087
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2088
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2089
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2090
4.38M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 321:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2091
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
2092
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2093
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2094
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2095
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2096
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2097
4.38M
        // GIR_Coverage, 3890,
2098
4.38M
        GIR_Done,
2099
4.38M
      // Label 122: @3347
2100
4.38M
      GIM_Try, /*On fail goto*//*Label 123*/ 3399, // Rule ID 3896 //
2101
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2102
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2103
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2104
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2105
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2106
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2107
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2108
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2109
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2110
4.38M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 379:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2111
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
2112
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2113
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2114
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2115
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2116
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2117
4.38M
        // GIR_Coverage, 3896,
2118
4.38M
        GIR_Done,
2119
4.38M
      // Label 123: @3399
2120
4.38M
      GIM_Try, /*On fail goto*//*Label 124*/ 3463, // Rule ID 986 //
2121
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2122
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2123
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2124
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2125
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2126
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2127
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2128
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2129
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2130
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2131
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2132
4.38M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 320:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2133
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
2134
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2135
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2136
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2137
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2138
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2139
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2140
4.38M
        // GIR_Coverage, 986,
2141
4.38M
        GIR_Done,
2142
4.38M
      // Label 124: @3463
2143
4.38M
      GIM_Try, /*On fail goto*//*Label 125*/ 3527, // Rule ID 1097 //
2144
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2145
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2146
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2147
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2148
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2149
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2150
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2151
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2152
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2153
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2154
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2155
4.38M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 378:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2156
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
2157
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2158
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2159
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2160
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2161
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2162
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2163
4.38M
        // GIR_Coverage, 1097,
2164
4.38M
        GIR_Done,
2165
4.38M
      // Label 125: @3527
2166
4.38M
      GIM_Try, /*On fail goto*//*Label 126*/ 3579, // Rule ID 710 //
2167
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2168
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2169
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2170
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2171
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2172
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2173
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2174
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2175
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2176
4.38M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 321:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2177
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
2178
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2179
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2180
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2181
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2182
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2183
4.38M
        // GIR_Coverage, 710,
2184
4.38M
        GIR_Done,
2185
4.38M
      // Label 126: @3579
2186
4.38M
      GIM_Try, /*On fail goto*//*Label 127*/ 3631, // Rule ID 754 //
2187
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2188
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2189
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2190
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2191
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2192
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2193
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2194
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2195
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2196
4.38M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 379:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2197
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
2198
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2199
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2200
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2201
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2202
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2203
4.38M
        // GIR_Coverage, 754,
2204
4.38M
        GIR_Done,
2205
4.38M
      // Label 127: @3631
2206
4.38M
      GIM_Try, /*On fail goto*//*Label 128*/ 3688, // Rule ID 3904 //
2207
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2208
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2209
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2210
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2211
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2212
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2213
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2214
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2215
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2216
4.38M
        // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (MLAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2217
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16,
2218
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2219
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2220
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2221
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2222
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2223
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2224
4.38M
        // GIR_Coverage, 3904,
2225
4.38M
        GIR_Done,
2226
4.38M
      // Label 128: @3688
2227
4.38M
      GIM_Try, /*On fail goto*//*Label 129*/ 3745, // Rule ID 966 //
2228
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2229
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2230
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2231
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2232
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2233
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2234
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2235
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2236
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2237
4.38M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (MLAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2238
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16,
2239
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2240
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2241
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2242
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2243
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2244
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2245
4.38M
        // GIR_Coverage, 966,
2246
4.38M
        GIR_Done,
2247
4.38M
      // Label 129: @3745
2248
4.38M
      GIM_Try, /*On fail goto*//*Label 130*/ 3764, // Rule ID 790 //
2249
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2250
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2251
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2252
4.38M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2253
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i16,
2254
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2255
4.38M
        // GIR_Coverage, 790,
2256
4.38M
        GIR_Done,
2257
4.38M
      // Label 130: @3764
2258
4.38M
      GIM_Reject,
2259
4.38M
    // Label 119: @3765
2260
4.38M
    GIM_Reject,
2261
4.38M
    // Label 59: @3766
2262
4.38M
    GIM_Try, /*On fail goto*//*Label 131*/ 5238,
2263
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2264
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2265
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
2266
4.38M
      GIM_Try, /*On fail goto*//*Label 132*/ 3857, // Rule ID 3964 //
2267
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2268
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2269
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2270
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2271
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2272
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2273
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2274
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2275
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2276
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2277
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2278
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2279
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2280
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2281
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2282
4.38M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 320:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2283
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
2284
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2285
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2286
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2287
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2288
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2289
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2290
4.38M
        // GIR_Coverage, 3964,
2291
4.38M
        GIR_Done,
2292
4.38M
      // Label 132: @3857
2293
4.38M
      GIM_Try, /*On fail goto*//*Label 133*/ 3934, // Rule ID 3982 //
2294
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2295
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2296
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2297
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2298
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2299
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2300
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2301
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2302
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2303
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2304
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2305
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2306
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2307
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2308
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2309
4.38M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 378:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2310
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
2311
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2312
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2313
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2314
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2315
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2316
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2317
4.38M
        // GIR_Coverage, 3982,
2318
4.38M
        GIR_Done,
2319
4.38M
      // Label 133: @3934
2320
4.38M
      GIM_Try, /*On fail goto*//*Label 134*/ 4011, // Rule ID 1293 //
2321
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2322
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2323
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2324
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2325
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2326
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2327
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2328
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2329
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2330
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2331
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2332
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2333
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2334
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2335
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2336
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 320:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2337
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
2338
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2339
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2340
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2341
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2342
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2343
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2344
4.38M
        // GIR_Coverage, 1293,
2345
4.38M
        GIR_Done,
2346
4.38M
      // Label 134: @4011
2347
4.38M
      GIM_Try, /*On fail goto*//*Label 135*/ 4088, // Rule ID 1359 //
2348
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2349
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2350
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2351
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2352
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2353
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2354
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2355
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2356
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2357
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2358
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2359
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2360
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2361
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2362
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2363
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 378:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2364
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
2365
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2366
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2367
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2368
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2369
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2370
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2371
4.38M
        // GIR_Coverage, 1359,
2372
4.38M
        GIR_Done,
2373
4.38M
      // Label 135: @4088
2374
4.38M
      GIM_Try, /*On fail goto*//*Label 136*/ 4152, // Rule ID 3913 //
2375
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2376
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2377
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2378
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2379
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2380
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2381
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2382
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2383
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2384
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2385
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2386
4.38M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 320:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2387
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
2388
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2389
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2390
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2391
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2392
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2393
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2394
4.38M
        // GIR_Coverage, 3913,
2395
4.38M
        GIR_Done,
2396
4.38M
      // Label 136: @4152
2397
4.38M
      GIM_Try, /*On fail goto*//*Label 137*/ 4216, // Rule ID 3919 //
2398
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2399
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2400
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2401
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2402
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2403
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2404
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2405
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2406
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2407
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2408
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2409
4.38M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 378:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2410
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
2411
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2412
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2413
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2414
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2415
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2416
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2417
4.38M
        // GIR_Coverage, 3919,
2418
4.38M
        GIR_Done,
2419
4.38M
      // Label 137: @4216
2420
4.38M
      GIM_Try, /*On fail goto*//*Label 138*/ 4280, // Rule ID 3976 //
2421
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2422
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2423
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2424
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2425
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
2426
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2427
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2428
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2429
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2430
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2431
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2432
4.38M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 337:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2433
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
2434
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2435
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2436
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2437
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2438
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2439
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2440
4.38M
        // GIR_Coverage, 3976,
2441
4.38M
        GIR_Done,
2442
4.38M
      // Label 138: @4280
2443
4.38M
      GIM_Try, /*On fail goto*//*Label 139*/ 4344, // Rule ID 3994 //
2444
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2445
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2446
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2447
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2448
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
2449
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2450
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2451
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2452
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2453
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2454
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2455
4.38M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 391:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2456
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
2457
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2458
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2459
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2460
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2461
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2462
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2463
4.38M
        // GIR_Coverage, 3994,
2464
4.38M
        GIR_Done,
2465
4.38M
      // Label 139: @4344
2466
4.38M
      GIM_Try, /*On fail goto*//*Label 140*/ 4396, // Rule ID 3893 //
2467
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2468
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2469
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2470
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2471
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2472
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2473
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2474
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2475
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2476
4.38M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 321:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2477
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
2478
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2479
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2480
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2481
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2482
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2483
4.38M
        // GIR_Coverage, 3893,
2484
4.38M
        GIR_Done,
2485
4.38M
      // Label 140: @4396
2486
4.38M
      GIM_Try, /*On fail goto*//*Label 141*/ 4448, // Rule ID 3899 //
2487
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2488
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2489
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2490
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2491
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2492
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2493
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2494
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2495
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2496
4.38M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 379:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2497
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32,
2498
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2499
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2500
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2501
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2502
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2503
4.38M
        // GIR_Coverage, 3899,
2504
4.38M
        GIR_Done,
2505
4.38M
      // Label 141: @4448
2506
4.38M
      GIM_Try, /*On fail goto*//*Label 142*/ 4512, // Rule ID 989 //
2507
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2508
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2509
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2510
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2511
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2512
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2513
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2514
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2515
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2516
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2517
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2518
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 320:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2519
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
2520
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2521
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2522
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2523
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2524
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2525
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2526
4.38M
        // GIR_Coverage, 989,
2527
4.38M
        GIR_Done,
2528
4.38M
      // Label 142: @4512
2529
4.38M
      GIM_Try, /*On fail goto*//*Label 143*/ 4576, // Rule ID 1100 //
2530
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2531
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2532
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2533
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2534
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2535
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2536
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2537
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2538
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2539
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2540
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2541
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 378:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2542
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
2543
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2544
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2545
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2546
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2547
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2548
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2549
4.38M
        // GIR_Coverage, 1100,
2550
4.38M
        GIR_Done,
2551
4.38M
      // Label 143: @4576
2552
4.38M
      GIM_Try, /*On fail goto*//*Label 144*/ 4640, // Rule ID 1317 //
2553
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2554
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2555
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2556
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2557
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2558
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
2559
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2560
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2561
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2562
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2563
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2564
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 337:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2565
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
2566
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2567
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2568
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2569
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2570
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2571
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2572
4.38M
        // GIR_Coverage, 1317,
2573
4.38M
        GIR_Done,
2574
4.38M
      // Label 144: @4640
2575
4.38M
      GIM_Try, /*On fail goto*//*Label 145*/ 4704, // Rule ID 1377 //
2576
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2577
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2578
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2579
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2580
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2581
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
2582
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2583
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2584
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2585
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2586
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2587
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 391:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2588
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
2589
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2590
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2591
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2592
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2593
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2594
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2595
4.38M
        // GIR_Coverage, 1377,
2596
4.38M
        GIR_Done,
2597
4.38M
      // Label 145: @4704
2598
4.38M
      GIM_Try, /*On fail goto*//*Label 146*/ 4756, // Rule ID 713 //
2599
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2600
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2601
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2602
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2603
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2604
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2605
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2606
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2607
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2608
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 321:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2609
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
2610
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2611
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2612
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2613
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2614
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2615
4.38M
        // GIR_Coverage, 713,
2616
4.38M
        GIR_Done,
2617
4.38M
      // Label 146: @4756
2618
4.38M
      GIM_Try, /*On fail goto*//*Label 147*/ 4808, // Rule ID 757 //
2619
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2620
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2621
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2622
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2623
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2624
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2625
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2626
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2627
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2628
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 379:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2629
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32,
2630
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2631
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2632
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2633
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2634
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2635
4.38M
        // GIR_Coverage, 757,
2636
4.38M
        GIR_Done,
2637
4.38M
      // Label 147: @4808
2638
4.38M
      GIM_Try, /*On fail goto*//*Label 148*/ 4866, // Rule ID 1305 //
2639
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2640
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2641
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2642
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2643
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2644
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2645
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2646
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2647
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2648
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2649
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2650
4.38M
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2651
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv4i16_v4i32,
2652
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2653
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2654
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
2655
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2656
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2657
4.38M
        // GIR_Coverage, 1305,
2658
4.38M
        GIR_Done,
2659
4.38M
      // Label 148: @4866
2660
4.38M
      GIM_Try, /*On fail goto*//*Label 149*/ 4924, // Rule ID 1365 //
2661
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2662
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2663
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2664
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2665
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2666
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2667
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2668
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2669
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2670
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2671
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2672
4.38M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2673
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32,
2674
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2675
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2676
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
2677
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2678
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2679
4.38M
        // GIR_Coverage, 1365,
2680
4.38M
        GIR_Done,
2681
4.38M
      // Label 149: @4924
2682
4.38M
      GIM_Try, /*On fail goto*//*Label 150*/ 4981, // Rule ID 3907 //
2683
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2684
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2685
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2686
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2687
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2688
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2689
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2690
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2691
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2692
4.38M
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (MLAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2693
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32,
2694
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2695
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2696
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2697
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2698
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2699
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2700
4.38M
        // GIR_Coverage, 3907,
2701
4.38M
        GIR_Done,
2702
4.38M
      // Label 150: @4981
2703
4.38M
      GIM_Try, /*On fail goto*//*Label 151*/ 5026, // Rule ID 3970 //
2704
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2705
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2706
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2707
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2708
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2709
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2710
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2711
4.38M
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2712
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32,
2713
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2714
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
2715
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2716
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2717
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2718
4.38M
        // GIR_Coverage, 3970,
2719
4.38M
        GIR_Done,
2720
4.38M
      // Label 151: @5026
2721
4.38M
      GIM_Try, /*On fail goto*//*Label 152*/ 5071, // Rule ID 3988 //
2722
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2723
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2724
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2725
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2726
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2727
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2728
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2729
4.38M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2730
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32,
2731
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2732
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
2733
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2734
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2735
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2736
4.38M
        // GIR_Coverage, 3988,
2737
4.38M
        GIR_Done,
2738
4.38M
      // Label 152: @5071
2739
4.38M
      GIM_Try, /*On fail goto*//*Label 153*/ 5128, // Rule ID 969 //
2740
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2741
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2742
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2743
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2744
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2745
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2746
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2747
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2748
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2749
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (MLAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2750
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32,
2751
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2752
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2753
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2754
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2755
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2756
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2757
4.38M
        // GIR_Coverage, 969,
2758
4.38M
        GIR_Done,
2759
4.38M
      // Label 153: @5128
2760
4.38M
      GIM_Try, /*On fail goto*//*Label 154*/ 5173, // Rule ID 1311 //
2761
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2762
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2763
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2764
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2765
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2766
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2767
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2768
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2769
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32,
2770
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2771
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
2772
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2773
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2774
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2775
4.38M
        // GIR_Coverage, 1311,
2776
4.38M
        GIR_Done,
2777
4.38M
      // Label 154: @5173
2778
4.38M
      GIM_Try, /*On fail goto*//*Label 155*/ 5218, // Rule ID 1371 //
2779
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2780
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2781
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2782
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2783
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2784
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2785
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2786
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2787
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32,
2788
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2789
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
2790
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2791
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2792
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2793
4.38M
        // GIR_Coverage, 1371,
2794
4.38M
        GIR_Done,
2795
4.38M
      // Label 155: @5218
2796
4.38M
      GIM_Try, /*On fail goto*//*Label 156*/ 5237, // Rule ID 793 //
2797
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2798
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2799
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2800
4.38M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2801
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i32,
2802
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2803
4.38M
        // GIR_Coverage, 793,
2804
4.38M
        GIR_Done,
2805
4.38M
      // Label 156: @5237
2806
4.38M
      GIM_Reject,
2807
4.38M
    // Label 131: @5238
2808
4.38M
    GIM_Reject,
2809
4.38M
    // Label 60: @5239
2810
4.38M
    GIM_Try, /*On fail goto*//*Label 157*/ 5643,
2811
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
2812
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
2813
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
2814
4.38M
      GIM_Try, /*On fail goto*//*Label 158*/ 5317, // Rule ID 3908 //
2815
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2816
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2817
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2818
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2819
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2820
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2821
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2822
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2823
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2824
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2825
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2826
4.38M
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 320:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2827
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
2828
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2829
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2830
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2831
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2832
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2833
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2834
4.38M
        // GIR_Coverage, 3908,
2835
4.38M
        GIR_Done,
2836
4.38M
      // Label 158: @5317
2837
4.38M
      GIM_Try, /*On fail goto*//*Label 159*/ 5381, // Rule ID 3914 //
2838
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2839
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2840
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2841
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2842
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2843
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2844
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2845
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2846
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2847
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2848
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2849
4.38M
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 378:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2850
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
2851
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2852
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2853
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2854
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2855
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2856
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2857
4.38M
        // GIR_Coverage, 3914,
2858
4.38M
        GIR_Done,
2859
4.38M
      // Label 159: @5381
2860
4.38M
      GIM_Try, /*On fail goto*//*Label 160*/ 5445, // Rule ID 984 //
2861
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2862
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2863
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2864
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2865
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2866
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2867
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2868
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2869
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2870
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2871
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2872
4.38M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 320:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2873
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
2874
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2875
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2876
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2877
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2878
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2879
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2880
4.38M
        // GIR_Coverage, 984,
2881
4.38M
        GIR_Done,
2882
4.38M
      // Label 160: @5445
2883
4.38M
      GIM_Try, /*On fail goto*//*Label 161*/ 5509, // Rule ID 1095 //
2884
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2885
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2886
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2887
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2888
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2889
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2890
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2891
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2892
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2893
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2894
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2895
4.38M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 378:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2896
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
2897
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2898
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2899
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2900
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2901
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2902
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2903
4.38M
        // GIR_Coverage, 1095,
2904
4.38M
        GIR_Done,
2905
4.38M
      // Label 161: @5509
2906
4.38M
      GIM_Try, /*On fail goto*//*Label 162*/ 5566, // Rule ID 3902 //
2907
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2908
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2909
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2910
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2911
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2912
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2913
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2914
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2915
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2916
4.38M
        // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (MLAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2917
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8,
2918
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2919
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2920
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2921
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2922
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2923
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2924
4.38M
        // GIR_Coverage, 3902,
2925
4.38M
        GIR_Done,
2926
4.38M
      // Label 162: @5566
2927
4.38M
      GIM_Try, /*On fail goto*//*Label 163*/ 5623, // Rule ID 964 //
2928
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2929
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2930
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2931
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2932
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2933
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2934
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2935
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2936
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2937
4.38M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (MLAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2938
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8,
2939
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2940
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2941
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2942
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2943
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2944
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2945
4.38M
        // GIR_Coverage, 964,
2946
4.38M
        GIR_Done,
2947
4.38M
      // Label 163: @5623
2948
4.38M
      GIM_Try, /*On fail goto*//*Label 164*/ 5642, // Rule ID 788 //
2949
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2950
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2951
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2952
4.38M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2953
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i8,
2954
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2955
4.38M
        // GIR_Coverage, 788,
2956
4.38M
        GIR_Done,
2957
4.38M
      // Label 164: @5642
2958
4.38M
      GIM_Reject,
2959
4.38M
    // Label 157: @5643
2960
4.38M
    GIM_Reject,
2961
4.38M
    // Label 61: @5644
2962
4.38M
    GIM_Try, /*On fail goto*//*Label 165*/ 7116,
2963
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2964
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2965
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
2966
4.38M
      GIM_Try, /*On fail goto*//*Label 166*/ 5735, // Rule ID 3962 //
2967
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2968
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2969
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2970
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2971
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2972
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2973
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2974
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2975
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2976
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2977
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2978
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2979
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2980
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2981
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2982
4.38M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 320:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2983
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
2984
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2985
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2986
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2987
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2988
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
2989
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2990
4.38M
        // GIR_Coverage, 3962,
2991
4.38M
        GIR_Done,
2992
4.38M
      // Label 166: @5735
2993
4.38M
      GIM_Try, /*On fail goto*//*Label 167*/ 5812, // Rule ID 3980 //
2994
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
2995
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2996
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2997
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2998
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2999
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3000
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3001
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3002
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3003
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3004
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3005
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3006
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3007
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3008
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3009
4.38M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 378:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3010
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
3011
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3012
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3013
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
3014
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
3015
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3016
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3017
4.38M
        // GIR_Coverage, 3980,
3018
4.38M
        GIR_Done,
3019
4.38M
      // Label 167: @5812
3020
4.38M
      GIM_Try, /*On fail goto*//*Label 168*/ 5889, // Rule ID 1291 //
3021
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3022
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3023
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3024
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3025
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3026
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3027
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3028
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3029
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3030
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3031
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3032
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3033
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3034
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3035
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3036
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 320:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3037
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
3038
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3039
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3040
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
3041
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
3042
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3043
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3044
4.38M
        // GIR_Coverage, 1291,
3045
4.38M
        GIR_Done,
3046
4.38M
      // Label 168: @5889
3047
4.38M
      GIM_Try, /*On fail goto*//*Label 169*/ 5966, // Rule ID 1357 //
3048
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3049
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3050
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3051
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3052
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3053
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3054
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3055
4.38M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3056
4.38M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3057
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3058
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3059
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3060
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3061
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3062
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3063
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 378:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3064
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
3065
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3066
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3067
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
3068
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
3069
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3070
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3071
4.38M
        // GIR_Coverage, 1357,
3072
4.38M
        GIR_Done,
3073
4.38M
      // Label 169: @5966
3074
4.38M
      GIM_Try, /*On fail goto*//*Label 170*/ 6030, // Rule ID 3911 //
3075
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3076
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3077
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3078
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3079
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3080
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3081
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3082
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3083
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3084
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3085
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3086
4.38M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 320:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3087
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
3088
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3089
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3090
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3091
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3092
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3093
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3094
4.38M
        // GIR_Coverage, 3911,
3095
4.38M
        GIR_Done,
3096
4.38M
      // Label 170: @6030
3097
4.38M
      GIM_Try, /*On fail goto*//*Label 171*/ 6094, // Rule ID 3917 //
3098
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3099
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3100
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3101
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3102
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3103
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3104
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3105
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3106
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3107
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3108
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3109
4.38M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 378:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3110
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
3111
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3112
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3113
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3114
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3115
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3116
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3117
4.38M
        // GIR_Coverage, 3917,
3118
4.38M
        GIR_Done,
3119
4.38M
      // Label 171: @6094
3120
4.38M
      GIM_Try, /*On fail goto*//*Label 172*/ 6158, // Rule ID 3974 //
3121
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3122
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3123
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3124
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3125
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
3126
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3127
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3128
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3129
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3130
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3131
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3132
4.38M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 337:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3133
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
3134
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3135
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3136
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3137
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3138
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3139
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3140
4.38M
        // GIR_Coverage, 3974,
3141
4.38M
        GIR_Done,
3142
4.38M
      // Label 172: @6158
3143
4.38M
      GIM_Try, /*On fail goto*//*Label 173*/ 6222, // Rule ID 3992 //
3144
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3145
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3146
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3147
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3148
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
3149
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3150
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3151
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3152
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3153
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3154
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3155
4.38M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 391:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3156
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
3157
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3158
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3159
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3160
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3161
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3162
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3163
4.38M
        // GIR_Coverage, 3992,
3164
4.38M
        GIR_Done,
3165
4.38M
      // Label 173: @6222
3166
4.38M
      GIM_Try, /*On fail goto*//*Label 174*/ 6274, // Rule ID 3891 //
3167
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3168
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3169
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3170
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3171
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
3172
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3173
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3174
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3175
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3176
4.38M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 321:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3177
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
3178
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3179
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3180
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3181
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3182
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3183
4.38M
        // GIR_Coverage, 3891,
3184
4.38M
        GIR_Done,
3185
4.38M
      // Label 174: @6274
3186
4.38M
      GIM_Try, /*On fail goto*//*Label 175*/ 6326, // Rule ID 3897 //
3187
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3188
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3189
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3190
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3191
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
3192
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3193
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3194
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3195
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3196
4.38M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 379:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3197
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
3198
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3199
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3200
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3201
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3202
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3203
4.38M
        // GIR_Coverage, 3897,
3204
4.38M
        GIR_Done,
3205
4.38M
      // Label 175: @6326
3206
4.38M
      GIM_Try, /*On fail goto*//*Label 176*/ 6390, // Rule ID 987 //
3207
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3208
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3209
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3210
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3211
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3212
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3213
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3214
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3215
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3216
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3217
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3218
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 320:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3219
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
3220
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3221
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3222
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3223
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3224
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3225
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3226
4.38M
        // GIR_Coverage, 987,
3227
4.38M
        GIR_Done,
3228
4.38M
      // Label 176: @6390
3229
4.38M
      GIM_Try, /*On fail goto*//*Label 177*/ 6454, // Rule ID 1098 //
3230
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3231
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3232
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3233
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3234
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3235
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3236
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3237
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3238
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3239
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3240
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3241
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 378:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3242
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
3243
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3244
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3245
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3246
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3247
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3248
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3249
4.38M
        // GIR_Coverage, 1098,
3250
4.38M
        GIR_Done,
3251
4.38M
      // Label 177: @6454
3252
4.38M
      GIM_Try, /*On fail goto*//*Label 178*/ 6518, // Rule ID 1315 //
3253
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3254
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3255
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3256
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3257
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3258
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
3259
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3260
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3261
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3262
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3263
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3264
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 337:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3265
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
3266
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3267
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3268
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3269
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3270
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3271
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3272
4.38M
        // GIR_Coverage, 1315,
3273
4.38M
        GIR_Done,
3274
4.38M
      // Label 178: @6518
3275
4.38M
      GIM_Try, /*On fail goto*//*Label 179*/ 6582, // Rule ID 1375 //
3276
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3277
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3278
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3279
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3280
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3281
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
3282
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3283
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3284
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3285
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3286
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3287
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 391:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3288
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
3289
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3290
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3291
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3292
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3293
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3294
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3295
4.38M
        // GIR_Coverage, 1375,
3296
4.38M
        GIR_Done,
3297
4.38M
      // Label 179: @6582
3298
4.38M
      GIM_Try, /*On fail goto*//*Label 180*/ 6634, // Rule ID 711 //
3299
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3300
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3301
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3302
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3303
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3304
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
3305
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3306
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3307
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3308
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 321:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3309
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
3310
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3311
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3312
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3313
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3314
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3315
4.38M
        // GIR_Coverage, 711,
3316
4.38M
        GIR_Done,
3317
4.38M
      // Label 180: @6634
3318
4.38M
      GIM_Try, /*On fail goto*//*Label 181*/ 6686, // Rule ID 755 //
3319
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3320
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3321
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3322
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3323
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3324
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
3325
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3326
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3327
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3328
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 379:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3329
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
3330
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3331
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3332
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3333
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3334
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3335
4.38M
        // GIR_Coverage, 755,
3336
4.38M
        GIR_Done,
3337
4.38M
      // Label 181: @6686
3338
4.38M
      GIM_Try, /*On fail goto*//*Label 182*/ 6744, // Rule ID 1303 //
3339
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3340
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3341
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3342
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3343
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3344
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3345
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3346
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3347
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3348
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3349
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3350
4.38M
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3351
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv8i8_v8i16,
3352
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3353
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3354
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3355
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3356
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3357
4.38M
        // GIR_Coverage, 1303,
3358
4.38M
        GIR_Done,
3359
4.38M
      // Label 182: @6744
3360
4.38M
      GIM_Try, /*On fail goto*//*Label 183*/ 6802, // Rule ID 1363 //
3361
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3362
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3363
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3364
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3365
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3366
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3367
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3368
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3369
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3370
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3371
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3372
4.38M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3373
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16,
3374
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3375
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3376
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3377
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3378
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3379
4.38M
        // GIR_Coverage, 1363,
3380
4.38M
        GIR_Done,
3381
4.38M
      // Label 183: @6802
3382
4.38M
      GIM_Try, /*On fail goto*//*Label 184*/ 6859, // Rule ID 3905 //
3383
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3384
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3385
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3386
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3387
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3388
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3389
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3390
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3391
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3392
4.38M
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (MLAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3393
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16,
3394
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3395
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3396
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3397
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3398
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3399
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3400
4.38M
        // GIR_Coverage, 3905,
3401
4.38M
        GIR_Done,
3402
4.38M
      // Label 184: @6859
3403
4.38M
      GIM_Try, /*On fail goto*//*Label 185*/ 6904, // Rule ID 3968 //
3404
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3405
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3406
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3407
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3408
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3409
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3410
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3411
4.38M
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3412
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16,
3413
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3414
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3415
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3416
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3417
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3418
4.38M
        // GIR_Coverage, 3968,
3419
4.38M
        GIR_Done,
3420
4.38M
      // Label 185: @6904
3421
4.38M
      GIM_Try, /*On fail goto*//*Label 186*/ 6949, // Rule ID 3986 //
3422
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3423
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3424
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3425
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3426
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3427
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3428
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3429
4.38M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3430
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16,
3431
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3432
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3433
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3434
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3435
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3436
4.38M
        // GIR_Coverage, 3986,
3437
4.38M
        GIR_Done,
3438
4.38M
      // Label 186: @6949
3439
4.38M
      GIM_Try, /*On fail goto*//*Label 187*/ 7006, // Rule ID 967 //
3440
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3441
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3442
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3443
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3444
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3445
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3446
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3447
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3448
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3449
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (MLAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3450
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16,
3451
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3452
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3453
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3454
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3455
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3456
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3457
4.38M
        // GIR_Coverage, 967,
3458
4.38M
        GIR_Done,
3459
4.38M
      // Label 187: @7006
3460
4.38M
      GIM_Try, /*On fail goto*//*Label 188*/ 7051, // Rule ID 1309 //
3461
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3462
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3463
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3464
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3465
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3466
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3467
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3468
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3469
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16,
3470
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3471
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3472
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3473
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3474
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3475
4.38M
        // GIR_Coverage, 1309,
3476
4.38M
        GIR_Done,
3477
4.38M
      // Label 188: @7051
3478
4.38M
      GIM_Try, /*On fail goto*//*Label 189*/ 7096, // Rule ID 1369 //
3479
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3480
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3481
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3482
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3483
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3484
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3485
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3486
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3487
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16,
3488
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3489
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3490
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3491
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3492
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3493
4.38M
        // GIR_Coverage, 1369,
3494
4.38M
        GIR_Done,
3495
4.38M
      // Label 189: @7096
3496
4.38M
      GIM_Try, /*On fail goto*//*Label 190*/ 7115, // Rule ID 791 //
3497
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3498
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3499
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3500
4.38M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3501
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i16,
3502
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3503
4.38M
        // GIR_Coverage, 791,
3504
4.38M
        GIR_Done,
3505
4.38M
      // Label 190: @7115
3506
4.38M
      GIM_Reject,
3507
4.38M
    // Label 165: @7116
3508
4.38M
    GIM_Reject,
3509
4.38M
    // Label 62: @7117
3510
4.38M
    GIM_Try, /*On fail goto*//*Label 191*/ 7521,
3511
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3512
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3513
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
3514
4.38M
      GIM_Try, /*On fail goto*//*Label 192*/ 7195, // Rule ID 3909 //
3515
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3516
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3517
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3518
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3519
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3520
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3521
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3522
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3523
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3524
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3525
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3526
4.38M
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 320:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3527
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
3528
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3529
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3530
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3531
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3532
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3533
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3534
4.38M
        // GIR_Coverage, 3909,
3535
4.38M
        GIR_Done,
3536
4.38M
      // Label 192: @7195
3537
4.38M
      GIM_Try, /*On fail goto*//*Label 193*/ 7259, // Rule ID 3915 //
3538
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3539
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3540
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3541
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3542
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3543
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3544
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3545
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3546
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3547
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3548
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3549
4.38M
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 378:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3550
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
3551
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3552
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3553
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3554
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3555
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3556
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3557
4.38M
        // GIR_Coverage, 3915,
3558
4.38M
        GIR_Done,
3559
4.38M
      // Label 193: @7259
3560
4.38M
      GIM_Try, /*On fail goto*//*Label 194*/ 7323, // Rule ID 985 //
3561
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3562
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3563
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3564
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3565
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3566
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3567
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3568
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3569
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3570
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3571
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3572
4.38M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 320:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3573
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
3574
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3575
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3576
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3577
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3578
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3579
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3580
4.38M
        // GIR_Coverage, 985,
3581
4.38M
        GIR_Done,
3582
4.38M
      // Label 194: @7323
3583
4.38M
      GIM_Try, /*On fail goto*//*Label 195*/ 7387, // Rule ID 1096 //
3584
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3585
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3586
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3587
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3588
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3589
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3590
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3591
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3592
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3593
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3594
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3595
4.38M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 378:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3596
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
3597
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3598
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3599
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3600
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3601
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3602
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3603
4.38M
        // GIR_Coverage, 1096,
3604
4.38M
        GIR_Done,
3605
4.38M
      // Label 195: @7387
3606
4.38M
      GIM_Try, /*On fail goto*//*Label 196*/ 7444, // Rule ID 3903 //
3607
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3608
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3609
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3610
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3611
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3612
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3613
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3614
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3615
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3616
4.38M
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (MLAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3617
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8,
3618
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3619
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3620
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3621
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3622
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3623
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3624
4.38M
        // GIR_Coverage, 3903,
3625
4.38M
        GIR_Done,
3626
4.38M
      // Label 196: @7444
3627
4.38M
      GIM_Try, /*On fail goto*//*Label 197*/ 7501, // Rule ID 965 //
3628
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3629
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3630
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3631
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3632
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3633
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3634
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3635
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3636
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3637
4.38M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (MLAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3638
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8,
3639
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3640
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3641
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3642
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3643
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3644
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3645
4.38M
        // GIR_Coverage, 965,
3646
4.38M
        GIR_Done,
3647
4.38M
      // Label 197: @7501
3648
4.38M
      GIM_Try, /*On fail goto*//*Label 198*/ 7520, // Rule ID 789 //
3649
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
3650
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3651
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3652
4.38M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3653
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv16i8,
3654
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3655
4.38M
        // GIR_Coverage, 789,
3656
4.38M
        GIR_Done,
3657
4.38M
      // Label 198: @7520
3658
4.38M
      GIM_Reject,
3659
4.38M
    // Label 191: @7521
3660
4.38M
    GIM_Reject,
3661
4.38M
    // Label 63: @7522
3662
4.38M
    GIM_Reject,
3663
4.38M
    // Label 1: @7523
3664
4.38M
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 208*/ 10103,
3665
4.38M
    /*GILLT_s32*//*Label 199*/ 7539,
3666
4.38M
    /*GILLT_s64*//*Label 200*/ 7659, 0,
3667
4.38M
    /*GILLT_v2s32*//*Label 201*/ 8530,
3668
4.38M
    /*GILLT_v2s64*//*Label 202*/ 8618,
3669
4.38M
    /*GILLT_v4s16*//*Label 203*/ 8987,
3670
4.38M
    /*GILLT_v4s32*//*Label 204*/ 9075,
3671
4.38M
    /*GILLT_v8s8*//*Label 205*/ 9501,
3672
4.38M
    /*GILLT_v8s16*//*Label 206*/ 9589,
3673
4.38M
    /*GILLT_v16s8*//*Label 207*/ 10015,
3674
4.38M
    // Label 199: @7539
3675
4.38M
    GIM_Try, /*On fail goto*//*Label 209*/ 7658,
3676
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3677
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3678
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
3679
4.38M
      GIM_Try, /*On fail goto*//*Label 210*/ 7607, // Rule ID 1899 //
3680
4.38M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3681
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3682
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3683
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3684
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3685
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3686
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
3687
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3688
4.38M
        // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
3689
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
3690
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3691
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3692
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3693
4.38M
        GIR_AddRegister, /*InsnID*/0, AArch64::WZR,
3694
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3695
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3696
4.38M
        // GIR_Coverage, 1899,
3697
4.38M
        GIR_Done,
3698
4.38M
      // Label 210: @7607
3699
4.38M
      GIM_Try, /*On fail goto*//*Label 211*/ 7637, // Rule ID 1865 //
3700
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
3701
4.38M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
3702
4.38M
        // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
3703
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri,
3704
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3705
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3706
4.38M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
3707
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3708
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3709
4.38M
        // GIR_Coverage, 1865,
3710
4.38M
        GIR_Done,
3711
4.38M
      // Label 211: @7637
3712
4.38M
      GIM_Try, /*On fail goto*//*Label 212*/ 7657, // Rule ID 1867 //
3713
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3714
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
3715
4.38M
        // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SUBSWrr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
3716
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSWrr,
3717
4.38M
        GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV,
3718
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3719
4.38M
        // GIR_Coverage, 1867,
3720
4.38M
        GIR_Done,
3721
4.38M
      // Label 212: @7657
3722
4.38M
      GIM_Reject,
3723
4.38M
    // Label 209: @7658
3724
4.38M
    GIM_Reject,
3725
4.38M
    // Label 200: @7659
3726
4.38M
    GIM_Try, /*On fail goto*//*Label 213*/ 8529,
3727
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3728
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3729
4.38M
      GIM_Try, /*On fail goto*//*Label 214*/ 7764, // Rule ID 1910 //
3730
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3731
4.38M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3732
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3733
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3734
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3735
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3736
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3737
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3738
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3739
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3740
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3741
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3742
4.38M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
3743
4.38M
        // MIs[3] Operand 1
3744
4.38M
        // No operand predicates
3745
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3746
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3747
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3748
4.38M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
3749
4.38M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3750
4.38M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3751
4.38M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3752
4.38M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3753
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3754
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3755
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3756
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3757
4.38M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3758
4.38M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3759
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3760
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3761
4.38M
        // GIR_Coverage, 1910,
3762
4.38M
        GIR_Done,
3763
4.38M
      // Label 214: @7764
3764
4.38M
      GIM_Try, /*On fail goto*//*Label 215*/ 7859, // Rule ID 1911 //
3765
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3766
4.38M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3767
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3768
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3769
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3770
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3771
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3772
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3773
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3774
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3775
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3776
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3777
4.38M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
3778
4.38M
        // MIs[3] Operand 1
3779
4.38M
        // No operand predicates
3780
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3781
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3782
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3783
4.38M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
3784
4.38M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3785
4.38M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3786
4.38M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3787
4.38M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3788
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3789
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3790
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3791
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3792
4.38M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3793
4.38M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3794
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3795
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3796
4.38M
        // GIR_Coverage, 1911,
3797
4.38M
        GIR_Done,
3798
4.38M
      // Label 215: @7859
3799
4.38M
      GIM_Try, /*On fail goto*//*Label 216*/ 7943, // Rule ID 1905 //
3800
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3801
4.38M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3802
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3803
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3804
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3805
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3806
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3807
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3808
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3809
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3810
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3811
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
3812
4.38M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3813
4.38M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3814
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3815
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3816
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3817
4.38M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
3818
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3819
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3820
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3821
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3822
4.38M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3823
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3824
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3825
4.38M
        // GIR_Coverage, 1905,
3826
4.38M
        GIR_Done,
3827
4.38M
      // Label 216: @7943
3828
4.38M
      GIM_Try, /*On fail goto*//*Label 217*/ 8027, // Rule ID 1906 //
3829
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3830
4.38M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3831
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3832
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3833
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3834
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3835
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3836
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3837
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3838
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3839
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3840
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
3841
4.38M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3842
4.38M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3843
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3844
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3845
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3846
4.38M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
3847
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3848
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3849
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3850
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3851
4.38M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3852
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3853
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3854
4.38M
        // GIR_Coverage, 1906,
3855
4.38M
        GIR_Done,
3856
4.38M
      // Label 217: @8027
3857
4.38M
      GIM_Try, /*On fail goto*//*Label 218*/ 8123, // Rule ID 1916 //
3858
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3859
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3860
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3861
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3862
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3863
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3864
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3865
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3866
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3867
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3868
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3869
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3870
4.38M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
3871
4.38M
        // MIs[3] Operand 1
3872
4.38M
        // No operand predicates
3873
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3874
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3875
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3876
4.38M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
3877
4.38M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3878
4.38M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3879
4.38M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3880
4.38M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3881
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3882
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3883
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3884
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3885
4.38M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3886
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3887
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3888
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3889
4.38M
        // GIR_Coverage, 1916,
3890
4.38M
        GIR_Done,
3891
4.38M
      // Label 218: @8123
3892
4.38M
      GIM_Try, /*On fail goto*//*Label 219*/ 8219, // Rule ID 1917 //
3893
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3894
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3895
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3896
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3897
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3898
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3899
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3900
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3901
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3902
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3903
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3904
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3905
4.38M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
3906
4.38M
        // MIs[3] Operand 1
3907
4.38M
        // No operand predicates
3908
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3909
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3910
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3911
4.38M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
3912
4.38M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3913
4.38M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3914
4.38M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3915
4.38M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3916
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3917
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3918
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3919
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3920
4.38M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3921
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3922
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3923
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3924
4.38M
        // GIR_Coverage, 1917,
3925
4.38M
        GIR_Done,
3926
4.38M
      // Label 219: @8219
3927
4.38M
      GIM_Try, /*On fail goto*//*Label 220*/ 8304, // Rule ID 83 //
3928
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3929
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3930
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3931
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3932
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3933
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3934
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3935
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3936
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3937
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3938
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3939
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
3940
4.38M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3941
4.38M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3942
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3943
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3944
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3945
4.38M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
3946
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3947
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3948
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3949
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3950
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3951
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3952
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3953
4.38M
        // GIR_Coverage, 83,
3954
4.38M
        GIR_Done,
3955
4.38M
      // Label 220: @8304
3956
4.38M
      GIM_Try, /*On fail goto*//*Label 221*/ 8389, // Rule ID 85 //
3957
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3958
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3959
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3960
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3961
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3962
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3963
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3964
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3965
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3966
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3967
4.38M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3968
4.38M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
3969
4.38M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3970
4.38M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3971
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3972
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3973
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3974
4.38M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
3975
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3976
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3977
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3978
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3979
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3980
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
3981
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3982
4.38M
        // GIR_Coverage, 85,
3983
4.38M
        GIR_Done,
3984
4.38M
      // Label 221: @8389
3985
4.38M
      GIM_Try, /*On fail goto*//*Label 222*/ 8447, // Rule ID 1900 //
3986
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3987
4.38M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3988
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3989
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3990
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3991
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3992
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3993
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
3994
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3995
4.38M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
3996
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
3997
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3998
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3999
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4000
4.38M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
4001
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4002
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4003
4.38M
        // GIR_Coverage, 1900,
4004
4.38M
        GIR_Done,
4005
4.38M
      // Label 222: @8447
4006
4.38M
      GIM_Try, /*On fail goto*//*Label 223*/ 8481, // Rule ID 1866 //
4007
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
4008
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
4009
4.38M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
4010
4.38M
        // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
4011
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri,
4012
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4013
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4014
4.38M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
4015
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4016
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4017
4.38M
        // GIR_Coverage, 1866,
4018
4.38M
        GIR_Done,
4019
4.38M
      // Label 223: @8481
4020
4.38M
      GIM_Try, /*On fail goto*//*Label 224*/ 8504, // Rule ID 1250 //
4021
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4022
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4023
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4024
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4025
4.38M
        // (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
4026
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv1i64,
4027
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4028
4.38M
        // GIR_Coverage, 1250,
4029
4.38M
        GIR_Done,
4030
4.38M
      // Label 224: @8504
4031
4.38M
      GIM_Try, /*On fail goto*//*Label 225*/ 8528, // Rule ID 1868 //
4032
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
4033
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
4034
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
4035
4.38M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SUBSXrr:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
4036
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSXrr,
4037
4.38M
        GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV,
4038
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4039
4.38M
        // GIR_Coverage, 1868,
4040
4.38M
        GIR_Done,
4041
4.38M
      // Label 225: @8528
4042
4.38M
      GIM_Reject,
4043
4.38M
    // Label 213: @8529
4044
4.38M
    GIM_Reject,
4045
4.38M
    // Label 201: @8530
4046
4.38M
    GIM_Try, /*On fail goto*//*Label 226*/ 8617,
4047
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
4048
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
4049
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4050
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4051
4.38M
      GIM_Try, /*On fail goto*//*Label 227*/ 8601, // Rule ID 974 //
4052
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4053
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4054
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4055
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4056
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4057
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4058
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4059
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4060
4.38M
        // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (MLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4061
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv2i32,
4062
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4063
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4064
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4065
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4066
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4067
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4068
4.38M
        // GIR_Coverage, 974,
4069
4.38M
        GIR_Done,
4070
4.38M
      // Label 227: @8601
4071
4.38M
      GIM_Try, /*On fail goto*//*Label 228*/ 8616, // Rule ID 1092 //
4072
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4073
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4074
4.38M
        // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4075
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i32,
4076
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4077
4.38M
        // GIR_Coverage, 1092,
4078
4.38M
        GIR_Done,
4079
4.38M
      // Label 228: @8616
4080
4.38M
      GIM_Reject,
4081
4.38M
    // Label 226: @8617
4082
4.38M
    GIM_Reject,
4083
4.38M
    // Label 202: @8618
4084
4.38M
    GIM_Try, /*On fail goto*//*Label 229*/ 8986,
4085
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4086
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4087
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4088
4.38M
      GIM_Try, /*On fail goto*//*Label 230*/ 8696, // Rule ID 1325 //
4089
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4090
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4091
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4092
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4093
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4094
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4095
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4096
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
4097
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4098
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4099
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4100
4.38M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 337:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4101
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv2i32_v2i64,
4102
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4103
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4104
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4105
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4106
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4107
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4108
4.38M
        // GIR_Coverage, 1325,
4109
4.38M
        GIR_Done,
4110
4.38M
      // Label 230: @8696
4111
4.38M
      GIM_Try, /*On fail goto*//*Label 231*/ 8760, // Rule ID 1385 //
4112
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4113
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4114
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4115
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4116
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4117
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4118
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4119
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
4120
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4121
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4122
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4123
4.38M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 391:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4124
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv2i32_v2i64,
4125
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4126
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4127
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4128
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4129
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4130
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4131
4.38M
        // GIR_Coverage, 1385,
4132
4.38M
        GIR_Done,
4133
4.38M
      // Label 231: @8760
4134
4.38M
      GIM_Try, /*On fail goto*//*Label 232*/ 8818, // Rule ID 1349 //
4135
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4136
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4137
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4138
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4139
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4140
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4141
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4142
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4143
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4144
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4145
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4146
4.38M
        // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4147
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv2i32_v2i64,
4148
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4149
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4150
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4151
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4152
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4153
4.38M
        // GIR_Coverage, 1349,
4154
4.38M
        GIR_Done,
4155
4.38M
      // Label 232: @8818
4156
4.38M
      GIM_Try, /*On fail goto*//*Label 233*/ 8876, // Rule ID 1397 //
4157
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4158
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4159
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4160
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4161
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4162
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4163
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4164
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4165
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4166
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4167
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4168
4.38M
        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4169
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64,
4170
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4171
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4172
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4173
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4174
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4175
4.38M
        // GIR_Coverage, 1397,
4176
4.38M
        GIR_Done,
4177
4.38M
      // Label 233: @8876
4178
4.38M
      GIM_Try, /*On fail goto*//*Label 234*/ 8921, // Rule ID 1355 //
4179
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4180
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4181
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4182
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4183
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4184
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4185
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4186
4.38M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4187
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv2i32_v2i64,
4188
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4189
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4190
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4191
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4192
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4193
4.38M
        // GIR_Coverage, 1355,
4194
4.38M
        GIR_Done,
4195
4.38M
      // Label 234: @8921
4196
4.38M
      GIM_Try, /*On fail goto*//*Label 235*/ 8966, // Rule ID 1403 //
4197
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4198
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4199
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4200
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4201
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4202
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4203
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4204
4.38M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4205
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv2i32_v2i64,
4206
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4207
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4208
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4209
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4210
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4211
4.38M
        // GIR_Coverage, 1403,
4212
4.38M
        GIR_Done,
4213
4.38M
      // Label 235: @8966
4214
4.38M
      GIM_Try, /*On fail goto*//*Label 236*/ 8985, // Rule ID 1094 //
4215
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4216
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4217
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4218
4.38M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
4219
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i64,
4220
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4221
4.38M
        // GIR_Coverage, 1094,
4222
4.38M
        GIR_Done,
4223
4.38M
      // Label 236: @8985
4224
4.38M
      GIM_Reject,
4225
4.38M
    // Label 229: @8986
4226
4.38M
    GIM_Reject,
4227
4.38M
    // Label 203: @8987
4228
4.38M
    GIM_Try, /*On fail goto*//*Label 237*/ 9074,
4229
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4230
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4231
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4232
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4233
4.38M
      GIM_Try, /*On fail goto*//*Label 238*/ 9058, // Rule ID 972 //
4234
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4235
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4236
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4237
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4238
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4239
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4240
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4241
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4242
4.38M
        // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (MLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4243
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i16,
4244
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4245
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4246
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4247
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4248
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4249
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4250
4.38M
        // GIR_Coverage, 972,
4251
4.38M
        GIR_Done,
4252
4.38M
      // Label 238: @9058
4253
4.38M
      GIM_Try, /*On fail goto*//*Label 239*/ 9073, // Rule ID 1090 //
4254
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4255
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4256
4.38M
        // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4257
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i16,
4258
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4259
4.38M
        // GIR_Coverage, 1090,
4260
4.38M
        GIR_Done,
4261
4.38M
      // Label 239: @9073
4262
4.38M
      GIM_Reject,
4263
4.38M
    // Label 237: @9074
4264
4.38M
    GIM_Reject,
4265
4.38M
    // Label 204: @9075
4266
4.38M
    GIM_Try, /*On fail goto*//*Label 240*/ 9500,
4267
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4268
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4269
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4270
4.38M
      GIM_Try, /*On fail goto*//*Label 241*/ 9153, // Rule ID 1323 //
4271
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4272
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4273
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4274
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4275
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4276
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4277
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4278
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4279
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4280
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4281
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4282
4.38M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 337:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4283
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv4i16_v4i32,
4284
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4285
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4286
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4287
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4288
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4289
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4290
4.38M
        // GIR_Coverage, 1323,
4291
4.38M
        GIR_Done,
4292
4.38M
      // Label 241: @9153
4293
4.38M
      GIM_Try, /*On fail goto*//*Label 242*/ 9217, // Rule ID 1383 //
4294
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4295
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4296
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4297
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4298
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4299
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4300
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4301
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4302
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4303
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4304
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4305
4.38M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 391:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4306
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv4i16_v4i32,
4307
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4308
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4309
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4310
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4311
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4312
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4313
4.38M
        // GIR_Coverage, 1383,
4314
4.38M
        GIR_Done,
4315
4.38M
      // Label 242: @9217
4316
4.38M
      GIM_Try, /*On fail goto*//*Label 243*/ 9275, // Rule ID 1347 //
4317
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4318
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4319
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4320
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4321
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4322
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4323
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4324
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4325
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4326
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4327
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4328
4.38M
        // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4329
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv4i16_v4i32,
4330
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4331
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4332
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4333
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4334
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4335
4.38M
        // GIR_Coverage, 1347,
4336
4.38M
        GIR_Done,
4337
4.38M
      // Label 243: @9275
4338
4.38M
      GIM_Try, /*On fail goto*//*Label 244*/ 9333, // Rule ID 1395 //
4339
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4340
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4341
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4342
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4343
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4344
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4345
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4346
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4347
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4348
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4349
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4350
4.38M
        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4351
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32,
4352
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4353
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4354
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4355
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4356
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4357
4.38M
        // GIR_Coverage, 1395,
4358
4.38M
        GIR_Done,
4359
4.38M
      // Label 244: @9333
4360
4.38M
      GIM_Try, /*On fail goto*//*Label 245*/ 9390, // Rule ID 975 //
4361
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4362
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4363
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4364
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4365
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4366
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4367
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4368
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4369
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4370
4.38M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (MLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4371
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i32,
4372
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4373
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4374
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4375
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4376
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4377
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4378
4.38M
        // GIR_Coverage, 975,
4379
4.38M
        GIR_Done,
4380
4.38M
      // Label 245: @9390
4381
4.38M
      GIM_Try, /*On fail goto*//*Label 246*/ 9435, // Rule ID 1353 //
4382
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4383
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4384
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4385
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4386
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4387
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4388
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4389
4.38M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4390
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv4i16_v4i32,
4391
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4392
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4393
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4394
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4395
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4396
4.38M
        // GIR_Coverage, 1353,
4397
4.38M
        GIR_Done,
4398
4.38M
      // Label 246: @9435
4399
4.38M
      GIM_Try, /*On fail goto*//*Label 247*/ 9480, // Rule ID 1401 //
4400
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4401
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4402
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4403
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4404
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4405
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4406
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4407
4.38M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4408
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv4i16_v4i32,
4409
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4410
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4411
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4412
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4413
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4414
4.38M
        // GIR_Coverage, 1401,
4415
4.38M
        GIR_Done,
4416
4.38M
      // Label 247: @9480
4417
4.38M
      GIM_Try, /*On fail goto*//*Label 248*/ 9499, // Rule ID 1093 //
4418
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4419
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4420
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4421
4.38M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4422
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i32,
4423
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4424
4.38M
        // GIR_Coverage, 1093,
4425
4.38M
        GIR_Done,
4426
4.38M
      // Label 248: @9499
4427
4.38M
      GIM_Reject,
4428
4.38M
    // Label 240: @9500
4429
4.38M
    GIM_Reject,
4430
4.38M
    // Label 205: @9501
4431
4.38M
    GIM_Try, /*On fail goto*//*Label 249*/ 9588,
4432
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4433
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4434
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4435
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4436
4.38M
      GIM_Try, /*On fail goto*//*Label 250*/ 9572, // Rule ID 970 //
4437
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4438
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4439
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4440
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4441
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4442
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4443
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4444
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4445
4.38M
        // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (MLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4446
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i8,
4447
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4448
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4449
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4450
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4451
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4452
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4453
4.38M
        // GIR_Coverage, 970,
4454
4.38M
        GIR_Done,
4455
4.38M
      // Label 250: @9572
4456
4.38M
      GIM_Try, /*On fail goto*//*Label 251*/ 9587, // Rule ID 1088 //
4457
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4458
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4459
4.38M
        // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4460
4.38M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i8,
4461
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4462
4.38M
        // GIR_Coverage, 1088,
4463
4.38M
        GIR_Done,
4464
4.38M
      // Label 251: @9587
4465
4.38M
      GIM_Reject,
4466
4.38M
    // Label 249: @9588
4467
4.38M
    GIM_Reject,
4468
4.38M
    // Label 206: @9589
4469
4.38M
    GIM_Try, /*On fail goto*//*Label 252*/ 10014,
4470
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4471
4.38M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4472
4.38M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4473
4.38M
      GIM_Try, /*On fail goto*//*Label 253*/ 9667, // Rule ID 1321 //
4474
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4475
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4476
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4477
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4478
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4479
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4480
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4481
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
4482
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4483
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4484
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4485
4.38M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 337:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4486
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv8i8_v8i16,
4487
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4488
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4489
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4490
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4491
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4492
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4493
4.38M
        // GIR_Coverage, 1321,
4494
4.38M
        GIR_Done,
4495
4.38M
      // Label 253: @9667
4496
4.38M
      GIM_Try, /*On fail goto*//*Label 254*/ 9731, // Rule ID 1381 //
4497
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4498
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4499
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4500
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4501
4.38M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4502
4.38M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4503
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4504
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
4505
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4506
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4507
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4508
4.38M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 391:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4509
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv8i8_v8i16,
4510
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4511
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4512
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4513
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4514
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4515
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4516
4.38M
        // GIR_Coverage, 1381,
4517
4.38M
        GIR_Done,
4518
4.38M
      // Label 254: @9731
4519
4.38M
      GIM_Try, /*On fail goto*//*Label 255*/ 9789, // Rule ID 1345 //
4520
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4521
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4522
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4523
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4524
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4525
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4526
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4527
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4528
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4529
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4530
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4531
4.38M
        // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4532
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv8i8_v8i16,
4533
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4534
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4535
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4536
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4537
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4538
4.38M
        // GIR_Coverage, 1345,
4539
4.38M
        GIR_Done,
4540
4.38M
      // Label 255: @9789
4541
4.38M
      GIM_Try, /*On fail goto*//*Label 256*/ 9847, // Rule ID 1393 //
4542
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4543
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4544
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4545
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4546
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4547
4.38M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4548
4.38M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4549
4.38M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4550
4.38M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4551
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4552
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4553
4.38M
        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4554
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16,
4555
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4556
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4557
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4558
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4559
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4560
4.38M
        // GIR_Coverage, 1393,
4561
4.38M
        GIR_Done,
4562
4.38M
      // Label 256: @9847
4563
4.38M
      GIM_Try, /*On fail goto*//*Label 257*/ 9904, // Rule ID 973 //
4564
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4565
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4566
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4567
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4568
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4569
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4570
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4571
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4572
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4573
4.38M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (MLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
4574
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i16,
4575
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4576
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4577
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4578
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4579
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4580
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4581
4.38M
        // GIR_Coverage, 973,
4582
4.38M
        GIR_Done,
4583
4.38M
      // Label 257: @9904
4584
4.38M
      GIM_Try, /*On fail goto*//*Label 258*/ 9949, // Rule ID 1351 //
4585
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4586
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4587
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4588
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4589
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4590
4.38M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4591
4.38M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4592
4.38M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4593
4.38M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv8i8_v8i16,
4594
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4595
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4596
4.38M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4597
4.38M
        GIR_EraseFromParent, /*InsnID*/0,
4598
4.38M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4599
4.38M
        // GIR_Coverage, 1351,
4600
4.38M
        GIR_Done,
4601
4.38M
      // Label 258: @9949
4602
4.38M
      GIM_Try, /*On fail goto*//*Label 259*/ 9994, // Rule ID 1399 //
4603
4.38M
        GIM_CheckFeatures, GIFBS_HasNEON,
4604
4.38M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4605
4.38M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4606
4.38M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4607
4.38M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GIL