Coverage Report

Created: 2018-09-25 17:16

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AArch64/AArch64GenGlobalISel.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the AArch64 target                         *|
4
|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 16;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
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#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static AArch64InstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
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28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
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, State(1),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
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33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_HasFPARMv8Bit = 3,
37
  Feature_HasNEONBit = 4,
38
  Feature_HasSHA2Bit = 7,
39
  Feature_HasAESBit = 6,
40
  Feature_HasDotProdBit = 0,
41
  Feature_HasCRCBit = 1,
42
  Feature_HasLSEBit = 8,
43
  Feature_HasRDMBit = 5,
44
  Feature_HasPerfMonBit = 9,
45
  Feature_HasFullFP16Bit = 2,
46
  Feature_HasFuseAESBit = 14,
47
  Feature_IsLEBit = 10,
48
  Feature_IsBEBit = 15,
49
  Feature_UseAlternateSExtLoadCVTF32Bit = 13,
50
  Feature_NotForCodeSizeBit = 12,
51
  Feature_UseSTRQroBit = 11,
52
};
53
54
PredicateBitset AArch64InstructionSelector::
55
8.60k
computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const {
56
8.60k
  PredicateBitset Features;
57
8.60k
  if (Subtarget->hasFPARMv8())
58
8.58k
    Features[Feature_HasFPARMv8Bit] = 1;
59
8.60k
  if (Subtarget->hasNEON())
60
8.58k
    Features[Feature_HasNEONBit] = 1;
61
8.60k
  if (Subtarget->hasSHA2())
62
8.60k
    Features[Feature_HasSHA2Bit] = 1;
63
8.60k
  if (Subtarget->hasAES())
64
8.60k
    Features[Feature_HasAESBit] = 1;
65
8.60k
  if (Subtarget->hasDotProd())
66
5
    Features[Feature_HasDotProdBit] = 1;
67
8.60k
  if (Subtarget->hasCRC())
68
166
    Features[Feature_HasCRCBit] = 1;
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8.60k
  if (Subtarget->hasLSE())
70
32
    Features[Feature_HasLSEBit] = 1;
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8.60k
  if (Subtarget->hasRDM())
72
37
    Features[Feature_HasRDMBit] = 1;
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8.60k
  if (Subtarget->hasPerfMon())
74
8.59k
    Features[Feature_HasPerfMonBit] = 1;
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8.60k
  if (Subtarget->hasFullFP16())
76
19
    Features[Feature_HasFullFP16Bit] = 1;
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8.60k
  if (Subtarget->hasFuseAES())
78
8.56k
    Features[Feature_HasFuseAESBit] = 1;
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8.60k
  if (Subtarget->isLittleEndian())
80
8.57k
    Features[Feature_IsLEBit] = 1;
81
8.60k
  if (!Subtarget->isLittleEndian())
82
28
    Features[Feature_IsBEBit] = 1;
83
8.60k
  if (Subtarget->useAlternateSExtLoadCVTF32Pattern())
84
7.13k
    Features[Feature_UseAlternateSExtLoadCVTF32Bit] = 1;
85
8.60k
  return Features;
86
8.60k
}
87
88
PredicateBitset AArch64InstructionSelector::
89
4.50M
computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const {
90
4.50M
  PredicateBitset Features;
91
4.50M
  if (!MF->getFunction().optForSize())
92
4.50M
    Features[Feature_NotForCodeSizeBit] = 1;
93
4.50M
  if (!Subtarget->isSTRQroSlow() || 
MF->getFunction().optForSize()0
)
94
4.50M
    Features[Feature_UseSTRQroBit] = 1;
95
4.50M
  return Features;
96
4.50M
}
97
98
// LLT Objects.
99
enum {
100
  GILLT_s16,
101
  GILLT_s32,
102
  GILLT_s64,
103
  GILLT_s128,
104
  GILLT_v2s32,
105
  GILLT_v2s64,
106
  GILLT_v4s16,
107
  GILLT_v4s32,
108
  GILLT_v8s8,
109
  GILLT_v8s16,
110
  GILLT_v16s8,
111
};
112
const static size_t NumTypeObjects = 11;
113
const static LLT TypeObjects[] = {
114
  LLT::scalar(16),
115
  LLT::scalar(32),
116
  LLT::scalar(64),
117
  LLT::scalar(128),
118
  LLT::vector(2, 32),
119
  LLT::vector(2, 64),
120
  LLT::vector(4, 16),
121
  LLT::vector(4, 32),
122
  LLT::vector(8, 8),
123
  LLT::vector(8, 16),
124
  LLT::vector(16, 8),
125
};
126
127
// Feature bitsets.
128
enum {
129
  GIFBS_Invalid,
130
  GIFBS_HasAES,
131
  GIFBS_HasCRC,
132
  GIFBS_HasDotProd,
133
  GIFBS_HasFPARMv8,
134
  GIFBS_HasFullFP16,
135
  GIFBS_HasFuseAES,
136
  GIFBS_HasLSE,
137
  GIFBS_HasNEON,
138
  GIFBS_HasRDM,
139
  GIFBS_HasSHA2,
140
  GIFBS_IsBE,
141
  GIFBS_IsLE,
142
  GIFBS_HasFullFP16_HasNEON,
143
  GIFBS_HasNEON_HasRDM,
144
};
145
const static PredicateBitset FeatureBitsets[] {
146
  {}, // GIFBS_Invalid
147
  {Feature_HasAESBit, },
148
  {Feature_HasCRCBit, },
149
  {Feature_HasDotProdBit, },
150
  {Feature_HasFPARMv8Bit, },
151
  {Feature_HasFullFP16Bit, },
152
  {Feature_HasFuseAESBit, },
153
  {Feature_HasLSEBit, },
154
  {Feature_HasNEONBit, },
155
  {Feature_HasRDMBit, },
156
  {Feature_HasSHA2Bit, },
157
  {Feature_IsBEBit, },
158
  {Feature_IsLEBit, },
159
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
160
  {Feature_HasNEONBit, Feature_HasRDMBit, },
161
};
162
163
// ComplexPattern predicates.
164
enum {
165
  GICP_Invalid,
166
  GICP_gi_addsub_shifted_imm32,
167
  GICP_gi_addsub_shifted_imm64,
168
  GICP_gi_am_indexed128,
169
  GICP_gi_am_indexed16,
170
  GICP_gi_am_indexed32,
171
  GICP_gi_am_indexed64,
172
  GICP_gi_am_indexed8,
173
  GICP_gi_am_unscaled128,
174
  GICP_gi_am_unscaled16,
175
  GICP_gi_am_unscaled32,
176
  GICP_gi_am_unscaled64,
177
  GICP_gi_am_unscaled8,
178
};
179
// See constructor for table contents
180
181
// PatFrag predicates.
182
enum {
183
  GIPFP_I64_Predicate_VectorIndex1 = GIPFP_I64_Invalid + 1,
184
  GIPFP_I64_Predicate_VectorIndexB,
185
  GIPFP_I64_Predicate_VectorIndexD,
186
  GIPFP_I64_Predicate_VectorIndexH,
187
  GIPFP_I64_Predicate_VectorIndexS,
188
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16,
189
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32,
190
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64,
191
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8,
192
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16,
193
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32,
194
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64,
195
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8,
196
  GIPFP_I64_Predicate_i64imm_32bit,
197
  GIPFP_I64_Predicate_imm0_1,
198
  GIPFP_I64_Predicate_imm0_127,
199
  GIPFP_I64_Predicate_imm0_15,
200
  GIPFP_I64_Predicate_imm0_255,
201
  GIPFP_I64_Predicate_imm0_31,
202
  GIPFP_I64_Predicate_imm0_63,
203
  GIPFP_I64_Predicate_imm0_65535,
204
  GIPFP_I64_Predicate_imm0_7,
205
  GIPFP_I64_Predicate_imm32_0_15,
206
  GIPFP_I64_Predicate_imm32_0_31,
207
  GIPFP_I64_Predicate_maski16_or_more,
208
  GIPFP_I64_Predicate_maski8_or_more,
209
  GIPFP_I64_Predicate_s64imm_32bit,
210
  GIPFP_I64_Predicate_simm4s1,
211
  GIPFP_I64_Predicate_simm4s16,
212
  GIPFP_I64_Predicate_simm4s2,
213
  GIPFP_I64_Predicate_simm4s3,
214
  GIPFP_I64_Predicate_simm4s4,
215
  GIPFP_I64_Predicate_simm5_32b,
216
  GIPFP_I64_Predicate_simm5_64b,
217
  GIPFP_I64_Predicate_simm6_32b,
218
  GIPFP_I64_Predicate_simm6s1,
219
  GIPFP_I64_Predicate_simm8,
220
  GIPFP_I64_Predicate_simm9,
221
  GIPFP_I64_Predicate_sve_elm_idx_extdup_b,
222
  GIPFP_I64_Predicate_sve_elm_idx_extdup_d,
223
  GIPFP_I64_Predicate_sve_elm_idx_extdup_h,
224
  GIPFP_I64_Predicate_sve_elm_idx_extdup_q,
225
  GIPFP_I64_Predicate_sve_elm_idx_extdup_s,
226
  GIPFP_I64_Predicate_sve_incdec_imm,
227
  GIPFP_I64_Predicate_sve_pred_enum,
228
  GIPFP_I64_Predicate_sve_prfop,
229
  GIPFP_I64_Predicate_tbz_imm0_31_diag,
230
  GIPFP_I64_Predicate_tbz_imm0_31_nodiag,
231
  GIPFP_I64_Predicate_tbz_imm32_63,
232
  GIPFP_I64_Predicate_uimm5s2,
233
  GIPFP_I64_Predicate_uimm5s4,
234
  GIPFP_I64_Predicate_uimm5s8,
235
  GIPFP_I64_Predicate_uimm6,
236
  GIPFP_I64_Predicate_uimm6s1,
237
  GIPFP_I64_Predicate_uimm6s2,
238
  GIPFP_I64_Predicate_uimm6s4,
239
  GIPFP_I64_Predicate_uimm6s8,
240
  GIPFP_I64_Predicate_vecshiftL16,
241
  GIPFP_I64_Predicate_vecshiftL32,
242
  GIPFP_I64_Predicate_vecshiftL64,
243
  GIPFP_I64_Predicate_vecshiftL8,
244
  GIPFP_I64_Predicate_vecshiftR16,
245
  GIPFP_I64_Predicate_vecshiftR16Narrow,
246
  GIPFP_I64_Predicate_vecshiftR32,
247
  GIPFP_I64_Predicate_vecshiftR32Narrow,
248
  GIPFP_I64_Predicate_vecshiftR64,
249
  GIPFP_I64_Predicate_vecshiftR64Narrow,
250
  GIPFP_I64_Predicate_vecshiftR8,
251
};
252
22.0k
bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
253
22.0k
  switch (PredicateID) {
254
22.0k
  case GIPFP_I64_Predicate_VectorIndex1: {
255
0
     return ((uint64_t)Imm) == 1; 
256
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
257
22.0k
    
return false0
;
258
22.0k
  }
259
22.0k
  case GIPFP_I64_Predicate_VectorIndexB: {
260
0
     return ((uint64_t)Imm) < 16; 
261
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
262
22.0k
    
return false0
;
263
22.0k
  }
264
22.0k
  case GIPFP_I64_Predicate_VectorIndexD: {
265
0
     return ((uint64_t)Imm) < 2; 
266
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
267
22.0k
    
return false0
;
268
22.0k
  }
269
22.0k
  case GIPFP_I64_Predicate_VectorIndexH: {
270
0
     return ((uint64_t)Imm) < 8; 
271
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
272
22.0k
    
return false0
;
273
22.0k
  }
274
22.0k
  case GIPFP_I64_Predicate_VectorIndexS: {
275
0
     return ((uint64_t)Imm) < 4; 
276
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
277
22.0k
    
return false0
;
278
22.0k
  }
279
22.0k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16: {
280
0
    
281
0
  return AArch64_AM::isSVEAddSubImm<int16_t>(Imm);
282
22.0k
283
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
284
22.0k
    
return false0
;
285
22.0k
  }
286
22.0k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32: {
287
0
    
288
0
  return AArch64_AM::isSVEAddSubImm<int32_t>(Imm);
289
22.0k
290
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
291
22.0k
    
return false0
;
292
22.0k
  }
293
22.0k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64: {
294
0
    
295
0
  return AArch64_AM::isSVEAddSubImm<int64_t>(Imm);
296
22.0k
297
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
298
22.0k
    
return false0
;
299
22.0k
  }
300
22.0k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8: {
301
0
    
302
0
  return AArch64_AM::isSVEAddSubImm<int8_t>(Imm);
303
22.0k
304
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
305
22.0k
    
return false0
;
306
22.0k
  }
307
22.0k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16: {
308
0
    
309
0
  return AArch64_AM::isSVECpyImm<int16_t>(Imm);
310
22.0k
311
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
312
22.0k
    
return false0
;
313
22.0k
  }
314
22.0k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32: {
315
0
    
316
0
  return AArch64_AM::isSVECpyImm<int32_t>(Imm);
317
22.0k
318
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
319
22.0k
    
return false0
;
320
22.0k
  }
321
22.0k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64: {
322
0
    
323
0
  return AArch64_AM::isSVECpyImm<int64_t>(Imm);
324
22.0k
325
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
326
22.0k
    
return false0
;
327
22.0k
  }
328
22.0k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8: {
329
0
    
330
0
  return AArch64_AM::isSVECpyImm<int8_t>(Imm);
331
22.0k
332
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
333
22.0k
    
return false0
;
334
22.0k
  }
335
22.0k
  case GIPFP_I64_Predicate_i64imm_32bit: {
336
133
    
337
133
  return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
338
22.0k
339
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
340
22.0k
    
return false0
;
341
22.0k
  }
342
22.0k
  case GIPFP_I64_Predicate_imm0_1: {
343
0
    
344
0
  return ((uint64_t)Imm) < 2;
345
22.0k
346
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
347
22.0k
    
return false0
;
348
22.0k
  }
349
22.0k
  case GIPFP_I64_Predicate_imm0_127: {
350
1
    
351
1
  return ((uint32_t)Imm) < 128;
352
22.0k
353
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
354
22.0k
    
return false0
;
355
22.0k
  }
356
22.0k
  case GIPFP_I64_Predicate_imm0_15: {
357
0
    
358
0
  return ((uint64_t)Imm) < 16;
359
22.0k
360
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
361
22.0k
    
return false0
;
362
22.0k
  }
363
22.0k
  case GIPFP_I64_Predicate_imm0_255: {
364
0
    
365
0
  return ((uint32_t)Imm) < 256;
366
22.0k
367
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
368
22.0k
    
return false0
;
369
22.0k
  }
370
22.0k
  case GIPFP_I64_Predicate_imm0_31: {
371
0
    
372
0
  return ((uint64_t)Imm) < 32;
373
22.0k
374
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
375
22.0k
    
return false0
;
376
22.0k
  }
377
22.0k
  case GIPFP_I64_Predicate_imm0_63: {
378
18.0k
    
379
18.0k
  return ((uint64_t)Imm) < 64;
380
22.0k
381
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
382
22.0k
    
return false0
;
383
22.0k
  }
384
22.0k
  case GIPFP_I64_Predicate_imm0_65535: {
385
0
    
386
0
  return ((uint32_t)Imm) < 65536;
387
22.0k
388
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
389
22.0k
    
return false0
;
390
22.0k
  }
391
22.0k
  case GIPFP_I64_Predicate_imm0_7: {
392
0
    
393
0
  return ((uint64_t)Imm) < 8;
394
22.0k
395
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
396
22.0k
    
return false0
;
397
22.0k
  }
398
22.0k
  case GIPFP_I64_Predicate_imm32_0_15: {
399
0
    
400
0
  return ((uint32_t)Imm) < 16;
401
22.0k
402
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
403
22.0k
    
return false0
;
404
22.0k
  }
405
22.0k
  case GIPFP_I64_Predicate_imm32_0_31: {
406
0
    
407
0
  return ((uint64_t)Imm) < 32;
408
22.0k
409
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
410
22.0k
    
return false0
;
411
22.0k
  }
412
22.0k
  case GIPFP_I64_Predicate_maski16_or_more: {
413
0
     return (Imm & 0xffff) == 0xffff; 
414
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
415
22.0k
    
return false0
;
416
22.0k
  }
417
22.0k
  case GIPFP_I64_Predicate_maski8_or_more: {
418
0
     return (Imm & 0xff) == 0xff; 
419
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
420
22.0k
    
return false0
;
421
22.0k
  }
422
22.0k
  case GIPFP_I64_Predicate_s64imm_32bit: {
423
3.78k
    
424
3.78k
  int64_t Imm64 = static_cast<int64_t>(Imm);
425
3.78k
  return Imm64 >= std::numeric_limits<int32_t>::min() &&
426
3.78k
         Imm64 <= std::numeric_limits<int32_t>::max();
427
22.0k
428
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
429
22.0k
    
return false0
;
430
22.0k
  }
431
22.0k
  case GIPFP_I64_Predicate_simm4s1: {
432
0
     return Imm >=-8  && Imm <= 7; 
433
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
434
22.0k
    
return false0
;
435
22.0k
  }
436
22.0k
  case GIPFP_I64_Predicate_simm4s16: {
437
0
     return Imm >=-128  && Imm <= 112 && (Imm % 16) == 0x0; 
438
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
439
22.0k
    
return false0
;
440
22.0k
  }
441
22.0k
  case GIPFP_I64_Predicate_simm4s2: {
442
0
     return Imm >=-16  && Imm <= 14 && (Imm % 2) == 0x0; 
443
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
444
22.0k
    
return false0
;
445
22.0k
  }
446
22.0k
  case GIPFP_I64_Predicate_simm4s3: {
447
0
     return Imm >=-24  && Imm <= 21 && (Imm % 3) == 0x0; 
448
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
449
22.0k
    
return false0
;
450
22.0k
  }
451
22.0k
  case GIPFP_I64_Predicate_simm4s4: {
452
0
     return Imm >=-32  && Imm <= 28 && (Imm % 4) == 0x0; 
453
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
454
22.0k
    
return false0
;
455
22.0k
  }
456
22.0k
  case GIPFP_I64_Predicate_simm5_32b: {
457
0
     return Imm >= -16 && Imm < 16; 
458
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
459
22.0k
    
return false0
;
460
22.0k
  }
461
22.0k
  case GIPFP_I64_Predicate_simm5_64b: {
462
0
     return Imm >= -16 && Imm < 16; 
463
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
464
22.0k
    
return false0
;
465
22.0k
  }
466
22.0k
  case GIPFP_I64_Predicate_simm6_32b: {
467
0
     return Imm >= -32 && Imm < 32; 
468
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
469
22.0k
    
return false0
;
470
22.0k
  }
471
22.0k
  case GIPFP_I64_Predicate_simm6s1: {
472
0
     return Imm >= -32 && Imm < 32; 
473
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
474
22.0k
    
return false0
;
475
22.0k
  }
476
22.0k
  case GIPFP_I64_Predicate_simm8: {
477
0
     return Imm >= -128 && Imm < 127; 
478
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
479
22.0k
    
return false0
;
480
22.0k
  }
481
22.0k
  case GIPFP_I64_Predicate_simm9: {
482
0
     return Imm >= -256 && Imm < 256; 
483
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
484
22.0k
    
return false0
;
485
22.0k
  }
486
22.0k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_b: {
487
0
     return ((uint64_t)Imm) < 64; 
488
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
489
22.0k
    
return false0
;
490
22.0k
  }
491
22.0k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_d: {
492
0
     return ((uint64_t)Imm) < 8; 
493
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
494
22.0k
    
return false0
;
495
22.0k
  }
496
22.0k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_h: {
497
0
     return ((uint64_t)Imm) < 32; 
498
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
499
22.0k
    
return false0
;
500
22.0k
  }
501
22.0k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_q: {
502
0
     return ((uint64_t)Imm) < 4; 
503
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
504
22.0k
    
return false0
;
505
22.0k
  }
506
22.0k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_s: {
507
0
     return ((uint64_t)Imm) < 16; 
508
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
509
22.0k
    
return false0
;
510
22.0k
  }
511
22.0k
  case GIPFP_I64_Predicate_sve_incdec_imm: {
512
0
    
513
0
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
514
22.0k
515
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
516
22.0k
    
return false0
;
517
22.0k
  }
518
22.0k
  case GIPFP_I64_Predicate_sve_pred_enum: {
519
0
    
520
0
  return (((uint32_t)Imm) < 32);
521
22.0k
  
522
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
523
22.0k
    
return false0
;
524
22.0k
  }
525
22.0k
  case GIPFP_I64_Predicate_sve_prfop: {
526
0
    
527
0
    return (((uint32_t)Imm) <= 15);
528
22.0k
  
529
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
530
22.0k
    
return false0
;
531
22.0k
  }
532
22.0k
  case GIPFP_I64_Predicate_tbz_imm0_31_diag: {
533
0
    
534
0
  return (((uint32_t)Imm) < 32);
535
22.0k
536
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
537
22.0k
    
return false0
;
538
22.0k
  }
539
22.0k
  case GIPFP_I64_Predicate_tbz_imm0_31_nodiag: {
540
0
    
541
0
  return (((uint32_t)Imm) < 32);
542
22.0k
543
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
544
22.0k
    
return false0
;
545
22.0k
  }
546
22.0k
  case GIPFP_I64_Predicate_tbz_imm32_63: {
547
0
    
548
0
  return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
549
22.0k
550
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
551
22.0k
    
return false0
;
552
22.0k
  }
553
22.0k
  case GIPFP_I64_Predicate_uimm5s2: {
554
0
     return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); 
555
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
556
22.0k
    
return false0
;
557
22.0k
  }
558
22.0k
  case GIPFP_I64_Predicate_uimm5s4: {
559
0
     return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); 
560
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
561
22.0k
    
return false0
;
562
22.0k
  }
563
22.0k
  case GIPFP_I64_Predicate_uimm5s8: {
564
0
     return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); 
565
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
566
22.0k
    
return false0
;
567
22.0k
  }
568
22.0k
  case GIPFP_I64_Predicate_uimm6: {
569
0
     return Imm >= 0 && Imm < 64; 
570
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
571
22.0k
    
return false0
;
572
22.0k
  }
573
22.0k
  case GIPFP_I64_Predicate_uimm6s1: {
574
0
     return Imm >= 0 && Imm < 64; 
575
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
576
22.0k
    
return false0
;
577
22.0k
  }
578
22.0k
  case GIPFP_I64_Predicate_uimm6s2: {
579
0
     return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); 
580
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
581
22.0k
    
return false0
;
582
22.0k
  }
583
22.0k
  case GIPFP_I64_Predicate_uimm6s4: {
584
0
     return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); 
585
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
586
22.0k
    
return false0
;
587
22.0k
  }
588
22.0k
  case GIPFP_I64_Predicate_uimm6s8: {
589
0
     return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); 
590
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
591
22.0k
    
return false0
;
592
22.0k
  }
593
22.0k
  case GIPFP_I64_Predicate_vecshiftL16: {
594
3
    
595
3
  return (((uint32_t)Imm) < 16);
596
22.0k
597
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
598
22.0k
    
return false0
;
599
22.0k
  }
600
22.0k
  case GIPFP_I64_Predicate_vecshiftL32: {
601
2
    
602
2
  return (((uint32_t)Imm) < 32);
603
22.0k
604
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
605
22.0k
    
return false0
;
606
22.0k
  }
607
22.0k
  case GIPFP_I64_Predicate_vecshiftL64: {
608
0
    
609
0
  return (((uint32_t)Imm) < 64);
610
22.0k
611
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
612
22.0k
    
return false0
;
613
22.0k
  }
614
22.0k
  case GIPFP_I64_Predicate_vecshiftL8: {
615
3
    
616
3
  return (((uint32_t)Imm) < 8);
617
22.0k
618
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
619
22.0k
    
return false0
;
620
22.0k
  }
621
22.0k
  case GIPFP_I64_Predicate_vecshiftR16: {
622
3
    
623
3
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
624
22.0k
625
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
626
22.0k
    
return false0
;
627
22.0k
  }
628
22.0k
  case GIPFP_I64_Predicate_vecshiftR16Narrow: {
629
8
    
630
8
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
631
22.0k
632
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
633
22.0k
    
return false0
;
634
22.0k
  }
635
22.0k
  case GIPFP_I64_Predicate_vecshiftR32: {
636
2
    
637
2
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
638
22.0k
639
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
640
22.0k
    
return false0
;
641
22.0k
  }
642
22.0k
  case GIPFP_I64_Predicate_vecshiftR32Narrow: {
643
8
    
644
8
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
645
22.0k
646
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
647
22.0k
    
return false0
;
648
22.0k
  }
649
22.0k
  case GIPFP_I64_Predicate_vecshiftR64: {
650
1
    
651
1
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
652
22.0k
653
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
654
22.0k
    
return false0
;
655
22.0k
  }
656
22.0k
  case GIPFP_I64_Predicate_vecshiftR64Narrow: {
657
8
    
658
8
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
659
22.0k
660
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
661
22.0k
    
return false0
;
662
22.0k
  }
663
22.0k
  case GIPFP_I64_Predicate_vecshiftR8: {
664
3
    
665
3
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
666
22.0k
667
22.0k
    
llvm_unreachable0
("ImmediateCode should have returned");
668
22.0k
    
return false0
;
669
0
  }
670
0
  }
671
0
  llvm_unreachable("Unknown predicate");
672
0
  return false;
673
0
}
674
// PatFrag predicates.
675
enum {
676
  GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1,
677
  GIPFP_APFloat_Predicate_fpimm16,
678
  GIPFP_APFloat_Predicate_fpimm32,
679
  GIPFP_APFloat_Predicate_fpimm64,
680
  GIPFP_APFloat_Predicate_simdimmtype10,
681
};
682
2.45k
bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
683
2.45k
  switch (PredicateID) {
684
2.45k
  case GIPFP_APFloat_Predicate_fpimm0: {
685
2.45k
    
686
2.45k
  return Imm.isExactlyValue(+0.0);
687
2.45k
688
2.45k
    
llvm_unreachable0
("ImmediateCode should have returned");
689
2.45k
    
return false0
;
690
2.45k
  }
691
2.45k
  case GIPFP_APFloat_Predicate_fpimm16: {
692
0
    
693
0
      return AArch64_AM::getFP16Imm(Imm) != -1;
694
2.45k
    
695
2.45k
    
llvm_unreachable0
("ImmediateCode should have returned");
696
2.45k
    
return false0
;
697
2.45k
  }
698
2.45k
  case GIPFP_APFloat_Predicate_fpimm32: {
699
0
    
700
0
      return AArch64_AM::getFP32Imm(Imm) != -1;
701
2.45k
    
702
2.45k
    
llvm_unreachable0
("ImmediateCode should have returned");
703
2.45k
    
return false0
;
704
2.45k
  }
705
2.45k
  case GIPFP_APFloat_Predicate_fpimm64: {
706
0
    
707
0
      return AArch64_AM::getFP64Imm(Imm) != -1;
708
2.45k
    
709
2.45k
    
llvm_unreachable0
("ImmediateCode should have returned");
710
2.45k
    
return false0
;
711
2.45k
  }
712
2.45k
  case GIPFP_APFloat_Predicate_simdimmtype10: {
713
0
    
714
0
      return AArch64_AM::isAdvSIMDModImmType10(
715
0
                 Imm.bitcastToAPInt().getZExtValue());
716
2.45k
    
717
2.45k
    
llvm_unreachable0
("ImmediateCode should have returned");
718
2.45k
    
return false0
;
719
0
  }
720
0
  }
721
0
  llvm_unreachable("Unknown predicate");
722
0
  return false;
723
0
}
724
// PatFrag predicates.
725
enum {
726
  GIPFP_APInt_Predicate_logical_imm32 = GIPFP_APInt_Invalid + 1,
727
  GIPFP_APInt_Predicate_logical_imm64,
728
};
729
0
bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
730
0
  switch (PredicateID) {
731
0
  case GIPFP_APInt_Predicate_logical_imm32: {
732
0
    
733
0
  return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32);
734
0
735
0
    llvm_unreachable("ImmediateCode should have returned");
736
0
    return false;
737
0
  }
738
0
  case GIPFP_APInt_Predicate_logical_imm64: {
739
0
    
740
0
  return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64);
741
0
742
0
    llvm_unreachable("ImmediateCode should have returned");
743
0
    return false;
744
0
  }
745
0
  }
746
0
  llvm_unreachable("Unknown predicate");
747
0
  return false;
748
0
}
749
0
bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
750
0
  const MachineFunction &MF = *MI.getParent()->getParent();
751
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
752
0
  (void)MRI;
753
0
  llvm_unreachable("Unknown predicate");
754
0
  return false;
755
0
}
756
757
AArch64InstructionSelector::ComplexMatcherMemFn
758
AArch64InstructionSelector::ComplexPredicateFns[] = {
759
  nullptr, // GICP_Invalid
760
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32
761
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64
762
  &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128
763
  &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16
764
  &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32
765
  &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64
766
  &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8
767
  &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128
768
  &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16
769
  &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32
770
  &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64
771
  &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8
772
};
773
774
// Custom renderers.
775
enum {
776
  GICR_Invalid,
777
  GICR_renderTruncImm, 
778
};
779
AArch64InstructionSelector::CustomRendererFn
780
AArch64InstructionSelector::CustomRenderers[] = {
781
  nullptr, // GICP_Invalid
782
  &AArch64InstructionSelector::renderTruncImm, // gi_trunc_imm
783
};
784
785
4.50M
bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
786
4.50M
  MachineFunction &MF = *I.getParent()->getParent();
787
4.50M
  MachineRegisterInfo &MRI = MF.getRegInfo();
788
4.50M
  // FIXME: This should be computed on a per-function basis rather than per-insn.
789
4.50M
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
790
4.50M
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
791
4.50M
  NewMIVector OutMIs;
792
4.50M
  State.MIs.clear();
793
4.50M
  State.MIs.push_back(&I);
794
4.50M
795
4.50M
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
796
1.81M
    return true;
797
1.81M
  }
798
2.69M
799
2.69M
  return false;
800
2.69M
}
801
802
4.50M
const int64_t *AArch64InstructionSelector::getMatchTable() const {
803
4.50M
  constexpr static int64_t MatchTable0[] = {
804
4.50M
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 135, /*)*//*default:*//*Label 52*/ 78305,
805
4.50M
    /*TargetOpcode::G_ADD*//*Label 0*/ 106,
806
4.50M
    /*TargetOpcode::G_SUB*//*Label 1*/ 7381,
807
4.50M
    /*TargetOpcode::G_MUL*//*Label 2*/ 9962,
808
4.50M
    /*TargetOpcode::G_SDIV*//*Label 3*/ 10743,
809
4.50M
    /*TargetOpcode::G_UDIV*//*Label 4*/ 10812, 0, 0,
810
4.50M
    /*TargetOpcode::G_AND*//*Label 5*/ 10881,
811
4.50M
    /*TargetOpcode::G_OR*//*Label 6*/ 11423,
812
4.50M
    /*TargetOpcode::G_XOR*//*Label 7*/ 11965, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
813
4.50M
    /*TargetOpcode::G_BITCAST*//*Label 8*/ 12675, 0, 0,
814
4.50M
    /*TargetOpcode::G_LOAD*//*Label 9*/ 20168,
815
4.50M
    /*TargetOpcode::G_SEXTLOAD*//*Label 10*/ 22224,
816
4.50M
    /*TargetOpcode::G_ZEXTLOAD*//*Label 11*/ 22695,
817
4.50M
    /*TargetOpcode::G_STORE*//*Label 12*/ 23047, 0,
818
4.50M
    /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 13*/ 24946,
819
4.50M
    /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 14*/ 26143,
820
4.50M
    /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 15*/ 27172,
821
4.50M
    /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 16*/ 28201,
822
4.50M
    /*TargetOpcode::G_ATOMICRMW_AND*//*Label 17*/ 29610, 0,
823
4.50M
    /*TargetOpcode::G_ATOMICRMW_OR*//*Label 18*/ 31019,
824
4.50M
    /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 19*/ 32048,
825
4.50M
    /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 20*/ 33077,
826
4.50M
    /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 21*/ 34106,
827
4.50M
    /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 22*/ 35135,
828
4.50M
    /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 23*/ 36164, 0, 0,
829
4.50M
    /*TargetOpcode::G_INTRINSIC*//*Label 24*/ 37193,
830
4.50M
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 25*/ 71124,
831
4.50M
    /*TargetOpcode::G_ANYEXT*//*Label 26*/ 71304,
832
4.50M
    /*TargetOpcode::G_TRUNC*//*Label 27*/ 71418,
833
4.50M
    /*TargetOpcode::G_CONSTANT*//*Label 28*/ 71543,
834
4.50M
    /*TargetOpcode::G_FCONSTANT*//*Label 29*/ 71596, 0, 0,
835
4.50M
    /*TargetOpcode::G_SEXT*//*Label 30*/ 71674,
836
4.50M
    /*TargetOpcode::G_ZEXT*//*Label 31*/ 71788,
837
4.50M
    /*TargetOpcode::G_SHL*//*Label 32*/ 72247,
838
4.50M
    /*TargetOpcode::G_LSHR*//*Label 33*/ 72423,
839
4.50M
    /*TargetOpcode::G_ASHR*//*Label 34*/ 72674, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
840
4.50M
    /*TargetOpcode::G_FADD*//*Label 35*/ 72925,
841
4.50M
    /*TargetOpcode::G_FSUB*//*Label 36*/ 73198,
842
4.50M
    /*TargetOpcode::G_FMUL*//*Label 37*/ 73471,
843
4.50M
    /*TargetOpcode::G_FMA*//*Label 38*/ 73744,
844
4.50M
    /*TargetOpcode::G_FDIV*//*Label 39*/ 75268, 0, 0, 0, 0, 0, 0,
845
4.50M
    /*TargetOpcode::G_FNEG*//*Label 40*/ 75541,
846
4.50M
    /*TargetOpcode::G_FPEXT*//*Label 41*/ 76089,
847
4.50M
    /*TargetOpcode::G_FPTRUNC*//*Label 42*/ 76218,
848
4.50M
    /*TargetOpcode::G_FPTOSI*//*Label 43*/ 76347,
849
4.50M
    /*TargetOpcode::G_FPTOUI*//*Label 44*/ 76623,
850
4.50M
    /*TargetOpcode::G_SITOFP*//*Label 45*/ 76899,
851
4.50M
    /*TargetOpcode::G_UITOFP*//*Label 46*/ 77177, 0, 0, 0,
852
4.50M
    /*TargetOpcode::G_BR*//*Label 47*/ 77455, 0, 0, 0,
853
4.50M
    /*TargetOpcode::G_CTTZ*//*Label 48*/ 77468, 0,
854
4.50M
    /*TargetOpcode::G_CTLZ*//*Label 49*/ 77571, 0,
855
4.50M
    /*TargetOpcode::G_CTPOP*//*Label 50*/ 78194,
856
4.50M
    /*TargetOpcode::G_BSWAP*//*Label 51*/ 78252,
857
4.50M
    // Label 0: @106
858
4.50M
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 62*/ 7380,
859
4.50M
    /*GILLT_s32*//*Label 53*/ 122,
860
4.50M
    /*GILLT_s64*//*Label 54*/ 223, 0,
861
4.50M
    /*GILLT_v2s32*//*Label 55*/ 1295,
862
4.50M
    /*GILLT_v2s64*//*Label 56*/ 1908,
863
4.50M
    /*GILLT_v4s16*//*Label 57*/ 3011,
864
4.50M
    /*GILLT_v4s32*//*Label 58*/ 3624,
865
4.50M
    /*GILLT_v8s8*//*Label 59*/ 5097,
866
4.50M
    /*GILLT_v8s16*//*Label 60*/ 5502,
867
4.50M
    /*GILLT_v16s8*//*Label 61*/ 6975,
868
4.50M
    // Label 53: @122
869
4.50M
    GIM_Try, /*On fail goto*//*Label 63*/ 222,
870
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
871
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
872
4.50M
      GIM_Try, /*On fail goto*//*Label 64*/ 166, // Rule ID 3787 //
873
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
874
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID,
875
4.50M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
876
4.50M
        // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
877
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
878
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
879
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
880
4.50M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
881
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
882
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
883
4.50M
        // GIR_Coverage, 3787,
884
4.50M
        GIR_Done,
885
4.50M
      // Label 64: @166
886
4.50M
      GIM_Try, /*On fail goto*//*Label 65*/ 200, // Rule ID 33 //
887
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
888
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
889
4.50M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
890
4.50M
        // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
891
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
892
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
893
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
894
4.50M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
895
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
896
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
897
4.50M
        // GIR_Coverage, 33,
898
4.50M
        GIR_Done,
899
4.50M
      // Label 65: @200
900
4.50M
      GIM_Try, /*On fail goto*//*Label 66*/ 221, // Rule ID 35 //
901
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
902
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
903
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
904
4.50M
        // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
905
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDWrr,
906
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
907
4.50M
        // GIR_Coverage, 35,
908
4.50M
        GIR_Done,
909
4.50M
      // Label 66: @221
910
4.50M
      GIM_Reject,
911
4.50M
    // Label 63: @222
912
4.50M
    GIM_Reject,
913
4.50M
    // Label 54: @223
914
4.50M
    GIM_Try, /*On fail goto*//*Label 67*/ 1294,
915
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
916
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
917
4.50M
      GIM_Try, /*On fail goto*//*Label 68*/ 267, // Rule ID 3788 //
918
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
919
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID,
920
4.50M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
921
4.50M
        // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
922
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
923
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
924
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
925
4.50M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
926
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
927
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
928
4.50M
        // GIR_Coverage, 3788,
929
4.50M
        GIR_Done,
930
4.50M
      // Label 68: @267
931
4.50M
      GIM_Try, /*On fail goto*//*Label 69*/ 363, // Rule ID 1893 //
932
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
933
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
934
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
935
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
936
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
937
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
938
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
939
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
940
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
941
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
942
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
943
4.50M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
944
4.50M
        // MIs[3] Operand 1
945
4.50M
        // No operand predicates
946
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
947
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
948
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
949
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
950
4.50M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
951
4.50M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
952
4.50M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
953
4.50M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
954
4.50M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
955
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
956
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
957
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
958
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
959
4.50M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
960
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
961
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
962
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
963
4.50M
        // GIR_Coverage, 1893,
964
4.50M
        GIR_Done,
965
4.50M
      // Label 69: @363
966
4.50M
      GIM_Try, /*On fail goto*//*Label 70*/ 459, // Rule ID 1894 //
967
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
968
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
969
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
970
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
971
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
972
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
973
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
974
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
975
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
976
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
977
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
978
4.50M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
979
4.50M
        // MIs[3] Operand 1
980
4.50M
        // No operand predicates
981
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
982
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
983
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
984
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
985
4.50M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
986
4.50M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
987
4.50M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
988
4.50M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
989
4.50M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
990
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
991
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
992
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
993
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
994
4.50M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
995
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
996
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
997
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
998
4.50M
        // GIR_Coverage, 1894,
999
4.50M
        GIR_Done,
1000
4.50M
      // Label 70: @459
1001
4.50M
      GIM_Try, /*On fail goto*//*Label 71*/ 493, // Rule ID 34 //
1002
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
1003
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
1004
4.50M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
1005
4.50M
        // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
1006
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
1007
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1008
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1009
4.50M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
1010
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1011
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1012
4.50M
        // GIR_Coverage, 34,
1013
4.50M
        GIR_Done,
1014
4.50M
      // Label 71: @493
1015
4.50M
      GIM_Try, /*On fail goto*//*Label 72*/ 589, // Rule ID 4039 //
1016
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1017
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1018
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1019
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1020
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1021
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1022
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1023
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1024
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1025
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1026
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1027
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1028
4.50M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
1029
4.50M
        // MIs[3] Operand 1
1030
4.50M
        // No operand predicates
1031
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1032
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1033
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1034
4.50M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1035
4.50M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1036
4.50M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1037
4.50M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1038
4.50M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1039
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1040
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1041
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1042
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1043
4.50M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1044
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1045
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1046
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1047
4.50M
        // GIR_Coverage, 4039,
1048
4.50M
        GIR_Done,
1049
4.50M
      // Label 72: @589
1050
4.50M
      GIM_Try, /*On fail goto*//*Label 73*/ 685, // Rule ID 4040 //
1051
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1052
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1053
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1054
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1055
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1056
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1057
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1058
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1059
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1060
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1061
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1062
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1063
4.50M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
1064
4.50M
        // MIs[3] Operand 1
1065
4.50M
        // No operand predicates
1066
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1067
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1068
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1069
4.50M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1070
4.50M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1071
4.50M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1072
4.50M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1073
4.50M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1074
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1075
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1076
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1077
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1078
4.50M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1079
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1080
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1081
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1082
4.50M
        // GIR_Coverage, 4040,
1083
4.50M
        GIR_Done,
1084
4.50M
      // Label 73: @685
1085
4.50M
      GIM_Try, /*On fail goto*//*Label 74*/ 770, // Rule ID 3799 //
1086
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1087
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1088
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1089
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1090
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1091
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1092
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1093
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1094
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1095
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1096
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
1097
4.50M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1098
4.50M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1099
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1100
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1101
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1102
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1103
4.50M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1104
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1105
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1106
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1107
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1108
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1109
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1110
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1111
4.50M
        // GIR_Coverage, 3799,
1112
4.50M
        GIR_Done,
1113
4.50M
      // Label 74: @770
1114
4.50M
      GIM_Try, /*On fail goto*//*Label 75*/ 855, // Rule ID 3800 //
1115
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1116
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1117
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1118
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1119
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1120
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1121
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1122
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1123
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1124
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1125
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
1126
4.50M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1127
4.50M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1128
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1129
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1130
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1131
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1132
4.50M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1133
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1134
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1135
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1136
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1137
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1138
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1139
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1140
4.50M
        // GIR_Coverage, 3800,
1141
4.50M
        GIR_Done,
1142
4.50M
      // Label 75: @855
1143
4.50M
      GIM_Try, /*On fail goto*//*Label 76*/ 940, // Rule ID 65 //
1144
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1145
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1146
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1147
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1148
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1149
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1150
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1151
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1152
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1153
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1154
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1155
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
1156
4.50M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1157
4.50M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1158
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1159
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1160
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1161
4.50M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1162
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1163
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1164
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1165
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1166
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1167
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1168
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1169
4.50M
        // GIR_Coverage, 65,
1170
4.50M
        GIR_Done,
1171
4.50M
      // Label 76: @940
1172
4.50M
      GIM_Try, /*On fail goto*//*Label 77*/ 1025, // Rule ID 67 //
1173
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1174
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1175
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1176
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1177
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1178
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1179
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1180
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1181
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1182
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1183
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1184
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
1185
4.50M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1186
4.50M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1187
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1188
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1189
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1190
4.50M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1191
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1192
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1193
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1194
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1195
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1196
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1197
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1198
4.50M
        // GIR_Coverage, 67,
1199
4.50M
        GIR_Done,
1200
4.50M
      // Label 77: @1025
1201
4.50M
      GIM_Try, /*On fail goto*//*Label 78*/ 1081, // Rule ID 3853 //
1202
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1203
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1204
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1205
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1206
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1207
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1208
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1209
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1210
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1211
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1212
4.50M
        // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 271:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1213
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
1214
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1215
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1216
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1217
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1218
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1219
4.50M
        // GIR_Coverage, 3853,
1220
4.50M
        GIR_Done,
1221
4.50M
      // Label 78: @1081
1222
4.50M
      GIM_Try, /*On fail goto*//*Label 79*/ 1137, // Rule ID 3859 //
1223
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1224
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1225
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1226
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1227
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1228
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1229
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1230
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1231
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1232
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1233
4.50M
        // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 329:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1234
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64,
1235
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1236
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1237
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1238
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1239
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1240
4.50M
        // GIR_Coverage, 3859,
1241
4.50M
        GIR_Done,
1242
4.50M
      // Label 79: @1137
1243
4.50M
      GIM_Try, /*On fail goto*//*Label 80*/ 1193, // Rule ID 694 //
1244
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1245
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1246
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1247
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1248
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1249
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1250
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1251
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1252
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1253
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1254
4.50M
        // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 271:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1255
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
1256
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1257
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1258
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1259
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1260
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1261
4.50M
        // GIR_Coverage, 694,
1262
4.50M
        GIR_Done,
1263
4.50M
      // Label 80: @1193
1264
4.50M
      GIM_Try, /*On fail goto*//*Label 81*/ 1249, // Rule ID 738 //
1265
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1266
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1267
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1268
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1269
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1270
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1271
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1272
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1273
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1274
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1275
4.50M
        // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 329:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1276
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64,
1277
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1278
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1279
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1280
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1281
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1282
4.50M
        // GIR_Coverage, 738,
1283
4.50M
        GIR_Done,
1284
4.50M
      // Label 81: @1249
1285
4.50M
      GIM_Try, /*On fail goto*//*Label 82*/ 1270, // Rule ID 36 //
1286
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1287
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1288
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1289
4.50M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ADDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
1290
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDXrr,
1291
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1292
4.50M
        // GIR_Coverage, 36,
1293
4.50M
        GIR_Done,
1294
4.50M
      // Label 82: @1270
1295
4.50M
      GIM_Try, /*On fail goto*//*Label 83*/ 1293, // Rule ID 1193 //
1296
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1297
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1298
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1299
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1300
4.50M
        // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (ADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
1301
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv1i64,
1302
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1303
4.50M
        // GIR_Coverage, 1193,
1304
4.50M
        GIR_Done,
1305
4.50M
      // Label 83: @1293
1306
4.50M
      GIM_Reject,
1307
4.50M
    // Label 67: @1294
1308
4.50M
    GIM_Reject,
1309
4.50M
    // Label 55: @1295
1310
4.50M
    GIM_Try, /*On fail goto*//*Label 84*/ 1907,
1311
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1312
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1313
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1314
4.50M
      GIM_Try, /*On fail goto*//*Label 85*/ 1373, // Rule ID 3871 //
1315
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1316
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1317
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1318
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1319
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1320
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1321
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1322
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1323
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1324
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1325
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1326
4.50M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 270:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1327
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
1328
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1329
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1330
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1331
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1332
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1333
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1334
4.50M
        // GIR_Coverage, 3871,
1335
4.50M
        GIR_Done,
1336
4.50M
      // Label 85: @1373
1337
4.50M
      GIM_Try, /*On fail goto*//*Label 86*/ 1437, // Rule ID 3877 //
1338
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1339
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1340
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1341
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1342
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1343
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1344
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1345
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1346
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1347
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1348
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1349
4.50M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 328:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1350
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
1351
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1352
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1353
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1354
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1355
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1356
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1357
4.50M
        // GIR_Coverage, 3877,
1358
4.50M
        GIR_Done,
1359
4.50M
      // Label 86: @1437
1360
4.50M
      GIM_Try, /*On fail goto*//*Label 87*/ 1489, // Rule ID 3851 //
1361
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1362
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1363
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1364
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1365
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1366
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1367
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1368
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1369
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1370
4.50M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 271:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1371
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
1372
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1373
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1374
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1375
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1376
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1377
4.50M
        // GIR_Coverage, 3851,
1378
4.50M
        GIR_Done,
1379
4.50M
      // Label 87: @1489
1380
4.50M
      GIM_Try, /*On fail goto*//*Label 88*/ 1541, // Rule ID 3857 //
1381
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1382
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1383
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1384
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1385
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1386
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1387
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1388
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1389
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1390
4.50M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 329:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1391
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32,
1392
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1393
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1394
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1395
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1396
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1397
4.50M
        // GIR_Coverage, 3857,
1398
4.50M
        GIR_Done,
1399
4.50M
      // Label 88: @1541
1400
4.50M
      GIM_Try, /*On fail goto*//*Label 89*/ 1605, // Rule ID 968 //
1401
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1402
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1403
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1404
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1405
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1406
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1407
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1408
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1409
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1410
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1411
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1412
4.50M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 270:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1413
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
1414
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1415
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1416
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1417
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1418
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1419
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1420
4.50M
        // GIR_Coverage, 968,
1421
4.50M
        GIR_Done,
1422
4.50M
      // Label 89: @1605
1423
4.50M
      GIM_Try, /*On fail goto*//*Label 90*/ 1669, // Rule ID 1079 //
1424
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1425
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1426
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1427
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1428
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1429
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1430
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1431
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1432
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1433
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1434
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1435
4.50M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 328:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1436
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
1437
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1438
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1439
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1440
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1441
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1442
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1443
4.50M
        // GIR_Coverage, 1079,
1444
4.50M
        GIR_Done,
1445
4.50M
      // Label 90: @1669
1446
4.50M
      GIM_Try, /*On fail goto*//*Label 91*/ 1721, // Rule ID 692 //
1447
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1448
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1449
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1450
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1451
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1452
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1453
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1454
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1455
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1456
4.50M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 271:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1457
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
1458
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1459
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1460
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1461
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1462
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1463
4.50M
        // GIR_Coverage, 692,
1464
4.50M
        GIR_Done,
1465
4.50M
      // Label 91: @1721
1466
4.50M
      GIM_Try, /*On fail goto*//*Label 92*/ 1773, // Rule ID 736 //
1467
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1468
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1469
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1470
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1471
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1472
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1473
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1474
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1475
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1476
4.50M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 329:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1477
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32,
1478
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1479
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1480
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1481
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1482
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1483
4.50M
        // GIR_Coverage, 736,
1484
4.50M
        GIR_Done,
1485
4.50M
      // Label 92: @1773
1486
4.50M
      GIM_Try, /*On fail goto*//*Label 93*/ 1830, // Rule ID 3865 //
1487
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1488
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1489
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1490
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1491
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1492
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1493
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1494
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1495
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1496
4.50M
        // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (MLAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1497
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32,
1498
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1499
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1500
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1501
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1502
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1503
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1504
4.50M
        // GIR_Coverage, 3865,
1505
4.50M
        GIR_Done,
1506
4.50M
      // Label 93: @1830
1507
4.50M
      GIM_Try, /*On fail goto*//*Label 94*/ 1887, // Rule ID 948 //
1508
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1509
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1510
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1511
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1512
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1513
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1514
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1515
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1516
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1517
4.50M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (MLAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1518
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32,
1519
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1520
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1521
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1522
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1523
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1524
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1525
4.50M
        // GIR_Coverage, 948,
1526
4.50M
        GIR_Done,
1527
4.50M
      // Label 94: @1887
1528
4.50M
      GIM_Try, /*On fail goto*//*Label 95*/ 1906, // Rule ID 772 //
1529
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1530
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1531
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1532
4.50M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1533
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i32,
1534
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1535
4.50M
        // GIR_Coverage, 772,
1536
4.50M
        GIR_Done,
1537
4.50M
      // Label 95: @1906
1538
4.50M
      GIM_Reject,
1539
4.50M
    // Label 84: @1907
1540
4.50M
    GIM_Reject,
1541
4.50M
    // Label 56: @1908
1542
4.50M
    GIM_Try, /*On fail goto*//*Label 96*/ 3010,
1543
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1544
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1545
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
1546
4.50M
      GIM_Try, /*On fail goto*//*Label 97*/ 1999, // Rule ID 3925 //
1547
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1548
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1549
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1550
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1551
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1552
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1553
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1554
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1555
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1556
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1557
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1558
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1559
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1560
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1561
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1562
4.50M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 270:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1563
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
1564
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1565
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1566
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1567
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1568
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1569
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1570
4.50M
        // GIR_Coverage, 3925,
1571
4.50M
        GIR_Done,
1572
4.50M
      // Label 97: @1999
1573
4.50M
      GIM_Try, /*On fail goto*//*Label 98*/ 2076, // Rule ID 3943 //
1574
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1575
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1576
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1577
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1578
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1579
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1580
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1581
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1582
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1583
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1584
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1585
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1586
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1587
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1588
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1589
4.50M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 328:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1590
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
1591
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1592
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1593
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1594
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1595
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1596
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1597
4.50M
        // GIR_Coverage, 3943,
1598
4.50M
        GIR_Done,
1599
4.50M
      // Label 98: @2076
1600
4.50M
      GIM_Try, /*On fail goto*//*Label 99*/ 2153, // Rule ID 1275 //
1601
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1602
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1603
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1604
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1605
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1606
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1607
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1608
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1609
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1610
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1611
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1612
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1613
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1614
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1615
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1616
4.50M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 270:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1617
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
1618
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1619
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1620
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1621
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1622
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1623
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1624
4.50M
        // GIR_Coverage, 1275,
1625
4.50M
        GIR_Done,
1626
4.50M
      // Label 99: @2153
1627
4.50M
      GIM_Try, /*On fail goto*//*Label 100*/ 2230, // Rule ID 1341 //
1628
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1629
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1630
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1631
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1632
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1633
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1634
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1635
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1636
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1637
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1638
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1639
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1640
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1641
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1642
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1643
4.50M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 328:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1644
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
1645
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1646
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1647
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1648
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1649
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1650
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1651
4.50M
        // GIR_Coverage, 1341,
1652
4.50M
        GIR_Done,
1653
4.50M
      // Label 100: @2230
1654
4.50M
      GIM_Try, /*On fail goto*//*Label 101*/ 2294, // Rule ID 3937 //
1655
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1656
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1657
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1658
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1659
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
1660
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1661
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1662
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1663
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1664
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1665
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1666
4.50M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 287:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1667
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
1668
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1669
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1670
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1671
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1672
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1673
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1674
4.50M
        // GIR_Coverage, 3937,
1675
4.50M
        GIR_Done,
1676
4.50M
      // Label 101: @2294
1677
4.50M
      GIM_Try, /*On fail goto*//*Label 102*/ 2358, // Rule ID 3955 //
1678
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1679
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1680
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1681
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1682
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
1683
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1684
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1685
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1686
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1687
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1688
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1689
4.50M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 341:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1690
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
1691
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1692
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1693
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1694
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1695
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1696
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1697
4.50M
        // GIR_Coverage, 3955,
1698
4.50M
        GIR_Done,
1699
4.50M
      // Label 102: @2358
1700
4.50M
      GIM_Try, /*On fail goto*//*Label 103*/ 2410, // Rule ID 3854 //
1701
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1702
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1703
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1704
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1705
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1706
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1707
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1708
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1709
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1710
4.50M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 271:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1711
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
1712
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1713
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1714
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1715
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1716
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1717
4.50M
        // GIR_Coverage, 3854,
1718
4.50M
        GIR_Done,
1719
4.50M
      // Label 103: @2410
1720
4.50M
      GIM_Try, /*On fail goto*//*Label 104*/ 2462, // Rule ID 3860 //
1721
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1722
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1723
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1724
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1725
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1726
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1727
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1728
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1729
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1730
4.50M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 329:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1731
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64,
1732
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1733
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1734
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1735
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1736
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1737
4.50M
        // GIR_Coverage, 3860,
1738
4.50M
        GIR_Done,
1739
4.50M
      // Label 104: @2462
1740
4.50M
      GIM_Try, /*On fail goto*//*Label 105*/ 2526, // Rule ID 1299 //
1741
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1742
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1743
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1744
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1745
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1746
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
1747
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1748
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1749
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1750
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1751
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1752
4.50M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 287:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1753
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
1754
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1755
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1756
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1757
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1758
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1759
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1760
4.50M
        // GIR_Coverage, 1299,
1761
4.50M
        GIR_Done,
1762
4.50M
      // Label 105: @2526
1763
4.50M
      GIM_Try, /*On fail goto*//*Label 106*/ 2590, // Rule ID 1359 //
1764
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1765
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1766
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1767
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1768
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1769
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
1770
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1771
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1772
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1773
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1774
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1775
4.50M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 341:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1776
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
1777
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1778
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1779
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1780
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1781
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1782
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1783
4.50M
        // GIR_Coverage, 1359,
1784
4.50M
        GIR_Done,
1785
4.50M
      // Label 106: @2590
1786
4.50M
      GIM_Try, /*On fail goto*//*Label 107*/ 2642, // Rule ID 695 //
1787
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1788
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1789
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1790
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1791
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1792
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1793
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1794
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1795
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1796
4.50M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 271:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1797
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
1798
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1799
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1800
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1801
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1802
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1803
4.50M
        // GIR_Coverage, 695,
1804
4.50M
        GIR_Done,
1805
4.50M
      // Label 107: @2642
1806
4.50M
      GIM_Try, /*On fail goto*//*Label 108*/ 2694, // Rule ID 739 //
1807
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1808
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1809
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1810
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1811
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1812
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1813
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1814
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1815
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1816
4.50M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 329:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1817
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64,
1818
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1819
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1820
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1821
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1822
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1823
4.50M
        // GIR_Coverage, 739,
1824
4.50M
        GIR_Done,
1825
4.50M
      // Label 108: @2694
1826
4.50M
      GIM_Try, /*On fail goto*//*Label 109*/ 2752, // Rule ID 1287 //
1827
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1828
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1829
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1830
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1831
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1832
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1833
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1834
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1835
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1836
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1837
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1838
4.50M
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1839
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv2i32_v2i64,
1840
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1841
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1842
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1843
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1844
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1845
4.50M
        // GIR_Coverage, 1287,
1846
4.50M
        GIR_Done,
1847
4.50M
      // Label 109: @2752
1848
4.50M
      GIM_Try, /*On fail goto*//*Label 110*/ 2810, // Rule ID 1347 //
1849
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1850
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1851
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1852
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1853
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1854
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1855
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1856
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1857
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1858
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1859
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1860
4.50M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1861
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64,
1862
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1863
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1864
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1865
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1866
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1867
4.50M
        // GIR_Coverage, 1347,
1868
4.50M
        GIR_Done,
1869
4.50M
      // Label 110: @2810
1870
4.50M
      GIM_Try, /*On fail goto*//*Label 111*/ 2855, // Rule ID 3931 //
1871
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1872
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1873
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1874
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1875
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1876
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1877
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1878
4.50M
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1879
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64,
1880
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1881
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1882
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1883
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1884
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1885
4.50M
        // GIR_Coverage, 3931,
1886
4.50M
        GIR_Done,
1887
4.50M
      // Label 111: @2855
1888
4.50M
      GIM_Try, /*On fail goto*//*Label 112*/ 2900, // Rule ID 3949 //
1889
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1890
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1891
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1892
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1893
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1894
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1895
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1896
4.50M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1897
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64,
1898
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1899
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1900
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1901
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1902
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1903
4.50M
        // GIR_Coverage, 3949,
1904
4.50M
        GIR_Done,
1905
4.50M
      // Label 112: @2900
1906
4.50M
      GIM_Try, /*On fail goto*//*Label 113*/ 2945, // Rule ID 1293 //
1907
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1908
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1909
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1910
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1911
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1912
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1913
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1914
4.50M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1915
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64,
1916
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1917
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1918
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1919
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1920
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1921
4.50M
        // GIR_Coverage, 1293,
1922
4.50M
        GIR_Done,
1923
4.50M
      // Label 113: @2945
1924
4.50M
      GIM_Try, /*On fail goto*//*Label 114*/ 2990, // Rule ID 1353 //
1925
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1926
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1927
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1928
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1929
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1930
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1931
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1932
4.50M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1933
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64,
1934
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1935
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1936
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1937
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1938
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1939
4.50M
        // GIR_Coverage, 1353,
1940
4.50M
        GIR_Done,
1941
4.50M
      // Label 114: @2990
1942
4.50M
      GIM_Try, /*On fail goto*//*Label 115*/ 3009, // Rule ID 774 //
1943
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1944
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1945
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1946
4.50M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
1947
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i64,
1948
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1949
4.50M
        // GIR_Coverage, 774,
1950
4.50M
        GIR_Done,
1951
4.50M
      // Label 115: @3009
1952
4.50M
      GIM_Reject,
1953
4.50M
    // Label 96: @3010
1954
4.50M
    GIM_Reject,
1955
4.50M
    // Label 57: @3011
1956
4.50M
    GIM_Try, /*On fail goto*//*Label 116*/ 3623,
1957
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1958
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
1959
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1960
4.50M
      GIM_Try, /*On fail goto*//*Label 117*/ 3089, // Rule ID 3869 //
1961
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1962
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1963
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1964
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1965
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1966
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1967
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1968
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1969
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1970
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1971
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1972
4.50M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 270:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
1973
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
1974
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1975
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1976
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1977
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1978
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
1979
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1980
4.50M
        // GIR_Coverage, 3869,
1981
4.50M
        GIR_Done,
1982
4.50M
      // Label 117: @3089
1983
4.50M
      GIM_Try, /*On fail goto*//*Label 118*/ 3153, // Rule ID 3875 //
1984
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
1985
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1986
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1987
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1988
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1989
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1990
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1991
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1992
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1993
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1994
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1995
4.50M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 328:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
1996
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
1997
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1998
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1999
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2000
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2001
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2002
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2003
4.50M
        // GIR_Coverage, 3875,
2004
4.50M
        GIR_Done,
2005
4.50M
      // Label 118: @3153
2006
4.50M
      GIM_Try, /*On fail goto*//*Label 119*/ 3205, // Rule ID 3849 //
2007
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2008
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2009
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2010
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2011
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2012
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2013
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2014
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2015
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2016
4.50M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 271:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2017
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
2018
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2019
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2020
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2021
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2022
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2023
4.50M
        // GIR_Coverage, 3849,
2024
4.50M
        GIR_Done,
2025
4.50M
      // Label 119: @3205
2026
4.50M
      GIM_Try, /*On fail goto*//*Label 120*/ 3257, // Rule ID 3855 //
2027
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2028
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2029
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2030
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2031
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2032
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2033
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2034
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2035
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2036
4.50M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 329:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2037
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
2038
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2039
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2040
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2041
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2042
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2043
4.50M
        // GIR_Coverage, 3855,
2044
4.50M
        GIR_Done,
2045
4.50M
      // Label 120: @3257
2046
4.50M
      GIM_Try, /*On fail goto*//*Label 121*/ 3321, // Rule ID 966 //
2047
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2048
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2049
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2050
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2051
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2052
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2053
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2054
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2055
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2056
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2057
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2058
4.50M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 270:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2059
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
2060
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2061
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2062
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2063
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2064
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2065
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2066
4.50M
        // GIR_Coverage, 966,
2067
4.50M
        GIR_Done,
2068
4.50M
      // Label 121: @3321
2069
4.50M
      GIM_Try, /*On fail goto*//*Label 122*/ 3385, // Rule ID 1077 //
2070
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2071
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2072
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2073
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2074
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2075
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2076
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2077
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2078
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2079
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2080
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2081
4.50M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 328:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2082
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
2083
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2084
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2085
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2086
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2087
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2088
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2089
4.50M
        // GIR_Coverage, 1077,
2090
4.50M
        GIR_Done,
2091
4.50M
      // Label 122: @3385
2092
4.50M
      GIM_Try, /*On fail goto*//*Label 123*/ 3437, // Rule ID 690 //
2093
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2094
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2095
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2096
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2097
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2098
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2099
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2100
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2101
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2102
4.50M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 271:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2103
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
2104
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2105
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2106
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2107
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2108
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2109
4.50M
        // GIR_Coverage, 690,
2110
4.50M
        GIR_Done,
2111
4.50M
      // Label 123: @3437
2112
4.50M
      GIM_Try, /*On fail goto*//*Label 124*/ 3489, // Rule ID 734 //
2113
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2114
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2115
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2116
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2117
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2118
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2119
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2120
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2121
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2122
4.50M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 329:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2123
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
2124
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2125
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2126
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2127
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2128
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2129
4.50M
        // GIR_Coverage, 734,
2130
4.50M
        GIR_Done,
2131
4.50M
      // Label 124: @3489
2132
4.50M
      GIM_Try, /*On fail goto*//*Label 125*/ 3546, // Rule ID 3863 //
2133
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2134
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2135
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2136
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2137
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2138
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2139
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2140
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2141
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2142
4.50M
        // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (MLAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2143
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16,
2144
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2145
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2146
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2147
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2148
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2149
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2150
4.50M
        // GIR_Coverage, 3863,
2151
4.50M
        GIR_Done,
2152
4.50M
      // Label 125: @3546
2153
4.50M
      GIM_Try, /*On fail goto*//*Label 126*/ 3603, // Rule ID 946 //
2154
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2155
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2156
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2157
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2158
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2159
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2160
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2161
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2162
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2163
4.50M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (MLAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2164
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16,
2165
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2166
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2167
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2168
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2169
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2170
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2171
4.50M
        // GIR_Coverage, 946,
2172
4.50M
        GIR_Done,
2173
4.50M
      // Label 126: @3603
2174
4.50M
      GIM_Try, /*On fail goto*//*Label 127*/ 3622, // Rule ID 770 //
2175
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2176
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2177
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2178
4.50M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2179
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i16,
2180
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2181
4.50M
        // GIR_Coverage, 770,
2182
4.50M
        GIR_Done,
2183
4.50M
      // Label 127: @3622
2184
4.50M
      GIM_Reject,
2185
4.50M
    // Label 116: @3623
2186
4.50M
    GIM_Reject,
2187
4.50M
    // Label 58: @3624
2188
4.50M
    GIM_Try, /*On fail goto*//*Label 128*/ 5096,
2189
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2190
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2191
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
2192
4.50M
      GIM_Try, /*On fail goto*//*Label 129*/ 3715, // Rule ID 3923 //
2193
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2194
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2195
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2196
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2197
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2198
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2199
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2200
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2201
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2202
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2203
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2204
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2205
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2206
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2207
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2208
4.50M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 270:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2209
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
2210
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2211
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2212
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2213
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2214
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2215
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2216
4.50M
        // GIR_Coverage, 3923,
2217
4.50M
        GIR_Done,
2218
4.50M
      // Label 129: @3715
2219
4.50M
      GIM_Try, /*On fail goto*//*Label 130*/ 3792, // Rule ID 3941 //
2220
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2221
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2222
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2223
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2224
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2225
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2226
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2227
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2228
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2229
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2230
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2231
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2232
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2233
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2234
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2235
4.50M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 328:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2236
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
2237
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2238
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2239
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2240
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2241
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2242
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2243
4.50M
        // GIR_Coverage, 3941,
2244
4.50M
        GIR_Done,
2245
4.50M
      // Label 130: @3792
2246
4.50M
      GIM_Try, /*On fail goto*//*Label 131*/ 3869, // Rule ID 1273 //
2247
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2248
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2249
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2250
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2251
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2252
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2253
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2254
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2255
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2256
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2257
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2258
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2259
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2260
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2261
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2262
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 270:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2263
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
2264
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2265
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2266
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2267
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2268
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2269
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2270
4.50M
        // GIR_Coverage, 1273,
2271
4.50M
        GIR_Done,
2272
4.50M
      // Label 131: @3869
2273
4.50M
      GIM_Try, /*On fail goto*//*Label 132*/ 3946, // Rule ID 1339 //
2274
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2275
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2276
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2277
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2278
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2279
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2280
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2281
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2282
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2283
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2284
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2285
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2286
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2287
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2288
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2289
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 328:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2290
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
2291
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2292
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2293
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2294
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2295
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2296
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2297
4.50M
        // GIR_Coverage, 1339,
2298
4.50M
        GIR_Done,
2299
4.50M
      // Label 132: @3946
2300
4.50M
      GIM_Try, /*On fail goto*//*Label 133*/ 4010, // Rule ID 3872 //
2301
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2302
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2303
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2304
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2305
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2306
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2307
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2308
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2309
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2310
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2311
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2312
4.50M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 270:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2313
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
2314
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2315
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2316
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2317
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2318
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2319
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2320
4.50M
        // GIR_Coverage, 3872,
2321
4.50M
        GIR_Done,
2322
4.50M
      // Label 133: @4010
2323
4.50M
      GIM_Try, /*On fail goto*//*Label 134*/ 4074, // Rule ID 3878 //
2324
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2325
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2326
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2327
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2328
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2329
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2330
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2331
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2332
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2333
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2334
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2335
4.50M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 328:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2336
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
2337
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2338
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2339
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2340
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2341
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2342
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2343
4.50M
        // GIR_Coverage, 3878,
2344
4.50M
        GIR_Done,
2345
4.50M
      // Label 134: @4074
2346
4.50M
      GIM_Try, /*On fail goto*//*Label 135*/ 4138, // Rule ID 3935 //
2347
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2348
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2349
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2350
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2351
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
2352
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2353
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2354
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2355
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2356
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2357
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2358
4.50M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 287:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2359
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
2360
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2361
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2362
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2363
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2364
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2365
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2366
4.50M
        // GIR_Coverage, 3935,
2367
4.50M
        GIR_Done,
2368
4.50M
      // Label 135: @4138
2369
4.50M
      GIM_Try, /*On fail goto*//*Label 136*/ 4202, // Rule ID 3953 //
2370
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2371
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2372
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2373
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2374
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
2375
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2376
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2377
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2378
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2379
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2380
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2381
4.50M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 341:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2382
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
2383
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2384
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2385
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2386
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2387
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2388
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2389
4.50M
        // GIR_Coverage, 3953,
2390
4.50M
        GIR_Done,
2391
4.50M
      // Label 136: @4202
2392
4.50M
      GIM_Try, /*On fail goto*//*Label 137*/ 4254, // Rule ID 3852 //
2393
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2394
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2395
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2396
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2397
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2398
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2399
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2400
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2401
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2402
4.50M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 271:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2403
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
2404
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2405
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2406
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2407
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2408
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2409
4.50M
        // GIR_Coverage, 3852,
2410
4.50M
        GIR_Done,
2411
4.50M
      // Label 137: @4254
2412
4.50M
      GIM_Try, /*On fail goto*//*Label 138*/ 4306, // Rule ID 3858 //
2413
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2414
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2415
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2416
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2417
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2418
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2419
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2420
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2421
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2422
4.50M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 329:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2423
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32,
2424
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2425
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2426
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2427
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2428
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2429
4.50M
        // GIR_Coverage, 3858,
2430
4.50M
        GIR_Done,
2431
4.50M
      // Label 138: @4306
2432
4.50M
      GIM_Try, /*On fail goto*//*Label 139*/ 4370, // Rule ID 969 //
2433
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2434
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2435
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2436
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2437
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2438
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2439
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2440
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2441
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2442
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2443
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2444
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 270:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2445
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
2446
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2447
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2448
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2449
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2450
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2451
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2452
4.50M
        // GIR_Coverage, 969,
2453
4.50M
        GIR_Done,
2454
4.50M
      // Label 139: @4370
2455
4.50M
      GIM_Try, /*On fail goto*//*Label 140*/ 4434, // Rule ID 1080 //
2456
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2457
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2458
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2459
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2460
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2461
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2462
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2463
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2464
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2465
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2466
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2467
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 328:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2468
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
2469
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2470
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2471
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2472
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2473
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2474
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2475
4.50M
        // GIR_Coverage, 1080,
2476
4.50M
        GIR_Done,
2477
4.50M
      // Label 140: @4434
2478
4.50M
      GIM_Try, /*On fail goto*//*Label 141*/ 4498, // Rule ID 1297 //
2479
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2480
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2481
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2482
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2483
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2484
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
2485
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2486
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2487
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2488
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2489
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2490
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 287:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2491
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
2492
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2493
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2494
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2495
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2496
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2497
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2498
4.50M
        // GIR_Coverage, 1297,
2499
4.50M
        GIR_Done,
2500
4.50M
      // Label 141: @4498
2501
4.50M
      GIM_Try, /*On fail goto*//*Label 142*/ 4562, // Rule ID 1357 //
2502
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2503
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2504
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2505
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2506
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2507
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
2508
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2509
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2510
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2511
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2512
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2513
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 341:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2514
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
2515
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2516
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2517
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2518
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2519
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2520
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2521
4.50M
        // GIR_Coverage, 1357,
2522
4.50M
        GIR_Done,
2523
4.50M
      // Label 142: @4562
2524
4.50M
      GIM_Try, /*On fail goto*//*Label 143*/ 4614, // Rule ID 693 //
2525
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2526
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2527
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2528
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2529
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2530
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2531
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2532
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2533
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2534
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 271:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2535
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
2536
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2537
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2538
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2539
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2540
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2541
4.50M
        // GIR_Coverage, 693,
2542
4.50M
        GIR_Done,
2543
4.50M
      // Label 143: @4614
2544
4.50M
      GIM_Try, /*On fail goto*//*Label 144*/ 4666, // Rule ID 737 //
2545
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2546
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2547
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2548
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2549
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2550
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2551
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2552
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2553
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2554
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 329:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2555
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32,
2556
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2557
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2558
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2559
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2560
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2561
4.50M
        // GIR_Coverage, 737,
2562
4.50M
        GIR_Done,
2563
4.50M
      // Label 144: @4666
2564
4.50M
      GIM_Try, /*On fail goto*//*Label 145*/ 4724, // Rule ID 1285 //
2565
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2566
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2567
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2568
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2569
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2570
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2571
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2572
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2573
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2574
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2575
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2576
4.50M
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2577
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv4i16_v4i32,
2578
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2579
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2580
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
2581
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2582
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2583
4.50M
        // GIR_Coverage, 1285,
2584
4.50M
        GIR_Done,
2585
4.50M
      // Label 145: @4724
2586
4.50M
      GIM_Try, /*On fail goto*//*Label 146*/ 4782, // Rule ID 1345 //
2587
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2588
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2589
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2590
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2591
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2592
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2593
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2594
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2595
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2596
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2597
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2598
4.50M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2599
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32,
2600
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2601
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2602
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
2603
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2604
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2605
4.50M
        // GIR_Coverage, 1345,
2606
4.50M
        GIR_Done,
2607
4.50M
      // Label 146: @4782
2608
4.50M
      GIM_Try, /*On fail goto*//*Label 147*/ 4839, // Rule ID 3866 //
2609
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2610
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2611
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2612
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2613
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2614
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2615
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2616
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2617
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2618
4.50M
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (MLAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2619
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32,
2620
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2621
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2622
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2623
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2624
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2625
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2626
4.50M
        // GIR_Coverage, 3866,
2627
4.50M
        GIR_Done,
2628
4.50M
      // Label 147: @4839
2629
4.50M
      GIM_Try, /*On fail goto*//*Label 148*/ 4884, // Rule ID 3929 //
2630
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2631
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2632
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2633
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2634
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2635
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2636
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2637
4.50M
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2638
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32,
2639
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2640
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
2641
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2642
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2643
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2644
4.50M
        // GIR_Coverage, 3929,
2645
4.50M
        GIR_Done,
2646
4.50M
      // Label 148: @4884
2647
4.50M
      GIM_Try, /*On fail goto*//*Label 149*/ 4929, // Rule ID 3947 //
2648
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2649
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2650
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2651
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2652
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2653
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2654
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2655
4.50M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2656
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32,
2657
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2658
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
2659
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2660
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2661
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2662
4.50M
        // GIR_Coverage, 3947,
2663
4.50M
        GIR_Done,
2664
4.50M
      // Label 149: @4929
2665
4.50M
      GIM_Try, /*On fail goto*//*Label 150*/ 4986, // Rule ID 949 //
2666
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2667
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2668
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2669
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2670
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2671
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2672
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2673
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2674
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2675
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (MLAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2676
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32,
2677
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2678
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2679
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2680
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2681
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2682
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2683
4.50M
        // GIR_Coverage, 949,
2684
4.50M
        GIR_Done,
2685
4.50M
      // Label 150: @4986
2686
4.50M
      GIM_Try, /*On fail goto*//*Label 151*/ 5031, // Rule ID 1291 //
2687
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2688
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2689
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2690
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2691
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2692
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2693
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2694
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2695
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32,
2696
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2697
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
2698
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2699
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2700
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2701
4.50M
        // GIR_Coverage, 1291,
2702
4.50M
        GIR_Done,
2703
4.50M
      // Label 151: @5031
2704
4.50M
      GIM_Try, /*On fail goto*//*Label 152*/ 5076, // Rule ID 1351 //
2705
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2706
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2707
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2708
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2709
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2710
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2711
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2712
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2713
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32,
2714
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2715
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
2716
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2717
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2718
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2719
4.50M
        // GIR_Coverage, 1351,
2720
4.50M
        GIR_Done,
2721
4.50M
      // Label 152: @5076
2722
4.50M
      GIM_Try, /*On fail goto*//*Label 153*/ 5095, // Rule ID 773 //
2723
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2724
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2725
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2726
4.50M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2727
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i32,
2728
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2729
4.50M
        // GIR_Coverage, 773,
2730
4.50M
        GIR_Done,
2731
4.50M
      // Label 153: @5095
2732
4.50M
      GIM_Reject,
2733
4.50M
    // Label 128: @5096
2734
4.50M
    GIM_Reject,
2735
4.50M
    // Label 59: @5097
2736
4.50M
    GIM_Try, /*On fail goto*//*Label 154*/ 5501,
2737
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
2738
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
2739
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
2740
4.50M
      GIM_Try, /*On fail goto*//*Label 155*/ 5175, // Rule ID 3867 //
2741
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2742
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2743
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2744
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2745
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2746
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2747
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2748
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2749
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2750
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2751
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2752
4.50M
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 270:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2753
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
2754
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2755
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2756
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2757
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2758
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2759
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2760
4.50M
        // GIR_Coverage, 3867,
2761
4.50M
        GIR_Done,
2762
4.50M
      // Label 155: @5175
2763
4.50M
      GIM_Try, /*On fail goto*//*Label 156*/ 5239, // Rule ID 3873 //
2764
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2765
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2766
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2767
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2768
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2769
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2770
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2771
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2772
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2773
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2774
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2775
4.50M
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 328:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2776
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
2777
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2778
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2779
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2780
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2781
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2782
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2783
4.50M
        // GIR_Coverage, 3873,
2784
4.50M
        GIR_Done,
2785
4.50M
      // Label 156: @5239
2786
4.50M
      GIM_Try, /*On fail goto*//*Label 157*/ 5303, // Rule ID 964 //
2787
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2788
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2789
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2790
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2791
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2792
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2793
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2794
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2795
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2796
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2797
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2798
4.50M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 270:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2799
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
2800
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2801
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2802
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2803
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2804
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2805
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2806
4.50M
        // GIR_Coverage, 964,
2807
4.50M
        GIR_Done,
2808
4.50M
      // Label 157: @5303
2809
4.50M
      GIM_Try, /*On fail goto*//*Label 158*/ 5367, // Rule ID 1075 //
2810
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2811
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2812
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2813
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2814
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2815
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2816
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2817
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2818
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2819
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2820
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2821
4.50M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 328:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2822
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
2823
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2824
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2825
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2826
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2827
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2828
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2829
4.50M
        // GIR_Coverage, 1075,
2830
4.50M
        GIR_Done,
2831
4.50M
      // Label 158: @5367
2832
4.50M
      GIM_Try, /*On fail goto*//*Label 159*/ 5424, // Rule ID 3861 //
2833
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2834
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2835
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2836
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2837
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2838
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2839
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2840
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2841
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2842
4.50M
        // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (MLAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2843
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8,
2844
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2845
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2846
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2847
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2848
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2849
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2850
4.50M
        // GIR_Coverage, 3861,
2851
4.50M
        GIR_Done,
2852
4.50M
      // Label 159: @5424
2853
4.50M
      GIM_Try, /*On fail goto*//*Label 160*/ 5481, // Rule ID 944 //
2854
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2855
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2856
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2857
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2858
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2859
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2860
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2861
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2862
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2863
4.50M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (MLAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2864
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8,
2865
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2866
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2867
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2868
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2869
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2870
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2871
4.50M
        // GIR_Coverage, 944,
2872
4.50M
        GIR_Done,
2873
4.50M
      // Label 160: @5481
2874
4.50M
      GIM_Try, /*On fail goto*//*Label 161*/ 5500, // Rule ID 768 //
2875
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2876
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2877
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2878
4.50M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2879
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i8,
2880
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2881
4.50M
        // GIR_Coverage, 768,
2882
4.50M
        GIR_Done,
2883
4.50M
      // Label 161: @5500
2884
4.50M
      GIM_Reject,
2885
4.50M
    // Label 154: @5501
2886
4.50M
    GIM_Reject,
2887
4.50M
    // Label 60: @5502
2888
4.50M
    GIM_Try, /*On fail goto*//*Label 162*/ 6974,
2889
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2890
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2891
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
2892
4.50M
      GIM_Try, /*On fail goto*//*Label 163*/ 5593, // Rule ID 3921 //
2893
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2894
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2895
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2896
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2897
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2898
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2899
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2900
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2901
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2902
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2903
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2904
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2905
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2906
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2907
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2908
4.50M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 270:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2909
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
2910
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2911
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2912
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2913
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2914
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2915
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2916
4.50M
        // GIR_Coverage, 3921,
2917
4.50M
        GIR_Done,
2918
4.50M
      // Label 163: @5593
2919
4.50M
      GIM_Try, /*On fail goto*//*Label 164*/ 5670, // Rule ID 3939 //
2920
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2921
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2922
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2923
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2924
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2925
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2926
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2927
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2928
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2929
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2930
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2931
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2932
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2933
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2934
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2935
4.50M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 328:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2936
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
2937
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2938
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2939
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2940
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2941
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2942
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2943
4.50M
        // GIR_Coverage, 3939,
2944
4.50M
        GIR_Done,
2945
4.50M
      // Label 164: @5670
2946
4.50M
      GIM_Try, /*On fail goto*//*Label 165*/ 5747, // Rule ID 1271 //
2947
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2948
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2949
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2950
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2951
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2952
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2953
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2954
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2955
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2956
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2957
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2958
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2959
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2960
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2961
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2962
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 270:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2963
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
2964
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2965
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2966
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2967
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2968
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2969
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2970
4.50M
        // GIR_Coverage, 1271,
2971
4.50M
        GIR_Done,
2972
4.50M
      // Label 165: @5747
2973
4.50M
      GIM_Try, /*On fail goto*//*Label 166*/ 5824, // Rule ID 1337 //
2974
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
2975
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2976
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2977
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2978
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2979
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2980
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2981
4.50M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2982
4.50M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2983
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2984
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2985
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2986
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2987
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2988
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2989
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 328:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2990
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
2991
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2992
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2993
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2994
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2995
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
2996
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2997
4.50M
        // GIR_Coverage, 1337,
2998
4.50M
        GIR_Done,
2999
4.50M
      // Label 166: @5824
3000
4.50M
      GIM_Try, /*On fail goto*//*Label 167*/ 5888, // Rule ID 3870 //
3001
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3002
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3003
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3004
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3005
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3006
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3007
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3008
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3009
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3010
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3011
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3012
4.50M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 270:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3013
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
3014
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3015
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3016
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3017
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3018
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3019
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3020
4.50M
        // GIR_Coverage, 3870,
3021
4.50M
        GIR_Done,
3022
4.50M
      // Label 167: @5888
3023
4.50M
      GIM_Try, /*On fail goto*//*Label 168*/ 5952, // Rule ID 3876 //
3024
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3025
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3026
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3027
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3028
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3029
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3030
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3031
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3032
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3033
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3034
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3035
4.50M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 328:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3036
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
3037
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3038
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3039
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3040
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3041
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3042
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3043
4.50M
        // GIR_Coverage, 3876,
3044
4.50M
        GIR_Done,
3045
4.50M
      // Label 168: @5952
3046
4.50M
      GIM_Try, /*On fail goto*//*Label 169*/ 6016, // Rule ID 3933 //
3047
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3048
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3049
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3050
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3051
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
3052
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3053
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3054
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3055
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3056
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3057
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3058
4.50M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 287:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3059
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
3060
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3061
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3062
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3063
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3064
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3065
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3066
4.50M
        // GIR_Coverage, 3933,
3067
4.50M
        GIR_Done,
3068
4.50M
      // Label 169: @6016
3069
4.50M
      GIM_Try, /*On fail goto*//*Label 170*/ 6080, // Rule ID 3951 //
3070
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3071
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3072
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3073
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3074
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
3075
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3076
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3077
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3078
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3079
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3080
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3081
4.50M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 341:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3082
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
3083
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3084
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3085
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3086
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3087
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3088
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3089
4.50M
        // GIR_Coverage, 3951,
3090
4.50M
        GIR_Done,
3091
4.50M
      // Label 170: @6080
3092
4.50M
      GIM_Try, /*On fail goto*//*Label 171*/ 6132, // Rule ID 3850 //
3093
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3094
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3095
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3096
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3097
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
3098
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3099
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3100
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3101
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3102
4.50M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 271:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3103
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
3104
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3105
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3106
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3107
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3108
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3109
4.50M
        // GIR_Coverage, 3850,
3110
4.50M
        GIR_Done,
3111
4.50M
      // Label 171: @6132
3112
4.50M
      GIM_Try, /*On fail goto*//*Label 172*/ 6184, // Rule ID 3856 //
3113
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3114
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3115
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3116
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3117
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
3118
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3119
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3120
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3121
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3122
4.50M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 329:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3123
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
3124
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3125
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3126
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3127
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3128
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3129
4.50M
        // GIR_Coverage, 3856,
3130
4.50M
        GIR_Done,
3131
4.50M
      // Label 172: @6184
3132
4.50M
      GIM_Try, /*On fail goto*//*Label 173*/ 6248, // Rule ID 967 //
3133
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3134
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3135
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3136
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3137
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3138
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3139
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3140
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3141
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3142
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3143
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3144
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 270:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3145
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
3146
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3147
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3148
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3149
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3150
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3151
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3152
4.50M
        // GIR_Coverage, 967,
3153
4.50M
        GIR_Done,
3154
4.50M
      // Label 173: @6248
3155
4.50M
      GIM_Try, /*On fail goto*//*Label 174*/ 6312, // Rule ID 1078 //
3156
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3157
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3158
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3159
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3160
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3161
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3162
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3163
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3164
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3165
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3166
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3167
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 328:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3168
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
3169
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3170
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3171
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3172
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3173
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3174
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3175
4.50M
        // GIR_Coverage, 1078,
3176
4.50M
        GIR_Done,
3177
4.50M
      // Label 174: @6312
3178
4.50M
      GIM_Try, /*On fail goto*//*Label 175*/ 6376, // Rule ID 1295 //
3179
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3180
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3181
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3182
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3183
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3184
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
3185
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3186
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3187
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3188
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3189
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3190
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 287:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3191
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
3192
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3193
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3194
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3195
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3196
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3197
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3198
4.50M
        // GIR_Coverage, 1295,
3199
4.50M
        GIR_Done,
3200
4.50M
      // Label 175: @6376
3201
4.50M
      GIM_Try, /*On fail goto*//*Label 176*/ 6440, // Rule ID 1355 //
3202
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3203
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3204
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3205
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3206
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3207
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
3208
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3209
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3210
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3211
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3212
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3213
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 341:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3214
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
3215
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3216
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3217
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3218
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3219
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3220
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3221
4.50M
        // GIR_Coverage, 1355,
3222
4.50M
        GIR_Done,
3223
4.50M
      // Label 176: @6440
3224
4.50M
      GIM_Try, /*On fail goto*//*Label 177*/ 6492, // Rule ID 691 //
3225
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3226
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3227
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3228
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3229
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3230
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
3231
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3232
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3233
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3234
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 271:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3235
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
3236
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3237
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3238
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3239
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3240
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3241
4.50M
        // GIR_Coverage, 691,
3242
4.50M
        GIR_Done,
3243
4.50M
      // Label 177: @6492
3244
4.50M
      GIM_Try, /*On fail goto*//*Label 178*/ 6544, // Rule ID 735 //
3245
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3246
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3247
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3248
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3249
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3250
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
3251
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3252
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3253
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3254
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 329:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3255
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
3256
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3257
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3258
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3259
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3260
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3261
4.50M
        // GIR_Coverage, 735,
3262
4.50M
        GIR_Done,
3263
4.50M
      // Label 178: @6544
3264
4.50M
      GIM_Try, /*On fail goto*//*Label 179*/ 6602, // Rule ID 1283 //
3265
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3266
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3267
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3268
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3269
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3270
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3271
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3272
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3273
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3274
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3275
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3276
4.50M
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3277
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv8i8_v8i16,
3278
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3279
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3280
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3281
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3282
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3283
4.50M
        // GIR_Coverage, 1283,
3284
4.50M
        GIR_Done,
3285
4.50M
      // Label 179: @6602
3286
4.50M
      GIM_Try, /*On fail goto*//*Label 180*/ 6660, // Rule ID 1343 //
3287
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3288
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3289
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3290
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3291
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3292
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3293
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3294
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3295
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3296
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3297
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3298
4.50M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3299
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16,
3300
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3301
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3302
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3303
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3304
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3305
4.50M
        // GIR_Coverage, 1343,
3306
4.50M
        GIR_Done,
3307
4.50M
      // Label 180: @6660
3308
4.50M
      GIM_Try, /*On fail goto*//*Label 181*/ 6717, // Rule ID 3864 //
3309
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3310
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3311
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3312
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3313
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3314
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3315
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3316
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3317
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3318
4.50M
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (MLAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3319
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16,
3320
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3321
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3322
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3323
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3324
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3325
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3326
4.50M
        // GIR_Coverage, 3864,
3327
4.50M
        GIR_Done,
3328
4.50M
      // Label 181: @6717
3329
4.50M
      GIM_Try, /*On fail goto*//*Label 182*/ 6762, // Rule ID 3927 //
3330
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3331
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3332
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3333
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3334
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3335
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3336
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3337
4.50M
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3338
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16,
3339
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3340
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3341
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3342
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3343
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3344
4.50M
        // GIR_Coverage, 3927,
3345
4.50M
        GIR_Done,
3346
4.50M
      // Label 182: @6762
3347
4.50M
      GIM_Try, /*On fail goto*//*Label 183*/ 6807, // Rule ID 3945 //
3348
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3349
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3350
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3351
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3352
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3353
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3354
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3355
4.50M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3356
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16,
3357
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3358
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3359
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3360
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3361
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3362
4.50M
        // GIR_Coverage, 3945,
3363
4.50M
        GIR_Done,
3364
4.50M
      // Label 183: @6807
3365
4.50M
      GIM_Try, /*On fail goto*//*Label 184*/ 6864, // Rule ID 947 //
3366
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3367
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3368
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3369
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3370
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3371
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3372
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3373
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3374
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3375
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (MLAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3376
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16,
3377
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3378
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3379
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3380
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3381
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3382
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3383
4.50M
        // GIR_Coverage, 947,
3384
4.50M
        GIR_Done,
3385
4.50M
      // Label 184: @6864
3386
4.50M
      GIM_Try, /*On fail goto*//*Label 185*/ 6909, // Rule ID 1289 //
3387
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3388
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3389
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3390
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3391
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3392
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3393
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3394
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3395
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16,
3396
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3397
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3398
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3399
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3400
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3401
4.50M
        // GIR_Coverage, 1289,
3402
4.50M
        GIR_Done,
3403
4.50M
      // Label 185: @6909
3404
4.50M
      GIM_Try, /*On fail goto*//*Label 186*/ 6954, // Rule ID 1349 //
3405
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3406
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3407
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3408
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3409
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3410
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3411
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3412
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3413
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16,
3414
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3415
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3416
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3417
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3418
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3419
4.50M
        // GIR_Coverage, 1349,
3420
4.50M
        GIR_Done,
3421
4.50M
      // Label 186: @6954
3422
4.50M
      GIM_Try, /*On fail goto*//*Label 187*/ 6973, // Rule ID 771 //
3423
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3424
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3425
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3426
4.50M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3427
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i16,
3428
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3429
4.50M
        // GIR_Coverage, 771,
3430
4.50M
        GIR_Done,
3431
4.50M
      // Label 187: @6973
3432
4.50M
      GIM_Reject,
3433
4.50M
    // Label 162: @6974
3434
4.50M
    GIM_Reject,
3435
4.50M
    // Label 61: @6975
3436
4.50M
    GIM_Try, /*On fail goto*//*Label 188*/ 7379,
3437
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3438
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3439
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
3440
4.50M
      GIM_Try, /*On fail goto*//*Label 189*/ 7053, // Rule ID 3868 //
3441
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3442
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3443
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3444
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3445
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3446
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3447
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3448
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3449
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3450
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3451
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3452
4.50M
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 270:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3453
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
3454
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3455
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3456
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3457
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3458
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3459
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3460
4.50M
        // GIR_Coverage, 3868,
3461
4.50M
        GIR_Done,
3462
4.50M
      // Label 189: @7053
3463
4.50M
      GIM_Try, /*On fail goto*//*Label 190*/ 7117, // Rule ID 3874 //
3464
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3465
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3466
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3467
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3468
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3469
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3470
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3471
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3472
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3473
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3474
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3475
4.50M
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 328:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3476
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
3477
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3478
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3479
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3480
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3481
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3482
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3483
4.50M
        // GIR_Coverage, 3874,
3484
4.50M
        GIR_Done,
3485
4.50M
      // Label 190: @7117
3486
4.50M
      GIM_Try, /*On fail goto*//*Label 191*/ 7181, // Rule ID 965 //
3487
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3488
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3489
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3490
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3491
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3492
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3493
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3494
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3495
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3496
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3497
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3498
4.50M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 270:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3499
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
3500
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3501
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3502
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3503
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3504
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3505
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3506
4.50M
        // GIR_Coverage, 965,
3507
4.50M
        GIR_Done,
3508
4.50M
      // Label 191: @7181
3509
4.50M
      GIM_Try, /*On fail goto*//*Label 192*/ 7245, // Rule ID 1076 //
3510
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3511
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3512
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3513
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3514
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3515
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3516
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3517
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3518
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3519
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3520
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3521
4.50M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 328:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3522
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
3523
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3524
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3525
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3526
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3527
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3528
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3529
4.50M
        // GIR_Coverage, 1076,
3530
4.50M
        GIR_Done,
3531
4.50M
      // Label 192: @7245
3532
4.50M
      GIM_Try, /*On fail goto*//*Label 193*/ 7302, // Rule ID 3862 //
3533
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3534
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3535
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3536
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3537
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3538
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3539
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3540
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3541
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3542
4.50M
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (MLAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3543
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8,
3544
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3545
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3546
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3547
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3548
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3549
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3550
4.50M
        // GIR_Coverage, 3862,
3551
4.50M
        GIR_Done,
3552
4.50M
      // Label 193: @7302
3553
4.50M
      GIM_Try, /*On fail goto*//*Label 194*/ 7359, // Rule ID 945 //
3554
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3555
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3556
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3557
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3558
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3559
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3560
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3561
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3562
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3563
4.50M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (MLAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3564
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8,
3565
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3566
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3567
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3568
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3569
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3570
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3571
4.50M
        // GIR_Coverage, 945,
3572
4.50M
        GIR_Done,
3573
4.50M
      // Label 194: @7359
3574
4.50M
      GIM_Try, /*On fail goto*//*Label 195*/ 7378, // Rule ID 769 //
3575
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3576
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3577
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3578
4.50M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3579
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv16i8,
3580
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3581
4.50M
        // GIR_Coverage, 769,
3582
4.50M
        GIR_Done,
3583
4.50M
      // Label 195: @7378
3584
4.50M
      GIM_Reject,
3585
4.50M
    // Label 188: @7379
3586
4.50M
    GIM_Reject,
3587
4.50M
    // Label 62: @7380
3588
4.50M
    GIM_Reject,
3589
4.50M
    // Label 1: @7381
3590
4.50M
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 205*/ 9961,
3591
4.50M
    /*GILLT_s32*//*Label 196*/ 7397,
3592
4.50M
    /*GILLT_s64*//*Label 197*/ 7517, 0,
3593
4.50M
    /*GILLT_v2s32*//*Label 198*/ 8388,
3594
4.50M
    /*GILLT_v2s64*//*Label 199*/ 8476,
3595
4.50M
    /*GILLT_v4s16*//*Label 200*/ 8845,
3596
4.50M
    /*GILLT_v4s32*//*Label 201*/ 8933,
3597
4.50M
    /*GILLT_v8s8*//*Label 202*/ 9359,
3598
4.50M
    /*GILLT_v8s16*//*Label 203*/ 9447,
3599
4.50M
    /*GILLT_v16s8*//*Label 204*/ 9873,
3600
4.50M
    // Label 196: @7397
3601
4.50M
    GIM_Try, /*On fail goto*//*Label 206*/ 7516,
3602
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3603
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3604
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
3605
4.50M
      GIM_Try, /*On fail goto*//*Label 207*/ 7465, // Rule ID 1879 //
3606
4.50M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3607
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3608
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3609
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3610
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3611
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3612
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
3613
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3614
4.50M
        // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
3615
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
3616
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3617
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3618
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3619
4.50M
        GIR_AddRegister, /*InsnID*/0, AArch64::WZR,
3620
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3621
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3622
4.50M
        // GIR_Coverage, 1879,
3623
4.50M
        GIR_Done,
3624
4.50M
      // Label 207: @7465
3625
4.50M
      GIM_Try, /*On fail goto*//*Label 208*/ 7495, // Rule ID 1845 //
3626
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
3627
4.50M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
3628
4.50M
        // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
3629
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri,
3630
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3631
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3632
4.50M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
3633
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3634
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3635
4.50M
        // GIR_Coverage, 1845,
3636
4.50M
        GIR_Done,
3637
4.50M
      // Label 208: @7495
3638
4.50M
      GIM_Try, /*On fail goto*//*Label 209*/ 7515, // Rule ID 1847 //
3639
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3640
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
3641
4.50M
        // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SUBSWrr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
3642
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSWrr,
3643
4.50M
        GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV,
3644
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3645
4.50M
        // GIR_Coverage, 1847,
3646
4.50M
        GIR_Done,
3647
4.50M
      // Label 209: @7515
3648
4.50M
      GIM_Reject,
3649
4.50M
    // Label 206: @7516
3650
4.50M
    GIM_Reject,
3651
4.50M
    // Label 197: @7517
3652
4.50M
    GIM_Try, /*On fail goto*//*Label 210*/ 8387,
3653
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3654
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3655
4.50M
      GIM_Try, /*On fail goto*//*Label 211*/ 7622, // Rule ID 1890 //
3656
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3657
4.50M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3658
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3659
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3660
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3661
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3662
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3663
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3664
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3665
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3666
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3667
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3668
4.50M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
3669
4.50M
        // MIs[3] Operand 1
3670
4.50M
        // No operand predicates
3671
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3672
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3673
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3674
4.50M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
3675
4.50M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3676
4.50M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3677
4.50M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3678
4.50M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3679
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3680
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3681
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3682
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3683
4.50M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3684
4.50M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3685
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3686
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3687
4.50M
        // GIR_Coverage, 1890,
3688
4.50M
        GIR_Done,
3689
4.50M
      // Label 211: @7622
3690
4.50M
      GIM_Try, /*On fail goto*//*Label 212*/ 7717, // Rule ID 1891 //
3691
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3692
4.50M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3693
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3694
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3695
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3696
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3697
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3698
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3699
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3700
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3701
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3702
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3703
4.50M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
3704
4.50M
        // MIs[3] Operand 1
3705
4.50M
        // No operand predicates
3706
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3707
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3708
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3709
4.50M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
3710
4.50M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3711
4.50M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3712
4.50M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3713
4.50M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3714
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3715
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3716
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3717
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3718
4.50M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3719
4.50M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3720
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3721
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3722
4.50M
        // GIR_Coverage, 1891,
3723
4.50M
        GIR_Done,
3724
4.50M
      // Label 212: @7717
3725
4.50M
      GIM_Try, /*On fail goto*//*Label 213*/ 7801, // Rule ID 1885 //
3726
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3727
4.50M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3728
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3729
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3730
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3731
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3732
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3733
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3734
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3735
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3736
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3737
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
3738
4.50M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3739
4.50M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3740
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3741
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3742
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3743
4.50M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
3744
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3745
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3746
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3747
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3748
4.50M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3749
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3750
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3751
4.50M
        // GIR_Coverage, 1885,
3752
4.50M
        GIR_Done,
3753
4.50M
      // Label 213: @7801
3754
4.50M
      GIM_Try, /*On fail goto*//*Label 214*/ 7885, // Rule ID 1886 //
3755
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3756
4.50M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3757
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3758
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3759
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3760
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3761
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3762
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3763
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3764
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3765
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3766
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
3767
4.50M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3768
4.50M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3769
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3770
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3771
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3772
4.50M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
3773
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3774
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3775
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3776
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3777
4.50M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3778
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3779
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3780
4.50M
        // GIR_Coverage, 1886,
3781
4.50M
        GIR_Done,
3782
4.50M
      // Label 214: @7885
3783
4.50M
      GIM_Try, /*On fail goto*//*Label 215*/ 7981, // Rule ID 1896 //
3784
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3785
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3786
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3787
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3788
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3789
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3790
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3791
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3792
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3793
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3794
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3795
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3796
4.50M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
3797
4.50M
        // MIs[3] Operand 1
3798
4.50M
        // No operand predicates
3799
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3800
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3801
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3802
4.50M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
3803
4.50M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3804
4.50M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3805
4.50M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3806
4.50M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3807
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3808
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3809
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3810
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3811
4.50M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3812
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3813
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3814
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3815
4.50M
        // GIR_Coverage, 1896,
3816
4.50M
        GIR_Done,
3817
4.50M
      // Label 215: @7981
3818
4.50M
      GIM_Try, /*On fail goto*//*Label 216*/ 8077, // Rule ID 1897 //
3819
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3820
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3821
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3822
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3823
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3824
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3825
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3826
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3827
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3828
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3829
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3830
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3831
4.50M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
3832
4.50M
        // MIs[3] Operand 1
3833
4.50M
        // No operand predicates
3834
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3835
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3836
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3837
4.50M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
3838
4.50M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3839
4.50M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3840
4.50M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3841
4.50M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3842
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3843
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3844
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3845
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3846
4.50M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3847
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3848
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3849
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3850
4.50M
        // GIR_Coverage, 1897,
3851
4.50M
        GIR_Done,
3852
4.50M
      // Label 216: @8077
3853
4.50M
      GIM_Try, /*On fail goto*//*Label 217*/ 8162, // Rule ID 66 //
3854
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3855
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3856
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3857
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3858
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3859
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3860
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3861
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3862
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3863
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3864
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3865
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
3866
4.50M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3867
4.50M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3868
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3869
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3870
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3871
4.50M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
3872
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3873
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3874
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3875
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3876
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3877
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3878
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3879
4.50M
        // GIR_Coverage, 66,
3880
4.50M
        GIR_Done,
3881
4.50M
      // Label 217: @8162
3882
4.50M
      GIM_Try, /*On fail goto*//*Label 218*/ 8247, // Rule ID 68 //
3883
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3884
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3885
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3886
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3887
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3888
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3889
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3890
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3891
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3892
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3893
4.50M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3894
4.50M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
3895
4.50M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3896
4.50M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3897
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3898
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3899
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3900
4.50M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
3901
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3902
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3903
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3904
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3905
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3906
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3907
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3908
4.50M
        // GIR_Coverage, 68,
3909
4.50M
        GIR_Done,
3910
4.50M
      // Label 218: @8247
3911
4.50M
      GIM_Try, /*On fail goto*//*Label 219*/ 8305, // Rule ID 1880 //
3912
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3913
4.50M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3914
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3915
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3916
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3917
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3918
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3919
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
3920
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3921
4.50M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
3922
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
3923
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3924
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3925
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3926
4.50M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3927
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3928
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3929
4.50M
        // GIR_Coverage, 1880,
3930
4.50M
        GIR_Done,
3931
4.50M
      // Label 219: @8305
3932
4.50M
      GIM_Try, /*On fail goto*//*Label 220*/ 8339, // Rule ID 1846 //
3933
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3934
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
3935
4.50M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
3936
4.50M
        // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
3937
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri,
3938
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3939
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3940
4.50M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
3941
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3942
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3943
4.50M
        // GIR_Coverage, 1846,
3944
4.50M
        GIR_Done,
3945
4.50M
      // Label 220: @8339
3946
4.50M
      GIM_Try, /*On fail goto*//*Label 221*/ 8362, // Rule ID 1230 //
3947
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3948
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
3949
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3950
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3951
4.50M
        // (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
3952
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv1i64,
3953
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3954
4.50M
        // GIR_Coverage, 1230,
3955
4.50M
        GIR_Done,
3956
4.50M
      // Label 221: @8362
3957
4.50M
      GIM_Try, /*On fail goto*//*Label 222*/ 8386, // Rule ID 1848 //
3958
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3959
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3960
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
3961
4.50M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SUBSXrr:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
3962
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSXrr,
3963
4.50M
        GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV,
3964
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3965
4.50M
        // GIR_Coverage, 1848,
3966
4.50M
        GIR_Done,
3967
4.50M
      // Label 222: @8386
3968
4.50M
      GIM_Reject,
3969
4.50M
    // Label 210: @8387
3970
4.50M
    GIM_Reject,
3971
4.50M
    // Label 198: @8388
3972
4.50M
    GIM_Try, /*On fail goto*//*Label 223*/ 8475,
3973
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
3974
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
3975
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
3976
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3977
4.50M
      GIM_Try, /*On fail goto*//*Label 224*/ 8459, // Rule ID 954 //
3978
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3979
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3980
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3981
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3982
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3983
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3984
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3985
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3986
4.50M
        // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (MLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3987
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv2i32,
3988
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3989
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3990
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3991
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3992
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
3993
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3994
4.50M
        // GIR_Coverage, 954,
3995
4.50M
        GIR_Done,
3996
4.50M
      // Label 224: @8459
3997
4.50M
      GIM_Try, /*On fail goto*//*Label 225*/ 8474, // Rule ID 1072 //
3998
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
3999
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4000
4.50M
        // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4001
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i32,
4002
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4003
4.50M
        // GIR_Coverage, 1072,
4004
4.50M
        GIR_Done,
4005
4.50M
      // Label 225: @8474
4006
4.50M
      GIM_Reject,
4007
4.50M
    // Label 223: @8475
4008
4.50M
    GIM_Reject,
4009
4.50M
    // Label 199: @8476
4010
4.50M
    GIM_Try, /*On fail goto*//*Label 226*/ 8844,
4011
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4012
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4013
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4014
4.50M
      GIM_Try, /*On fail goto*//*Label 227*/ 8554, // Rule ID 1305 //
4015
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4016
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4017
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4018
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4019
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4020
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4021
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4022
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
4023
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4024
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4025
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4026
4.50M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 287:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4027
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv2i32_v2i64,
4028
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4029
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4030
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4031
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4032
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4033
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4034
4.50M
        // GIR_Coverage, 1305,
4035
4.50M
        GIR_Done,
4036
4.50M
      // Label 227: @8554
4037
4.50M
      GIM_Try, /*On fail goto*//*Label 228*/ 8618, // Rule ID 1365 //
4038
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4039
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4040
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4041
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4042
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4043
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4044
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4045
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
4046
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4047
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4048
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4049
4.50M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 341:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4050
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv2i32_v2i64,
4051
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4052
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4053
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4054
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4055
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4056
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4057
4.50M
        // GIR_Coverage, 1365,
4058
4.50M
        GIR_Done,
4059
4.50M
      // Label 228: @8618
4060
4.50M
      GIM_Try, /*On fail goto*//*Label 229*/ 8676, // Rule ID 1329 //
4061
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4062
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4063
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4064
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4065
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4066
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4067
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4068
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4069
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4070
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4071
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4072
4.50M
        // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4073
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv2i32_v2i64,
4074
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4075
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4076
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4077
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4078
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4079
4.50M
        // GIR_Coverage, 1329,
4080
4.50M
        GIR_Done,
4081
4.50M
      // Label 229: @8676
4082
4.50M
      GIM_Try, /*On fail goto*//*Label 230*/ 8734, // Rule ID 1377 //
4083
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4084
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4085
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4086
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4087
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4088
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4089
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4090
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4091
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4092
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4093
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4094
4.50M
        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4095
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64,
4096
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4097
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4098
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4099
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4100
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4101
4.50M
        // GIR_Coverage, 1377,
4102
4.50M
        GIR_Done,
4103
4.50M
      // Label 230: @8734
4104
4.50M
      GIM_Try, /*On fail goto*//*Label 231*/ 8779, // Rule ID 1335 //
4105
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4106
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4107
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4108
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4109
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4110
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4111
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4112
4.50M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4113
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv2i32_v2i64,
4114
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4115
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4116
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4117
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4118
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4119
4.50M
        // GIR_Coverage, 1335,
4120
4.50M
        GIR_Done,
4121
4.50M
      // Label 231: @8779
4122
4.50M
      GIM_Try, /*On fail goto*//*Label 232*/ 8824, // Rule ID 1383 //
4123
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4124
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4125
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4126
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4127
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4128
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4129
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4130
4.50M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4131
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv2i32_v2i64,
4132
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4133
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4134
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4135
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4136
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4137
4.50M
        // GIR_Coverage, 1383,
4138
4.50M
        GIR_Done,
4139
4.50M
      // Label 232: @8824
4140
4.50M
      GIM_Try, /*On fail goto*//*Label 233*/ 8843, // Rule ID 1074 //
4141
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4142
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4143
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4144
4.50M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
4145
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i64,
4146
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4147
4.50M
        // GIR_Coverage, 1074,
4148
4.50M
        GIR_Done,
4149
4.50M
      // Label 233: @8843
4150
4.50M
      GIM_Reject,
4151
4.50M
    // Label 226: @8844
4152
4.50M
    GIM_Reject,
4153
4.50M
    // Label 200: @8845
4154
4.50M
    GIM_Try, /*On fail goto*//*Label 234*/ 8932,
4155
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4156
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4157
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4158
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4159
4.50M
      GIM_Try, /*On fail goto*//*Label 235*/ 8916, // Rule ID 952 //
4160
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4161
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4162
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4163
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4164
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4165
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4166
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4167
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4168
4.50M
        // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (MLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4169
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i16,
4170
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4171
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4172
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4173
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4174
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4175
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4176
4.50M
        // GIR_Coverage, 952,
4177
4.50M
        GIR_Done,
4178
4.50M
      // Label 235: @8916
4179
4.50M
      GIM_Try, /*On fail goto*//*Label 236*/ 8931, // Rule ID 1070 //
4180
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4181
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4182
4.50M
        // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4183
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i16,
4184
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4185
4.50M
        // GIR_Coverage, 1070,
4186
4.50M
        GIR_Done,
4187
4.50M
      // Label 236: @8931
4188
4.50M
      GIM_Reject,
4189
4.50M
    // Label 234: @8932
4190
4.50M
    GIM_Reject,
4191
4.50M
    // Label 201: @8933
4192
4.50M
    GIM_Try, /*On fail goto*//*Label 237*/ 9358,
4193
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4194
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4195
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4196
4.50M
      GIM_Try, /*On fail goto*//*Label 238*/ 9011, // Rule ID 1303 //
4197
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4198
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4199
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4200
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4201
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4202
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4203
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4204
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4205
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4206
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4207
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4208
4.50M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 287:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4209
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv4i16_v4i32,
4210
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4211
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4212
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4213
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4214
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4215
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4216
4.50M
        // GIR_Coverage, 1303,
4217
4.50M
        GIR_Done,
4218
4.50M
      // Label 238: @9011
4219
4.50M
      GIM_Try, /*On fail goto*//*Label 239*/ 9075, // Rule ID 1363 //
4220
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4221
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4222
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4223
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4224
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4225
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4226
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4227
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4228
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4229
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4230
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4231
4.50M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 341:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4232
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv4i16_v4i32,
4233
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4234
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4235
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4236
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4237
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4238
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4239
4.50M
        // GIR_Coverage, 1363,
4240
4.50M
        GIR_Done,
4241
4.50M
      // Label 239: @9075
4242
4.50M
      GIM_Try, /*On fail goto*//*Label 240*/ 9133, // Rule ID 1327 //
4243
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4244
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4245
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4246
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4247
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4248
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4249
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4250
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4251
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4252
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4253
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4254
4.50M
        // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4255
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv4i16_v4i32,
4256
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4257
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4258
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4259
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4260
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4261
4.50M
        // GIR_Coverage, 1327,
4262
4.50M
        GIR_Done,
4263
4.50M
      // Label 240: @9133
4264
4.50M
      GIM_Try, /*On fail goto*//*Label 241*/ 9191, // Rule ID 1375 //
4265
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4266
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4267
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4268
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4269
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4270
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4271
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4272
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4273
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4274
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4275
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4276
4.50M
        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4277
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32,
4278
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4279
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4280
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4281
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4282
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4283
4.50M
        // GIR_Coverage, 1375,
4284
4.50M
        GIR_Done,
4285
4.50M
      // Label 241: @9191
4286
4.50M
      GIM_Try, /*On fail goto*//*Label 242*/ 9248, // Rule ID 955 //
4287
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4288
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4289
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4290
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4291
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4292
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4293
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4294
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4295
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4296
4.50M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (MLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4297
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i32,
4298
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4299
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4300
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4301
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4302
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4303
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4304
4.50M
        // GIR_Coverage, 955,
4305
4.50M
        GIR_Done,
4306
4.50M
      // Label 242: @9248
4307
4.50M
      GIM_Try, /*On fail goto*//*Label 243*/ 9293, // Rule ID 1333 //
4308
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4309
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4310
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4311
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4312
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4313
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4314
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4315
4.50M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4316
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv4i16_v4i32,
4317
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4318
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4319
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4320
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4321
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4322
4.50M
        // GIR_Coverage, 1333,
4323
4.50M
        GIR_Done,
4324
4.50M
      // Label 243: @9293
4325
4.50M
      GIM_Try, /*On fail goto*//*Label 244*/ 9338, // Rule ID 1381 //
4326
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4327
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4328
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4329
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4330
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4331
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4332
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4333
4.50M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4334
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv4i16_v4i32,
4335
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4336
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4337
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4338
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4339
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4340
4.50M
        // GIR_Coverage, 1381,
4341
4.50M
        GIR_Done,
4342
4.50M
      // Label 244: @9338
4343
4.50M
      GIM_Try, /*On fail goto*//*Label 245*/ 9357, // Rule ID 1073 //
4344
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4345
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4346
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4347
4.50M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4348
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i32,
4349
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4350
4.50M
        // GIR_Coverage, 1073,
4351
4.50M
        GIR_Done,
4352
4.50M
      // Label 245: @9357
4353
4.50M
      GIM_Reject,
4354
4.50M
    // Label 237: @9358
4355
4.50M
    GIM_Reject,
4356
4.50M
    // Label 202: @9359
4357
4.50M
    GIM_Try, /*On fail goto*//*Label 246*/ 9446,
4358
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4359
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4360
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4361
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4362
4.50M
      GIM_Try, /*On fail goto*//*Label 247*/ 9430, // Rule ID 950 //
4363
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4364
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4365
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4366
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4367
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4368
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4369
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4370
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4371
4.50M
        // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (MLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4372
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i8,
4373
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4374
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4375
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4376
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4377
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4378
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4379
4.50M
        // GIR_Coverage, 950,
4380
4.50M
        GIR_Done,
4381
4.50M
      // Label 247: @9430
4382
4.50M
      GIM_Try, /*On fail goto*//*Label 248*/ 9445, // Rule ID 1068 //
4383
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4384
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4385
4.50M
        // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4386
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i8,
4387
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4388
4.50M
        // GIR_Coverage, 1068,
4389
4.50M
        GIR_Done,
4390
4.50M
      // Label 248: @9445
4391
4.50M
      GIM_Reject,
4392
4.50M
    // Label 246: @9446
4393
4.50M
    GIM_Reject,
4394
4.50M
    // Label 203: @9447
4395
4.50M
    GIM_Try, /*On fail goto*//*Label 249*/ 9872,
4396
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4397
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4398
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4399
4.50M
      GIM_Try, /*On fail goto*//*Label 250*/ 9525, // Rule ID 1301 //
4400
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4401
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4402
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4403
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4404
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4405
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4406
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4407
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
4408
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4409
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4410
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4411
4.50M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 287:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4412
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv8i8_v8i16,
4413
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4414
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4415
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4416
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4417
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4418
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4419
4.50M
        // GIR_Coverage, 1301,
4420
4.50M
        GIR_Done,
4421
4.50M
      // Label 250: @9525
4422
4.50M
      GIM_Try, /*On fail goto*//*Label 251*/ 9589, // Rule ID 1361 //
4423
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4424
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4425
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4426
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4427
4.50M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4428
4.50M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4429
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4430
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
4431
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4432
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4433
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4434
4.50M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 341:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4435
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv8i8_v8i16,
4436
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4437
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4438
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4439
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4440
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4441
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4442
4.50M
        // GIR_Coverage, 1361,
4443
4.50M
        GIR_Done,
4444
4.50M
      // Label 251: @9589
4445
4.50M
      GIM_Try, /*On fail goto*//*Label 252*/ 9647, // Rule ID 1325 //
4446
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4447
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4448
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4449
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4450
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4451
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4452
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4453
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4454
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4455
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4456
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4457
4.50M
        // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4458
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv8i8_v8i16,
4459
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4460
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4461
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4462
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4463
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4464
4.50M
        // GIR_Coverage, 1325,
4465
4.50M
        GIR_Done,
4466
4.50M
      // Label 252: @9647
4467
4.50M
      GIM_Try, /*On fail goto*//*Label 253*/ 9705, // Rule ID 1373 //
4468
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4469
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4470
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4471
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4472
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4473
4.50M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4474
4.50M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4475
4.50M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4476
4.50M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4477
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4478
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4479
4.50M
        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4480
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16,
4481
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4482
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4483
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4484
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4485
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4486
4.50M
        // GIR_Coverage, 1373,
4487
4.50M
        GIR_Done,
4488
4.50M
      // Label 253: @9705
4489
4.50M
      GIM_Try, /*On fail goto*//*Label 254*/ 9762, // Rule ID 953 //
4490
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4491
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4492
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4493
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4494
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4495
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4496
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4497
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4498
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4499
4.50M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (MLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
4500
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i16,
4501
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4502
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4503
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4504
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4505
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4506
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4507
4.50M
        // GIR_Coverage, 953,
4508
4.50M
        GIR_Done,
4509
4.50M
      // Label 254: @9762
4510
4.50M
      GIM_Try, /*On fail goto*//*Label 255*/ 9807, // Rule ID 1331 //
4511
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4512
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4513
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4514
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4515
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4516
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4517
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4518
4.50M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4519
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv8i8_v8i16,
4520
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4521
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4522
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4523
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4524
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4525
4.50M
        // GIR_Coverage, 1331,
4526
4.50M
        GIR_Done,
4527
4.50M
      // Label 255: @9807
4528
4.50M
      GIM_Try, /*On fail goto*//*Label 256*/ 9852, // Rule ID 1379 //
4529
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4530
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4531
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4532
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4533
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4534
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4535
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4536
4.50M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4537
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv8i8_v8i16,
4538
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4539
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4540
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4541
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4542
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4543
4.50M
        // GIR_Coverage, 1379,
4544
4.50M
        GIR_Done,
4545
4.50M
      // Label 256: @9852
4546
4.50M
      GIM_Try, /*On fail goto*//*Label 257*/ 9871, // Rule ID 1071 //
4547
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4548
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4549
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4550
4.50M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
4551
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i16,
4552
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4553
4.50M
        // GIR_Coverage, 1071,
4554
4.50M
        GIR_Done,
4555
4.50M
      // Label 257: @9871
4556
4.50M
      GIM_Reject,
4557
4.50M
    // Label 249: @9872
4558
4.50M
    GIM_Reject,
4559
4.50M
    // Label 204: @9873
4560
4.50M
    GIM_Try, /*On fail goto*//*Label 258*/ 9960,
4561
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4562
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
4563
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4564
4.50M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4565
4.50M
      GIM_Try, /*On fail goto*//*Label 259*/ 9944, // Rule ID 951 //
4566
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4567
4.50M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4568
4.50M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4569
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
4570
4.50M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
4571
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4572
4.50M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4573
4.50M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4574
4.50M
        // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (MLSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
4575
4.50M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv16i8,
4576
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4577
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4578
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4579
4.50M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4580
4.50M
        GIR_EraseFromParent, /*InsnID*/0,
4581
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4582
4.50M
        // GIR_Coverage, 951,
4583
4.50M
        GIR_Done,
4584
4.50M
      // Label 259: @9944
4585
4.50M
      GIM_Try, /*On fail goto*//*Label 260*/ 9959, // Rule ID 1069 //
4586
4.50M
        GIM_CheckFeatures, GIFBS_HasNEON,
4587
4.50M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4588
4.50M
        // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
4589
4.50M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv16i8,
4590
4.50M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4591
4.50M
        // GIR_Coverage, 1069,
4592
4.50M
        GIR_Done,
4593
4.50M
      // Label 260: @9959
4594
4.50M
      GIM_Reject,
4595
4.50M
    // Label 258: @9960
4596
4.50M
    GIM_Reject,
4597
4.50M
    // Label 205: @9961
4598
4.50M
    GIM_Reject,
4599
4.50M
    // Label 2: @9962
4600
4.50M
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 269*/ 10742,
4601
4.50M
    /*GILLT_s32*//*Label 261*/ 9978,
4602
4.50M
    /*GILLT_s64*//*Label 262*/ 10135, 0,
4603
4.50M
    /*GILLT_v2s32*//*Label 263*/ 10550, 0,
4604
4.50M
    /*GILLT_v4s16*//*Label 264*/ 10582,
4605
4.50M
    /*GILLT_v4s32*//*Label 265*/ 10614,
4606
4.50M
    /*GILLT_v8s8*//*Label 266*/ 10646,
4607
4.50M
    /*GILLT_v8s16*//*Label 267*/ 10678,
4608
4.50M
    /*GILLT_v16s8*//*Label 268*/ 10710,
4609
4.50M
    // Label 261: @9978
4610
4.50M
    GIM_Try, /*On fail goto*//*Label 270*/ 10134,
4611
4.50M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4612
4.50M
      GIM_Chec