Coverage Report

Created: 2019-03-24 22:13

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AArch64/AArch64GenGlobalISel.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the AArch64 target                         *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 19;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
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14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static AArch64InstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
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28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(1),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
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33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_HasFPARMv8Bit = 5,
37
  Feature_HasNEONBit = 2,
38
  Feature_HasSHA2Bit = 8,
39
  Feature_HasAESBit = 7,
40
  Feature_HasDotProdBit = 0,
41
  Feature_HasCRCBit = 3,
42
  Feature_HasLSEBit = 9,
43
  Feature_HasRDMBit = 6,
44
  Feature_HasPerfMonBit = 10,
45
  Feature_HasFullFP16Bit = 4,
46
  Feature_HasFP16FMLBit = 1,
47
  Feature_HasFuseAESBit = 15,
48
  Feature_IsLEBit = 11,
49
  Feature_IsBEBit = 16,
50
  Feature_UseAlternateSExtLoadCVTF32Bit = 14,
51
  Feature_NotForCodeSizeBit = 13,
52
  Feature_UseSTRQroBit = 12,
53
  Feature_UseBTIBit = 18,
54
  Feature_NotUseBTIBit = 17,
55
};
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57
PredicateBitset AArch64InstructionSelector::
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computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const {
59
8.90k
  PredicateBitset Features;
60
8.90k
  if (Subtarget->hasFPARMv8())
61
8.89k
    Features[Feature_HasFPARMv8Bit] = 1;
62
8.90k
  if (Subtarget->hasNEON())
63
8.88k
    Features[Feature_HasNEONBit] = 1;
64
8.90k
  if (Subtarget->hasSHA2())
65
8.90k
    Features[Feature_HasSHA2Bit] = 1;
66
8.90k
  if (Subtarget->hasAES())
67
8.90k
    Features[Feature_HasAESBit] = 1;
68
8.90k
  if (Subtarget->hasDotProd())
69
25
    Features[Feature_HasDotProdBit] = 1;
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8.90k
  if (Subtarget->hasCRC())
71
182
    Features[Feature_HasCRCBit] = 1;
72
8.90k
  if (Subtarget->hasLSE())
73
51
    Features[Feature_HasLSEBit] = 1;
74
8.90k
  if (Subtarget->hasRDM())
75
55
    Features[Feature_HasRDMBit] = 1;
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8.90k
  if (Subtarget->hasPerfMon())
77
8.89k
    Features[Feature_HasPerfMonBit] = 1;
78
8.90k
  if (Subtarget->hasFullFP16())
79
51
    Features[Feature_HasFullFP16Bit] = 1;
80
8.90k
  if (Subtarget->hasFP16FML())
81
3
    Features[Feature_HasFP16FMLBit] = 1;
82
8.90k
  if (Subtarget->hasFuseAES())
83
8.86k
    Features[Feature_HasFuseAESBit] = 1;
84
8.90k
  if (Subtarget->isLittleEndian())
85
8.87k
    Features[Feature_IsLEBit] = 1;
86
8.90k
  if (!Subtarget->isLittleEndian())
87
30
    Features[Feature_IsBEBit] = 1;
88
8.90k
  if (Subtarget->useAlternateSExtLoadCVTF32Pattern())
89
7.15k
    Features[Feature_UseAlternateSExtLoadCVTF32Bit] = 1;
90
8.90k
  return Features;
91
8.90k
}
92
93
PredicateBitset AArch64InstructionSelector::
94
7.52M
computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const {
95
7.52M
  PredicateBitset Features;
96
7.52M
  if (!MF->getFunction().optForSize())
97
7.52M
    Features[Feature_NotForCodeSizeBit] = 1;
98
7.52M
  if (!Subtarget->isSTRQroSlow() || 
MF->getFunction().optForSize()0
)
99
7.52M
    Features[Feature_UseSTRQroBit] = 1;
100
7.52M
  if ( MF->getFunction().hasFnAttribute("branch-target-enforcement") )
101
0
    Features[Feature_UseBTIBit] = 1;
102
7.52M
  if ( !MF->getFunction().hasFnAttribute("branch-target-enforcement") )
103
7.52M
    Features[Feature_NotUseBTIBit] = 1;
104
7.52M
  return Features;
105
7.52M
}
106
107
// LLT Objects.
108
enum {
109
  GILLT_s16,
110
  GILLT_s32,
111
  GILLT_s64,
112
  GILLT_s128,
113
  GILLT_v2s32,
114
  GILLT_v2s64,
115
  GILLT_v4s16,
116
  GILLT_v4s32,
117
  GILLT_v8s8,
118
  GILLT_v8s16,
119
  GILLT_v16s8,
120
};
121
const static size_t NumTypeObjects = 11;
122
const static LLT TypeObjects[] = {
123
  LLT::scalar(16),
124
  LLT::scalar(32),
125
  LLT::scalar(64),
126
  LLT::scalar(128),
127
  LLT::vector(2, 32),
128
  LLT::vector(2, 64),
129
  LLT::vector(4, 16),
130
  LLT::vector(4, 32),
131
  LLT::vector(8, 8),
132
  LLT::vector(8, 16),
133
  LLT::vector(16, 8),
134
};
135
136
// Feature bitsets.
137
enum {
138
  GIFBS_Invalid,
139
  GIFBS_HasAES,
140
  GIFBS_HasCRC,
141
  GIFBS_HasDotProd,
142
  GIFBS_HasFPARMv8,
143
  GIFBS_HasFullFP16,
144
  GIFBS_HasFuseAES,
145
  GIFBS_HasLSE,
146
  GIFBS_HasNEON,
147
  GIFBS_HasRDM,
148
  GIFBS_HasSHA2,
149
  GIFBS_IsBE,
150
  GIFBS_IsLE,
151
  GIFBS_HasFP16FML_HasNEON,
152
  GIFBS_HasFullFP16_HasNEON,
153
  GIFBS_HasNEON_HasRDM,
154
};
155
const static PredicateBitset FeatureBitsets[] {
156
  {}, // GIFBS_Invalid
157
  {Feature_HasAESBit, },
158
  {Feature_HasCRCBit, },
159
  {Feature_HasDotProdBit, },
160
  {Feature_HasFPARMv8Bit, },
161
  {Feature_HasFullFP16Bit, },
162
  {Feature_HasFuseAESBit, },
163
  {Feature_HasLSEBit, },
164
  {Feature_HasNEONBit, },
165
  {Feature_HasRDMBit, },
166
  {Feature_HasSHA2Bit, },
167
  {Feature_IsBEBit, },
168
  {Feature_IsLEBit, },
169
  {Feature_HasFP16FMLBit, Feature_HasNEONBit, },
170
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
171
  {Feature_HasNEONBit, Feature_HasRDMBit, },
172
};
173
174
// ComplexPattern predicates.
175
enum {
176
  GICP_Invalid,
177
  GICP_gi_addsub_shifted_imm32,
178
  GICP_gi_addsub_shifted_imm64,
179
  GICP_gi_am_indexed128,
180
  GICP_gi_am_indexed16,
181
  GICP_gi_am_indexed32,
182
  GICP_gi_am_indexed64,
183
  GICP_gi_am_indexed8,
184
  GICP_gi_am_unscaled128,
185
  GICP_gi_am_unscaled16,
186
  GICP_gi_am_unscaled32,
187
  GICP_gi_am_unscaled64,
188
  GICP_gi_am_unscaled8,
189
};
190
// See constructor for table contents
191
192
// PatFrag predicates.
193
enum {
194
  GIPFP_I64_Predicate_VectorIndex1 = GIPFP_I64_Invalid + 1,
195
  GIPFP_I64_Predicate_VectorIndexB,
196
  GIPFP_I64_Predicate_VectorIndexD,
197
  GIPFP_I64_Predicate_VectorIndexH,
198
  GIPFP_I64_Predicate_VectorIndexS,
199
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16,
200
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32,
201
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64,
202
  GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8,
203
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16,
204
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32,
205
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64,
206
  GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8,
207
  GIPFP_I64_Predicate_i64imm_32bit,
208
  GIPFP_I64_Predicate_imm0_1,
209
  GIPFP_I64_Predicate_imm0_127,
210
  GIPFP_I64_Predicate_imm0_15,
211
  GIPFP_I64_Predicate_imm0_255,
212
  GIPFP_I64_Predicate_imm0_31,
213
  GIPFP_I64_Predicate_imm0_63,
214
  GIPFP_I64_Predicate_imm0_65535,
215
  GIPFP_I64_Predicate_imm0_7,
216
  GIPFP_I64_Predicate_imm32_0_15,
217
  GIPFP_I64_Predicate_imm32_0_31,
218
  GIPFP_I64_Predicate_maski16_or_more,
219
  GIPFP_I64_Predicate_maski8_or_more,
220
  GIPFP_I64_Predicate_s64imm_32bit,
221
  GIPFP_I64_Predicate_simm4s1,
222
  GIPFP_I64_Predicate_simm4s16,
223
  GIPFP_I64_Predicate_simm4s2,
224
  GIPFP_I64_Predicate_simm4s3,
225
  GIPFP_I64_Predicate_simm4s4,
226
  GIPFP_I64_Predicate_simm5_32b,
227
  GIPFP_I64_Predicate_simm5_64b,
228
  GIPFP_I64_Predicate_simm6_32b,
229
  GIPFP_I64_Predicate_simm6s1,
230
  GIPFP_I64_Predicate_simm8,
231
  GIPFP_I64_Predicate_simm9,
232
  GIPFP_I64_Predicate_sve_elm_idx_extdup_b,
233
  GIPFP_I64_Predicate_sve_elm_idx_extdup_d,
234
  GIPFP_I64_Predicate_sve_elm_idx_extdup_h,
235
  GIPFP_I64_Predicate_sve_elm_idx_extdup_q,
236
  GIPFP_I64_Predicate_sve_elm_idx_extdup_s,
237
  GIPFP_I64_Predicate_sve_incdec_imm,
238
  GIPFP_I64_Predicate_sve_pred_enum,
239
  GIPFP_I64_Predicate_sve_prfop,
240
  GIPFP_I64_Predicate_tbz_imm0_31_diag,
241
  GIPFP_I64_Predicate_tbz_imm0_31_nodiag,
242
  GIPFP_I64_Predicate_tbz_imm32_63,
243
  GIPFP_I64_Predicate_uimm16,
244
  GIPFP_I64_Predicate_uimm5s2,
245
  GIPFP_I64_Predicate_uimm5s4,
246
  GIPFP_I64_Predicate_uimm5s8,
247
  GIPFP_I64_Predicate_uimm6,
248
  GIPFP_I64_Predicate_uimm6s1,
249
  GIPFP_I64_Predicate_uimm6s16,
250
  GIPFP_I64_Predicate_uimm6s2,
251
  GIPFP_I64_Predicate_uimm6s4,
252
  GIPFP_I64_Predicate_uimm6s8,
253
  GIPFP_I64_Predicate_vecshiftL16,
254
  GIPFP_I64_Predicate_vecshiftL32,
255
  GIPFP_I64_Predicate_vecshiftL64,
256
  GIPFP_I64_Predicate_vecshiftL8,
257
  GIPFP_I64_Predicate_vecshiftR16,
258
  GIPFP_I64_Predicate_vecshiftR16Narrow,
259
  GIPFP_I64_Predicate_vecshiftR32,
260
  GIPFP_I64_Predicate_vecshiftR32Narrow,
261
  GIPFP_I64_Predicate_vecshiftR64,
262
  GIPFP_I64_Predicate_vecshiftR64Narrow,
263
  GIPFP_I64_Predicate_vecshiftR8,
264
};
265
43.3k
bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
266
43.3k
  switch (PredicateID) {
267
43.3k
  case GIPFP_I64_Predicate_VectorIndex1: {
268
0
     return ((uint64_t)Imm) == 1; 
269
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
270
43.3k
    
return false0
;
271
43.3k
  }
272
43.3k
  case GIPFP_I64_Predicate_VectorIndexB: {
273
0
     return ((uint64_t)Imm) < 16; 
274
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
275
43.3k
    
return false0
;
276
43.3k
  }
277
43.3k
  case GIPFP_I64_Predicate_VectorIndexD: {
278
1.17k
     return ((uint64_t)Imm) < 2; 
279
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
280
43.3k
    
return false0
;
281
43.3k
  }
282
43.3k
  case GIPFP_I64_Predicate_VectorIndexH: {
283
0
     return ((uint64_t)Imm) < 8; 
284
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
285
43.3k
    
return false0
;
286
43.3k
  }
287
43.3k
  case GIPFP_I64_Predicate_VectorIndexS: {
288
238
     return ((uint64_t)Imm) < 4; 
289
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
290
43.3k
    
return false0
;
291
43.3k
  }
292
43.3k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16: {
293
0
    
294
0
  return AArch64_AM::isSVEAddSubImm<int16_t>(Imm);
295
43.3k
296
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
297
43.3k
    
return false0
;
298
43.3k
  }
299
43.3k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32: {
300
0
    
301
0
  return AArch64_AM::isSVEAddSubImm<int32_t>(Imm);
302
43.3k
303
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
304
43.3k
    
return false0
;
305
43.3k
  }
306
43.3k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64: {
307
0
    
308
0
  return AArch64_AM::isSVEAddSubImm<int64_t>(Imm);
309
43.3k
310
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
311
43.3k
    
return false0
;
312
43.3k
  }
313
43.3k
  case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8: {
314
0
    
315
0
  return AArch64_AM::isSVEAddSubImm<int8_t>(Imm);
316
43.3k
317
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
318
43.3k
    
return false0
;
319
43.3k
  }
320
43.3k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16: {
321
0
    
322
0
  return AArch64_AM::isSVECpyImm<int16_t>(Imm);
323
43.3k
324
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
325
43.3k
    
return false0
;
326
43.3k
  }
327
43.3k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32: {
328
0
    
329
0
  return AArch64_AM::isSVECpyImm<int32_t>(Imm);
330
43.3k
331
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
332
43.3k
    
return false0
;
333
43.3k
  }
334
43.3k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64: {
335
0
    
336
0
  return AArch64_AM::isSVECpyImm<int64_t>(Imm);
337
43.3k
338
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
339
43.3k
    
return false0
;
340
43.3k
  }
341
43.3k
  case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8: {
342
0
    
343
0
  return AArch64_AM::isSVECpyImm<int8_t>(Imm);
344
43.3k
345
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
346
43.3k
    
return false0
;
347
43.3k
  }
348
43.3k
  case GIPFP_I64_Predicate_i64imm_32bit: {
349
195
    
350
195
  return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
351
43.3k
352
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
353
43.3k
    
return false0
;
354
43.3k
  }
355
43.3k
  case GIPFP_I64_Predicate_imm0_1: {
356
0
    
357
0
  return ((uint64_t)Imm) < 2;
358
43.3k
359
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
360
43.3k
    
return false0
;
361
43.3k
  }
362
43.3k
  case GIPFP_I64_Predicate_imm0_127: {
363
1
    
364
1
  return ((uint32_t)Imm) < 128;
365
43.3k
366
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
367
43.3k
    
return false0
;
368
43.3k
  }
369
43.3k
  case GIPFP_I64_Predicate_imm0_15: {
370
0
    
371
0
  return ((uint64_t)Imm) < 16;
372
43.3k
373
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
374
43.3k
    
return false0
;
375
43.3k
  }
376
43.3k
  case GIPFP_I64_Predicate_imm0_255: {
377
0
    
378
0
  return ((uint32_t)Imm) < 256;
379
43.3k
380
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
381
43.3k
    
return false0
;
382
43.3k
  }
383
43.3k
  case GIPFP_I64_Predicate_imm0_31: {
384
0
    
385
0
  return ((uint64_t)Imm) < 32;
386
43.3k
387
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
388
43.3k
    
return false0
;
389
43.3k
  }
390
43.3k
  case GIPFP_I64_Predicate_imm0_63: {
391
36.6k
    
392
36.6k
  return ((uint64_t)Imm) < 64;
393
43.3k
394
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
395
43.3k
    
return false0
;
396
43.3k
  }
397
43.3k
  case GIPFP_I64_Predicate_imm0_65535: {
398
0
    
399
0
  return ((uint32_t)Imm) < 65536;
400
43.3k
401
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
402
43.3k
    
return false0
;
403
43.3k
  }
404
43.3k
  case GIPFP_I64_Predicate_imm0_7: {
405
0
    
406
0
  return ((uint64_t)Imm) < 8;
407
43.3k
408
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
409
43.3k
    
return false0
;
410
43.3k
  }
411
43.3k
  case GIPFP_I64_Predicate_imm32_0_15: {
412
0
    
413
0
  return ((uint32_t)Imm) < 16;
414
43.3k
415
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
416
43.3k
    
return false0
;
417
43.3k
  }
418
43.3k
  case GIPFP_I64_Predicate_imm32_0_31: {
419
0
    
420
0
  return ((uint64_t)Imm) < 32;
421
43.3k
422
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
423
43.3k
    
return false0
;
424
43.3k
  }
425
43.3k
  case GIPFP_I64_Predicate_maski16_or_more: {
426
0
     return (Imm & 0xffff) == 0xffff; 
427
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
428
43.3k
    
return false0
;
429
43.3k
  }
430
43.3k
  case GIPFP_I64_Predicate_maski8_or_more: {
431
0
     return (Imm & 0xff) == 0xff; 
432
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
433
43.3k
    
return false0
;
434
43.3k
  }
435
43.3k
  case GIPFP_I64_Predicate_s64imm_32bit: {
436
5.09k
    
437
5.09k
  int64_t Imm64 = static_cast<int64_t>(Imm);
438
5.09k
  return Imm64 >= std::numeric_limits<int32_t>::min() &&
439
5.09k
         
Imm64 <= std::numeric_limits<int32_t>::max()5.09k
;
440
43.3k
441
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
442
43.3k
    
return false0
;
443
43.3k
  }
444
43.3k
  case GIPFP_I64_Predicate_simm4s1: {
445
0
     return Imm >=-8  && Imm <= 7; 
446
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
447
43.3k
    
return false0
;
448
43.3k
  }
449
43.3k
  case GIPFP_I64_Predicate_simm4s16: {
450
0
     return Imm >=-128  && Imm <= 112 && (Imm % 16) == 0x0; 
451
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
452
43.3k
    
return false0
;
453
43.3k
  }
454
43.3k
  case GIPFP_I64_Predicate_simm4s2: {
455
0
     return Imm >=-16  && Imm <= 14 && (Imm % 2) == 0x0; 
456
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
457
43.3k
    
return false0
;
458
43.3k
  }
459
43.3k
  case GIPFP_I64_Predicate_simm4s3: {
460
0
     return Imm >=-24  && Imm <= 21 && (Imm % 3) == 0x0; 
461
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
462
43.3k
    
return false0
;
463
43.3k
  }
464
43.3k
  case GIPFP_I64_Predicate_simm4s4: {
465
0
     return Imm >=-32  && Imm <= 28 && (Imm % 4) == 0x0; 
466
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
467
43.3k
    
return false0
;
468
43.3k
  }
469
43.3k
  case GIPFP_I64_Predicate_simm5_32b: {
470
0
     return Imm >= -16 && Imm < 16; 
471
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
472
43.3k
    
return false0
;
473
43.3k
  }
474
43.3k
  case GIPFP_I64_Predicate_simm5_64b: {
475
0
     return Imm >= -16 && Imm < 16; 
476
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
477
43.3k
    
return false0
;
478
43.3k
  }
479
43.3k
  case GIPFP_I64_Predicate_simm6_32b: {
480
0
     return Imm >= -32 && Imm < 32; 
481
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
482
43.3k
    
return false0
;
483
43.3k
  }
484
43.3k
  case GIPFP_I64_Predicate_simm6s1: {
485
0
     return Imm >= -32 && Imm < 32; 
486
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
487
43.3k
    
return false0
;
488
43.3k
  }
489
43.3k
  case GIPFP_I64_Predicate_simm8: {
490
0
     return Imm >= -128 && Imm < 127; 
491
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
492
43.3k
    
return false0
;
493
43.3k
  }
494
43.3k
  case GIPFP_I64_Predicate_simm9: {
495
0
     return Imm >= -256 && Imm < 256; 
496
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
497
43.3k
    
return false0
;
498
43.3k
  }
499
43.3k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_b: {
500
0
     return ((uint64_t)Imm) < 64; 
501
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
502
43.3k
    
return false0
;
503
43.3k
  }
504
43.3k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_d: {
505
0
     return ((uint64_t)Imm) < 8; 
506
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
507
43.3k
    
return false0
;
508
43.3k
  }
509
43.3k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_h: {
510
0
     return ((uint64_t)Imm) < 32; 
511
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
512
43.3k
    
return false0
;
513
43.3k
  }
514
43.3k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_q: {
515
0
     return ((uint64_t)Imm) < 4; 
516
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
517
43.3k
    
return false0
;
518
43.3k
  }
519
43.3k
  case GIPFP_I64_Predicate_sve_elm_idx_extdup_s: {
520
0
     return ((uint64_t)Imm) < 16; 
521
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
522
43.3k
    
return false0
;
523
43.3k
  }
524
43.3k
  case GIPFP_I64_Predicate_sve_incdec_imm: {
525
0
    
526
0
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
527
43.3k
528
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
529
43.3k
    
return false0
;
530
43.3k
  }
531
43.3k
  case GIPFP_I64_Predicate_sve_pred_enum: {
532
0
    
533
0
  return (((uint32_t)Imm) < 32);
534
43.3k
  
535
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
536
43.3k
    
return false0
;
537
43.3k
  }
538
43.3k
  case GIPFP_I64_Predicate_sve_prfop: {
539
0
    
540
0
    return (((uint32_t)Imm) <= 15);
541
43.3k
  
542
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
543
43.3k
    
return false0
;
544
43.3k
  }
545
43.3k
  case GIPFP_I64_Predicate_tbz_imm0_31_diag: {
546
0
    
547
0
  return (((uint32_t)Imm) < 32);
548
43.3k
549
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
550
43.3k
    
return false0
;
551
43.3k
  }
552
43.3k
  case GIPFP_I64_Predicate_tbz_imm0_31_nodiag: {
553
0
    
554
0
  return (((uint32_t)Imm) < 32);
555
43.3k
556
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
557
43.3k
    
return false0
;
558
43.3k
  }
559
43.3k
  case GIPFP_I64_Predicate_tbz_imm32_63: {
560
0
    
561
0
  return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
562
43.3k
563
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
564
43.3k
    
return false0
;
565
43.3k
  }
566
43.3k
  case GIPFP_I64_Predicate_uimm16: {
567
0
    return Imm >= 0 && Imm < 65536;
568
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
569
43.3k
    
return false0
;
570
43.3k
  }
571
43.3k
  case GIPFP_I64_Predicate_uimm5s2: {
572
0
     return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); 
573
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
574
43.3k
    
return false0
;
575
43.3k
  }
576
43.3k
  case GIPFP_I64_Predicate_uimm5s4: {
577
0
     return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); 
578
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
579
43.3k
    
return false0
;
580
43.3k
  }
581
43.3k
  case GIPFP_I64_Predicate_uimm5s8: {
582
0
     return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); 
583
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
584
43.3k
    
return false0
;
585
43.3k
  }
586
43.3k
  case GIPFP_I64_Predicate_uimm6: {
587
0
     return Imm >= 0 && Imm < 64; 
588
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
589
43.3k
    
return false0
;
590
43.3k
  }
591
43.3k
  case GIPFP_I64_Predicate_uimm6s1: {
592
0
     return Imm >= 0 && Imm < 64; 
593
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
594
43.3k
    
return false0
;
595
43.3k
  }
596
43.3k
  case GIPFP_I64_Predicate_uimm6s16: {
597
0
     return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0); 
598
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
599
43.3k
    
return false0
;
600
43.3k
  }
601
43.3k
  case GIPFP_I64_Predicate_uimm6s2: {
602
0
     return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); 
603
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
604
43.3k
    
return false0
;
605
43.3k
  }
606
43.3k
  case GIPFP_I64_Predicate_uimm6s4: {
607
0
     return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); 
608
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
609
43.3k
    
return false0
;
610
43.3k
  }
611
43.3k
  case GIPFP_I64_Predicate_uimm6s8: {
612
0
     return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); 
613
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
614
43.3k
    
return false0
;
615
43.3k
  }
616
43.3k
  case GIPFP_I64_Predicate_vecshiftL16: {
617
6
    
618
6
  return (((uint32_t)Imm) < 16);
619
43.3k
620
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
621
43.3k
    
return false0
;
622
43.3k
  }
623
43.3k
  case GIPFP_I64_Predicate_vecshiftL32: {
624
4
    
625
4
  return (((uint32_t)Imm) < 32);
626
43.3k
627
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
628
43.3k
    
return false0
;
629
43.3k
  }
630
43.3k
  case GIPFP_I64_Predicate_vecshiftL64: {
631
2
    
632
2
  return (((uint32_t)Imm) < 64);
633
43.3k
634
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
635
43.3k
    
return false0
;
636
43.3k
  }
637
43.3k
  case GIPFP_I64_Predicate_vecshiftL8: {
638
0
    
639
0
  return (((uint32_t)Imm) < 8);
640
43.3k
641
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
642
43.3k
    
return false0
;
643
43.3k
  }
644
43.3k
  case GIPFP_I64_Predicate_vecshiftR16: {
645
6
    
646
6
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
647
43.3k
648
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
649
43.3k
    
return false0
;
650
43.3k
  }
651
43.3k
  case GIPFP_I64_Predicate_vecshiftR16Narrow: {
652
8
    
653
8
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
654
43.3k
655
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
656
43.3k
    
return false0
;
657
43.3k
  }
658
43.3k
  case GIPFP_I64_Predicate_vecshiftR32: {
659
4
    
660
4
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
661
43.3k
662
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
663
43.3k
    
return false0
;
664
43.3k
  }
665
43.3k
  case GIPFP_I64_Predicate_vecshiftR32Narrow: {
666
14
    
667
14
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
668
43.3k
669
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
670
43.3k
    
return false0
;
671
43.3k
  }
672
43.3k
  case GIPFP_I64_Predicate_vecshiftR64: {
673
3
    
674
3
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
675
43.3k
676
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
677
43.3k
    
return false0
;
678
43.3k
  }
679
43.3k
  case GIPFP_I64_Predicate_vecshiftR64Narrow: {
680
8
    
681
8
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
682
43.3k
683
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
684
43.3k
    
return false0
;
685
43.3k
  }
686
43.3k
  case GIPFP_I64_Predicate_vecshiftR8: {
687
0
    
688
0
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
689
43.3k
690
43.3k
    
llvm_unreachable0
("ImmediateCode should have returned");
691
43.3k
    
return false0
;
692
0
  }
693
0
  }
694
0
  llvm_unreachable("Unknown predicate");
695
0
  return false;
696
0
}
697
// PatFrag predicates.
698
enum {
699
  GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1,
700
  GIPFP_APFloat_Predicate_fpimm16,
701
  GIPFP_APFloat_Predicate_fpimm32,
702
  GIPFP_APFloat_Predicate_fpimm64,
703
  GIPFP_APFloat_Predicate_simdimmtype10,
704
};
705
23.6k
bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
706
23.6k
  switch (PredicateID) {
707
23.6k
  case GIPFP_APFloat_Predicate_fpimm0: {
708
23.6k
    
709
23.6k
  return Imm.isExactlyValue(+0.0);
710
23.6k
711
23.6k
    
llvm_unreachable0
("ImmediateCode should have returned");
712
23.6k
    
return false0
;
713
23.6k
  }
714
23.6k
  case GIPFP_APFloat_Predicate_fpimm16: {
715
0
    
716
0
      return AArch64_AM::getFP16Imm(Imm) != -1;
717
23.6k
    
718
23.6k
    
llvm_unreachable0
("ImmediateCode should have returned");
719
23.6k
    
return false0
;
720
23.6k
  }
721
23.6k
  case GIPFP_APFloat_Predicate_fpimm32: {
722
0
    
723
0
      return AArch64_AM::getFP32Imm(Imm) != -1;
724
23.6k
    
725
23.6k
    
llvm_unreachable0
("ImmediateCode should have returned");
726
23.6k
    
return false0
;
727
23.6k
  }
728
23.6k
  case GIPFP_APFloat_Predicate_fpimm64: {
729
0
    
730
0
      return AArch64_AM::getFP64Imm(Imm) != -1;
731
23.6k
    
732
23.6k
    
llvm_unreachable0
("ImmediateCode should have returned");
733
23.6k
    
return false0
;
734
23.6k
  }
735
23.6k
  case GIPFP_APFloat_Predicate_simdimmtype10: {
736
0
    
737
0
      return AArch64_AM::isAdvSIMDModImmType10(
738
0
                 Imm.bitcastToAPInt().getZExtValue());
739
23.6k
    
740
23.6k
    
llvm_unreachable0
("ImmediateCode should have returned");
741
23.6k
    
return false0
;
742
0
  }
743
0
  }
744
0
  llvm_unreachable("Unknown predicate");
745
0
  return false;
746
0
}
747
// PatFrag predicates.
748
enum {
749
  GIPFP_APInt_Predicate_logical_imm32 = GIPFP_APInt_Invalid + 1,
750
  GIPFP_APInt_Predicate_logical_imm64,
751
};
752
0
bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
753
0
  switch (PredicateID) {
754
0
  case GIPFP_APInt_Predicate_logical_imm32: {
755
0
    
756
0
  return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32);
757
0
758
0
    llvm_unreachable("ImmediateCode should have returned");
759
0
    return false;
760
0
  }
761
0
  case GIPFP_APInt_Predicate_logical_imm64: {
762
0
    
763
0
  return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64);
764
0
765
0
    llvm_unreachable("ImmediateCode should have returned");
766
0
    return false;
767
0
  }
768
0
  }
769
0
  llvm_unreachable("Unknown predicate");
770
0
  return false;
771
0
}
772
0
bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
773
0
  const MachineFunction &MF = *MI.getParent()->getParent();
774
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
775
0
  (void)MRI;
776
0
  llvm_unreachable("Unknown predicate");
777
0
  return false;
778
0
}
779
780
AArch64InstructionSelector::ComplexMatcherMemFn
781
AArch64InstructionSelector::ComplexPredicateFns[] = {
782
  nullptr, // GICP_Invalid
783
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32
784
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64
785
  &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128
786
  &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16
787
  &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32
788
  &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64
789
  &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8
790
  &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128
791
  &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16
792
  &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32
793
  &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64
794
  &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8
795
};
796
797
// Custom renderers.
798
enum {
799
  GICR_Invalid,
800
  GICR_renderTruncImm, 
801
};
802
AArch64InstructionSelector::CustomRendererFn
803
AArch64InstructionSelector::CustomRenderers[] = {
804
  nullptr, // GICP_Invalid
805
  &AArch64InstructionSelector::renderTruncImm, // gi_trunc_imm
806
};
807
808
7.52M
bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
809
7.52M
  MachineFunction &MF = *I.getParent()->getParent();
810
7.52M
  MachineRegisterInfo &MRI = MF.getRegInfo();
811
7.52M
  // FIXME: This should be computed on a per-function basis rather than per-insn.
812
7.52M
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
813
7.52M
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
814
7.52M
  NewMIVector OutMIs;
815
7.52M
  State.MIs.clear();
816
7.52M
  State.MIs.push_back(&I);
817
7.52M
818
7.52M
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
819
3.24M
    return true;
820
3.24M
  }
821
4.27M
822
4.27M
  return false;
823
4.27M
}
824
825
7.52M
const int64_t *AArch64InstructionSelector::getMatchTable() const {
826
7.52M
  constexpr static int64_t MatchTable0[] = {
827
7.52M
    GIM_SwitchOpcode, /*MI*/0, /*[*/35, 146, /*)*//*default:*//*Label 57*/ 84935,
828
7.52M
    /*TargetOpcode::G_ADD*//*Label 0*/ 116,
829
7.52M
    /*TargetOpcode::G_SUB*//*Label 1*/ 7529,
830
7.52M
    /*TargetOpcode::G_MUL*//*Label 2*/ 10110,
831
7.52M
    /*TargetOpcode::G_SDIV*//*Label 3*/ 10891,
832
7.52M
    /*TargetOpcode::G_UDIV*//*Label 4*/ 10960, 0, 0,
833
7.52M
    /*TargetOpcode::G_AND*//*Label 5*/ 11029,
834
7.52M
    /*TargetOpcode::G_OR*//*Label 6*/ 11687,
835
7.52M
    /*TargetOpcode::G_XOR*//*Label 7*/ 12229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
836
7.52M
    /*TargetOpcode::G_BITCAST*//*Label 8*/ 12939, 0, 0,
837
7.52M
    /*TargetOpcode::G_LOAD*//*Label 9*/ 20432,
838
7.52M
    /*TargetOpcode::G_SEXTLOAD*//*Label 10*/ 22488,
839
7.52M
    /*TargetOpcode::G_ZEXTLOAD*//*Label 11*/ 22959,
840
7.52M
    /*TargetOpcode::G_STORE*//*Label 12*/ 23311, 0,
841
7.52M
    /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 13*/ 25558,
842
7.52M
    /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 14*/ 26755,
843
7.52M
    /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 15*/ 27784,
844
7.52M
    /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 16*/ 28813,
845
7.52M
    /*TargetOpcode::G_ATOMICRMW_AND*//*Label 17*/ 30222, 0,
846
7.52M
    /*TargetOpcode::G_ATOMICRMW_OR*//*Label 18*/ 31631,
847
7.52M
    /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 19*/ 32660,
848
7.52M
    /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 20*/ 33689,
849
7.52M
    /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 21*/ 34718,
850
7.52M
    /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 22*/ 35747,
851
7.52M
    /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 23*/ 36776, 0, 0,
852
7.52M
    /*TargetOpcode::G_INTRINSIC*//*Label 24*/ 37805,
853
7.52M
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 25*/ 73466,
854
7.52M
    /*TargetOpcode::G_ANYEXT*//*Label 26*/ 73708,
855
7.52M
    /*TargetOpcode::G_TRUNC*//*Label 27*/ 73822,
856
7.52M
    /*TargetOpcode::G_CONSTANT*//*Label 28*/ 73947,
857
7.52M
    /*TargetOpcode::G_FCONSTANT*//*Label 29*/ 74000, 0, 0,
858
7.52M
    /*TargetOpcode::G_SEXT*//*Label 30*/ 74078,
859
7.52M
    /*TargetOpcode::G_ZEXT*//*Label 31*/ 74258,
860
7.52M
    /*TargetOpcode::G_SHL*//*Label 32*/ 74717,
861
7.52M
    /*TargetOpcode::G_LSHR*//*Label 33*/ 74893,
862
7.52M
    /*TargetOpcode::G_ASHR*//*Label 34*/ 75144, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
863
7.52M
    /*TargetOpcode::G_FADD*//*Label 35*/ 75395,
864
7.52M
    /*TargetOpcode::G_FSUB*//*Label 36*/ 75968,
865
7.52M
    /*TargetOpcode::G_FMUL*//*Label 37*/ 76241,
866
7.52M
    /*TargetOpcode::G_FMA*//*Label 38*/ 76907,
867
7.52M
    /*TargetOpcode::G_FDIV*//*Label 39*/ 79731, 0, 0, 0, 0, 0, 0, 0,
868
7.52M
    /*TargetOpcode::G_FNEG*//*Label 40*/ 80004,
869
7.52M
    /*TargetOpcode::G_FPEXT*//*Label 41*/ 80552,
870
7.52M
    /*TargetOpcode::G_FPTRUNC*//*Label 42*/ 80681,
871
7.52M
    /*TargetOpcode::G_FPTOSI*//*Label 43*/ 80810,
872
7.52M
    /*TargetOpcode::G_FPTOUI*//*Label 44*/ 81398,
873
7.52M
    /*TargetOpcode::G_SITOFP*//*Label 45*/ 81986,
874
7.52M
    /*TargetOpcode::G_UITOFP*//*Label 46*/ 82264,
875
7.52M
    /*TargetOpcode::G_FABS*//*Label 47*/ 82542, 0, 0, 0,
876
7.52M
    /*TargetOpcode::G_BR*//*Label 48*/ 83099, 0,
877
7.52M
    /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 49*/ 83112, 0,
878
7.52M
    /*TargetOpcode::G_CTTZ*//*Label 50*/ 83471, 0,
879
7.52M
    /*TargetOpcode::G_CTLZ*//*Label 51*/ 83574, 0,
880
7.52M
    /*TargetOpcode::G_CTPOP*//*Label 52*/ 84197,
881
7.52M
    /*TargetOpcode::G_BSWAP*//*Label 53*/ 84255,
882
7.52M
    /*TargetOpcode::G_FCEIL*//*Label 54*/ 84308, 0, 0,
883
7.52M
    /*TargetOpcode::G_FSQRT*//*Label 55*/ 84517,
884
7.52M
    /*TargetOpcode::G_FFLOOR*//*Label 56*/ 84726,
885
7.52M
    // Label 0: @116
886
7.52M
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 67*/ 7528,
887
7.52M
    /*GILLT_s32*//*Label 58*/ 132,
888
7.52M
    /*GILLT_s64*//*Label 59*/ 233, 0,
889
7.52M
    /*GILLT_v2s32*//*Label 60*/ 1443,
890
7.52M
    /*GILLT_v2s64*//*Label 61*/ 2056,
891
7.52M
    /*GILLT_v4s16*//*Label 62*/ 3159,
892
7.52M
    /*GILLT_v4s32*//*Label 63*/ 3772,
893
7.52M
    /*GILLT_v8s8*//*Label 64*/ 5245,
894
7.52M
    /*GILLT_v8s16*//*Label 65*/ 5650,
895
7.52M
    /*GILLT_v16s8*//*Label 66*/ 7123,
896
7.52M
    // Label 58: @132
897
7.52M
    GIM_Try, /*On fail goto*//*Label 68*/ 232,
898
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
899
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
900
7.52M
      GIM_Try, /*On fail goto*//*Label 69*/ 176, // Rule ID 3838 //
901
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
902
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID,
903
7.52M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
904
7.52M
        // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
905
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
906
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
907
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
908
7.52M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
909
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
910
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
911
7.52M
        // GIR_Coverage, 3838,
912
7.52M
        GIR_Done,
913
7.52M
      // Label 69: @176
914
7.52M
      GIM_Try, /*On fail goto*//*Label 70*/ 210, // Rule ID 51 //
915
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
916
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
917
7.52M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
918
7.52M
        // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
919
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
920
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
921
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
922
7.52M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
923
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
924
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
925
7.52M
        // GIR_Coverage, 51,
926
7.52M
        GIR_Done,
927
7.52M
      // Label 70: @210
928
7.52M
      GIM_Try, /*On fail goto*//*Label 71*/ 231, // Rule ID 53 //
929
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
930
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
931
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
932
7.52M
        // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
933
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDWrr,
934
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
935
7.52M
        // GIR_Coverage, 53,
936
7.52M
        GIR_Done,
937
7.52M
      // Label 71: @231
938
7.52M
      GIM_Reject,
939
7.52M
    // Label 68: @232
940
7.52M
    GIM_Reject,
941
7.52M
    // Label 59: @233
942
7.52M
    GIM_Try, /*On fail goto*//*Label 72*/ 1442,
943
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
944
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
945
7.52M
      GIM_Try, /*On fail goto*//*Label 73*/ 312, // Rule ID 3509 //
946
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
947
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
948
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT,
949
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
950
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
951
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
952
7.52M
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0,
953
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
954
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT,
955
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
956
7.52M
        // MIs[2] Rn
957
7.52M
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
958
7.52M
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
959
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
960
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
961
7.52M
        // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }))  =>  (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn)
962
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p,
963
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
964
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
965
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
966
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
967
7.52M
        // GIR_Coverage, 3509,
968
7.52M
        GIR_Done,
969
7.52M
      // Label 73: @312
970
7.52M
      GIM_Try, /*On fail goto*//*Label 74*/ 381, // Rule ID 4257 //
971
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
972
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
973
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT,
974
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
975
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
976
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
977
7.52M
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
978
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
979
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT,
980
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
981
7.52M
        // MIs[2] Rn
982
7.52M
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
983
7.52M
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0,
984
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
985
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
986
7.52M
        // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn)
987
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p,
988
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
989
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
990
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
991
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
992
7.52M
        // GIR_Coverage, 4257,
993
7.52M
        GIR_Done,
994
7.52M
      // Label 74: @381
995
7.52M
      GIM_Try, /*On fail goto*//*Label 75*/ 415, // Rule ID 3839 //
996
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
997
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID,
998
7.52M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
999
7.52M
        // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
1000
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
1001
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1002
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1003
7.52M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
1004
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1005
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1006
7.52M
        // GIR_Coverage, 3839,
1007
7.52M
        GIR_Done,
1008
7.52M
      // Label 75: @415
1009
7.52M
      GIM_Try, /*On fail goto*//*Label 76*/ 511, // Rule ID 1922 //
1010
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1011
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1012
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1013
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1014
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1015
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1016
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1017
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1018
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1019
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1020
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1021
7.52M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
1022
7.52M
        // MIs[3] Operand 1
1023
7.52M
        // No operand predicates
1024
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1025
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1026
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1027
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1028
7.52M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1029
7.52M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1030
7.52M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1031
7.52M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1032
7.52M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1033
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1034
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1035
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1036
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1037
7.52M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1038
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1039
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1040
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1041
7.52M
        // GIR_Coverage, 1922,
1042
7.52M
        GIR_Done,
1043
7.52M
      // Label 76: @511
1044
7.52M
      GIM_Try, /*On fail goto*//*Label 77*/ 607, // Rule ID 1923 //
1045
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1046
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1047
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1048
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1049
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1050
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1051
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1052
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1053
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1054
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1055
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1056
7.52M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
1057
7.52M
        // MIs[3] Operand 1
1058
7.52M
        // No operand predicates
1059
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1060
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1061
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1062
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1063
7.52M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1064
7.52M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1065
7.52M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1066
7.52M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1067
7.52M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1068
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1069
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1070
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1071
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1072
7.52M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1073
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1074
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1075
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1076
7.52M
        // GIR_Coverage, 1923,
1077
7.52M
        GIR_Done,
1078
7.52M
      // Label 77: @607
1079
7.52M
      GIM_Try, /*On fail goto*//*Label 78*/ 641, // Rule ID 52 //
1080
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID,
1081
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
1082
7.52M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
1083
7.52M
        // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
1084
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
1085
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1086
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1087
7.52M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
1088
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1089
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1090
7.52M
        // GIR_Coverage, 52,
1091
7.52M
        GIR_Done,
1092
7.52M
      // Label 78: @641
1093
7.52M
      GIM_Try, /*On fail goto*//*Label 79*/ 737, // Rule ID 4090 //
1094
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1095
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1096
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1097
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1098
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1099
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1100
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1101
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1102
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1103
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1104
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1105
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1106
7.52M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
1107
7.52M
        // MIs[3] Operand 1
1108
7.52M
        // No operand predicates
1109
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1110
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1111
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1112
7.52M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1113
7.52M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1114
7.52M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1115
7.52M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1116
7.52M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1117
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1118
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1119
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1120
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1121
7.52M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1122
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1123
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1124
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1125
7.52M
        // GIR_Coverage, 4090,
1126
7.52M
        GIR_Done,
1127
7.52M
      // Label 79: @737
1128
7.52M
      GIM_Try, /*On fail goto*//*Label 80*/ 833, // Rule ID 4091 //
1129
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1130
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1131
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1132
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1133
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1134
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1135
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1136
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1137
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1138
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1139
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1140
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
1141
7.52M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
1142
7.52M
        // MIs[3] Operand 1
1143
7.52M
        // No operand predicates
1144
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1145
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1146
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1147
7.52M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
1148
7.52M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1149
7.52M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
1150
7.52M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1151
7.52M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
1152
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1153
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1154
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1155
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1156
7.52M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1157
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1158
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1159
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1160
7.52M
        // GIR_Coverage, 4091,
1161
7.52M
        GIR_Done,
1162
7.52M
      // Label 80: @833
1163
7.52M
      GIM_Try, /*On fail goto*//*Label 81*/ 918, // Rule ID 3850 //
1164
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1165
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1166
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1167
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1168
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1169
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1170
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1171
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1172
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1173
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1174
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
1175
7.52M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1176
7.52M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1177
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1178
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1179
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1180
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1181
7.52M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1182
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1183
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1184
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1185
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1186
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1187
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1188
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1189
7.52M
        // GIR_Coverage, 3850,
1190
7.52M
        GIR_Done,
1191
7.52M
      // Label 81: @918
1192
7.52M
      GIM_Try, /*On fail goto*//*Label 82*/ 1003, // Rule ID 3851 //
1193
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1194
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1195
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1196
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1197
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1198
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1199
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1200
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1201
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1202
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1203
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
1204
7.52M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1205
7.52M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1206
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1207
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1208
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1209
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1210
7.52M
        // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1211
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1212
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1213
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1214
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1215
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1216
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1217
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1218
7.52M
        // GIR_Coverage, 3851,
1219
7.52M
        GIR_Done,
1220
7.52M
      // Label 82: @1003
1221
7.52M
      GIM_Try, /*On fail goto*//*Label 83*/ 1088, // Rule ID 83 //
1222
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1223
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1224
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1225
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1226
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1227
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1228
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1229
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1230
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1231
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1232
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1233
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
1234
7.52M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1235
7.52M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1236
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1237
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1238
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1239
7.52M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1240
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr,
1241
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1242
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1243
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1244
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1245
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1246
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1247
7.52M
        // GIR_Coverage, 83,
1248
7.52M
        GIR_Done,
1249
7.52M
      // Label 83: @1088
1250
7.52M
      GIM_Try, /*On fail goto*//*Label 84*/ 1173, // Rule ID 85 //
1251
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1252
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1253
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1254
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1255
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1256
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1257
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1258
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1259
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1260
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1261
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1262
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
1263
7.52M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1264
7.52M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1265
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1266
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1267
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1268
7.52M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
1269
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr,
1270
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1271
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1272
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1273
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1274
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1275
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1276
7.52M
        // GIR_Coverage, 85,
1277
7.52M
        GIR_Done,
1278
7.52M
      // Label 84: @1173
1279
7.52M
      GIM_Try, /*On fail goto*//*Label 85*/ 1229, // Rule ID 3904 //
1280
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1281
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1282
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1283
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1284
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1285
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1286
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1287
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1288
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1289
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1290
7.52M
        // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 325:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1291
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
1292
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1293
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1294
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1295
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1296
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1297
7.52M
        // GIR_Coverage, 3904,
1298
7.52M
        GIR_Done,
1299
7.52M
      // Label 85: @1229
1300
7.52M
      GIM_Try, /*On fail goto*//*Label 86*/ 1285, // Rule ID 3910 //
1301
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1302
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1303
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1304
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1305
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1306
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1307
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1308
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1309
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1310
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1311
7.52M
        // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 383:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1312
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64,
1313
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1314
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1315
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1316
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1317
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1318
7.52M
        // GIR_Coverage, 3910,
1319
7.52M
        GIR_Done,
1320
7.52M
      // Label 86: @1285
1321
7.52M
      GIM_Try, /*On fail goto*//*Label 87*/ 1341, // Rule ID 715 //
1322
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1323
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1324
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1325
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1326
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1327
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1328
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1329
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1330
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1331
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1332
7.52M
        // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 325:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1333
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64,
1334
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1335
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1336
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1337
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1338
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1339
7.52M
        // GIR_Coverage, 715,
1340
7.52M
        GIR_Done,
1341
7.52M
      // Label 87: @1341
1342
7.52M
      GIM_Try, /*On fail goto*//*Label 88*/ 1397, // Rule ID 759 //
1343
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1344
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1345
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1346
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1347
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1348
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1349
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1350
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1351
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1352
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1353
7.52M
        // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 383:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
1354
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64,
1355
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1356
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1357
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1358
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1359
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1360
7.52M
        // GIR_Coverage, 759,
1361
7.52M
        GIR_Done,
1362
7.52M
      // Label 88: @1397
1363
7.52M
      GIM_Try, /*On fail goto*//*Label 89*/ 1418, // Rule ID 54 //
1364
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
1365
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
1366
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
1367
7.52M
        // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ADDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
1368
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDXrr,
1369
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1370
7.52M
        // GIR_Coverage, 54,
1371
7.52M
        GIR_Done,
1372
7.52M
      // Label 89: @1418
1373
7.52M
      GIM_Try, /*On fail goto*//*Label 90*/ 1441, // Rule ID 1214 //
1374
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1375
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1376
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1377
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1378
7.52M
        // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (ADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
1379
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv1i64,
1380
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1381
7.52M
        // GIR_Coverage, 1214,
1382
7.52M
        GIR_Done,
1383
7.52M
      // Label 90: @1441
1384
7.52M
      GIM_Reject,
1385
7.52M
    // Label 72: @1442
1386
7.52M
    GIM_Reject,
1387
7.52M
    // Label 60: @1443
1388
7.52M
    GIM_Try, /*On fail goto*//*Label 91*/ 2055,
1389
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1390
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1391
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
1392
7.52M
      GIM_Try, /*On fail goto*//*Label 92*/ 1521, // Rule ID 3922 //
1393
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1394
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1395
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1396
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1397
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1398
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1399
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1400
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1401
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1402
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1403
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1404
7.52M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 324:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1405
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
1406
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1407
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1408
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1409
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1410
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1411
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1412
7.52M
        // GIR_Coverage, 3922,
1413
7.52M
        GIR_Done,
1414
7.52M
      // Label 92: @1521
1415
7.52M
      GIM_Try, /*On fail goto*//*Label 93*/ 1585, // Rule ID 3928 //
1416
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1417
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1418
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1419
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1420
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1421
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1422
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1423
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1424
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1425
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1426
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1427
7.52M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 382:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1428
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
1429
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1430
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1431
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1432
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1433
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1434
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1435
7.52M
        // GIR_Coverage, 3928,
1436
7.52M
        GIR_Done,
1437
7.52M
      // Label 93: @1585
1438
7.52M
      GIM_Try, /*On fail goto*//*Label 94*/ 1637, // Rule ID 3902 //
1439
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1440
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1441
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1442
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1443
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1444
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1445
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1446
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1447
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1448
7.52M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 325:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1449
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
1450
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1451
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1452
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1453
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1454
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1455
7.52M
        // GIR_Coverage, 3902,
1456
7.52M
        GIR_Done,
1457
7.52M
      // Label 94: @1637
1458
7.52M
      GIM_Try, /*On fail goto*//*Label 95*/ 1689, // Rule ID 3908 //
1459
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1460
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1461
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1462
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1463
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1464
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1465
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1466
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1467
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1468
7.52M
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 383:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1469
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32,
1470
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1471
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1472
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1473
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1474
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1475
7.52M
        // GIR_Coverage, 3908,
1476
7.52M
        GIR_Done,
1477
7.52M
      // Label 95: @1689
1478
7.52M
      GIM_Try, /*On fail goto*//*Label 96*/ 1753, // Rule ID 989 //
1479
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1480
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1481
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1482
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1483
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1484
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1485
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1486
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1487
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1488
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1489
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1490
7.52M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 324:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1491
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32,
1492
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1493
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1494
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1495
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1496
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1497
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1498
7.52M
        // GIR_Coverage, 989,
1499
7.52M
        GIR_Done,
1500
7.52M
      // Label 96: @1753
1501
7.52M
      GIM_Try, /*On fail goto*//*Label 97*/ 1817, // Rule ID 1100 //
1502
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1503
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1504
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1505
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1506
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1507
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1508
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1509
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1510
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1511
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1512
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1513
7.52M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 382:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1514
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32,
1515
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1516
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1517
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1518
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1519
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1520
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1521
7.52M
        // GIR_Coverage, 1100,
1522
7.52M
        GIR_Done,
1523
7.52M
      // Label 97: @1817
1524
7.52M
      GIM_Try, /*On fail goto*//*Label 98*/ 1869, // Rule ID 713 //
1525
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1526
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1527
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1528
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1529
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1530
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1531
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1532
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1533
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1534
7.52M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 325:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1535
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32,
1536
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1537
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1538
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1539
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1540
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1541
7.52M
        // GIR_Coverage, 713,
1542
7.52M
        GIR_Done,
1543
7.52M
      // Label 98: @1869
1544
7.52M
      GIM_Try, /*On fail goto*//*Label 99*/ 1921, // Rule ID 757 //
1545
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1546
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1547
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1548
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1549
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1550
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1551
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1552
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1553
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1554
7.52M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 383:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
1555
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32,
1556
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1557
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1558
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1559
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1560
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1561
7.52M
        // GIR_Coverage, 757,
1562
7.52M
        GIR_Done,
1563
7.52M
      // Label 99: @1921
1564
7.52M
      GIM_Try, /*On fail goto*//*Label 100*/ 1978, // Rule ID 3916 //
1565
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1566
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1567
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1568
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1569
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1570
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1571
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1572
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1573
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1574
7.52M
        // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (MLAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1575
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32,
1576
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1577
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1578
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1579
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1580
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1581
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1582
7.52M
        // GIR_Coverage, 3916,
1583
7.52M
        GIR_Done,
1584
7.52M
      // Label 100: @1978
1585
7.52M
      GIM_Try, /*On fail goto*//*Label 101*/ 2035, // Rule ID 969 //
1586
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1587
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1588
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1589
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1590
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1591
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1592
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1593
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1594
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1595
7.52M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (MLAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1596
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32,
1597
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1598
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1599
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1600
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1601
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1602
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1603
7.52M
        // GIR_Coverage, 969,
1604
7.52M
        GIR_Done,
1605
7.52M
      // Label 101: @2035
1606
7.52M
      GIM_Try, /*On fail goto*//*Label 102*/ 2054, // Rule ID 793 //
1607
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1608
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1609
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1610
7.52M
        // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1611
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i32,
1612
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1613
7.52M
        // GIR_Coverage, 793,
1614
7.52M
        GIR_Done,
1615
7.52M
      // Label 102: @2054
1616
7.52M
      GIM_Reject,
1617
7.52M
    // Label 91: @2055
1618
7.52M
    GIM_Reject,
1619
7.52M
    // Label 61: @2056
1620
7.52M
    GIM_Try, /*On fail goto*//*Label 103*/ 3158,
1621
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1622
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1623
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
1624
7.52M
      GIM_Try, /*On fail goto*//*Label 104*/ 2147, // Rule ID 3976 //
1625
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1626
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1627
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1628
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1629
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1630
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1631
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1632
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1633
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1634
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1635
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1636
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1637
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1638
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1639
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1640
7.52M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 324:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1641
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
1642
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1643
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1644
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1645
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1646
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1647
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1648
7.52M
        // GIR_Coverage, 3976,
1649
7.52M
        GIR_Done,
1650
7.52M
      // Label 104: @2147
1651
7.52M
      GIM_Try, /*On fail goto*//*Label 105*/ 2224, // Rule ID 3994 //
1652
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1653
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1654
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1655
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1656
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1657
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1658
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1659
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1660
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1661
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1662
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1663
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1664
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1665
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1666
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1667
7.52M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 382:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1668
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
1669
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1670
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1671
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1672
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1673
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1674
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1675
7.52M
        // GIR_Coverage, 3994,
1676
7.52M
        GIR_Done,
1677
7.52M
      // Label 105: @2224
1678
7.52M
      GIM_Try, /*On fail goto*//*Label 106*/ 2301, // Rule ID 1296 //
1679
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1680
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1681
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1682
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1683
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1684
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1685
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1686
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1687
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
1688
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1689
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1690
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1691
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1692
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1693
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1694
7.52M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 324:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1695
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64,
1696
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1697
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1698
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1699
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1700
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1701
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1702
7.52M
        // GIR_Coverage, 1296,
1703
7.52M
        GIR_Done,
1704
7.52M
      // Label 106: @2301
1705
7.52M
      GIM_Try, /*On fail goto*//*Label 107*/ 2378, // Rule ID 1362 //
1706
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1707
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1708
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1709
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1710
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1711
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1712
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1713
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1714
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
1715
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1716
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1717
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1718
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1719
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1720
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1721
7.52M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 382:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1722
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64,
1723
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1724
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1725
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
1726
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
1727
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1728
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1729
7.52M
        // GIR_Coverage, 1362,
1730
7.52M
        GIR_Done,
1731
7.52M
      // Label 107: @2378
1732
7.52M
      GIM_Try, /*On fail goto*//*Label 108*/ 2442, // Rule ID 3988 //
1733
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1734
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1735
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1736
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1737
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
1738
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1739
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1740
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1741
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1742
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1743
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1744
7.52M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 341:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1745
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
1746
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1747
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1748
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1749
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1750
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1751
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1752
7.52M
        // GIR_Coverage, 3988,
1753
7.52M
        GIR_Done,
1754
7.52M
      // Label 108: @2442
1755
7.52M
      GIM_Try, /*On fail goto*//*Label 109*/ 2506, // Rule ID 4006 //
1756
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1757
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1758
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1759
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1760
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
1761
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1762
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1763
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1764
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1765
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1766
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1767
7.52M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 395:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1768
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
1769
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1770
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1771
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1772
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1773
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1774
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1775
7.52M
        // GIR_Coverage, 4006,
1776
7.52M
        GIR_Done,
1777
7.52M
      // Label 109: @2506
1778
7.52M
      GIM_Try, /*On fail goto*//*Label 110*/ 2558, // Rule ID 3905 //
1779
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1780
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1781
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1782
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1783
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1784
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1785
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1786
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1787
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1788
7.52M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 325:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1789
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
1790
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1791
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1792
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1793
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1794
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1795
7.52M
        // GIR_Coverage, 3905,
1796
7.52M
        GIR_Done,
1797
7.52M
      // Label 110: @2558
1798
7.52M
      GIM_Try, /*On fail goto*//*Label 111*/ 2610, // Rule ID 3911 //
1799
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1800
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1801
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1802
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1803
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1804
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1805
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1806
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1807
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1808
7.52M
        // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 383:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1809
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64,
1810
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1811
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
1812
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1813
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1814
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1815
7.52M
        // GIR_Coverage, 3911,
1816
7.52M
        GIR_Done,
1817
7.52M
      // Label 111: @2610
1818
7.52M
      GIM_Try, /*On fail goto*//*Label 112*/ 2674, // Rule ID 1320 //
1819
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1820
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1821
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1822
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1823
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1824
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
1825
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1826
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1827
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1828
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1829
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1830
7.52M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 341:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1831
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64,
1832
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1833
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1834
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1835
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1836
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1837
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1838
7.52M
        // GIR_Coverage, 1320,
1839
7.52M
        GIR_Done,
1840
7.52M
      // Label 112: @2674
1841
7.52M
      GIM_Try, /*On fail goto*//*Label 113*/ 2738, // Rule ID 1380 //
1842
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1843
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1844
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1845
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1846
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1847
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
1848
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1849
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1850
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
1851
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
1852
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1853
7.52M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 395:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1854
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64,
1855
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1856
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1857
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1858
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
1859
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1860
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1861
7.52M
        // GIR_Coverage, 1380,
1862
7.52M
        GIR_Done,
1863
7.52M
      // Label 113: @2738
1864
7.52M
      GIM_Try, /*On fail goto*//*Label 114*/ 2790, // Rule ID 716 //
1865
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1866
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1867
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1868
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1869
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1870
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
1871
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1872
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1873
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1874
7.52M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 325:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1875
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64,
1876
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1877
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1878
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1879
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1880
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1881
7.52M
        // GIR_Coverage, 716,
1882
7.52M
        GIR_Done,
1883
7.52M
      // Label 114: @2790
1884
7.52M
      GIM_Try, /*On fail goto*//*Label 115*/ 2842, // Rule ID 760 //
1885
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1886
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1887
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1888
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1889
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
1890
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
1891
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1892
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1893
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1894
7.52M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 383:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
1895
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64,
1896
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1897
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
1898
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1899
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1900
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1901
7.52M
        // GIR_Coverage, 760,
1902
7.52M
        GIR_Done,
1903
7.52M
      // Label 115: @2842
1904
7.52M
      GIM_Try, /*On fail goto*//*Label 116*/ 2900, // Rule ID 1308 //
1905
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1906
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1907
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1908
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1909
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1910
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1911
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1912
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1913
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1914
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1915
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1916
7.52M
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1917
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv2i32_v2i64,
1918
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1919
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1920
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1921
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1922
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1923
7.52M
        // GIR_Coverage, 1308,
1924
7.52M
        GIR_Done,
1925
7.52M
      // Label 116: @2900
1926
7.52M
      GIM_Try, /*On fail goto*//*Label 117*/ 2958, // Rule ID 1368 //
1927
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1928
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1929
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1930
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1931
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1932
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1933
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1934
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1935
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1936
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1937
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1938
7.52M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1939
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64,
1940
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1941
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1942
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1943
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1944
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1945
7.52M
        // GIR_Coverage, 1368,
1946
7.52M
        GIR_Done,
1947
7.52M
      // Label 117: @2958
1948
7.52M
      GIM_Try, /*On fail goto*//*Label 118*/ 3003, // Rule ID 3982 //
1949
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1950
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1951
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1952
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1953
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1954
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1955
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1956
7.52M
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1957
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64,
1958
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1959
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1960
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1961
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1962
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1963
7.52M
        // GIR_Coverage, 3982,
1964
7.52M
        GIR_Done,
1965
7.52M
      // Label 118: @3003
1966
7.52M
      GIM_Try, /*On fail goto*//*Label 119*/ 3048, // Rule ID 4000 //
1967
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1968
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1969
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1970
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1971
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1972
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
1973
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1974
7.52M
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1975
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64,
1976
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1977
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1978
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1979
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1980
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1981
7.52M
        // GIR_Coverage, 4000,
1982
7.52M
        GIR_Done,
1983
7.52M
      // Label 119: @3048
1984
7.52M
      GIM_Try, /*On fail goto*//*Label 120*/ 3093, // Rule ID 1314 //
1985
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
1986
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
1987
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1988
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1989
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1990
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
1991
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1992
7.52M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
1993
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64,
1994
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1995
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1996
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1997
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
1998
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1999
7.52M
        // GIR_Coverage, 1314,
2000
7.52M
        GIR_Done,
2001
7.52M
      // Label 120: @3093
2002
7.52M
      GIM_Try, /*On fail goto*//*Label 121*/ 3138, // Rule ID 1374 //
2003
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2004
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2005
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2006
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2007
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2008
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2009
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2010
7.52M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
2011
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64,
2012
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2013
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
2014
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2015
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2016
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2017
7.52M
        // GIR_Coverage, 1374,
2018
7.52M
        GIR_Done,
2019
7.52M
      // Label 121: @3138
2020
7.52M
      GIM_Try, /*On fail goto*//*Label 122*/ 3157, // Rule ID 795 //
2021
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2022
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2023
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2024
7.52M
        // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
2025
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i64,
2026
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2027
7.52M
        // GIR_Coverage, 795,
2028
7.52M
        GIR_Done,
2029
7.52M
      // Label 122: @3157
2030
7.52M
      GIM_Reject,
2031
7.52M
    // Label 103: @3158
2032
7.52M
    GIM_Reject,
2033
7.52M
    // Label 62: @3159
2034
7.52M
    GIM_Try, /*On fail goto*//*Label 123*/ 3771,
2035
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
2036
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
2037
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
2038
7.52M
      GIM_Try, /*On fail goto*//*Label 124*/ 3237, // Rule ID 3920 //
2039
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2040
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2041
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2042
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2043
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2044
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2045
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2046
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2047
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2048
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2049
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2050
7.52M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 324:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2051
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
2052
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2053
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2054
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2055
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2056
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2057
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2058
7.52M
        // GIR_Coverage, 3920,
2059
7.52M
        GIR_Done,
2060
7.52M
      // Label 124: @3237
2061
7.52M
      GIM_Try, /*On fail goto*//*Label 125*/ 3301, // Rule ID 3926 //
2062
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2063
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2064
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2065
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2066
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2067
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2068
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2069
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2070
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2071
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2072
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2073
7.52M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 382:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2074
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
2075
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2076
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2077
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2078
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2079
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2080
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2081
7.52M
        // GIR_Coverage, 3926,
2082
7.52M
        GIR_Done,
2083
7.52M
      // Label 125: @3301
2084
7.52M
      GIM_Try, /*On fail goto*//*Label 126*/ 3353, // Rule ID 3900 //
2085
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2086
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2087
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2088
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2089
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2090
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2091
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2092
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2093
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2094
7.52M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 325:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2095
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
2096
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2097
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2098
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2099
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2100
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2101
7.52M
        // GIR_Coverage, 3900,
2102
7.52M
        GIR_Done,
2103
7.52M
      // Label 126: @3353
2104
7.52M
      GIM_Try, /*On fail goto*//*Label 127*/ 3405, // Rule ID 3906 //
2105
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2106
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2107
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2108
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2109
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2110
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2111
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2112
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2113
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2114
7.52M
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 383:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2115
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
2116
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2117
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2118
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2119
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2120
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2121
7.52M
        // GIR_Coverage, 3906,
2122
7.52M
        GIR_Done,
2123
7.52M
      // Label 127: @3405
2124
7.52M
      GIM_Try, /*On fail goto*//*Label 128*/ 3469, // Rule ID 987 //
2125
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2126
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2127
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2128
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2129
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2130
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2131
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2132
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2133
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2134
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2135
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2136
7.52M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 324:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2137
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16,
2138
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2139
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2140
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2141
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2142
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2143
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2144
7.52M
        // GIR_Coverage, 987,
2145
7.52M
        GIR_Done,
2146
7.52M
      // Label 128: @3469
2147
7.52M
      GIM_Try, /*On fail goto*//*Label 129*/ 3533, // Rule ID 1098 //
2148
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2149
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2150
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2151
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2152
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2153
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2154
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2155
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2156
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2157
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2158
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2159
7.52M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 382:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2160
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16,
2161
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2162
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2163
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2164
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2165
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2166
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2167
7.52M
        // GIR_Coverage, 1098,
2168
7.52M
        GIR_Done,
2169
7.52M
      // Label 129: @3533
2170
7.52M
      GIM_Try, /*On fail goto*//*Label 130*/ 3585, // Rule ID 711 //
2171
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2172
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2173
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2174
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2175
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2176
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2177
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2178
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2179
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2180
7.52M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 325:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2181
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16,
2182
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2183
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2184
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2185
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2186
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2187
7.52M
        // GIR_Coverage, 711,
2188
7.52M
        GIR_Done,
2189
7.52M
      // Label 130: @3585
2190
7.52M
      GIM_Try, /*On fail goto*//*Label 131*/ 3637, // Rule ID 755 //
2191
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2192
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2193
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2194
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2195
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2196
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2197
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2198
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2199
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2200
7.52M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 383:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
2201
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16,
2202
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2203
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2204
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2205
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2206
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2207
7.52M
        // GIR_Coverage, 755,
2208
7.52M
        GIR_Done,
2209
7.52M
      // Label 131: @3637
2210
7.52M
      GIM_Try, /*On fail goto*//*Label 132*/ 3694, // Rule ID 3914 //
2211
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2212
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2213
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2214
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2215
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2216
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2217
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2218
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2219
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2220
7.52M
        // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (MLAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2221
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16,
2222
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2223
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2224
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2225
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2226
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2227
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2228
7.52M
        // GIR_Coverage, 3914,
2229
7.52M
        GIR_Done,
2230
7.52M
      // Label 132: @3694
2231
7.52M
      GIM_Try, /*On fail goto*//*Label 133*/ 3751, // Rule ID 967 //
2232
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2233
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2234
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2235
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2236
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2237
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2238
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2239
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2240
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2241
7.52M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (MLAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2242
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16,
2243
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2244
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2245
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2246
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2247
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2248
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2249
7.52M
        // GIR_Coverage, 967,
2250
7.52M
        GIR_Done,
2251
7.52M
      // Label 133: @3751
2252
7.52M
      GIM_Try, /*On fail goto*//*Label 134*/ 3770, // Rule ID 791 //
2253
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2254
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2255
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2256
7.52M
        // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2257
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i16,
2258
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2259
7.52M
        // GIR_Coverage, 791,
2260
7.52M
        GIR_Done,
2261
7.52M
      // Label 134: @3770
2262
7.52M
      GIM_Reject,
2263
7.52M
    // Label 123: @3771
2264
7.52M
    GIM_Reject,
2265
7.52M
    // Label 63: @3772
2266
7.52M
    GIM_Try, /*On fail goto*//*Label 135*/ 5244,
2267
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2268
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2269
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
2270
7.52M
      GIM_Try, /*On fail goto*//*Label 136*/ 3863, // Rule ID 3974 //
2271
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2272
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2273
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2274
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2275
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2276
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2277
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2278
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2279
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2280
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2281
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2282
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2283
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2284
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2285
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2286
7.52M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 324:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2287
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
2288
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2289
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2290
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2291
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2292
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2293
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2294
7.52M
        // GIR_Coverage, 3974,
2295
7.52M
        GIR_Done,
2296
7.52M
      // Label 136: @3863
2297
7.52M
      GIM_Try, /*On fail goto*//*Label 137*/ 3940, // Rule ID 3992 //
2298
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2299
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2300
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2301
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2302
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2303
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2304
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2305
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2306
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2307
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2308
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2309
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2310
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2311
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2312
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2313
7.52M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 382:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2314
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
2315
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2316
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2317
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2318
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2319
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2320
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2321
7.52M
        // GIR_Coverage, 3992,
2322
7.52M
        GIR_Done,
2323
7.52M
      // Label 137: @3940
2324
7.52M
      GIM_Try, /*On fail goto*//*Label 138*/ 4017, // Rule ID 1294 //
2325
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2326
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2327
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2328
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2329
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2330
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2331
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2332
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2333
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2334
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2335
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2336
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2337
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2338
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2339
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2340
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 324:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2341
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32,
2342
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2343
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2344
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2345
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2346
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2347
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2348
7.52M
        // GIR_Coverage, 1294,
2349
7.52M
        GIR_Done,
2350
7.52M
      // Label 138: @4017
2351
7.52M
      GIM_Try, /*On fail goto*//*Label 139*/ 4094, // Rule ID 1360 //
2352
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2353
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2354
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2355
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2356
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2357
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2358
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2359
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2360
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2361
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2362
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2363
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2364
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2365
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2366
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2367
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 382:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2368
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32,
2369
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2370
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2371
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2372
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2373
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2374
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2375
7.52M
        // GIR_Coverage, 1360,
2376
7.52M
        GIR_Done,
2377
7.52M
      // Label 139: @4094
2378
7.52M
      GIM_Try, /*On fail goto*//*Label 140*/ 4158, // Rule ID 3923 //
2379
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2380
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2381
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2382
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2383
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2384
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2385
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2386
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2387
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2388
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2389
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2390
7.52M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 324:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2391
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
2392
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2393
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2394
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2395
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2396
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2397
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2398
7.52M
        // GIR_Coverage, 3923,
2399
7.52M
        GIR_Done,
2400
7.52M
      // Label 140: @4158
2401
7.52M
      GIM_Try, /*On fail goto*//*Label 141*/ 4222, // Rule ID 3929 //
2402
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2403
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2404
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2405
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2406
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2407
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2408
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2409
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2410
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2411
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2412
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2413
7.52M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 382:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2414
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
2415
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2416
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2417
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2418
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2419
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2420
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2421
7.52M
        // GIR_Coverage, 3929,
2422
7.52M
        GIR_Done,
2423
7.52M
      // Label 141: @4222
2424
7.52M
      GIM_Try, /*On fail goto*//*Label 142*/ 4286, // Rule ID 3986 //
2425
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2426
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2427
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2428
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2429
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
2430
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2431
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2432
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2433
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2434
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2435
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2436
7.52M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 341:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2437
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
2438
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2439
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2440
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2441
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2442
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2443
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2444
7.52M
        // GIR_Coverage, 3986,
2445
7.52M
        GIR_Done,
2446
7.52M
      // Label 142: @4286
2447
7.52M
      GIM_Try, /*On fail goto*//*Label 143*/ 4350, // Rule ID 4004 //
2448
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2449
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2450
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2451
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2452
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
2453
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2454
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2455
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2456
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2457
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2458
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2459
7.52M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 395:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2460
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
2461
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2462
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2463
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2464
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2465
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2466
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2467
7.52M
        // GIR_Coverage, 4004,
2468
7.52M
        GIR_Done,
2469
7.52M
      // Label 143: @4350
2470
7.52M
      GIM_Try, /*On fail goto*//*Label 144*/ 4402, // Rule ID 3903 //
2471
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2472
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2473
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2474
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2475
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2476
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2477
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2478
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2479
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2480
7.52M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 325:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2481
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
2482
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2483
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2484
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2485
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2486
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2487
7.52M
        // GIR_Coverage, 3903,
2488
7.52M
        GIR_Done,
2489
7.52M
      // Label 144: @4402
2490
7.52M
      GIM_Try, /*On fail goto*//*Label 145*/ 4454, // Rule ID 3909 //
2491
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2492
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2493
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2494
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2495
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2496
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2497
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2498
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2499
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2500
7.52M
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 383:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2501
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32,
2502
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2503
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2504
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2505
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2506
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2507
7.52M
        // GIR_Coverage, 3909,
2508
7.52M
        GIR_Done,
2509
7.52M
      // Label 145: @4454
2510
7.52M
      GIM_Try, /*On fail goto*//*Label 146*/ 4518, // Rule ID 990 //
2511
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2512
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2513
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2514
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2515
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2516
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2517
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2518
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2519
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2520
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2521
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2522
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 324:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2523
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32,
2524
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2525
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2526
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2527
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2528
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2529
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2530
7.52M
        // GIR_Coverage, 990,
2531
7.52M
        GIR_Done,
2532
7.52M
      // Label 146: @4518
2533
7.52M
      GIM_Try, /*On fail goto*//*Label 147*/ 4582, // Rule ID 1101 //
2534
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2535
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2536
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2537
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2538
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2539
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2540
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2541
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2542
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2543
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
2544
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2545
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 382:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2546
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32,
2547
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2548
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2549
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2550
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2551
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2552
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2553
7.52M
        // GIR_Coverage, 1101,
2554
7.52M
        GIR_Done,
2555
7.52M
      // Label 147: @4582
2556
7.52M
      GIM_Try, /*On fail goto*//*Label 148*/ 4646, // Rule ID 1318 //
2557
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2558
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2559
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2560
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2561
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2562
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
2563
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2564
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2565
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2566
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2567
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2568
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 341:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2569
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32,
2570
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2571
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2572
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2573
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2574
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2575
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2576
7.52M
        // GIR_Coverage, 1318,
2577
7.52M
        GIR_Done,
2578
7.52M
      // Label 148: @4646
2579
7.52M
      GIM_Try, /*On fail goto*//*Label 149*/ 4710, // Rule ID 1378 //
2580
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2581
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2582
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2583
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2584
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2585
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
2586
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2587
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2588
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2589
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2590
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2591
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 395:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2592
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32,
2593
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2594
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2595
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2596
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2597
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2598
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2599
7.52M
        // GIR_Coverage, 1378,
2600
7.52M
        GIR_Done,
2601
7.52M
      // Label 149: @4710
2602
7.52M
      GIM_Try, /*On fail goto*//*Label 150*/ 4762, // Rule ID 714 //
2603
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2604
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2605
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2606
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2607
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2608
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
2609
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2610
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2611
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2612
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 325:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2613
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32,
2614
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2615
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2616
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2617
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2618
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2619
7.52M
        // GIR_Coverage, 714,
2620
7.52M
        GIR_Done,
2621
7.52M
      // Label 150: @4762
2622
7.52M
      GIM_Try, /*On fail goto*//*Label 151*/ 4814, // Rule ID 758 //
2623
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2624
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2625
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2626
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2627
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2628
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
2629
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2630
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2631
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2632
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 383:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
2633
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32,
2634
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2635
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2636
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2637
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2638
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2639
7.52M
        // GIR_Coverage, 758,
2640
7.52M
        GIR_Done,
2641
7.52M
      // Label 151: @4814
2642
7.52M
      GIM_Try, /*On fail goto*//*Label 152*/ 4872, // Rule ID 1306 //
2643
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2644
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2645
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2646
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2647
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2648
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2649
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2650
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2651
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2652
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2653
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2654
7.52M
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2655
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv4i16_v4i32,
2656
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2657
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2658
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
2659
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2660
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2661
7.52M
        // GIR_Coverage, 1306,
2662
7.52M
        GIR_Done,
2663
7.52M
      // Label 152: @4872
2664
7.52M
      GIM_Try, /*On fail goto*//*Label 153*/ 4930, // Rule ID 1366 //
2665
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2666
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2667
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2668
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2669
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2670
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2671
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2672
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2673
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2674
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2675
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2676
7.52M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2677
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32,
2678
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2679
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2680
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
2681
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2682
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2683
7.52M
        // GIR_Coverage, 1366,
2684
7.52M
        GIR_Done,
2685
7.52M
      // Label 153: @4930
2686
7.52M
      GIM_Try, /*On fail goto*//*Label 154*/ 4987, // Rule ID 3917 //
2687
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2688
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2689
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2690
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2691
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2692
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2693
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2694
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2695
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2696
7.52M
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (MLAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2697
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32,
2698
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2699
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2700
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2701
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2702
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2703
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2704
7.52M
        // GIR_Coverage, 3917,
2705
7.52M
        GIR_Done,
2706
7.52M
      // Label 154: @4987
2707
7.52M
      GIM_Try, /*On fail goto*//*Label 155*/ 5032, // Rule ID 3980 //
2708
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2709
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2710
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2711
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2712
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2713
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2714
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2715
7.52M
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2716
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32,
2717
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2718
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
2719
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2720
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2721
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2722
7.52M
        // GIR_Coverage, 3980,
2723
7.52M
        GIR_Done,
2724
7.52M
      // Label 155: @5032
2725
7.52M
      GIM_Try, /*On fail goto*//*Label 156*/ 5077, // Rule ID 3998 //
2726
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2727
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2728
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2729
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2730
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2731
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2732
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2733
7.52M
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2734
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32,
2735
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2736
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
2737
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2738
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2739
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2740
7.52M
        // GIR_Coverage, 3998,
2741
7.52M
        GIR_Done,
2742
7.52M
      // Label 156: @5077
2743
7.52M
      GIM_Try, /*On fail goto*//*Label 157*/ 5134, // Rule ID 970 //
2744
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2745
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2746
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2747
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2748
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2749
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2750
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2751
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2752
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2753
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (MLAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2754
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32,
2755
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2756
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2757
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2758
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2759
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2760
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2761
7.52M
        // GIR_Coverage, 970,
2762
7.52M
        GIR_Done,
2763
7.52M
      // Label 157: @5134
2764
7.52M
      GIM_Try, /*On fail goto*//*Label 158*/ 5179, // Rule ID 1312 //
2765
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2766
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2767
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2768
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2769
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2770
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2771
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2772
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2773
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32,
2774
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2775
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
2776
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2777
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2778
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2779
7.52M
        // GIR_Coverage, 1312,
2780
7.52M
        GIR_Done,
2781
7.52M
      // Label 158: @5179
2782
7.52M
      GIM_Try, /*On fail goto*//*Label 159*/ 5224, // Rule ID 1372 //
2783
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2784
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2785
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2786
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2787
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2788
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2789
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2790
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
2791
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32,
2792
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
2793
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
2794
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2795
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2796
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2797
7.52M
        // GIR_Coverage, 1372,
2798
7.52M
        GIR_Done,
2799
7.52M
      // Label 159: @5224
2800
7.52M
      GIM_Try, /*On fail goto*//*Label 160*/ 5243, // Rule ID 794 //
2801
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2802
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
2803
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2804
7.52M
        // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
2805
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i32,
2806
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2807
7.52M
        // GIR_Coverage, 794,
2808
7.52M
        GIR_Done,
2809
7.52M
      // Label 160: @5243
2810
7.52M
      GIM_Reject,
2811
7.52M
    // Label 135: @5244
2812
7.52M
    GIM_Reject,
2813
7.52M
    // Label 64: @5245
2814
7.52M
    GIM_Try, /*On fail goto*//*Label 161*/ 5649,
2815
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
2816
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
2817
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
2818
7.52M
      GIM_Try, /*On fail goto*//*Label 162*/ 5323, // Rule ID 3918 //
2819
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2820
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2821
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2822
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2823
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2824
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2825
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2826
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2827
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2828
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2829
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2830
7.52M
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 324:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2831
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
2832
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2833
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2834
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2835
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2836
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2837
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2838
7.52M
        // GIR_Coverage, 3918,
2839
7.52M
        GIR_Done,
2840
7.52M
      // Label 162: @5323
2841
7.52M
      GIM_Try, /*On fail goto*//*Label 163*/ 5387, // Rule ID 3924 //
2842
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2843
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2844
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2845
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2846
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2847
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2848
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2849
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2850
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2851
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2852
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2853
7.52M
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 382:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2854
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
2855
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2856
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2857
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2858
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2859
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2860
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2861
7.52M
        // GIR_Coverage, 3924,
2862
7.52M
        GIR_Done,
2863
7.52M
      // Label 163: @5387
2864
7.52M
      GIM_Try, /*On fail goto*//*Label 164*/ 5451, // Rule ID 985 //
2865
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2866
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2867
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2868
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2869
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2870
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2871
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2872
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2873
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2874
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2875
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2876
7.52M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 324:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2877
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8,
2878
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2879
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2880
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2881
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2882
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2883
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2884
7.52M
        // GIR_Coverage, 985,
2885
7.52M
        GIR_Done,
2886
7.52M
      // Label 164: @5451
2887
7.52M
      GIM_Try, /*On fail goto*//*Label 165*/ 5515, // Rule ID 1096 //
2888
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2889
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2890
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2891
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2892
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2893
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
2894
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2895
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2896
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2897
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2898
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2899
7.52M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 382:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2900
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8,
2901
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2902
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2903
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2904
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
2905
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2906
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2907
7.52M
        // GIR_Coverage, 1096,
2908
7.52M
        GIR_Done,
2909
7.52M
      // Label 165: @5515
2910
7.52M
      GIM_Try, /*On fail goto*//*Label 166*/ 5572, // Rule ID 3912 //
2911
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2912
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2913
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2914
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2915
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2916
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2917
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2918
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2919
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2920
7.52M
        // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (MLAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2921
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8,
2922
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2923
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2924
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2925
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2926
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2927
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2928
7.52M
        // GIR_Coverage, 3912,
2929
7.52M
        GIR_Done,
2930
7.52M
      // Label 166: @5572
2931
7.52M
      GIM_Try, /*On fail goto*//*Label 167*/ 5629, // Rule ID 965 //
2932
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2933
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2934
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2935
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2936
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2937
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2938
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2939
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2940
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2941
7.52M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (MLAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2942
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8,
2943
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2944
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
2945
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2946
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2947
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2948
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2949
7.52M
        // GIR_Coverage, 965,
2950
7.52M
        GIR_Done,
2951
7.52M
      // Label 167: @5629
2952
7.52M
      GIM_Try, /*On fail goto*//*Label 168*/ 5648, // Rule ID 789 //
2953
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2954
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
2955
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2956
7.52M
        // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2957
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i8,
2958
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2959
7.52M
        // GIR_Coverage, 789,
2960
7.52M
        GIR_Done,
2961
7.52M
      // Label 168: @5648
2962
7.52M
      GIM_Reject,
2963
7.52M
    // Label 161: @5649
2964
7.52M
    GIM_Reject,
2965
7.52M
    // Label 65: @5650
2966
7.52M
    GIM_Try, /*On fail goto*//*Label 169*/ 7122,
2967
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2968
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2969
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
2970
7.52M
      GIM_Try, /*On fail goto*//*Label 170*/ 5741, // Rule ID 3972 //
2971
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2972
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2973
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2974
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2975
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2976
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2977
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2978
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
2979
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2980
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2981
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
2982
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
2983
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
2984
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2985
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2986
7.52M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 324:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
2987
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
2988
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2989
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
2990
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
2991
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
2992
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
2993
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2994
7.52M
        // GIR_Coverage, 3972,
2995
7.52M
        GIR_Done,
2996
7.52M
      // Label 170: @5741
2997
7.52M
      GIM_Try, /*On fail goto*//*Label 171*/ 5818, // Rule ID 3990 //
2998
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
2999
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3000
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3001
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3002
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3003
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3004
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3005
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3006
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3007
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3008
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3009
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3010
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3011
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3012
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3013
7.52M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 382:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3014
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
3015
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3016
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3017
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
3018
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
3019
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3020
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3021
7.52M
        // GIR_Coverage, 3990,
3022
7.52M
        GIR_Done,
3023
7.52M
      // Label 171: @5818
3024
7.52M
      GIM_Try, /*On fail goto*//*Label 172*/ 5895, // Rule ID 1292 //
3025
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3026
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3027
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3028
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3029
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3030
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3031
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3032
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3033
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3034
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3035
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3036
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3037
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3038
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3039
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3040
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 324:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3041
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16,
3042
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3043
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3044
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
3045
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
3046
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3047
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3048
7.52M
        // GIR_Coverage, 1292,
3049
7.52M
        GIR_Done,
3050
7.52M
      // Label 172: @5895
3051
7.52M
      GIM_Try, /*On fail goto*//*Label 173*/ 5972, // Rule ID 1358 //
3052
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3053
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3054
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3055
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3056
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3057
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3058
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3059
7.52M
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3060
7.52M
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3061
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3062
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3063
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3064
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3065
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3066
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3067
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 382:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3068
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16,
3069
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3070
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3071
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
3072
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
3073
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3074
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3075
7.52M
        // GIR_Coverage, 1358,
3076
7.52M
        GIR_Done,
3077
7.52M
      // Label 173: @5972
3078
7.52M
      GIM_Try, /*On fail goto*//*Label 174*/ 6036, // Rule ID 3921 //
3079
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3080
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3081
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3082
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3083
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3084
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3085
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3086
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3087
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3088
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3089
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3090
7.52M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 324:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3091
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
3092
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3093
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3094
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3095
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3096
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3097
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3098
7.52M
        // GIR_Coverage, 3921,
3099
7.52M
        GIR_Done,
3100
7.52M
      // Label 174: @6036
3101
7.52M
      GIM_Try, /*On fail goto*//*Label 175*/ 6100, // Rule ID 3927 //
3102
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3103
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3104
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3105
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3106
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3107
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3108
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3109
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3110
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3111
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3112
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3113
7.52M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 382:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3114
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
3115
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3116
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3117
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3118
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3119
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3120
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3121
7.52M
        // GIR_Coverage, 3927,
3122
7.52M
        GIR_Done,
3123
7.52M
      // Label 175: @6100
3124
7.52M
      GIM_Try, /*On fail goto*//*Label 176*/ 6164, // Rule ID 3984 //
3125
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3126
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3127
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3128
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3129
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
3130
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3131
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3132
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3133
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3134
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3135
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3136
7.52M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 341:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3137
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
3138
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3139
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3140
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3141
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3142
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3143
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3144
7.52M
        // GIR_Coverage, 3984,
3145
7.52M
        GIR_Done,
3146
7.52M
      // Label 176: @6164
3147
7.52M
      GIM_Try, /*On fail goto*//*Label 177*/ 6228, // Rule ID 4002 //
3148
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3149
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3150
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3151
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3152
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
3153
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3154
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3155
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3156
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3157
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3158
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3159
7.52M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 395:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3160
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
3161
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3162
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3163
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3164
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3165
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3166
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3167
7.52M
        // GIR_Coverage, 4002,
3168
7.52M
        GIR_Done,
3169
7.52M
      // Label 177: @6228
3170
7.52M
      GIM_Try, /*On fail goto*//*Label 178*/ 6280, // Rule ID 3901 //
3171
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3172
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3173
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3174
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3175
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
3176
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3177
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3178
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3179
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3180
7.52M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 325:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3181
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
3182
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3183
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3184
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3185
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3186
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3187
7.52M
        // GIR_Coverage, 3901,
3188
7.52M
        GIR_Done,
3189
7.52M
      // Label 178: @6280
3190
7.52M
      GIM_Try, /*On fail goto*//*Label 179*/ 6332, // Rule ID 3907 //
3191
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3192
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3193
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3194
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3195
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
3196
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3197
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3198
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3199
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3200
7.52M
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 383:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3201
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
3202
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3203
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3204
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3205
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3206
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3207
7.52M
        // GIR_Coverage, 3907,
3208
7.52M
        GIR_Done,
3209
7.52M
      // Label 179: @6332
3210
7.52M
      GIM_Try, /*On fail goto*//*Label 180*/ 6396, // Rule ID 988 //
3211
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3212
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3213
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3214
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3215
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3216
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3217
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3218
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3219
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3220
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3221
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3222
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 324:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3223
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16,
3224
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3225
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3226
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3227
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3228
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3229
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3230
7.52M
        // GIR_Coverage, 988,
3231
7.52M
        GIR_Done,
3232
7.52M
      // Label 180: @6396
3233
7.52M
      GIM_Try, /*On fail goto*//*Label 181*/ 6460, // Rule ID 1099 //
3234
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3235
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3236
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3237
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3238
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3239
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3240
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3241
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3242
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3243
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3244
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3245
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 382:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3246
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16,
3247
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3248
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3249
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3250
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3251
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3252
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3253
7.52M
        // GIR_Coverage, 1099,
3254
7.52M
        GIR_Done,
3255
7.52M
      // Label 181: @6460
3256
7.52M
      GIM_Try, /*On fail goto*//*Label 182*/ 6524, // Rule ID 1316 //
3257
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3258
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3259
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3260
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3261
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3262
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
3263
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3264
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3265
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3266
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3267
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3268
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 341:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3269
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16,
3270
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3271
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3272
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3273
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3274
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3275
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3276
7.52M
        // GIR_Coverage, 1316,
3277
7.52M
        GIR_Done,
3278
7.52M
      // Label 182: @6524
3279
7.52M
      GIM_Try, /*On fail goto*//*Label 183*/ 6588, // Rule ID 1376 //
3280
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3281
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3282
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3283
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3284
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3285
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
3286
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3287
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3288
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
3289
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
3290
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3291
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 395:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3292
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16,
3293
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3294
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3295
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3296
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3297
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3298
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3299
7.52M
        // GIR_Coverage, 1376,
3300
7.52M
        GIR_Done,
3301
7.52M
      // Label 183: @6588
3302
7.52M
      GIM_Try, /*On fail goto*//*Label 184*/ 6640, // Rule ID 712 //
3303
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3304
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3305
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3306
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3307
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3308
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp,
3309
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3310
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3311
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3312
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 325:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3313
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16,
3314
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3315
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3316
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3317
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3318
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3319
7.52M
        // GIR_Coverage, 712,
3320
7.52M
        GIR_Done,
3321
7.52M
      // Label 184: @6640
3322
7.52M
      GIM_Try, /*On fail goto*//*Label 185*/ 6692, // Rule ID 756 //
3323
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3324
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3325
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3326
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3327
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3328
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp,
3329
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3330
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3331
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3332
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 383:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
3333
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16,
3334
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3335
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3336
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3337
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3338
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3339
7.52M
        // GIR_Coverage, 756,
3340
7.52M
        GIR_Done,
3341
7.52M
      // Label 185: @6692
3342
7.52M
      GIM_Try, /*On fail goto*//*Label 186*/ 6750, // Rule ID 1304 //
3343
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3344
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3345
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3346
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3347
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3348
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3349
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3350
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3351
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3352
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3353
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3354
7.52M
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3355
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv8i8_v8i16,
3356
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3357
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3358
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3359
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3360
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3361
7.52M
        // GIR_Coverage, 1304,
3362
7.52M
        GIR_Done,
3363
7.52M
      // Label 186: @6750
3364
7.52M
      GIM_Try, /*On fail goto*//*Label 187*/ 6808, // Rule ID 1364 //
3365
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3366
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3367
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3368
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3369
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3370
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3371
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3372
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3373
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3374
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3375
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3376
7.52M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3377
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16,
3378
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3379
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3380
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3381
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3382
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3383
7.52M
        // GIR_Coverage, 1364,
3384
7.52M
        GIR_Done,
3385
7.52M
      // Label 187: @6808
3386
7.52M
      GIM_Try, /*On fail goto*//*Label 188*/ 6865, // Rule ID 3915 //
3387
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3388
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3389
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3390
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3391
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3392
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3393
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3394
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3395
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3396
7.52M
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (MLAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3397
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16,
3398
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3399
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3400
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3401
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3402
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3403
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3404
7.52M
        // GIR_Coverage, 3915,
3405
7.52M
        GIR_Done,
3406
7.52M
      // Label 188: @6865
3407
7.52M
      GIM_Try, /*On fail goto*//*Label 189*/ 6910, // Rule ID 3978 //
3408
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3409
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3410
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3411
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3412
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3413
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3414
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3415
7.52M
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3416
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16,
3417
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3418
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3419
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3420
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3421
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3422
7.52M
        // GIR_Coverage, 3978,
3423
7.52M
        GIR_Done,
3424
7.52M
      // Label 189: @6910
3425
7.52M
      GIM_Try, /*On fail goto*//*Label 190*/ 6955, // Rule ID 3996 //
3426
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3427
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3428
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3429
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3430
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3431
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3432
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3433
7.52M
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3434
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16,
3435
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3436
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3437
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3438
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3439
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3440
7.52M
        // GIR_Coverage, 3996,
3441
7.52M
        GIR_Done,
3442
7.52M
      // Label 190: @6955
3443
7.52M
      GIM_Try, /*On fail goto*//*Label 191*/ 7012, // Rule ID 968 //
3444
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3445
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3446
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3447
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3448
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3449
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3450
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3451
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3452
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3453
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (MLAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3454
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16,
3455
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3456
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3457
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3458
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3459
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3460
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3461
7.52M
        // GIR_Coverage, 968,
3462
7.52M
        GIR_Done,
3463
7.52M
      // Label 191: @7012
3464
7.52M
      GIM_Try, /*On fail goto*//*Label 192*/ 7057, // Rule ID 1310 //
3465
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3466
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3467
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3468
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3469
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3470
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3471
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3472
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3473
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16,
3474
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3475
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3476
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3477
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3478
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3479
7.52M
        // GIR_Coverage, 1310,
3480
7.52M
        GIR_Done,
3481
7.52M
      // Label 192: @7057
3482
7.52M
      GIM_Try, /*On fail goto*//*Label 193*/ 7102, // Rule ID 1370 //
3483
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3484
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3485
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3486
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3487
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3488
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
3489
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3490
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
3491
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16,
3492
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3493
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3494
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
3495
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3496
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3497
7.52M
        // GIR_Coverage, 1370,
3498
7.52M
        GIR_Done,
3499
7.52M
      // Label 193: @7102
3500
7.52M
      GIM_Try, /*On fail goto*//*Label 194*/ 7121, // Rule ID 792 //
3501
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3502
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3503
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3504
7.52M
        // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
3505
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i16,
3506
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3507
7.52M
        // GIR_Coverage, 792,
3508
7.52M
        GIR_Done,
3509
7.52M
      // Label 194: @7121
3510
7.52M
      GIM_Reject,
3511
7.52M
    // Label 169: @7122
3512
7.52M
    GIM_Reject,
3513
7.52M
    // Label 66: @7123
3514
7.52M
    GIM_Try, /*On fail goto*//*Label 195*/ 7527,
3515
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3516
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3517
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
3518
7.52M
      GIM_Try, /*On fail goto*//*Label 196*/ 7201, // Rule ID 3919 //
3519
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3520
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3521
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3522
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3523
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3524
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3525
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3526
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3527
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3528
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3529
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3530
7.52M
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 324:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3531
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
3532
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3533
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3534
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3535
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3536
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3537
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3538
7.52M
        // GIR_Coverage, 3919,
3539
7.52M
        GIR_Done,
3540
7.52M
      // Label 196: @7201
3541
7.52M
      GIM_Try, /*On fail goto*//*Label 197*/ 7265, // Rule ID 3925 //
3542
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3543
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3544
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3545
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3546
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3547
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3548
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3549
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3550
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3551
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3552
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3553
7.52M
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 382:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3554
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
3555
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3556
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3557
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3558
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3559
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3560
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3561
7.52M
        // GIR_Coverage, 3925,
3562
7.52M
        GIR_Done,
3563
7.52M
      // Label 197: @7265
3564
7.52M
      GIM_Try, /*On fail goto*//*Label 198*/ 7329, // Rule ID 986 //
3565
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3566
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3567
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3568
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3569
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3570
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd,
3571
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3572
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3573
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3574
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3575
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3576
7.52M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 324:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3577
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8,
3578
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3579
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3580
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3581
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3582
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3583
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3584
7.52M
        // GIR_Coverage, 986,
3585
7.52M
        GIR_Done,
3586
7.52M
      // Label 198: @7329
3587
7.52M
      GIM_Try, /*On fail goto*//*Label 199*/ 7393, // Rule ID 1097 //
3588
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3589
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3590
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3591
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3592
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3593
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd,
3594
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3595
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3596
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3597
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID,
3598
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3599
7.52M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 382:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3600
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8,
3601
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3602
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3603
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3604
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3605
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3606
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3607
7.52M
        // GIR_Coverage, 1097,
3608
7.52M
        GIR_Done,
3609
7.52M
      // Label 199: @7393
3610
7.52M
      GIM_Try, /*On fail goto*//*Label 200*/ 7450, // Rule ID 3913 //
3611
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3612
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3613
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3614
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3615
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3616
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3617
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3618
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3619
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3620
7.52M
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (MLAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3621
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8,
3622
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3623
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd
3624
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3625
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3626
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3627
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3628
7.52M
        // GIR_Coverage, 3913,
3629
7.52M
        GIR_Done,
3630
7.52M
      // Label 200: @7450
3631
7.52M
      GIM_Try, /*On fail goto*//*Label 201*/ 7507, // Rule ID 966 //
3632
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3633
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3634
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3635
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3636
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3637
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3638
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3639
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3640
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3641
7.52M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (MLAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3642
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8,
3643
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3644
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
3645
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3646
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3647
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3648
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3649
7.52M
        // GIR_Coverage, 966,
3650
7.52M
        GIR_Done,
3651
7.52M
      // Label 201: @7507
3652
7.52M
      GIM_Try, /*On fail goto*//*Label 202*/ 7526, // Rule ID 790 //
3653
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
3654
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
3655
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
3656
7.52M
        // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
3657
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv16i8,
3658
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3659
7.52M
        // GIR_Coverage, 790,
3660
7.52M
        GIR_Done,
3661
7.52M
      // Label 202: @7526
3662
7.52M
      GIM_Reject,
3663
7.52M
    // Label 195: @7527
3664
7.52M
    GIM_Reject,
3665
7.52M
    // Label 67: @7528
3666
7.52M
    GIM_Reject,
3667
7.52M
    // Label 1: @7529
3668
7.52M
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 212*/ 10109,
3669
7.52M
    /*GILLT_s32*//*Label 203*/ 7545,
3670
7.52M
    /*GILLT_s64*//*Label 204*/ 7665, 0,
3671
7.52M
    /*GILLT_v2s32*//*Label 205*/ 8536,
3672
7.52M
    /*GILLT_v2s64*//*Label 206*/ 8624,
3673
7.52M
    /*GILLT_v4s16*//*Label 207*/ 8993,
3674
7.52M
    /*GILLT_v4s32*//*Label 208*/ 9081,
3675
7.52M
    /*GILLT_v8s8*//*Label 209*/ 9507,
3676
7.52M
    /*GILLT_v8s16*//*Label 210*/ 9595,
3677
7.52M
    /*GILLT_v16s8*//*Label 211*/ 10021,
3678
7.52M
    // Label 203: @7545
3679
7.52M
    GIM_Try, /*On fail goto*//*Label 213*/ 7664,
3680
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3681
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3682
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
3683
7.52M
      GIM_Try, /*On fail goto*//*Label 214*/ 7613, // Rule ID 1908 //
3684
7.52M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3685
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3686
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3687
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3688
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3689
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3690
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
3691
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3692
7.52M
        // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
3693
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr,
3694
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3695
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3696
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3697
7.52M
        GIR_AddRegister, /*InsnID*/0, AArch64::WZR,
3698
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3699
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3700
7.52M
        // GIR_Coverage, 1908,
3701
7.52M
        GIR_Done,
3702
7.52M
      // Label 214: @7613
3703
7.52M
      GIM_Try, /*On fail goto*//*Label 215*/ 7643, // Rule ID 1868 //
3704
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
3705
7.52M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
3706
7.52M
        // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
3707
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri,
3708
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3709
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3710
7.52M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
3711
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3712
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3713
7.52M
        // GIR_Coverage, 1868,
3714
7.52M
        GIR_Done,
3715
7.52M
      // Label 215: @7643
3716
7.52M
      GIM_Try, /*On fail goto*//*Label 216*/ 7663, // Rule ID 1870 //
3717
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3718
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
3719
7.52M
        // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SUBSWrr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
3720
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSWrr,
3721
7.52M
        GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV,
3722
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3723
7.52M
        // GIR_Coverage, 1870,
3724
7.52M
        GIR_Done,
3725
7.52M
      // Label 216: @7663
3726
7.52M
      GIM_Reject,
3727
7.52M
    // Label 213: @7664
3728
7.52M
    GIM_Reject,
3729
7.52M
    // Label 204: @7665
3730
7.52M
    GIM_Try, /*On fail goto*//*Label 217*/ 8535,
3731
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3732
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3733
7.52M
      GIM_Try, /*On fail goto*//*Label 218*/ 7770, // Rule ID 1919 //
3734
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3735
7.52M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3736
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3737
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3738
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3739
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3740
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3741
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3742
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3743
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3744
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3745
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3746
7.52M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
3747
7.52M
        // MIs[3] Operand 1
3748
7.52M
        // No operand predicates
3749
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3750
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3751
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3752
7.52M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
3753
7.52M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3754
7.52M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3755
7.52M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3756
7.52M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3757
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3758
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3759
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3760
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3761
7.52M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3762
7.52M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3763
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3764
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3765
7.52M
        // GIR_Coverage, 1919,
3766
7.52M
        GIR_Done,
3767
7.52M
      // Label 218: @7770
3768
7.52M
      GIM_Try, /*On fail goto*//*Label 219*/ 7865, // Rule ID 1920 //
3769
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3770
7.52M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3771
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3772
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3773
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3774
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3775
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3776
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3777
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3778
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3779
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3780
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3781
7.52M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
3782
7.52M
        // MIs[3] Operand 1
3783
7.52M
        // No operand predicates
3784
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3785
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3786
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3787
7.52M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
3788
7.52M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3789
7.52M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3790
7.52M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3791
7.52M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3792
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3793
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3794
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3795
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3796
7.52M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3797
7.52M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3798
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3799
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3800
7.52M
        // GIR_Coverage, 1920,
3801
7.52M
        GIR_Done,
3802
7.52M
      // Label 219: @7865
3803
7.52M
      GIM_Try, /*On fail goto*//*Label 220*/ 7949, // Rule ID 1914 //
3804
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3805
7.52M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3806
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3807
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3808
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3809
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3810
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3811
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3812
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3813
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3814
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3815
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
3816
7.52M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3817
7.52M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3818
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3819
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3820
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3821
7.52M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
3822
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3823
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3824
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3825
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3826
7.52M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3827
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3828
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3829
7.52M
        // GIR_Coverage, 1914,
3830
7.52M
        GIR_Done,
3831
7.52M
      // Label 220: @7949
3832
7.52M
      GIM_Try, /*On fail goto*//*Label 221*/ 8033, // Rule ID 1915 //
3833
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3834
7.52M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3835
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3836
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3837
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3838
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3839
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3840
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3841
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3842
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3843
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3844
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
3845
7.52M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3846
7.52M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3847
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3848
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3849
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3850
7.52M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
3851
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3852
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3853
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3854
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3855
7.52M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
3856
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3857
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3858
7.52M
        // GIR_Coverage, 1915,
3859
7.52M
        GIR_Done,
3860
7.52M
      // Label 221: @8033
3861
7.52M
      GIM_Try, /*On fail goto*//*Label 222*/ 8129, // Rule ID 1925 //
3862
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3863
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3864
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3865
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3866
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3867
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3868
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3869
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3870
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3871
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3872
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3873
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3874
7.52M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit,
3875
7.52M
        // MIs[3] Operand 1
3876
7.52M
        // No operand predicates
3877
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3878
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3879
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3880
7.52M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
3881
7.52M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3882
7.52M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3883
7.52M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3884
7.52M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3885
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3886
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3887
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3888
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3889
7.52M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3890
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3891
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3892
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3893
7.52M
        // GIR_Coverage, 1925,
3894
7.52M
        GIR_Done,
3895
7.52M
      // Label 222: @8129
3896
7.52M
      GIM_Try, /*On fail goto*//*Label 223*/ 8225, // Rule ID 1926 //
3897
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3898
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3899
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3900
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3901
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3902
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3903
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3904
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3905
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3906
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3907
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3908
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
3909
7.52M
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit,
3910
7.52M
        // MIs[3] Operand 1
3911
7.52M
        // No operand predicates
3912
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3913
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3914
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3915
7.52M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
3916
7.52M
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
3917
7.52M
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm,
3918
7.52M
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3919
7.52M
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C
3920
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3921
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3922
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3923
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3924
7.52M
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3925
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3926
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3927
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3928
7.52M
        // GIR_Coverage, 1926,
3929
7.52M
        GIR_Done,
3930
7.52M
      // Label 223: @8225
3931
7.52M
      GIM_Try, /*On fail goto*//*Label 224*/ 8310, // Rule ID 84 //
3932
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3933
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3934
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3935
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3936
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3937
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3938
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3939
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3940
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3941
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3942
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3943
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
3944
7.52M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3945
7.52M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3946
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3947
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3948
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3949
7.52M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
3950
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr,
3951
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3952
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3953
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3954
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3955
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3956
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3957
7.52M
        // GIR_Coverage, 84,
3958
7.52M
        GIR_Done,
3959
7.52M
      // Label 224: @8310
3960
7.52M
      GIM_Try, /*On fail goto*//*Label 225*/ 8395, // Rule ID 86 //
3961
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3962
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3963
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3964
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3965
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3966
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3967
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3968
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3969
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3970
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3971
7.52M
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
3972
7.52M
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
3973
7.52M
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
3974
7.52M
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
3975
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3976
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3977
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/3,
3978
7.52M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
3979
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr,
3980
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3981
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
3982
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
3983
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3984
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
3985
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3986
7.52M
        // GIR_Coverage, 86,
3987
7.52M
        GIR_Done,
3988
7.52M
      // Label 225: @8395
3989
7.52M
      GIM_Try, /*On fail goto*//*Label 226*/ 8453, // Rule ID 1909 //
3990
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
3991
7.52M
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
3992
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3993
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3994
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3995
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3996
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
3997
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
3998
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3999
7.52M
        // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
4000
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr,
4001
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4002
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4003
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4004
7.52M
        GIR_AddRegister, /*InsnID*/0, AArch64::XZR,
4005
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4006
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4007
7.52M
        // GIR_Coverage, 1909,
4008
7.52M
        GIR_Done,
4009
7.52M
      // Label 226: @8453
4010
7.52M
      GIM_Try, /*On fail goto*//*Label 227*/ 8487, // Rule ID 1869 //
4011
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
4012
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID,
4013
7.52M
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64,
4014
7.52M
        // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
4015
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri,
4016
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4017
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4018
7.52M
        GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
4019
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4020
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4021
7.52M
        // GIR_Coverage, 1869,
4022
7.52M
        GIR_Done,
4023
7.52M
      // Label 227: @8487
4024
7.52M
      GIM_Try, /*On fail goto*//*Label 228*/ 8510, // Rule ID 1251 //
4025
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4026
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4027
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4028
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4029
7.52M
        // (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
4030
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv1i64,
4031
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4032
7.52M
        // GIR_Coverage, 1251,
4033
7.52M
        GIR_Done,
4034
7.52M
      // Label 228: @8510
4035
7.52M
      GIM_Try, /*On fail goto*//*Label 229*/ 8534, // Rule ID 1871 //
4036
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID,
4037
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID,
4038
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID,
4039
7.52M
        // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SUBSXrr:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
4040
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSXrr,
4041
7.52M
        GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV,
4042
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4043
7.52M
        // GIR_Coverage, 1871,
4044
7.52M
        GIR_Done,
4045
7.52M
      // Label 229: @8534
4046
7.52M
      GIM_Reject,
4047
7.52M
    // Label 217: @8535
4048
7.52M
    GIM_Reject,
4049
7.52M
    // Label 205: @8536
4050
7.52M
    GIM_Try, /*On fail goto*//*Label 230*/ 8623,
4051
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
4052
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
4053
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4054
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4055
7.52M
      GIM_Try, /*On fail goto*//*Label 231*/ 8607, // Rule ID 975 //
4056
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4057
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4058
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4059
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4060
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4061
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4062
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4063
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4064
7.52M
        // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (MLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4065
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv2i32,
4066
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4067
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4068
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4069
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4070
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4071
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4072
7.52M
        // GIR_Coverage, 975,
4073
7.52M
        GIR_Done,
4074
7.52M
      // Label 231: @8607
4075
7.52M
      GIM_Try, /*On fail goto*//*Label 232*/ 8622, // Rule ID 1093 //
4076
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4077
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4078
7.52M
        // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4079
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i32,
4080
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4081
7.52M
        // GIR_Coverage, 1093,
4082
7.52M
        GIR_Done,
4083
7.52M
      // Label 232: @8622
4084
7.52M
      GIM_Reject,
4085
7.52M
    // Label 230: @8623
4086
7.52M
    GIM_Reject,
4087
7.52M
    // Label 206: @8624
4088
7.52M
    GIM_Try, /*On fail goto*//*Label 233*/ 8992,
4089
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4090
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4091
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4092
7.52M
      GIM_Try, /*On fail goto*//*Label 234*/ 8702, // Rule ID 1326 //
4093
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4094
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4095
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4096
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4097
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4098
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4099
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4100
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
4101
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4102
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4103
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4104
7.52M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 341:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4105
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv2i32_v2i64,
4106
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4107
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4108
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4109
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4110
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4111
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4112
7.52M
        // GIR_Coverage, 1326,
4113
7.52M
        GIR_Done,
4114
7.52M
      // Label 234: @8702
4115
7.52M
      GIM_Try, /*On fail goto*//*Label 235*/ 8766, // Rule ID 1386 //
4116
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4117
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4118
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4119
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4120
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4121
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4122
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4123
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
4124
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4125
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4126
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4127
7.52M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 395:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4128
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv2i32_v2i64,
4129
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4130
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4131
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4132
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4133
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4134
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4135
7.52M
        // GIR_Coverage, 1386,
4136
7.52M
        GIR_Done,
4137
7.52M
      // Label 235: @8766
4138
7.52M
      GIM_Try, /*On fail goto*//*Label 236*/ 8824, // Rule ID 1350 //
4139
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4140
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4141
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4142
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4143
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4144
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4145
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4146
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4147
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4148
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4149
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4150
7.52M
        // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4151
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv2i32_v2i64,
4152
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4153
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4154
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4155
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4156
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4157
7.52M
        // GIR_Coverage, 1350,
4158
7.52M
        GIR_Done,
4159
7.52M
      // Label 236: @8824
4160
7.52M
      GIM_Try, /*On fail goto*//*Label 237*/ 8882, // Rule ID 1398 //
4161
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4162
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4163
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4164
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4165
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4166
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4167
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4168
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4169
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4170
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4171
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4172
7.52M
        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4173
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64,
4174
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4175
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4176
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4177
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4178
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4179
7.52M
        // GIR_Coverage, 1398,
4180
7.52M
        GIR_Done,
4181
7.52M
      // Label 237: @8882
4182
7.52M
      GIM_Try, /*On fail goto*//*Label 238*/ 8927, // Rule ID 1356 //
4183
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4184
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4185
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4186
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4187
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4188
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4189
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4190
7.52M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4191
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv2i32_v2i64,
4192
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4193
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4194
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4195
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4196
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4197
7.52M
        // GIR_Coverage, 1356,
4198
7.52M
        GIR_Done,
4199
7.52M
      // Label 238: @8927
4200
7.52M
      GIM_Try, /*On fail goto*//*Label 239*/ 8972, // Rule ID 1404 //
4201
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4202
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4203
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4204
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4205
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4206
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4207
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4208
7.52M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4209
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv2i32_v2i64,
4210
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4211
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4212
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4213
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4214
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4215
7.52M
        // GIR_Coverage, 1404,
4216
7.52M
        GIR_Done,
4217
7.52M
      // Label 239: @8972
4218
7.52M
      GIM_Try, /*On fail goto*//*Label 240*/ 8991, // Rule ID 1095 //
4219
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4220
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4221
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4222
7.52M
        // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
4223
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i64,
4224
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4225
7.52M
        // GIR_Coverage, 1095,
4226
7.52M
        GIR_Done,
4227
7.52M
      // Label 240: @8991
4228
7.52M
      GIM_Reject,
4229
7.52M
    // Label 233: @8992
4230
7.52M
    GIM_Reject,
4231
7.52M
    // Label 207: @8993
4232
7.52M
    GIM_Try, /*On fail goto*//*Label 241*/ 9080,
4233
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4234
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4235
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4236
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4237
7.52M
      GIM_Try, /*On fail goto*//*Label 242*/ 9064, // Rule ID 973 //
4238
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4239
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4240
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4241
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4242
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4243
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4244
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4245
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4246
7.52M
        // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (MLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4247
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i16,
4248
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4249
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4250
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4251
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4252
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4253
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4254
7.52M
        // GIR_Coverage, 973,
4255
7.52M
        GIR_Done,
4256
7.52M
      // Label 242: @9064
4257
7.52M
      GIM_Try, /*On fail goto*//*Label 243*/ 9079, // Rule ID 1091 //
4258
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4259
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4260
7.52M
        // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4261
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i16,
4262
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4263
7.52M
        // GIR_Coverage, 1091,
4264
7.52M
        GIR_Done,
4265
7.52M
      // Label 243: @9079
4266
7.52M
      GIM_Reject,
4267
7.52M
    // Label 241: @9080
4268
7.52M
    GIM_Reject,
4269
7.52M
    // Label 208: @9081
4270
7.52M
    GIM_Try, /*On fail goto*//*Label 244*/ 9506,
4271
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4272
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4273
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4274
7.52M
      GIM_Try, /*On fail goto*//*Label 245*/ 9159, // Rule ID 1324 //
4275
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4276
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4277
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4278
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4279
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4280
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4281
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4282
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4283
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4284
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4285
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4286
7.52M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 341:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4287
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv4i16_v4i32,
4288
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4289
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4290
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4291
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4292
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4293
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4294
7.52M
        // GIR_Coverage, 1324,
4295
7.52M
        GIR_Done,
4296
7.52M
      // Label 245: @9159
4297
7.52M
      GIM_Try, /*On fail goto*//*Label 246*/ 9223, // Rule ID 1384 //
4298
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4299
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4300
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4301
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4302
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4303
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4304
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4305
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4306
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4307
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4308
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4309
7.52M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 395:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4310
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv4i16_v4i32,
4311
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4312
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4313
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4314
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4315
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4316
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4317
7.52M
        // GIR_Coverage, 1384,
4318
7.52M
        GIR_Done,
4319
7.52M
      // Label 246: @9223
4320
7.52M
      GIM_Try, /*On fail goto*//*Label 247*/ 9281, // Rule ID 1348 //
4321
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4322
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4323
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4324
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4325
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4326
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4327
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4328
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4329
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4330
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4331
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4332
7.52M
        // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4333
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv4i16_v4i32,
4334
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4335
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4336
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4337
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4338
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4339
7.52M
        // GIR_Coverage, 1348,
4340
7.52M
        GIR_Done,
4341
7.52M
      // Label 247: @9281
4342
7.52M
      GIM_Try, /*On fail goto*//*Label 248*/ 9339, // Rule ID 1396 //
4343
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4344
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4345
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4346
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4347
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4348
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4349
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4350
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4351
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4352
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4353
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4354
7.52M
        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4355
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32,
4356
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4357
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4358
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4359
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4360
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4361
7.52M
        // GIR_Coverage, 1396,
4362
7.52M
        GIR_Done,
4363
7.52M
      // Label 248: @9339
4364
7.52M
      GIM_Try, /*On fail goto*//*Label 249*/ 9396, // Rule ID 976 //
4365
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4366
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4367
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4368
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4369
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4370
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4371
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4372
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4373
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4374
7.52M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (MLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4375
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i32,
4376
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4377
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4378
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4379
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4380
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4381
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4382
7.52M
        // GIR_Coverage, 976,
4383
7.52M
        GIR_Done,
4384
7.52M
      // Label 249: @9396
4385
7.52M
      GIM_Try, /*On fail goto*//*Label 250*/ 9441, // Rule ID 1354 //
4386
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4387
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4388
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4389
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4390
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4391
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4392
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4393
7.52M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4394
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv4i16_v4i32,
4395
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4396
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4397
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4398
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4399
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4400
7.52M
        // GIR_Coverage, 1354,
4401
7.52M
        GIR_Done,
4402
7.52M
      // Label 250: @9441
4403
7.52M
      GIM_Try, /*On fail goto*//*Label 251*/ 9486, // Rule ID 1402 //
4404
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4405
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4406
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4407
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4408
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4409
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4410
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4411
7.52M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4412
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv4i16_v4i32,
4413
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4414
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4415
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4416
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4417
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4418
7.52M
        // GIR_Coverage, 1402,
4419
7.52M
        GIR_Done,
4420
7.52M
      // Label 251: @9486
4421
7.52M
      GIM_Try, /*On fail goto*//*Label 252*/ 9505, // Rule ID 1094 //
4422
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4423
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4424
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4425
7.52M
        // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4426
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i32,
4427
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4428
7.52M
        // GIR_Coverage, 1094,
4429
7.52M
        GIR_Done,
4430
7.52M
      // Label 252: @9505
4431
7.52M
      GIM_Reject,
4432
7.52M
    // Label 244: @9506
4433
7.52M
    GIM_Reject,
4434
7.52M
    // Label 209: @9507
4435
7.52M
    GIM_Try, /*On fail goto*//*Label 253*/ 9594,
4436
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4437
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4438
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID,
4439
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4440
7.52M
      GIM_Try, /*On fail goto*//*Label 254*/ 9578, // Rule ID 971 //
4441
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4442
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4443
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4444
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4445
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4446
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4447
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4448
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4449
7.52M
        // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (MLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4450
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i8,
4451
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4452
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4453
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4454
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4455
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4456
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4457
7.52M
        // GIR_Coverage, 971,
4458
7.52M
        GIR_Done,
4459
7.52M
      // Label 254: @9578
4460
7.52M
      GIM_Try, /*On fail goto*//*Label 255*/ 9593, // Rule ID 1089 //
4461
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4462
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4463
7.52M
        // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4464
7.52M
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i8,
4465
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4466
7.52M
        // GIR_Coverage, 1089,
4467
7.52M
        GIR_Done,
4468
7.52M
      // Label 255: @9593
4469
7.52M
      GIM_Reject,
4470
7.52M
    // Label 253: @9594
4471
7.52M
    GIM_Reject,
4472
7.52M
    // Label 210: @9595
4473
7.52M
    GIM_Try, /*On fail goto*//*Label 256*/ 10020,
4474
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4475
7.52M
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4476
7.52M
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID,
4477
7.52M
      GIM_Try, /*On fail goto*//*Label 257*/ 9673, // Rule ID 1322 //
4478
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4479
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4480
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4481
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4482
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4483
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull,
4484
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4485
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
4486
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4487
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4488
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4489
7.52M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 341:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4490
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv8i8_v8i16,
4491
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4492
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4493
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4494
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4495
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4496
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4497
7.52M
        // GIR_Coverage, 1322,
4498
7.52M
        GIR_Done,
4499
7.52M
      // Label 257: @9673
4500
7.52M
      GIM_Try, /*On fail goto*//*Label 258*/ 9737, // Rule ID 1382 //
4501
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4502
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4503
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4504
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
4505
7.52M
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4506
7.52M
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull,
4507
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4508
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
4509
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID,
4510
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID,
4511
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4512
7.52M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 395:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4513
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv8i8_v8i16,
4514
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4515
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4516
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4517
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4518
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4519
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4520
7.52M
        // GIR_Coverage, 1382,
4521
7.52M
        GIR_Done,
4522
7.52M
      // Label 258: @9737
4523
7.52M
      GIM_Try, /*On fail goto*//*Label 259*/ 9795, // Rule ID 1346 //
4524
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4525
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4526
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4527
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4528
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4529
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4530
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4531
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4532
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4533
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4534
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4535
7.52M
        // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4536
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv8i8_v8i16,
4537
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4538
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4539
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4540
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4541
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4542
7.52M
        // GIR_Coverage, 1346,
4543
7.52M
        GIR_Done,
4544
7.52M
      // Label 259: @9795
4545
7.52M
      GIM_Try, /*On fail goto*//*Label 260*/ 9853, // Rule ID 1394 //
4546
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4547
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4548
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4549
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4550
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4551
7.52M
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4552
7.52M
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4553
7.52M
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4554
7.52M
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4555
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4556
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4557
7.52M
        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4558
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16,
4559
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4560
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4561
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4562
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4563
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4564
7.52M
        // GIR_Coverage, 1394,
4565
7.52M
        GIR_Done,
4566
7.52M
      // Label 260: @9853
4567
7.52M
      GIM_Try, /*On fail goto*//*Label 261*/ 9910, // Rule ID 974 //
4568
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4569
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4570
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4571
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4572
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4573
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4574
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4575
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID,
4576
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4577
7.52M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (MLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
4578
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i16,
4579
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4580
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd
4581
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4582
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4583
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4584
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4585
7.52M
        // GIR_Coverage, 974,
4586
7.52M
        GIR_Done,
4587
7.52M
      // Label 261: @9910
4588
7.52M
      GIM_Try, /*On fail goto*//*Label 262*/ 9955, // Rule ID 1352 //
4589
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4590
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4591
7.52M
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4592
7.52M
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4593
7.52M
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4594
7.52M
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID,
4595
7.52M
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4596
7.52M
        // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
4597
7.52M
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv8i8_v8i16,
4598
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4599
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4600
7.52M
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4601
7.52M
        GIR_EraseFromParent, /*InsnID*/0,
4602
7.52M
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4603
7.52M
        // GIR_Coverage, 1352,
4604
7.52M
        GIR_Done,
4605
7.52M
      // Label 262: @9955
4606
7.52M
      GIM_Try, /*On fail goto*//*Label 263*/ 10000, // Rule ID 1400 //
4607
7.52M
        GIM_CheckFeatures, GIFBS_HasNEON,
4608
7.52M
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID,
4609