Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AArch64/AArch64GenRegisterBank.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Register Bank Source Fragments                                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGBANK_DECLARATIONS
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#undef GET_REGBANK_DECLARATIONS
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namespace llvm {
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namespace AArch64 {
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enum {
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  CCRegBankID,
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  FPRRegBankID,
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  GPRRegBankID,
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  NumRegisterBanks,
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};
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} // end namespace AArch64
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} // end namespace llvm
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#endif // GET_REGBANK_DECLARATIONS
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#ifdef GET_TARGET_REGBANK_CLASS
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#undef GET_TARGET_REGBANK_CLASS
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private:
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  static RegisterBank *RegBanks[];
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protected:
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  AArch64GenRegisterBankInfo();
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#endif // GET_TARGET_REGBANK_CLASS
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#ifdef GET_TARGET_REGBANK_IMPL
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#undef GET_TARGET_REGBANK_IMPL
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namespace llvm {
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namespace AArch64 {
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const uint32_t CCRegBankCoverageData[] = {
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    // 0-31
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    (1u << (AArch64::CCRRegClassID - 0)) |
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    0,
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    // 32-63
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    0,
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    // 64-95
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    0,
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    // 96-127
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    0,
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};
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const uint32_t FPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (AArch64::FPR8RegClassID - 0)) |
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    (1u << (AArch64::FPR16RegClassID - 0)) |
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    (1u << (AArch64::FPR32RegClassID - 0)) |
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    (1u << (AArch64::FPR64RegClassID - 0)) |
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    (1u << (AArch64::DDRegClassID - 0)) |
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    (1u << (AArch64::FPR128RegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (AArch64::DDDRegClassID - 32)) |
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    (1u << (AArch64::DDDDRegClassID - 32)) |
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    (1u << (AArch64::QQRegClassID - 32)) |
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    (1u << (AArch64::QQQRegClassID - 32)) |
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    (1u << (AArch64::FPR128_loRegClassID - 32)) |
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    (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
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    (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
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    (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
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    (1u << (AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
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    (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
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    (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
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    (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
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    (1u << (AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
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    (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
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    0,
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    // 64-95
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    (1u << (AArch64::QQQQRegClassID - 64)) |
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    (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 64)) |
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    (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID - 64)) |
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    (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
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    (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) |
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    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 64)) |
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    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
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    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) |
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    (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
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    (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) |
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    (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) |
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    0,
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    // 96-127
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    0,
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};
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const uint32_t GPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (AArch64::GPR64allRegClassID - 0)) |
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    (1u << (AArch64::GPR32allRegClassID - 0)) |
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    (1u << (AArch64::GPR64RegClassID - 0)) |
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    (1u << (AArch64::GPR32RegClassID - 0)) |
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    (1u << (AArch64::GPR64commonRegClassID - 0)) |
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    (1u << (AArch64::GPR32spRegClassID - 0)) |
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    (1u << (AArch64::GPR32commonRegClassID - 0)) |
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    (1u << (AArch64::tcGPR64RegClassID - 0)) |
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    (1u << (AArch64::GPR64spRegClassID - 0)) |
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    (1u << (AArch64::GPR64sponlyRegClassID - 0)) |
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    (1u << (AArch64::GPR32sponlyRegClassID - 0)) |
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    0,
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    // 32-63
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    0,
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    // 64-95
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    0,
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    // 96-127
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    0,
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};
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RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* Size */ 32, /* CoveredRegClasses */ CCRegBankCoverageData, /* NumRegClasses */ 100);
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RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* Size */ 512, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 100);
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RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 100);
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} // end namespace AArch64
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RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
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    &AArch64::CCRegBank,
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    &AArch64::FPRRegBank,
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    &AArch64::GPRRegBank,
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};
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AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo()
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8.43k
    : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks) {
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8.43k
  // Assert that RegBank indices match their ID's
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#ifndef NDEBUG
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  unsigned Index = 0;
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  for (const auto &RB : RegBanks)
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    assert(Index++ == RB->getID() && "Index != ID");
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#endif // NDEBUG
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}
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} // end namespace llvm
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#endif // GET_TARGET_REGBANK_IMPL