/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AArch64/AArch64GenRegisterBank.inc
Line | Count | Source |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Register Bank Source Fragments *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | #ifdef GET_REGBANK_DECLARATIONS |
10 | | #undef GET_REGBANK_DECLARATIONS |
11 | | namespace llvm { |
12 | | namespace AArch64 { |
13 | | enum { |
14 | | CCRegBankID, |
15 | | FPRRegBankID, |
16 | | GPRRegBankID, |
17 | | NumRegisterBanks, |
18 | | }; |
19 | | } // end namespace AArch64 |
20 | | } // end namespace llvm |
21 | | #endif // GET_REGBANK_DECLARATIONS |
22 | | |
23 | | #ifdef GET_TARGET_REGBANK_CLASS |
24 | | #undef GET_TARGET_REGBANK_CLASS |
25 | | private: |
26 | | static RegisterBank *RegBanks[]; |
27 | | |
28 | | protected: |
29 | | AArch64GenRegisterBankInfo(); |
30 | | |
31 | | #endif // GET_TARGET_REGBANK_CLASS |
32 | | |
33 | | #ifdef GET_TARGET_REGBANK_IMPL |
34 | | #undef GET_TARGET_REGBANK_IMPL |
35 | | namespace llvm { |
36 | | namespace AArch64 { |
37 | | const uint32_t CCRegBankCoverageData[] = { |
38 | | // 0-31 |
39 | | (1u << (AArch64::CCRRegClassID - 0)) | |
40 | | 0, |
41 | | // 32-63 |
42 | | 0, |
43 | | // 64-95 |
44 | | 0, |
45 | | // 96-127 |
46 | | 0, |
47 | | }; |
48 | | const uint32_t FPRRegBankCoverageData[] = { |
49 | | // 0-31 |
50 | | (1u << (AArch64::FPR8RegClassID - 0)) | |
51 | | (1u << (AArch64::FPR16RegClassID - 0)) | |
52 | | (1u << (AArch64::FPR32RegClassID - 0)) | |
53 | | (1u << (AArch64::FPR64RegClassID - 0)) | |
54 | | (1u << (AArch64::DDRegClassID - 0)) | |
55 | | 0, |
56 | | // 32-63 |
57 | | (1u << (AArch64::FPR128RegClassID - 32)) | |
58 | | (1u << (AArch64::DDDRegClassID - 32)) | |
59 | | (1u << (AArch64::DDDDRegClassID - 32)) | |
60 | | (1u << (AArch64::QQRegClassID - 32)) | |
61 | | (1u << (AArch64::QQQRegClassID - 32)) | |
62 | | (1u << (AArch64::FPR128_loRegClassID - 32)) | |
63 | | (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 32)) | |
64 | | (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 32)) | |
65 | | (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 32)) | |
66 | | (1u << (AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID - 32)) | |
67 | | (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) | |
68 | | (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) | |
69 | | 0, |
70 | | // 64-95 |
71 | | (1u << (AArch64::QQQQRegClassID - 64)) | |
72 | | (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 64)) | |
73 | | (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID - 64)) | |
74 | | (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID - 64)) | |
75 | | (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) | |
76 | | (1u << (AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 64)) | |
77 | | (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 64)) | |
78 | | (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 64)) | |
79 | | (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) | |
80 | | (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) | |
81 | | (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) | |
82 | | (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) | |
83 | | (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) | |
84 | | 0, |
85 | | // 96-127 |
86 | | (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 96)) | |
87 | | 0, |
88 | | }; |
89 | | const uint32_t GPRRegBankCoverageData[] = { |
90 | | // 0-31 |
91 | | (1u << (AArch64::GPR64allRegClassID - 0)) | |
92 | | (1u << (AArch64::GPR32allRegClassID - 0)) | |
93 | | (1u << (AArch64::GPR64RegClassID - 0)) | |
94 | | (1u << (AArch64::GPR32RegClassID - 0)) | |
95 | | (1u << (AArch64::GPR64commonRegClassID - 0)) | |
96 | | (1u << (AArch64::GPR32spRegClassID - 0)) | |
97 | | (1u << (AArch64::GPR32commonRegClassID - 0)) | |
98 | | (1u << (AArch64::GPR64common_and_GPR64noipRegClassID - 0)) | |
99 | | (1u << (AArch64::GPR64noip_and_tcGPR64RegClassID - 0)) | |
100 | | (1u << (AArch64::GPR64argRegClassID - 0)) | |
101 | | (1u << (AArch64::GPR32argRegClassID - 0)) | |
102 | | (1u << (AArch64::tcGPR64RegClassID - 0)) | |
103 | | (1u << (AArch64::rtcGPR64RegClassID - 0)) | |
104 | | (1u << (AArch64::GPR64noipRegClassID - 0)) | |
105 | | (1u << (AArch64::GPR64spRegClassID - 0)) | |
106 | | (1u << (AArch64::GPR64sponlyRegClassID - 0)) | |
107 | | (1u << (AArch64::GPR32sponlyRegClassID - 0)) | |
108 | | 0, |
109 | | // 32-63 |
110 | | 0, |
111 | | // 64-95 |
112 | | 0, |
113 | | // 96-127 |
114 | | 0, |
115 | | }; |
116 | | |
117 | | RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* Size */ 32, /* CoveredRegClasses */ CCRegBankCoverageData, /* NumRegClasses */ 108); |
118 | | RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* Size */ 512, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 108); |
119 | | RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 108); |
120 | | } // end namespace AArch64 |
121 | | |
122 | | RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = { |
123 | | &AArch64::CCRegBank, |
124 | | &AArch64::FPRRegBank, |
125 | | &AArch64::GPRRegBank, |
126 | | }; |
127 | | |
128 | | AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo() |
129 | 9.10k | : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks) { |
130 | 9.10k | // Assert that RegBank indices match their ID's |
131 | | #ifndef NDEBUG |
132 | | unsigned Index = 0; |
133 | | for (const auto &RB : RegBanks) |
134 | | assert(Index++ == RB->getID() && "Index != ID"); |
135 | | #endif // NDEBUG |
136 | | } |
137 | | } // end namespace llvm |
138 | | #endif // GET_TARGET_REGBANK_IMPL |