Coverage Report

Created: 2019-03-22 08:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AArch64/AArch64GenRegisterInfo.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass AArch64MCRegisterClasses[];
17
18
namespace AArch64 {
19
enum {
20
  NoRegister,
21
  FFR = 1,
22
  FP = 2,
23
  LR = 3,
24
  NZCV = 4,
25
  SP = 5,
26
  WSP = 6,
27
  WZR = 7,
28
  XZR = 8,
29
  B0 = 9,
30
  B1 = 10,
31
  B2 = 11,
32
  B3 = 12,
33
  B4 = 13,
34
  B5 = 14,
35
  B6 = 15,
36
  B7 = 16,
37
  B8 = 17,
38
  B9 = 18,
39
  B10 = 19,
40
  B11 = 20,
41
  B12 = 21,
42
  B13 = 22,
43
  B14 = 23,
44
  B15 = 24,
45
  B16 = 25,
46
  B17 = 26,
47
  B18 = 27,
48
  B19 = 28,
49
  B20 = 29,
50
  B21 = 30,
51
  B22 = 31,
52
  B23 = 32,
53
  B24 = 33,
54
  B25 = 34,
55
  B26 = 35,
56
  B27 = 36,
57
  B28 = 37,
58
  B29 = 38,
59
  B30 = 39,
60
  B31 = 40,
61
  D0 = 41,
62
  D1 = 42,
63
  D2 = 43,
64
  D3 = 44,
65
  D4 = 45,
66
  D5 = 46,
67
  D6 = 47,
68
  D7 = 48,
69
  D8 = 49,
70
  D9 = 50,
71
  D10 = 51,
72
  D11 = 52,
73
  D12 = 53,
74
  D13 = 54,
75
  D14 = 55,
76
  D15 = 56,
77
  D16 = 57,
78
  D17 = 58,
79
  D18 = 59,
80
  D19 = 60,
81
  D20 = 61,
82
  D21 = 62,
83
  D22 = 63,
84
  D23 = 64,
85
  D24 = 65,
86
  D25 = 66,
87
  D26 = 67,
88
  D27 = 68,
89
  D28 = 69,
90
  D29 = 70,
91
  D30 = 71,
92
  D31 = 72,
93
  H0 = 73,
94
  H1 = 74,
95
  H2 = 75,
96
  H3 = 76,
97
  H4 = 77,
98
  H5 = 78,
99
  H6 = 79,
100
  H7 = 80,
101
  H8 = 81,
102
  H9 = 82,
103
  H10 = 83,
104
  H11 = 84,
105
  H12 = 85,
106
  H13 = 86,
107
  H14 = 87,
108
  H15 = 88,
109
  H16 = 89,
110
  H17 = 90,
111
  H18 = 91,
112
  H19 = 92,
113
  H20 = 93,
114
  H21 = 94,
115
  H22 = 95,
116
  H23 = 96,
117
  H24 = 97,
118
  H25 = 98,
119
  H26 = 99,
120
  H27 = 100,
121
  H28 = 101,
122
  H29 = 102,
123
  H30 = 103,
124
  H31 = 104,
125
  P0 = 105,
126
  P1 = 106,
127
  P2 = 107,
128
  P3 = 108,
129
  P4 = 109,
130
  P5 = 110,
131
  P6 = 111,
132
  P7 = 112,
133
  P8 = 113,
134
  P9 = 114,
135
  P10 = 115,
136
  P11 = 116,
137
  P12 = 117,
138
  P13 = 118,
139
  P14 = 119,
140
  P15 = 120,
141
  Q0 = 121,
142
  Q1 = 122,
143
  Q2 = 123,
144
  Q3 = 124,
145
  Q4 = 125,
146
  Q5 = 126,
147
  Q6 = 127,
148
  Q7 = 128,
149
  Q8 = 129,
150
  Q9 = 130,
151
  Q10 = 131,
152
  Q11 = 132,
153
  Q12 = 133,
154
  Q13 = 134,
155
  Q14 = 135,
156
  Q15 = 136,
157
  Q16 = 137,
158
  Q17 = 138,
159
  Q18 = 139,
160
  Q19 = 140,
161
  Q20 = 141,
162
  Q21 = 142,
163
  Q22 = 143,
164
  Q23 = 144,
165
  Q24 = 145,
166
  Q25 = 146,
167
  Q26 = 147,
168
  Q27 = 148,
169
  Q28 = 149,
170
  Q29 = 150,
171
  Q30 = 151,
172
  Q31 = 152,
173
  S0 = 153,
174
  S1 = 154,
175
  S2 = 155,
176
  S3 = 156,
177
  S4 = 157,
178
  S5 = 158,
179
  S6 = 159,
180
  S7 = 160,
181
  S8 = 161,
182
  S9 = 162,
183
  S10 = 163,
184
  S11 = 164,
185
  S12 = 165,
186
  S13 = 166,
187
  S14 = 167,
188
  S15 = 168,
189
  S16 = 169,
190
  S17 = 170,
191
  S18 = 171,
192
  S19 = 172,
193
  S20 = 173,
194
  S21 = 174,
195
  S22 = 175,
196
  S23 = 176,
197
  S24 = 177,
198
  S25 = 178,
199
  S26 = 179,
200
  S27 = 180,
201
  S28 = 181,
202
  S29 = 182,
203
  S30 = 183,
204
  S31 = 184,
205
  W0 = 185,
206
  W1 = 186,
207
  W2 = 187,
208
  W3 = 188,
209
  W4 = 189,
210
  W5 = 190,
211
  W6 = 191,
212
  W7 = 192,
213
  W8 = 193,
214
  W9 = 194,
215
  W10 = 195,
216
  W11 = 196,
217
  W12 = 197,
218
  W13 = 198,
219
  W14 = 199,
220
  W15 = 200,
221
  W16 = 201,
222
  W17 = 202,
223
  W18 = 203,
224
  W19 = 204,
225
  W20 = 205,
226
  W21 = 206,
227
  W22 = 207,
228
  W23 = 208,
229
  W24 = 209,
230
  W25 = 210,
231
  W26 = 211,
232
  W27 = 212,
233
  W28 = 213,
234
  W29 = 214,
235
  W30 = 215,
236
  X0 = 216,
237
  X1 = 217,
238
  X2 = 218,
239
  X3 = 219,
240
  X4 = 220,
241
  X5 = 221,
242
  X6 = 222,
243
  X7 = 223,
244
  X8 = 224,
245
  X9 = 225,
246
  X10 = 226,
247
  X11 = 227,
248
  X12 = 228,
249
  X13 = 229,
250
  X14 = 230,
251
  X15 = 231,
252
  X16 = 232,
253
  X17 = 233,
254
  X18 = 234,
255
  X19 = 235,
256
  X20 = 236,
257
  X21 = 237,
258
  X22 = 238,
259
  X23 = 239,
260
  X24 = 240,
261
  X25 = 241,
262
  X26 = 242,
263
  X27 = 243,
264
  X28 = 244,
265
  Z0 = 245,
266
  Z1 = 246,
267
  Z2 = 247,
268
  Z3 = 248,
269
  Z4 = 249,
270
  Z5 = 250,
271
  Z6 = 251,
272
  Z7 = 252,
273
  Z8 = 253,
274
  Z9 = 254,
275
  Z10 = 255,
276
  Z11 = 256,
277
  Z12 = 257,
278
  Z13 = 258,
279
  Z14 = 259,
280
  Z15 = 260,
281
  Z16 = 261,
282
  Z17 = 262,
283
  Z18 = 263,
284
  Z19 = 264,
285
  Z20 = 265,
286
  Z21 = 266,
287
  Z22 = 267,
288
  Z23 = 268,
289
  Z24 = 269,
290
  Z25 = 270,
291
  Z26 = 271,
292
  Z27 = 272,
293
  Z28 = 273,
294
  Z29 = 274,
295
  Z30 = 275,
296
  Z31 = 276,
297
  Z0_HI = 277,
298
  Z1_HI = 278,
299
  Z2_HI = 279,
300
  Z3_HI = 280,
301
  Z4_HI = 281,
302
  Z5_HI = 282,
303
  Z6_HI = 283,
304
  Z7_HI = 284,
305
  Z8_HI = 285,
306
  Z9_HI = 286,
307
  Z10_HI = 287,
308
  Z11_HI = 288,
309
  Z12_HI = 289,
310
  Z13_HI = 290,
311
  Z14_HI = 291,
312
  Z15_HI = 292,
313
  Z16_HI = 293,
314
  Z17_HI = 294,
315
  Z18_HI = 295,
316
  Z19_HI = 296,
317
  Z20_HI = 297,
318
  Z21_HI = 298,
319
  Z22_HI = 299,
320
  Z23_HI = 300,
321
  Z24_HI = 301,
322
  Z25_HI = 302,
323
  Z26_HI = 303,
324
  Z27_HI = 304,
325
  Z28_HI = 305,
326
  Z29_HI = 306,
327
  Z30_HI = 307,
328
  Z31_HI = 308,
329
  D0_D1 = 309,
330
  D1_D2 = 310,
331
  D2_D3 = 311,
332
  D3_D4 = 312,
333
  D4_D5 = 313,
334
  D5_D6 = 314,
335
  D6_D7 = 315,
336
  D7_D8 = 316,
337
  D8_D9 = 317,
338
  D9_D10 = 318,
339
  D10_D11 = 319,
340
  D11_D12 = 320,
341
  D12_D13 = 321,
342
  D13_D14 = 322,
343
  D14_D15 = 323,
344
  D15_D16 = 324,
345
  D16_D17 = 325,
346
  D17_D18 = 326,
347
  D18_D19 = 327,
348
  D19_D20 = 328,
349
  D20_D21 = 329,
350
  D21_D22 = 330,
351
  D22_D23 = 331,
352
  D23_D24 = 332,
353
  D24_D25 = 333,
354
  D25_D26 = 334,
355
  D26_D27 = 335,
356
  D27_D28 = 336,
357
  D28_D29 = 337,
358
  D29_D30 = 338,
359
  D30_D31 = 339,
360
  D31_D0 = 340,
361
  D0_D1_D2_D3 = 341,
362
  D1_D2_D3_D4 = 342,
363
  D2_D3_D4_D5 = 343,
364
  D3_D4_D5_D6 = 344,
365
  D4_D5_D6_D7 = 345,
366
  D5_D6_D7_D8 = 346,
367
  D6_D7_D8_D9 = 347,
368
  D7_D8_D9_D10 = 348,
369
  D8_D9_D10_D11 = 349,
370
  D9_D10_D11_D12 = 350,
371
  D10_D11_D12_D13 = 351,
372
  D11_D12_D13_D14 = 352,
373
  D12_D13_D14_D15 = 353,
374
  D13_D14_D15_D16 = 354,
375
  D14_D15_D16_D17 = 355,
376
  D15_D16_D17_D18 = 356,
377
  D16_D17_D18_D19 = 357,
378
  D17_D18_D19_D20 = 358,
379
  D18_D19_D20_D21 = 359,
380
  D19_D20_D21_D22 = 360,
381
  D20_D21_D22_D23 = 361,
382
  D21_D22_D23_D24 = 362,
383
  D22_D23_D24_D25 = 363,
384
  D23_D24_D25_D26 = 364,
385
  D24_D25_D26_D27 = 365,
386
  D25_D26_D27_D28 = 366,
387
  D26_D27_D28_D29 = 367,
388
  D27_D28_D29_D30 = 368,
389
  D28_D29_D30_D31 = 369,
390
  D29_D30_D31_D0 = 370,
391
  D30_D31_D0_D1 = 371,
392
  D31_D0_D1_D2 = 372,
393
  D0_D1_D2 = 373,
394
  D1_D2_D3 = 374,
395
  D2_D3_D4 = 375,
396
  D3_D4_D5 = 376,
397
  D4_D5_D6 = 377,
398
  D5_D6_D7 = 378,
399
  D6_D7_D8 = 379,
400
  D7_D8_D9 = 380,
401
  D8_D9_D10 = 381,
402
  D9_D10_D11 = 382,
403
  D10_D11_D12 = 383,
404
  D11_D12_D13 = 384,
405
  D12_D13_D14 = 385,
406
  D13_D14_D15 = 386,
407
  D14_D15_D16 = 387,
408
  D15_D16_D17 = 388,
409
  D16_D17_D18 = 389,
410
  D17_D18_D19 = 390,
411
  D18_D19_D20 = 391,
412
  D19_D20_D21 = 392,
413
  D20_D21_D22 = 393,
414
  D21_D22_D23 = 394,
415
  D22_D23_D24 = 395,
416
  D23_D24_D25 = 396,
417
  D24_D25_D26 = 397,
418
  D25_D26_D27 = 398,
419
  D26_D27_D28 = 399,
420
  D27_D28_D29 = 400,
421
  D28_D29_D30 = 401,
422
  D29_D30_D31 = 402,
423
  D30_D31_D0 = 403,
424
  D31_D0_D1 = 404,
425
  Q0_Q1 = 405,
426
  Q1_Q2 = 406,
427
  Q2_Q3 = 407,
428
  Q3_Q4 = 408,
429
  Q4_Q5 = 409,
430
  Q5_Q6 = 410,
431
  Q6_Q7 = 411,
432
  Q7_Q8 = 412,
433
  Q8_Q9 = 413,
434
  Q9_Q10 = 414,
435
  Q10_Q11 = 415,
436
  Q11_Q12 = 416,
437
  Q12_Q13 = 417,
438
  Q13_Q14 = 418,
439
  Q14_Q15 = 419,
440
  Q15_Q16 = 420,
441
  Q16_Q17 = 421,
442
  Q17_Q18 = 422,
443
  Q18_Q19 = 423,
444
  Q19_Q20 = 424,
445
  Q20_Q21 = 425,
446
  Q21_Q22 = 426,
447
  Q22_Q23 = 427,
448
  Q23_Q24 = 428,
449
  Q24_Q25 = 429,
450
  Q25_Q26 = 430,
451
  Q26_Q27 = 431,
452
  Q27_Q28 = 432,
453
  Q28_Q29 = 433,
454
  Q29_Q30 = 434,
455
  Q30_Q31 = 435,
456
  Q31_Q0 = 436,
457
  Q0_Q1_Q2_Q3 = 437,
458
  Q1_Q2_Q3_Q4 = 438,
459
  Q2_Q3_Q4_Q5 = 439,
460
  Q3_Q4_Q5_Q6 = 440,
461
  Q4_Q5_Q6_Q7 = 441,
462
  Q5_Q6_Q7_Q8 = 442,
463
  Q6_Q7_Q8_Q9 = 443,
464
  Q7_Q8_Q9_Q10 = 444,
465
  Q8_Q9_Q10_Q11 = 445,
466
  Q9_Q10_Q11_Q12 = 446,
467
  Q10_Q11_Q12_Q13 = 447,
468
  Q11_Q12_Q13_Q14 = 448,
469
  Q12_Q13_Q14_Q15 = 449,
470
  Q13_Q14_Q15_Q16 = 450,
471
  Q14_Q15_Q16_Q17 = 451,
472
  Q15_Q16_Q17_Q18 = 452,
473
  Q16_Q17_Q18_Q19 = 453,
474
  Q17_Q18_Q19_Q20 = 454,
475
  Q18_Q19_Q20_Q21 = 455,
476
  Q19_Q20_Q21_Q22 = 456,
477
  Q20_Q21_Q22_Q23 = 457,
478
  Q21_Q22_Q23_Q24 = 458,
479
  Q22_Q23_Q24_Q25 = 459,
480
  Q23_Q24_Q25_Q26 = 460,
481
  Q24_Q25_Q26_Q27 = 461,
482
  Q25_Q26_Q27_Q28 = 462,
483
  Q26_Q27_Q28_Q29 = 463,
484
  Q27_Q28_Q29_Q30 = 464,
485
  Q28_Q29_Q30_Q31 = 465,
486
  Q29_Q30_Q31_Q0 = 466,
487
  Q30_Q31_Q0_Q1 = 467,
488
  Q31_Q0_Q1_Q2 = 468,
489
  Q0_Q1_Q2 = 469,
490
  Q1_Q2_Q3 = 470,
491
  Q2_Q3_Q4 = 471,
492
  Q3_Q4_Q5 = 472,
493
  Q4_Q5_Q6 = 473,
494
  Q5_Q6_Q7 = 474,
495
  Q6_Q7_Q8 = 475,
496
  Q7_Q8_Q9 = 476,
497
  Q8_Q9_Q10 = 477,
498
  Q9_Q10_Q11 = 478,
499
  Q10_Q11_Q12 = 479,
500
  Q11_Q12_Q13 = 480,
501
  Q12_Q13_Q14 = 481,
502
  Q13_Q14_Q15 = 482,
503
  Q14_Q15_Q16 = 483,
504
  Q15_Q16_Q17 = 484,
505
  Q16_Q17_Q18 = 485,
506
  Q17_Q18_Q19 = 486,
507
  Q18_Q19_Q20 = 487,
508
  Q19_Q20_Q21 = 488,
509
  Q20_Q21_Q22 = 489,
510
  Q21_Q22_Q23 = 490,
511
  Q22_Q23_Q24 = 491,
512
  Q23_Q24_Q25 = 492,
513
  Q24_Q25_Q26 = 493,
514
  Q25_Q26_Q27 = 494,
515
  Q26_Q27_Q28 = 495,
516
  Q27_Q28_Q29 = 496,
517
  Q28_Q29_Q30 = 497,
518
  Q29_Q30_Q31 = 498,
519
  Q30_Q31_Q0 = 499,
520
  Q31_Q0_Q1 = 500,
521
  W30_WZR = 501,
522
  W0_W1 = 502,
523
  W2_W3 = 503,
524
  W4_W5 = 504,
525
  W6_W7 = 505,
526
  W8_W9 = 506,
527
  W10_W11 = 507,
528
  W12_W13 = 508,
529
  W14_W15 = 509,
530
  W16_W17 = 510,
531
  W18_W19 = 511,
532
  W20_W21 = 512,
533
  W22_W23 = 513,
534
  W24_W25 = 514,
535
  W26_W27 = 515,
536
  W28_W29 = 516,
537
  LR_XZR = 517,
538
  X28_FP = 518,
539
  X0_X1 = 519,
540
  X2_X3 = 520,
541
  X4_X5 = 521,
542
  X6_X7 = 522,
543
  X8_X9 = 523,
544
  X10_X11 = 524,
545
  X12_X13 = 525,
546
  X14_X15 = 526,
547
  X16_X17 = 527,
548
  X18_X19 = 528,
549
  X20_X21 = 529,
550
  X22_X23 = 530,
551
  X24_X25 = 531,
552
  X26_X27 = 532,
553
  Z0_Z1 = 533,
554
  Z1_Z2 = 534,
555
  Z2_Z3 = 535,
556
  Z3_Z4 = 536,
557
  Z4_Z5 = 537,
558
  Z5_Z6 = 538,
559
  Z6_Z7 = 539,
560
  Z7_Z8 = 540,
561
  Z8_Z9 = 541,
562
  Z9_Z10 = 542,
563
  Z10_Z11 = 543,
564
  Z11_Z12 = 544,
565
  Z12_Z13 = 545,
566
  Z13_Z14 = 546,
567
  Z14_Z15 = 547,
568
  Z15_Z16 = 548,
569
  Z16_Z17 = 549,
570
  Z17_Z18 = 550,
571
  Z18_Z19 = 551,
572
  Z19_Z20 = 552,
573
  Z20_Z21 = 553,
574
  Z21_Z22 = 554,
575
  Z22_Z23 = 555,
576
  Z23_Z24 = 556,
577
  Z24_Z25 = 557,
578
  Z25_Z26 = 558,
579
  Z26_Z27 = 559,
580
  Z27_Z28 = 560,
581
  Z28_Z29 = 561,
582
  Z29_Z30 = 562,
583
  Z30_Z31 = 563,
584
  Z31_Z0 = 564,
585
  Z0_Z1_Z2_Z3 = 565,
586
  Z1_Z2_Z3_Z4 = 566,
587
  Z2_Z3_Z4_Z5 = 567,
588
  Z3_Z4_Z5_Z6 = 568,
589
  Z4_Z5_Z6_Z7 = 569,
590
  Z5_Z6_Z7_Z8 = 570,
591
  Z6_Z7_Z8_Z9 = 571,
592
  Z7_Z8_Z9_Z10 = 572,
593
  Z8_Z9_Z10_Z11 = 573,
594
  Z9_Z10_Z11_Z12 = 574,
595
  Z10_Z11_Z12_Z13 = 575,
596
  Z11_Z12_Z13_Z14 = 576,
597
  Z12_Z13_Z14_Z15 = 577,
598
  Z13_Z14_Z15_Z16 = 578,
599
  Z14_Z15_Z16_Z17 = 579,
600
  Z15_Z16_Z17_Z18 = 580,
601
  Z16_Z17_Z18_Z19 = 581,
602
  Z17_Z18_Z19_Z20 = 582,
603
  Z18_Z19_Z20_Z21 = 583,
604
  Z19_Z20_Z21_Z22 = 584,
605
  Z20_Z21_Z22_Z23 = 585,
606
  Z21_Z22_Z23_Z24 = 586,
607
  Z22_Z23_Z24_Z25 = 587,
608
  Z23_Z24_Z25_Z26 = 588,
609
  Z24_Z25_Z26_Z27 = 589,
610
  Z25_Z26_Z27_Z28 = 590,
611
  Z26_Z27_Z28_Z29 = 591,
612
  Z27_Z28_Z29_Z30 = 592,
613
  Z28_Z29_Z30_Z31 = 593,
614
  Z29_Z30_Z31_Z0 = 594,
615
  Z30_Z31_Z0_Z1 = 595,
616
  Z31_Z0_Z1_Z2 = 596,
617
  Z0_Z1_Z2 = 597,
618
  Z1_Z2_Z3 = 598,
619
  Z2_Z3_Z4 = 599,
620
  Z3_Z4_Z5 = 600,
621
  Z4_Z5_Z6 = 601,
622
  Z5_Z6_Z7 = 602,
623
  Z6_Z7_Z8 = 603,
624
  Z7_Z8_Z9 = 604,
625
  Z8_Z9_Z10 = 605,
626
  Z9_Z10_Z11 = 606,
627
  Z10_Z11_Z12 = 607,
628
  Z11_Z12_Z13 = 608,
629
  Z12_Z13_Z14 = 609,
630
  Z13_Z14_Z15 = 610,
631
  Z14_Z15_Z16 = 611,
632
  Z15_Z16_Z17 = 612,
633
  Z16_Z17_Z18 = 613,
634
  Z17_Z18_Z19 = 614,
635
  Z18_Z19_Z20 = 615,
636
  Z19_Z20_Z21 = 616,
637
  Z20_Z21_Z22 = 617,
638
  Z21_Z22_Z23 = 618,
639
  Z22_Z23_Z24 = 619,
640
  Z23_Z24_Z25 = 620,
641
  Z24_Z25_Z26 = 621,
642
  Z25_Z26_Z27 = 622,
643
  Z26_Z27_Z28 = 623,
644
  Z27_Z28_Z29 = 624,
645
  Z28_Z29_Z30 = 625,
646
  Z29_Z30_Z31 = 626,
647
  Z30_Z31_Z0 = 627,
648
  Z31_Z0_Z1 = 628,
649
  NUM_TARGET_REGS   // 629
650
};
651
} // end namespace AArch64
652
653
// Register classes
654
655
namespace AArch64 {
656
enum {
657
  FPR8RegClassID = 0,
658
  FPR16RegClassID = 1,
659
  PPRRegClassID = 2,
660
  PPR_3bRegClassID = 3,
661
  GPR32allRegClassID = 4,
662
  FPR32RegClassID = 5,
663
  GPR32RegClassID = 6,
664
  GPR32spRegClassID = 7,
665
  GPR32commonRegClassID = 8,
666
  GPR32argRegClassID = 9,
667
  CCRRegClassID = 10,
668
  GPR32sponlyRegClassID = 11,
669
  WSeqPairsClassRegClassID = 12,
670
  WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 13,
671
  WSeqPairsClass_with_sube32_in_GPR32argRegClassID = 14,
672
  GPR64allRegClassID = 15,
673
  FPR64RegClassID = 16,
674
  GPR64RegClassID = 17,
675
  GPR64spRegClassID = 18,
676
  GPR64commonRegClassID = 19,
677
  GPR64noipRegClassID = 20,
678
  GPR64common_and_GPR64noipRegClassID = 21,
679
  tcGPR64RegClassID = 22,
680
  GPR64noip_and_tcGPR64RegClassID = 23,
681
  GPR64argRegClassID = 24,
682
  rtcGPR64RegClassID = 25,
683
  GPR64sponlyRegClassID = 26,
684
  DDRegClassID = 27,
685
  XSeqPairsClassRegClassID = 28,
686
  XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 29,
687
  XSeqPairsClass_with_subo64_in_GPR64noipRegClassID = 30,
688
  XSeqPairsClass_with_sube64_in_GPR64noipRegClassID = 31,
689
  XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 32,
690
  XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClassID = 33,
691
  XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 34,
692
  XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID = 35,
693
  XSeqPairsClass_with_sub_32_in_GPR32argRegClassID = 36,
694
  XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID = 37,
695
  FPR128RegClassID = 38,
696
  ZPRRegClassID = 39,
697
  FPR128_loRegClassID = 40,
698
  ZPR_4bRegClassID = 41,
699
  ZPR_3bRegClassID = 42,
700
  DDDRegClassID = 43,
701
  DDDDRegClassID = 44,
702
  QQRegClassID = 45,
703
  ZPR2RegClassID = 46,
704
  QQ_with_qsub0_in_FPR128_loRegClassID = 47,
705
  QQ_with_qsub1_in_FPR128_loRegClassID = 48,
706
  ZPR2_with_zsub1_in_ZPR_4bRegClassID = 49,
707
  ZPR2_with_zsub_in_FPR128_loRegClassID = 50,
708
  QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 51,
709
  ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 52,
710
  ZPR2_with_zsub0_in_ZPR_3bRegClassID = 53,
711
  ZPR2_with_zsub1_in_ZPR_3bRegClassID = 54,
712
  ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 55,
713
  QQQRegClassID = 56,
714
  ZPR3RegClassID = 57,
715
  QQQ_with_qsub0_in_FPR128_loRegClassID = 58,
716
  QQQ_with_qsub1_in_FPR128_loRegClassID = 59,
717
  QQQ_with_qsub2_in_FPR128_loRegClassID = 60,
718
  ZPR3_with_zsub1_in_ZPR_4bRegClassID = 61,
719
  ZPR3_with_zsub2_in_ZPR_4bRegClassID = 62,
720
  ZPR3_with_zsub_in_FPR128_loRegClassID = 63,
721
  QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 64,
722
  QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 65,
723
  ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 66,
724
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 67,
725
  QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 68,
726
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 69,
727
  ZPR3_with_zsub0_in_ZPR_3bRegClassID = 70,
728
  ZPR3_with_zsub1_in_ZPR_3bRegClassID = 71,
729
  ZPR3_with_zsub2_in_ZPR_3bRegClassID = 72,
730
  ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 73,
731
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 74,
732
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 75,
733
  QQQQRegClassID = 76,
734
  ZPR4RegClassID = 77,
735
  QQQQ_with_qsub0_in_FPR128_loRegClassID = 78,
736
  QQQQ_with_qsub1_in_FPR128_loRegClassID = 79,
737
  QQQQ_with_qsub2_in_FPR128_loRegClassID = 80,
738
  QQQQ_with_qsub3_in_FPR128_loRegClassID = 81,
739
  ZPR4_with_zsub1_in_ZPR_4bRegClassID = 82,
740
  ZPR4_with_zsub2_in_ZPR_4bRegClassID = 83,
741
  ZPR4_with_zsub3_in_ZPR_4bRegClassID = 84,
742
  ZPR4_with_zsub_in_FPR128_loRegClassID = 85,
743
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 86,
744
  QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 87,
745
  QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 88,
746
  ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 89,
747
  ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 90,
748
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 91,
749
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 92,
750
  QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 93,
751
  ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 94,
752
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 95,
753
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 96,
754
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 97,
755
  ZPR4_with_zsub0_in_ZPR_3bRegClassID = 98,
756
  ZPR4_with_zsub1_in_ZPR_3bRegClassID = 99,
757
  ZPR4_with_zsub2_in_ZPR_3bRegClassID = 100,
758
  ZPR4_with_zsub3_in_ZPR_3bRegClassID = 101,
759
  ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 102,
760
  ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 103,
761
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 104,
762
  ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 105,
763
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 106,
764
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 107,
765
766
  };
767
} // end namespace AArch64
768
769
770
// Register alternate name indices
771
772
namespace AArch64 {
773
enum {
774
  NoRegAltName, // 0
775
  vlist1, // 1
776
  vreg, // 2
777
  NUM_TARGET_REG_ALT_NAMES = 3
778
};
779
} // end namespace AArch64
780
781
782
// Subregister indices
783
784
namespace AArch64 {
785
enum {
786
  NoSubRegister,
787
  bsub, // 1
788
  dsub, // 2
789
  dsub0,  // 3
790
  dsub1,  // 4
791
  dsub2,  // 5
792
  dsub3,  // 6
793
  hsub, // 7
794
  qhisub, // 8
795
  qsub, // 9
796
  qsub0,  // 10
797
  qsub1,  // 11
798
  qsub2,  // 12
799
  qsub3,  // 13
800
  ssub, // 14
801
  sub_32, // 15
802
  sube32, // 16
803
  sube64, // 17
804
  subo32, // 18
805
  subo64, // 19
806
  zsub, // 20
807
  zsub0,  // 21
808
  zsub1,  // 22
809
  zsub2,  // 23
810
  zsub3,  // 24
811
  zsub_hi,  // 25
812
  dsub1_then_bsub,  // 26
813
  dsub1_then_hsub,  // 27
814
  dsub1_then_ssub,  // 28
815
  dsub3_then_bsub,  // 29
816
  dsub3_then_hsub,  // 30
817
  dsub3_then_ssub,  // 31
818
  dsub2_then_bsub,  // 32
819
  dsub2_then_hsub,  // 33
820
  dsub2_then_ssub,  // 34
821
  qsub1_then_bsub,  // 35
822
  qsub1_then_dsub,  // 36
823
  qsub1_then_hsub,  // 37
824
  qsub1_then_ssub,  // 38
825
  qsub3_then_bsub,  // 39
826
  qsub3_then_dsub,  // 40
827
  qsub3_then_hsub,  // 41
828
  qsub3_then_ssub,  // 42
829
  qsub2_then_bsub,  // 43
830
  qsub2_then_dsub,  // 44
831
  qsub2_then_hsub,  // 45
832
  qsub2_then_ssub,  // 46
833
  subo64_then_sub_32, // 47
834
  zsub1_then_bsub,  // 48
835
  zsub1_then_dsub,  // 49
836
  zsub1_then_hsub,  // 50
837
  zsub1_then_ssub,  // 51
838
  zsub1_then_zsub,  // 52
839
  zsub1_then_zsub_hi, // 53
840
  zsub3_then_bsub,  // 54
841
  zsub3_then_dsub,  // 55
842
  zsub3_then_hsub,  // 56
843
  zsub3_then_ssub,  // 57
844
  zsub3_then_zsub,  // 58
845
  zsub3_then_zsub_hi, // 59
846
  zsub2_then_bsub,  // 60
847
  zsub2_then_dsub,  // 61
848
  zsub2_then_hsub,  // 62
849
  zsub2_then_ssub,  // 63
850
  zsub2_then_zsub,  // 64
851
  zsub2_then_zsub_hi, // 65
852
  dsub0_dsub1,  // 66
853
  dsub0_dsub1_dsub2,  // 67
854
  dsub1_dsub2,  // 68
855
  dsub1_dsub2_dsub3,  // 69
856
  dsub2_dsub3,  // 70
857
  dsub_qsub1_then_dsub, // 71
858
  dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 72
859
  dsub_qsub1_then_dsub_qsub2_then_dsub, // 73
860
  qsub0_qsub1,  // 74
861
  qsub0_qsub1_qsub2,  // 75
862
  qsub1_qsub2,  // 76
863
  qsub1_qsub2_qsub3,  // 77
864
  qsub2_qsub3,  // 78
865
  qsub1_then_dsub_qsub2_then_dsub,  // 79
866
  qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,  // 80
867
  qsub2_then_dsub_qsub3_then_dsub,  // 81
868
  sub_32_subo64_then_sub_32,  // 82
869
  dsub_zsub1_then_dsub, // 83
870
  zsub_zsub1_then_zsub, // 84
871
  dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 85
872
  dsub_zsub1_then_dsub_zsub2_then_dsub, // 86
873
  zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 87
874
  zsub_zsub1_then_zsub_zsub2_then_zsub, // 88
875
  zsub0_zsub1,  // 89
876
  zsub0_zsub1_zsub2,  // 90
877
  zsub1_zsub2,  // 91
878
  zsub1_zsub2_zsub3,  // 92
879
  zsub2_zsub3,  // 93
880
  zsub1_then_dsub_zsub2_then_dsub,  // 94
881
  zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub,  // 95
882
  zsub1_then_zsub_zsub2_then_zsub,  // 96
883
  zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub,  // 97
884
  zsub2_then_dsub_zsub3_then_dsub,  // 98
885
  zsub2_then_zsub_zsub3_then_zsub,  // 99
886
  NUM_TARGET_SUBREGS
887
};
888
} // end namespace AArch64
889
890
} // end namespace llvm
891
892
#endif // GET_REGINFO_ENUM
893
894
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
895
|*                                                                            *|
896
|* MC Register Information                                                    *|
897
|*                                                                            *|
898
|* Automatically generated file, do not edit!                                 *|
899
|*                                                                            *|
900
\*===----------------------------------------------------------------------===*/
901
902
903
#ifdef GET_REGINFO_MC_DESC
904
#undef GET_REGINFO_MC_DESC
905
906
namespace llvm {
907
908
extern const MCPhysReg AArch64RegDiffLists[] = {
909
  /* 0 */ 64977, 1, 1, 1, 74, 1, 1, 1, 0,
910
  /* 9 */ 65105, 1, 1, 1, 0,
911
  /* 14 */ 65201, 1, 1, 1, 0,
912
  /* 19 */ 6, 29, 1, 1, 0,
913
  /* 24 */ 6, 29, 1, 1, 46, 29, 1, 1, 0,
914
  /* 33 */ 64945, 1, 1, 75, 1, 1, 0,
915
  /* 40 */ 65073, 1, 1, 0,
916
  /* 44 */ 65169, 1, 1, 0,
917
  /* 48 */ 6, 1, 29, 1, 0,
918
  /* 53 */ 6, 1, 29, 1, 46, 1, 29, 1, 0,
919
  /* 62 */ 6, 30, 1, 0,
920
  /* 66 */ 6, 30, 1, 46, 30, 1, 0,
921
  /* 73 */ 65009, 1, 76, 1, 0,
922
  /* 78 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0,
923
  /* 93 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0,
924
  /* 108 */ 64552, 1, 0,
925
  /* 111 */ 64586, 1, 0,
926
  /* 114 */ 65137, 1, 0,
927
  /* 117 */ 65219, 1, 0,
928
  /* 120 */ 65220, 1, 0,
929
  /* 123 */ 65221, 1, 0,
930
  /* 126 */ 65222, 1, 0,
931
  /* 129 */ 65223, 1, 0,
932
  /* 132 */ 65224, 1, 0,
933
  /* 135 */ 65225, 1, 0,
934
  /* 138 */ 65226, 1, 0,
935
  /* 141 */ 65227, 1, 0,
936
  /* 144 */ 65228, 1, 0,
937
  /* 147 */ 65229, 1, 0,
938
  /* 150 */ 65230, 1, 0,
939
  /* 153 */ 65231, 1, 0,
940
  /* 156 */ 65232, 1, 0,
941
  /* 159 */ 65233, 1, 0,
942
  /* 162 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 95, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
943
  /* 195 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 95, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
944
  /* 215 */ 65504, 287, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
945
  /* 226 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 65, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
946
  /* 259 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 65, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
947
  /* 279 */ 65504, 288, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
948
  /* 290 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 96, 63, 65503, 34, 65503, 1, 0,
949
  /* 308 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 65, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
950
  /* 341 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 65, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
951
  /* 361 */ 65504, 287, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
952
  /* 372 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 65, 64, 65504, 63, 65503, 1, 0,
953
  /* 390 */ 65503, 1, 128, 65503, 1, 160, 65503, 1, 0,
954
  /* 399 */ 31, 272, 2, 0,
955
  /* 403 */ 65324, 514, 2, 0,
956
  /* 407 */ 2, 3, 0,
957
  /* 410 */ 65021, 3, 0,
958
  /* 413 */ 4, 0,
959
  /* 415 */ 5, 0,
960
  /* 417 */ 1, 493, 16, 0,
961
  /* 421 */ 65324, 498, 16, 0,
962
  /* 425 */ 31, 272, 17, 0,
963
  /* 429 */ 31, 273, 17, 0,
964
  /* 433 */ 31, 274, 17, 0,
965
  /* 437 */ 31, 275, 17, 0,
966
  /* 441 */ 31, 276, 17, 0,
967
  /* 445 */ 31, 277, 17, 0,
968
  /* 449 */ 31, 278, 17, 0,
969
  /* 453 */ 31, 279, 17, 0,
970
  /* 457 */ 31, 280, 17, 0,
971
  /* 461 */ 31, 281, 17, 0,
972
  /* 465 */ 31, 282, 17, 0,
973
  /* 469 */ 31, 283, 17, 0,
974
  /* 473 */ 31, 284, 17, 0,
975
  /* 477 */ 31, 285, 17, 0,
976
  /* 481 */ 31, 286, 17, 0,
977
  /* 485 */ 6, 1, 1, 29, 0,
978
  /* 490 */ 6, 1, 1, 29, 46, 1, 1, 29, 0,
979
  /* 499 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 66, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
980
  /* 532 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 66, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
981
  /* 552 */ 65504, 287, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
982
  /* 563 */ 6, 1, 30, 0,
983
  /* 567 */ 6, 1, 30, 46, 1, 30, 0,
984
  /* 574 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 66, 63, 1, 65503, 1, 30, 0,
985
  /* 592 */ 6, 31, 0,
986
  /* 595 */ 6, 31, 46, 31, 0,
987
  /* 600 */ 65504, 31, 97, 65504, 31, 129, 65504, 31, 0,
988
  /* 609 */ 65297, 77, 0,
989
  /* 612 */ 1, 81, 0,
990
  /* 615 */ 65021, 81, 0,
991
  /* 618 */ 65248, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 31, 96, 0,
992
  /* 635 */ 65248, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 63, 96, 0,
993
  /* 652 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 30, 96, 65504, 96, 64, 1, 65312, 96, 0,
994
  /* 682 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 64, 1, 65312, 96, 0,
995
  /* 712 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 64, 65505, 65312, 96, 0,
996
  /* 742 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 64, 64, 65473, 64, 65441, 65343, 64, 32, 64, 65345, 96, 0,
997
  /* 788 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 64, 64, 65441, 64, 65473, 65311, 64, 32, 64, 65377, 96, 0,
998
  /* 834 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 29, 96, 65472, 32, 64, 32, 64, 64, 65473, 64, 65473, 65311, 64, 32, 64, 65377, 96, 0,
999
  /* 880 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 64, 64, 65473, 64, 65473, 65311, 64, 32, 64, 65377, 96, 0,
1000
  /* 926 */ 96, 128, 0,
1001
  /* 929 */ 212, 0,
1002
  /* 931 */ 65412, 65456, 112, 65456, 65472, 268, 0,
1003
  /* 938 */ 274, 0,
1004
  /* 940 */ 289, 0,
1005
  /* 942 */ 290, 0,
1006
  /* 944 */ 291, 0,
1007
  /* 946 */ 292, 0,
1008
  /* 948 */ 293, 0,
1009
  /* 950 */ 294, 0,
1010
  /* 952 */ 295, 0,
1011
  /* 954 */ 296, 0,
1012
  /* 956 */ 297, 0,
1013
  /* 958 */ 298, 0,
1014
  /* 960 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0,
1015
  /* 972 */ 300, 0,
1016
  /* 974 */ 301, 0,
1017
  /* 976 */ 65262, 65505, 65325, 212, 302, 0,
1018
  /* 982 */ 65246, 65505, 32, 65505, 303, 0,
1019
  /* 988 */ 65245, 65505, 32, 65505, 304, 0,
1020
  /* 994 */ 65244, 65505, 32, 65505, 305, 0,
1021
  /* 1000 */ 65243, 65505, 32, 65505, 306, 0,
1022
  /* 1006 */ 65242, 65505, 32, 65505, 307, 0,
1023
  /* 1012 */ 65241, 65505, 32, 65505, 308, 0,
1024
  /* 1018 */ 65240, 65505, 32, 65505, 309, 0,
1025
  /* 1024 */ 65239, 65505, 32, 65505, 310, 0,
1026
  /* 1030 */ 65238, 65505, 32, 65505, 311, 0,
1027
  /* 1036 */ 65237, 65505, 32, 65505, 312, 0,
1028
  /* 1042 */ 65236, 65505, 32, 65505, 313, 0,
1029
  /* 1048 */ 65235, 65505, 32, 65505, 314, 0,
1030
  /* 1054 */ 65234, 65505, 32, 65505, 315, 0,
1031
  /* 1060 */ 65233, 65505, 32, 65505, 316, 0,
1032
  /* 1066 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0,
1033
  /* 1078 */ 65022, 212, 65329, 65535, 494, 0,
1034
  /* 1084 */ 509, 0,
1035
  /* 1086 */ 514, 0,
1036
  /* 1088 */ 516, 0,
1037
  /* 1090 */ 65323, 0,
1038
  /* 1092 */ 65250, 65328, 0,
1039
  /* 1095 */ 65342, 0,
1040
  /* 1097 */ 65374, 0,
1041
  /* 1099 */ 65389, 0,
1042
  /* 1101 */ 65405, 0,
1043
  /* 1103 */ 65421, 0,
1044
  /* 1105 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0,
1045
  /* 1126 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0,
1046
  /* 1147 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0,
1047
  /* 1168 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
1048
  /* 1200 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0,
1049
  /* 1222 */ 65469, 0,
1050
  /* 1224 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0,
1051
  /* 1233 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0,
1052
  /* 1242 */ 65456, 112, 65456, 65472, 0,
1053
  /* 1247 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
1054
  /* 1279 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1055
  /* 1311 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1056
  /* 1343 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0,
1057
  /* 1365 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0,
1058
  /* 1387 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0,
1059
  /* 1409 */ 65501, 0,
1060
  /* 1411 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0,
1061
  /* 1426 */ 65533, 0,
1062
  /* 1428 */ 65535, 0,
1063
};
1064
1065
extern const LaneBitmask AArch64LaneMaskLists[] = {
1066
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
1067
  /* 2 */ LaneBitmask(0x00000080), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1068
  /* 5 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1069
  /* 10 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1070
  /* 14 */ LaneBitmask(0x00000400), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1071
  /* 17 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1072
  /* 22 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1073
  /* 26 */ LaneBitmask(0x00002000), LaneBitmask(0x00000008), LaneBitmask::getAll(),
1074
  /* 29 */ LaneBitmask(0x00000020), LaneBitmask(0x00000010), LaneBitmask::getAll(),
1075
  /* 32 */ LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
1076
  /* 35 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1077
  /* 38 */ LaneBitmask(0x00004000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1078
  /* 43 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1079
  /* 52 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1080
  /* 59 */ LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
1081
  /* 64 */ LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
1082
  /* 68 */ LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask::getAll(),
1083
  /* 73 */ LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask::getAll(),
1084
  /* 78 */ LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
1085
  /* 83 */ LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
1086
  /* 87 */ LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask::getAll(),
1087
  /* 92 */ LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask::getAll(),
1088
  /* 97 */ LaneBitmask(0x00000008), LaneBitmask(0x00002000), LaneBitmask::getAll(),
1089
  /* 100 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1090
  /* 105 */ LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1091
  /* 114 */ LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1092
  /* 121 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
1093
  /* 130 */ LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
1094
  /* 139 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
1095
};
1096
1097
extern const uint16_t AArch64SubRegIdxLists[] = {
1098
  /* 0 */ 2, 14, 7, 1, 0,
1099
  /* 5 */ 15, 0,
1100
  /* 7 */ 16, 18, 0,
1101
  /* 10 */ 20, 2, 14, 7, 1, 25, 0,
1102
  /* 17 */ 3, 14, 7, 1, 4, 28, 27, 26, 0,
1103
  /* 26 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 66, 68, 0,
1104
  /* 41 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 6, 31, 30, 29, 66, 67, 68, 69, 70, 0,
1105
  /* 63 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 71, 0,
1106
  /* 75 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 71, 73, 74, 76, 79, 0,
1107
  /* 96 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 13, 40, 42, 41, 39, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 0,
1108
  /* 128 */ 17, 15, 19, 47, 82, 0,
1109
  /* 134 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 83, 84, 0,
1110
  /* 151 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 83, 84, 86, 88, 89, 91, 94, 96, 0,
1111
  /* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0,
1112
};
1113
1114
extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = {
1115
  { 65535, 65535 },
1116
  { 0, 8 }, // bsub
1117
  { 0, 32 },  // dsub
1118
  { 0, 64 },  // dsub0
1119
  { 0, 64 },  // dsub1
1120
  { 0, 64 },  // dsub2
1121
  { 0, 64 },  // dsub3
1122
  { 0, 16 },  // hsub
1123
  { 0, 64 },  // qhisub
1124
  { 0, 64 },  // qsub
1125
  { 0, 128 }, // qsub0
1126
  { 0, 128 }, // qsub1
1127
  { 0, 128 }, // qsub2
1128
  { 0, 128 }, // qsub3
1129
  { 0, 32 },  // ssub
1130
  { 0, 32 },  // sub_32
1131
  { 0, 32 },  // sube32
1132
  { 0, 64 },  // sube64
1133
  { 0, 32 },  // subo32
1134
  { 0, 64 },  // subo64
1135
  { 0, 128 }, // zsub
1136
  { 65535, 128 }, // zsub0
1137
  { 65535, 128 }, // zsub1
1138
  { 65535, 128 }, // zsub2
1139
  { 65535, 128 }, // zsub3
1140
  { 0, 128 }, // zsub_hi
1141
  { 0, 8 }, // dsub1_then_bsub
1142
  { 0, 16 },  // dsub1_then_hsub
1143
  { 0, 32 },  // dsub1_then_ssub
1144
  { 0, 8 }, // dsub3_then_bsub
1145
  { 0, 16 },  // dsub3_then_hsub
1146
  { 0, 32 },  // dsub3_then_ssub
1147
  { 0, 8 }, // dsub2_then_bsub
1148
  { 0, 16 },  // dsub2_then_hsub
1149
  { 0, 32 },  // dsub2_then_ssub
1150
  { 0, 8 }, // qsub1_then_bsub
1151
  { 0, 32 },  // qsub1_then_dsub
1152
  { 0, 16 },  // qsub1_then_hsub
1153
  { 0, 32 },  // qsub1_then_ssub
1154
  { 0, 8 }, // qsub3_then_bsub
1155
  { 0, 32 },  // qsub3_then_dsub
1156
  { 0, 16 },  // qsub3_then_hsub
1157
  { 0, 32 },  // qsub3_then_ssub
1158
  { 0, 8 }, // qsub2_then_bsub
1159
  { 0, 32 },  // qsub2_then_dsub
1160
  { 0, 16 },  // qsub2_then_hsub
1161
  { 0, 32 },  // qsub2_then_ssub
1162
  { 0, 32 },  // subo64_then_sub_32
1163
  { 65535, 65535 }, // zsub1_then_bsub
1164
  { 65535, 65535 }, // zsub1_then_dsub
1165
  { 65535, 65535 }, // zsub1_then_hsub
1166
  { 65535, 65535 }, // zsub1_then_ssub
1167
  { 65535, 65535 }, // zsub1_then_zsub
1168
  { 65535, 65535 }, // zsub1_then_zsub_hi
1169
  { 65535, 65535 }, // zsub3_then_bsub
1170
  { 65535, 65535 }, // zsub3_then_dsub
1171
  { 65535, 65535 }, // zsub3_then_hsub
1172
  { 65535, 65535 }, // zsub3_then_ssub
1173
  { 65535, 65535 }, // zsub3_then_zsub
1174
  { 65535, 65535 }, // zsub3_then_zsub_hi
1175
  { 65535, 65535 }, // zsub2_then_bsub
1176
  { 65535, 65535 }, // zsub2_then_dsub
1177
  { 65535, 65535 }, // zsub2_then_hsub
1178
  { 65535, 65535 }, // zsub2_then_ssub
1179
  { 65535, 65535 }, // zsub2_then_zsub
1180
  { 65535, 65535 }, // zsub2_then_zsub_hi
1181
  { 65535, 128 }, // dsub0_dsub1
1182
  { 65535, 192 }, // dsub0_dsub1_dsub2
1183
  { 65535, 128 }, // dsub1_dsub2
1184
  { 65535, 192 }, // dsub1_dsub2_dsub3
1185
  { 65535, 128 }, // dsub2_dsub3
1186
  { 65535, 64 },  // dsub_qsub1_then_dsub
1187
  { 65535, 128 }, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
1188
  { 65535, 96 },  // dsub_qsub1_then_dsub_qsub2_then_dsub
1189
  { 65535, 256 }, // qsub0_qsub1
1190
  { 65535, 384 }, // qsub0_qsub1_qsub2
1191
  { 65535, 256 }, // qsub1_qsub2
1192
  { 65535, 384 }, // qsub1_qsub2_qsub3
1193
  { 65535, 256 }, // qsub2_qsub3
1194
  { 65535, 64 },  // qsub1_then_dsub_qsub2_then_dsub
1195
  { 65535, 96 },  // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
1196
  { 65535, 64 },  // qsub2_then_dsub_qsub3_then_dsub
1197
  { 65535, 64 },  // sub_32_subo64_then_sub_32
1198
  { 65535, 31 },  // dsub_zsub1_then_dsub
1199
  { 65535, 127 }, // zsub_zsub1_then_zsub
1200
  { 65535, 29 },  // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
1201
  { 65535, 30 },  // dsub_zsub1_then_dsub_zsub2_then_dsub
1202
  { 65535, 125 }, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
1203
  { 65535, 126 }, // zsub_zsub1_then_zsub_zsub2_then_zsub
1204
  { 65535, 256 }, // zsub0_zsub1
1205
  { 65535, 384 }, // zsub0_zsub1_zsub2
1206
  { 65535, 256 }, // zsub1_zsub2
1207
  { 65535, 384 }, // zsub1_zsub2_zsub3
1208
  { 65535, 256 }, // zsub2_zsub3
1209
  { 65535, 65534 }, // zsub1_then_dsub_zsub2_then_dsub
1210
  { 65535, 65533 }, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
1211
  { 65535, 65534 }, // zsub1_then_zsub_zsub2_then_zsub
1212
  { 65535, 65533 }, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
1213
  { 65535, 65534 }, // zsub2_then_dsub_zsub3_then_dsub
1214
  { 65535, 65534 }, // zsub2_then_zsub_zsub3_then_zsub
1215
};
1216
1217
extern const char AArch64RegStrings[] = {
1218
  /* 0 */ 'B', '1', '0', 0,
1219
  /* 4 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
1220
  /* 17 */ 'H', '1', '0', 0,
1221
  /* 21 */ 'P', '1', '0', 0,
1222
  /* 25 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
1223
  /* 38 */ 'S', '1', '0', 0,
1224
  /* 42 */ 'W', '1', '0', 0,
1225
  /* 46 */ 'X', '1', '0', 0,
1226
  /* 50 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0,
1227
  /* 63 */ 'B', '2', '0', 0,
1228
  /* 67 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
1229
  /* 83 */ 'H', '2', '0', 0,
1230
  /* 87 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
1231
  /* 103 */ 'S', '2', '0', 0,
1232
  /* 107 */ 'W', '2', '0', 0,
1233
  /* 111 */ 'X', '2', '0', 0,
1234
  /* 115 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0,
1235
  /* 131 */ 'B', '3', '0', 0,
1236
  /* 135 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
1237
  /* 151 */ 'H', '3', '0', 0,
1238
  /* 155 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
1239
  /* 171 */ 'S', '3', '0', 0,
1240
  /* 175 */ 'W', '3', '0', 0,
1241
  /* 179 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0,
1242
  /* 195 */ 'B', '0', 0,
1243
  /* 198 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
1244
  /* 213 */ 'H', '0', 0,
1245
  /* 216 */ 'P', '0', 0,
1246
  /* 219 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
1247
  /* 234 */ 'S', '0', 0,
1248
  /* 237 */ 'W', '0', 0,
1249
  /* 240 */ 'X', '0', 0,
1250
  /* 243 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0,
1251
  /* 258 */ 'B', '1', '1', 0,
1252
  /* 262 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
1253
  /* 276 */ 'H', '1', '1', 0,
1254
  /* 280 */ 'P', '1', '1', 0,
1255
  /* 284 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
1256
  /* 298 */ 'S', '1', '1', 0,
1257
  /* 302 */ 'W', '1', '0', '_', 'W', '1', '1', 0,
1258
  /* 310 */ 'X', '1', '0', '_', 'X', '1', '1', 0,
1259
  /* 318 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0,
1260
  /* 332 */ 'B', '2', '1', 0,
1261
  /* 336 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
1262
  /* 352 */ 'H', '2', '1', 0,
1263
  /* 356 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
1264
  /* 372 */ 'S', '2', '1', 0,
1265
  /* 376 */ 'W', '2', '0', '_', 'W', '2', '1', 0,
1266
  /* 384 */ 'X', '2', '0', '_', 'X', '2', '1', 0,
1267
  /* 392 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0,
1268
  /* 408 */ 'B', '3', '1', 0,
1269
  /* 412 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
1270
  /* 428 */ 'H', '3', '1', 0,
1271
  /* 432 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
1272
  /* 448 */ 'S', '3', '1', 0,
1273
  /* 452 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0,
1274
  /* 468 */ 'B', '1', 0,
1275
  /* 471 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
1276
  /* 485 */ 'H', '1', 0,
1277
  /* 488 */ 'P', '1', 0,
1278
  /* 491 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
1279
  /* 505 */ 'S', '1', 0,
1280
  /* 508 */ 'W', '0', '_', 'W', '1', 0,
1281
  /* 514 */ 'X', '0', '_', 'X', '1', 0,
1282
  /* 520 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0,
1283
  /* 534 */ 'B', '1', '2', 0,
1284
  /* 538 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
1285
  /* 553 */ 'H', '1', '2', 0,
1286
  /* 557 */ 'P', '1', '2', 0,
1287
  /* 561 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
1288
  /* 576 */ 'S', '1', '2', 0,
1289
  /* 580 */ 'W', '1', '2', 0,
1290
  /* 584 */ 'X', '1', '2', 0,
1291
  /* 588 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0,
1292
  /* 603 */ 'B', '2', '2', 0,
1293
  /* 607 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
1294
  /* 623 */ 'H', '2', '2', 0,
1295
  /* 627 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
1296
  /* 643 */ 'S', '2', '2', 0,
1297
  /* 647 */ 'W', '2', '2', 0,
1298
  /* 651 */ 'X', '2', '2', 0,
1299
  /* 655 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0,
1300
  /* 671 */ 'B', '2', 0,
1301
  /* 674 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
1302
  /* 687 */ 'H', '2', 0,
1303
  /* 690 */ 'P', '2', 0,
1304
  /* 693 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
1305
  /* 706 */ 'S', '2', 0,
1306
  /* 709 */ 'W', '2', 0,
1307
  /* 712 */ 'X', '2', 0,
1308
  /* 715 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0,
1309
  /* 728 */ 'B', '1', '3', 0,
1310
  /* 732 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
1311
  /* 748 */ 'H', '1', '3', 0,
1312
  /* 752 */ 'P', '1', '3', 0,
1313
  /* 756 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
1314
  /* 772 */ 'S', '1', '3', 0,
1315
  /* 776 */ 'W', '1', '2', '_', 'W', '1', '3', 0,
1316
  /* 784 */ 'X', '1', '2', '_', 'X', '1', '3', 0,
1317
  /* 792 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0,
1318
  /* 808 */ 'B', '2', '3', 0,
1319
  /* 812 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
1320
  /* 828 */ 'H', '2', '3', 0,
1321
  /* 832 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
1322
  /* 848 */ 'S', '2', '3', 0,
1323
  /* 852 */ 'W', '2', '2', '_', 'W', '2', '3', 0,
1324
  /* 860 */ 'X', '2', '2', '_', 'X', '2', '3', 0,
1325
  /* 868 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0,
1326
  /* 884 */ 'B', '3', 0,
1327
  /* 887 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
1328
  /* 899 */ 'H', '3', 0,
1329
  /* 902 */ 'P', '3', 0,
1330
  /* 905 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
1331
  /* 917 */ 'S', '3', 0,
1332
  /* 920 */ 'W', '2', '_', 'W', '3', 0,
1333
  /* 926 */ 'X', '2', '_', 'X', '3', 0,
1334
  /* 932 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0,
1335
  /* 944 */ 'B', '1', '4', 0,
1336
  /* 948 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
1337
  /* 964 */ 'H', '1', '4', 0,
1338
  /* 968 */ 'P', '1', '4', 0,
1339
  /* 972 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
1340
  /* 988 */ 'S', '1', '4', 0,
1341
  /* 992 */ 'W', '1', '4', 0,
1342
  /* 996 */ 'X', '1', '4', 0,
1343
  /* 1000 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0,
1344
  /* 1016 */ 'B', '2', '4', 0,
1345
  /* 1020 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
1346
  /* 1036 */ 'H', '2', '4', 0,
1347
  /* 1040 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
1348
  /* 1056 */ 'S', '2', '4', 0,
1349
  /* 1060 */ 'W', '2', '4', 0,
1350
  /* 1064 */ 'X', '2', '4', 0,
1351
  /* 1068 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0,
1352
  /* 1084 */ 'B', '4', 0,
1353
  /* 1087 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
1354
  /* 1099 */ 'H', '4', 0,
1355
  /* 1102 */ 'P', '4', 0,
1356
  /* 1105 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
1357
  /* 1117 */ 'S', '4', 0,
1358
  /* 1120 */ 'W', '4', 0,
1359
  /* 1123 */ 'X', '4', 0,
1360
  /* 1126 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0,
1361
  /* 1138 */ 'B', '1', '5', 0,
1362
  /* 1142 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
1363
  /* 1158 */ 'H', '1', '5', 0,
1364
  /* 1162 */ 'P', '1', '5', 0,
1365
  /* 1166 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
1366
  /* 1182 */ 'S', '1', '5', 0,
1367
  /* 1186 */ 'W', '1', '4', '_', 'W', '1', '5', 0,
1368
  /* 1194 */ 'X', '1', '4', '_', 'X', '1', '5', 0,
1369
  /* 1202 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0,
1370
  /* 1218 */ 'B', '2', '5', 0,
1371
  /* 1222 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
1372
  /* 1238 */ 'H', '2', '5', 0,
1373
  /* 1242 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
1374
  /* 1258 */ 'S', '2', '5', 0,
1375
  /* 1262 */ 'W', '2', '4', '_', 'W', '2', '5', 0,
1376
  /* 1270 */ 'X', '2', '4', '_', 'X', '2', '5', 0,
1377
  /* 1278 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0,
1378
  /* 1294 */ 'B', '5', 0,
1379
  /* 1297 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
1380
  /* 1309 */ 'H', '5', 0,
1381
  /* 1312 */ 'P', '5', 0,
1382
  /* 1315 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
1383
  /* 1327 */ 'S', '5', 0,
1384
  /* 1330 */ 'W', '4', '_', 'W', '5', 0,
1385
  /* 1336 */ 'X', '4', '_', 'X', '5', 0,
1386
  /* 1342 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0,
1387
  /* 1354 */ 'B', '1', '6', 0,
1388
  /* 1358 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
1389
  /* 1374 */ 'H', '1', '6', 0,
1390
  /* 1378 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
1391
  /* 1394 */ 'S', '1', '6', 0,
1392
  /* 1398 */ 'W', '1', '6', 0,
1393
  /* 1402 */ 'X', '1', '6', 0,
1394
  /* 1406 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0,
1395
  /* 1422 */ 'B', '2', '6', 0,
1396
  /* 1426 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
1397
  /* 1442 */ 'H', '2', '6', 0,
1398
  /* 1446 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
1399
  /* 1462 */ 'S', '2', '6', 0,
1400
  /* 1466 */ 'W', '2', '6', 0,
1401
  /* 1470 */ 'X', '2', '6', 0,
1402
  /* 1474 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0,
1403
  /* 1490 */ 'B', '6', 0,
1404
  /* 1493 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
1405
  /* 1505 */ 'H', '6', 0,
1406
  /* 1508 */ 'P', '6', 0,
1407
  /* 1511 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
1408
  /* 1523 */ 'S', '6', 0,
1409
  /* 1526 */ 'W', '6', 0,
1410
  /* 1529 */ 'X', '6', 0,
1411
  /* 1532 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0,
1412
  /* 1544 */ 'B', '1', '7', 0,
1413
  /* 1548 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
1414
  /* 1564 */ 'H', '1', '7', 0,
1415
  /* 1568 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
1416
  /* 1584 */ 'S', '1', '7', 0,
1417
  /* 1588 */ 'W', '1', '6', '_', 'W', '1', '7', 0,
1418
  /* 1596 */ 'X', '1', '6', '_', 'X', '1', '7', 0,
1419
  /* 1604 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0,
1420
  /* 1620 */ 'B', '2', '7', 0,
1421
  /* 1624 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
1422
  /* 1640 */ 'H', '2', '7', 0,
1423
  /* 1644 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
1424
  /* 1660 */ 'S', '2', '7', 0,
1425
  /* 1664 */ 'W', '2', '6', '_', 'W', '2', '7', 0,
1426
  /* 1672 */ 'X', '2', '6', '_', 'X', '2', '7', 0,
1427
  /* 1680 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0,
1428
  /* 1696 */ 'B', '7', 0,
1429
  /* 1699 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
1430
  /* 1711 */ 'H', '7', 0,
1431
  /* 1714 */ 'P', '7', 0,
1432
  /* 1717 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
1433
  /* 1729 */ 'S', '7', 0,
1434
  /* 1732 */ 'W', '6', '_', 'W', '7', 0,
1435
  /* 1738 */ 'X', '6', '_', 'X', '7', 0,
1436
  /* 1744 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0,
1437
  /* 1756 */ 'B', '1', '8', 0,
1438
  /* 1760 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
1439
  /* 1776 */ 'H', '1', '8', 0,
1440
  /* 1780 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
1441
  /* 1796 */ 'S', '1', '8', 0,
1442
  /* 1800 */ 'W', '1', '8', 0,
1443
  /* 1804 */ 'X', '1', '8', 0,
1444
  /* 1808 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0,
1445
  /* 1824 */ 'B', '2', '8', 0,
1446
  /* 1828 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
1447
  /* 1844 */ 'H', '2', '8', 0,
1448
  /* 1848 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
1449
  /* 1864 */ 'S', '2', '8', 0,
1450
  /* 1868 */ 'W', '2', '8', 0,
1451
  /* 1872 */ 'X', '2', '8', 0,
1452
  /* 1876 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0,
1453
  /* 1892 */ 'B', '8', 0,
1454
  /* 1895 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
1455
  /* 1907 */ 'H', '8', 0,
1456
  /* 1910 */ 'P', '8', 0,
1457
  /* 1913 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
1458
  /* 1925 */ 'S', '8', 0,
1459
  /* 1928 */ 'W', '8', 0,
1460
  /* 1931 */ 'X', '8', 0,
1461
  /* 1934 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0,
1462
  /* 1946 */ 'B', '1', '9', 0,
1463
  /* 1950 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
1464
  /* 1966 */ 'H', '1', '9', 0,
1465
  /* 1970 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
1466
  /* 1986 */ 'S', '1', '9', 0,
1467
  /* 1990 */ 'W', '1', '8', '_', 'W', '1', '9', 0,
1468
  /* 1998 */ 'X', '1', '8', '_', 'X', '1', '9', 0,
1469
  /* 2006 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0,
1470
  /* 2022 */ 'B', '2', '9', 0,
1471
  /* 2026 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
1472
  /* 2042 */ 'H', '2', '9', 0,
1473
  /* 2046 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
1474
  /* 2062 */ 'S', '2', '9', 0,
1475
  /* 2066 */ 'W', '2', '8', '_', 'W', '2', '9', 0,
1476
  /* 2074 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0,
1477
  /* 2090 */ 'B', '9', 0,
1478
  /* 2093 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
1479
  /* 2105 */ 'H', '9', 0,
1480
  /* 2108 */ 'P', '9', 0,
1481
  /* 2111 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
1482
  /* 2123 */ 'S', '9', 0,
1483
  /* 2126 */ 'W', '8', '_', 'W', '9', 0,
1484
  /* 2132 */ 'X', '8', '_', 'X', '9', 0,
1485
  /* 2138 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0,
1486
  /* 2150 */ 'Z', '1', '0', '_', 'H', 'I', 0,
1487
  /* 2157 */ 'Z', '2', '0', '_', 'H', 'I', 0,
1488
  /* 2164 */ 'Z', '3', '0', '_', 'H', 'I', 0,
1489
  /* 2171 */ 'Z', '0', '_', 'H', 'I', 0,
1490
  /* 2177 */ 'Z', '1', '1', '_', 'H', 'I', 0,
1491
  /* 2184 */ 'Z', '2', '1', '_', 'H', 'I', 0,
1492
  /* 2191 */ 'Z', '3', '1', '_', 'H', 'I', 0,
1493
  /* 2198 */ 'Z', '1', '_', 'H', 'I', 0,
1494
  /* 2204 */ 'Z', '1', '2', '_', 'H', 'I', 0,
1495
  /* 2211 */ 'Z', '2', '2', '_', 'H', 'I', 0,
1496
  /* 2218 */ 'Z', '2', '_', 'H', 'I', 0,
1497
  /* 2224 */ 'Z', '1', '3', '_', 'H', 'I', 0,
1498
  /* 2231 */ 'Z', '2', '3', '_', 'H', 'I', 0,
1499
  /* 2238 */ 'Z', '3', '_', 'H', 'I', 0,
1500
  /* 2244 */ 'Z', '1', '4', '_', 'H', 'I', 0,
1501
  /* 2251 */ 'Z', '2', '4', '_', 'H', 'I', 0,
1502
  /* 2258 */ 'Z', '4', '_', 'H', 'I', 0,
1503
  /* 2264 */ 'Z', '1', '5', '_', 'H', 'I', 0,
1504
  /* 2271 */ 'Z', '2', '5', '_', 'H', 'I', 0,
1505
  /* 2278 */ 'Z', '5', '_', 'H', 'I', 0,
1506
  /* 2284 */ 'Z', '1', '6', '_', 'H', 'I', 0,
1507
  /* 2291 */ 'Z', '2', '6', '_', 'H', 'I', 0,
1508
  /* 2298 */ 'Z', '6', '_', 'H', 'I', 0,
1509
  /* 2304 */ 'Z', '1', '7', '_', 'H', 'I', 0,
1510
  /* 2311 */ 'Z', '2', '7', '_', 'H', 'I', 0,
1511
  /* 2318 */ 'Z', '7', '_', 'H', 'I', 0,
1512
  /* 2324 */ 'Z', '1', '8', '_', 'H', 'I', 0,
1513
  /* 2331 */ 'Z', '2', '8', '_', 'H', 'I', 0,
1514
  /* 2338 */ 'Z', '8', '_', 'H', 'I', 0,
1515
  /* 2344 */ 'Z', '1', '9', '_', 'H', 'I', 0,
1516
  /* 2351 */ 'Z', '2', '9', '_', 'H', 'I', 0,
1517
  /* 2358 */ 'Z', '9', '_', 'H', 'I', 0,
1518
  /* 2364 */ 'X', '2', '8', '_', 'F', 'P', 0,
1519
  /* 2371 */ 'W', 'S', 'P', 0,
1520
  /* 2375 */ 'F', 'F', 'R', 0,
1521
  /* 2379 */ 'L', 'R', 0,
1522
  /* 2382 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0,
1523
  /* 2390 */ 'L', 'R', '_', 'X', 'Z', 'R', 0,
1524
  /* 2397 */ 'N', 'Z', 'C', 'V', 0,
1525
};
1526
1527
extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
1528
  { 3, 0, 0, 0, 0, 0 },
1529
  { 2375, 8, 8, 4, 22849, 0 },
1530
  { 2368, 929, 1088, 5, 22849, 27 },
1531
  { 2379, 929, 1086, 5, 22849, 27 },
1532
  { 2397, 8, 8, 4, 22849, 0 },
1533
  { 2372, 7, 8, 5, 6608, 27 },
1534
  { 2371, 8, 1428, 4, 6608, 0 },
1535
  { 2386, 8, 417, 4, 6640, 0 },
1536
  { 2393, 1428, 1084, 5, 6640, 27 },
1537
  { 195, 8, 226, 4, 22817, 0 },
1538
  { 468, 8, 308, 4, 22817, 0 },
1539
  { 671, 8, 499, 4, 22817, 0 },
1540
  { 884, 8, 162, 4, 22817, 0 },
1541
  { 1084, 8, 162, 4, 22817, 0 },
1542
  { 1294, 8, 162, 4, 22817, 0 },
1543
  { 1490, 8, 162, 4, 22817, 0 },
1544
  { 1696, 8, 162, 4, 22817, 0 },
1545
  { 1892, 8, 162, 4, 22817, 0 },
1546
  { 2090, 8, 162, 4, 22817, 0 },
1547
  { 0, 8, 162, 4, 22817, 0 },
1548
  { 258, 8, 162, 4, 22817, 0 },
1549
  { 534, 8, 162, 4, 22817, 0 },
1550
  { 728, 8, 162, 4, 22817, 0 },
1551
  { 944, 8, 162, 4, 22817, 0 },
1552
  { 1138, 8, 162, 4, 22817, 0 },
1553
  { 1354, 8, 162, 4, 22817, 0 },
1554
  { 1544, 8, 162, 4, 22817, 0 },
1555
  { 1756, 8, 162, 4, 22817, 0 },
1556
  { 1946, 8, 162, 4, 22817, 0 },
1557
  { 63, 8, 162, 4, 22817, 0 },
1558
  { 332, 8, 162, 4, 22817, 0 },
1559
  { 603, 8, 162, 4, 22817, 0 },
1560
  { 808, 8, 162, 4, 22817, 0 },
1561
  { 1016, 8, 162, 4, 22817, 0 },
1562
  { 1218, 8, 162, 4, 22817, 0 },
1563
  { 1422, 8, 162, 4, 22817, 0 },
1564
  { 1620, 8, 162, 4, 22817, 0 },
1565
  { 1824, 8, 162, 4, 22817, 0 },
1566
  { 2022, 8, 162, 4, 22817, 0 },
1567
  { 131, 8, 162, 4, 22817, 0 },
1568
  { 408, 8, 162, 4, 22817, 0 },
1569
  { 210, 1229, 229, 1, 22545, 3 },
1570
  { 482, 1229, 311, 1, 22545, 3 },
1571
  { 684, 1229, 502, 1, 22545, 3 },
1572
  { 896, 1229, 165, 1, 22545, 3 },
1573
  { 1096, 1229, 165, 1, 22545, 3 },
1574
  { 1306, 1229, 165, 1, 22545, 3 },
1575
  { 1502, 1229, 165, 1, 22545, 3 },
1576
  { 1708, 1229, 165, 1, 22545, 3 },
1577
  { 1904, 1229, 165, 1, 22545, 3 },
1578
  { 2102, 1229, 165, 1, 22545, 3 },
1579
  { 13, 1229, 165, 1, 22545, 3 },
1580
  { 272, 1229, 165, 1, 22545, 3 },
1581
  { 549, 1229, 165, 1, 22545, 3 },
1582
  { 744, 1229, 165, 1, 22545, 3 },
1583
  { 960, 1229, 165, 1, 22545, 3 },
1584
  { 1154, 1229, 165, 1, 22545, 3 },
1585
  { 1370, 1229, 165, 1, 22545, 3 },
1586
  { 1560, 1229, 165, 1, 22545, 3 },
1587
  { 1772, 1229, 165, 1, 22545, 3 },
1588
  { 1962, 1229, 165, 1, 22545, 3 },
1589
  { 79, 1229, 165, 1, 22545, 3 },
1590
  { 348, 1229, 165, 1, 22545, 3 },
1591
  { 619, 1229, 165, 1, 22545, 3 },
1592
  { 824, 1229, 165, 1, 22545, 3 },
1593
  { 1032, 1229, 165, 1, 22545, 3 },
1594
  { 1234, 1229, 165, 1, 22545, 3 },
1595
  { 1438, 1229, 165, 1, 22545, 3 },
1596
  { 1636, 1229, 165, 1, 22545, 3 },
1597
  { 1840, 1229, 165, 1, 22545, 3 },
1598
  { 2038, 1229, 165, 1, 22545, 3 },
1599
  { 147, 1229, 165, 1, 22545, 3 },
1600
  { 424, 1229, 165, 1, 22545, 3 },
1601
  { 213, 1231, 227, 3, 19553, 3 },
1602
  { 485, 1231, 309, 3, 19553, 3 },
1603
  { 687, 1231, 500, 3, 19553, 3 },
1604
  { 899, 1231, 163, 3, 19553, 3 },
1605
  { 1099, 1231, 163, 3, 19553, 3 },
1606
  { 1309, 1231, 163, 3, 19553, 3 },
1607
  { 1505, 1231, 163, 3, 19553, 3 },
1608
  { 1711, 1231, 163, 3, 19553, 3 },
1609
  { 1907, 1231, 163, 3, 19553, 3 },
1610
  { 2105, 1231, 163, 3, 19553, 3 },
1611
  { 17, 1231, 163, 3, 19553, 3 },
1612
  { 276, 1231, 163, 3, 19553, 3 },
1613
  { 553, 1231, 163, 3, 19553, 3 },
1614
  { 748, 1231, 163, 3, 19553, 3 },
1615
  { 964, 1231, 163, 3, 19553, 3 },
1616
  { 1158, 1231, 163, 3, 19553, 3 },
1617
  { 1374, 1231, 163, 3, 19553, 3 },
1618
  { 1564, 1231, 163, 3, 19553, 3 },
1619
  { 1776, 1231, 163, 3, 19553, 3 },
1620
  { 1966, 1231, 163, 3, 19553, 3 },
1621
  { 83, 1231, 163, 3, 19553, 3 },
1622
  { 352, 1231, 163, 3, 19553, 3 },
1623
  { 623, 1231, 163, 3, 19553, 3 },
1624
  { 828, 1231, 163, 3, 19553, 3 },
1625
  { 1036, 1231, 163, 3, 19553, 3 },
1626
  { 1238, 1231, 163, 3, 19553, 3 },
1627
  { 1442, 1231, 163, 3, 19553, 3 },
1628
  { 1640, 1231, 163, 3, 19553, 3 },
1629
  { 1844, 1231, 163, 3, 19553, 3 },
1630
  { 2042, 1231, 163, 3, 19553, 3 },
1631
  { 151, 1231, 163, 3, 19553, 3 },
1632
  { 428, 1231, 163, 3, 19553, 3 },
1633
  { 216, 8, 8, 4, 19553, 0 },
1634
  { 488, 8, 8, 4, 19553, 0 },
1635
  { 690, 8, 8, 4, 19553, 0 },
1636
  { 902, 8, 8, 4, 19553, 0 },
1637
  { 1102, 8, 8, 4, 19553, 0 },
1638
  { 1312, 8, 8, 4, 19553, 0 },
1639
  { 1508, 8, 8, 4, 19553, 0 },
1640
  { 1714, 8, 8, 4, 19553, 0 },
1641
  { 1910, 8, 8, 4, 19553, 0 },
1642
  { 2108, 8, 8, 4, 19553, 0 },
1643
  { 21, 8, 8, 4, 19553, 0 },
1644
  { 280, 8, 8, 4, 19553, 0 },
1645
  { 557, 8, 8, 4, 19553, 0 },
1646
  { 752, 8, 8, 4, 19553, 0 },
1647
  { 968, 8, 8, 4, 19553, 0 },
1648
  { 1162, 8, 8, 4, 19553, 0 },
1649
  { 231, 1242, 259, 0, 17649, 3 },
1650
  { 502, 1242, 341, 0, 17649, 3 },
1651
  { 703, 1242, 532, 0, 17649, 3 },
1652
  { 914, 1242, 195, 0, 17649, 3 },
1653
  { 1114, 1242, 195, 0, 17649, 3 },
1654
  { 1324, 1242, 195, 0, 17649, 3 },
1655
  { 1520, 1242, 195, 0, 17649, 3 },
1656
  { 1726, 1242, 195, 0, 17649, 3 },
1657
  { 1922, 1242, 195, 0, 17649, 3 },
1658
  { 2120, 1242, 195, 0, 17649, 3 },
1659
  { 34, 1242, 195, 0, 17649, 3 },
1660
  { 294, 1242, 195, 0, 17649, 3 },
1661
  { 572, 1242, 195, 0, 17649, 3 },
1662
  { 768, 1242, 195, 0, 17649, 3 },
1663
  { 984, 1242, 195, 0, 17649, 3 },
1664
  { 1178, 1242, 195, 0, 17649, 3 },
1665
  { 1390, 1242, 195, 0, 17649, 3 },
1666
  { 1580, 1242, 195, 0, 17649, 3 },
1667
  { 1792, 1242, 195, 0, 17649, 3 },
1668
  { 1982, 1242, 195, 0, 17649, 3 },
1669
  { 99, 1242, 195, 0, 17649, 3 },
1670
  { 368, 1242, 195, 0, 17649, 3 },
1671
  { 639, 1242, 195, 0, 17649, 3 },
1672
  { 844, 1242, 195, 0, 17649, 3 },
1673
  { 1052, 1242, 195, 0, 17649, 3 },
1674
  { 1254, 1242, 195, 0, 17649, 3 },
1675
  { 1458, 1242, 195, 0, 17649, 3 },
1676
  { 1656, 1242, 195, 0, 17649, 3 },
1677
  { 1860, 1242, 195, 0, 17649, 3 },
1678
  { 2058, 1242, 195, 0, 17649, 3 },
1679
  { 167, 1242, 195, 0, 17649, 3 },
1680
  { 444, 1242, 195, 0, 17649, 3 },
1681
  { 234, 1230, 228, 2, 17585, 3 },
1682
  { 505, 1230, 310, 2, 17585, 3 },
1683
  { 706, 1230, 501, 2, 17585, 3 },
1684
  { 917, 1230, 164, 2, 17585, 3 },
1685
  { 1117, 1230, 164, 2, 17585, 3 },
1686
  { 1327, 1230, 164, 2, 17585, 3 },
1687
  { 1523, 1230, 164, 2, 17585, 3 },
1688
  { 1729, 1230, 164, 2, 17585, 3 },
1689
  { 1925, 1230, 164, 2, 17585, 3 },
1690
  { 2123, 1230, 164, 2, 17585, 3 },
1691
  { 38, 1230, 164, 2, 17585, 3 },
1692
  { 298, 1230, 164, 2, 17585, 3 },
1693
  { 576, 1230, 164, 2, 17585, 3 },
1694
  { 772, 1230, 164, 2, 17585, 3 },
1695
  { 988, 1230, 164, 2, 17585, 3 },
1696
  { 1182, 1230, 164, 2, 17585, 3 },
1697
  { 1394, 1230, 164, 2, 17585, 3 },
1698
  { 1584, 1230, 164, 2, 17585, 3 },
1699
  { 1796, 1230, 164, 2, 17585, 3 },
1700
  { 1986, 1230, 164, 2, 17585, 3 },
1701
  { 103, 1230, 164, 2, 17585, 3 },
1702
  { 372, 1230, 164, 2, 17585, 3 },
1703
  { 643, 1230, 164, 2, 17585, 3 },
1704
  { 848, 1230, 164, 2, 17585, 3 },
1705
  { 1056, 1230, 164, 2, 17585, 3 },
1706
  { 1258, 1230, 164, 2, 17585, 3 },
1707
  { 1462, 1230, 164, 2, 17585, 3 },
1708
  { 1660, 1230, 164, 2, 17585, 3 },
1709
  { 1864, 1230, 164, 2, 17585, 3 },
1710
  { 2062, 1230, 164, 2, 17585, 3 },
1711
  { 171, 1230, 164, 2, 17585, 3 },
1712
  { 448, 1230, 164, 2, 17585, 3 },
1713
  { 237, 8, 481, 4, 17617, 0 },
1714
  { 511, 8, 477, 4, 17617, 0 },
1715
  { 709, 8, 477, 4, 17617, 0 },
1716
  { 923, 8, 473, 4, 17617, 0 },
1717
  { 1120, 8, 473, 4, 17617, 0 },
1718
  { 1333, 8, 469, 4, 17617, 0 },
1719
  { 1526, 8, 469, 4, 17617, 0 },
1720
  { 1735, 8, 465, 4, 17617, 0 },
1721
  { 1928, 8, 465, 4, 17617, 0 },
1722
  { 2129, 8, 461, 4, 17617, 0 },
1723
  { 42, 8, 461, 4, 17617, 0 },
1724
  { 306, 8, 457, 4, 17617, 0 },
1725
  { 580, 8, 457, 4, 17617, 0 },
1726
  { 780, 8, 453, 4, 17617, 0 },
1727
  { 992, 8, 453, 4, 17617, 0 },
1728
  { 1190, 8, 449, 4, 17617, 0 },
1729
  { 1398, 8, 449, 4, 17617, 0 },
1730
  { 1592, 8, 445, 4, 17617, 0 },
1731
  { 1800, 8, 445, 4, 17617, 0 },
1732
  { 1994, 8, 441, 4, 17617, 0 },
1733
  { 107, 8, 441, 4, 17617, 0 },
1734
  { 380, 8, 437, 4, 17617, 0 },
1735
  { 647, 8, 437, 4, 17617, 0 },
1736
  { 856, 8, 433, 4, 17617, 0 },
1737
  { 1060, 8, 433, 4, 17617, 0 },
1738
  { 1266, 8, 429, 4, 17617, 0 },
1739
  { 1466, 8, 429, 4, 17617, 0 },
1740
  { 1668, 8, 425, 4, 17617, 0 },
1741
  { 1868, 8, 399, 4, 17617, 0 },
1742
  { 2070, 8, 403, 4, 17441, 0 },
1743
  { 175, 8, 421, 4, 17441, 0 },
1744
  { 240, 1424, 986, 5, 17553, 27 },
1745
  { 517, 1424, 980, 5, 17553, 27 },
1746
  { 712, 1424, 980, 5, 17553, 27 },
1747
  { 929, 1424, 974, 5, 17553, 27 },
1748
  { 1123, 1424, 974, 5, 17553, 27 },
1749
  { 1339, 1424, 972, 5, 17553, 27 },
1750
  { 1529, 1424, 972, 5, 17553, 27 },
1751
  { 1741, 1424, 970, 5, 17553, 27 },
1752
  { 1931, 1424, 970, 5, 17553, 27 },
1753
  { 2135, 1424, 958, 5, 17553, 27 },
1754
  { 46, 1424, 958, 5, 17553, 27 },
1755
  { 314, 1424, 956, 5, 17553, 27 },
1756
  { 584, 1424, 956, 5, 17553, 27 },
1757
  { 788, 1424, 954, 5, 17553, 27 },
1758
  { 996, 1424, 954, 5, 17553, 27 },
1759
  { 1198, 1424, 952, 5, 17553, 27 },
1760
  { 1402, 1424, 952, 5, 17553, 27 },
1761
  { 1600, 1424, 950, 5, 17553, 27 },
1762
  { 1804, 1424, 950, 5, 17553, 27 },
1763
  { 2002, 1424, 948, 5, 17553, 27 },
1764
  { 111, 1424, 948, 5, 17553, 27 },
1765
  { 388, 1424, 946, 5, 17553, 27 },
1766
  { 651, 1424, 946, 5, 17553, 27 },
1767
  { 864, 1424, 944, 5, 17553, 27 },
1768
  { 1064, 1424, 944, 5, 17553, 27 },
1769
  { 1274, 1424, 942, 5, 17553, 27 },
1770
  { 1470, 1424, 942, 5, 17553, 27 },
1771
  { 1676, 1424, 940, 5, 17553, 27 },
1772
  { 1872, 1424, 938, 5, 17553, 27 },
1773
  { 255, 931, 280, 10, 9745, 35 },
1774
  { 531, 931, 362, 10, 9745, 35 },
1775
  { 725, 931, 553, 10, 9745, 35 },
1776
  { 941, 931, 216, 10, 9745, 35 },
1777
  { 1135, 931, 216, 10, 9745, 35 },
1778
  { 1351, 931, 216, 10, 9745, 35 },
1779
  { 1541, 931, 216, 10, 9745, 35 },
1780
  { 1753, 931, 216, 10, 9745, 35 },
1781
  { 1943, 931, 216, 10, 9745, 35 },
1782
  { 2147, 931, 216, 10, 9745, 35 },
1783
  { 59, 931, 216, 10, 9745, 35 },
1784
  { 328, 931, 216, 10, 9745, 35 },
1785
  { 599, 931, 216, 10, 9745, 35 },
1786
  { 804, 931, 216, 10, 9745, 35 },
1787
  { 1012, 931, 216, 10, 9745, 35 },
1788
  { 1214, 931, 216, 10, 9745, 35 },
1789
  { 1418, 931, 216, 10, 9745, 35 },
1790
  { 1616, 931, 216, 10, 9745, 35 },
1791
  { 1820, 931, 216, 10, 9745, 35 },
1792
  { 2018, 931, 216, 10, 9745, 35 },
1793
  { 127, 931, 216, 10, 9745, 35 },
1794
  { 404, 931, 216, 10, 9745, 35 },
1795
  { 667, 931, 216, 10, 9745, 35 },
1796
  { 880, 931, 216, 10, 9745, 35 },
1797
  { 1080, 931, 216, 10, 9745, 35 },
1798
  { 1290, 931, 216, 10, 9745, 35 },
1799
  { 1486, 931, 216, 10, 9745, 35 },
1800
  { 1692, 931, 216, 10, 9745, 35 },
1801
  { 1888, 931, 216, 10, 9745, 35 },
1802
  { 2086, 931, 216, 10, 9745, 35 },
1803
  { 191, 931, 216, 10, 9745, 35 },
1804
  { 464, 931, 216, 10, 9745, 35 },
1805
  { 2171, 8, 279, 4, 17521, 0 },
1806
  { 2198, 8, 361, 4, 17521, 0 },
1807
  { 2218, 8, 552, 4, 17521, 0 },
1808
  { 2238, 8, 215, 4, 17521, 0 },
1809
  { 2258, 8, 215, 4, 17521, 0 },
1810
  { 2278, 8, 215, 4, 17521, 0 },
1811
  { 2298, 8, 215, 4, 17521, 0 },
1812
  { 2318, 8, 215, 4, 17521, 0 },
1813
  { 2338, 8, 215, 4, 17521, 0 },
1814
  { 2358, 8, 215, 4, 17521, 0 },
1815
  { 2150, 8, 215, 4, 17521, 0 },
1816
  { 2177, 8, 215, 4, 17521, 0 },
1817
  { 2204, 8, 215, 4, 17521, 0 },
1818
  { 2224, 8, 215, 4, 17521, 0 },
1819
  { 2244, 8, 215, 4, 17521, 0 },
1820
  { 2264, 8, 215, 4, 17521, 0 },
1821
  { 2284, 8, 215, 4, 17521, 0 },
1822
  { 2304, 8, 215, 4, 17521, 0 },
1823
  { 2324, 8, 215, 4, 17521, 0 },
1824
  { 2344, 8, 215, 4, 17521, 0 },
1825
  { 2157, 8, 215, 4, 17521, 0 },
1826
  { 2184, 8, 215, 4, 17521, 0 },
1827
  { 2211, 8, 215, 4, 17521, 0 },
1828
  { 2231, 8, 215, 4, 17521, 0 },
1829
  { 2251, 8, 215, 4, 17521, 0 },
1830
  { 2271, 8, 215, 4, 17521, 0 },
1831
  { 2291, 8, 215, 4, 17521, 0 },
1832
  { 2311, 8, 215, 4, 17521, 0 },
1833
  { 2331, 8, 215, 4, 17521, 0 },
1834
  { 2351, 8, 215, 4, 17521, 0 },
1835
  { 2164, 8, 215, 4, 17521, 0 },
1836
  { 2191, 8, 215, 4, 17521, 0 },
1837
  { 479, 1233, 372, 17, 2545, 61 },
1838
  { 681, 1233, 574, 17, 2545, 61 },
1839
  { 893, 1233, 290, 17, 2545, 61 },
1840
  { 1093, 1233, 290, 17, 2545, 61 },
1841
  { 1303, 1233, 290, 17, 2545, 61 },
1842
  { 1499, 1233, 290, 17, 2545, 61 },
1843
  { 1705, 1233, 290, 17, 2545, 61 },
1844
  { 1901, 1233, 290, 17, 2545, 61 },
1845
  { 2099, 1233, 290, 17, 2545, 61 },
1846
  { 10, 1233, 290, 17, 2545, 61 },
1847
  { 268, 1233, 290, 17, 2545, 61 },
1848
  { 545, 1233, 290, 17, 2545, 61 },
1849
  { 740, 1233, 290, 17, 2545, 61 },
1850
  { 956, 1233, 290, 17, 2545, 61 },
1851
  { 1150, 1233, 290, 17, 2545, 61 },
1852
  { 1366, 1233, 290, 17, 2545, 61 },
1853
  { 1556, 1233, 290, 17, 2545, 61 },
1854
  { 1768, 1233, 290, 17, 2545, 61 },
1855
  { 1958, 1233, 290, 17, 2545, 61 },
1856
  { 75, 1233, 290, 17, 2545, 61 },
1857
  { 344, 1233, 290, 17, 2545, 61 },
1858
  { 615, 1233, 290, 17, 2545, 61 },
1859
  { 820, 1233, 290, 17, 2545, 61 },
1860
  { 1028, 1233, 290, 17, 2545, 61 },
1861
  { 1230, 1233, 290, 17, 2545, 61 },
1862
  { 1434, 1233, 290, 17, 2545, 61 },
1863
  { 1632, 1233, 290, 17, 2545, 61 },
1864
  { 1836, 1233, 290, 17, 2545, 61 },
1865
  { 2034, 1233, 290, 17, 2545, 61 },
1866
  { 143, 1233, 290, 17, 2545, 61 },
1867
  { 420, 1233, 290, 17, 2545, 61 },
1868
  { 206, 1224, 290, 17, 9472, 2 },
1869
  { 887, 1365, 926, 41, 225, 68 },
1870
  { 1087, 1365, 926, 41, 225, 68 },
1871
  { 1297, 1365, 926, 41, 225, 68 },
1872
  { 1493, 1365, 926, 41, 225, 68 },
1873
  { 1699, 1365, 926, 41, 225, 68 },
1874
  { 1895, 1365, 926, 41, 225, 68 },
1875
  { 2093, 1365, 926, 41, 225, 68 },
1876
  { 4, 1365, 926, 41, 225, 68 },
1877
  { 262, 1365, 926, 41, 225, 68 },
1878
  { 538, 1365, 926, 41, 225, 68 },
1879
  { 732, 1365, 926, 41, 225, 68 },
1880
  { 948, 1365, 926, 41, 225, 68 },
1881
  { 1142, 1365, 926, 41, 225, 68 },
1882
  { 1358, 1365, 926, 41, 225, 68 },
1883
  { 1548, 1365, 926, 41, 225, 68 },
1884
  { 1760, 1365, 926, 41, 225, 68 },
1885
  { 1950, 1365, 926, 41, 225, 68 },
1886
  { 67, 1365, 926, 41, 225, 68 },
1887
  { 336, 1365, 926, 41, 225, 68 },
1888
  { 607, 1365, 926, 41, 225, 68 },
1889
  { 812, 1365, 926, 41, 225, 68 },
1890
  { 1020, 1365, 926, 41, 225, 68 },
1891
  { 1222, 1365, 926, 41, 225, 68 },
1892
  { 1426, 1365, 926, 41, 225, 68 },
1893
  { 1624, 1365, 926, 41, 225, 68 },
1894
  { 1828, 1365, 926, 41, 225, 68 },
1895
  { 2026, 1365, 926, 41, 225, 68 },
1896
  { 135, 1365, 926, 41, 225, 68 },
1897
  { 412, 1365, 926, 41, 225, 68 },
1898
  { 198, 1387, 926, 41, 304, 73 },
1899
  { 471, 1200, 926, 41, 768, 59 },
1900
  { 674, 1343, 926, 41, 7760, 5 },
1901
  { 678, 78, 600, 26, 705, 74 },
1902
  { 890, 78, 390, 26, 705, 74 },
1903
  { 1090, 78, 390, 26, 705, 74 },
1904
  { 1300, 78, 390, 26, 705, 74 },
1905
  { 1496, 78, 390, 26, 705, 74 },
1906
  { 1702, 78, 390, 26, 705, 74 },
1907
  { 1898, 78, 390, 26, 705, 74 },
1908
  { 2096, 78, 390, 26, 705, 74 },
1909
  { 7, 78, 390, 26, 705, 74 },
1910
  { 265, 78, 390, 26, 705, 74 },
1911
  { 541, 78, 390, 26, 705, 74 },
1912
  { 736, 78, 390, 26, 705, 74 },
1913
  { 952, 78, 390, 26, 705, 74 },
1914
  { 1146, 78, 390, 26, 705, 74 },
1915
  { 1362, 78, 390, 26, 705, 74 },
1916
  { 1552, 78, 390, 26, 705, 74 },
1917
  { 1764, 78, 390, 26, 705, 74 },
1918
  { 1954, 78, 390, 26, 705, 74 },
1919
  { 71, 78, 390, 26, 705, 74 },
1920
  { 340, 78, 390, 26, 705, 74 },
1921
  { 611, 78, 390, 26, 705, 74 },
1922
  { 816, 78, 390, 26, 705, 74 },
1923
  { 1024, 78, 390, 26, 705, 74 },
1924
  { 1226, 78, 390, 26, 705, 74 },
1925
  { 1430, 78, 390, 26, 705, 74 },
1926
  { 1628, 78, 390, 26, 705, 74 },
1927
  { 1832, 78, 390, 26, 705, 74 },
1928
  { 2030, 78, 390, 26, 705, 74 },
1929
  { 139, 78, 390, 26, 705, 74 },
1930
  { 416, 78, 390, 26, 705, 74 },
1931
  { 202, 93, 390, 26, 992, 64 },
1932
  { 475, 1411, 390, 26, 9008, 10 },
1933
  { 499, 960, 378, 63, 1825, 80 },
1934
  { 700, 960, 580, 63, 1825, 80 },
1935
  { 911, 960, 296, 63, 1825, 80 },
1936
  { 1111, 960, 296, 63, 1825, 80 },
1937
  { 1321, 960, 296, 63, 1825, 80 },
1938
  { 1517, 960, 296, 63, 1825, 80 },
1939
  { 1723, 960, 296, 63, 1825, 80 },
1940
  { 1919, 960, 296, 63, 1825, 80 },
1941
  { 2117, 960, 296, 63, 1825, 80 },
1942
  { 31, 960, 296, 63, 1825, 80 },
1943
  { 290, 960, 296, 63, 1825, 80 },
1944
  { 568, 960, 296, 63, 1825, 80 },
1945
  { 764, 960, 296, 63, 1825, 80 },
1946
  { 980, 960, 296, 63, 1825, 80 },
1947
  { 1174, 960, 296, 63, 1825, 80 },
1948
  { 1386, 960, 296, 63, 1825, 80 },
1949
  { 1576, 960, 296, 63, 1825, 80 },
1950
  { 1788, 960, 296, 63, 1825, 80 },
1951
  { 1978, 960, 296, 63, 1825, 80 },
1952
  { 95, 960, 296, 63, 1825, 80 },
1953
  { 364, 960, 296, 63, 1825, 80 },
1954
  { 635, 960, 296, 63, 1825, 80 },
1955
  { 840, 960, 296, 63, 1825, 80 },
1956
  { 1048, 960, 296, 63, 1825, 80 },
1957
  { 1250, 960, 296, 63, 1825, 80 },
1958
  { 1454, 960, 296, 63, 1825, 80 },
1959
  { 1652, 960, 296, 63, 1825, 80 },
1960
  { 1856, 960, 296, 63, 1825, 80 },
1961
  { 2054, 960, 296, 63, 1825, 80 },
1962
  { 163, 960, 296, 63, 1825, 80 },
1963
  { 440, 960, 296, 63, 1825, 80 },
1964
  { 227, 1066, 296, 63, 9472, 14 },
1965
  { 905, 1279, 927, 96, 145, 87 },
1966
  { 1105, 1279, 927, 96, 145, 87 },
1967
  { 1315, 1279, 927, 96, 145, 87 },
1968
  { 1511, 1279, 927, 96, 145, 87 },
1969
  { 1717, 1279, 927, 96, 145, 87 },
1970
  { 1913, 1279, 927, 96, 145, 87 },
1971
  { 2111, 1279, 927, 96, 145, 87 },
1972
  { 25, 1279, 927, 96, 145, 87 },
1973
  { 284, 1279, 927, 96, 145, 87 },
1974
  { 561, 1279, 927, 96, 145, 87 },
1975
  { 756, 1279, 927, 96, 145, 87 },
1976
  { 972, 1279, 927, 96, 145, 87 },
1977
  { 1166, 1279, 927, 96, 145, 87 },
1978
  { 1378, 1279, 927, 96, 145, 87 },
1979
  { 1568, 1279, 927, 96, 145, 87 },
1980
  { 1780, 1279, 927, 96, 145, 87 },
1981
  { 1970, 1279, 927, 96, 145, 87 },
1982
  { 87, 1279, 927, 96, 145, 87 },
1983
  { 356, 1279, 927, 96, 145, 87 },
1984
  { 627, 1279, 927, 96, 145, 87 },
1985
  { 832, 1279, 927, 96, 145, 87 },
1986
  { 1040, 1279, 927, 96, 145, 87 },
1987
  { 1242, 1279, 927, 96, 145, 87 },
1988
  { 1446, 1279, 927, 96, 145, 87 },
1989
  { 1644, 1279, 927, 96, 145, 87 },
1990
  { 1848, 1279, 927, 96, 145, 87 },
1991
  { 2046, 1279, 927, 96, 145, 87 },
1992
  { 155, 1279, 927, 96, 145, 87 },
1993
  { 432, 1279, 927, 96, 145, 87 },
1994
  { 219, 1311, 927, 96, 304, 92 },
1995
  { 491, 1168, 927, 96, 768, 78 },
1996
  { 693, 1247, 927, 96, 7760, 17 },
1997
  { 697, 1105, 603, 75, 641, 93 },
1998
  { 908, 1105, 393, 75, 641, 93 },
1999
  { 1108, 1105, 393, 75, 641, 93 },
2000
  { 1318, 1105, 393, 75, 641, 93 },
2001
  { 1514, 1105, 393, 75, 641, 93 },
2002
  { 1720, 1105, 393, 75, 641, 93 },
2003
  { 1916, 1105, 393, 75, 641, 93 },
2004
  { 2114, 1105, 393, 75, 641, 93 },
2005
  { 28, 1105, 393, 75, 641, 93 },
2006
  { 287, 1105, 393, 75, 641, 93 },
2007
  { 564, 1105, 393, 75, 641, 93 },
2008
  { 760, 1105, 393, 75, 641, 93 },
2009
  { 976, 1105, 393, 75, 641, 93 },
2010
  { 1170, 1105, 393, 75, 641, 93 },
2011
  { 1382, 1105, 393, 75, 641, 93 },
2012
  { 1572, 1105, 393, 75, 641, 93 },
2013
  { 1784, 1105, 393, 75, 641, 93 },
2014
  { 1974, 1105, 393, 75, 641, 93 },
2015
  { 91, 1105, 393, 75, 641, 93 },
2016
  { 360, 1105, 393, 75, 641, 93 },
2017
  { 631, 1105, 393, 75, 641, 93 },
2018
  { 836, 1105, 393, 75, 641, 93 },
2019
  { 1044, 1105, 393, 75, 641, 93 },
2020
  { 1246, 1105, 393, 75, 641, 93 },
2021
  { 1450, 1105, 393, 75, 641, 93 },
2022
  { 1648, 1105, 393, 75, 641, 93 },
2023
  { 1852, 1105, 393, 75, 641, 93 },
2024
  { 2050, 1105, 393, 75, 641, 93 },
2025
  { 159, 1105, 393, 75, 641, 93 },
2026
  { 436, 1105, 393, 75, 641, 93 },
2027
  { 223, 1126, 393, 75, 992, 83 },
2028
  { 495, 1147, 393, 75, 9008, 22 },
2029
  { 2382, 1092, 419, 7, 6512, 32 },
2030
  { 508, 117, 427, 7, 1778, 32 },
2031
  { 920, 120, 427, 7, 1778, 32 },
2032
  { 1330, 123, 427, 7, 1778, 32 },
2033
  { 1732, 126, 427, 7, 1778, 32 },
2034
  { 2126, 129, 427, 7, 1778, 32 },
2035
  { 302, 132, 427, 7, 1778, 32 },
2036
  { 776, 135, 427, 7, 1778, 32 },
2037
  { 1186, 138, 427, 7, 1778, 32 },
2038
  { 1588, 141, 427, 7, 1778, 32 },
2039
  { 1990, 144, 427, 7, 1778, 32 },
2040
  { 376, 147, 427, 7, 1778, 32 },
2041
  { 852, 150, 427, 7, 1778, 32 },
2042
  { 1262, 153, 427, 7, 1778, 32 },
2043
  { 1664, 156, 427, 7, 1778, 32 },
2044
  { 2066, 159, 401, 7, 9841, 29 },
2045
  { 2390, 1078, 8, 128, 6561, 97 },
2046
  { 2364, 976, 8, 128, 9792, 26 },
2047
  { 514, 1060, 8, 128, 1730, 97 },
2048
  { 926, 1054, 8, 128, 1730, 97 },
2049
  { 1336, 1048, 8, 128, 1730, 97 },
2050
  { 1738, 1042, 8, 128, 1730, 97 },
2051
  { 2132, 1036, 8, 128, 1730, 97 },
2052
  { 310, 1030, 8, 128, 1730, 97 },
2053
  { 784, 1024, 8, 128, 1730, 97 },
2054
  { 1194, 1018, 8, 128, 1730, 97 },
2055
  { 1596, 1012, 8, 128, 1730, 97 },
2056
  { 1998, 1006, 8, 128, 1730, 97 },
2057
  { 384, 1000, 8, 128, 1730, 97 },
2058
  { 860, 994, 8, 128, 1730, 97 },
2059
  { 1270, 988, 8, 128, 1730, 97 },
2060
  { 1672, 982, 8, 128, 1730, 97 },
2061
  { 528, 618, 384, 134, 1169, 100 },
2062
  { 722, 618, 586, 134, 1169, 100 },
2063
  { 938, 618, 302, 134, 1169, 100 },
2064
  { 1132, 618, 302, 134, 1169, 100 },
2065
  { 1348, 618, 302, 134, 1169, 100 },
2066
  { 1538, 618, 302, 134, 1169, 100 },
2067
  { 1750, 618, 302, 134, 1169, 100 },
2068
  { 1940, 618, 302, 134, 1169, 100 },
2069
  { 2144, 618, 302, 134, 1169, 100 },
2070
  { 56, 618, 302, 134, 1169, 100 },
2071
  { 324, 618, 302, 134, 1169, 100 },
2072
  { 595, 618, 302, 134, 1169, 100 },
2073
  { 800, 618, 302, 134, 1169, 100 },
2074
  { 1008, 618, 302, 134, 1169, 100 },
2075
  { 1210, 618, 302, 134, 1169, 100 },
2076
  { 1414, 618, 302, 134, 1169, 100 },
2077
  { 1612, 618, 302, 134, 1169, 100 },
2078
  { 1816, 618, 302, 134, 1169, 100 },
2079
  { 2014, 618, 302, 134, 1169, 100 },
2080
  { 123, 618, 302, 134, 1169, 100 },
2081
  { 400, 618, 302, 134, 1169, 100 },
2082
  { 663, 618, 302, 134, 1169, 100 },
2083
  { 876, 618, 302, 134, 1169, 100 },
2084
  { 1076, 618, 302, 134, 1169, 100 },
2085
  { 1286, 618, 302, 134, 1169, 100 },
2086
  { 1482, 618, 302, 134, 1169, 100 },
2087
  { 1688, 618, 302, 134, 1169, 100 },
2088
  { 1884, 618, 302, 134, 1169, 100 },
2089
  { 2082, 618, 302, 134, 1169, 100 },
2090
  { 187, 618, 302, 134, 1169, 100 },
2091
  { 460, 618, 302, 134, 1169, 100 },
2092
  { 251, 635, 302, 134, 9520, 38 },
2093
  { 932, 834, 8, 181, 1, 121 },
2094
  { 1126, 834, 8, 181, 1, 121 },
2095
  { 1342, 834, 8, 181, 1, 121 },
2096
  { 1532, 834, 8, 181, 1, 121 },
2097
  { 1744, 834, 8, 181, 1, 121 },
2098
  { 1934, 834, 8, 181, 1, 121 },
2099
  { 2138, 834, 8, 181, 1, 121 },
2100
  { 50, 834, 8, 181, 1, 121 },
2101
  { 318, 834, 8, 181, 1, 121 },
2102
  { 588, 834, 8, 181, 1, 121 },
2103
  { 792, 834, 8, 181, 1, 121 },
2104
  { 1000, 834, 8, 181, 1, 121 },
2105
  { 1202, 834, 8, 181, 1, 121 },
2106
  { 1406, 834, 8, 181, 1, 121 },
2107
  { 1604, 834, 8, 181, 1, 121 },
2108
  { 1808, 834, 8, 181, 1, 121 },
2109
  { 2006, 834, 8, 181, 1, 121 },
2110
  { 115, 834, 8, 181, 1, 121 },
2111
  { 392, 834, 8, 181, 1, 121 },
2112
  { 655, 834, 8, 181, 1, 121 },
2113
  { 868, 834, 8, 181, 1, 121 },
2114
  { 1068, 834, 8, 181, 1, 121 },
2115
  { 1278, 834, 8, 181, 1, 121 },
2116
  { 1474, 834, 8, 181, 1, 121 },
2117
  { 1680, 834, 8, 181, 1, 121 },
2118
  { 1876, 834, 8, 181, 1, 121 },
2119
  { 2074, 834, 8, 181, 1, 121 },
2120
  { 179, 834, 8, 181, 1, 121 },
2121
  { 452, 834, 8, 181, 1, 121 },
2122
  { 243, 880, 8, 181, 384, 130 },
2123
  { 520, 742, 8, 181, 848, 105 },
2124
  { 715, 788, 8, 181, 7840, 43 },
2125
  { 719, 652, 606, 151, 529, 139 },
2126
  { 935, 652, 192, 151, 529, 139 },
2127
  { 1129, 652, 192, 151, 529, 139 },
2128
  { 1345, 652, 192, 151, 529, 139 },
2129
  { 1535, 652, 192, 151, 529, 139 },
2130
  { 1747, 652, 192, 151, 529, 139 },
2131
  { 1937, 652, 192, 151, 529, 139 },
2132
  { 2141, 652, 192, 151, 529, 139 },
2133
  { 53, 652, 192, 151, 529, 139 },
2134
  { 321, 652, 192, 151, 529, 139 },
2135
  { 591, 652, 192, 151, 529, 139 },
2136
  { 796, 652, 192, 151, 529, 139 },
2137
  { 1004, 652, 192, 151, 529, 139 },
2138
  { 1206, 652, 192, 151, 529, 139 },
2139
  { 1410, 652, 192, 151, 529, 139 },
2140
  { 1608, 652, 192, 151, 529, 139 },
2141
  { 1812, 652, 192, 151, 529, 139 },
2142
  { 2010, 652, 192, 151, 529, 139 },
2143
  { 119, 652, 192, 151, 529, 139 },
2144
  { 396, 652, 192, 151, 529, 139 },
2145
  { 659, 652, 192, 151, 529, 139 },
2146
  { 872, 652, 192, 151, 529, 139 },
2147
  { 1072, 652, 192, 151, 529, 139 },
2148
  { 1282, 652, 192, 151, 529, 139 },
2149
  { 1478, 652, 192, 151, 529, 139 },
2150
  { 1684, 652, 192, 151, 529, 139 },
2151
  { 1880, 652, 192, 151, 529, 139 },
2152
  { 2078, 652, 192, 151, 529, 139 },
2153
  { 183, 652, 192, 151, 529, 139 },
2154
  { 456, 652, 192, 151, 529, 139 },
2155
  { 247, 682, 192, 151, 1056, 114 },
2156
  { 524, 712, 192, 151, 9072, 52 },
2157
};
2158
2159
extern const MCPhysReg AArch64RegUnitRoots[][2] = {
2160
  { AArch64::FFR },
2161
  { AArch64::W29 },
2162
  { AArch64::W30 },
2163
  { AArch64::NZCV },
2164
  { AArch64::WSP },
2165
  { AArch64::WZR },
2166
  { AArch64::B0 },
2167
  { AArch64::B1 },
2168
  { AArch64::B2 },
2169
  { AArch64::B3 },
2170
  { AArch64::B4 },
2171
  { AArch64::B5 },
2172
  { AArch64::B6 },
2173
  { AArch64::B7 },
2174
  { AArch64::B8 },
2175
  { AArch64::B9 },
2176
  { AArch64::B10 },
2177
  { AArch64::B11 },
2178
  { AArch64::B12 },
2179
  { AArch64::B13 },
2180
  { AArch64::B14 },
2181
  { AArch64::B15 },
2182
  { AArch64::B16 },
2183
  { AArch64::B17 },
2184
  { AArch64::B18 },
2185
  { AArch64::B19 },
2186
  { AArch64::B20 },
2187
  { AArch64::B21 },
2188
  { AArch64::B22 },
2189
  { AArch64::B23 },
2190
  { AArch64::B24 },
2191
  { AArch64::B25 },
2192
  { AArch64::B26 },
2193
  { AArch64::B27 },
2194
  { AArch64::B28 },
2195
  { AArch64::B29 },
2196
  { AArch64::B30 },
2197
  { AArch64::B31 },
2198
  { AArch64::P0 },
2199
  { AArch64::P1 },
2200
  { AArch64::P2 },
2201
  { AArch64::P3 },
2202
  { AArch64::P4 },
2203
  { AArch64::P5 },
2204
  { AArch64::P6 },
2205
  { AArch64::P7 },
2206
  { AArch64::P8 },
2207
  { AArch64::P9 },
2208
  { AArch64::P10 },
2209
  { AArch64::P11 },
2210
  { AArch64::P12 },
2211
  { AArch64::P13 },
2212
  { AArch64::P14 },
2213
  { AArch64::P15 },
2214
  { AArch64::W0 },
2215
  { AArch64::W1 },
2216
  { AArch64::W2 },
2217
  { AArch64::W3 },
2218
  { AArch64::W4 },
2219
  { AArch64::W5 },
2220
  { AArch64::W6 },
2221
  { AArch64::W7 },
2222
  { AArch64::W8 },
2223
  { AArch64::W9 },
2224
  { AArch64::W10 },
2225
  { AArch64::W11 },
2226
  { AArch64::W12 },
2227
  { AArch64::W13 },
2228
  { AArch64::W14 },
2229
  { AArch64::W15 },
2230
  { AArch64::W16 },
2231
  { AArch64::W17 },
2232
  { AArch64::W18 },
2233
  { AArch64::W19 },
2234
  { AArch64::W20 },
2235
  { AArch64::W21 },
2236
  { AArch64::W22 },
2237
  { AArch64::W23 },
2238
  { AArch64::W24 },
2239
  { AArch64::W25 },
2240
  { AArch64::W26 },
2241
  { AArch64::W27 },
2242
  { AArch64::W28 },
2243
  { AArch64::Z0_HI },
2244
  { AArch64::Z1_HI },
2245
  { AArch64::Z2_HI },
2246
  { AArch64::Z3_HI },
2247
  { AArch64::Z4_HI },
2248
  { AArch64::Z5_HI },
2249
  { AArch64::Z6_HI },
2250
  { AArch64::Z7_HI },
2251
  { AArch64::Z8_HI },
2252
  { AArch64::Z9_HI },
2253
  { AArch64::Z10_HI },
2254
  { AArch64::Z11_HI },
2255
  { AArch64::Z12_HI },
2256
  { AArch64::Z13_HI },
2257
  { AArch64::Z14_HI },
2258
  { AArch64::Z15_HI },
2259
  { AArch64::Z16_HI },
2260
  { AArch64::Z17_HI },
2261
  { AArch64::Z18_HI },
2262
  { AArch64::Z19_HI },
2263
  { AArch64::Z20_HI },
2264
  { AArch64::Z21_HI },
2265
  { AArch64::Z22_HI },
2266
  { AArch64::Z23_HI },
2267
  { AArch64::Z24_HI },
2268
  { AArch64::Z25_HI },
2269
  { AArch64::Z26_HI },
2270
  { AArch64::Z27_HI },
2271
  { AArch64::Z28_HI },
2272
  { AArch64::Z29_HI },
2273
  { AArch64::Z30_HI },
2274
  { AArch64::Z31_HI },
2275
};
2276
2277
namespace {     // Register classes...
2278
  // FPR8 Register Class...
2279
  const MCPhysReg FPR8[] = {
2280
    AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, 
2281
  };
2282
2283
  // FPR8 Bit set.
2284
  const uint8_t FPR8Bits[] = {
2285
    0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2286
  };
2287
2288
  // FPR16 Register Class...
2289
  const MCPhysReg FPR16[] = {
2290
    AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, 
2291
  };
2292
2293
  // FPR16 Bit set.
2294
  const uint8_t FPR16Bits[] = {
2295
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2296
  };
2297
2298
  // PPR Register Class...
2299
  const MCPhysReg PPR[] = {
2300
    AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, 
2301
  };
2302
2303
  // PPR Bit set.
2304
  const uint8_t PPRBits[] = {
2305
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
2306
  };
2307
2308
  // PPR_3b Register Class...
2309
  const MCPhysReg PPR_3b[] = {
2310
    AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 
2311
  };
2312
2313
  // PPR_3b Bit set.
2314
  const uint8_t PPR_3bBits[] = {
2315
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
2316
  };
2317
2318
  // GPR32all Register Class...
2319
  const MCPhysReg GPR32all[] = {
2320
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP, 
2321
  };
2322
2323
  // GPR32all Bit set.
2324
  const uint8_t GPR32allBits[] = {
2325
    0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2326
  };
2327
2328
  // FPR32 Register Class...
2329
  const MCPhysReg FPR32[] = {
2330
    AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, 
2331
  };
2332
2333
  // FPR32 Bit set.
2334
  const uint8_t FPR32Bits[] = {
2335
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2336
  };
2337
2338
  // GPR32 Register Class...
2339
  const MCPhysReg GPR32[] = {
2340
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, 
2341
  };
2342
2343
  // GPR32 Bit set.
2344
  const uint8_t GPR32Bits[] = {
2345
    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2346
  };
2347
2348
  // GPR32sp Register Class...
2349
  const MCPhysReg GPR32sp[] = {
2350
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, 
2351
  };
2352
2353
  // GPR32sp Bit set.
2354
  const uint8_t GPR32spBits[] = {
2355
    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2356
  };
2357
2358
  // GPR32common Register Class...
2359
  const MCPhysReg GPR32common[] = {
2360
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, 
2361
  };
2362
2363
  // GPR32common Bit set.
2364
  const uint8_t GPR32commonBits[] = {
2365
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2366
  };
2367
2368
  // GPR32arg Register Class...
2369
  const MCPhysReg GPR32arg[] = {
2370
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, 
2371
  };
2372
2373
  // GPR32arg Bit set.
2374
  const uint8_t GPR32argBits[] = {
2375
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
2376
  };
2377
2378
  // CCR Register Class...
2379
  const MCPhysReg CCR[] = {
2380
    AArch64::NZCV, 
2381
  };
2382
2383
  // CCR Bit set.
2384
  const uint8_t CCRBits[] = {
2385
    0x10, 
2386
  };
2387
2388
  // GPR32sponly Register Class...
2389
  const MCPhysReg GPR32sponly[] = {
2390
    AArch64::WSP, 
2391
  };
2392
2393
  // GPR32sponly Bit set.
2394
  const uint8_t GPR32sponlyBits[] = {
2395
    0x40, 
2396
  };
2397
2398
  // WSeqPairsClass Register Class...
2399
  const MCPhysReg WSeqPairsClass[] = {
2400
    AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7, AArch64::W8_W9, AArch64::W10_W11, AArch64::W12_W13, AArch64::W14_W15, AArch64::W16_W17, AArch64::W18_W19, AArch64::W20_W21, AArch64::W22_W23, AArch64::W24_W25, AArch64::W26_W27, AArch64::W28_W29, AArch64::W30_WZR, 
2401
  };
2402
2403
  // WSeqPairsClass Bit set.
2404
  const uint8_t WSeqPairsClassBits[] = {
2405
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2406
  };
2407
2408
  // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
2409
  const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
2410
    AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7, AArch64::W8_W9, AArch64::W10_W11, AArch64::W12_W13, AArch64::W14_W15, AArch64::W16_W17, AArch64::W18_W19, AArch64::W20_W21, AArch64::W22_W23, AArch64::W24_W25, AArch64::W26_W27, AArch64::W28_W29, 
2411
  };
2412
2413
  // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
2414
  const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
2415
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 
2416
  };
2417
2418
  // WSeqPairsClass_with_sube32_in_GPR32arg Register Class...
2419
  const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32arg[] = {
2420
    AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7, 
2421
  };
2422
2423
  // WSeqPairsClass_with_sube32_in_GPR32arg Bit set.
2424
  const uint8_t WSeqPairsClass_with_sube32_in_GPR32argBits[] = {
2425
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
2426
  };
2427
2428
  // GPR64all Register Class...
2429
  const MCPhysReg GPR64all[] = {
2430
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP, 
2431
  };
2432
2433
  // GPR64all Bit set.
2434
  const uint8_t GPR64allBits[] = {
2435
    0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2436
  };
2437
2438
  // FPR64 Register Class...
2439
  const MCPhysReg FPR64[] = {
2440
    AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 
2441
  };
2442
2443
  // FPR64 Bit set.
2444
  const uint8_t FPR64Bits[] = {
2445
    0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2446
  };
2447
2448
  // GPR64 Register Class...
2449
  const MCPhysReg GPR64[] = {
2450
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, 
2451
  };
2452
2453
  // GPR64 Bit set.
2454
  const uint8_t GPR64Bits[] = {
2455
    0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2456
  };
2457
2458
  // GPR64sp Register Class...
2459
  const MCPhysReg GPR64sp[] = {
2460
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, 
2461
  };
2462
2463
  // GPR64sp Bit set.
2464
  const uint8_t GPR64spBits[] = {
2465
    0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2466
  };
2467
2468
  // GPR64common Register Class...
2469
  const MCPhysReg GPR64common[] = {
2470
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, 
2471
  };
2472
2473
  // GPR64common Bit set.
2474
  const uint8_t GPR64commonBits[] = {
2475
    0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2476
  };
2477
2478
  // GPR64noip Register Class...
2479
  const MCPhysReg GPR64noip[] = {
2480
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::XZR, 
2481
  };
2482
2483
  // GPR64noip Bit set.
2484
  const uint8_t GPR64noipBits[] = {
2485
    0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfc, 0x1f, 
2486
  };
2487
2488
  // GPR64common_and_GPR64noip Register Class...
2489
  const MCPhysReg GPR64common_and_GPR64noip[] = {
2490
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 
2491
  };
2492
2493
  // GPR64common_and_GPR64noip Bit set.
2494
  const uint8_t GPR64common_and_GPR64noipBits[] = {
2495
    0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfc, 0x1f, 
2496
  };
2497
2498
  // tcGPR64 Register Class...
2499
  const MCPhysReg tcGPR64[] = {
2500
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, 
2501
  };
2502
2503
  // tcGPR64 Bit set.
2504
  const uint8_t tcGPR64Bits[] = {
2505
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07, 
2506
  };
2507
2508
  // GPR64noip_and_tcGPR64 Register Class...
2509
  const MCPhysReg GPR64noip_and_tcGPR64[] = {
2510
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, 
2511
  };
2512
2513
  // GPR64noip_and_tcGPR64 Bit set.
2514
  const uint8_t GPR64noip_and_tcGPR64Bits[] = {
2515
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x04, 
2516
  };
2517
2518
  // GPR64arg Register Class...
2519
  const MCPhysReg GPR64arg[] = {
2520
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, 
2521
  };
2522
2523
  // GPR64arg Bit set.
2524
  const uint8_t GPR64argBits[] = {
2525
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 
2526
  };
2527
2528
  // rtcGPR64 Register Class...
2529
  const MCPhysReg rtcGPR64[] = {
2530
    AArch64::X16, AArch64::X17, 
2531
  };
2532
2533
  // rtcGPR64 Bit set.
2534
  const uint8_t rtcGPR64Bits[] = {
2535
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 
2536
  };
2537
2538
  // GPR64sponly Register Class...
2539
  const MCPhysReg GPR64sponly[] = {
2540
    AArch64::SP, 
2541
  };
2542
2543
  // GPR64sponly Bit set.
2544
  const uint8_t GPR64sponlyBits[] = {
2545
    0x20, 
2546
  };
2547
2548
  // DD Register Class...
2549
  const MCPhysReg DD[] = {
2550
    AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0, 
2551
  };
2552
2553
  // DD Bit set.
2554
  const uint8_t DDBits[] = {
2555
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2556
  };
2557
2558
  // XSeqPairsClass Register Class...
2559
  const MCPhysReg XSeqPairsClass[] = {
2560
    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, AArch64::LR_XZR, 
2561
  };
2562
2563
  // XSeqPairsClass Bit set.
2564
  const uint8_t XSeqPairsClassBits[] = {
2565
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2566
  };
2567
2568
  // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
2569
  const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
2570
    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, 
2571
  };
2572
2573
  // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
2574
  const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
2575
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 
2576
  };
2577
2578
  // XSeqPairsClass_with_subo64_in_GPR64noip Register Class...
2579
  const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64noip[] = {
2580
    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, AArch64::LR_XZR, 
2581
  };
2582
2583
  // XSeqPairsClass_with_subo64_in_GPR64noip Bit set.
2584
  const uint8_t XSeqPairsClass_with_subo64_in_GPR64noipBits[] = {
2585
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x7f, 0x1f, 
2586
  };
2587
2588
  // XSeqPairsClass_with_sube64_in_GPR64noip Register Class...
2589
  const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64noip[] = {
2590
    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, 
2591
  };
2592
2593
  // XSeqPairsClass_with_sube64_in_GPR64noip Bit set.
2594
  const uint8_t XSeqPairsClass_with_sube64_in_GPR64noipBits[] = {
2595
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x7f, 0x1f, 
2596
  };
2597
2598
  // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
2599
  const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
2600
    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19, 
2601
  };
2602
2603
  // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
2604
  const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
2605
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 
2606
  };
2607
2608
  // XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 Register Class...
2609
  const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64[] = {
2610
    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19, 
2611
  };
2612
2613
  // XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 Bit set.
2614
  const uint8_t XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits[] = {
2615
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x01, 
2616
  };
2617
2618
  // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
2619
  const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
2620
    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, 
2621
  };
2622
2623
  // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
2624
  const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
2625
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 
2626
  };
2627
2628
  // XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 Register Class...
2629
  const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64[] = {
2630
    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, 
2631
  };
2632
2633
  // XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 Bit set.
2634
  const uint8_t XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits[] = {
2635
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
2636
  };
2637
2638
  // XSeqPairsClass_with_sub_32_in_GPR32arg Register Class...
2639
  const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32arg[] = {
2640
    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, 
2641
  };
2642
2643
  // XSeqPairsClass_with_sub_32_in_GPR32arg Bit set.
2644
  const uint8_t XSeqPairsClass_with_sub_32_in_GPR32argBits[] = {
2645
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
2646
  };
2647
2648
  // XSeqPairsClass_with_sube64_in_rtcGPR64 Register Class...
2649
  const MCPhysReg XSeqPairsClass_with_sube64_in_rtcGPR64[] = {
2650
    AArch64::X16_X17, 
2651
  };
2652
2653
  // XSeqPairsClass_with_sube64_in_rtcGPR64 Bit set.
2654
  const uint8_t XSeqPairsClass_with_sube64_in_rtcGPR64Bits[] = {
2655
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 
2656
  };
2657
2658
  // FPR128 Register Class...
2659
  const MCPhysReg FPR128[] = {
2660
    AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 
2661
  };
2662
2663
  // FPR128 Bit set.
2664
  const uint8_t FPR128Bits[] = {
2665
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2666
  };
2667
2668
  // ZPR Register Class...
2669
  const MCPhysReg ZPR[] = {
2670
    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31, 
2671
  };
2672
2673
  // ZPR Bit set.
2674
  const uint8_t ZPRBits[] = {
2675
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2676
  };
2677
2678
  // FPR128_lo Register Class...
2679
  const MCPhysReg FPR128_lo[] = {
2680
    AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, 
2681
  };
2682
2683
  // FPR128_lo Bit set.
2684
  const uint8_t FPR128_loBits[] = {
2685
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
2686
  };
2687
2688
  // ZPR_4b Register Class...
2689
  const MCPhysReg ZPR_4b[] = {
2690
    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 
2691
  };
2692
2693
  // ZPR_4b Bit set.
2694
  const uint8_t ZPR_4bBits[] = {
2695
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2696
  };
2697
2698
  // ZPR_3b Register Class...
2699
  const MCPhysReg ZPR_3b[] = {
2700
    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 
2701
  };
2702
2703
  // ZPR_3b Bit set.
2704
  const uint8_t ZPR_3bBits[] = {
2705
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2706
  };
2707
2708
  // DDD Register Class...
2709
  const MCPhysReg DDD[] = {
2710
    AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1, 
2711
  };
2712
2713
  // DDD Bit set.
2714
  const uint8_t DDDBits[] = {
2715
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2716
  };
2717
2718
  // DDDD Register Class...
2719
  const MCPhysReg DDDD[] = {
2720
    AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, 
2721
  };
2722
2723
  // DDDD Bit set.
2724
  const uint8_t DDDDBits[] = {
2725
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2726
  };
2727
2728
  // QQ Register Class...
2729
  const MCPhysReg QQ[] = {
2730
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0, 
2731
  };
2732
2733
  // QQ Bit set.
2734
  const uint8_t QQBits[] = {
2735
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2736
  };
2737
2738
  // ZPR2 Register Class...
2739
  const MCPhysReg ZPR2[] = {
2740
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0, 
2741
  };
2742
2743
  // ZPR2 Bit set.
2744
  const uint8_t ZPR2Bits[] = {
2745
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2746
  };
2747
2748
  // QQ_with_qsub0_in_FPR128_lo Register Class...
2749
  const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
2750
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 
2751
  };
2752
2753
  // QQ_with_qsub0_in_FPR128_lo Bit set.
2754
  const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
2755
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2756
  };
2757
2758
  // QQ_with_qsub1_in_FPR128_lo Register Class...
2759
  const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
2760
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0, 
2761
  };
2762
2763
  // QQ_with_qsub1_in_FPR128_lo Bit set.
2764
  const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
2765
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2766
  };
2767
2768
  // ZPR2_with_zsub1_in_ZPR_4b Register Class...
2769
  const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = {
2770
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z31_Z0, 
2771
  };
2772
2773
  // ZPR2_with_zsub1_in_ZPR_4b Bit set.
2774
  const uint8_t ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2775
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2776
  };
2777
2778
  // ZPR2_with_zsub_in_FPR128_lo Register Class...
2779
  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = {
2780
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 
2781
  };
2782
2783
  // ZPR2_with_zsub_in_FPR128_lo Bit set.
2784
  const uint8_t ZPR2_with_zsub_in_FPR128_loBits[] = {
2785
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2786
  };
2787
2788
  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
2789
  const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
2790
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, 
2791
  };
2792
2793
  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
2794
  const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
2795
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2796
  };
2797
2798
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Register Class...
2799
  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = {
2800
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, 
2801
  };
2802
2803
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Bit set.
2804
  const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2805
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2806
  };
2807
2808
  // ZPR2_with_zsub0_in_ZPR_3b Register Class...
2809
  const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = {
2810
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 
2811
  };
2812
2813
  // ZPR2_with_zsub0_in_ZPR_3b Bit set.
2814
  const uint8_t ZPR2_with_zsub0_in_ZPR_3bBits[] = {
2815
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2816
  };
2817
2818
  // ZPR2_with_zsub1_in_ZPR_3b Register Class...
2819
  const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = {
2820
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z31_Z0, 
2821
  };
2822
2823
  // ZPR2_with_zsub1_in_ZPR_3b Bit set.
2824
  const uint8_t ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2825
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
2826
  };
2827
2828
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Register Class...
2829
  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = {
2830
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, 
2831
  };
2832
2833
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Bit set.
2834
  const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2835
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
2836
  };
2837
2838
  // QQQ Register Class...
2839
  const MCPhysReg QQQ[] = {
2840
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
2841
  };
2842
2843
  // QQQ Bit set.
2844
  const uint8_t QQQBits[] = {
2845
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2846
  };
2847
2848
  // ZPR3 Register Class...
2849
  const MCPhysReg ZPR3[] = {
2850
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
2851
  };
2852
2853
  // ZPR3 Bit set.
2854
  const uint8_t ZPR3Bits[] = {
2855
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2856
  };
2857
2858
  // QQQ_with_qsub0_in_FPR128_lo Register Class...
2859
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
2860
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, 
2861
  };
2862
2863
  // QQQ_with_qsub0_in_FPR128_lo Bit set.
2864
  const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
2865
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2866
  };
2867
2868
  // QQQ_with_qsub1_in_FPR128_lo Register Class...
2869
  const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
2870
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1, 
2871
  };
2872
2873
  // QQQ_with_qsub1_in_FPR128_lo Bit set.
2874
  const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
2875
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2876
  };
2877
2878
  // QQQ_with_qsub2_in_FPR128_lo Register Class...
2879
  const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
2880
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
2881
  };
2882
2883
  // QQQ_with_qsub2_in_FPR128_lo Bit set.
2884
  const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
2885
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
2886
  };
2887
2888
  // ZPR3_with_zsub1_in_ZPR_4b Register Class...
2889
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = {
2890
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z31_Z0_Z1, 
2891
  };
2892
2893
  // ZPR3_with_zsub1_in_ZPR_4b Bit set.
2894
  const uint8_t ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2895
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2896
  };
2897
2898
  // ZPR3_with_zsub2_in_ZPR_4b Register Class...
2899
  const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = {
2900
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
2901
  };
2902
2903
  // ZPR3_with_zsub2_in_ZPR_4b Bit set.
2904
  const uint8_t ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2905
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
2906
  };
2907
2908
  // ZPR3_with_zsub_in_FPR128_lo Register Class...
2909
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = {
2910
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, 
2911
  };
2912
2913
  // ZPR3_with_zsub_in_FPR128_lo Bit set.
2914
  const uint8_t ZPR3_with_zsub_in_FPR128_loBits[] = {
2915
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2916
  };
2917
2918
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
2919
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
2920
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 
2921
  };
2922
2923
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
2924
  const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
2925
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2926
  };
2927
2928
  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2929
  const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2930
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1, 
2931
  };
2932
2933
  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2934
  const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2935
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
2936
  };
2937
2938
  // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2939
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2940
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z31_Z0_Z1, 
2941
  };
2942
2943
  // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2944
  const uint8_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2945
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
2946
  };
2947
2948
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Register Class...
2949
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = {
2950
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 
2951
  };
2952
2953
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Bit set.
2954
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2955
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2956
  };
2957
2958
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2959
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2960
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, 
2961
  };
2962
2963
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2964
  const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2965
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
2966
  };
2967
2968
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2969
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2970
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, 
2971
  };
2972
2973
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2974
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2975
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
2976
  };
2977
2978
  // ZPR3_with_zsub0_in_ZPR_3b Register Class...
2979
  const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = {
2980
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, 
2981
  };
2982
2983
  // ZPR3_with_zsub0_in_ZPR_3b Bit set.
2984
  const uint8_t ZPR3_with_zsub0_in_ZPR_3bBits[] = {
2985
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2986
  };
2987
2988
  // ZPR3_with_zsub1_in_ZPR_3b Register Class...
2989
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = {
2990
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z31_Z0_Z1, 
2991
  };
2992
2993
  // ZPR3_with_zsub1_in_ZPR_3b Bit set.
2994
  const uint8_t ZPR3_with_zsub1_in_ZPR_3bBits[] = {
2995
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
2996
  };
2997
2998
  // ZPR3_with_zsub2_in_ZPR_3b Register Class...
2999
  const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = {
3000
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
3001
  };
3002
3003
  // ZPR3_with_zsub2_in_ZPR_3b Bit set.
3004
  const uint8_t ZPR3_with_zsub2_in_ZPR_3bBits[] = {
3005
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, 
3006
  };
3007
3008
  // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
3009
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
3010
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z31_Z0_Z1, 
3011
  };
3012
3013
  // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
3014
  const uint8_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
3015
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, 
3016
  };
3017
3018
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Register Class...
3019
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = {
3020
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, 
3021
  };
3022
3023
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Bit set.
3024
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits[] = {
3025
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
3026
  };
3027
3028
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
3029
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
3030
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 
3031
  };
3032
3033
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
3034
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
3035
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 
3036
  };
3037
3038
  // QQQQ Register Class...
3039
  const MCPhysReg QQQQ[] = {
3040
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
3041
  };
3042
3043
  // QQQQ Bit set.
3044
  const uint8_t QQQQBits[] = {
3045
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
3046
  };
3047
3048
  // ZPR4 Register Class...
3049
  const MCPhysReg ZPR4[] = {
3050
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3051
  };
3052
3053
  // ZPR4 Bit set.
3054
  const uint8_t ZPR4Bits[] = {
3055
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
3056
  };
3057
3058
  // QQQQ_with_qsub0_in_FPR128_lo Register Class...
3059
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
3060
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, 
3061
  };
3062
3063
  // QQQQ_with_qsub0_in_FPR128_lo Bit set.
3064
  const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
3065
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
3066
  };
3067
3068
  // QQQQ_with_qsub1_in_FPR128_lo Register Class...
3069
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
3070
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2, 
3071
  };
3072
3073
  // QQQQ_with_qsub1_in_FPR128_lo Bit set.
3074
  const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
3075
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
3076
  };
3077
3078
  // QQQQ_with_qsub2_in_FPR128_lo Register Class...
3079
  const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
3080
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
3081
  };
3082
3083
  // QQQQ_with_qsub2_in_FPR128_lo Bit set.
3084
  const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
3085
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
3086
  };
3087
3088
  // QQQQ_with_qsub3_in_FPR128_lo Register Class...
3089
  const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
3090
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
3091
  };
3092
3093
  // QQQQ_with_qsub3_in_FPR128_lo Bit set.
3094
  const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
3095
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, 
3096
  };
3097
3098
  // ZPR4_with_zsub1_in_ZPR_4b Register Class...
3099
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = {
3100
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z31_Z0_Z1_Z2, 
3101
  };
3102
3103
  // ZPR4_with_zsub1_in_ZPR_4b Bit set.
3104
  const uint8_t ZPR4_with_zsub1_in_ZPR_4bBits[] = {
3105
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
3106
  };
3107
3108
  // ZPR4_with_zsub2_in_ZPR_4b Register Class...
3109
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = {
3110
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3111
  };
3112
3113
  // ZPR4_with_zsub2_in_ZPR_4b Bit set.
3114
  const uint8_t ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3115
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
3116
  };
3117
3118
  // ZPR4_with_zsub3_in_ZPR_4b Register Class...
3119
  const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = {
3120
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3121
  };
3122
3123
  // ZPR4_with_zsub3_in_ZPR_4b Bit set.
3124
  const uint8_t ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3125
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, 
3126
  };
3127
3128
  // ZPR4_with_zsub_in_FPR128_lo Register Class...
3129
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = {
3130
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, 
3131
  };
3132
3133
  // ZPR4_with_zsub_in_FPR128_lo Bit set.
3134
  const uint8_t ZPR4_with_zsub_in_FPR128_loBits[] = {
3135
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
3136
  };
3137
3138
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
3139
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
3140
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 
3141
  };
3142
3143
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
3144
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
3145
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
3146
  };
3147
3148
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
3149
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3150
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2, 
3151
  };
3152
3153
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
3154
  const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
3155
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
3156
  };
3157
3158
  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3159
  const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3160
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
3161
  };
3162
3163
  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3164
  const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3165
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, 
3166
  };
3167
3168
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
3169
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3170
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z31_Z0_Z1_Z2, 
3171
  };
3172
3173
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
3174
  const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3175
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
3176
  };
3177
3178
  // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3179
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3180
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3181
  };
3182
3183
  // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3184
  const uint8_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3185
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, 
3186
  };
3187
3188
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Register Class...
3189
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = {
3190
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 
3191
  };
3192
3193
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Bit set.
3194
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits[] = {
3195
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
3196
  };
3197
3198
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
3199
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3200
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, 
3201
  };
3202
3203
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
3204
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
3205
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
3206
  };
3207
3208
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3209
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3210
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2, 
3211
  };
3212
3213
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3214
  const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3215
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, 
3216
  };
3217
3218
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3219
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3220
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z31_Z0_Z1_Z2, 
3221
  };
3222
3223
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3224
  const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3225
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, 
3226
  };
3227
3228
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
3229
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3230
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, 
3231
  };
3232
3233
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
3234
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3235
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
3236
  };
3237
3238
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3239
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3240
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, 
3241
  };
3242
3243
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3244
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3245
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 
3246
  };
3247
3248
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3249
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3250
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, 
3251
  };
3252
3253
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3254
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3255
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 
3256
  };
3257
3258
  // ZPR4_with_zsub0_in_ZPR_3b Register Class...
3259
  const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = {
3260
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, 
3261
  };
3262
3263
  // ZPR4_with_zsub0_in_ZPR_3b Bit set.
3264
  const uint8_t ZPR4_with_zsub0_in_ZPR_3bBits[] = {
3265
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
3266
  };
3267
3268
  // ZPR4_with_zsub1_in_ZPR_3b Register Class...
3269
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = {
3270
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z31_Z0_Z1_Z2, 
3271
  };
3272
3273
  // ZPR4_with_zsub1_in_ZPR_3b Bit set.
3274
  const uint8_t ZPR4_with_zsub1_in_ZPR_3bBits[] = {
3275
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
3276
  };
3277
3278
  // ZPR4_with_zsub2_in_ZPR_3b Register Class...
3279
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = {
3280
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3281
  };
3282
3283
  // ZPR4_with_zsub2_in_ZPR_3b Bit set.
3284
  const uint8_t ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3285
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, 
3286
  };
3287
3288
  // ZPR4_with_zsub3_in_ZPR_3b Register Class...
3289
  const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = {
3290
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3291
  };
3292
3293
  // ZPR4_with_zsub3_in_ZPR_3b Bit set.
3294
  const uint8_t ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3295
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x1c, 
3296
  };
3297
3298
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
3299
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3300
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z31_Z0_Z1_Z2, 
3301
  };
3302
3303
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
3304
  const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3305
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, 
3306
  };
3307
3308
  // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3309
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3310
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3311
  };
3312
3313
  // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3314
  const uint8_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3315
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x18, 
3316
  };
3317
3318
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Register Class...
3319
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = {
3320
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, 
3321
  };
3322
3323
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Bit set.
3324
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits[] = {
3325
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
3326
  };
3327
3328
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3329
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3330
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z31_Z0_Z1_Z2, 
3331
  };
3332
3333
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3334
  const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3335
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x10, 
3336
  };
3337
3338
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
3339
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3340
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 
3341
  };
3342
3343
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
3344
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3345
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 
3346
  };
3347
3348
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3349
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3350
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, 
3351
  };
3352
3353
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3354
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3355
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 
3356
  };
3357
3358
} // end anonymous namespace
3359
3360
extern const char AArch64RegClassStrings[] = {
3361
  /* 0 */ 'F', 'P', 'R', '3', '2', 0,
3362
  /* 6 */ 'G', 'P', 'R', '3', '2', 0,
3363
  /* 12 */ 'Z', 'P', 'R', '2', 0,
3364
  /* 17 */ 'Z', 'P', 'R', '3', 0,
3365
  /* 22 */ 'F', 'P', 'R', '6', '4', 0,
3366
  /* 28 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'n', 'o', 'i', 'p', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3367
  /* 80 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'n', 'o', 'i', 'p', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3368
  /* 132 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3369
  /* 170 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3370
  /* 208 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 'r', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3371
  /* 247 */ 'Z', 'P', 'R', '4', 0,
3372
  /* 252 */ 'F', 'P', 'R', '1', '6', 0,
3373
  /* 258 */ 'F', 'P', 'R', '1', '2', '8', 0,
3374
  /* 265 */ 'F', 'P', 'R', '8', 0,
3375
  /* 270 */ 'D', 'D', 'D', 'D', 0,
3376
  /* 275 */ 'Q', 'Q', 'Q', 'Q', 0,
3377
  /* 280 */ 'C', 'C', 'R', 0,
3378
  /* 284 */ 'P', 'P', 'R', 0,
3379
  /* 288 */ 'Z', 'P', 'R', 0,
3380
  /* 292 */ 'P', 'P', 'R', '_', '3', 'b', 0,
3381
  /* 299 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3382
  /* 325 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3383
  /* 351 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3384
  /* 377 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3385
  /* 435 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3386
  /* 493 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3387
  /* 551 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3388
  /* 607 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3389
  /* 665 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3390
  /* 721 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3391
  /* 779 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3392
  /* 835 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3393
  /* 891 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3394
  /* 949 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3395
  /* 1007 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3396
  /* 1065 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3397
  /* 1123 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3398
  /* 1179 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3399
  /* 1237 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3400
  /* 1293 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3401
  /* 1351 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3402
  /* 1407 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3403
  /* 1463 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3404
  /* 1521 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'a', 'r', 'g', 0,
3405
  /* 1560 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'a', 'r', 'g', 0,
3406
  /* 1599 */ 'G', 'P', 'R', '6', '4', 'a', 'r', 'g', 0,
3407
  /* 1608 */ 'G', 'P', 'R', '3', '2', 'a', 'l', 'l', 0,
3408
  /* 1617 */ 'G', 'P', 'R', '6', '4', 'a', 'l', 'l', 0,
3409
  /* 1626 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3410
  /* 1668 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3411
  /* 1710 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3412
  /* 1739 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3413
  /* 1801 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3414
  /* 1861 */ 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3415
  /* 1919 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3416
  /* 1981 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3417
  /* 2043 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3418
  /* 2103 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3419
  /* 2163 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3420
  /* 2225 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3421
  /* 2287 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3422
  /* 2349 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3423
  /* 2377 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3424
  /* 2405 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3425
  /* 2433 */ 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', '6', '4', 'n', 'o', 'i', 'p', 0,
3426
  /* 2459 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'n', 'o', 'i', 'p', 0,
3427
  /* 2499 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'n', 'o', 'i', 'p', 0,
3428
  /* 2539 */ 'G', 'P', 'R', '3', '2', 's', 'p', 0,
3429
  /* 2547 */ 'G', 'P', 'R', '6', '4', 's', 'p', 0,
3430
  /* 2555 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
3431
  /* 2570 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
3432
  /* 2585 */ 'G', 'P', 'R', '3', '2', 's', 'p', 'o', 'n', 'l', 'y', 0,
3433
  /* 2597 */ 'G', 'P', 'R', '6', '4', 's', 'p', 'o', 'n', 'l', 'y', 0,
3434
};
3435
3436
extern const MCRegisterClass AArch64MCRegisterClasses[] = {
3437
  { FPR8, FPR8Bits, 265, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, true },
3438
  { FPR16, FPR16Bits, 252, 32, sizeof(FPR16Bits), AArch64::FPR16RegClassID, 1, true },
3439
  { PPR, PPRBits, 284, 16, sizeof(PPRBits), AArch64::PPRRegClassID, 1, true },
3440
  { PPR_3b, PPR_3bBits, 292, 8, sizeof(PPR_3bBits), AArch64::PPR_3bRegClassID, 1, true },
3441
  { GPR32all, GPR32allBits, 1608, 33, sizeof(GPR32allBits), AArch64::GPR32allRegClassID, 1, true },
3442
  { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64::FPR32RegClassID, 1, true },
3443
  { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 1, true },
3444
  { GPR32sp, GPR32spBits, 2539, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 1, true },
3445
  { GPR32common, GPR32commonBits, 1656, 31, sizeof(GPR32commonBits), AArch64::GPR32commonRegClassID, 1, true },
3446
  { GPR32arg, GPR32argBits, 1551, 8, sizeof(GPR32argBits), AArch64::GPR32argRegClassID, 1, true },
3447
  { CCR, CCRBits, 280, 1, sizeof(CCRBits), AArch64::CCRRegClassID, -1, false },
3448
  { GPR32sponly, GPR32sponlyBits, 2585, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 1, true },
3449
  { WSeqPairsClass, WSeqPairsClassBits, 2555, 16, sizeof(WSeqPairsClassBits), AArch64::WSeqPairsClassRegClassID, 1, true },
3450
  { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, 1626, 15, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 1, true },
3451
  { WSeqPairsClass_with_sube32_in_GPR32arg, WSeqPairsClass_with_sube32_in_GPR32argBits, 1560, 4, sizeof(WSeqPairsClass_with_sube32_in_GPR32argBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32argRegClassID, 1, true },
3452
  { GPR64all, GPR64allBits, 1617, 33, sizeof(GPR64allBits), AArch64::GPR64allRegClassID, 1, true },
3453
  { FPR64, FPR64Bits, 22, 32, sizeof(FPR64Bits), AArch64::FPR64RegClassID, 1, true },
3454
  { GPR64, GPR64Bits, 74, 32, sizeof(GPR64Bits), AArch64::GPR64RegClassID, 1, true },
3455
  { GPR64sp, GPR64spBits, 2547, 32, sizeof(GPR64spBits), AArch64::GPR64spRegClassID, 1, true },
3456
  { GPR64common, GPR64commonBits, 1698, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 1, true },
3457
  { GPR64noip, GPR64noipBits, 2449, 29, sizeof(GPR64noipBits), AArch64::GPR64noipRegClassID, 1, true },
3458
  { GPR64common_and_GPR64noip, GPR64common_and_GPR64noipBits, 2433, 28, sizeof(GPR64common_and_GPR64noipBits), AArch64::GPR64common_and_GPR64noipRegClassID, 1, true },
3459
  { tcGPR64, tcGPR64Bits, 72, 19, sizeof(tcGPR64Bits), AArch64::tcGPR64RegClassID, 1, true },
3460
  { GPR64noip_and_tcGPR64, GPR64noip_and_tcGPR64Bits, 58, 17, sizeof(GPR64noip_and_tcGPR64Bits), AArch64::GPR64noip_and_tcGPR64RegClassID, 1, true },
3461
  { GPR64arg, GPR64argBits, 1599, 8, sizeof(GPR64argBits), AArch64::GPR64argRegClassID, 1, true },
3462
  { rtcGPR64, rtcGPR64Bits, 238, 2, sizeof(rtcGPR64Bits), AArch64::rtcGPR64RegClassID, 1, true },
3463
  { GPR64sponly, GPR64sponlyBits, 2597, 1, sizeof(GPR64sponlyBits), AArch64::GPR64sponlyRegClassID, 1, true },
3464
  { DD, DDBits, 272, 32, sizeof(DDBits), AArch64::DDRegClassID, 1, true },
3465
  { XSeqPairsClass, XSeqPairsClassBits, 2570, 16, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 1, true },
3466
  { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, 1668, 15, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 1, true },
3467
  { XSeqPairsClass_with_subo64_in_GPR64noip, XSeqPairsClass_with_subo64_in_GPR64noipBits, 2499, 15, sizeof(XSeqPairsClass_with_subo64_in_GPR64noipBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClassID, 1, true },
3468
  { XSeqPairsClass_with_sube64_in_GPR64noip, XSeqPairsClass_with_sube64_in_GPR64noipBits, 2459, 14, sizeof(XSeqPairsClass_with_sube64_in_GPR64noipBits), AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClassID, 1, true },
3469
  { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, 132, 10, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, 1, true },
3470
  { XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64, XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits, 28, 9, sizeof(XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClassID, 1, true },
3471
  { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, 170, 9, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 1, true },
3472
  { XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64, XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits, 80, 8, sizeof(XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID, 1, true },
3473
  { XSeqPairsClass_with_sub_32_in_GPR32arg, XSeqPairsClass_with_sub_32_in_GPR32argBits, 1521, 4, sizeof(XSeqPairsClass_with_sub_32_in_GPR32argBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32argRegClassID, 1, true },
3474
  { XSeqPairsClass_with_sube64_in_rtcGPR64, XSeqPairsClass_with_sube64_in_rtcGPR64Bits, 208, 1, sizeof(XSeqPairsClass_with_sube64_in_rtcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID, 1, true },
3475
  { FPR128, FPR128Bits, 258, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 1, true },
3476
  { ZPR, ZPRBits, 288, 32, sizeof(ZPRBits), AArch64::ZPRRegClassID, 1, true },
3477
  { FPR128_lo, FPR128_loBits, 1729, 16, sizeof(FPR128_loBits), AArch64::FPR128_loRegClassID, 1, true },
3478
  { ZPR_4b, ZPR_4bBits, 1000, 16, sizeof(ZPR_4bBits), AArch64::ZPR_4bRegClassID, 1, true },
3479
  { ZPR_3b, ZPR_3bBits, 318, 8, sizeof(ZPR_3bBits), AArch64::ZPR_3bRegClassID, 1, true },
3480
  { DDD, DDDBits, 271, 32, sizeof(DDDBits), AArch64::DDDRegClassID, 1, true },
3481
  { DDDD, DDDDBits, 270, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 1, true },
3482
  { QQ, QQBits, 277, 32, sizeof(QQBits), AArch64::QQRegClassID, 1, true },
3483
  { ZPR2, ZPR2Bits, 12, 32, sizeof(ZPR2Bits), AArch64::ZPR2RegClassID, 1, true },
3484
  { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 1712, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3485
  { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 1774, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3486
  { ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub1_in_ZPR_4bBits, 981, 16, sizeof(ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3487
  { ZPR2_with_zsub_in_FPR128_lo, ZPR2_with_zsub_in_FPR128_loBits, 2349, 16, sizeof(ZPR2_with_zsub_in_FPR128_loBits), AArch64::ZPR2_with_zsub_in_FPR128_loRegClassID, 1, true },
3488
  { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 1861, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3489
  { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits, 949, 15, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3490
  { ZPR2_with_zsub0_in_ZPR_3b, ZPR2_with_zsub0_in_ZPR_3bBits, 299, 8, sizeof(ZPR2_with_zsub0_in_ZPR_3bBits), AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3491
  { ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub1_in_ZPR_3bBits, 409, 8, sizeof(ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3492
  { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits, 377, 7, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3493
  { QQQ, QQQBits, 276, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 1, true },
3494
  { ZPR3, ZPR3Bits, 17, 32, sizeof(ZPR3Bits), AArch64::ZPR3RegClassID, 1, true },
3495
  { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 1711, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3496
  { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 1773, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3497
  { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 1953, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3498
  { ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4bBits, 1039, 16, sizeof(ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3499
  { ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub2_in_ZPR_4bBits, 1153, 16, sizeof(ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3500
  { ZPR3_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_loBits, 2377, 16, sizeof(ZPR3_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub_in_FPR128_loRegClassID, 1, true },
3501
  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 1801, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3502
  { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2103, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3503
  { ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1123, 15, sizeof(ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3504
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits, 1007, 15, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3505
  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2043, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3506
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1179, 14, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3507
  { ZPR3_with_zsub0_in_ZPR_3b, ZPR3_with_zsub0_in_ZPR_3bBits, 325, 8, sizeof(ZPR3_with_zsub0_in_ZPR_3bBits), AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3508
  { ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3bBits, 467, 8, sizeof(ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3509
  { ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub2_in_ZPR_3bBits, 581, 8, sizeof(ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3510
  { ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits, 551, 7, sizeof(ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3511
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits, 435, 7, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3512
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits, 607, 6, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3513
  { QQQQ, QQQQBits, 275, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 1, true },
3514
  { ZPR4, ZPR4Bits, 247, 32, sizeof(ZPR4Bits), AArch64::ZPR4RegClassID, 1, true },
3515
  { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 1710, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3516
  { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 1772, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3517
  { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 1952, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3518
  { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 2196, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3519
  { ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4bBits, 1097, 16, sizeof(ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3520
  { ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4bBits, 1267, 16, sizeof(ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3521
  { ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub3_in_ZPR_4bBits, 1381, 16, sizeof(ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3522
  { ZPR4_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_loBits, 2405, 16, sizeof(ZPR4_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub_in_FPR128_loRegClassID, 1, true },
3523
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 1739, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3524
  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 1981, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3525
  { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2287, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3526
  { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1237, 15, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3527
  { ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1407, 15, sizeof(ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3528
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits, 1065, 15, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3529
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 1919, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3530
  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2225, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3531
  { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1351, 14, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3532
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1293, 14, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3533
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2163, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3534
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1463, 13, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3535
  { ZPR4_with_zsub0_in_ZPR_3b, ZPR4_with_zsub0_in_ZPR_3bBits, 351, 8, sizeof(ZPR4_with_zsub0_in_ZPR_3bBits), AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3536
  { ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3bBits, 525, 8, sizeof(ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3537
  { ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3bBits, 695, 8, sizeof(ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3538
  { ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub3_in_ZPR_3bBits, 809, 8, sizeof(ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3539
  { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits, 665, 7, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3540
  { ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 835, 7, sizeof(ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3541
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits, 493, 7, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3542
  { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 779, 6, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3543
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits, 721, 6, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3544
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits, 891, 5, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3545
};
3546
3547
// AArch64 Dwarf<->LLVM register mappings.
3548
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
3549
  { 0U, AArch64::W0 },
3550
  { 1U, AArch64::W1 },
3551
  { 2U, AArch64::W2 },
3552
  { 3U, AArch64::W3 },
3553
  { 4U, AArch64::W4 },
3554
  { 5U, AArch64::W5 },
3555
  { 6U, AArch64::W6 },
3556
  { 7U, AArch64::W7 },
3557
  { 8U, AArch64::W8 },
3558
  { 9U, AArch64::W9 },
3559
  { 10U, AArch64::W10 },
3560
  { 11U, AArch64::W11 },
3561
  { 12U, AArch64::W12 },
3562
  { 13U, AArch64::W13 },
3563
  { 14U, AArch64::W14 },
3564
  { 15U, AArch64::W15 },
3565
  { 16U, AArch64::W16 },
3566
  { 17U, AArch64::W17 },
3567
  { 18U, AArch64::W18 },
3568
  { 19U, AArch64::W19 },
3569
  { 20U, AArch64::W20 },
3570
  { 21U, AArch64::W21 },
3571
  { 22U, AArch64::W22 },
3572
  { 23U, AArch64::W23 },
3573
  { 24U, AArch64::W24 },
3574
  { 25U, AArch64::W25 },
3575
  { 26U, AArch64::W26 },
3576
  { 27U, AArch64::W27 },
3577
  { 28U, AArch64::W28 },
3578
  { 29U, AArch64::W29 },
3579
  { 30U, AArch64::W30 },
3580
  { 31U, AArch64::WSP },
3581
  { 47U, AArch64::FFR },
3582
  { 48U, AArch64::P0 },
3583
  { 49U, AArch64::P1 },
3584
  { 50U, AArch64::P2 },
3585
  { 51U, AArch64::P3 },
3586
  { 52U, AArch64::P4 },
3587
  { 53U, AArch64::P5 },
3588
  { 54U, AArch64::P6 },
3589
  { 55U, AArch64::P7 },
3590
  { 56U, AArch64::P8 },
3591
  { 57U, AArch64::P9 },
3592
  { 58U, AArch64::P10 },
3593
  { 59U, AArch64::P11 },
3594
  { 60U, AArch64::P12 },
3595
  { 61U, AArch64::P13 },
3596
  { 62U, AArch64::P14 },
3597
  { 63U, AArch64::P15 },
3598
  { 64U, AArch64::B0 },
3599
  { 65U, AArch64::B1 },
3600
  { 66U, AArch64::B2 },
3601
  { 67U, AArch64::B3 },
3602
  { 68U, AArch64::B4 },
3603
  { 69U, AArch64::B5 },
3604
  { 70U, AArch64::B6 },
3605
  { 71U, AArch64::B7 },
3606
  { 72U, AArch64::B8 },
3607
  { 73U, AArch64::B9 },
3608
  { 74U, AArch64::B10 },
3609
  { 75U, AArch64::B11 },
3610
  { 76U, AArch64::B12 },
3611
  { 77U, AArch64::B13 },
3612
  { 78U, AArch64::B14 },
3613
  { 79U, AArch64::B15 },
3614
  { 80U, AArch64::B16 },
3615
  { 81U, AArch64::B17 },
3616
  { 82U, AArch64::B18 },
3617
  { 83U, AArch64::B19 },
3618
  { 84U, AArch64::B20 },
3619
  { 85U, AArch64::B21 },
3620
  { 86U, AArch64::B22 },
3621
  { 87U, AArch64::B23 },
3622
  { 88U, AArch64::B24 },
3623
  { 89U, AArch64::B25 },
3624
  { 90U, AArch64::B26 },
3625
  { 91U, AArch64::B27 },
3626
  { 92U, AArch64::B28 },
3627
  { 93U, AArch64::B29 },
3628
  { 94U, AArch64::B30 },
3629
  { 95U, AArch64::B31 },
3630
  { 96U, AArch64::Z0 },
3631
  { 97U, AArch64::Z1 },
3632
  { 98U, AArch64::Z2 },
3633
  { 99U, AArch64::Z3 },
3634
  { 100U, AArch64::Z4 },
3635
  { 101U, AArch64::Z5 },
3636
  { 102U, AArch64::Z6 },
3637
  { 103U, AArch64::Z7 },
3638
  { 104U, AArch64::Z8 },
3639
  { 105U, AArch64::Z9 },
3640
  { 106U, AArch64::Z10 },
3641
  { 107U, AArch64::Z11 },
3642
  { 108U, AArch64::Z12 },
3643
  { 109U, AArch64::Z13 },
3644
  { 110U, AArch64::Z14 },
3645
  { 111U, AArch64::Z15 },
3646
  { 112U, AArch64::Z16 },
3647
  { 113U, AArch64::Z17 },
3648
  { 114U, AArch64::Z18 },
3649
  { 115U, AArch64::Z19 },
3650
  { 116U, AArch64::Z20 },
3651
  { 117U, AArch64::Z21 },
3652
  { 118U, AArch64::Z22 },
3653
  { 119U, AArch64::Z23 },
3654
  { 120U, AArch64::Z24 },
3655
  { 121U, AArch64::Z25 },
3656
  { 122U, AArch64::Z26 },
3657
  { 123U, AArch64::Z27 },
3658
  { 124U, AArch64::Z28 },
3659
  { 125U, AArch64::Z29 },
3660
  { 126U, AArch64::Z30 },
3661
  { 127U, AArch64::Z31 },
3662
};
3663
extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = array_lengthof(AArch64DwarfFlavour0Dwarf2L);
3664
3665
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
3666
  { 0U, AArch64::W0 },
3667
  { 1U, AArch64::W1 },
3668
  { 2U, AArch64::W2 },
3669
  { 3U, AArch64::W3 },
3670
  { 4U, AArch64::W4 },
3671
  { 5U, AArch64::W5 },
3672
  { 6U, AArch64::W6 },
3673
  { 7U, AArch64::W7 },
3674
  { 8U, AArch64::W8 },
3675
  { 9U, AArch64::W9 },
3676
  { 10U, AArch64::W10 },
3677
  { 11U, AArch64::W11 },
3678
  { 12U, AArch64::W12 },
3679
  { 13U, AArch64::W13 },
3680
  { 14U, AArch64::W14 },
3681
  { 15U, AArch64::W15 },
3682
  { 16U, AArch64::W16 },
3683
  { 17U, AArch64::W17 },
3684
  { 18U, AArch64::W18 },
3685
  { 19U, AArch64::W19 },
3686
  { 20U, AArch64::W20 },
3687
  { 21U, AArch64::W21 },
3688
  { 22U, AArch64::W22 },
3689
  { 23U, AArch64::W23 },
3690
  { 24U, AArch64::W24 },
3691
  { 25U, AArch64::W25 },
3692
  { 26U, AArch64::W26 },
3693
  { 27U, AArch64::W27 },
3694
  { 28U, AArch64::W28 },
3695
  { 29U, AArch64::W29 },
3696
  { 30U, AArch64::W30 },
3697
  { 31U, AArch64::WSP },
3698
  { 47U, AArch64::FFR },
3699
  { 48U, AArch64::P0 },
3700
  { 49U, AArch64::P1 },
3701
  { 50U, AArch64::P2 },
3702
  { 51U, AArch64::P3 },
3703
  { 52U, AArch64::P4 },
3704
  { 53U, AArch64::P5 },
3705
  { 54U, AArch64::P6 },
3706
  { 55U, AArch64::P7 },
3707
  { 56U, AArch64::P8 },
3708
  { 57U, AArch64::P9 },
3709
  { 58U, AArch64::P10 },
3710
  { 59U, AArch64::P11 },
3711
  { 60U, AArch64::P12 },
3712
  { 61U, AArch64::P13 },
3713
  { 62U, AArch64::P14 },
3714
  { 63U, AArch64::P15 },
3715
  { 64U, AArch64::B0 },
3716
  { 65U, AArch64::B1 },
3717
  { 66U, AArch64::B2 },
3718
  { 67U, AArch64::B3 },
3719
  { 68U, AArch64::B4 },
3720
  { 69U, AArch64::B5 },
3721
  { 70U, AArch64::B6 },
3722
  { 71U, AArch64::B7 },
3723
  { 72U, AArch64::B8 },
3724
  { 73U, AArch64::B9 },
3725
  { 74U, AArch64::B10 },
3726
  { 75U, AArch64::B11 },
3727
  { 76U, AArch64::B12 },
3728
  { 77U, AArch64::B13 },
3729
  { 78U, AArch64::B14 },
3730
  { 79U, AArch64::B15 },
3731
  { 80U, AArch64::B16 },
3732
  { 81U, AArch64::B17 },
3733
  { 82U, AArch64::B18 },
3734
  { 83U, AArch64::B19 },
3735
  { 84U, AArch64::B20 },
3736
  { 85U, AArch64::B21 },
3737
  { 86U, AArch64::B22 },
3738
  { 87U, AArch64::B23 },
3739
  { 88U, AArch64::B24 },
3740
  { 89U, AArch64::B25 },
3741
  { 90U, AArch64::B26 },
3742
  { 91U, AArch64::B27 },
3743
  { 92U, AArch64::B28 },
3744
  { 93U, AArch64::B29 },
3745
  { 94U, AArch64::B30 },
3746
  { 95U, AArch64::B31 },
3747
  { 96U, AArch64::Z0 },
3748
  { 97U, AArch64::Z1 },
3749
  { 98U, AArch64::Z2 },
3750
  { 99U, AArch64::Z3 },
3751
  { 100U, AArch64::Z4 },
3752
  { 101U, AArch64::Z5 },
3753
  { 102U, AArch64::Z6 },
3754
  { 103U, AArch64::Z7 },
3755
  { 104U, AArch64::Z8 },
3756
  { 105U, AArch64::Z9 },
3757
  { 106U, AArch64::Z10 },
3758
  { 107U, AArch64::Z11 },
3759
  { 108U, AArch64::Z12 },
3760
  { 109U, AArch64::Z13 },
3761
  { 110U, AArch64::Z14 },
3762
  { 111U, AArch64::Z15 },
3763
  { 112U, AArch64::Z16 },
3764
  { 113U, AArch64::Z17 },
3765
  { 114U, AArch64::Z18 },
3766
  { 115U, AArch64::Z19 },
3767
  { 116U, AArch64::Z20 },
3768
  { 117U, AArch64::Z21 },
3769
  { 118U, AArch64::Z22 },
3770
  { 119U, AArch64::Z23 },
3771
  { 120U, AArch64::Z24 },
3772
  { 121U, AArch64::Z25 },
3773
  { 122U, AArch64::Z26 },
3774
  { 123U, AArch64::Z27 },
3775
  { 124U, AArch64::Z28 },
3776
  { 125U, AArch64::Z29 },
3777
  { 126U, AArch64::Z30 },
3778
  { 127U, AArch64::Z31 },
3779
};
3780
extern const unsigned AArch64EHFlavour0Dwarf2LSize = array_lengthof(AArch64EHFlavour0Dwarf2L);
3781
3782
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
3783
  { AArch64::FFR, 47U },
3784
  { AArch64::FP, 29U },
3785
  { AArch64::LR, 30U },
3786
  { AArch64::SP, 31U },
3787
  { AArch64::WSP, 31U },
3788
  { AArch64::WZR, 31U },
3789
  { AArch64::XZR, 31U },
3790
  { AArch64::B0, 64U },
3791
  { AArch64::B1, 65U },
3792
  { AArch64::B2, 66U },
3793
  { AArch64::B3, 67U },
3794
  { AArch64::B4, 68U },
3795
  { AArch64::B5, 69U },
3796
  { AArch64::B6, 70U },
3797
  { AArch64::B7, 71U },
3798
  { AArch64::B8, 72U },
3799
  { AArch64::B9, 73U },
3800
  { AArch64::B10, 74U },
3801
  { AArch64::B11, 75U },
3802
  { AArch64::B12, 76U },
3803
  { AArch64::B13, 77U },
3804
  { AArch64::B14, 78U },
3805
  { AArch64::B15, 79U },
3806
  { AArch64::B16, 80U },
3807
  { AArch64::B17, 81U },
3808
  { AArch64::B18, 82U },
3809
  { AArch64::B19, 83U },
3810
  { AArch64::B20, 84U },
3811
  { AArch64::B21, 85U },
3812
  { AArch64::B22, 86U },
3813
  { AArch64::B23, 87U },
3814
  { AArch64::B24, 88U },
3815
  { AArch64::B25, 89U },
3816
  { AArch64::B26, 90U },
3817
  { AArch64::B27, 91U },
3818
  { AArch64::B28, 92U },
3819
  { AArch64::B29, 93U },
3820
  { AArch64::B30, 94U },
3821
  { AArch64::B31, 95U },
3822
  { AArch64::D0, 64U },
3823
  { AArch64::D1, 65U },
3824
  { AArch64::D2, 66U },
3825
  { AArch64::D3, 67U },
3826
  { AArch64::D4, 68U },
3827
  { AArch64::D5, 69U },
3828
  { AArch64::D6, 70U },
3829
  { AArch64::D7, 71U },
3830
  { AArch64::D8, 72U },
3831
  { AArch64::D9, 73U },
3832
  { AArch64::D10, 74U },
3833
  { AArch64::D11, 75U },
3834
  { AArch64::D12, 76U },
3835
  { AArch64::D13, 77U },
3836
  { AArch64::D14, 78U },
3837
  { AArch64::D15, 79U },
3838
  { AArch64::D16, 80U },
3839
  { AArch64::D17, 81U },
3840
  { AArch64::D18, 82U },
3841
  { AArch64::D19, 83U },
3842
  { AArch64::D20, 84U },
3843
  { AArch64::D21, 85U },
3844
  { AArch64::D22, 86U },
3845
  { AArch64::D23, 87U },
3846
  { AArch64::D24, 88U },
3847
  { AArch64::D25, 89U },
3848
  { AArch64::D26, 90U },
3849
  { AArch64::D27, 91U },
3850
  { AArch64::D28, 92U },
3851
  { AArch64::D29, 93U },
3852
  { AArch64::D30, 94U },
3853
  { AArch64::D31, 95U },
3854
  { AArch64::H0, 64U },
3855
  { AArch64::H1, 65U },
3856
  { AArch64::H2, 66U },
3857
  { AArch64::H3, 67U },
3858
  { AArch64::H4, 68U },
3859
  { AArch64::H5, 69U },
3860
  { AArch64::H6, 70U },
3861
  { AArch64::H7, 71U },
3862
  { AArch64::H8, 72U },
3863
  { AArch64::H9, 73U },
3864
  { AArch64::H10, 74U },
3865
  { AArch64::H11, 75U },
3866
  { AArch64::H12, 76U },
3867
  { AArch64::H13, 77U },
3868
  { AArch64::H14, 78U },
3869
  { AArch64::H15, 79U },
3870
  { AArch64::H16, 80U },
3871
  { AArch64::H17, 81U },
3872
  { AArch64::H18, 82U },
3873
  { AArch64::H19, 83U },
3874
  { AArch64::H20, 84U },
3875
  { AArch64::H21, 85U },
3876
  { AArch64::H22, 86U },
3877
  { AArch64::H23, 87U },
3878
  { AArch64::H24, 88U },
3879
  { AArch64::H25, 89U },
3880
  { AArch64::H26, 90U },
3881
  { AArch64::H27, 91U },
3882
  { AArch64::H28, 92U },
3883
  { AArch64::H29, 93U },
3884
  { AArch64::H30, 94U },
3885
  { AArch64::H31, 95U },
3886
  { AArch64::P0, 48U },
3887
  { AArch64::P1, 49U },
3888
  { AArch64::P2, 50U },
3889
  { AArch64::P3, 51U },
3890
  { AArch64::P4, 52U },
3891
  { AArch64::P5, 53U },
3892
  { AArch64::P6, 54U },
3893
  { AArch64::P7, 55U },
3894
  { AArch64::P8, 56U },
3895
  { AArch64::P9, 57U },
3896
  { AArch64::P10, 58U },
3897
  { AArch64::P11, 59U },
3898
  { AArch64::P12, 60U },
3899
  { AArch64::P13, 61U },
3900
  { AArch64::P14, 62U },
3901
  { AArch64::P15, 63U },
3902
  { AArch64::Q0, 64U },
3903
  { AArch64::Q1, 65U },
3904
  { AArch64::Q2, 66U },
3905
  { AArch64::Q3, 67U },
3906
  { AArch64::Q4, 68U },
3907
  { AArch64::Q5, 69U },
3908
  { AArch64::Q6, 70U },
3909
  { AArch64::Q7, 71U },
3910
  { AArch64::Q8, 72U },
3911
  { AArch64::Q9, 73U },
3912
  { AArch64::Q10, 74U },
3913
  { AArch64::Q11, 75U },
3914
  { AArch64::Q12, 76U },
3915
  { AArch64::Q13, 77U },
3916
  { AArch64::Q14, 78U },
3917
  { AArch64::Q15, 79U },
3918
  { AArch64::Q16, 80U },
3919
  { AArch64::Q17, 81U },
3920
  { AArch64::Q18, 82U },
3921
  { AArch64::Q19, 83U },
3922
  { AArch64::Q20, 84U },
3923
  { AArch64::Q21, 85U },
3924
  { AArch64::Q22, 86U },
3925
  { AArch64::Q23, 87U },
3926
  { AArch64::Q24, 88U },
3927
  { AArch64::Q25, 89U },
3928
  { AArch64::Q26, 90U },
3929
  { AArch64::Q27, 91U },
3930
  { AArch64::Q28, 92U },
3931
  { AArch64::Q29, 93U },
3932
  { AArch64::Q30, 94U },
3933
  { AArch64::Q31, 95U },
3934
  { AArch64::S0, 64U },
3935
  { AArch64::S1, 65U },
3936
  { AArch64::S2, 66U },
3937
  { AArch64::S3, 67U },
3938
  { AArch64::S4, 68U },
3939
  { AArch64::S5, 69U },
3940
  { AArch64::S6, 70U },
3941
  { AArch64::S7, 71U },
3942
  { AArch64::S8, 72U },
3943
  { AArch64::S9, 73U },
3944
  { AArch64::S10, 74U },
3945
  { AArch64::S11, 75U },
3946
  { AArch64::S12, 76U },
3947
  { AArch64::S13, 77U },
3948
  { AArch64::S14, 78U },
3949
  { AArch64::S15, 79U },
3950
  { AArch64::S16, 80U },
3951
  { AArch64::S17, 81U },
3952
  { AArch64::S18, 82U },
3953
  { AArch64::S19, 83U },
3954
  { AArch64::S20, 84U },
3955
  { AArch64::S21, 85U },
3956
  { AArch64::S22, 86U },
3957
  { AArch64::S23, 87U },
3958
  { AArch64::S24, 88U },
3959
  { AArch64::S25, 89U },
3960
  { AArch64::S26, 90U },
3961
  { AArch64::S27, 91U },
3962
  { AArch64::S28, 92U },
3963
  { AArch64::S29, 93U },
3964
  { AArch64::S30, 94U },
3965
  { AArch64::S31, 95U },
3966
  { AArch64::W0, 0U },
3967
  { AArch64::W1, 1U },
3968
  { AArch64::W2, 2U },
3969
  { AArch64::W3, 3U },
3970
  { AArch64::W4, 4U },
3971
  { AArch64::W5, 5U },
3972
  { AArch64::W6, 6U },
3973
  { AArch64::W7, 7U },
3974
  { AArch64::W8, 8U },
3975
  { AArch64::W9, 9U },
3976
  { AArch64::W10, 10U },
3977
  { AArch64::W11, 11U },
3978
  { AArch64::W12, 12U },
3979
  { AArch64::W13, 13U },
3980
  { AArch64::W14, 14U },
3981
  { AArch64::W15, 15U },
3982
  { AArch64::W16, 16U },
3983
  { AArch64::W17, 17U },
3984
  { AArch64::W18, 18U },
3985
  { AArch64::W19, 19U },
3986
  { AArch64::W20, 20U },
3987
  { AArch64::W21, 21U },
3988
  { AArch64::W22, 22U },
3989
  { AArch64::W23, 23U },
3990
  { AArch64::W24, 24U },
3991
  { AArch64::W25, 25U },
3992
  { AArch64::W26, 26U },
3993
  { AArch64::W27, 27U },
3994
  { AArch64::W28, 28U },
3995
  { AArch64::W29, 29U },
3996
  { AArch64::W30, 30U },
3997
  { AArch64::X0, 0U },
3998
  { AArch64::X1, 1U },
3999
  { AArch64::X2, 2U },
4000
  { AArch64::X3, 3U },
4001
  { AArch64::X4, 4U },
4002
  { AArch64::X5, 5U },
4003
  { AArch64::X6, 6U },
4004
  { AArch64::X7, 7U },
4005
  { AArch64::X8, 8U },
4006
  { AArch64::X9, 9U },
4007
  { AArch64::X10, 10U },
4008
  { AArch64::X11, 11U },
4009
  { AArch64::X12, 12U },
4010
  { AArch64::X13, 13U },
4011
  { AArch64::X14, 14U },
4012
  { AArch64::X15, 15U },
4013
  { AArch64::X16, 16U },
4014
  { AArch64::X17, 17U },
4015
  { AArch64::X18, 18U },
4016
  { AArch64::X19, 19U },
4017
  { AArch64::X20, 20U },
4018
  { AArch64::X21, 21U },
4019
  { AArch64::X22, 22U },
4020
  { AArch64::X23, 23U },
4021
  { AArch64::X24, 24U },
4022
  { AArch64::X25, 25U },
4023
  { AArch64::X26, 26U },
4024
  { AArch64::X27, 27U },
4025
  { AArch64::X28, 28U },
4026
  { AArch64::Z0, 96U },
4027
  { AArch64::Z1, 97U },
4028
  { AArch64::Z2, 98U },
4029
  { AArch64::Z3, 99U },
4030
  { AArch64::Z4, 100U },
4031
  { AArch64::Z5, 101U },
4032
  { AArch64::Z6, 102U },
4033
  { AArch64::Z7, 103U },
4034
  { AArch64::Z8, 104U },
4035
  { AArch64::Z9, 105U },
4036
  { AArch64::Z10, 106U },
4037
  { AArch64::Z11, 107U },
4038
  { AArch64::Z12, 108U },
4039
  { AArch64::Z13, 109U },
4040
  { AArch64::Z14, 110U },
4041
  { AArch64::Z15, 111U },
4042
  { AArch64::Z16, 112U },
4043
  { AArch64::Z17, 113U },
4044
  { AArch64::Z18, 114U },
4045
  { AArch64::Z19, 115U },
4046
  { AArch64::Z20, 116U },
4047
  { AArch64::Z21, 117U },
4048
  { AArch64::Z22, 118U },
4049
  { AArch64::Z23, 119U },
4050
  { AArch64::Z24, 120U },
4051
  { AArch64::Z25, 121U },
4052
  { AArch64::Z26, 122U },
4053
  { AArch64::Z27, 123U },
4054
  { AArch64::Z28, 124U },
4055
  { AArch64::Z29, 125U },
4056
  { AArch64::Z30, 126U },
4057
  { AArch64::Z31, 127U },
4058
};
4059
extern const unsigned AArch64DwarfFlavour0L2DwarfSize = array_lengthof(AArch64DwarfFlavour0L2Dwarf);
4060
4061
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
4062
  { AArch64::FFR, 47U },
4063
  { AArch64::FP, 29U },
4064
  { AArch64::LR, 30U },
4065
  { AArch64::SP, 31U },
4066
  { AArch64::WSP, 31U },
4067
  { AArch64::WZR, 31U },
4068
  { AArch64::XZR, 31U },
4069
  { AArch64::B0, 64U },
4070
  { AArch64::B1, 65U },
4071
  { AArch64::B2, 66U },
4072
  { AArch64::B3, 67U },
4073
  { AArch64::B4, 68U },
4074
  { AArch64::B5, 69U },
4075
  { AArch64::B6, 70U },
4076
  { AArch64::B7, 71U },
4077
  { AArch64::B8, 72U },
4078
  { AArch64::B9, 73U },
4079
  { AArch64::B10, 74U },
4080
  { AArch64::B11, 75U },
4081
  { AArch64::B12, 76U },
4082
  { AArch64::B13, 77U },
4083
  { AArch64::B14, 78U },
4084
  { AArch64::B15, 79U },
4085
  { AArch64::B16, 80U },
4086
  { AArch64::B17, 81U },
4087
  { AArch64::B18, 82U },
4088
  { AArch64::B19, 83U },
4089
  { AArch64::B20, 84U },
4090
  { AArch64::B21, 85U },
4091
  { AArch64::B22, 86U },
4092
  { AArch64::B23, 87U },
4093
  { AArch64::B24, 88U },
4094
  { AArch64::B25, 89U },
4095
  { AArch64::B26, 90U },
4096
  { AArch64::B27, 91U },
4097
  { AArch64::B28, 92U },
4098
  { AArch64::B29, 93U },
4099
  { AArch64::B30, 94U },
4100
  { AArch64::B31, 95U },
4101
  { AArch64::D0, 64U },
4102
  { AArch64::D1, 65U },
4103
  { AArch64::D2, 66U },
4104
  { AArch64::D3, 67U },
4105
  { AArch64::D4, 68U },
4106
  { AArch64::D5, 69U },
4107
  { AArch64::D6, 70U },
4108
  { AArch64::D7, 71U },
4109
  { AArch64::D8, 72U },
4110
  { AArch64::D9, 73U },
4111
  { AArch64::D10, 74U },
4112
  { AArch64::D11, 75U },
4113
  { AArch64::D12, 76U },
4114
  { AArch64::D13, 77U },
4115
  { AArch64::D14, 78U },
4116
  { AArch64::D15, 79U },
4117
  { AArch64::D16, 80U },
4118
  { AArch64::D17, 81U },
4119
  { AArch64::D18, 82U },
4120
  { AArch64::D19, 83U },
4121
  { AArch64::D20, 84U },
4122
  { AArch64::D21, 85U },
4123
  { AArch64::D22, 86U },
4124
  { AArch64::D23, 87U },
4125
  { AArch64::D24, 88U },
4126
  { AArch64::D25, 89U },
4127
  { AArch64::D26, 90U },
4128
  { AArch64::D27, 91U },
4129
  { AArch64::D28, 92U },
4130
  { AArch64::D29, 93U },
4131
  { AArch64::D30, 94U },
4132
  { AArch64::D31, 95U },
4133
  { AArch64::H0, 64U },
4134
  { AArch64::H1, 65U },
4135
  { AArch64::H2, 66U },
4136
  { AArch64::H3, 67U },
4137
  { AArch64::H4, 68U },
4138
  { AArch64::H5, 69U },
4139
  { AArch64::H6, 70U },
4140
  { AArch64::H7, 71U },
4141
  { AArch64::H8, 72U },
4142
  { AArch64::H9, 73U },
4143
  { AArch64::H10, 74U },
4144
  { AArch64::H11, 75U },
4145
  { AArch64::H12, 76U },
4146
  { AArch64::H13, 77U },
4147
  { AArch64::H14, 78U },
4148
  { AArch64::H15, 79U },
4149
  { AArch64::H16, 80U },
4150
  { AArch64::H17, 81U },
4151
  { AArch64::H18, 82U },
4152
  { AArch64::H19, 83U },
4153
  { AArch64::H20, 84U },
4154
  { AArch64::H21, 85U },
4155
  { AArch64::H22, 86U },
4156
  { AArch64::H23, 87U },
4157
  { AArch64::H24, 88U },
4158
  { AArch64::H25, 89U },
4159
  { AArch64::H26, 90U },
4160
  { AArch64::H27, 91U },
4161
  { AArch64::H28, 92U },
4162
  { AArch64::H29, 93U },
4163
  { AArch64::H30, 94U },
4164
  { AArch64::H31, 95U },
4165
  { AArch64::P0, 48U },
4166
  { AArch64::P1, 49U },
4167
  { AArch64::P2, 50U },
4168
  { AArch64::P3, 51U },
4169
  { AArch64::P4, 52U },
4170
  { AArch64::P5, 53U },
4171
  { AArch64::P6, 54U },
4172
  { AArch64::P7, 55U },
4173
  { AArch64::P8, 56U },
4174
  { AArch64::P9, 57U },
4175
  { AArch64::P10, 58U },
4176
  { AArch64::P11, 59U },
4177
  { AArch64::P12, 60U },
4178
  { AArch64::P13, 61U },
4179
  { AArch64::P14, 62U },
4180
  { AArch64::P15, 63U },
4181
  { AArch64::Q0, 64U },
4182
  { AArch64::Q1, 65U },
4183
  { AArch64::Q2, 66U },
4184
  { AArch64::Q3, 67U },
4185
  { AArch64::Q4, 68U },
4186
  { AArch64::Q5, 69U },
4187
  { AArch64::Q6, 70U },
4188
  { AArch64::Q7, 71U },
4189
  { AArch64::Q8, 72U },
4190
  { AArch64::Q9, 73U },
4191
  { AArch64::Q10, 74U },
4192
  { AArch64::Q11, 75U },
4193
  { AArch64::Q12, 76U },
4194
  { AArch64::Q13, 77U },
4195
  { AArch64::Q14, 78U },
4196
  { AArch64::Q15, 79U },
4197
  { AArch64::Q16, 80U },
4198
  { AArch64::Q17, 81U },
4199
  { AArch64::Q18, 82U },
4200
  { AArch64::Q19, 83U },
4201
  { AArch64::Q20, 84U },
4202
  { AArch64::Q21, 85U },
4203
  { AArch64::Q22, 86U },
4204
  { AArch64::Q23, 87U },
4205
  { AArch64::Q24, 88U },
4206
  { AArch64::Q25, 89U },
4207
  { AArch64::Q26, 90U },
4208
  { AArch64::Q27, 91U },
4209
  { AArch64::Q28, 92U },
4210
  { AArch64::Q29, 93U },
4211
  { AArch64::Q30, 94U },
4212
  { AArch64::Q31, 95U },
4213
  { AArch64::S0, 64U },
4214
  { AArch64::S1, 65U },
4215
  { AArch64::S2, 66U },
4216
  { AArch64::S3, 67U },
4217
  { AArch64::S4, 68U },
4218
  { AArch64::S5, 69U },
4219
  { AArch64::S6, 70U },
4220
  { AArch64::S7, 71U },
4221
  { AArch64::S8, 72U },
4222
  { AArch64::S9, 73U },
4223
  { AArch64::S10, 74U },
4224
  { AArch64::S11, 75U },
4225
  { AArch64::S12, 76U },
4226
  { AArch64::S13, 77U },
4227
  { AArch64::S14, 78U },
4228
  { AArch64::S15, 79U },
4229
  { AArch64::S16, 80U },
4230
  { AArch64::S17, 81U },
4231
  { AArch64::S18, 82U },
4232
  { AArch64::S19, 83U },
4233
  { AArch64::S20, 84U },
4234
  { AArch64::S21, 85U },
4235
  { AArch64::S22, 86U },
4236
  { AArch64::S23, 87U },
4237
  { AArch64::S24, 88U },
4238
  { AArch64::S25, 89U },
4239
  { AArch64::S26, 90U },
4240
  { AArch64::S27, 91U },
4241
  { AArch64::S28, 92U },
4242
  { AArch64::S29, 93U },
4243
  { AArch64::S30, 94U },
4244
  { AArch64::S31, 95U },
4245
  { AArch64::W0, 0U },
4246
  { AArch64::W1, 1U },
4247
  { AArch64::W2, 2U },
4248
  { AArch64::W3, 3U },
4249
  { AArch64::W4, 4U },
4250
  { AArch64::W5, 5U },
4251
  { AArch64::W6, 6U },
4252
  { AArch64::W7, 7U },
4253
  { AArch64::W8, 8U },
4254
  { AArch64::W9, 9U },
4255
  { AArch64::W10, 10U },
4256
  { AArch64::W11, 11U },
4257
  { AArch64::W12, 12U },
4258
  { AArch64::W13, 13U },
4259
  { AArch64::W14, 14U },
4260
  { AArch64::W15, 15U },
4261
  { AArch64::W16, 16U },
4262
  { AArch64::W17, 17U },
4263
  { AArch64::W18, 18U },
4264
  { AArch64::W19, 19U },
4265
  { AArch64::W20, 20U },
4266
  { AArch64::W21, 21U },
4267
  { AArch64::W22, 22U },
4268
  { AArch64::W23, 23U },
4269
  { AArch64::W24, 24U },
4270
  { AArch64::W25, 25U },
4271
  { AArch64::W26, 26U },
4272
  { AArch64::W27, 27U },
4273
  { AArch64::W28, 28U },
4274
  { AArch64::W29, 29U },
4275
  { AArch64::W30, 30U },
4276
  { AArch64::X0, 0U },
4277
  { AArch64::X1, 1U },
4278
  { AArch64::X2, 2U },
4279
  { AArch64::X3, 3U },
4280
  { AArch64::X4, 4U },
4281
  { AArch64::X5, 5U },
4282
  { AArch64::X6, 6U },
4283
  { AArch64::X7, 7U },
4284
  { AArch64::X8, 8U },
4285
  { AArch64::X9, 9U },
4286
  { AArch64::X10, 10U },
4287
  { AArch64::X11, 11U },
4288
  { AArch64::X12, 12U },
4289
  { AArch64::X13, 13U },
4290
  { AArch64::X14, 14U },
4291
  { AArch64::X15, 15U },
4292
  { AArch64::X16, 16U },
4293
  { AArch64::X17, 17U },
4294
  { AArch64::X18, 18U },
4295
  { AArch64::X19, 19U },
4296
  { AArch64::X20, 20U },
4297
  { AArch64::X21, 21U },
4298
  { AArch64::X22, 22U },
4299
  { AArch64::X23, 23U },
4300
  { AArch64::X24, 24U },
4301
  { AArch64::X25, 25U },
4302
  { AArch64::X26, 26U },
4303
  { AArch64::X27, 27U },
4304
  { AArch64::X28, 28U },
4305
  { AArch64::Z0, 96U },
4306
  { AArch64::Z1, 97U },
4307
  { AArch64::Z2, 98U },
4308
  { AArch64::Z3, 99U },
4309
  { AArch64::Z4, 100U },
4310
  { AArch64::Z5, 101U },
4311
  { AArch64::Z6, 102U },
4312
  { AArch64::Z7, 103U },
4313
  { AArch64::Z8, 104U },
4314
  { AArch64::Z9, 105U },
4315
  { AArch64::Z10, 106U },
4316
  { AArch64::Z11, 107U },
4317
  { AArch64::Z12, 108U },
4318
  { AArch64::Z13, 109U },
4319
  { AArch64::Z14, 110U },
4320
  { AArch64::Z15, 111U },
4321
  { AArch64::Z16, 112U },
4322
  { AArch64::Z17, 113U },
4323
  { AArch64::Z18, 114U },
4324
  { AArch64::Z19, 115U },
4325
  { AArch64::Z20, 116U },
4326
  { AArch64::Z21, 117U },
4327
  { AArch64::Z22, 118U },
4328
  { AArch64::Z23, 119U },
4329
  { AArch64::Z24, 120U },
4330
  { AArch64::Z25, 121U },
4331
  { AArch64::Z26, 122U },
4332
  { AArch64::Z27, 123U },
4333
  { AArch64::Z28, 124U },
4334
  { AArch64::Z29, 125U },
4335
  { AArch64::Z30, 126U },
4336
  { AArch64::Z31, 127U },
4337
};
4338
extern const unsigned AArch64EHFlavour0L2DwarfSize = array_lengthof(AArch64EHFlavour0L2Dwarf);
4339
4340
extern const uint16_t AArch64RegEncodingTable[] = {
4341
  0,
4342
  0,
4343
  29,
4344
  30,
4345
  0,
4346
  31,
4347
  31,
4348
  31,
4349
  31,
4350
  0,
4351
  1,
4352
  2,
4353
  3,
4354
  4,
4355
  5,
4356
  6,
4357
  7,
4358
  8,
4359
  9,
4360
  10,
4361
  11,
4362
  12,
4363
  13,
4364
  14,
4365
  15,
4366
  16,
4367
  17,
4368
  18,
4369
  19,
4370
  20,
4371
  21,
4372
  22,
4373
  23,
4374
  24,
4375
  25,
4376
  26,
4377
  27,
4378
  28,
4379
  29,
4380
  30,
4381
  31,
4382
  0,
4383
  1,
4384
  2,
4385
  3,
4386
  4,
4387
  5,
4388
  6,
4389
  7,
4390
  8,
4391
  9,
4392
  10,
4393
  11,
4394
  12,
4395
  13,
4396
  14,
4397
  15,
4398
  16,
4399
  17,
4400
  18,
4401
  19,
4402
  20,
4403
  21,
4404
  22,
4405
  23,
4406
  24,
4407
  25,
4408
  26,
4409
  27,
4410
  28,
4411
  29,
4412
  30,
4413
  31,
4414
  0,
4415
  1,
4416
  2,
4417
  3,
4418
  4,
4419
  5,
4420
  6,
4421
  7,
4422
  8,
4423
  9,
4424
  10,
4425
  11,
4426
  12,
4427
  13,
4428
  14,
4429
  15,
4430
  16,
4431
  17,
4432
  18,
4433
  19,
4434
  20,
4435
  21,
4436
  22,
4437
  23,
4438
  24,
4439
  25,
4440
  26,
4441
  27,
4442
  28,
4443
  29,
4444
  30,
4445
  31,
4446
  0,
4447
  1,
4448
  2,
4449
  3,
4450
  4,
4451
  5,
4452
  6,
4453
  7,
4454
  8,
4455
  9,
4456
  10,
4457
  11,
4458
  12,
4459
  13,
4460
  14,
4461
  15,
4462
  0,
4463
  1,
4464
  2,
4465
  3,
4466
  4,
4467
  5,
4468
  6,
4469
  7,
4470
  8,
4471
  9,
4472
  10,
4473
  11,
4474
  12,
4475
  13,
4476
  14,
4477
  15,
4478
  16,
4479
  17,
4480
  18,
4481
  19,
4482
  20,
4483
  21,
4484
  22,
4485
  23,
4486
  24,
4487
  25,
4488
  26,
4489
  27,
4490
  28,
4491
  29,
4492
  30,
4493
  31,
4494
  0,
4495
  1,
4496
  2,
4497
  3,
4498
  4,
4499
  5,
4500
  6,
4501
  7,
4502
  8,
4503
  9,
4504
  10,
4505
  11,
4506
  12,
4507
  13,
4508
  14,
4509
  15,
4510
  16,
4511
  17,
4512
  18,
4513
  19,
4514
  20,
4515
  21,
4516
  22,
4517
  23,
4518
  24,
4519
  25,
4520
  26,
4521
  27,
4522
  28,
4523
  29,
4524
  30,
4525
  31,
4526
  0,
4527
  1,
4528
  2,
4529
  3,
4530
  4,
4531
  5,
4532
  6,
4533
  7,
4534
  8,
4535
  9,
4536
  10,
4537
  11,
4538
  12,
4539
  13,
4540
  14,
4541
  15,
4542
  16,
4543
  17,
4544
  18,
4545
  19,
4546
  20,
4547
  21,
4548
  22,
4549
  23,
4550
  24,
4551
  25,
4552
  26,
4553
  27,
4554
  28,
4555
  29,
4556
  30,
4557
  0,
4558
  1,
4559
  2,
4560
  3,
4561
  4,
4562
  5,
4563
  6,
4564
  7,
4565
  8,
4566
  9,
4567
  10,
4568
  11,
4569
  12,
4570
  13,
4571
  14,
4572
  15,
4573
  16,
4574
  17,
4575
  18,
4576
  19,
4577
  20,
4578
  21,
4579
  22,
4580
  23,
4581
  24,
4582
  25,
4583
  26,
4584
  27,
4585
  28,
4586
  0,
4587
  1,
4588
  2,
4589
  3,
4590
  4,
4591
  5,
4592
  6,
4593
  7,
4594
  8,
4595
  9,
4596
  10,
4597
  11,
4598
  12,
4599
  13,
4600
  14,
4601
  15,
4602
  16,
4603
  17,
4604
  18,
4605
  19,
4606
  20,
4607
  21,
4608
  22,
4609
  23,
4610
  24,
4611
  25,
4612
  26,
4613
  27,
4614
  28,
4615
  29,
4616
  30,
4617
  31,
4618
  0,
4619
  1,
4620
  2,
4621
  3,
4622
  4,
4623
  5,
4624
  6,
4625
  7,
4626
  8,
4627
  9,
4628
  10,
4629
  11,
4630
  12,
4631
  13,
4632
  14,
4633
  15,
4634
  16,
4635
  17,
4636
  18,
4637
  19,
4638
  20,
4639
  21,
4640
  22,
4641
  23,
4642
  24,
4643
  25,
4644
  26,
4645
  27,
4646
  28,
4647
  29,
4648
  30,
4649
  31,
4650
  0,
4651
  1,
4652
  2,
4653
  3,
4654
  4,
4655
  5,
4656
  6,
4657
  7,
4658
  8,
4659
  9,
4660
  10,
4661
  11,
4662
  12,
4663
  13,
4664
  14,
4665
  15,
4666
  16,
4667
  17,
4668
  18,
4669
  19,
4670
  20,
4671
  21,
4672
  22,
4673
  23,
4674
  24,
4675
  25,
4676
  26,
4677
  27,
4678
  28,
4679
  29,
4680
  30,
4681
  31,
4682
  0,
4683
  1,
4684
  2,
4685
  3,
4686
  4,
4687
  5,
4688
  6,
4689
  7,
4690
  8,
4691
  9,
4692
  10,
4693
  11,
4694
  12,
4695
  13,
4696
  14,
4697
  15,
4698
  16,
4699
  17,
4700
  18,
4701
  19,
4702
  20,
4703
  21,
4704
  22,
4705
  23,
4706
  24,
4707
  25,
4708
  26,
4709
  27,
4710
  28,
4711
  29,
4712
  30,
4713
  31,
4714
  0,
4715
  1,
4716
  2,
4717
  3,
4718
  4,
4719
  5,
4720
  6,
4721
  7,
4722
  8,
4723
  9,
4724
  10,
4725
  11,
4726
  12,
4727
  13,
4728
  14,
4729
  15,
4730
  16,
4731
  17,
4732
  18,
4733
  19,
4734
  20,
4735
  21,
4736
  22,
4737
  23,
4738
  24,
4739
  25,
4740
  26,
4741
  27,
4742
  28,
4743
  29,
4744
  30,
4745
  31,
4746
  0,
4747
  1,
4748
  2,
4749
  3,
4750
  4,
4751
  5,
4752
  6,
4753
  7,
4754
  8,
4755
  9,
4756
  10,
4757
  11,
4758
  12,
4759
  13,
4760
  14,
4761
  15,
4762
  16,
4763
  17,
4764
  18,
4765
  19,
4766
  20,
4767
  21,
4768
  22,
4769
  23,
4770
  24,
4771
  25,
4772
  26,
4773
  27,
4774
  28,
4775
  29,
4776
  30,
4777
  31,
4778
  0,
4779
  1,
4780
  2,
4781
  3,
4782
  4,
4783
  5,
4784
  6,
4785
  7,
4786
  8,
4787
  9,
4788
  10,
4789
  11,
4790
  12,
4791
  13,
4792
  14,
4793
  15,
4794
  16,
4795
  17,
4796
  18,
4797
  19,
4798
  20,
4799
  21,
4800
  22,
4801
  23,
4802
  24,
4803
  25,
4804
  26,
4805
  27,
4806
  28,
4807
  29,
4808
  30,
4809
  31,
4810
  0,
4811
  1,
4812
  2,
4813
  3,
4814
  4,
4815
  5,
4816
  6,
4817
  7,
4818
  8,
4819
  9,
4820
  10,
4821
  11,
4822
  12,
4823
  13,
4824
  14,
4825
  15,
4826
  16,
4827
  17,
4828
  18,
4829
  19,
4830
  20,
4831
  21,
4832
  22,
4833
  23,
4834
  24,
4835
  25,
4836
  26,
4837
  27,
4838
  28,
4839
  29,
4840
  30,
4841
  31,
4842
  30,
4843
  0,
4844
  2,
4845
  4,
4846
  6,
4847
  8,
4848
  10,
4849
  12,
4850
  14,
4851
  16,
4852
  18,
4853
  20,
4854
  22,
4855
  24,
4856
  26,
4857
  28,
4858
  30,
4859
  28,
4860
  0,
4861
  2,
4862
  4,
4863
  6,
4864
  8,
4865
  10,
4866
  12,
4867
  14,
4868
  16,
4869
  18,
4870
  20,
4871
  22,
4872
  24,
4873
  26,
4874
  0,
4875
  1,
4876
  2,
4877
  3,
4878
  4,
4879
  5,
4880
  6,
4881
  7,
4882
  8,
4883
  9,
4884
  10,
4885
  11,
4886
  12,
4887
  13,
4888
  14,
4889
  15,
4890
  16,
4891
  17,
4892
  18,
4893
  19,
4894
  20,
4895
  21,
4896
  22,
4897
  23,
4898
  24,
4899
  25,
4900
  26,
4901
  27,
4902
  28,
4903
  29,
4904
  30,
4905
  31,
4906
  0,
4907
  1,
4908
  2,
4909
  3,
4910
  4,
4911
  5,
4912
  6,
4913
  7,
4914
  8,
4915
  9,
4916
  10,
4917
  11,
4918
  12,
4919
  13,
4920
  14,
4921
  15,
4922
  16,
4923
  17,
4924
  18,
4925
  19,
4926
  20,
4927
  21,
4928
  22,
4929
  23,
4930
  24,
4931
  25,
4932
  26,
4933
  27,
4934
  28,
4935
  29,
4936
  30,
4937
  31,
4938
  0,
4939
  1,
4940
  2,
4941
  3,
4942
  4,
4943
  5,
4944
  6,
4945
  7,
4946
  8,
4947
  9,
4948
  10,
4949
  11,
4950
  12,
4951
  13,
4952
  14,
4953
  15,
4954
  16,
4955
  17,
4956
  18,
4957
  19,
4958
  20,
4959
  21,
4960
  22,
4961
  23,
4962
  24,
4963
  25,
4964
  26,
4965
  27,
4966
  28,
4967
  29,
4968
  30,
4969
  31,
4970
};
4971
12.6k
static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4972
12.6k
  RI->InitMCRegisterInfo(AArch64RegDesc, 629, RA, PC, AArch64MCRegisterClasses, 108, AArch64RegUnitRoots, 115, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 100,
4973
12.6k
AArch64SubRegIdxRanges, AArch64RegEncodingTable);
4974
12.6k
4975
12.6k
  switch (DwarfFlavour) {
4976
12.6k
  default:
4977
0
    llvm_unreachable("Unknown DWARF flavour");
4978
12.6k
  case 0:
4979
12.6k
    RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
4980
12.6k
    break;
4981
12.6k
  }
4982
12.6k
  switch (EHFlavour) {
4983
12.6k
  default:
4984
0
    llvm_unreachable("Unknown DWARF flavour");
4985
12.6k
  case 0:
4986
12.6k
    RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
4987
12.6k
    break;
4988
12.6k
  }
4989
12.6k
  switch (DwarfFlavour) {
4990
12.6k
  default:
4991
0
    llvm_unreachable("Unknown DWARF flavour");
4992
12.6k
  case 0:
4993
12.6k
    RI->mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
4994
12.6k
    break;
4995
12.6k
  }
4996
12.6k
  switch (EHFlavour) {
4997
12.6k
  default:
4998
0
    llvm_unreachable("Unknown DWARF flavour");
4999
12.6k
  case 0:
5000
12.6k
    RI->mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
5001
12.6k
    break;
5002
12.6k
  }
5003
12.6k
}
5004
5005
} // end namespace llvm
5006
5007
#endif // GET_REGINFO_MC_DESC
5008
5009
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5010
|*                                                                            *|
5011
|* Register Information Header Fragment                                       *|
5012
|*                                                                            *|
5013
|* Automatically generated file, do not edit!                                 *|
5014
|*                                                                            *|
5015
\*===----------------------------------------------------------------------===*/
5016
5017
5018
#ifdef GET_REGINFO_HEADER
5019
#undef GET_REGINFO_HEADER
5020
5021
#include "llvm/CodeGen/TargetRegisterInfo.h"
5022
5023
namespace llvm {
5024
5025
class AArch64FrameLowering;
5026
5027
struct AArch64GenRegisterInfo : public TargetRegisterInfo {
5028
  explicit AArch64GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
5029
      unsigned PC = 0, unsigned HwMode = 0);
5030
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
5031
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5032
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5033
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
5034
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
5035
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
5036
  unsigned getNumRegPressureSets() const override;
5037
  const char *getRegPressureSetName(unsigned Idx) const override;
5038
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
5039
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
5040
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
5041
  ArrayRef<const char *> getRegMaskNames() const override;
5042
  ArrayRef<const uint32_t *> getRegMasks() const override;
5043
  /// Devirtualized TargetFrameLowering.
5044
  static const AArch64FrameLowering *getFrameLowering(
5045
      const MachineFunction &MF);
5046
};
5047
5048
namespace AArch64 { // Register classes
5049
  extern const TargetRegisterClass FPR8RegClass;
5050
  extern const TargetRegisterClass FPR16RegClass;
5051
  extern const TargetRegisterClass PPRRegClass;
5052
  extern const TargetRegisterClass PPR_3bRegClass;
5053
  extern const TargetRegisterClass GPR32allRegClass;
5054
  extern const TargetRegisterClass FPR32RegClass;
5055
  extern const TargetRegisterClass GPR32RegClass;
5056
  extern const TargetRegisterClass GPR32spRegClass;
5057
  extern const TargetRegisterClass GPR32commonRegClass;
5058
  extern const TargetRegisterClass GPR32argRegClass;
5059
  extern const TargetRegisterClass CCRRegClass;
5060
  extern const TargetRegisterClass GPR32sponlyRegClass;
5061
  extern const TargetRegisterClass WSeqPairsClassRegClass;
5062
  extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
5063
  extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32argRegClass;
5064
  extern const TargetRegisterClass GPR64allRegClass;
5065
  extern const TargetRegisterClass FPR64RegClass;
5066
  extern const TargetRegisterClass GPR64RegClass;
5067
  extern const TargetRegisterClass GPR64spRegClass;
5068
  extern const TargetRegisterClass GPR64commonRegClass;
5069
  extern const TargetRegisterClass GPR64noipRegClass;
5070
  extern const TargetRegisterClass GPR64common_and_GPR64noipRegClass;
5071
  extern const TargetRegisterClass tcGPR64RegClass;
5072
  extern const TargetRegisterClass GPR64noip_and_tcGPR64RegClass;
5073
  extern const TargetRegisterClass GPR64argRegClass;
5074
  extern const TargetRegisterClass rtcGPR64RegClass;
5075
  extern const TargetRegisterClass GPR64sponlyRegClass;
5076
  extern const TargetRegisterClass DDRegClass;
5077
  extern const TargetRegisterClass XSeqPairsClassRegClass;
5078
  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
5079
  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noipRegClass;
5080
  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noipRegClass;
5081
  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass;
5082
  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass;
5083
  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
5084
  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClass;
5085
  extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32argRegClass;
5086
  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_rtcGPR64RegClass;
5087
  extern const TargetRegisterClass FPR128RegClass;
5088
  extern const TargetRegisterClass ZPRRegClass;
5089
  extern const TargetRegisterClass FPR128_loRegClass;
5090
  extern const TargetRegisterClass ZPR_4bRegClass;
5091
  extern const TargetRegisterClass ZPR_3bRegClass;
5092
  extern const TargetRegisterClass DDDRegClass;
5093
  extern const TargetRegisterClass DDDDRegClass;
5094
  extern const TargetRegisterClass QQRegClass;
5095
  extern const TargetRegisterClass ZPR2RegClass;
5096
  extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass;
5097
  extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass;