Coverage Report

Created: 2018-12-14 11:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AArch64/AArch64GenRegisterInfo.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass AArch64MCRegisterClasses[];
17
18
namespace AArch64 {
19
enum {
20
  NoRegister,
21
  FFR = 1,
22
  FP = 2,
23
  LR = 3,
24
  NZCV = 4,
25
  SP = 5,
26
  WSP = 6,
27
  WZR = 7,
28
  XZR = 8,
29
  B0 = 9,
30
  B1 = 10,
31
  B2 = 11,
32
  B3 = 12,
33
  B4 = 13,
34
  B5 = 14,
35
  B6 = 15,
36
  B7 = 16,
37
  B8 = 17,
38
  B9 = 18,
39
  B10 = 19,
40
  B11 = 20,
41
  B12 = 21,
42
  B13 = 22,
43
  B14 = 23,
44
  B15 = 24,
45
  B16 = 25,
46
  B17 = 26,
47
  B18 = 27,
48
  B19 = 28,
49
  B20 = 29,
50
  B21 = 30,
51
  B22 = 31,
52
  B23 = 32,
53
  B24 = 33,
54
  B25 = 34,
55
  B26 = 35,
56
  B27 = 36,
57
  B28 = 37,
58
  B29 = 38,
59
  B30 = 39,
60
  B31 = 40,
61
  D0 = 41,
62
  D1 = 42,
63
  D2 = 43,
64
  D3 = 44,
65
  D4 = 45,
66
  D5 = 46,
67
  D6 = 47,
68
  D7 = 48,
69
  D8 = 49,
70
  D9 = 50,
71
  D10 = 51,
72
  D11 = 52,
73
  D12 = 53,
74
  D13 = 54,
75
  D14 = 55,
76
  D15 = 56,
77
  D16 = 57,
78
  D17 = 58,
79
  D18 = 59,
80
  D19 = 60,
81
  D20 = 61,
82
  D21 = 62,
83
  D22 = 63,
84
  D23 = 64,
85
  D24 = 65,
86
  D25 = 66,
87
  D26 = 67,
88
  D27 = 68,
89
  D28 = 69,
90
  D29 = 70,
91
  D30 = 71,
92
  D31 = 72,
93
  H0 = 73,
94
  H1 = 74,
95
  H2 = 75,
96
  H3 = 76,
97
  H4 = 77,
98
  H5 = 78,
99
  H6 = 79,
100
  H7 = 80,
101
  H8 = 81,
102
  H9 = 82,
103
  H10 = 83,
104
  H11 = 84,
105
  H12 = 85,
106
  H13 = 86,
107
  H14 = 87,
108
  H15 = 88,
109
  H16 = 89,
110
  H17 = 90,
111
  H18 = 91,
112
  H19 = 92,
113
  H20 = 93,
114
  H21 = 94,
115
  H22 = 95,
116
  H23 = 96,
117
  H24 = 97,
118
  H25 = 98,
119
  H26 = 99,
120
  H27 = 100,
121
  H28 = 101,
122
  H29 = 102,
123
  H30 = 103,
124
  H31 = 104,
125
  P0 = 105,
126
  P1 = 106,
127
  P2 = 107,
128
  P3 = 108,
129
  P4 = 109,
130
  P5 = 110,
131
  P6 = 111,
132
  P7 = 112,
133
  P8 = 113,
134
  P9 = 114,
135
  P10 = 115,
136
  P11 = 116,
137
  P12 = 117,
138
  P13 = 118,
139
  P14 = 119,
140
  P15 = 120,
141
  Q0 = 121,
142
  Q1 = 122,
143
  Q2 = 123,
144
  Q3 = 124,
145
  Q4 = 125,
146
  Q5 = 126,
147
  Q6 = 127,
148
  Q7 = 128,
149
  Q8 = 129,
150
  Q9 = 130,
151
  Q10 = 131,
152
  Q11 = 132,
153
  Q12 = 133,
154
  Q13 = 134,
155
  Q14 = 135,
156
  Q15 = 136,
157
  Q16 = 137,
158
  Q17 = 138,
159
  Q18 = 139,
160
  Q19 = 140,
161
  Q20 = 141,
162
  Q21 = 142,
163
  Q22 = 143,
164
  Q23 = 144,
165
  Q24 = 145,
166
  Q25 = 146,
167
  Q26 = 147,
168
  Q27 = 148,
169
  Q28 = 149,
170
  Q29 = 150,
171
  Q30 = 151,
172
  Q31 = 152,
173
  S0 = 153,
174
  S1 = 154,
175
  S2 = 155,
176
  S3 = 156,
177
  S4 = 157,
178
  S5 = 158,
179
  S6 = 159,
180
  S7 = 160,
181
  S8 = 161,
182
  S9 = 162,
183
  S10 = 163,
184
  S11 = 164,
185
  S12 = 165,
186
  S13 = 166,
187
  S14 = 167,
188
  S15 = 168,
189
  S16 = 169,
190
  S17 = 170,
191
  S18 = 171,
192
  S19 = 172,
193
  S20 = 173,
194
  S21 = 174,
195
  S22 = 175,
196
  S23 = 176,
197
  S24 = 177,
198
  S25 = 178,
199
  S26 = 179,
200
  S27 = 180,
201
  S28 = 181,
202
  S29 = 182,
203
  S30 = 183,
204
  S31 = 184,
205
  W0 = 185,
206
  W1 = 186,
207
  W2 = 187,
208
  W3 = 188,
209
  W4 = 189,
210
  W5 = 190,
211
  W6 = 191,
212
  W7 = 192,
213
  W8 = 193,
214
  W9 = 194,
215
  W10 = 195,
216
  W11 = 196,
217
  W12 = 197,
218
  W13 = 198,
219
  W14 = 199,
220
  W15 = 200,
221
  W16 = 201,
222
  W17 = 202,
223
  W18 = 203,
224
  W19 = 204,
225
  W20 = 205,
226
  W21 = 206,
227
  W22 = 207,
228
  W23 = 208,
229
  W24 = 209,
230
  W25 = 210,
231
  W26 = 211,
232
  W27 = 212,
233
  W28 = 213,
234
  W29 = 214,
235
  W30 = 215,
236
  X0 = 216,
237
  X1 = 217,
238
  X2 = 218,
239
  X3 = 219,
240
  X4 = 220,
241
  X5 = 221,
242
  X6 = 222,
243
  X7 = 223,
244
  X8 = 224,
245
  X9 = 225,
246
  X10 = 226,
247
  X11 = 227,
248
  X12 = 228,
249
  X13 = 229,
250
  X14 = 230,
251
  X15 = 231,
252
  X16 = 232,
253
  X17 = 233,
254
  X18 = 234,
255
  X19 = 235,
256
  X20 = 236,
257
  X21 = 237,
258
  X22 = 238,
259
  X23 = 239,
260
  X24 = 240,
261
  X25 = 241,
262
  X26 = 242,
263
  X27 = 243,
264
  X28 = 244,
265
  Z0 = 245,
266
  Z1 = 246,
267
  Z2 = 247,
268
  Z3 = 248,
269
  Z4 = 249,
270
  Z5 = 250,
271
  Z6 = 251,
272
  Z7 = 252,
273
  Z8 = 253,
274
  Z9 = 254,
275
  Z10 = 255,
276
  Z11 = 256,
277
  Z12 = 257,
278
  Z13 = 258,
279
  Z14 = 259,
280
  Z15 = 260,
281
  Z16 = 261,
282
  Z17 = 262,
283
  Z18 = 263,
284
  Z19 = 264,
285
  Z20 = 265,
286
  Z21 = 266,
287
  Z22 = 267,
288
  Z23 = 268,
289
  Z24 = 269,
290
  Z25 = 270,
291
  Z26 = 271,
292
  Z27 = 272,
293
  Z28 = 273,
294
  Z29 = 274,
295
  Z30 = 275,
296
  Z31 = 276,
297
  Z0_HI = 277,
298
  Z1_HI = 278,
299
  Z2_HI = 279,
300
  Z3_HI = 280,
301
  Z4_HI = 281,
302
  Z5_HI = 282,
303
  Z6_HI = 283,
304
  Z7_HI = 284,
305
  Z8_HI = 285,
306
  Z9_HI = 286,
307
  Z10_HI = 287,
308
  Z11_HI = 288,
309
  Z12_HI = 289,
310
  Z13_HI = 290,
311
  Z14_HI = 291,
312
  Z15_HI = 292,
313
  Z16_HI = 293,
314
  Z17_HI = 294,
315
  Z18_HI = 295,
316
  Z19_HI = 296,
317
  Z20_HI = 297,
318
  Z21_HI = 298,
319
  Z22_HI = 299,
320
  Z23_HI = 300,
321
  Z24_HI = 301,
322
  Z25_HI = 302,
323
  Z26_HI = 303,
324
  Z27_HI = 304,
325
  Z28_HI = 305,
326
  Z29_HI = 306,
327
  Z30_HI = 307,
328
  Z31_HI = 308,
329
  D0_D1 = 309,
330
  D1_D2 = 310,
331
  D2_D3 = 311,
332
  D3_D4 = 312,
333
  D4_D5 = 313,
334
  D5_D6 = 314,
335
  D6_D7 = 315,
336
  D7_D8 = 316,
337
  D8_D9 = 317,
338
  D9_D10 = 318,
339
  D10_D11 = 319,
340
  D11_D12 = 320,
341
  D12_D13 = 321,
342
  D13_D14 = 322,
343
  D14_D15 = 323,
344
  D15_D16 = 324,
345
  D16_D17 = 325,
346
  D17_D18 = 326,
347
  D18_D19 = 327,
348
  D19_D20 = 328,
349
  D20_D21 = 329,
350
  D21_D22 = 330,
351
  D22_D23 = 331,
352
  D23_D24 = 332,
353
  D24_D25 = 333,
354
  D25_D26 = 334,
355
  D26_D27 = 335,
356
  D27_D28 = 336,
357
  D28_D29 = 337,
358
  D29_D30 = 338,
359
  D30_D31 = 339,
360
  D31_D0 = 340,
361
  D0_D1_D2_D3 = 341,
362
  D1_D2_D3_D4 = 342,
363
  D2_D3_D4_D5 = 343,
364
  D3_D4_D5_D6 = 344,
365
  D4_D5_D6_D7 = 345,
366
  D5_D6_D7_D8 = 346,
367
  D6_D7_D8_D9 = 347,
368
  D7_D8_D9_D10 = 348,
369
  D8_D9_D10_D11 = 349,
370
  D9_D10_D11_D12 = 350,
371
  D10_D11_D12_D13 = 351,
372
  D11_D12_D13_D14 = 352,
373
  D12_D13_D14_D15 = 353,
374
  D13_D14_D15_D16 = 354,
375
  D14_D15_D16_D17 = 355,
376
  D15_D16_D17_D18 = 356,
377
  D16_D17_D18_D19 = 357,
378
  D17_D18_D19_D20 = 358,
379
  D18_D19_D20_D21 = 359,
380
  D19_D20_D21_D22 = 360,
381
  D20_D21_D22_D23 = 361,
382
  D21_D22_D23_D24 = 362,
383
  D22_D23_D24_D25 = 363,
384
  D23_D24_D25_D26 = 364,
385
  D24_D25_D26_D27 = 365,
386
  D25_D26_D27_D28 = 366,
387
  D26_D27_D28_D29 = 367,
388
  D27_D28_D29_D30 = 368,
389
  D28_D29_D30_D31 = 369,
390
  D29_D30_D31_D0 = 370,
391
  D30_D31_D0_D1 = 371,
392
  D31_D0_D1_D2 = 372,
393
  D0_D1_D2 = 373,
394
  D1_D2_D3 = 374,
395
  D2_D3_D4 = 375,
396
  D3_D4_D5 = 376,
397
  D4_D5_D6 = 377,
398
  D5_D6_D7 = 378,
399
  D6_D7_D8 = 379,
400
  D7_D8_D9 = 380,
401
  D8_D9_D10 = 381,
402
  D9_D10_D11 = 382,
403
  D10_D11_D12 = 383,
404
  D11_D12_D13 = 384,
405
  D12_D13_D14 = 385,
406
  D13_D14_D15 = 386,
407
  D14_D15_D16 = 387,
408
  D15_D16_D17 = 388,
409
  D16_D17_D18 = 389,
410
  D17_D18_D19 = 390,
411
  D18_D19_D20 = 391,
412
  D19_D20_D21 = 392,
413
  D20_D21_D22 = 393,
414
  D21_D22_D23 = 394,
415
  D22_D23_D24 = 395,
416
  D23_D24_D25 = 396,
417
  D24_D25_D26 = 397,
418
  D25_D26_D27 = 398,
419
  D26_D27_D28 = 399,
420
  D27_D28_D29 = 400,
421
  D28_D29_D30 = 401,
422
  D29_D30_D31 = 402,
423
  D30_D31_D0 = 403,
424
  D31_D0_D1 = 404,
425
  Q0_Q1 = 405,
426
  Q1_Q2 = 406,
427
  Q2_Q3 = 407,
428
  Q3_Q4 = 408,
429
  Q4_Q5 = 409,
430
  Q5_Q6 = 410,
431
  Q6_Q7 = 411,
432
  Q7_Q8 = 412,
433
  Q8_Q9 = 413,
434
  Q9_Q10 = 414,
435
  Q10_Q11 = 415,
436
  Q11_Q12 = 416,
437
  Q12_Q13 = 417,
438
  Q13_Q14 = 418,
439
  Q14_Q15 = 419,
440
  Q15_Q16 = 420,
441
  Q16_Q17 = 421,
442
  Q17_Q18 = 422,
443
  Q18_Q19 = 423,
444
  Q19_Q20 = 424,
445
  Q20_Q21 = 425,
446
  Q21_Q22 = 426,
447
  Q22_Q23 = 427,
448
  Q23_Q24 = 428,
449
  Q24_Q25 = 429,
450
  Q25_Q26 = 430,
451
  Q26_Q27 = 431,
452
  Q27_Q28 = 432,
453
  Q28_Q29 = 433,
454
  Q29_Q30 = 434,
455
  Q30_Q31 = 435,
456
  Q31_Q0 = 436,
457
  Q0_Q1_Q2_Q3 = 437,
458
  Q1_Q2_Q3_Q4 = 438,
459
  Q2_Q3_Q4_Q5 = 439,
460
  Q3_Q4_Q5_Q6 = 440,
461
  Q4_Q5_Q6_Q7 = 441,
462
  Q5_Q6_Q7_Q8 = 442,
463
  Q6_Q7_Q8_Q9 = 443,
464
  Q7_Q8_Q9_Q10 = 444,
465
  Q8_Q9_Q10_Q11 = 445,
466
  Q9_Q10_Q11_Q12 = 446,
467
  Q10_Q11_Q12_Q13 = 447,
468
  Q11_Q12_Q13_Q14 = 448,
469
  Q12_Q13_Q14_Q15 = 449,
470
  Q13_Q14_Q15_Q16 = 450,
471
  Q14_Q15_Q16_Q17 = 451,
472
  Q15_Q16_Q17_Q18 = 452,
473
  Q16_Q17_Q18_Q19 = 453,
474
  Q17_Q18_Q19_Q20 = 454,
475
  Q18_Q19_Q20_Q21 = 455,
476
  Q19_Q20_Q21_Q22 = 456,
477
  Q20_Q21_Q22_Q23 = 457,
478
  Q21_Q22_Q23_Q24 = 458,
479
  Q22_Q23_Q24_Q25 = 459,
480
  Q23_Q24_Q25_Q26 = 460,
481
  Q24_Q25_Q26_Q27 = 461,
482
  Q25_Q26_Q27_Q28 = 462,
483
  Q26_Q27_Q28_Q29 = 463,
484
  Q27_Q28_Q29_Q30 = 464,
485
  Q28_Q29_Q30_Q31 = 465,
486
  Q29_Q30_Q31_Q0 = 466,
487
  Q30_Q31_Q0_Q1 = 467,
488
  Q31_Q0_Q1_Q2 = 468,
489
  Q0_Q1_Q2 = 469,
490
  Q1_Q2_Q3 = 470,
491
  Q2_Q3_Q4 = 471,
492
  Q3_Q4_Q5 = 472,
493
  Q4_Q5_Q6 = 473,
494
  Q5_Q6_Q7 = 474,
495
  Q6_Q7_Q8 = 475,
496
  Q7_Q8_Q9 = 476,
497
  Q8_Q9_Q10 = 477,
498
  Q9_Q10_Q11 = 478,
499
  Q10_Q11_Q12 = 479,
500
  Q11_Q12_Q13 = 480,
501
  Q12_Q13_Q14 = 481,
502
  Q13_Q14_Q15 = 482,
503
  Q14_Q15_Q16 = 483,
504
  Q15_Q16_Q17 = 484,
505
  Q16_Q17_Q18 = 485,
506
  Q17_Q18_Q19 = 486,
507
  Q18_Q19_Q20 = 487,
508
  Q19_Q20_Q21 = 488,
509
  Q20_Q21_Q22 = 489,
510
  Q21_Q22_Q23 = 490,
511
  Q22_Q23_Q24 = 491,
512
  Q23_Q24_Q25 = 492,
513
  Q24_Q25_Q26 = 493,
514
  Q25_Q26_Q27 = 494,
515
  Q26_Q27_Q28 = 495,
516
  Q27_Q28_Q29 = 496,
517
  Q28_Q29_Q30 = 497,
518
  Q29_Q30_Q31 = 498,
519
  Q30_Q31_Q0 = 499,
520
  Q31_Q0_Q1 = 500,
521
  WZR_W0 = 501,
522
  W30_WZR = 502,
523
  W0_W1 = 503,
524
  W1_W2 = 504,
525
  W2_W3 = 505,
526
  W3_W4 = 506,
527
  W4_W5 = 507,
528
  W5_W6 = 508,
529
  W6_W7 = 509,
530
  W7_W8 = 510,
531
  W8_W9 = 511,
532
  W9_W10 = 512,
533
  W10_W11 = 513,
534
  W11_W12 = 514,
535
  W12_W13 = 515,
536
  W13_W14 = 516,
537
  W14_W15 = 517,
538
  W15_W16 = 518,
539
  W16_W17 = 519,
540
  W17_W18 = 520,
541
  W18_W19 = 521,
542
  W19_W20 = 522,
543
  W20_W21 = 523,
544
  W21_W22 = 524,
545
  W22_W23 = 525,
546
  W23_W24 = 526,
547
  W24_W25 = 527,
548
  W25_W26 = 528,
549
  W26_W27 = 529,
550
  W27_W28 = 530,
551
  W28_W29 = 531,
552
  W29_W30 = 532,
553
  FP_LR = 533,
554
  LR_XZR = 534,
555
  XZR_X0 = 535,
556
  X28_FP = 536,
557
  X0_X1 = 537,
558
  X1_X2 = 538,
559
  X2_X3 = 539,
560
  X3_X4 = 540,
561
  X4_X5 = 541,
562
  X5_X6 = 542,
563
  X6_X7 = 543,
564
  X7_X8 = 544,
565
  X8_X9 = 545,
566
  X9_X10 = 546,
567
  X10_X11 = 547,
568
  X11_X12 = 548,
569
  X12_X13 = 549,
570
  X13_X14 = 550,
571
  X14_X15 = 551,
572
  X15_X16 = 552,
573
  X16_X17 = 553,
574
  X17_X18 = 554,
575
  X18_X19 = 555,
576
  X19_X20 = 556,
577
  X20_X21 = 557,
578
  X21_X22 = 558,
579
  X22_X23 = 559,
580
  X23_X24 = 560,
581
  X24_X25 = 561,
582
  X25_X26 = 562,
583
  X26_X27 = 563,
584
  X27_X28 = 564,
585
  Z0_Z1 = 565,
586
  Z1_Z2 = 566,
587
  Z2_Z3 = 567,
588
  Z3_Z4 = 568,
589
  Z4_Z5 = 569,
590
  Z5_Z6 = 570,
591
  Z6_Z7 = 571,
592
  Z7_Z8 = 572,
593
  Z8_Z9 = 573,
594
  Z9_Z10 = 574,
595
  Z10_Z11 = 575,
596
  Z11_Z12 = 576,
597
  Z12_Z13 = 577,
598
  Z13_Z14 = 578,
599
  Z14_Z15 = 579,
600
  Z15_Z16 = 580,
601
  Z16_Z17 = 581,
602
  Z17_Z18 = 582,
603
  Z18_Z19 = 583,
604
  Z19_Z20 = 584,
605
  Z20_Z21 = 585,
606
  Z21_Z22 = 586,
607
  Z22_Z23 = 587,
608
  Z23_Z24 = 588,
609
  Z24_Z25 = 589,
610
  Z25_Z26 = 590,
611
  Z26_Z27 = 591,
612
  Z27_Z28 = 592,
613
  Z28_Z29 = 593,
614
  Z29_Z30 = 594,
615
  Z30_Z31 = 595,
616
  Z31_Z0 = 596,
617
  Z0_Z1_Z2_Z3 = 597,
618
  Z1_Z2_Z3_Z4 = 598,
619
  Z2_Z3_Z4_Z5 = 599,
620
  Z3_Z4_Z5_Z6 = 600,
621
  Z4_Z5_Z6_Z7 = 601,
622
  Z5_Z6_Z7_Z8 = 602,
623
  Z6_Z7_Z8_Z9 = 603,
624
  Z7_Z8_Z9_Z10 = 604,
625
  Z8_Z9_Z10_Z11 = 605,
626
  Z9_Z10_Z11_Z12 = 606,
627
  Z10_Z11_Z12_Z13 = 607,
628
  Z11_Z12_Z13_Z14 = 608,
629
  Z12_Z13_Z14_Z15 = 609,
630
  Z13_Z14_Z15_Z16 = 610,
631
  Z14_Z15_Z16_Z17 = 611,
632
  Z15_Z16_Z17_Z18 = 612,
633
  Z16_Z17_Z18_Z19 = 613,
634
  Z17_Z18_Z19_Z20 = 614,
635
  Z18_Z19_Z20_Z21 = 615,
636
  Z19_Z20_Z21_Z22 = 616,
637
  Z20_Z21_Z22_Z23 = 617,
638
  Z21_Z22_Z23_Z24 = 618,
639
  Z22_Z23_Z24_Z25 = 619,
640
  Z23_Z24_Z25_Z26 = 620,
641
  Z24_Z25_Z26_Z27 = 621,
642
  Z25_Z26_Z27_Z28 = 622,
643
  Z26_Z27_Z28_Z29 = 623,
644
  Z27_Z28_Z29_Z30 = 624,
645
  Z28_Z29_Z30_Z31 = 625,
646
  Z29_Z30_Z31_Z0 = 626,
647
  Z30_Z31_Z0_Z1 = 627,
648
  Z31_Z0_Z1_Z2 = 628,
649
  Z0_Z1_Z2 = 629,
650
  Z1_Z2_Z3 = 630,
651
  Z2_Z3_Z4 = 631,
652
  Z3_Z4_Z5 = 632,
653
  Z4_Z5_Z6 = 633,
654
  Z5_Z6_Z7 = 634,
655
  Z6_Z7_Z8 = 635,
656
  Z7_Z8_Z9 = 636,
657
  Z8_Z9_Z10 = 637,
658
  Z9_Z10_Z11 = 638,
659
  Z10_Z11_Z12 = 639,
660
  Z11_Z12_Z13 = 640,
661
  Z12_Z13_Z14 = 641,
662
  Z13_Z14_Z15 = 642,
663
  Z14_Z15_Z16 = 643,
664
  Z15_Z16_Z17 = 644,
665
  Z16_Z17_Z18 = 645,
666
  Z17_Z18_Z19 = 646,
667
  Z18_Z19_Z20 = 647,
668
  Z19_Z20_Z21 = 648,
669
  Z20_Z21_Z22 = 649,
670
  Z21_Z22_Z23 = 650,
671
  Z22_Z23_Z24 = 651,
672
  Z23_Z24_Z25 = 652,
673
  Z24_Z25_Z26 = 653,
674
  Z25_Z26_Z27 = 654,
675
  Z26_Z27_Z28 = 655,
676
  Z27_Z28_Z29 = 656,
677
  Z28_Z29_Z30 = 657,
678
  Z29_Z30_Z31 = 658,
679
  Z30_Z31_Z0 = 659,
680
  Z31_Z0_Z1 = 660,
681
  NUM_TARGET_REGS   // 661
682
};
683
} // end namespace AArch64
684
685
// Register classes
686
687
namespace AArch64 {
688
enum {
689
  FPR8RegClassID = 0,
690
  FPR16RegClassID = 1,
691
  PPRRegClassID = 2,
692
  PPR_3bRegClassID = 3,
693
  GPR32allRegClassID = 4,
694
  FPR32RegClassID = 5,
695
  GPR32RegClassID = 6,
696
  GPR32spRegClassID = 7,
697
  GPR32commonRegClassID = 8,
698
  CCRRegClassID = 9,
699
  GPR32sponlyRegClassID = 10,
700
  WSeqPairsClassRegClassID = 11,
701
  WSeqPairsClass_with_sube32_in_GPR32commonRegClassID = 12,
702
  WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 13,
703
  WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 14,
704
  GPR64allRegClassID = 15,
705
  FPR64RegClassID = 16,
706
  GPR64RegClassID = 17,
707
  GPR64spRegClassID = 18,
708
  GPR64commonRegClassID = 19,
709
  tcGPR64RegClassID = 20,
710
  rtcGPR64RegClassID = 21,
711
  GPR64sponlyRegClassID = 22,
712
  DDRegClassID = 23,
713
  XSeqPairsClassRegClassID = 24,
714
  XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID = 25,
715
  XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 26,
716
  XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 27,
717
  XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 28,
718
  XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 29,
719
  XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 30,
720
  XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID = 31,
721
  XSeqPairsClass_with_subo64_in_rtcGPR64RegClassID = 32,
722
  XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64RegClassID = 33,
723
  FPR128RegClassID = 34,
724
  ZPRRegClassID = 35,
725
  FPR128_loRegClassID = 36,
726
  ZPR_4bRegClassID = 37,
727
  ZPR_3bRegClassID = 38,
728
  DDDRegClassID = 39,
729
  DDDDRegClassID = 40,
730
  QQRegClassID = 41,
731
  ZPR2RegClassID = 42,
732
  QQ_with_qsub0_in_FPR128_loRegClassID = 43,
733
  QQ_with_qsub1_in_FPR128_loRegClassID = 44,
734
  ZPR2_with_zsub1_in_ZPR_4bRegClassID = 45,
735
  ZPR2_with_zsub_in_FPR128_loRegClassID = 46,
736
  QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 47,
737
  ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 48,
738
  ZPR2_with_zsub0_in_ZPR_3bRegClassID = 49,
739
  ZPR2_with_zsub1_in_ZPR_3bRegClassID = 50,
740
  ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 51,
741
  QQQRegClassID = 52,
742
  ZPR3RegClassID = 53,
743
  QQQ_with_qsub0_in_FPR128_loRegClassID = 54,
744
  QQQ_with_qsub1_in_FPR128_loRegClassID = 55,
745
  QQQ_with_qsub2_in_FPR128_loRegClassID = 56,
746
  ZPR3_with_zsub1_in_ZPR_4bRegClassID = 57,
747
  ZPR3_with_zsub2_in_ZPR_4bRegClassID = 58,
748
  ZPR3_with_zsub_in_FPR128_loRegClassID = 59,
749
  QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 60,
750
  QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 61,
751
  ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 62,
752
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 63,
753
  QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 64,
754
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 65,
755
  ZPR3_with_zsub0_in_ZPR_3bRegClassID = 66,
756
  ZPR3_with_zsub1_in_ZPR_3bRegClassID = 67,
757
  ZPR3_with_zsub2_in_ZPR_3bRegClassID = 68,
758
  ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 69,
759
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 70,
760
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 71,
761
  QQQQRegClassID = 72,
762
  ZPR4RegClassID = 73,
763
  QQQQ_with_qsub0_in_FPR128_loRegClassID = 74,
764
  QQQQ_with_qsub1_in_FPR128_loRegClassID = 75,
765
  QQQQ_with_qsub2_in_FPR128_loRegClassID = 76,
766
  QQQQ_with_qsub3_in_FPR128_loRegClassID = 77,
767
  ZPR4_with_zsub1_in_ZPR_4bRegClassID = 78,
768
  ZPR4_with_zsub2_in_ZPR_4bRegClassID = 79,
769
  ZPR4_with_zsub3_in_ZPR_4bRegClassID = 80,
770
  ZPR4_with_zsub_in_FPR128_loRegClassID = 81,
771
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 82,
772
  QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 83,
773
  QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 84,
774
  ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 85,
775
  ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 86,
776
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 87,
777
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 88,
778
  QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 89,
779
  ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 90,
780
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 91,
781
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 92,
782
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 93,
783
  ZPR4_with_zsub0_in_ZPR_3bRegClassID = 94,
784
  ZPR4_with_zsub1_in_ZPR_3bRegClassID = 95,
785
  ZPR4_with_zsub2_in_ZPR_3bRegClassID = 96,
786
  ZPR4_with_zsub3_in_ZPR_3bRegClassID = 97,
787
  ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 98,
788
  ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 99,
789
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 100,
790
  ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 101,
791
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 102,
792
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 103,
793
794
  };
795
} // end namespace AArch64
796
797
798
// Register alternate name indices
799
800
namespace AArch64 {
801
enum {
802
  NoRegAltName, // 0
803
  vlist1, // 1
804
  vreg, // 2
805
  NUM_TARGET_REG_ALT_NAMES = 3
806
};
807
} // end namespace AArch64
808
809
810
// Subregister indices
811
812
namespace AArch64 {
813
enum {
814
  NoSubRegister,
815
  bsub, // 1
816
  dsub, // 2
817
  dsub0,  // 3
818
  dsub1,  // 4
819
  dsub2,  // 5
820
  dsub3,  // 6
821
  hsub, // 7
822
  qhisub, // 8
823
  qsub, // 9
824
  qsub0,  // 10
825
  qsub1,  // 11
826
  qsub2,  // 12
827
  qsub3,  // 13
828
  ssub, // 14
829
  sub_32, // 15
830
  sube32, // 16
831
  sube64, // 17
832
  subo32, // 18
833
  subo64, // 19
834
  zsub, // 20
835
  zsub0,  // 21
836
  zsub1,  // 22
837
  zsub2,  // 23
838
  zsub3,  // 24
839
  zsub_hi,  // 25
840
  dsub1_then_bsub,  // 26
841
  dsub1_then_hsub,  // 27
842
  dsub1_then_ssub,  // 28
843
  dsub3_then_bsub,  // 29
844
  dsub3_then_hsub,  // 30
845
  dsub3_then_ssub,  // 31
846
  dsub2_then_bsub,  // 32
847
  dsub2_then_hsub,  // 33
848
  dsub2_then_ssub,  // 34
849
  qsub1_then_bsub,  // 35
850
  qsub1_then_dsub,  // 36
851
  qsub1_then_hsub,  // 37
852
  qsub1_then_ssub,  // 38
853
  qsub3_then_bsub,  // 39
854
  qsub3_then_dsub,  // 40
855
  qsub3_then_hsub,  // 41
856
  qsub3_then_ssub,  // 42
857
  qsub2_then_bsub,  // 43
858
  qsub2_then_dsub,  // 44
859
  qsub2_then_hsub,  // 45
860
  qsub2_then_ssub,  // 46
861
  subo64_then_sub_32, // 47
862
  zsub1_then_bsub,  // 48
863
  zsub1_then_dsub,  // 49
864
  zsub1_then_hsub,  // 50
865
  zsub1_then_ssub,  // 51
866
  zsub1_then_zsub,  // 52
867
  zsub1_then_zsub_hi, // 53
868
  zsub3_then_bsub,  // 54
869
  zsub3_then_dsub,  // 55
870
  zsub3_then_hsub,  // 56
871
  zsub3_then_ssub,  // 57
872
  zsub3_then_zsub,  // 58
873
  zsub3_then_zsub_hi, // 59
874
  zsub2_then_bsub,  // 60
875
  zsub2_then_dsub,  // 61
876
  zsub2_then_hsub,  // 62
877
  zsub2_then_ssub,  // 63
878
  zsub2_then_zsub,  // 64
879
  zsub2_then_zsub_hi, // 65
880
  dsub0_dsub1,  // 66
881
  dsub0_dsub1_dsub2,  // 67
882
  dsub1_dsub2,  // 68
883
  dsub1_dsub2_dsub3,  // 69
884
  dsub2_dsub3,  // 70
885
  dsub_qsub1_then_dsub, // 71
886
  dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 72
887
  dsub_qsub1_then_dsub_qsub2_then_dsub, // 73
888
  qsub0_qsub1,  // 74
889
  qsub0_qsub1_qsub2,  // 75
890
  qsub1_qsub2,  // 76
891
  qsub1_qsub2_qsub3,  // 77
892
  qsub2_qsub3,  // 78
893
  qsub1_then_dsub_qsub2_then_dsub,  // 79
894
  qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,  // 80
895
  qsub2_then_dsub_qsub3_then_dsub,  // 81
896
  sub_32_subo64_then_sub_32,  // 82
897
  dsub_zsub1_then_dsub, // 83
898
  zsub_zsub1_then_zsub, // 84
899
  dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 85
900
  dsub_zsub1_then_dsub_zsub2_then_dsub, // 86
901
  zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 87
902
  zsub_zsub1_then_zsub_zsub2_then_zsub, // 88
903
  zsub0_zsub1,  // 89
904
  zsub0_zsub1_zsub2,  // 90
905
  zsub1_zsub2,  // 91
906
  zsub1_zsub2_zsub3,  // 92
907
  zsub2_zsub3,  // 93
908
  zsub1_then_dsub_zsub2_then_dsub,  // 94
909
  zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub,  // 95
910
  zsub1_then_zsub_zsub2_then_zsub,  // 96
911
  zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub,  // 97
912
  zsub2_then_dsub_zsub3_then_dsub,  // 98
913
  zsub2_then_zsub_zsub3_then_zsub,  // 99
914
  NUM_TARGET_SUBREGS
915
};
916
} // end namespace AArch64
917
918
} // end namespace llvm
919
920
#endif // GET_REGINFO_ENUM
921
922
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
923
|*                                                                            *|
924
|* MC Register Information                                                    *|
925
|*                                                                            *|
926
|* Automatically generated file, do not edit!                                 *|
927
|*                                                                            *|
928
\*===----------------------------------------------------------------------===*/
929
930
931
#ifdef GET_REGINFO_MC_DESC
932
#undef GET_REGINFO_MC_DESC
933
934
namespace llvm {
935
936
extern const MCPhysReg AArch64RegDiffLists[] = {
937
  /* 0 */ 64945, 1, 1, 1, 74, 1, 1, 1, 0,
938
  /* 9 */ 65105, 1, 1, 1, 0,
939
  /* 14 */ 65201, 1, 1, 1, 0,
940
  /* 19 */ 6, 29, 1, 1, 0,
941
  /* 24 */ 6, 29, 1, 1, 46, 29, 1, 1, 0,
942
  /* 33 */ 65324, 499, 30, 1, 1, 0,
943
  /* 39 */ 64913, 1, 1, 75, 1, 1, 0,
944
  /* 46 */ 65073, 1, 1, 0,
945
  /* 50 */ 65169, 1, 1, 0,
946
  /* 54 */ 6, 1, 29, 1, 0,
947
  /* 59 */ 6, 1, 29, 1, 46, 1, 29, 1, 0,
948
  /* 68 */ 6, 30, 1, 0,
949
  /* 72 */ 6, 30, 1, 46, 30, 1, 0,
950
  /* 79 */ 1, 493, 1, 32, 1, 0,
951
  /* 85 */ 31, 286, 1, 33, 1, 0,
952
  /* 91 */ 64977, 1, 76, 1, 0,
953
  /* 96 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0,
954
  /* 111 */ 320, 1, 0,
955
  /* 114 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0,
956
  /* 129 */ 526, 1, 0,
957
  /* 132 */ 530, 1, 0,
958
  /* 135 */ 65053, 1, 0,
959
  /* 138 */ 65087, 1, 0,
960
  /* 141 */ 65137, 1, 0,
961
  /* 144 */ 65218, 1, 0,
962
  /* 147 */ 65233, 1, 0,
963
  /* 150 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
964
  /* 183 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
965
  /* 203 */ 65504, 319, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
966
  /* 214 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
967
  /* 247 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
968
  /* 267 */ 65504, 320, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
969
  /* 278 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 128, 63, 65503, 34, 65503, 1, 0,
970
  /* 296 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
971
  /* 329 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
972
  /* 349 */ 65504, 319, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
973
  /* 360 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 97, 64, 65504, 63, 65503, 1, 0,
974
  /* 378 */ 65503, 1, 128, 65503, 1, 192, 65503, 1, 0,
975
  /* 387 */ 31, 285, 2, 32, 2, 0,
976
  /* 393 */ 319, 2, 0,
977
  /* 396 */ 65324, 529, 1, 1, 3, 0,
978
  /* 402 */ 2, 3, 0,
979
  /* 405 */ 531, 3, 0,
980
  /* 408 */ 65004, 3, 0,
981
  /* 411 */ 4, 0,
982
  /* 413 */ 5, 0,
983
  /* 415 */ 31, 286, 1, 5, 28, 0,
984
  /* 421 */ 292, 28, 0,
985
  /* 424 */ 6, 1, 1, 29, 0,
986
  /* 429 */ 6, 1, 1, 29, 46, 1, 1, 29, 0,
987
  /* 438 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
988
  /* 471 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
989
  /* 491 */ 65504, 319, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
990
  /* 502 */ 6, 1, 30, 0,
991
  /* 506 */ 6, 1, 30, 46, 1, 30, 0,
992
  /* 513 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 98, 63, 1, 65503, 1, 30, 0,
993
  /* 531 */ 6, 31, 0,
994
  /* 534 */ 6, 31, 46, 31, 0,
995
  /* 539 */ 65504, 31, 97, 65504, 31, 161, 65504, 31, 0,
996
  /* 548 */ 32, 0,
997
  /* 550 */ 34, 0,
998
  /* 552 */ 5, 49, 0,
999
  /* 555 */ 63936, 49, 0,
1000
  /* 558 */ 65297, 77, 0,
1001
  /* 561 */ 1, 81, 0,
1002
  /* 564 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 31, 96, 0,
1003
  /* 581 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 63, 96, 0,
1004
  /* 598 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 30, 96, 65504, 96, 96, 1, 65280, 96, 0,
1005
  /* 628 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 1, 65280, 96, 0,
1006
  /* 658 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 65505, 65280, 96, 0,
1007
  /* 688 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65441, 65311, 64, 32, 64, 65345, 96, 0,
1008
  /* 734 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65441, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
1009
  /* 780 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 29, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
1010
  /* 826 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
1011
  /* 872 */ 96, 160, 0,
1012
  /* 875 */ 65042, 178, 0,
1013
  /* 878 */ 212, 0,
1014
  /* 880 */ 65412, 65456, 112, 65456, 65472, 268, 0,
1015
  /* 887 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0,
1016
  /* 899 */ 65009, 65535, 209, 65505, 316, 0,
1017
  /* 905 */ 65005, 212, 65325, 212, 317, 0,
1018
  /* 911 */ 65244, 65505, 65325, 212, 317, 0,
1019
  /* 917 */ 65215, 65505, 32, 65505, 317, 0,
1020
  /* 923 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0,
1021
  /* 935 */ 65005, 212, 65329, 65535, 495, 0,
1022
  /* 941 */ 65323, 0,
1023
  /* 943 */ 65249, 65328, 0,
1024
  /* 946 */ 65342, 0,
1025
  /* 948 */ 65374, 0,
1026
  /* 950 */ 65389, 0,
1027
  /* 952 */ 65405, 0,
1028
  /* 954 */ 65421, 0,
1029
  /* 956 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0,
1030
  /* 977 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0,
1031
  /* 998 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0,
1032
  /* 1019 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
1033
  /* 1051 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0,
1034
  /* 1073 */ 65469, 0,
1035
  /* 1075 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0,
1036
  /* 1084 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0,
1037
  /* 1093 */ 65456, 112, 65456, 65472, 0,
1038
  /* 1098 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
1039
  /* 1130 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1040
  /* 1162 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1041
  /* 1194 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0,
1042
  /* 1216 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0,
1043
  /* 1238 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0,
1044
  /* 1260 */ 65501, 0,
1045
  /* 1262 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0,
1046
  /* 1277 */ 65533, 0,
1047
  /* 1279 */ 65535, 0,
1048
};
1049
1050
extern const LaneBitmask AArch64LaneMaskLists[] = {
1051
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
1052
  /* 2 */ LaneBitmask(0x00000080), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1053
  /* 5 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1054
  /* 10 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1055
  /* 14 */ LaneBitmask(0x00000400), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1056
  /* 17 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1057
  /* 22 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1058
  /* 26 */ LaneBitmask(0x00002000), LaneBitmask(0x00000008), LaneBitmask::getAll(),
1059
  /* 29 */ LaneBitmask(0x00000020), LaneBitmask(0x00000010), LaneBitmask::getAll(),
1060
  /* 32 */ LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
1061
  /* 35 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1062
  /* 38 */ LaneBitmask(0x00004000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1063
  /* 43 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1064
  /* 52 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1065
  /* 59 */ LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
1066
  /* 64 */ LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
1067
  /* 68 */ LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask::getAll(),
1068
  /* 73 */ LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask::getAll(),
1069
  /* 78 */ LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
1070
  /* 83 */ LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
1071
  /* 87 */ LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask::getAll(),
1072
  /* 92 */ LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask::getAll(),
1073
  /* 97 */ LaneBitmask(0x00000008), LaneBitmask(0x00002000), LaneBitmask::getAll(),
1074
  /* 100 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1075
  /* 105 */ LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1076
  /* 114 */ LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1077
  /* 121 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
1078
  /* 130 */ LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
1079
  /* 139 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
1080
};
1081
1082
extern const uint16_t AArch64SubRegIdxLists[] = {
1083
  /* 0 */ 2, 14, 7, 1, 0,
1084
  /* 5 */ 15, 0,
1085
  /* 7 */ 16, 18, 0,
1086
  /* 10 */ 20, 2, 14, 7, 1, 25, 0,
1087
  /* 17 */ 3, 14, 7, 1, 4, 28, 27, 26, 0,
1088
  /* 26 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 66, 68, 0,
1089
  /* 41 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 6, 31, 30, 29, 66, 67, 68, 69, 70, 0,
1090
  /* 63 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 71, 0,
1091
  /* 75 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 71, 73, 74, 76, 79, 0,
1092
  /* 96 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 13, 40, 42, 41, 39, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 0,
1093
  /* 128 */ 17, 15, 19, 47, 82, 0,
1094
  /* 134 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 83, 84, 0,
1095
  /* 151 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 83, 84, 86, 88, 89, 91, 94, 96, 0,
1096
  /* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0,
1097
};
1098
1099
extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = {
1100
  { 65535, 65535 },
1101
  { 0, 8 }, // bsub
1102
  { 0, 32 },  // dsub
1103
  { 0, 64 },  // dsub0
1104
  { 0, 64 },  // dsub1
1105
  { 0, 64 },  // dsub2
1106
  { 0, 64 },  // dsub3
1107
  { 0, 16 },  // hsub
1108
  { 0, 64 },  // qhisub
1109
  { 0, 64 },  // qsub
1110
  { 0, 128 }, // qsub0
1111
  { 0, 128 }, // qsub1
1112
  { 0, 128 }, // qsub2
1113
  { 0, 128 }, // qsub3
1114
  { 0, 32 },  // ssub
1115
  { 0, 32 },  // sub_32
1116
  { 0, 32 },  // sube32
1117
  { 0, 64 },  // sube64
1118
  { 0, 32 },  // subo32
1119
  { 0, 64 },  // subo64
1120
  { 0, 128 }, // zsub
1121
  { 65535, 128 }, // zsub0
1122
  { 65535, 128 }, // zsub1
1123
  { 65535, 128 }, // zsub2
1124
  { 65535, 128 }, // zsub3
1125
  { 0, 128 }, // zsub_hi
1126
  { 0, 8 }, // dsub1_then_bsub
1127
  { 0, 16 },  // dsub1_then_hsub
1128
  { 0, 32 },  // dsub1_then_ssub
1129
  { 0, 8 }, // dsub3_then_bsub
1130
  { 0, 16 },  // dsub3_then_hsub
1131
  { 0, 32 },  // dsub3_then_ssub
1132
  { 0, 8 }, // dsub2_then_bsub
1133
  { 0, 16 },  // dsub2_then_hsub
1134
  { 0, 32 },  // dsub2_then_ssub
1135
  { 0, 8 }, // qsub1_then_bsub
1136
  { 0, 32 },  // qsub1_then_dsub
1137
  { 0, 16 },  // qsub1_then_hsub
1138
  { 0, 32 },  // qsub1_then_ssub
1139
  { 0, 8 }, // qsub3_then_bsub
1140
  { 0, 32 },  // qsub3_then_dsub
1141
  { 0, 16 },  // qsub3_then_hsub
1142
  { 0, 32 },  // qsub3_then_ssub
1143
  { 0, 8 }, // qsub2_then_bsub
1144
  { 0, 32 },  // qsub2_then_dsub
1145
  { 0, 16 },  // qsub2_then_hsub
1146
  { 0, 32 },  // qsub2_then_ssub
1147
  { 0, 32 },  // subo64_then_sub_32
1148
  { 65535, 65535 }, // zsub1_then_bsub
1149
  { 65535, 65535 }, // zsub1_then_dsub
1150
  { 65535, 65535 }, // zsub1_then_hsub
1151
  { 65535, 65535 }, // zsub1_then_ssub
1152
  { 65535, 65535 }, // zsub1_then_zsub
1153
  { 65535, 65535 }, // zsub1_then_zsub_hi
1154
  { 65535, 65535 }, // zsub3_then_bsub
1155
  { 65535, 65535 }, // zsub3_then_dsub
1156
  { 65535, 65535 }, // zsub3_then_hsub
1157
  { 65535, 65535 }, // zsub3_then_ssub
1158
  { 65535, 65535 }, // zsub3_then_zsub
1159
  { 65535, 65535 }, // zsub3_then_zsub_hi
1160
  { 65535, 65535 }, // zsub2_then_bsub
1161
  { 65535, 65535 }, // zsub2_then_dsub
1162
  { 65535, 65535 }, // zsub2_then_hsub
1163
  { 65535, 65535 }, // zsub2_then_ssub
1164
  { 65535, 65535 }, // zsub2_then_zsub
1165
  { 65535, 65535 }, // zsub2_then_zsub_hi
1166
  { 65535, 128 }, // dsub0_dsub1
1167
  { 65535, 192 }, // dsub0_dsub1_dsub2
1168
  { 65535, 128 }, // dsub1_dsub2
1169
  { 65535, 192 }, // dsub1_dsub2_dsub3
1170
  { 65535, 128 }, // dsub2_dsub3
1171
  { 65535, 64 },  // dsub_qsub1_then_dsub
1172
  { 65535, 128 }, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
1173
  { 65535, 96 },  // dsub_qsub1_then_dsub_qsub2_then_dsub
1174
  { 65535, 256 }, // qsub0_qsub1
1175
  { 65535, 384 }, // qsub0_qsub1_qsub2
1176
  { 65535, 256 }, // qsub1_qsub2
1177
  { 65535, 384 }, // qsub1_qsub2_qsub3
1178
  { 65535, 256 }, // qsub2_qsub3
1179
  { 65535, 64 },  // qsub1_then_dsub_qsub2_then_dsub
1180
  { 65535, 96 },  // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
1181
  { 65535, 64 },  // qsub2_then_dsub_qsub3_then_dsub
1182
  { 65535, 64 },  // sub_32_subo64_then_sub_32
1183
  { 65535, 31 },  // dsub_zsub1_then_dsub
1184
  { 65535, 127 }, // zsub_zsub1_then_zsub
1185
  { 65535, 29 },  // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
1186
  { 65535, 30 },  // dsub_zsub1_then_dsub_zsub2_then_dsub
1187
  { 65535, 125 }, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
1188
  { 65535, 126 }, // zsub_zsub1_then_zsub_zsub2_then_zsub
1189
  { 65535, 256 }, // zsub0_zsub1
1190
  { 65535, 384 }, // zsub0_zsub1_zsub2
1191
  { 65535, 256 }, // zsub1_zsub2
1192
  { 65535, 384 }, // zsub1_zsub2_zsub3
1193
  { 65535, 256 }, // zsub2_zsub3
1194
  { 65535, 65534 }, // zsub1_then_dsub_zsub2_then_dsub
1195
  { 65535, 65533 }, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
1196
  { 65535, 65534 }, // zsub1_then_zsub_zsub2_then_zsub
1197
  { 65535, 65533 }, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
1198
  { 65535, 65534 }, // zsub2_then_dsub_zsub3_then_dsub
1199
  { 65535, 65534 }, // zsub2_then_zsub_zsub3_then_zsub
1200
};
1201
1202
extern const char AArch64RegStrings[] = {
1203
  /* 0 */ 'B', '1', '0', 0,
1204
  /* 4 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
1205
  /* 17 */ 'H', '1', '0', 0,
1206
  /* 21 */ 'P', '1', '0', 0,
1207
  /* 25 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
1208
  /* 38 */ 'S', '1', '0', 0,
1209
  /* 42 */ 'W', '9', '_', 'W', '1', '0', 0,
1210
  /* 49 */ 'X', '9', '_', 'X', '1', '0', 0,
1211
  /* 56 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0,
1212
  /* 69 */ 'B', '2', '0', 0,
1213
  /* 73 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
1214
  /* 89 */ 'H', '2', '0', 0,
1215
  /* 93 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
1216
  /* 109 */ 'S', '2', '0', 0,
1217
  /* 113 */ 'W', '1', '9', '_', 'W', '2', '0', 0,
1218
  /* 121 */ 'X', '1', '9', '_', 'X', '2', '0', 0,
1219
  /* 129 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0,
1220
  /* 145 */ 'B', '3', '0', 0,
1221
  /* 149 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
1222
  /* 165 */ 'H', '3', '0', 0,
1223
  /* 169 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
1224
  /* 185 */ 'S', '3', '0', 0,
1225
  /* 189 */ 'W', '2', '9', '_', 'W', '3', '0', 0,
1226
  /* 197 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0,
1227
  /* 213 */ 'B', '0', 0,
1228
  /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
1229
  /* 231 */ 'H', '0', 0,
1230
  /* 234 */ 'P', '0', 0,
1231
  /* 237 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
1232
  /* 252 */ 'S', '0', 0,
1233
  /* 255 */ 'W', 'Z', 'R', '_', 'W', '0', 0,
1234
  /* 262 */ 'X', 'Z', 'R', '_', 'X', '0', 0,
1235
  /* 269 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0,
1236
  /* 284 */ 'B', '1', '1', 0,
1237
  /* 288 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
1238
  /* 302 */ 'H', '1', '1', 0,
1239
  /* 306 */ 'P', '1', '1', 0,
1240
  /* 310 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
1241
  /* 324 */ 'S', '1', '1', 0,
1242
  /* 328 */ 'W', '1', '0', '_', 'W', '1', '1', 0,
1243
  /* 336 */ 'X', '1', '0', '_', 'X', '1', '1', 0,
1244
  /* 344 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0,
1245
  /* 358 */ 'B', '2', '1', 0,
1246
  /* 362 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
1247
  /* 378 */ 'H', '2', '1', 0,
1248
  /* 382 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
1249
  /* 398 */ 'S', '2', '1', 0,
1250
  /* 402 */ 'W', '2', '0', '_', 'W', '2', '1', 0,
1251
  /* 410 */ 'X', '2', '0', '_', 'X', '2', '1', 0,
1252
  /* 418 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0,
1253
  /* 434 */ 'B', '3', '1', 0,
1254
  /* 438 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
1255
  /* 454 */ 'H', '3', '1', 0,
1256
  /* 458 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
1257
  /* 474 */ 'S', '3', '1', 0,
1258
  /* 478 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0,
1259
  /* 494 */ 'B', '1', 0,
1260
  /* 497 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
1261
  /* 511 */ 'H', '1', 0,
1262
  /* 514 */ 'P', '1', 0,
1263
  /* 517 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
1264
  /* 531 */ 'S', '1', 0,
1265
  /* 534 */ 'W', '0', '_', 'W', '1', 0,
1266
  /* 540 */ 'X', '0', '_', 'X', '1', 0,
1267
  /* 546 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0,
1268
  /* 560 */ 'B', '1', '2', 0,
1269
  /* 564 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
1270
  /* 579 */ 'H', '1', '2', 0,
1271
  /* 583 */ 'P', '1', '2', 0,
1272
  /* 587 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
1273
  /* 602 */ 'S', '1', '2', 0,
1274
  /* 606 */ 'W', '1', '1', '_', 'W', '1', '2', 0,
1275
  /* 614 */ 'X', '1', '1', '_', 'X', '1', '2', 0,
1276
  /* 622 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0,
1277
  /* 637 */ 'B', '2', '2', 0,
1278
  /* 641 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
1279
  /* 657 */ 'H', '2', '2', 0,
1280
  /* 661 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
1281
  /* 677 */ 'S', '2', '2', 0,
1282
  /* 681 */ 'W', '2', '1', '_', 'W', '2', '2', 0,
1283
  /* 689 */ 'X', '2', '1', '_', 'X', '2', '2', 0,
1284
  /* 697 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0,
1285
  /* 713 */ 'B', '2', 0,
1286
  /* 716 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
1287
  /* 729 */ 'H', '2', 0,
1288
  /* 732 */ 'P', '2', 0,
1289
  /* 735 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
1290
  /* 748 */ 'S', '2', 0,
1291
  /* 751 */ 'W', '1', '_', 'W', '2', 0,
1292
  /* 757 */ 'X', '1', '_', 'X', '2', 0,
1293
  /* 763 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0,
1294
  /* 776 */ 'B', '1', '3', 0,
1295
  /* 780 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
1296
  /* 796 */ 'H', '1', '3', 0,
1297
  /* 800 */ 'P', '1', '3', 0,
1298
  /* 804 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
1299
  /* 820 */ 'S', '1', '3', 0,
1300
  /* 824 */ 'W', '1', '2', '_', 'W', '1', '3', 0,
1301
  /* 832 */ 'X', '1', '2', '_', 'X', '1', '3', 0,
1302
  /* 840 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0,
1303
  /* 856 */ 'B', '2', '3', 0,
1304
  /* 860 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
1305
  /* 876 */ 'H', '2', '3', 0,
1306
  /* 880 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
1307
  /* 896 */ 'S', '2', '3', 0,
1308
  /* 900 */ 'W', '2', '2', '_', 'W', '2', '3', 0,
1309
  /* 908 */ 'X', '2', '2', '_', 'X', '2', '3', 0,
1310
  /* 916 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0,
1311
  /* 932 */ 'B', '3', 0,
1312
  /* 935 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
1313
  /* 947 */ 'H', '3', 0,
1314
  /* 950 */ 'P', '3', 0,
1315
  /* 953 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
1316
  /* 965 */ 'S', '3', 0,
1317
  /* 968 */ 'W', '2', '_', 'W', '3', 0,
1318
  /* 974 */ 'X', '2', '_', 'X', '3', 0,
1319
  /* 980 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0,
1320
  /* 992 */ 'B', '1', '4', 0,
1321
  /* 996 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
1322
  /* 1012 */ 'H', '1', '4', 0,
1323
  /* 1016 */ 'P', '1', '4', 0,
1324
  /* 1020 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
1325
  /* 1036 */ 'S', '1', '4', 0,
1326
  /* 1040 */ 'W', '1', '3', '_', 'W', '1', '4', 0,
1327
  /* 1048 */ 'X', '1', '3', '_', 'X', '1', '4', 0,
1328
  /* 1056 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0,
1329
  /* 1072 */ 'B', '2', '4', 0,
1330
  /* 1076 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
1331
  /* 1092 */ 'H', '2', '4', 0,
1332
  /* 1096 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
1333
  /* 1112 */ 'S', '2', '4', 0,
1334
  /* 1116 */ 'W', '2', '3', '_', 'W', '2', '4', 0,
1335
  /* 1124 */ 'X', '2', '3', '_', 'X', '2', '4', 0,
1336
  /* 1132 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0,
1337
  /* 1148 */ 'B', '4', 0,
1338
  /* 1151 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
1339
  /* 1163 */ 'H', '4', 0,
1340
  /* 1166 */ 'P', '4', 0,
1341
  /* 1169 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
1342
  /* 1181 */ 'S', '4', 0,
1343
  /* 1184 */ 'W', '3', '_', 'W', '4', 0,
1344
  /* 1190 */ 'X', '3', '_', 'X', '4', 0,
1345
  /* 1196 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0,
1346
  /* 1208 */ 'B', '1', '5', 0,
1347
  /* 1212 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
1348
  /* 1228 */ 'H', '1', '5', 0,
1349
  /* 1232 */ 'P', '1', '5', 0,
1350
  /* 1236 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
1351
  /* 1252 */ 'S', '1', '5', 0,
1352
  /* 1256 */ 'W', '1', '4', '_', 'W', '1', '5', 0,
1353
  /* 1264 */ 'X', '1', '4', '_', 'X', '1', '5', 0,
1354
  /* 1272 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0,
1355
  /* 1288 */ 'B', '2', '5', 0,
1356
  /* 1292 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
1357
  /* 1308 */ 'H', '2', '5', 0,
1358
  /* 1312 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
1359
  /* 1328 */ 'S', '2', '5', 0,
1360
  /* 1332 */ 'W', '2', '4', '_', 'W', '2', '5', 0,
1361
  /* 1340 */ 'X', '2', '4', '_', 'X', '2', '5', 0,
1362
  /* 1348 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0,
1363
  /* 1364 */ 'B', '5', 0,
1364
  /* 1367 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
1365
  /* 1379 */ 'H', '5', 0,
1366
  /* 1382 */ 'P', '5', 0,
1367
  /* 1385 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
1368
  /* 1397 */ 'S', '5', 0,
1369
  /* 1400 */ 'W', '4', '_', 'W', '5', 0,
1370
  /* 1406 */ 'X', '4', '_', 'X', '5', 0,
1371
  /* 1412 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0,
1372
  /* 1424 */ 'B', '1', '6', 0,
1373
  /* 1428 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
1374
  /* 1444 */ 'H', '1', '6', 0,
1375
  /* 1448 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
1376
  /* 1464 */ 'S', '1', '6', 0,
1377
  /* 1468 */ 'W', '1', '5', '_', 'W', '1', '6', 0,
1378
  /* 1476 */ 'X', '1', '5', '_', 'X', '1', '6', 0,
1379
  /* 1484 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0,
1380
  /* 1500 */ 'B', '2', '6', 0,
1381
  /* 1504 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
1382
  /* 1520 */ 'H', '2', '6', 0,
1383
  /* 1524 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
1384
  /* 1540 */ 'S', '2', '6', 0,
1385
  /* 1544 */ 'W', '2', '5', '_', 'W', '2', '6', 0,
1386
  /* 1552 */ 'X', '2', '5', '_', 'X', '2', '6', 0,
1387
  /* 1560 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0,
1388
  /* 1576 */ 'B', '6', 0,
1389
  /* 1579 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
1390
  /* 1591 */ 'H', '6', 0,
1391
  /* 1594 */ 'P', '6', 0,
1392
  /* 1597 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
1393
  /* 1609 */ 'S', '6', 0,
1394
  /* 1612 */ 'W', '5', '_', 'W', '6', 0,
1395
  /* 1618 */ 'X', '5', '_', 'X', '6', 0,
1396
  /* 1624 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0,
1397
  /* 1636 */ 'B', '1', '7', 0,
1398
  /* 1640 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
1399
  /* 1656 */ 'H', '1', '7', 0,
1400
  /* 1660 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
1401
  /* 1676 */ 'S', '1', '7', 0,
1402
  /* 1680 */ 'W', '1', '6', '_', 'W', '1', '7', 0,
1403
  /* 1688 */ 'X', '1', '6', '_', 'X', '1', '7', 0,
1404
  /* 1696 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0,
1405
  /* 1712 */ 'B', '2', '7', 0,
1406
  /* 1716 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
1407
  /* 1732 */ 'H', '2', '7', 0,
1408
  /* 1736 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
1409
  /* 1752 */ 'S', '2', '7', 0,
1410
  /* 1756 */ 'W', '2', '6', '_', 'W', '2', '7', 0,
1411
  /* 1764 */ 'X', '2', '6', '_', 'X', '2', '7', 0,
1412
  /* 1772 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0,
1413
  /* 1788 */ 'B', '7', 0,
1414
  /* 1791 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
1415
  /* 1803 */ 'H', '7', 0,
1416
  /* 1806 */ 'P', '7', 0,
1417
  /* 1809 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
1418
  /* 1821 */ 'S', '7', 0,
1419
  /* 1824 */ 'W', '6', '_', 'W', '7', 0,
1420
  /* 1830 */ 'X', '6', '_', 'X', '7', 0,
1421
  /* 1836 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0,
1422
  /* 1848 */ 'B', '1', '8', 0,
1423
  /* 1852 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
1424
  /* 1868 */ 'H', '1', '8', 0,
1425
  /* 1872 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
1426
  /* 1888 */ 'S', '1', '8', 0,
1427
  /* 1892 */ 'W', '1', '7', '_', 'W', '1', '8', 0,
1428
  /* 1900 */ 'X', '1', '7', '_', 'X', '1', '8', 0,
1429
  /* 1908 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0,
1430
  /* 1924 */ 'B', '2', '8', 0,
1431
  /* 1928 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
1432
  /* 1944 */ 'H', '2', '8', 0,
1433
  /* 1948 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
1434
  /* 1964 */ 'S', '2', '8', 0,
1435
  /* 1968 */ 'W', '2', '7', '_', 'W', '2', '8', 0,
1436
  /* 1976 */ 'X', '2', '7', '_', 'X', '2', '8', 0,
1437
  /* 1984 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0,
1438
  /* 2000 */ 'B', '8', 0,
1439
  /* 2003 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
1440
  /* 2015 */ 'H', '8', 0,
1441
  /* 2018 */ 'P', '8', 0,
1442
  /* 2021 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
1443
  /* 2033 */ 'S', '8', 0,
1444
  /* 2036 */ 'W', '7', '_', 'W', '8', 0,
1445
  /* 2042 */ 'X', '7', '_', 'X', '8', 0,
1446
  /* 2048 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0,
1447
  /* 2060 */ 'B', '1', '9', 0,
1448
  /* 2064 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
1449
  /* 2080 */ 'H', '1', '9', 0,
1450
  /* 2084 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
1451
  /* 2100 */ 'S', '1', '9', 0,
1452
  /* 2104 */ 'W', '1', '8', '_', 'W', '1', '9', 0,
1453
  /* 2112 */ 'X', '1', '8', '_', 'X', '1', '9', 0,
1454
  /* 2120 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0,
1455
  /* 2136 */ 'B', '2', '9', 0,
1456
  /* 2140 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
1457
  /* 2156 */ 'H', '2', '9', 0,
1458
  /* 2160 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
1459
  /* 2176 */ 'S', '2', '9', 0,
1460
  /* 2180 */ 'W', '2', '8', '_', 'W', '2', '9', 0,
1461
  /* 2188 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0,
1462
  /* 2204 */ 'B', '9', 0,
1463
  /* 2207 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
1464
  /* 2219 */ 'H', '9', 0,
1465
  /* 2222 */ 'P', '9', 0,
1466
  /* 2225 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
1467
  /* 2237 */ 'S', '9', 0,
1468
  /* 2240 */ 'W', '8', '_', 'W', '9', 0,
1469
  /* 2246 */ 'X', '8', '_', 'X', '9', 0,
1470
  /* 2252 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0,
1471
  /* 2264 */ 'Z', '1', '0', '_', 'H', 'I', 0,
1472
  /* 2271 */ 'Z', '2', '0', '_', 'H', 'I', 0,
1473
  /* 2278 */ 'Z', '3', '0', '_', 'H', 'I', 0,
1474
  /* 2285 */ 'Z', '0', '_', 'H', 'I', 0,
1475
  /* 2291 */ 'Z', '1', '1', '_', 'H', 'I', 0,
1476
  /* 2298 */ 'Z', '2', '1', '_', 'H', 'I', 0,
1477
  /* 2305 */ 'Z', '3', '1', '_', 'H', 'I', 0,
1478
  /* 2312 */ 'Z', '1', '_', 'H', 'I', 0,
1479
  /* 2318 */ 'Z', '1', '2', '_', 'H', 'I', 0,
1480
  /* 2325 */ 'Z', '2', '2', '_', 'H', 'I', 0,
1481
  /* 2332 */ 'Z', '2', '_', 'H', 'I', 0,
1482
  /* 2338 */ 'Z', '1', '3', '_', 'H', 'I', 0,
1483
  /* 2345 */ 'Z', '2', '3', '_', 'H', 'I', 0,
1484
  /* 2352 */ 'Z', '3', '_', 'H', 'I', 0,
1485
  /* 2358 */ 'Z', '1', '4', '_', 'H', 'I', 0,
1486
  /* 2365 */ 'Z', '2', '4', '_', 'H', 'I', 0,
1487
  /* 2372 */ 'Z', '4', '_', 'H', 'I', 0,
1488
  /* 2378 */ 'Z', '1', '5', '_', 'H', 'I', 0,
1489
  /* 2385 */ 'Z', '2', '5', '_', 'H', 'I', 0,
1490
  /* 2392 */ 'Z', '5', '_', 'H', 'I', 0,
1491
  /* 2398 */ 'Z', '1', '6', '_', 'H', 'I', 0,
1492
  /* 2405 */ 'Z', '2', '6', '_', 'H', 'I', 0,
1493
  /* 2412 */ 'Z', '6', '_', 'H', 'I', 0,
1494
  /* 2418 */ 'Z', '1', '7', '_', 'H', 'I', 0,
1495
  /* 2425 */ 'Z', '2', '7', '_', 'H', 'I', 0,
1496
  /* 2432 */ 'Z', '7', '_', 'H', 'I', 0,
1497
  /* 2438 */ 'Z', '1', '8', '_', 'H', 'I', 0,
1498
  /* 2445 */ 'Z', '2', '8', '_', 'H', 'I', 0,
1499
  /* 2452 */ 'Z', '8', '_', 'H', 'I', 0,
1500
  /* 2458 */ 'Z', '1', '9', '_', 'H', 'I', 0,
1501
  /* 2465 */ 'Z', '2', '9', '_', 'H', 'I', 0,
1502
  /* 2472 */ 'Z', '9', '_', 'H', 'I', 0,
1503
  /* 2478 */ 'X', '2', '8', '_', 'F', 'P', 0,
1504
  /* 2485 */ 'W', 'S', 'P', 0,
1505
  /* 2489 */ 'F', 'F', 'R', 0,
1506
  /* 2493 */ 'F', 'P', '_', 'L', 'R', 0,
1507
  /* 2499 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0,
1508
  /* 2507 */ 'L', 'R', '_', 'X', 'Z', 'R', 0,
1509
  /* 2514 */ 'N', 'Z', 'C', 'V', 0,
1510
};
1511
1512
extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
1513
  { 3, 0, 0, 0, 0, 0 },
1514
  { 2489, 8, 8, 4, 20465, 0 },
1515
  { 2482, 878, 405, 5, 20465, 27 },
1516
  { 2496, 878, 132, 5, 20465, 27 },
1517
  { 2514, 8, 8, 4, 20465, 0 },
1518
  { 2486, 7, 8, 5, 6576, 27 },
1519
  { 2485, 8, 1279, 4, 6576, 0 },
1520
  { 2503, 8, 79, 4, 6608, 0 },
1521
  { 2510, 1279, 129, 5, 6608, 27 },
1522
  { 213, 8, 214, 4, 20433, 0 },
1523
  { 494, 8, 296, 4, 20433, 0 },
1524
  { 713, 8, 438, 4, 20433, 0 },
1525
  { 932, 8, 150, 4, 20433, 0 },
1526
  { 1148, 8, 150, 4, 20433, 0 },
1527
  { 1364, 8, 150, 4, 20433, 0 },
1528
  { 1576, 8, 150, 4, 20433, 0 },
1529
  { 1788, 8, 150, 4, 20433, 0 },
1530
  { 2000, 8, 150, 4, 20433, 0 },
1531
  { 2204, 8, 150, 4, 20433, 0 },
1532
  { 0, 8, 150, 4, 20433, 0 },
1533
  { 284, 8, 150, 4, 20433, 0 },
1534
  { 560, 8, 150, 4, 20433, 0 },
1535
  { 776, 8, 150, 4, 20433, 0 },
1536
  { 992, 8, 150, 4, 20433, 0 },
1537
  { 1208, 8, 150, 4, 20433, 0 },
1538
  { 1424, 8, 150, 4, 20433, 0 },
1539
  { 1636, 8, 150, 4, 20433, 0 },
1540
  { 1848, 8, 150, 4, 20433, 0 },
1541
  { 2060, 8, 150, 4, 20433, 0 },
1542
  { 69, 8, 150, 4, 20433, 0 },
1543
  { 358, 8, 150, 4, 20433, 0 },
1544
  { 637, 8, 150, 4, 20433, 0 },
1545
  { 856, 8, 150, 4, 20433, 0 },
1546
  { 1072, 8, 150, 4, 20433, 0 },
1547
  { 1288, 8, 150, 4, 20433, 0 },
1548
  { 1500, 8, 150, 4, 20433, 0 },
1549
  { 1712, 8, 150, 4, 20433, 0 },
1550
  { 1924, 8, 150, 4, 20433, 0 },
1551
  { 2136, 8, 150, 4, 20433, 0 },
1552
  { 145, 8, 150, 4, 20433, 0 },
1553
  { 434, 8, 150, 4, 20433, 0 },
1554
  { 228, 1080, 217, 1, 20161, 3 },
1555
  { 508, 1080, 299, 1, 20161, 3 },
1556
  { 726, 1080, 441, 1, 20161, 3 },
1557
  { 944, 1080, 153, 1, 20161, 3 },
1558
  { 1160, 1080, 153, 1, 20161, 3 },
1559
  { 1376, 1080, 153, 1, 20161, 3 },
1560
  { 1588, 1080, 153, 1, 20161, 3 },
1561
  { 1800, 1080, 153, 1, 20161, 3 },
1562
  { 2012, 1080, 153, 1, 20161, 3 },
1563
  { 2216, 1080, 153, 1, 20161, 3 },
1564
  { 13, 1080, 153, 1, 20161, 3 },
1565
  { 298, 1080, 153, 1, 20161, 3 },
1566
  { 575, 1080, 153, 1, 20161, 3 },
1567
  { 792, 1080, 153, 1, 20161, 3 },
1568
  { 1008, 1080, 153, 1, 20161, 3 },
1569
  { 1224, 1080, 153, 1, 20161, 3 },
1570
  { 1440, 1080, 153, 1, 20161, 3 },
1571
  { 1652, 1080, 153, 1, 20161, 3 },
1572
  { 1864, 1080, 153, 1, 20161, 3 },
1573
  { 2076, 1080, 153, 1, 20161, 3 },
1574
  { 85, 1080, 153, 1, 20161, 3 },
1575
  { 374, 1080, 153, 1, 20161, 3 },
1576
  { 653, 1080, 153, 1, 20161, 3 },
1577
  { 872, 1080, 153, 1, 20161, 3 },
1578
  { 1088, 1080, 153, 1, 20161, 3 },
1579
  { 1304, 1080, 153, 1, 20161, 3 },
1580
  { 1516, 1080, 153, 1, 20161, 3 },
1581
  { 1728, 1080, 153, 1, 20161, 3 },
1582
  { 1940, 1080, 153, 1, 20161, 3 },
1583
  { 2152, 1080, 153, 1, 20161, 3 },
1584
  { 161, 1080, 153, 1, 20161, 3 },
1585
  { 450, 1080, 153, 1, 20161, 3 },
1586
  { 231, 1082, 215, 3, 17169, 3 },
1587
  { 511, 1082, 297, 3, 17169, 3 },
1588
  { 729, 1082, 439, 3, 17169, 3 },
1589
  { 947, 1082, 151, 3, 17169, 3 },
1590
  { 1163, 1082, 151, 3, 17169, 3 },
1591
  { 1379, 1082, 151, 3, 17169, 3 },
1592
  { 1591, 1082, 151, 3, 17169, 3 },
1593
  { 1803, 1082, 151, 3, 17169, 3 },
1594
  { 2015, 1082, 151, 3, 17169, 3 },
1595
  { 2219, 1082, 151, 3, 17169, 3 },
1596
  { 17, 1082, 151, 3, 17169, 3 },
1597
  { 302, 1082, 151, 3, 17169, 3 },
1598
  { 579, 1082, 151, 3, 17169, 3 },
1599
  { 796, 1082, 151, 3, 17169, 3 },
1600
  { 1012, 1082, 151, 3, 17169, 3 },
1601
  { 1228, 1082, 151, 3, 17169, 3 },
1602
  { 1444, 1082, 151, 3, 17169, 3 },
1603
  { 1656, 1082, 151, 3, 17169, 3 },
1604
  { 1868, 1082, 151, 3, 17169, 3 },
1605
  { 2080, 1082, 151, 3, 17169, 3 },
1606
  { 89, 1082, 151, 3, 17169, 3 },
1607
  { 378, 1082, 151, 3, 17169, 3 },
1608
  { 657, 1082, 151, 3, 17169, 3 },
1609
  { 876, 1082, 151, 3, 17169, 3 },
1610
  { 1092, 1082, 151, 3, 17169, 3 },
1611
  { 1308, 1082, 151, 3, 17169, 3 },
1612
  { 1520, 1082, 151, 3, 17169, 3 },
1613
  { 1732, 1082, 151, 3, 17169, 3 },
1614
  { 1944, 1082, 151, 3, 17169, 3 },
1615
  { 2156, 1082, 151, 3, 17169, 3 },
1616
  { 165, 1082, 151, 3, 17169, 3 },
1617
  { 454, 1082, 151, 3, 17169, 3 },
1618
  { 234, 8, 8, 4, 17169, 0 },
1619
  { 514, 8, 8, 4, 17169, 0 },
1620
  { 732, 8, 8, 4, 17169, 0 },
1621
  { 950, 8, 8, 4, 17169, 0 },
1622
  { 1166, 8, 8, 4, 17169, 0 },
1623
  { 1382, 8, 8, 4, 17169, 0 },
1624
  { 1594, 8, 8, 4, 17169, 0 },
1625
  { 1806, 8, 8, 4, 17169, 0 },
1626
  { 2018, 8, 8, 4, 17169, 0 },
1627
  { 2222, 8, 8, 4, 17169, 0 },
1628
  { 21, 8, 8, 4, 17169, 0 },
1629
  { 306, 8, 8, 4, 17169, 0 },
1630
  { 583, 8, 8, 4, 17169, 0 },
1631
  { 800, 8, 8, 4, 17169, 0 },
1632
  { 1016, 8, 8, 4, 17169, 0 },
1633
  { 1232, 8, 8, 4, 17169, 0 },
1634
  { 249, 1093, 247, 0, 15265, 3 },
1635
  { 528, 1093, 329, 0, 15265, 3 },
1636
  { 745, 1093, 471, 0, 15265, 3 },
1637
  { 962, 1093, 183, 0, 15265, 3 },
1638
  { 1178, 1093, 183, 0, 15265, 3 },
1639
  { 1394, 1093, 183, 0, 15265, 3 },
1640
  { 1606, 1093, 183, 0, 15265, 3 },
1641
  { 1818, 1093, 183, 0, 15265, 3 },
1642
  { 2030, 1093, 183, 0, 15265, 3 },
1643
  { 2234, 1093, 183, 0, 15265, 3 },
1644
  { 34, 1093, 183, 0, 15265, 3 },
1645
  { 320, 1093, 183, 0, 15265, 3 },
1646
  { 598, 1093, 183, 0, 15265, 3 },
1647
  { 816, 1093, 183, 0, 15265, 3 },
1648
  { 1032, 1093, 183, 0, 15265, 3 },
1649
  { 1248, 1093, 183, 0, 15265, 3 },
1650
  { 1460, 1093, 183, 0, 15265, 3 },
1651
  { 1672, 1093, 183, 0, 15265, 3 },
1652
  { 1884, 1093, 183, 0, 15265, 3 },
1653
  { 2096, 1093, 183, 0, 15265, 3 },
1654
  { 105, 1093, 183, 0, 15265, 3 },
1655
  { 394, 1093, 183, 0, 15265, 3 },
1656
  { 673, 1093, 183, 0, 15265, 3 },
1657
  { 892, 1093, 183, 0, 15265, 3 },
1658
  { 1108, 1093, 183, 0, 15265, 3 },
1659
  { 1324, 1093, 183, 0, 15265, 3 },
1660
  { 1536, 1093, 183, 0, 15265, 3 },
1661
  { 1748, 1093, 183, 0, 15265, 3 },
1662
  { 1960, 1093, 183, 0, 15265, 3 },
1663
  { 2172, 1093, 183, 0, 15265, 3 },
1664
  { 181, 1093, 183, 0, 15265, 3 },
1665
  { 470, 1093, 183, 0, 15265, 3 },
1666
  { 252, 1081, 216, 2, 15201, 3 },
1667
  { 531, 1081, 298, 2, 15201, 3 },
1668
  { 748, 1081, 440, 2, 15201, 3 },
1669
  { 965, 1081, 152, 2, 15201, 3 },
1670
  { 1181, 1081, 152, 2, 15201, 3 },
1671
  { 1397, 1081, 152, 2, 15201, 3 },
1672
  { 1609, 1081, 152, 2, 15201, 3 },
1673
  { 1821, 1081, 152, 2, 15201, 3 },
1674
  { 2033, 1081, 152, 2, 15201, 3 },
1675
  { 2237, 1081, 152, 2, 15201, 3 },
1676
  { 38, 1081, 152, 2, 15201, 3 },
1677
  { 324, 1081, 152, 2, 15201, 3 },
1678
  { 602, 1081, 152, 2, 15201, 3 },
1679
  { 820, 1081, 152, 2, 15201, 3 },
1680
  { 1036, 1081, 152, 2, 15201, 3 },
1681
  { 1252, 1081, 152, 2, 15201, 3 },
1682
  { 1464, 1081, 152, 2, 15201, 3 },
1683
  { 1676, 1081, 152, 2, 15201, 3 },
1684
  { 1888, 1081, 152, 2, 15201, 3 },
1685
  { 2100, 1081, 152, 2, 15201, 3 },
1686
  { 109, 1081, 152, 2, 15201, 3 },
1687
  { 398, 1081, 152, 2, 15201, 3 },
1688
  { 677, 1081, 152, 2, 15201, 3 },
1689
  { 896, 1081, 152, 2, 15201, 3 },
1690
  { 1112, 1081, 152, 2, 15201, 3 },
1691
  { 1328, 1081, 152, 2, 15201, 3 },
1692
  { 1540, 1081, 152, 2, 15201, 3 },
1693
  { 1752, 1081, 152, 2, 15201, 3 },
1694
  { 1964, 1081, 152, 2, 15201, 3 },
1695
  { 2176, 1081, 152, 2, 15201, 3 },
1696
  { 185, 1081, 152, 2, 15201, 3 },
1697
  { 474, 1081, 152, 2, 15201, 3 },
1698
  { 259, 8, 387, 4, 15233, 0 },
1699
  { 537, 8, 85, 4, 15233, 0 },
1700
  { 754, 8, 85, 4, 15233, 0 },
1701
  { 971, 8, 85, 4, 15233, 0 },
1702
  { 1187, 8, 85, 4, 15233, 0 },
1703
  { 1403, 8, 85, 4, 15233, 0 },
1704
  { 1615, 8, 85, 4, 15233, 0 },
1705
  { 1827, 8, 85, 4, 15233, 0 },
1706
  { 2039, 8, 85, 4, 15233, 0 },
1707
  { 2243, 8, 85, 4, 15233, 0 },
1708
  { 45, 8, 85, 4, 15233, 0 },
1709
  { 332, 8, 85, 4, 15233, 0 },
1710
  { 610, 8, 85, 4, 15233, 0 },
1711
  { 828, 8, 85, 4, 15233, 0 },
1712
  { 1044, 8, 85, 4, 15233, 0 },
1713
  { 1260, 8, 85, 4, 15233, 0 },
1714
  { 1472, 8, 85, 4, 15233, 0 },
1715
  { 1684, 8, 85, 4, 15233, 0 },
1716
  { 1896, 8, 85, 4, 15233, 0 },
1717
  { 2108, 8, 85, 4, 15233, 0 },
1718
  { 117, 8, 85, 4, 15233, 0 },
1719
  { 406, 8, 85, 4, 15233, 0 },
1720
  { 685, 8, 85, 4, 15233, 0 },
1721
  { 904, 8, 85, 4, 15233, 0 },
1722
  { 1120, 8, 85, 4, 15233, 0 },
1723
  { 1336, 8, 85, 4, 15233, 0 },
1724
  { 1548, 8, 85, 4, 15233, 0 },
1725
  { 1760, 8, 85, 4, 15233, 0 },
1726
  { 1972, 8, 415, 4, 15233, 0 },
1727
  { 2184, 8, 396, 4, 15057, 0 },
1728
  { 193, 8, 33, 4, 15057, 0 },
1729
  { 266, 1275, 393, 5, 15169, 27 },
1730
  { 543, 1275, 111, 5, 15169, 27 },
1731
  { 760, 1275, 111, 5, 15169, 27 },
1732
  { 977, 1275, 111, 5, 15169, 27 },
1733
  { 1193, 1275, 111, 5, 15169, 27 },
1734
  { 1409, 1275, 111, 5, 15169, 27 },
1735
  { 1621, 1275, 111, 5, 15169, 27 },
1736
  { 1833, 1275, 111, 5, 15169, 27 },
1737
  { 2045, 1275, 111, 5, 15169, 27 },
1738
  { 2249, 1275, 111, 5, 15169, 27 },
1739
  { 52, 1275, 111, 5, 15169, 27 },
1740
  { 340, 1275, 111, 5, 15169, 27 },
1741
  { 618, 1275, 111, 5, 15169, 27 },
1742
  { 836, 1275, 111, 5, 15169, 27 },
1743
  { 1052, 1275, 111, 5, 15169, 27 },
1744
  { 1268, 1275, 111, 5, 15169, 27 },
1745
  { 1480, 1275, 111, 5, 15169, 27 },
1746
  { 1692, 1275, 111, 5, 15169, 27 },
1747
  { 1904, 1275, 111, 5, 15169, 27 },
1748
  { 2116, 1275, 111, 5, 15169, 27 },
1749
  { 125, 1275, 111, 5, 15169, 27 },
1750
  { 414, 1275, 111, 5, 15169, 27 },
1751
  { 693, 1275, 111, 5, 15169, 27 },
1752
  { 912, 1275, 111, 5, 15169, 27 },
1753
  { 1128, 1275, 111, 5, 15169, 27 },
1754
  { 1344, 1275, 111, 5, 15169, 27 },
1755
  { 1556, 1275, 111, 5, 15169, 27 },
1756
  { 1768, 1275, 111, 5, 15169, 27 },
1757
  { 1980, 1275, 421, 5, 15169, 27 },
1758
  { 281, 880, 268, 10, 8929, 35 },
1759
  { 557, 880, 350, 10, 8929, 35 },
1760
  { 773, 880, 492, 10, 8929, 35 },
1761
  { 989, 880, 204, 10, 8929, 35 },
1762
  { 1205, 880, 204, 10, 8929, 35 },
1763
  { 1421, 880, 204, 10, 8929, 35 },
1764
  { 1633, 880, 204, 10, 8929, 35 },
1765
  { 1845, 880, 204, 10, 8929, 35 },
1766
  { 2057, 880, 204, 10, 8929, 35 },
1767
  { 2261, 880, 204, 10, 8929, 35 },
1768
  { 65, 880, 204, 10, 8929, 35 },
1769
  { 354, 880, 204, 10, 8929, 35 },
1770
  { 633, 880, 204, 10, 8929, 35 },
1771
  { 852, 880, 204, 10, 8929, 35 },
1772
  { 1068, 880, 204, 10, 8929, 35 },
1773
  { 1284, 880, 204, 10, 8929, 35 },
1774
  { 1496, 880, 204, 10, 8929, 35 },
1775
  { 1708, 880, 204, 10, 8929, 35 },
1776
  { 1920, 880, 204, 10, 8929, 35 },
1777
  { 2132, 880, 204, 10, 8929, 35 },
1778
  { 141, 880, 204, 10, 8929, 35 },
1779
  { 430, 880, 204, 10, 8929, 35 },
1780
  { 709, 880, 204, 10, 8929, 35 },
1781
  { 928, 880, 204, 10, 8929, 35 },
1782
  { 1144, 880, 204, 10, 8929, 35 },
1783
  { 1360, 880, 204, 10, 8929, 35 },
1784
  { 1572, 880, 204, 10, 8929, 35 },
1785
  { 1784, 880, 204, 10, 8929, 35 },
1786
  { 1996, 880, 204, 10, 8929, 35 },
1787
  { 2200, 880, 204, 10, 8929, 35 },
1788
  { 209, 880, 204, 10, 8929, 35 },
1789
  { 490, 880, 204, 10, 8929, 35 },
1790
  { 2285, 8, 267, 4, 15137, 0 },
1791
  { 2312, 8, 349, 4, 15137, 0 },
1792
  { 2332, 8, 491, 4, 15137, 0 },
1793
  { 2352, 8, 203, 4, 15137, 0 },
1794
  { 2372, 8, 203, 4, 15137, 0 },
1795
  { 2392, 8, 203, 4, 15137, 0 },
1796
  { 2412, 8, 203, 4, 15137, 0 },
1797
  { 2432, 8, 203, 4, 15137, 0 },
1798
  { 2452, 8, 203, 4, 15137, 0 },
1799
  { 2472, 8, 203, 4, 15137, 0 },
1800
  { 2264, 8, 203, 4, 15137, 0 },
1801
  { 2291, 8, 203, 4, 15137, 0 },
1802
  { 2318, 8, 203, 4, 15137, 0 },
1803
  { 2338, 8, 203, 4, 15137, 0 },
1804
  { 2358, 8, 203, 4, 15137, 0 },
1805
  { 2378, 8, 203, 4, 15137, 0 },
1806
  { 2398, 8, 203, 4, 15137, 0 },
1807
  { 2418, 8, 203, 4, 15137, 0 },
1808
  { 2438, 8, 203, 4, 15137, 0 },
1809
  { 2458, 8, 203, 4, 15137, 0 },
1810
  { 2271, 8, 203, 4, 15137, 0 },
1811
  { 2298, 8, 203, 4, 15137, 0 },
1812
  { 2325, 8, 203, 4, 15137, 0 },
1813
  { 2345, 8, 203, 4, 15137, 0 },
1814
  { 2365, 8, 203, 4, 15137, 0 },
1815
  { 2385, 8, 203, 4, 15137, 0 },
1816
  { 2405, 8, 203, 4, 15137, 0 },
1817
  { 2425, 8, 203, 4, 15137, 0 },
1818
  { 2445, 8, 203, 4, 15137, 0 },
1819
  { 2465, 8, 203, 4, 15137, 0 },
1820
  { 2278, 8, 203, 4, 15137, 0 },
1821
  { 2305, 8, 203, 4, 15137, 0 },
1822
  { 505, 1084, 360, 17, 2353, 61 },
1823
  { 723, 1084, 513, 17, 2353, 61 },
1824
  { 941, 1084, 278, 17, 2353, 61 },
1825
  { 1157, 1084, 278, 17, 2353, 61 },
1826
  { 1373, 1084, 278, 17, 2353, 61 },
1827
  { 1585, 1084, 278, 17, 2353, 61 },
1828
  { 1797, 1084, 278, 17, 2353, 61 },
1829
  { 2009, 1084, 278, 17, 2353, 61 },
1830
  { 2213, 1084, 278, 17, 2353, 61 },
1831
  { 10, 1084, 278, 17, 2353, 61 },
1832
  { 294, 1084, 278, 17, 2353, 61 },
1833
  { 571, 1084, 278, 17, 2353, 61 },
1834
  { 788, 1084, 278, 17, 2353, 61 },
1835
  { 1004, 1084, 278, 17, 2353, 61 },
1836
  { 1220, 1084, 278, 17, 2353, 61 },
1837
  { 1436, 1084, 278, 17, 2353, 61 },
1838
  { 1648, 1084, 278, 17, 2353, 61 },
1839
  { 1860, 1084, 278, 17, 2353, 61 },
1840
  { 2072, 1084, 278, 17, 2353, 61 },
1841
  { 81, 1084, 278, 17, 2353, 61 },
1842
  { 370, 1084, 278, 17, 2353, 61 },
1843
  { 649, 1084, 278, 17, 2353, 61 },
1844
  { 868, 1084, 278, 17, 2353, 61 },
1845
  { 1084, 1084, 278, 17, 2353, 61 },
1846
  { 1300, 1084, 278, 17, 2353, 61 },
1847
  { 1512, 1084, 278, 17, 2353, 61 },
1848
  { 1724, 1084, 278, 17, 2353, 61 },
1849
  { 1936, 1084, 278, 17, 2353, 61 },
1850
  { 2148, 1084, 278, 17, 2353, 61 },
1851
  { 157, 1084, 278, 17, 2353, 61 },
1852
  { 446, 1084, 278, 17, 2353, 61 },
1853
  { 224, 1075, 278, 17, 8496, 2 },
1854
  { 935, 1216, 872, 41, 225, 68 },
1855
  { 1151, 1216, 872, 41, 225, 68 },
1856
  { 1367, 1216, 872, 41, 225, 68 },
1857
  { 1579, 1216, 872, 41, 225, 68 },
1858
  { 1791, 1216, 872, 41, 225, 68 },
1859
  { 2003, 1216, 872, 41, 225, 68 },
1860
  { 2207, 1216, 872, 41, 225, 68 },
1861
  { 4, 1216, 872, 41, 225, 68 },
1862
  { 288, 1216, 872, 41, 225, 68 },
1863
  { 564, 1216, 872, 41, 225, 68 },
1864
  { 780, 1216, 872, 41, 225, 68 },
1865
  { 996, 1216, 872, 41, 225, 68 },
1866
  { 1212, 1216, 872, 41, 225, 68 },
1867
  { 1428, 1216, 872, 41, 225, 68 },
1868
  { 1640, 1216, 872, 41, 225, 68 },
1869
  { 1852, 1216, 872, 41, 225, 68 },
1870
  { 2064, 1216, 872, 41, 225, 68 },
1871
  { 73, 1216, 872, 41, 225, 68 },
1872
  { 362, 1216, 872, 41, 225, 68 },
1873
  { 641, 1216, 872, 41, 225, 68 },
1874
  { 860, 1216, 872, 41, 225, 68 },
1875
  { 1076, 1216, 872, 41, 225, 68 },
1876
  { 1292, 1216, 872, 41, 225, 68 },
1877
  { 1504, 1216, 872, 41, 225, 68 },
1878
  { 1716, 1216, 872, 41, 225, 68 },
1879
  { 1928, 1216, 872, 41, 225, 68 },
1880
  { 2140, 1216, 872, 41, 225, 68 },
1881
  { 149, 1216, 872, 41, 225, 68 },
1882
  { 438, 1216, 872, 41, 225, 68 },
1883
  { 216, 1238, 872, 41, 304, 73 },
1884
  { 497, 1051, 872, 41, 864, 59 },
1885
  { 716, 1194, 872, 41, 6784, 5 },
1886
  { 720, 96, 539, 26, 801, 74 },
1887
  { 938, 96, 378, 26, 801, 74 },
1888
  { 1154, 96, 378, 26, 801, 74 },
1889
  { 1370, 96, 378, 26, 801, 74 },
1890
  { 1582, 96, 378, 26, 801, 74 },
1891
  { 1794, 96, 378, 26, 801, 74 },
1892
  { 2006, 96, 378, 26, 801, 74 },
1893
  { 2210, 96, 378, 26, 801, 74 },
1894
  { 7, 96, 378, 26, 801, 74 },
1895
  { 291, 96, 378, 26, 801, 74 },
1896
  { 567, 96, 378, 26, 801, 74 },
1897
  { 784, 96, 378, 26, 801, 74 },
1898
  { 1000, 96, 378, 26, 801, 74 },
1899
  { 1216, 96, 378, 26, 801, 74 },
1900
  { 1432, 96, 378, 26, 801, 74 },
1901
  { 1644, 96, 378, 26, 801, 74 },
1902
  { 1856, 96, 378, 26, 801, 74 },
1903
  { 2068, 96, 378, 26, 801, 74 },
1904
  { 77, 96, 378, 26, 801, 74 },
1905
  { 366, 96, 378, 26, 801, 74 },
1906
  { 645, 96, 378, 26, 801, 74 },
1907
  { 864, 96, 378, 26, 801, 74 },
1908
  { 1080, 96, 378, 26, 801, 74 },
1909
  { 1296, 96, 378, 26, 801, 74 },
1910
  { 1508, 96, 378, 26, 801, 74 },
1911
  { 1720, 96, 378, 26, 801, 74 },
1912
  { 1932, 96, 378, 26, 801, 74 },
1913
  { 2144, 96, 378, 26, 801, 74 },
1914
  { 153, 96, 378, 26, 801, 74 },
1915
  { 442, 96, 378, 26, 801, 74 },
1916
  { 220, 114, 378, 26, 1088, 64 },
1917
  { 501, 1262, 378, 26, 8032, 10 },
1918
  { 525, 887, 366, 63, 2257, 80 },
1919
  { 742, 887, 519, 63, 2257, 80 },
1920
  { 959, 887, 284, 63, 2257, 80 },
1921
  { 1175, 887, 284, 63, 2257, 80 },
1922
  { 1391, 887, 284, 63, 2257, 80 },
1923
  { 1603, 887, 284, 63, 2257, 80 },
1924
  { 1815, 887, 284, 63, 2257, 80 },
1925
  { 2027, 887, 284, 63, 2257, 80 },
1926
  { 2231, 887, 284, 63, 2257, 80 },
1927
  { 31, 887, 284, 63, 2257, 80 },
1928
  { 316, 887, 284, 63, 2257, 80 },
1929
  { 594, 887, 284, 63, 2257, 80 },
1930
  { 812, 887, 284, 63, 2257, 80 },
1931
  { 1028, 887, 284, 63, 2257, 80 },
1932
  { 1244, 887, 284, 63, 2257, 80 },
1933
  { 1456, 887, 284, 63, 2257, 80 },
1934
  { 1668, 887, 284, 63, 2257, 80 },
1935
  { 1880, 887, 284, 63, 2257, 80 },
1936
  { 2092, 887, 284, 63, 2257, 80 },
1937
  { 101, 887, 284, 63, 2257, 80 },
1938
  { 390, 887, 284, 63, 2257, 80 },
1939
  { 669, 887, 284, 63, 2257, 80 },
1940
  { 888, 887, 284, 63, 2257, 80 },
1941
  { 1104, 887, 284, 63, 2257, 80 },
1942
  { 1320, 887, 284, 63, 2257, 80 },
1943
  { 1532, 887, 284, 63, 2257, 80 },
1944
  { 1744, 887, 284, 63, 2257, 80 },
1945
  { 1956, 887, 284, 63, 2257, 80 },
1946
  { 2168, 887, 284, 63, 2257, 80 },
1947
  { 177, 887, 284, 63, 2257, 80 },
1948
  { 466, 887, 284, 63, 2257, 80 },
1949
  { 245, 923, 284, 63, 8496, 14 },
1950
  { 953, 1130, 873, 96, 145, 87 },
1951
  { 1169, 1130, 873, 96, 145, 87 },
1952
  { 1385, 1130, 873, 96, 145, 87 },
1953
  { 1597, 1130, 873, 96, 145, 87 },
1954
  { 1809, 1130, 873, 96, 145, 87 },
1955
  { 2021, 1130, 873, 96, 145, 87 },
1956
  { 2225, 1130, 873, 96, 145, 87 },
1957
  { 25, 1130, 873, 96, 145, 87 },
1958
  { 310, 1130, 873, 96, 145, 87 },
1959
  { 587, 1130, 873, 96, 145, 87 },
1960
  { 804, 1130, 873, 96, 145, 87 },
1961
  { 1020, 1130, 873, 96, 145, 87 },
1962
  { 1236, 1130, 873, 96, 145, 87 },
1963
  { 1448, 1130, 873, 96, 145, 87 },
1964
  { 1660, 1130, 873, 96, 145, 87 },
1965
  { 1872, 1130, 873, 96, 145, 87 },
1966
  { 2084, 1130, 873, 96, 145, 87 },
1967
  { 93, 1130, 873, 96, 145, 87 },
1968
  { 382, 1130, 873, 96, 145, 87 },
1969
  { 661, 1130, 873, 96, 145, 87 },
1970
  { 880, 1130, 873, 96, 145, 87 },
1971
  { 1096, 1130, 873, 96, 145, 87 },
1972
  { 1312, 1130, 873, 96, 145, 87 },
1973
  { 1524, 1130, 873, 96, 145, 87 },
1974
  { 1736, 1130, 873, 96, 145, 87 },
1975
  { 1948, 1130, 873, 96, 145, 87 },
1976
  { 2160, 1130, 873, 96, 145, 87 },
1977
  { 169, 1130, 873, 96, 145, 87 },
1978
  { 458, 1130, 873, 96, 145, 87 },
1979
  { 237, 1162, 873, 96, 304, 92 },
1980
  { 517, 1019, 873, 96, 864, 78 },
1981
  { 735, 1098, 873, 96, 6784, 17 },
1982
  { 739, 956, 542, 75, 737, 93 },
1983
  { 956, 956, 381, 75, 737, 93 },
1984
  { 1172, 956, 381, 75, 737, 93 },
1985
  { 1388, 956, 381, 75, 737, 93 },
1986
  { 1600, 956, 381, 75, 737, 93 },
1987
  { 1812, 956, 381, 75, 737, 93 },
1988
  { 2024, 956, 381, 75, 737, 93 },
1989
  { 2228, 956, 381, 75, 737, 93 },
1990
  { 28, 956, 381, 75, 737, 93 },
1991
  { 313, 956, 381, 75, 737, 93 },
1992
  { 590, 956, 381, 75, 737, 93 },
1993
  { 808, 956, 381, 75, 737, 93 },
1994
  { 1024, 956, 381, 75, 737, 93 },
1995
  { 1240, 956, 381, 75, 737, 93 },
1996
  { 1452, 956, 381, 75, 737, 93 },
1997
  { 1664, 956, 381, 75, 737, 93 },
1998
  { 1876, 956, 381, 75, 737, 93 },
1999
  { 2088, 956, 381, 75, 737, 93 },
2000
  { 97, 956, 381, 75, 737, 93 },
2001
  { 386, 956, 381, 75, 737, 93 },
2002
  { 665, 956, 381, 75, 737, 93 },
2003
  { 884, 956, 381, 75, 737, 93 },
2004
  { 1100, 956, 381, 75, 737, 93 },
2005
  { 1316, 956, 381, 75, 737, 93 },
2006
  { 1528, 956, 381, 75, 737, 93 },
2007
  { 1740, 956, 381, 75, 737, 93 },
2008
  { 1952, 956, 381, 75, 737, 93 },
2009
  { 2164, 956, 381, 75, 737, 93 },
2010
  { 173, 956, 381, 75, 737, 93 },
2011
  { 462, 956, 381, 75, 737, 93 },
2012
  { 241, 977, 381, 75, 1088, 83 },
2013
  { 521, 998, 381, 75, 8032, 22 },
2014
  { 255, 875, 550, 7, 8832, 32 },
2015
  { 2499, 943, 548, 7, 6432, 32 },
2016
  { 534, 144, 550, 7, 2209, 32 },
2017
  { 751, 144, 550, 7, 2209, 32 },
2018
  { 968, 144, 550, 7, 2209, 32 },
2019
  { 1184, 144, 550, 7, 2209, 32 },
2020
  { 1400, 144, 550, 7, 2209, 32 },
2021
  { 1612, 144, 550, 7, 2209, 32 },
2022
  { 1824, 144, 550, 7, 2209, 32 },
2023
  { 2036, 144, 550, 7, 2209, 32 },
2024
  { 2240, 144, 550, 7, 2209, 32 },
2025
  { 42, 144, 550, 7, 2209, 32 },
2026
  { 328, 144, 550, 7, 2209, 32 },
2027
  { 606, 144, 550, 7, 2209, 32 },
2028
  { 824, 144, 550, 7, 2209, 32 },
2029
  { 1040, 144, 550, 7, 2209, 32 },
2030
  { 1256, 144, 550, 7, 2209, 32 },
2031
  { 1468, 144, 550, 7, 2209, 32 },
2032
  { 1680, 144, 550, 7, 2209, 32 },
2033
  { 1892, 144, 550, 7, 2209, 32 },
2034
  { 2104, 144, 550, 7, 2209, 32 },
2035
  { 113, 144, 550, 7, 2209, 32 },
2036
  { 402, 144, 550, 7, 2209, 32 },
2037
  { 681, 144, 550, 7, 2209, 32 },
2038
  { 900, 144, 550, 7, 2209, 32 },
2039
  { 1116, 144, 550, 7, 2209, 32 },
2040
  { 1332, 144, 550, 7, 2209, 32 },
2041
  { 1544, 144, 550, 7, 2209, 32 },
2042
  { 1756, 144, 550, 7, 2209, 32 },
2043
  { 1968, 144, 550, 7, 2209, 32 },
2044
  { 2180, 144, 413, 7, 8976, 29 },
2045
  { 189, 144, 7, 7, 96, 32 },
2046
  { 2493, 905, 8, 128, 96, 97 },
2047
  { 2507, 935, 8, 128, 6529, 97 },
2048
  { 262, 899, 8, 128, 8883, 97 },
2049
  { 2478, 911, 8, 128, 8976, 26 },
2050
  { 540, 917, 8, 128, 2161, 97 },
2051
  { 757, 917, 8, 128, 2161, 97 },
2052
  { 974, 917, 8, 128, 2161, 97 },
2053
  { 1190, 917, 8, 128, 2161, 97 },
2054
  { 1406, 917, 8, 128, 2161, 97 },
2055
  { 1618, 917, 8, 128, 2161, 97 },
2056
  { 1830, 917, 8, 128, 2161, 97 },
2057
  { 2042, 917, 8, 128, 2161, 97 },
2058
  { 2246, 917, 8, 128, 2161, 97 },
2059
  { 49, 917, 8, 128, 2161, 97 },
2060
  { 336, 917, 8, 128, 2161, 97 },
2061
  { 614, 917, 8, 128, 2161, 97 },
2062
  { 832, 917, 8, 128, 2161, 97 },
2063
  { 1048, 917, 8, 128, 2161, 97 },
2064
  { 1264, 917, 8, 128, 2161, 97 },
2065
  { 1476, 917, 8, 128, 2161, 97 },
2066
  { 1688, 917, 8, 128, 2161, 97 },
2067
  { 1900, 917, 8, 128, 2161, 97 },
2068
  { 2112, 917, 8, 128, 2161, 97 },
2069
  { 121, 917, 8, 128, 2161, 97 },
2070
  { 410, 917, 8, 128, 2161, 97 },
2071
  { 689, 917, 8, 128, 2161, 97 },
2072
  { 908, 917, 8, 128, 2161, 97 },
2073
  { 1124, 917, 8, 128, 2161, 97 },
2074
  { 1340, 917, 8, 128, 2161, 97 },
2075
  { 1552, 917, 8, 128, 2161, 97 },
2076
  { 1764, 917, 8, 128, 2161, 97 },
2077
  { 1976, 917, 8, 128, 2161, 97 },
2078
  { 554, 564, 372, 134, 1457, 100 },
2079
  { 770, 564, 525, 134, 1457, 100 },
2080
  { 986, 564, 290, 134, 1457, 100 },
2081
  { 1202, 564, 290, 134, 1457, 100 },
2082
  { 1418, 564, 290, 134, 1457, 100 },
2083
  { 1630, 564, 290, 134, 1457, 100 },
2084
  { 1842, 564, 290, 134, 1457, 100 },
2085
  { 2054, 564, 290, 134, 1457, 100 },
2086
  { 2258, 564, 290, 134, 1457, 100 },
2087
  { 62, 564, 290, 134, 1457, 100 },
2088
  { 350, 564, 290, 134, 1457, 100 },
2089
  { 629, 564, 290, 134, 1457, 100 },
2090
  { 848, 564, 290, 134, 1457, 100 },
2091
  { 1064, 564, 290, 134, 1457, 100 },
2092
  { 1280, 564, 290, 134, 1457, 100 },
2093
  { 1492, 564, 290, 134, 1457, 100 },
2094
  { 1704, 564, 290, 134, 1457, 100 },
2095
  { 1916, 564, 290, 134, 1457, 100 },
2096
  { 2128, 564, 290, 134, 1457, 100 },
2097
  { 137, 564, 290, 134, 1457, 100 },
2098
  { 426, 564, 290, 134, 1457, 100 },
2099
  { 705, 564, 290, 134, 1457, 100 },
2100
  { 924, 564, 290, 134, 1457, 100 },
2101
  { 1140, 564, 290, 134, 1457, 100 },
2102
  { 1356, 564, 290, 134, 1457, 100 },
2103
  { 1568, 564, 290, 134, 1457, 100 },
2104
  { 1780, 564, 290, 134, 1457, 100 },
2105
  { 1992, 564, 290, 134, 1457, 100 },
2106
  { 2196, 564, 290, 134, 1457, 100 },
2107
  { 205, 564, 290, 134, 1457, 100 },
2108
  { 486, 564, 290, 134, 1457, 100 },
2109
  { 277, 581, 290, 134, 8544, 38 },
2110
  { 980, 780, 8, 181, 1, 121 },
2111
  { 1196, 780, 8, 181, 1, 121 },
2112
  { 1412, 780, 8, 181, 1, 121 },
2113
  { 1624, 780, 8, 181, 1, 121 },
2114
  { 1836, 780, 8, 181, 1, 121 },
2115
  { 2048, 780, 8, 181, 1, 121 },
2116
  { 2252, 780, 8, 181, 1, 121 },
2117
  { 56, 780, 8, 181, 1, 121 },
2118
  { 344, 780, 8, 181, 1, 121 },
2119
  { 622, 780, 8, 181, 1, 121 },
2120
  { 840, 780, 8, 181, 1, 121 },
2121
  { 1056, 780, 8, 181, 1, 121 },
2122
  { 1272, 780, 8, 181, 1, 121 },
2123
  { 1484, 780, 8, 181, 1, 121 },
2124
  { 1696, 780, 8, 181, 1, 121 },
2125
  { 1908, 780, 8, 181, 1, 121 },
2126
  { 2120, 780, 8, 181, 1, 121 },
2127
  { 129, 780, 8, 181, 1, 121 },
2128
  { 418, 780, 8, 181, 1, 121 },
2129
  { 697, 780, 8, 181, 1, 121 },
2130
  { 916, 780, 8, 181, 1, 121 },
2131
  { 1132, 780, 8, 181, 1, 121 },
2132
  { 1348, 780, 8, 181, 1, 121 },
2133
  { 1560, 780, 8, 181, 1, 121 },
2134
  { 1772, 780, 8, 181, 1, 121 },
2135
  { 1984, 780, 8, 181, 1, 121 },
2136
  { 2188, 780, 8, 181, 1, 121 },
2137
  { 197, 780, 8, 181, 1, 121 },
2138
  { 478, 780, 8, 181, 1, 121 },
2139
  { 269, 826, 8, 181, 384, 130 },
2140
  { 546, 688, 8, 181, 944, 105 },
2141
  { 763, 734, 8, 181, 6864, 43 },
2142
  { 767, 598, 545, 151, 625, 139 },
2143
  { 983, 598, 180, 151, 625, 139 },
2144
  { 1199, 598, 180, 151, 625, 139 },
2145
  { 1415, 598, 180, 151, 625, 139 },
2146
  { 1627, 598, 180, 151, 625, 139 },
2147
  { 1839, 598, 180, 151, 625, 139 },
2148
  { 2051, 598, 180, 151, 625, 139 },
2149
  { 2255, 598, 180, 151, 625, 139 },
2150
  { 59, 598, 180, 151, 625, 139 },
2151
  { 347, 598, 180, 151, 625, 139 },
2152
  { 625, 598, 180, 151, 625, 139 },
2153
  { 844, 598, 180, 151, 625, 139 },
2154
  { 1060, 598, 180, 151, 625, 139 },
2155
  { 1276, 598, 180, 151, 625, 139 },
2156
  { 1488, 598, 180, 151, 625, 139 },
2157
  { 1700, 598, 180, 151, 625, 139 },
2158
  { 1912, 598, 180, 151, 625, 139 },
2159
  { 2124, 598, 180, 151, 625, 139 },
2160
  { 133, 598, 180, 151, 625, 139 },
2161
  { 422, 598, 180, 151, 625, 139 },
2162
  { 701, 598, 180, 151, 625, 139 },
2163
  { 920, 598, 180, 151, 625, 139 },
2164
  { 1136, 598, 180, 151, 625, 139 },
2165
  { 1352, 598, 180, 151, 625, 139 },
2166
  { 1564, 598, 180, 151, 625, 139 },
2167
  { 1776, 598, 180, 151, 625, 139 },
2168
  { 1988, 598, 180, 151, 625, 139 },
2169
  { 2192, 598, 180, 151, 625, 139 },
2170
  { 201, 598, 180, 151, 625, 139 },
2171
  { 482, 598, 180, 151, 625, 139 },
2172
  { 273, 628, 180, 151, 1152, 114 },
2173
  { 550, 658, 180, 151, 8096, 52 },
2174
};
2175
2176
extern const MCPhysReg AArch64RegUnitRoots[][2] = {
2177
  { AArch64::FFR },
2178
  { AArch64::W29 },
2179
  { AArch64::W30 },
2180
  { AArch64::NZCV },
2181
  { AArch64::WSP },
2182
  { AArch64::WZR },
2183
  { AArch64::B0 },
2184
  { AArch64::B1 },
2185
  { AArch64::B2 },
2186
  { AArch64::B3 },
2187
  { AArch64::B4 },
2188
  { AArch64::B5 },
2189
  { AArch64::B6 },
2190
  { AArch64::B7 },
2191
  { AArch64::B8 },
2192
  { AArch64::B9 },
2193
  { AArch64::B10 },
2194
  { AArch64::B11 },
2195
  { AArch64::B12 },
2196
  { AArch64::B13 },
2197
  { AArch64::B14 },
2198
  { AArch64::B15 },
2199
  { AArch64::B16 },
2200
  { AArch64::B17 },
2201
  { AArch64::B18 },
2202
  { AArch64::B19 },
2203
  { AArch64::B20 },
2204
  { AArch64::B21 },
2205
  { AArch64::B22 },
2206
  { AArch64::B23 },
2207
  { AArch64::B24 },
2208
  { AArch64::B25 },
2209
  { AArch64::B26 },
2210
  { AArch64::B27 },
2211
  { AArch64::B28 },
2212
  { AArch64::B29 },
2213
  { AArch64::B30 },
2214
  { AArch64::B31 },
2215
  { AArch64::P0 },
2216
  { AArch64::P1 },
2217
  { AArch64::P2 },
2218
  { AArch64::P3 },
2219
  { AArch64::P4 },
2220
  { AArch64::P5 },
2221
  { AArch64::P6 },
2222
  { AArch64::P7 },
2223
  { AArch64::P8 },
2224
  { AArch64::P9 },
2225
  { AArch64::P10 },
2226
  { AArch64::P11 },
2227
  { AArch64::P12 },
2228
  { AArch64::P13 },
2229
  { AArch64::P14 },
2230
  { AArch64::P15 },
2231
  { AArch64::W0 },
2232
  { AArch64::W1 },
2233
  { AArch64::W2 },
2234
  { AArch64::W3 },
2235
  { AArch64::W4 },
2236
  { AArch64::W5 },
2237
  { AArch64::W6 },
2238
  { AArch64::W7 },
2239
  { AArch64::W8 },
2240
  { AArch64::W9 },
2241
  { AArch64::W10 },
2242
  { AArch64::W11 },
2243
  { AArch64::W12 },
2244
  { AArch64::W13 },
2245
  { AArch64::W14 },
2246
  { AArch64::W15 },
2247
  { AArch64::W16 },
2248
  { AArch64::W17 },
2249
  { AArch64::W18 },
2250
  { AArch64::W19 },
2251
  { AArch64::W20 },
2252
  { AArch64::W21 },
2253
  { AArch64::W22 },
2254
  { AArch64::W23 },
2255
  { AArch64::W24 },
2256
  { AArch64::W25 },
2257
  { AArch64::W26 },
2258
  { AArch64::W27 },
2259
  { AArch64::W28 },
2260
  { AArch64::Z0_HI },
2261
  { AArch64::Z1_HI },
2262
  { AArch64::Z2_HI },
2263
  { AArch64::Z3_HI },
2264
  { AArch64::Z4_HI },
2265
  { AArch64::Z5_HI },
2266
  { AArch64::Z6_HI },
2267
  { AArch64::Z7_HI },
2268
  { AArch64::Z8_HI },
2269
  { AArch64::Z9_HI },
2270
  { AArch64::Z10_HI },
2271
  { AArch64::Z11_HI },
2272
  { AArch64::Z12_HI },
2273
  { AArch64::Z13_HI },
2274
  { AArch64::Z14_HI },
2275
  { AArch64::Z15_HI },
2276
  { AArch64::Z16_HI },
2277
  { AArch64::Z17_HI },
2278
  { AArch64::Z18_HI },
2279
  { AArch64::Z19_HI },
2280
  { AArch64::Z20_HI },
2281
  { AArch64::Z21_HI },
2282
  { AArch64::Z22_HI },
2283
  { AArch64::Z23_HI },
2284
  { AArch64::Z24_HI },
2285
  { AArch64::Z25_HI },
2286
  { AArch64::Z26_HI },
2287
  { AArch64::Z27_HI },
2288
  { AArch64::Z28_HI },
2289
  { AArch64::Z29_HI },
2290
  { AArch64::Z30_HI },
2291
  { AArch64::Z31_HI },
2292
};
2293
2294
namespace {     // Register classes...
2295
  // FPR8 Register Class...
2296
  const MCPhysReg FPR8[] = {
2297
    AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, 
2298
  };
2299
2300
  // FPR8 Bit set.
2301
  const uint8_t FPR8Bits[] = {
2302
    0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2303
  };
2304
2305
  // FPR16 Register Class...
2306
  const MCPhysReg FPR16[] = {
2307
    AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, 
2308
  };
2309
2310
  // FPR16 Bit set.
2311
  const uint8_t FPR16Bits[] = {
2312
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2313
  };
2314
2315
  // PPR Register Class...
2316
  const MCPhysReg PPR[] = {
2317
    AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, 
2318
  };
2319
2320
  // PPR Bit set.
2321
  const uint8_t PPRBits[] = {
2322
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
2323
  };
2324
2325
  // PPR_3b Register Class...
2326
  const MCPhysReg PPR_3b[] = {
2327
    AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 
2328
  };
2329
2330
  // PPR_3b Bit set.
2331
  const uint8_t PPR_3bBits[] = {
2332
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
2333
  };
2334
2335
  // GPR32all Register Class...
2336
  const MCPhysReg GPR32all[] = {
2337
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP, 
2338
  };
2339
2340
  // GPR32all Bit set.
2341
  const uint8_t GPR32allBits[] = {
2342
    0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2343
  };
2344
2345
  // FPR32 Register Class...
2346
  const MCPhysReg FPR32[] = {
2347
    AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, 
2348
  };
2349
2350
  // FPR32 Bit set.
2351
  const uint8_t FPR32Bits[] = {
2352
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2353
  };
2354
2355
  // GPR32 Register Class...
2356
  const MCPhysReg GPR32[] = {
2357
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, 
2358
  };
2359
2360
  // GPR32 Bit set.
2361
  const uint8_t GPR32Bits[] = {
2362
    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2363
  };
2364
2365
  // GPR32sp Register Class...
2366
  const MCPhysReg GPR32sp[] = {
2367
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, 
2368
  };
2369
2370
  // GPR32sp Bit set.
2371
  const uint8_t GPR32spBits[] = {
2372
    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2373
  };
2374
2375
  // GPR32common Register Class...
2376
  const MCPhysReg GPR32common[] = {
2377
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, 
2378
  };
2379
2380
  // GPR32common Bit set.
2381
  const uint8_t GPR32commonBits[] = {
2382
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2383
  };
2384
2385
  // CCR Register Class...
2386
  const MCPhysReg CCR[] = {
2387
    AArch64::NZCV, 
2388
  };
2389
2390
  // CCR Bit set.
2391
  const uint8_t CCRBits[] = {
2392
    0x10, 
2393
  };
2394
2395
  // GPR32sponly Register Class...
2396
  const MCPhysReg GPR32sponly[] = {
2397
    AArch64::WSP, 
2398
  };
2399
2400
  // GPR32sponly Bit set.
2401
  const uint8_t GPR32sponlyBits[] = {
2402
    0x40, 
2403
  };
2404
2405
  // WSeqPairsClass Register Class...
2406
  const MCPhysReg WSeqPairsClass[] = {
2407
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, AArch64::WZR_W0, 
2408
  };
2409
2410
  // WSeqPairsClass Bit set.
2411
  const uint8_t WSeqPairsClassBits[] = {
2412
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2413
  };
2414
2415
  // WSeqPairsClass_with_sube32_in_GPR32common Register Class...
2416
  const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common[] = {
2417
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, 
2418
  };
2419
2420
  // WSeqPairsClass_with_sube32_in_GPR32common Bit set.
2421
  const uint8_t WSeqPairsClass_with_sube32_in_GPR32commonBits[] = {
2422
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, 
2423
  };
2424
2425
  // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
2426
  const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
2427
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::WZR_W0, 
2428
  };
2429
2430
  // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
2431
  const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
2432
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, 
2433
  };
2434
2435
  // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Register Class...
2436
  const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common[] = {
2437
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, 
2438
  };
2439
2440
  // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Bit set.
2441
  const uint8_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
2442
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 
2443
  };
2444
2445
  // GPR64all Register Class...
2446
  const MCPhysReg GPR64all[] = {
2447
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP, 
2448
  };
2449
2450
  // GPR64all Bit set.
2451
  const uint8_t GPR64allBits[] = {
2452
    0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2453
  };
2454
2455
  // FPR64 Register Class...
2456
  const MCPhysReg FPR64[] = {
2457
    AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 
2458
  };
2459
2460
  // FPR64 Bit set.
2461
  const uint8_t FPR64Bits[] = {
2462
    0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2463
  };
2464
2465
  // GPR64 Register Class...
2466
  const MCPhysReg GPR64[] = {
2467
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, 
2468
  };
2469
2470
  // GPR64 Bit set.
2471
  const uint8_t GPR64Bits[] = {
2472
    0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2473
  };
2474
2475
  // GPR64sp Register Class...
2476
  const MCPhysReg GPR64sp[] = {
2477
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, 
2478
  };
2479
2480
  // GPR64sp Bit set.
2481
  const uint8_t GPR64spBits[] = {
2482
    0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2483
  };
2484
2485
  // GPR64common Register Class...
2486
  const MCPhysReg GPR64common[] = {
2487
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, 
2488
  };
2489
2490
  // GPR64common Bit set.
2491
  const uint8_t GPR64commonBits[] = {
2492
    0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2493
  };
2494
2495
  // tcGPR64 Register Class...
2496
  const MCPhysReg tcGPR64[] = {
2497
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, 
2498
  };
2499
2500
  // tcGPR64 Bit set.
2501
  const uint8_t tcGPR64Bits[] = {
2502
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07, 
2503
  };
2504
2505
  // rtcGPR64 Register Class...
2506
  const MCPhysReg rtcGPR64[] = {
2507
    AArch64::X16, AArch64::X17, 
2508
  };
2509
2510
  // rtcGPR64 Bit set.
2511
  const uint8_t rtcGPR64Bits[] = {
2512
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 
2513
  };
2514
2515
  // GPR64sponly Register Class...
2516
  const MCPhysReg GPR64sponly[] = {
2517
    AArch64::SP, 
2518
  };
2519
2520
  // GPR64sponly Bit set.
2521
  const uint8_t GPR64sponlyBits[] = {
2522
    0x20, 
2523
  };
2524
2525
  // DD Register Class...
2526
  const MCPhysReg DD[] = {
2527
    AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0, 
2528
  };
2529
2530
  // DD Bit set.
2531
  const uint8_t DDBits[] = {
2532
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2533
  };
2534
2535
  // XSeqPairsClass Register Class...
2536
  const MCPhysReg XSeqPairsClass[] = {
2537
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, AArch64::XZR_X0, 
2538
  };
2539
2540
  // XSeqPairsClass Bit set.
2541
  const uint8_t XSeqPairsClassBits[] = {
2542
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2543
  };
2544
2545
  // XSeqPairsClass_with_sub_32_in_GPR32common Register Class...
2546
  const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common[] = {
2547
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, 
2548
  };
2549
2550
  // XSeqPairsClass_with_sub_32_in_GPR32common Bit set.
2551
  const uint8_t XSeqPairsClass_with_sub_32_in_GPR32commonBits[] = {
2552
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0xff, 0x1f, 
2553
  };
2554
2555
  // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
2556
  const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
2557
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::XZR_X0, 
2558
  };
2559
2560
  // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
2561
  const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
2562
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, 
2563
  };
2564
2565
  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Register Class...
2566
  const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common[] = {
2567
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, 
2568
  };
2569
2570
  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Bit set.
2571
  const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
2572
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0xff, 0xff, 0xff, 0x1f, 
2573
  };
2574
2575
  // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
2576
  const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
2577
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, 
2578
  };
2579
2580
  // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
2581
  const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
2582
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x0f, 
2583
  };
2584
2585
  // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
2586
  const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
2587
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::XZR_X0, 
2588
  };
2589
2590
  // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
2591
  const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
2592
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xfe, 0xff, 0x07, 
2593
  };
2594
2595
  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
2596
  const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64[] = {
2597
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, 
2598
  };
2599
2600
  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
2601
  const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
2602
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x07, 
2603
  };
2604
2605
  // XSeqPairsClass_with_sube64_in_rtcGPR64 Register Class...
2606
  const MCPhysReg XSeqPairsClass_with_sube64_in_rtcGPR64[] = {
2607
    AArch64::X16_X17, AArch64::X17_X18, 
2608
  };
2609
2610
  // XSeqPairsClass_with_sube64_in_rtcGPR64 Bit set.
2611
  const uint8_t XSeqPairsClass_with_sube64_in_rtcGPR64Bits[] = {
2612
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 
2613
  };
2614
2615
  // XSeqPairsClass_with_subo64_in_rtcGPR64 Register Class...
2616
  const MCPhysReg XSeqPairsClass_with_subo64_in_rtcGPR64[] = {
2617
    AArch64::X15_X16, AArch64::X16_X17, 
2618
  };
2619
2620
  // XSeqPairsClass_with_subo64_in_rtcGPR64 Bit set.
2621
  const uint8_t XSeqPairsClass_with_subo64_in_rtcGPR64Bits[] = {
2622
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 
2623
  };
2624
2625
  // XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64 Register Class...
2626
  const MCPhysReg XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64[] = {
2627
    AArch64::X16_X17, 
2628
  };
2629
2630
  // XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64 Bit set.
2631
  const uint8_t XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64Bits[] = {
2632
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
2633
  };
2634
2635
  // FPR128 Register Class...
2636
  const MCPhysReg FPR128[] = {
2637
    AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 
2638
  };
2639
2640
  // FPR128 Bit set.
2641
  const uint8_t FPR128Bits[] = {
2642
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2643
  };
2644
2645
  // ZPR Register Class...
2646
  const MCPhysReg ZPR[] = {
2647
    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31, 
2648
  };
2649
2650
  // ZPR Bit set.
2651
  const uint8_t ZPRBits[] = {
2652
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2653
  };
2654
2655
  // FPR128_lo Register Class...
2656
  const MCPhysReg FPR128_lo[] = {
2657
    AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, 
2658
  };
2659
2660
  // FPR128_lo Bit set.
2661
  const uint8_t FPR128_loBits[] = {
2662
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
2663
  };
2664
2665
  // ZPR_4b Register Class...
2666
  const MCPhysReg ZPR_4b[] = {
2667
    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 
2668
  };
2669
2670
  // ZPR_4b Bit set.
2671
  const uint8_t ZPR_4bBits[] = {
2672
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2673
  };
2674
2675
  // ZPR_3b Register Class...
2676
  const MCPhysReg ZPR_3b[] = {
2677
    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 
2678
  };
2679
2680
  // ZPR_3b Bit set.
2681
  const uint8_t ZPR_3bBits[] = {
2682
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2683
  };
2684
2685
  // DDD Register Class...
2686
  const MCPhysReg DDD[] = {
2687
    AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1, 
2688
  };
2689
2690
  // DDD Bit set.
2691
  const uint8_t DDDBits[] = {
2692
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2693
  };
2694
2695
  // DDDD Register Class...
2696
  const MCPhysReg DDDD[] = {
2697
    AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, 
2698
  };
2699
2700
  // DDDD Bit set.
2701
  const uint8_t DDDDBits[] = {
2702
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2703
  };
2704
2705
  // QQ Register Class...
2706
  const MCPhysReg QQ[] = {
2707
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0, 
2708
  };
2709
2710
  // QQ Bit set.
2711
  const uint8_t QQBits[] = {
2712
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2713
  };
2714
2715
  // ZPR2 Register Class...
2716
  const MCPhysReg ZPR2[] = {
2717
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0, 
2718
  };
2719
2720
  // ZPR2 Bit set.
2721
  const uint8_t ZPR2Bits[] = {
2722
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2723
  };
2724
2725
  // QQ_with_qsub0_in_FPR128_lo Register Class...
2726
  const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
2727
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 
2728
  };
2729
2730
  // QQ_with_qsub0_in_FPR128_lo Bit set.
2731
  const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
2732
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2733
  };
2734
2735
  // QQ_with_qsub1_in_FPR128_lo Register Class...
2736
  const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
2737
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0, 
2738
  };
2739
2740
  // QQ_with_qsub1_in_FPR128_lo Bit set.
2741
  const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
2742
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2743
  };
2744
2745
  // ZPR2_with_zsub1_in_ZPR_4b Register Class...
2746
  const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = {
2747
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z31_Z0, 
2748
  };
2749
2750
  // ZPR2_with_zsub1_in_ZPR_4b Bit set.
2751
  const uint8_t ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2752
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2753
  };
2754
2755
  // ZPR2_with_zsub_in_FPR128_lo Register Class...
2756
  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = {
2757
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 
2758
  };
2759
2760
  // ZPR2_with_zsub_in_FPR128_lo Bit set.
2761
  const uint8_t ZPR2_with_zsub_in_FPR128_loBits[] = {
2762
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2763
  };
2764
2765
  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
2766
  const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
2767
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, 
2768
  };
2769
2770
  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
2771
  const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
2772
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2773
  };
2774
2775
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Register Class...
2776
  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = {
2777
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, 
2778
  };
2779
2780
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Bit set.
2781
  const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2782
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2783
  };
2784
2785
  // ZPR2_with_zsub0_in_ZPR_3b Register Class...
2786
  const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = {
2787
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 
2788
  };
2789
2790
  // ZPR2_with_zsub0_in_ZPR_3b Bit set.
2791
  const uint8_t ZPR2_with_zsub0_in_ZPR_3bBits[] = {
2792
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2793
  };
2794
2795
  // ZPR2_with_zsub1_in_ZPR_3b Register Class...
2796
  const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = {
2797
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z31_Z0, 
2798
  };
2799
2800
  // ZPR2_with_zsub1_in_ZPR_3b Bit set.
2801
  const uint8_t ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2802
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
2803
  };
2804
2805
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Register Class...
2806
  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = {
2807
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, 
2808
  };
2809
2810
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Bit set.
2811
  const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2812
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
2813
  };
2814
2815
  // QQQ Register Class...
2816
  const MCPhysReg QQQ[] = {
2817
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
2818
  };
2819
2820
  // QQQ Bit set.
2821
  const uint8_t QQQBits[] = {
2822
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2823
  };
2824
2825
  // ZPR3 Register Class...
2826
  const MCPhysReg ZPR3[] = {
2827
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
2828
  };
2829
2830
  // ZPR3 Bit set.
2831
  const uint8_t ZPR3Bits[] = {
2832
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2833
  };
2834
2835
  // QQQ_with_qsub0_in_FPR128_lo Register Class...
2836
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
2837
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, 
2838
  };
2839
2840
  // QQQ_with_qsub0_in_FPR128_lo Bit set.
2841
  const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
2842
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2843
  };
2844
2845
  // QQQ_with_qsub1_in_FPR128_lo Register Class...
2846
  const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
2847
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1, 
2848
  };
2849
2850
  // QQQ_with_qsub1_in_FPR128_lo Bit set.
2851
  const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
2852
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2853
  };
2854
2855
  // QQQ_with_qsub2_in_FPR128_lo Register Class...
2856
  const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
2857
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
2858
  };
2859
2860
  // QQQ_with_qsub2_in_FPR128_lo Bit set.
2861
  const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
2862
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
2863
  };
2864
2865
  // ZPR3_with_zsub1_in_ZPR_4b Register Class...
2866
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = {
2867
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z31_Z0_Z1, 
2868
  };
2869
2870
  // ZPR3_with_zsub1_in_ZPR_4b Bit set.
2871
  const uint8_t ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2872
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2873
  };
2874
2875
  // ZPR3_with_zsub2_in_ZPR_4b Register Class...
2876
  const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = {
2877
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
2878
  };
2879
2880
  // ZPR3_with_zsub2_in_ZPR_4b Bit set.
2881
  const uint8_t ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2882
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
2883
  };
2884
2885
  // ZPR3_with_zsub_in_FPR128_lo Register Class...
2886
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = {
2887
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, 
2888
  };
2889
2890
  // ZPR3_with_zsub_in_FPR128_lo Bit set.
2891
  const uint8_t ZPR3_with_zsub_in_FPR128_loBits[] = {
2892
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2893
  };
2894
2895
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
2896
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
2897
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 
2898
  };
2899
2900
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
2901
  const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
2902
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2903
  };
2904
2905
  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2906
  const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2907
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1, 
2908
  };
2909
2910
  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2911
  const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2912
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
2913
  };
2914
2915
  // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2916
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2917
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z31_Z0_Z1, 
2918
  };
2919
2920
  // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2921
  const uint8_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2922
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
2923
  };
2924
2925
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Register Class...
2926
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = {
2927
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 
2928
  };
2929
2930
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Bit set.
2931
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2932
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2933
  };
2934
2935
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2936
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2937
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, 
2938
  };
2939
2940
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2941
  const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2942
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
2943
  };
2944
2945
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2946
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2947
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, 
2948
  };
2949
2950
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2951
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2952
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
2953
  };
2954
2955
  // ZPR3_with_zsub0_in_ZPR_3b Register Class...
2956
  const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = {
2957
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, 
2958
  };
2959
2960
  // ZPR3_with_zsub0_in_ZPR_3b Bit set.
2961
  const uint8_t ZPR3_with_zsub0_in_ZPR_3bBits[] = {
2962
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2963
  };
2964
2965
  // ZPR3_with_zsub1_in_ZPR_3b Register Class...
2966
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = {
2967
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z31_Z0_Z1, 
2968
  };
2969
2970
  // ZPR3_with_zsub1_in_ZPR_3b Bit set.
2971
  const uint8_t ZPR3_with_zsub1_in_ZPR_3bBits[] = {
2972
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
2973
  };
2974
2975
  // ZPR3_with_zsub2_in_ZPR_3b Register Class...
2976
  const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = {
2977
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
2978
  };
2979
2980
  // ZPR3_with_zsub2_in_ZPR_3b Bit set.
2981
  const uint8_t ZPR3_with_zsub2_in_ZPR_3bBits[] = {
2982
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, 
2983
  };
2984
2985
  // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
2986
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
2987
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z31_Z0_Z1, 
2988
  };
2989
2990
  // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
2991
  const uint8_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
2992
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, 
2993
  };
2994
2995
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Register Class...
2996
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = {
2997
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, 
2998
  };
2999
3000
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Bit set.
3001
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits[] = {
3002
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
3003
  };
3004
3005
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
3006
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
3007
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 
3008
  };
3009
3010
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
3011
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
3012
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 
3013
  };
3014
3015
  // QQQQ Register Class...
3016
  const MCPhysReg QQQQ[] = {
3017
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
3018
  };
3019
3020
  // QQQQ Bit set.
3021
  const uint8_t QQQQBits[] = {
3022
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
3023
  };
3024
3025
  // ZPR4 Register Class...
3026
  const MCPhysReg ZPR4[] = {
3027
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3028
  };
3029
3030
  // ZPR4 Bit set.
3031
  const uint8_t ZPR4Bits[] = {
3032
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
3033
  };
3034
3035
  // QQQQ_with_qsub0_in_FPR128_lo Register Class...
3036
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
3037
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, 
3038
  };
3039
3040
  // QQQQ_with_qsub0_in_FPR128_lo Bit set.
3041
  const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
3042
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
3043
  };
3044
3045
  // QQQQ_with_qsub1_in_FPR128_lo Register Class...
3046
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
3047
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2, 
3048
  };
3049
3050
  // QQQQ_with_qsub1_in_FPR128_lo Bit set.
3051
  const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
3052
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
3053
  };
3054
3055
  // QQQQ_with_qsub2_in_FPR128_lo Register Class...
3056
  const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
3057
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
3058
  };
3059
3060
  // QQQQ_with_qsub2_in_FPR128_lo Bit set.
3061
  const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
3062
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
3063
  };
3064
3065
  // QQQQ_with_qsub3_in_FPR128_lo Register Class...
3066
  const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
3067
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
3068
  };
3069
3070
  // QQQQ_with_qsub3_in_FPR128_lo Bit set.
3071
  const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
3072
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, 
3073
  };
3074
3075
  // ZPR4_with_zsub1_in_ZPR_4b Register Class...
3076
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = {
3077
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z31_Z0_Z1_Z2, 
3078
  };
3079
3080
  // ZPR4_with_zsub1_in_ZPR_4b Bit set.
3081
  const uint8_t ZPR4_with_zsub1_in_ZPR_4bBits[] = {
3082
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
3083
  };
3084
3085
  // ZPR4_with_zsub2_in_ZPR_4b Register Class...
3086
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = {
3087
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3088
  };
3089
3090
  // ZPR4_with_zsub2_in_ZPR_4b Bit set.
3091
  const uint8_t ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3092
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
3093
  };
3094
3095
  // ZPR4_with_zsub3_in_ZPR_4b Register Class...
3096
  const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = {
3097
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3098
  };
3099
3100
  // ZPR4_with_zsub3_in_ZPR_4b Bit set.
3101
  const uint8_t ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3102
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, 
3103
  };
3104
3105
  // ZPR4_with_zsub_in_FPR128_lo Register Class...
3106
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = {
3107
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, 
3108
  };
3109
3110
  // ZPR4_with_zsub_in_FPR128_lo Bit set.
3111
  const uint8_t ZPR4_with_zsub_in_FPR128_loBits[] = {
3112
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
3113
  };
3114
3115
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
3116
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
3117
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 
3118
  };
3119
3120
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
3121
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
3122
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
3123
  };
3124
3125
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
3126
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3127
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2, 
3128
  };
3129
3130
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
3131
  const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
3132
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
3133
  };
3134
3135
  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3136
  const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3137
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
3138
  };
3139
3140
  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3141
  const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3142
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, 
3143
  };
3144
3145
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
3146
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3147
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z31_Z0_Z1_Z2, 
3148
  };
3149
3150
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
3151
  const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3152
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
3153
  };
3154
3155
  // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3156
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3157
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3158
  };
3159
3160
  // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3161
  const uint8_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3162
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, 
3163
  };
3164
3165
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Register Class...
3166
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = {
3167
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 
3168
  };
3169
3170
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Bit set.
3171
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits[] = {
3172
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
3173
  };
3174
3175
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
3176
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3177
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, 
3178
  };
3179
3180
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
3181
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
3182
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
3183
  };
3184
3185
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3186
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3187
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2, 
3188
  };
3189
3190
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3191
  const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3192
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, 
3193
  };
3194
3195
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3196
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3197
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z31_Z0_Z1_Z2, 
3198
  };
3199
3200
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3201
  const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3202
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, 
3203
  };
3204
3205
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
3206
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3207
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, 
3208
  };
3209
3210
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
3211
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3212
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
3213
  };
3214
3215
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3216
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3217
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, 
3218
  };
3219
3220
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3221
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3222
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 
3223
  };
3224
3225
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3226
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3227
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, 
3228
  };
3229
3230
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3231
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3232
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 
3233
  };
3234
3235
  // ZPR4_with_zsub0_in_ZPR_3b Register Class...
3236
  const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = {
3237
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, 
3238
  };
3239
3240
  // ZPR4_with_zsub0_in_ZPR_3b Bit set.
3241
  const uint8_t ZPR4_with_zsub0_in_ZPR_3bBits[] = {
3242
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
3243
  };
3244
3245
  // ZPR4_with_zsub1_in_ZPR_3b Register Class...
3246
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = {
3247
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z31_Z0_Z1_Z2, 
3248
  };
3249
3250
  // ZPR4_with_zsub1_in_ZPR_3b Bit set.
3251
  const uint8_t ZPR4_with_zsub1_in_ZPR_3bBits[] = {
3252
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
3253
  };
3254
3255
  // ZPR4_with_zsub2_in_ZPR_3b Register Class...
3256
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = {
3257
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3258
  };
3259
3260
  // ZPR4_with_zsub2_in_ZPR_3b Bit set.
3261
  const uint8_t ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3262
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, 
3263
  };
3264
3265
  // ZPR4_with_zsub3_in_ZPR_3b Register Class...
3266
  const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = {
3267
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3268
  };
3269
3270
  // ZPR4_with_zsub3_in_ZPR_3b Bit set.
3271
  const uint8_t ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3272
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x1c, 
3273
  };
3274
3275
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
3276
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3277
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z31_Z0_Z1_Z2, 
3278
  };
3279
3280
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
3281
  const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3282
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, 
3283
  };
3284
3285
  // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3286
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3287
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3288
  };
3289
3290
  // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3291
  const uint8_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3292
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x18, 
3293
  };
3294
3295
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Register Class...
3296
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = {
3297
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, 
3298
  };
3299
3300
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Bit set.
3301
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits[] = {
3302
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
3303
  };
3304
3305
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3306
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3307
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z31_Z0_Z1_Z2, 
3308
  };
3309
3310
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3311
  const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3312
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x10, 
3313
  };
3314
3315
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
3316
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3317
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 
3318
  };
3319
3320
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
3321
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3322
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 
3323
  };
3324
3325
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3326
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3327
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, 
3328
  };
3329
3330
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3331
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3332
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 
3333
  };
3334
3335
} // end anonymous namespace
3336
3337
extern const char AArch64RegClassStrings[] = {
3338
  /* 0 */ 'F', 'P', 'R', '3', '2', 0,
3339
  /* 6 */ 'G', 'P', 'R', '3', '2', 0,
3340
  /* 12 */ 'Z', 'P', 'R', '2', 0,
3341
  /* 17 */ 'Z', 'P', 'R', '3', 0,
3342
  /* 22 */ 'F', 'P', 'R', '6', '4', 0,
3343
  /* 28 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3344
  /* 66 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3345
  /* 150 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 'r', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3346
  /* 189 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 'r', 't', 'c', 'G', 'P', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'r', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3347
  /* 271 */ 'Z', 'P', 'R', '4', 0,
3348
  /* 276 */ 'F', 'P', 'R', '1', '6', 0,
3349
  /* 282 */ 'F', 'P', 'R', '1', '2', '8', 0,
3350
  /* 289 */ 'F', 'P', 'R', '8', 0,
3351
  /* 294 */ 'D', 'D', 'D', 'D', 0,
3352
  /* 299 */ 'Q', 'Q', 'Q', 'Q', 0,
3353
  /* 304 */ 'C', 'C', 'R', 0,
3354
  /* 308 */ 'P', 'P', 'R', 0,
3355
  /* 312 */ 'Z', 'P', 'R', 0,
3356
  /* 316 */ 'P', 'P', 'R', '_', '3', 'b', 0,
3357
  /* 323 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3358
  /* 349 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3359
  /* 375 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3360
  /* 401 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3361
  /* 459 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3362
  /* 517 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3363
  /* 575 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3364
  /* 631 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3365
  /* 689 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3366
  /* 745 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3367
  /* 803 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3368
  /* 859 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3369
  /* 915 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3370
  /* 973 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3371
  /* 1031 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3372
  /* 1089 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3373
  /* 1147 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3374
  /* 1203 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3375
  /* 1261 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3376
  /* 1317 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3377
  /* 1375 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3378
  /* 1431 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3379
  /* 1487 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3380
  /* 1545 */ 'G', 'P', 'R', '3', '2', 'a', 'l', 'l', 0,
3381
  /* 1554 */ 'G', 'P', 'R', '6', '4', 'a', 'l', 'l', 0,
3382
  /* 1563 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3383
  /* 1605 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3384
  /* 1647 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3385
  /* 1735 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3386
  /* 1823 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3387
  /* 1852 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3388
  /* 1914 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3389
  /* 1974 */ 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3390
  /* 2032 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3391
  /* 2094 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3392
  /* 2156 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3393
  /* 2216 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3394
  /* 2276 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3395
  /* 2338 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3396
  /* 2400 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3397
  /* 2462 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3398
  /* 2490 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3399
  /* 2518 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3400
  /* 2546 */ 'G', 'P', 'R', '3', '2', 's', 'p', 0,
3401
  /* 2554 */ 'G', 'P', 'R', '6', '4', 's', 'p', 0,
3402
  /* 2562 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
3403
  /* 2577 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
3404
  /* 2592 */ 'G', 'P', 'R', '3', '2', 's', 'p', 'o', 'n', 'l', 'y', 0,
3405
  /* 2604 */ 'G', 'P', 'R', '6', '4', 's', 'p', 'o', 'n', 'l', 'y', 0,
3406
};
3407
3408
extern const MCRegisterClass AArch64MCRegisterClasses[] = {
3409
  { FPR8, FPR8Bits, 289, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, true },
3410
  { FPR16, FPR16Bits, 276, 32, sizeof(FPR16Bits), AArch64::FPR16RegClassID, 1, true },
3411
  { PPR, PPRBits, 308, 16, sizeof(PPRBits), AArch64::PPRRegClassID, 1, true },
3412
  { PPR_3b, PPR_3bBits, 316, 8, sizeof(PPR_3bBits), AArch64::PPR_3bRegClassID, 1, true },
3413
  { GPR32all, GPR32allBits, 1545, 33, sizeof(GPR32allBits), AArch64::GPR32allRegClassID, 1, true },
3414
  { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64::FPR32RegClassID, 1, true },
3415
  { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 1, true },
3416
  { GPR32sp, GPR32spBits, 2546, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 1, true },
3417
  { GPR32common, GPR32commonBits, 1593, 31, sizeof(GPR32commonBits), AArch64::GPR32commonRegClassID, 1, true },
3418
  { CCR, CCRBits, 304, 1, sizeof(CCRBits), AArch64::CCRRegClassID, -1, false },
3419
  { GPR32sponly, GPR32sponlyBits, 2592, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 1, true },
3420
  { WSeqPairsClass, WSeqPairsClassBits, 2562, 32, sizeof(WSeqPairsClassBits), AArch64::WSeqPairsClassRegClassID, 1, true },
3421
  { WSeqPairsClass_with_sube32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32commonBits, 1605, 31, sizeof(WSeqPairsClass_with_sube32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClassID, 1, true },
3422
  { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, 1693, 31, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 1, true },
3423
  { WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits, 1647, 30, sizeof(WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 1, true },
3424
  { GPR64all, GPR64allBits, 1554, 33, sizeof(GPR64allBits), AArch64::GPR64allRegClassID, 1, true },
3425
  { FPR64, FPR64Bits, 22, 32, sizeof(FPR64Bits), AArch64::FPR64RegClassID, 1, true },
3426
  { GPR64, GPR64Bits, 60, 32, sizeof(GPR64Bits), AArch64::GPR64RegClassID, 1, true },
3427
  { GPR64sp, GPR64spBits, 2554, 32, sizeof(GPR64spBits), AArch64::GPR64spRegClassID, 1, true },
3428
  { GPR64common, GPR64commonBits, 1811, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 1, true },
3429
  { tcGPR64, tcGPR64Bits, 58, 19, sizeof(tcGPR64Bits), AArch64::tcGPR64RegClassID, 1, true },
3430
  { rtcGPR64, rtcGPR64Bits, 180, 2, sizeof(rtcGPR64Bits), AArch64::rtcGPR64RegClassID, 1, true },
3431
  { GPR64sponly, GPR64sponlyBits, 2604, 1, sizeof(GPR64sponlyBits), AArch64::GPR64sponlyRegClassID, 1, true },
3432
  { DD, DDBits, 296, 32, sizeof(DDBits), AArch64::DDRegClassID, 1, true },
3433
  { XSeqPairsClass, XSeqPairsClassBits, 2577, 32, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 1, true },
3434
  { XSeqPairsClass_with_sub_32_in_GPR32common, XSeqPairsClass_with_sub_32_in_GPR32commonBits, 1563, 31, sizeof(XSeqPairsClass_with_sub_32_in_GPR32commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID, 1, true },
3435
  { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, 1781, 31, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 1, true },
3436
  { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits, 1735, 30, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 1, true },
3437
  { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, 28, 19, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, 1, true },
3438
  { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, 112, 19, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 1, true },
3439
  { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits, 66, 18, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 1, true },
3440
  { XSeqPairsClass_with_sube64_in_rtcGPR64, XSeqPairsClass_with_sube64_in_rtcGPR64Bits, 150, 2, sizeof(XSeqPairsClass_with_sube64_in_rtcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID, 1, true },
3441
  { XSeqPairsClass_with_subo64_in_rtcGPR64, XSeqPairsClass_with_subo64_in_rtcGPR64Bits, 232, 2, sizeof(XSeqPairsClass_with_subo64_in_rtcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_rtcGPR64RegClassID, 1, true },
3442
  { XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64, XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64Bits, 189, 1, sizeof(XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64RegClassID, 1, true },
3443
  { FPR128, FPR128Bits, 282, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 1, true },
3444
  { ZPR, ZPRBits, 312, 32, sizeof(ZPRBits), AArch64::ZPRRegClassID, 1, true },
3445
  { FPR128_lo, FPR128_loBits, 1842, 16, sizeof(FPR128_loBits), AArch64::FPR128_loRegClassID, 1, true },
3446
  { ZPR_4b, ZPR_4bBits, 1024, 16, sizeof(ZPR_4bBits), AArch64::ZPR_4bRegClassID, 1, true },
3447
  { ZPR_3b, ZPR_3bBits, 342, 8, sizeof(ZPR_3bBits), AArch64::ZPR_3bRegClassID, 1, true },
3448
  { DDD, DDDBits, 295, 32, sizeof(DDDBits), AArch64::DDDRegClassID, 1, true },
3449
  { DDDD, DDDDBits, 294, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 1, true },
3450
  { QQ, QQBits, 301, 32, sizeof(QQBits), AArch64::QQRegClassID, 1, true },
3451
  { ZPR2, ZPR2Bits, 12, 32, sizeof(ZPR2Bits), AArch64::ZPR2RegClassID, 1, true },
3452
  { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 1825, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3453
  { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 1887, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3454
  { ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub1_in_ZPR_4bBits, 1005, 16, sizeof(ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3455
  { ZPR2_with_zsub_in_FPR128_lo, ZPR2_with_zsub_in_FPR128_loBits, 2462, 16, sizeof(ZPR2_with_zsub_in_FPR128_loBits), AArch64::ZPR2_with_zsub_in_FPR128_loRegClassID, 1, true },
3456
  { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 1974, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3457
  { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits, 973, 15, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3458
  { ZPR2_with_zsub0_in_ZPR_3b, ZPR2_with_zsub0_in_ZPR_3bBits, 323, 8, sizeof(ZPR2_with_zsub0_in_ZPR_3bBits), AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3459
  { ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub1_in_ZPR_3bBits, 433, 8, sizeof(ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3460
  { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits, 401, 7, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3461
  { QQQ, QQQBits, 300, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 1, true },
3462
  { ZPR3, ZPR3Bits, 17, 32, sizeof(ZPR3Bits), AArch64::ZPR3RegClassID, 1, true },
3463
  { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 1824, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3464
  { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 1886, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3465
  { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 2066, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3466
  { ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4bBits, 1063, 16, sizeof(ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3467
  { ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub2_in_ZPR_4bBits, 1177, 16, sizeof(ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3468
  { ZPR3_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_loBits, 2490, 16, sizeof(ZPR3_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub_in_FPR128_loRegClassID, 1, true },
3469
  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 1914, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3470
  { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2216, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3471
  { ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1147, 15, sizeof(ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3472
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits, 1031, 15, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3473
  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2156, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3474
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1203, 14, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3475
  { ZPR3_with_zsub0_in_ZPR_3b, ZPR3_with_zsub0_in_ZPR_3bBits, 349, 8, sizeof(ZPR3_with_zsub0_in_ZPR_3bBits), AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3476
  { ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3bBits, 491, 8, sizeof(ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3477
  { ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub2_in_ZPR_3bBits, 605, 8, sizeof(ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3478
  { ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits, 575, 7, sizeof(ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3479
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits, 459, 7, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3480
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits, 631, 6, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3481
  { QQQQ, QQQQBits, 299, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 1, true },
3482
  { ZPR4, ZPR4Bits, 271, 32, sizeof(ZPR4Bits), AArch64::ZPR4RegClassID, 1, true },
3483
  { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 1823, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3484
  { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 1885, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3485
  { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 2065, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3486
  { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 2309, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3487
  { ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4bBits, 1121, 16, sizeof(ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3488
  { ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4bBits, 1291, 16, sizeof(ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3489
  { ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub3_in_ZPR_4bBits, 1405, 16, sizeof(ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3490
  { ZPR4_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_loBits, 2518, 16, sizeof(ZPR4_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub_in_FPR128_loRegClassID, 1, true },
3491
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 1852, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3492
  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 2094, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3493
  { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2400, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3494
  { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1261, 15, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3495
  { ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1431, 15, sizeof(ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3496
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits, 1089, 15, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3497
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 2032, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3498
  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2338, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3499
  { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1375, 14, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3500
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1317, 14, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3501
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2276, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3502
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1487, 13, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3503
  { ZPR4_with_zsub0_in_ZPR_3b, ZPR4_with_zsub0_in_ZPR_3bBits, 375, 8, sizeof(ZPR4_with_zsub0_in_ZPR_3bBits), AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3504
  { ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3bBits, 549, 8, sizeof(ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3505
  { ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3bBits, 719, 8, sizeof(ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3506
  { ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub3_in_ZPR_3bBits, 833, 8, sizeof(ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3507
  { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits, 689, 7, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3508
  { ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 859, 7, sizeof(ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3509
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits, 517, 7, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3510
  { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 803, 6, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3511
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits, 745, 6, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3512
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits, 915, 5, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3513
};
3514
3515
// AArch64 Dwarf<->LLVM register mappings.
3516
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
3517
  { 0U, AArch64::W0 },
3518
  { 1U, AArch64::W1 },
3519
  { 2U, AArch64::W2 },
3520
  { 3U, AArch64::W3 },
3521
  { 4U, AArch64::W4 },
3522
  { 5U, AArch64::W5 },
3523
  { 6U, AArch64::W6 },
3524
  { 7U, AArch64::W7 },
3525
  { 8U, AArch64::W8 },
3526
  { 9U, AArch64::W9 },
3527
  { 10U, AArch64::W10 },
3528
  { 11U, AArch64::W11 },
3529
  { 12U, AArch64::W12 },
3530
  { 13U, AArch64::W13 },
3531
  { 14U, AArch64::W14 },
3532
  { 15U, AArch64::W15 },
3533
  { 16U, AArch64::W16 },
3534
  { 17U, AArch64::W17 },
3535
  { 18U, AArch64::W18 },
3536
  { 19U, AArch64::W19 },
3537
  { 20U, AArch64::W20 },
3538
  { 21U, AArch64::W21 },
3539
  { 22U, AArch64::W22 },
3540
  { 23U, AArch64::W23 },
3541
  { 24U, AArch64::W24 },
3542
  { 25U, AArch64::W25 },
3543
  { 26U, AArch64::W26 },
3544
  { 27U, AArch64::W27 },
3545
  { 28U, AArch64::W28 },
3546
  { 29U, AArch64::W29 },
3547
  { 30U, AArch64::W30 },
3548
  { 31U, AArch64::WSP },
3549
  { 47U, AArch64::FFR },
3550
  { 48U, AArch64::P0 },
3551
  { 49U, AArch64::P1 },
3552
  { 50U, AArch64::P2 },
3553
  { 51U, AArch64::P3 },
3554
  { 52U, AArch64::P4 },
3555
  { 53U, AArch64::P5 },
3556
  { 54U, AArch64::P6 },
3557
  { 55U, AArch64::P7 },
3558
  { 56U, AArch64::P8 },
3559
  { 57U, AArch64::P9 },
3560
  { 58U, AArch64::P10 },
3561
  { 59U, AArch64::P11 },
3562
  { 60U, AArch64::P12 },
3563
  { 61U, AArch64::P13 },
3564
  { 62U, AArch64::P14 },
3565
  { 63U, AArch64::P15 },
3566
  { 64U, AArch64::B0 },
3567
  { 65U, AArch64::B1 },
3568
  { 66U, AArch64::B2 },
3569
  { 67U, AArch64::B3 },
3570
  { 68U, AArch64::B4 },
3571
  { 69U, AArch64::B5 },
3572
  { 70U, AArch64::B6 },
3573
  { 71U, AArch64::B7 },
3574
  { 72U, AArch64::B8 },
3575
  { 73U, AArch64::B9 },
3576
  { 74U, AArch64::B10 },
3577
  { 75U, AArch64::B11 },
3578
  { 76U, AArch64::B12 },
3579
  { 77U, AArch64::B13 },
3580
  { 78U, AArch64::B14 },
3581
  { 79U, AArch64::B15 },
3582
  { 80U, AArch64::B16 },
3583
  { 81U, AArch64::B17 },
3584
  { 82U, AArch64::B18 },
3585
  { 83U, AArch64::B19 },
3586
  { 84U, AArch64::B20 },
3587
  { 85U, AArch64::B21 },
3588
  { 86U, AArch64::B22 },
3589
  { 87U, AArch64::B23 },
3590
  { 88U, AArch64::B24 },
3591
  { 89U, AArch64::B25 },
3592
  { 90U, AArch64::B26 },
3593
  { 91U, AArch64::B27 },
3594
  { 92U, AArch64::B28 },
3595
  { 93U, AArch64::B29 },
3596
  { 94U, AArch64::B30 },
3597
  { 95U, AArch64::B31 },
3598
  { 96U, AArch64::Z0 },
3599
  { 97U, AArch64::Z1 },
3600
  { 98U, AArch64::Z2 },
3601
  { 99U, AArch64::Z3 },
3602
  { 100U, AArch64::Z4 },
3603
  { 101U, AArch64::Z5 },
3604
  { 102U, AArch64::Z6 },
3605
  { 103U, AArch64::Z7 },
3606
  { 104U, AArch64::Z8 },
3607
  { 105U, AArch64::Z9 },
3608
  { 106U, AArch64::Z10 },
3609
  { 107U, AArch64::Z11 },
3610
  { 108U, AArch64::Z12 },
3611
  { 109U, AArch64::Z13 },
3612
  { 110U, AArch64::Z14 },
3613
  { 111U, AArch64::Z15 },
3614
  { 112U, AArch64::Z16 },
3615
  { 113U, AArch64::Z17 },
3616
  { 114U, AArch64::Z18 },
3617
  { 115U, AArch64::Z19 },
3618
  { 116U, AArch64::Z20 },
3619
  { 117U, AArch64::Z21 },
3620
  { 118U, AArch64::Z22 },
3621
  { 119U, AArch64::Z23 },
3622
  { 120U, AArch64::Z24 },
3623
  { 121U, AArch64::Z25 },
3624
  { 122U, AArch64::Z26 },
3625
  { 123U, AArch64::Z27 },
3626
  { 124U, AArch64::Z28 },
3627
  { 125U, AArch64::Z29 },
3628
  { 126U, AArch64::Z30 },
3629
  { 127U, AArch64::Z31 },
3630
};
3631
extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = array_lengthof(AArch64DwarfFlavour0Dwarf2L);
3632
3633
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
3634
  { 0U, AArch64::W0 },
3635
  { 1U, AArch64::W1 },
3636
  { 2U, AArch64::W2 },
3637
  { 3U, AArch64::W3 },
3638
  { 4U, AArch64::W4 },
3639
  { 5U, AArch64::W5 },
3640
  { 6U, AArch64::W6 },
3641
  { 7U, AArch64::W7 },
3642
  { 8U, AArch64::W8 },
3643
  { 9U, AArch64::W9 },
3644
  { 10U, AArch64::W10 },
3645
  { 11U, AArch64::W11 },
3646
  { 12U, AArch64::W12 },
3647
  { 13U, AArch64::W13 },
3648
  { 14U, AArch64::W14 },
3649
  { 15U, AArch64::W15 },
3650
  { 16U, AArch64::W16 },
3651
  { 17U, AArch64::W17 },
3652
  { 18U, AArch64::W18 },
3653
  { 19U, AArch64::W19 },
3654
  { 20U, AArch64::W20 },
3655
  { 21U, AArch64::W21 },
3656
  { 22U, AArch64::W22 },
3657
  { 23U, AArch64::W23 },
3658
  { 24U, AArch64::W24 },
3659
  { 25U, AArch64::W25 },
3660
  { 26U, AArch64::W26 },
3661
  { 27U, AArch64::W27 },
3662
  { 28U, AArch64::W28 },
3663
  { 29U, AArch64::W29 },
3664
  { 30U, AArch64::W30 },
3665
  { 31U, AArch64::WSP },
3666
  { 47U, AArch64::FFR },
3667
  { 48U, AArch64::P0 },
3668
  { 49U, AArch64::P1 },
3669
  { 50U, AArch64::P2 },
3670
  { 51U, AArch64::P3 },
3671
  { 52U, AArch64::P4 },
3672
  { 53U, AArch64::P5 },
3673
  { 54U, AArch64::P6 },
3674
  { 55U, AArch64::P7 },
3675
  { 56U, AArch64::P8 },
3676
  { 57U, AArch64::P9 },
3677
  { 58U, AArch64::P10 },
3678
  { 59U, AArch64::P11 },
3679
  { 60U, AArch64::P12 },
3680
  { 61U, AArch64::P13 },
3681
  { 62U, AArch64::P14 },
3682
  { 63U, AArch64::P15 },
3683
  { 64U, AArch64::B0 },
3684
  { 65U, AArch64::B1 },
3685
  { 66U, AArch64::B2 },
3686
  { 67U, AArch64::B3 },
3687
  { 68U, AArch64::B4 },
3688
  { 69U, AArch64::B5 },
3689
  { 70U, AArch64::B6 },
3690
  { 71U, AArch64::B7 },
3691
  { 72U, AArch64::B8 },
3692
  { 73U, AArch64::B9 },
3693
  { 74U, AArch64::B10 },
3694
  { 75U, AArch64::B11 },
3695
  { 76U, AArch64::B12 },
3696
  { 77U, AArch64::B13 },
3697
  { 78U, AArch64::B14 },
3698
  { 79U, AArch64::B15 },
3699
  { 80U, AArch64::B16 },
3700
  { 81U, AArch64::B17 },
3701
  { 82U, AArch64::B18 },
3702
  { 83U, AArch64::B19 },
3703
  { 84U, AArch64::B20 },
3704
  { 85U, AArch64::B21 },
3705
  { 86U, AArch64::B22 },
3706
  { 87U, AArch64::B23 },
3707
  { 88U, AArch64::B24 },
3708
  { 89U, AArch64::B25 },
3709
  { 90U, AArch64::B26 },
3710
  { 91U, AArch64::B27 },
3711
  { 92U, AArch64::B28 },
3712
  { 93U, AArch64::B29 },
3713
  { 94U, AArch64::B30 },
3714
  { 95U, AArch64::B31 },
3715
  { 96U, AArch64::Z0 },
3716
  { 97U, AArch64::Z1 },
3717
  { 98U, AArch64::Z2 },
3718
  { 99U, AArch64::Z3 },
3719
  { 100U, AArch64::Z4 },
3720
  { 101U, AArch64::Z5 },
3721
  { 102U, AArch64::Z6 },
3722
  { 103U, AArch64::Z7 },
3723
  { 104U, AArch64::Z8 },
3724
  { 105U, AArch64::Z9 },
3725
  { 106U, AArch64::Z10 },
3726
  { 107U, AArch64::Z11 },
3727
  { 108U, AArch64::Z12 },
3728
  { 109U, AArch64::Z13 },
3729
  { 110U, AArch64::Z14 },
3730
  { 111U, AArch64::Z15 },
3731
  { 112U, AArch64::Z16 },
3732
  { 113U, AArch64::Z17 },
3733
  { 114U, AArch64::Z18 },
3734
  { 115U, AArch64::Z19 },
3735
  { 116U, AArch64::Z20 },
3736
  { 117U, AArch64::Z21 },
3737
  { 118U, AArch64::Z22 },
3738
  { 119U, AArch64::Z23 },
3739
  { 120U, AArch64::Z24 },
3740
  { 121U, AArch64::Z25 },
3741
  { 122U, AArch64::Z26 },
3742
  { 123U, AArch64::Z27 },
3743
  { 124U, AArch64::Z28 },
3744
  { 125U, AArch64::Z29 },
3745
  { 126U, AArch64::Z30 },
3746
  { 127U, AArch64::Z31 },
3747
};
3748
extern const unsigned AArch64EHFlavour0Dwarf2LSize = array_lengthof(AArch64EHFlavour0Dwarf2L);
3749
3750
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
3751
  { AArch64::FFR, 47U },
3752
  { AArch64::FP, 29U },
3753
  { AArch64::LR, 30U },
3754
  { AArch64::SP, 31U },
3755
  { AArch64::WSP, 31U },
3756
  { AArch64::WZR, 31U },
3757
  { AArch64::XZR, 31U },
3758
  { AArch64::B0, 64U },
3759
  { AArch64::B1, 65U },
3760
  { AArch64::B2, 66U },
3761
  { AArch64::B3, 67U },
3762
  { AArch64::B4, 68U },
3763
  { AArch64::B5, 69U },
3764
  { AArch64::B6, 70U },
3765
  { AArch64::B7, 71U },
3766
  { AArch64::B8, 72U },
3767
  { AArch64::B9, 73U },
3768
  { AArch64::B10, 74U },
3769
  { AArch64::B11, 75U },
3770
  { AArch64::B12, 76U },
3771
  { AArch64::B13, 77U },
3772
  { AArch64::B14, 78U },
3773
  { AArch64::B15, 79U },
3774
  { AArch64::B16, 80U },
3775
  { AArch64::B17, 81U },
3776
  { AArch64::B18, 82U },
3777
  { AArch64::B19, 83U },
3778
  { AArch64::B20, 84U },
3779
  { AArch64::B21, 85U },
3780
  { AArch64::B22, 86U },
3781
  { AArch64::B23, 87U },
3782
  { AArch64::B24, 88U },
3783
  { AArch64::B25, 89U },
3784
  { AArch64::B26, 90U },
3785
  { AArch64::B27, 91U },
3786
  { AArch64::B28, 92U },
3787
  { AArch64::B29, 93U },
3788
  { AArch64::B30, 94U },
3789
  { AArch64::B31, 95U },
3790
  { AArch64::D0, 64U },
3791
  { AArch64::D1, 65U },
3792
  { AArch64::D2, 66U },
3793
  { AArch64::D3, 67U },
3794
  { AArch64::D4, 68U },
3795
  { AArch64::D5, 69U },
3796
  { AArch64::D6, 70U },
3797
  { AArch64::D7, 71U },
3798
  { AArch64::D8, 72U },
3799
  { AArch64::D9, 73U },
3800
  { AArch64::D10, 74U },
3801
  { AArch64::D11, 75U },
3802
  { AArch64::D12, 76U },
3803
  { AArch64::D13, 77U },
3804
  { AArch64::D14, 78U },
3805
  { AArch64::D15, 79U },
3806
  { AArch64::D16, 80U },
3807
  { AArch64::D17, 81U },
3808
  { AArch64::D18, 82U },
3809
  { AArch64::D19, 83U },
3810
  { AArch64::D20, 84U },
3811
  { AArch64::D21, 85U },
3812
  { AArch64::D22, 86U },
3813
  { AArch64::D23, 87U },
3814
  { AArch64::D24, 88U },
3815
  { AArch64::D25, 89U },
3816
  { AArch64::D26, 90U },
3817
  { AArch64::D27, 91U },
3818
  { AArch64::D28, 92U },
3819
  { AArch64::D29, 93U },
3820
  { AArch64::D30, 94U },
3821
  { AArch64::D31, 95U },
3822
  { AArch64::H0, 64U },
3823
  { AArch64::H1, 65U },
3824
  { AArch64::H2, 66U },
3825
  { AArch64::H3, 67U },
3826
  { AArch64::H4, 68U },
3827
  { AArch64::H5, 69U },
3828
  { AArch64::H6, 70U },
3829
  { AArch64::H7, 71U },
3830
  { AArch64::H8, 72U },
3831
  { AArch64::H9, 73U },
3832
  { AArch64::H10, 74U },
3833
  { AArch64::H11, 75U },
3834
  { AArch64::H12, 76U },
3835
  { AArch64::H13, 77U },
3836
  { AArch64::H14, 78U },
3837
  { AArch64::H15, 79U },
3838
  { AArch64::H16, 80U },
3839
  { AArch64::H17, 81U },
3840
  { AArch64::H18, 82U },
3841
  { AArch64::H19, 83U },
3842
  { AArch64::H20, 84U },
3843
  { AArch64::H21, 85U },
3844
  { AArch64::H22, 86U },
3845
  { AArch64::H23, 87U },
3846
  { AArch64::H24, 88U },
3847
  { AArch64::H25, 89U },
3848
  { AArch64::H26, 90U },
3849
  { AArch64::H27, 91U },
3850
  { AArch64::H28, 92U },
3851
  { AArch64::H29, 93U },
3852
  { AArch64::H30, 94U },
3853
  { AArch64::H31, 95U },
3854
  { AArch64::P0, 48U },
3855
  { AArch64::P1, 49U },
3856
  { AArch64::P2, 50U },
3857
  { AArch64::P3, 51U },
3858
  { AArch64::P4, 52U },
3859
  { AArch64::P5, 53U },
3860
  { AArch64::P6, 54U },
3861
  { AArch64::P7, 55U },
3862
  { AArch64::P8, 56U },
3863
  { AArch64::P9, 57U },
3864
  { AArch64::P10, 58U },
3865
  { AArch64::P11, 59U },
3866
  { AArch64::P12, 60U },
3867
  { AArch64::P13, 61U },
3868
  { AArch64::P14, 62U },
3869
  { AArch64::P15, 63U },
3870
  { AArch64::Q0, 64U },
3871
  { AArch64::Q1, 65U },
3872
  { AArch64::Q2, 66U },
3873
  { AArch64::Q3, 67U },
3874
  { AArch64::Q4, 68U },
3875
  { AArch64::Q5, 69U },
3876
  { AArch64::Q6, 70U },
3877
  { AArch64::Q7, 71U },
3878
  { AArch64::Q8, 72U },
3879
  { AArch64::Q9, 73U },
3880
  { AArch64::Q10, 74U },
3881
  { AArch64::Q11, 75U },
3882
  { AArch64::Q12, 76U },
3883
  { AArch64::Q13, 77U },
3884
  { AArch64::Q14, 78U },
3885
  { AArch64::Q15, 79U },
3886
  { AArch64::Q16, 80U },
3887
  { AArch64::Q17, 81U },
3888
  { AArch64::Q18, 82U },
3889
  { AArch64::Q19, 83U },
3890
  { AArch64::Q20, 84U },
3891
  { AArch64::Q21, 85U },
3892
  { AArch64::Q22, 86U },
3893
  { AArch64::Q23, 87U },
3894
  { AArch64::Q24, 88U },
3895
  { AArch64::Q25, 89U },
3896
  { AArch64::Q26, 90U },
3897
  { AArch64::Q27, 91U },
3898
  { AArch64::Q28, 92U },
3899
  { AArch64::Q29, 93U },
3900
  { AArch64::Q30, 94U },
3901
  { AArch64::Q31, 95U },
3902
  { AArch64::S0, 64U },
3903
  { AArch64::S1, 65U },
3904
  { AArch64::S2, 66U },
3905
  { AArch64::S3, 67U },
3906
  { AArch64::S4, 68U },
3907
  { AArch64::S5, 69U },
3908
  { AArch64::S6, 70U },
3909
  { AArch64::S7, 71U },
3910
  { AArch64::S8, 72U },
3911
  { AArch64::S9, 73U },
3912
  { AArch64::S10, 74U },
3913
  { AArch64::S11, 75U },
3914
  { AArch64::S12, 76U },
3915
  { AArch64::S13, 77U },
3916
  { AArch64::S14, 78U },
3917
  { AArch64::S15, 79U },
3918
  { AArch64::S16, 80U },
3919
  { AArch64::S17, 81U },
3920
  { AArch64::S18, 82U },
3921
  { AArch64::S19, 83U },
3922
  { AArch64::S20, 84U },
3923
  { AArch64::S21, 85U },
3924
  { AArch64::S22, 86U },
3925
  { AArch64::S23, 87U },
3926
  { AArch64::S24, 88U },
3927
  { AArch64::S25, 89U },
3928
  { AArch64::S26, 90U },
3929
  { AArch64::S27, 91U },
3930
  { AArch64::S28, 92U },
3931
  { AArch64::S29, 93U },
3932
  { AArch64::S30, 94U },
3933
  { AArch64::S31, 95U },
3934
  { AArch64::W0, 0U },
3935
  { AArch64::W1, 1U },
3936
  { AArch64::W2, 2U },
3937
  { AArch64::W3, 3U },
3938
  { AArch64::W4, 4U },
3939
  { AArch64::W5, 5U },
3940
  { AArch64::W6, 6U },
3941
  { AArch64::W7, 7U },
3942
  { AArch64::W8, 8U },
3943
  { AArch64::W9, 9U },
3944
  { AArch64::W10, 10U },
3945
  { AArch64::W11, 11U },
3946
  { AArch64::W12, 12U },
3947
  { AArch64::W13, 13U },
3948
  { AArch64::W14, 14U },
3949
  { AArch64::W15, 15U },
3950
  { AArch64::W16, 16U },
3951
  { AArch64::W17, 17U },
3952
  { AArch64::W18, 18U },
3953
  { AArch64::W19, 19U },
3954
  { AArch64::W20, 20U },
3955
  { AArch64::W21, 21U },
3956
  { AArch64::W22, 22U },
3957
  { AArch64::W23, 23U },
3958
  { AArch64::W24, 24U },
3959
  { AArch64::W25, 25U },
3960
  { AArch64::W26, 26U },
3961
  { AArch64::W27, 27U },
3962
  { AArch64::W28, 28U },
3963
  { AArch64::W29, 29U },
3964
  { AArch64::W30, 30U },
3965
  { AArch64::X0, 0U },
3966
  { AArch64::X1, 1U },
3967
  { AArch64::X2, 2U },
3968
  { AArch64::X3, 3U },
3969
  { AArch64::X4, 4U },
3970
  { AArch64::X5, 5U },
3971
  { AArch64::X6, 6U },
3972
  { AArch64::X7, 7U },
3973
  { AArch64::X8, 8U },
3974
  { AArch64::X9, 9U },
3975
  { AArch64::X10, 10U },
3976
  { AArch64::X11, 11U },
3977
  { AArch64::X12, 12U },
3978
  { AArch64::X13, 13U },
3979
  { AArch64::X14, 14U },
3980
  { AArch64::X15, 15U },
3981
  { AArch64::X16, 16U },
3982
  { AArch64::X17, 17U },
3983
  { AArch64::X18, 18U },
3984
  { AArch64::X19, 19U },
3985
  { AArch64::X20, 20U },
3986
  { AArch64::X21, 21U },
3987
  { AArch64::X22, 22U },
3988
  { AArch64::X23, 23U },
3989
  { AArch64::X24, 24U },
3990
  { AArch64::X25, 25U },
3991
  { AArch64::X26, 26U },
3992
  { AArch64::X27, 27U },
3993
  { AArch64::X28, 28U },
3994
  { AArch64::Z0, 96U },
3995
  { AArch64::Z1, 97U },
3996
  { AArch64::Z2, 98U },
3997
  { AArch64::Z3, 99U },
3998
  { AArch64::Z4, 100U },
3999
  { AArch64::Z5, 101U },
4000
  { AArch64::Z6, 102U },
4001
  { AArch64::Z7, 103U },
4002
  { AArch64::Z8, 104U },
4003
  { AArch64::Z9, 105U },
4004
  { AArch64::Z10, 106U },
4005
  { AArch64::Z11, 107U },
4006
  { AArch64::Z12, 108U },
4007
  { AArch64::Z13, 109U },
4008
  { AArch64::Z14, 110U },
4009
  { AArch64::Z15, 111U },
4010
  { AArch64::Z16, 112U },
4011
  { AArch64::Z17, 113U },
4012
  { AArch64::Z18, 114U },
4013
  { AArch64::Z19, 115U },
4014
  { AArch64::Z20, 116U },
4015
  { AArch64::Z21, 117U },
4016
  { AArch64::Z22, 118U },
4017
  { AArch64::Z23, 119U },
4018
  { AArch64::Z24, 120U },
4019
  { AArch64::Z25, 121U },
4020
  { AArch64::Z26, 122U },
4021
  { AArch64::Z27, 123U },
4022
  { AArch64::Z28, 124U },
4023
  { AArch64::Z29, 125U },
4024
  { AArch64::Z30, 126U },
4025
  { AArch64::Z31, 127U },
4026
};
4027
extern const unsigned AArch64DwarfFlavour0L2DwarfSize = array_lengthof(AArch64DwarfFlavour0L2Dwarf);
4028
4029
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
4030
  { AArch64::FFR, 47U },
4031
  { AArch64::FP, 29U },
4032
  { AArch64::LR, 30U },
4033
  { AArch64::SP, 31U },
4034
  { AArch64::WSP, 31U },
4035
  { AArch64::WZR, 31U },
4036
  { AArch64::XZR, 31U },
4037
  { AArch64::B0, 64U },
4038
  { AArch64::B1, 65U },
4039
  { AArch64::B2, 66U },
4040
  { AArch64::B3, 67U },
4041
  { AArch64::B4, 68U },
4042
  { AArch64::B5, 69U },
4043
  { AArch64::B6, 70U },
4044
  { AArch64::B7, 71U },
4045
  { AArch64::B8, 72U },
4046
  { AArch64::B9, 73U },
4047
  { AArch64::B10, 74U },
4048
  { AArch64::B11, 75U },
4049
  { AArch64::B12, 76U },
4050
  { AArch64::B13, 77U },
4051
  { AArch64::B14, 78U },
4052
  { AArch64::B15, 79U },
4053
  { AArch64::B16, 80U },
4054
  { AArch64::B17, 81U },
4055
  { AArch64::B18, 82U },
4056
  { AArch64::B19, 83U },
4057
  { AArch64::B20, 84U },
4058
  { AArch64::B21, 85U },
4059
  { AArch64::B22, 86U },
4060
  { AArch64::B23, 87U },
4061
  { AArch64::B24, 88U },
4062
  { AArch64::B25, 89U },
4063
  { AArch64::B26, 90U },
4064
  { AArch64::B27, 91U },
4065
  { AArch64::B28, 92U },
4066
  { AArch64::B29, 93U },
4067
  { AArch64::B30, 94U },
4068
  { AArch64::B31, 95U },
4069
  { AArch64::D0, 64U },
4070
  { AArch64::D1, 65U },
4071
  { AArch64::D2, 66U },
4072
  { AArch64::D3, 67U },
4073
  { AArch64::D4, 68U },
4074
  { AArch64::D5, 69U },
4075
  { AArch64::D6, 70U },
4076
  { AArch64::D7, 71U },
4077
  { AArch64::D8, 72U },
4078
  { AArch64::D9, 73U },
4079
  { AArch64::D10, 74U },
4080
  { AArch64::D11, 75U },
4081
  { AArch64::D12, 76U },
4082
  { AArch64::D13, 77U },
4083
  { AArch64::D14, 78U },
4084
  { AArch64::D15, 79U },
4085
  { AArch64::D16, 80U },
4086
  { AArch64::D17, 81U },
4087
  { AArch64::D18, 82U },
4088
  { AArch64::D19, 83U },
4089
  { AArch64::D20, 84U },
4090
  { AArch64::D21, 85U },
4091
  { AArch64::D22, 86U },
4092
  { AArch64::D23, 87U },
4093
  { AArch64::D24, 88U },
4094
  { AArch64::D25, 89U },
4095
  { AArch64::D26, 90U },
4096
  { AArch64::D27, 91U },
4097
  { AArch64::D28, 92U },
4098
  { AArch64::D29, 93U },
4099
  { AArch64::D30, 94U },
4100
  { AArch64::D31, 95U },
4101
  { AArch64::H0, 64U },
4102
  { AArch64::H1, 65U },
4103
  { AArch64::H2, 66U },
4104
  { AArch64::H3, 67U },
4105
  { AArch64::H4, 68U },
4106
  { AArch64::H5, 69U },
4107
  { AArch64::H6, 70U },
4108
  { AArch64::H7, 71U },
4109
  { AArch64::H8, 72U },
4110
  { AArch64::H9, 73U },
4111
  { AArch64::H10, 74U },
4112
  { AArch64::H11, 75U },
4113
  { AArch64::H12, 76U },
4114
  { AArch64::H13, 77U },
4115
  { AArch64::H14, 78U },
4116
  { AArch64::H15, 79U },
4117
  { AArch64::H16, 80U },
4118
  { AArch64::H17, 81U },
4119
  { AArch64::H18, 82U },
4120
  { AArch64::H19, 83U },
4121
  { AArch64::H20, 84U },
4122
  { AArch64::H21, 85U },
4123
  { AArch64::H22, 86U },
4124
  { AArch64::H23, 87U },
4125
  { AArch64::H24, 88U },
4126
  { AArch64::H25, 89U },
4127
  { AArch64::H26, 90U },
4128
  { AArch64::H27, 91U },
4129
  { AArch64::H28, 92U },
4130
  { AArch64::H29, 93U },
4131
  { AArch64::H30, 94U },
4132
  { AArch64::H31, 95U },
4133
  { AArch64::P0, 48U },
4134
  { AArch64::P1, 49U },
4135
  { AArch64::P2, 50U },
4136
  { AArch64::P3, 51U },
4137
  { AArch64::P4, 52U },
4138
  { AArch64::P5, 53U },
4139
  { AArch64::P6, 54U },
4140
  { AArch64::P7, 55U },
4141
  { AArch64::P8, 56U },
4142
  { AArch64::P9, 57U },
4143
  { AArch64::P10, 58U },
4144
  { AArch64::P11, 59U },
4145
  { AArch64::P12, 60U },
4146
  { AArch64::P13, 61U },
4147
  { AArch64::P14, 62U },
4148
  { AArch64::P15, 63U },
4149
  { AArch64::Q0, 64U },
4150
  { AArch64::Q1, 65U },
4151
  { AArch64::Q2, 66U },
4152
  { AArch64::Q3, 67U },
4153
  { AArch64::Q4, 68U },
4154
  { AArch64::Q5, 69U },
4155
  { AArch64::Q6, 70U },
4156
  { AArch64::Q7, 71U },
4157
  { AArch64::Q8, 72U },
4158
  { AArch64::Q9, 73U },
4159
  { AArch64::Q10, 74U },
4160
  { AArch64::Q11, 75U },
4161
  { AArch64::Q12, 76U },
4162
  { AArch64::Q13, 77U },
4163
  { AArch64::Q14, 78U },
4164
  { AArch64::Q15, 79U },
4165
  { AArch64::Q16, 80U },
4166
  { AArch64::Q17, 81U },
4167
  { AArch64::Q18, 82U },
4168
  { AArch64::Q19, 83U },
4169
  { AArch64::Q20, 84U },
4170
  { AArch64::Q21, 85U },
4171
  { AArch64::Q22, 86U },
4172
  { AArch64::Q23, 87U },
4173
  { AArch64::Q24, 88U },
4174
  { AArch64::Q25, 89U },
4175
  { AArch64::Q26, 90U },
4176
  { AArch64::Q27, 91U },
4177
  { AArch64::Q28, 92U },
4178
  { AArch64::Q29, 93U },
4179
  { AArch64::Q30, 94U },
4180
  { AArch64::Q31, 95U },
4181
  { AArch64::S0, 64U },
4182
  { AArch64::S1, 65U },
4183
  { AArch64::S2, 66U },
4184
  { AArch64::S3, 67U },
4185
  { AArch64::S4, 68U },
4186
  { AArch64::S5, 69U },
4187
  { AArch64::S6, 70U },
4188
  { AArch64::S7, 71U },
4189
  { AArch64::S8, 72U },
4190
  { AArch64::S9, 73U },
4191
  { AArch64::S10, 74U },
4192
  { AArch64::S11, 75U },
4193
  { AArch64::S12, 76U },
4194
  { AArch64::S13, 77U },
4195
  { AArch64::S14, 78U },
4196
  { AArch64::S15, 79U },
4197
  { AArch64::S16, 80U },
4198
  { AArch64::S17, 81U },
4199
  { AArch64::S18, 82U },
4200
  { AArch64::S19, 83U },
4201
  { AArch64::S20, 84U },
4202
  { AArch64::S21, 85U },
4203
  { AArch64::S22, 86U },
4204
  { AArch64::S23, 87U },
4205
  { AArch64::S24, 88U },
4206
  { AArch64::S25, 89U },
4207
  { AArch64::S26, 90U },
4208
  { AArch64::S27, 91U },
4209
  { AArch64::S28, 92U },
4210
  { AArch64::S29, 93U },
4211
  { AArch64::S30, 94U },
4212
  { AArch64::S31, 95U },
4213
  { AArch64::W0, 0U },
4214
  { AArch64::W1, 1U },
4215
  { AArch64::W2, 2U },
4216
  { AArch64::W3, 3U },
4217
  { AArch64::W4, 4U },
4218
  { AArch64::W5, 5U },
4219
  { AArch64::W6, 6U },
4220
  { AArch64::W7, 7U },
4221
  { AArch64::W8, 8U },
4222
  { AArch64::W9, 9U },
4223
  { AArch64::W10, 10U },
4224
  { AArch64::W11, 11U },
4225
  { AArch64::W12, 12U },
4226
  { AArch64::W13, 13U },
4227
  { AArch64::W14, 14U },
4228
  { AArch64::W15, 15U },
4229
  { AArch64::W16, 16U },
4230
  { AArch64::W17, 17U },
4231
  { AArch64::W18, 18U },
4232
  { AArch64::W19, 19U },
4233
  { AArch64::W20, 20U },
4234
  { AArch64::W21, 21U },
4235
  { AArch64::W22, 22U },
4236
  { AArch64::W23, 23U },
4237
  { AArch64::W24, 24U },
4238
  { AArch64::W25, 25U },
4239
  { AArch64::W26, 26U },
4240
  { AArch64::W27, 27U },
4241
  { AArch64::W28, 28U },
4242
  { AArch64::W29, 29U },
4243
  { AArch64::W30, 30U },
4244
  { AArch64::X0, 0U },
4245
  { AArch64::X1, 1U },
4246
  { AArch64::X2, 2U },
4247
  { AArch64::X3, 3U },
4248
  { AArch64::X4, 4U },
4249
  { AArch64::X5, 5U },
4250
  { AArch64::X6, 6U },
4251
  { AArch64::X7, 7U },
4252
  { AArch64::X8, 8U },
4253
  { AArch64::X9, 9U },
4254
  { AArch64::X10, 10U },
4255
  { AArch64::X11, 11U },
4256
  { AArch64::X12, 12U },
4257
  { AArch64::X13, 13U },
4258
  { AArch64::X14, 14U },
4259
  { AArch64::X15, 15U },
4260
  { AArch64::X16, 16U },
4261
  { AArch64::X17, 17U },
4262
  { AArch64::X18, 18U },
4263
  { AArch64::X19, 19U },
4264
  { AArch64::X20, 20U },
4265
  { AArch64::X21, 21U },
4266
  { AArch64::X22, 22U },
4267
  { AArch64::X23, 23U },
4268
  { AArch64::X24, 24U },
4269
  { AArch64::X25, 25U },
4270
  { AArch64::X26, 26U },
4271
  { AArch64::X27, 27U },
4272
  { AArch64::X28, 28U },
4273
  { AArch64::Z0, 96U },
4274
  { AArch64::Z1, 97U },
4275
  { AArch64::Z2, 98U },
4276
  { AArch64::Z3, 99U },
4277
  { AArch64::Z4, 100U },
4278
  { AArch64::Z5, 101U },
4279
  { AArch64::Z6, 102U },
4280
  { AArch64::Z7, 103U },
4281
  { AArch64::Z8, 104U },
4282
  { AArch64::Z9, 105U },
4283
  { AArch64::Z10, 106U },
4284
  { AArch64::Z11, 107U },
4285
  { AArch64::Z12, 108U },
4286
  { AArch64::Z13, 109U },
4287
  { AArch64::Z14, 110U },
4288
  { AArch64::Z15, 111U },
4289
  { AArch64::Z16, 112U },
4290
  { AArch64::Z17, 113U },
4291
  { AArch64::Z18, 114U },
4292
  { AArch64::Z19, 115U },
4293
  { AArch64::Z20, 116U },
4294
  { AArch64::Z21, 117U },
4295
  { AArch64::Z22, 118U },
4296
  { AArch64::Z23, 119U },
4297
  { AArch64::Z24, 120U },
4298
  { AArch64::Z25, 121U },
4299
  { AArch64::Z26, 122U },
4300
  { AArch64::Z27, 123U },
4301
  { AArch64::Z28, 124U },
4302
  { AArch64::Z29, 125U },
4303
  { AArch64::Z30, 126U },
4304
  { AArch64::Z31, 127U },
4305
};
4306
extern const unsigned AArch64EHFlavour0L2DwarfSize = array_lengthof(AArch64EHFlavour0L2Dwarf);
4307
4308
extern const uint16_t AArch64RegEncodingTable[] = {
4309
  0,
4310
  0,
4311
  29,
4312
  30,
4313
  0,
4314
  31,
4315
  31,
4316
  31,
4317
  31,
4318
  0,
4319
  1,
4320
  2,
4321
  3,
4322
  4,
4323
  5,
4324
  6,
4325
  7,
4326
  8,
4327
  9,
4328
  10,
4329
  11,
4330
  12,
4331
  13,
4332
  14,
4333
  15,
4334
  16,
4335
  17,
4336
  18,
4337
  19,
4338
  20,
4339
  21,
4340
  22,
4341
  23,
4342
  24,
4343
  25,
4344
  26,
4345
  27,
4346
  28,
4347
  29,
4348
  30,
4349
  31,
4350
  0,
4351
  1,
4352
  2,
4353
  3,
4354
  4,
4355
  5,
4356
  6,
4357
  7,
4358
  8,
4359
  9,
4360
  10,
4361
  11,
4362
  12,
4363
  13,
4364
  14,
4365
  15,
4366
  16,
4367
  17,
4368
  18,
4369
  19,
4370
  20,
4371
  21,
4372
  22,
4373
  23,
4374
  24,
4375
  25,
4376
  26,
4377
  27,
4378
  28,
4379
  29,
4380
  30,
4381
  31,
4382
  0,
4383
  1,
4384
  2,
4385
  3,
4386
  4,
4387
  5,
4388
  6,
4389
  7,
4390
  8,
4391
  9,
4392
  10,
4393
  11,
4394
  12,
4395
  13,
4396
  14,
4397
  15,
4398
  16,
4399
  17,
4400
  18,
4401
  19,
4402
  20,
4403
  21,
4404
  22,
4405
  23,
4406
  24,
4407
  25,
4408
  26,
4409
  27,
4410
  28,
4411
  29,
4412
  30,
4413
  31,
4414
  0,
4415
  1,
4416
  2,
4417
  3,
4418
  4,
4419
  5,
4420
  6,
4421
  7,
4422
  8,
4423
  9,
4424
  10,
4425
  11,
4426
  12,
4427
  13,
4428
  14,
4429
  15,
4430
  0,
4431
  1,
4432
  2,
4433
  3,
4434
  4,
4435
  5,
4436
  6,
4437
  7,
4438
  8,
4439
  9,
4440
  10,
4441
  11,
4442
  12,
4443
  13,
4444
  14,
4445
  15,
4446
  16,
4447
  17,
4448
  18,
4449
  19,
4450
  20,
4451
  21,
4452
  22,
4453
  23,
4454
  24,
4455
  25,
4456
  26,
4457
  27,
4458
  28,
4459
  29,
4460
  30,
4461
  31,
4462
  0,
4463
  1,
4464
  2,
4465
  3,
4466
  4,
4467
  5,
4468
  6,
4469
  7,
4470
  8,
4471
  9,
4472
  10,
4473
  11,
4474
  12,
4475
  13,
4476
  14,
4477
  15,
4478
  16,
4479
  17,
4480
  18,
4481
  19,
4482
  20,
4483
  21,
4484
  22,
4485
  23,
4486
  24,
4487
  25,
4488
  26,
4489
  27,
4490
  28,
4491
  29,
4492
  30,
4493
  31,
4494
  0,
4495
  1,
4496
  2,
4497
  3,
4498
  4,
4499
  5,
4500
  6,
4501
  7,
4502
  8,
4503
  9,
4504
  10,
4505
  11,
4506
  12,
4507
  13,
4508
  14,
4509
  15,
4510
  16,
4511
  17,
4512
  18,
4513
  19,
4514
  20,
4515
  21,
4516
  22,
4517
  23,
4518
  24,
4519
  25,
4520
  26,
4521
  27,
4522
  28,
4523
  29,
4524
  30,
4525
  0,
4526
  1,
4527
  2,
4528
  3,
4529
  4,
4530
  5,
4531
  6,
4532
  7,
4533
  8,
4534
  9,
4535
  10,
4536
  11,
4537
  12,
4538
  13,
4539
  14,
4540
  15,
4541
  16,
4542
  17,
4543
  18,
4544
  19,
4545
  20,
4546
  21,
4547
  22,
4548
  23,
4549
  24,
4550
  25,
4551
  26,
4552
  27,
4553
  28,
4554
  0,
4555
  1,
4556
  2,
4557
  3,
4558
  4,
4559
  5,
4560
  6,
4561
  7,
4562
  8,
4563
  9,
4564
  10,
4565
  11,
4566
  12,
4567
  13,
4568
  14,
4569
  15,
4570
  16,
4571
  17,
4572
  18,
4573
  19,
4574
  20,
4575
  21,
4576
  22,
4577
  23,
4578
  24,
4579
  25,
4580
  26,
4581
  27,
4582
  28,
4583
  29,
4584
  30,
4585
  31,
4586
  0,
4587
  1,
4588
  2,
4589
  3,
4590
  4,
4591
  5,
4592
  6,
4593
  7,
4594
  8,
4595
  9,
4596
  10,
4597
  11,
4598
  12,
4599
  13,
4600
  14,
4601
  15,
4602
  16,
4603
  17,
4604
  18,
4605
  19,
4606
  20,
4607
  21,
4608
  22,
4609
  23,
4610
  24,
4611
  25,
4612
  26,
4613
  27,
4614
  28,
4615
  29,
4616
  30,
4617
  31,
4618
  0,
4619
  1,
4620
  2,
4621
  3,
4622
  4,
4623
  5,
4624
  6,
4625
  7,
4626
  8,
4627
  9,
4628
  10,
4629
  11,
4630
  12,
4631
  13,
4632
  14,
4633
  15,
4634
  16,
4635
  17,
4636
  18,
4637
  19,
4638
  20,
4639
  21,
4640
  22,
4641
  23,
4642
  24,
4643
  25,
4644
  26,
4645
  27,
4646
  28,
4647
  29,
4648
  30,
4649
  31,
4650
  0,
4651
  1,
4652
  2,
4653
  3,
4654
  4,
4655
  5,
4656
  6,
4657
  7,
4658
  8,
4659
  9,
4660
  10,
4661
  11,
4662
  12,
4663
  13,
4664
  14,
4665
  15,
4666
  16,
4667
  17,
4668
  18,
4669
  19,
4670
  20,
4671
  21,
4672
  22,
4673
  23,
4674
  24,
4675
  25,
4676
  26,
4677
  27,
4678
  28,
4679
  29,
4680
  30,
4681
  31,
4682
  0,
4683
  1,
4684
  2,
4685
  3,
4686
  4,
4687
  5,
4688
  6,
4689
  7,
4690
  8,
4691
  9,
4692
  10,
4693
  11,
4694
  12,
4695
  13,
4696
  14,
4697
  15,
4698
  16,
4699
  17,
4700
  18,
4701
  19,
4702
  20,
4703
  21,
4704
  22,
4705
  23,
4706
  24,
4707
  25,
4708
  26,
4709
  27,
4710
  28,
4711
  29,
4712
  30,
4713
  31,
4714
  0,
4715
  1,
4716
  2,
4717
  3,
4718
  4,
4719
  5,
4720
  6,
4721
  7,
4722
  8,
4723
  9,
4724
  10,
4725
  11,
4726
  12,
4727
  13,
4728
  14,
4729
  15,
4730
  16,
4731
  17,
4732
  18,
4733
  19,
4734
  20,
4735
  21,
4736
  22,
4737
  23,
4738
  24,
4739
  25,
4740
  26,
4741
  27,
4742
  28,
4743
  29,
4744
  30,
4745
  31,
4746
  0,
4747
  1,
4748
  2,
4749
  3,
4750
  4,
4751
  5,
4752
  6,
4753
  7,
4754
  8,
4755
  9,
4756
  10,
4757
  11,
4758
  12,
4759
  13,
4760
  14,
4761
  15,
4762
  16,
4763
  17,
4764
  18,
4765
  19,
4766
  20,
4767
  21,
4768
  22,
4769
  23,
4770
  24,
4771
  25,
4772
  26,
4773
  27,
4774
  28,
4775
  29,
4776
  30,
4777
  31,
4778
  0,
4779
  1,
4780
  2,
4781
  3,
4782
  4,
4783
  5,
4784
  6,
4785
  7,
4786
  8,
4787
  9,
4788
  10,
4789
  11,
4790
  12,
4791
  13,
4792
  14,
4793
  15,
4794
  16,
4795
  17,
4796
  18,
4797
  19,
4798
  20,
4799
  21,
4800
  22,
4801
  23,
4802
  24,
4803
  25,
4804
  26,
4805
  27,
4806
  28,
4807
  29,
4808
  30,
4809
  31,
4810
  31,
4811
  30,
4812
  0,
4813
  1,
4814
  2,
4815
  3,
4816
  4,
4817
  5,
4818
  6,
4819
  7,
4820
  8,
4821
  9,
4822
  10,
4823
  11,
4824
  12,
4825
  13,
4826
  14,
4827
  15,
4828
  16,
4829
  17,
4830
  18,
4831
  19,
4832
  20,
4833
  21,
4834
  22,
4835
  23,
4836
  24,
4837
  25,
4838
  26,
4839
  27,
4840
  28,
4841
  29,
4842
  29,
4843
  30,
4844
  31,
4845
  28,
4846
  0,
4847
  1,
4848
  2,
4849
  3,
4850
  4,
4851
  5,
4852
  6,
4853
  7,
4854
  8,
4855
  9,
4856
  10,
4857
  11,
4858
  12,
4859
  13,
4860
  14,
4861
  15,
4862
  16,
4863
  17,
4864
  18,
4865
  19,
4866
  20,
4867
  21,
4868
  22,
4869
  23,
4870
  24,
4871
  25,
4872
  26,
4873
  27,
4874
  0,
4875
  1,
4876
  2,
4877
  3,
4878
  4,
4879
  5,
4880
  6,
4881
  7,
4882
  8,
4883
  9,
4884
  10,
4885
  11,
4886
  12,
4887
  13,
4888
  14,
4889
  15,
4890
  16,
4891
  17,
4892
  18,
4893
  19,
4894
  20,
4895
  21,
4896
  22,
4897
  23,
4898
  24,
4899
  25,
4900
  26,
4901
  27,
4902
  28,
4903
  29,
4904
  30,
4905
  31,
4906
  0,
4907
  1,
4908
  2,
4909
  3,
4910
  4,
4911
  5,
4912
  6,
4913
  7,
4914
  8,
4915
  9,
4916
  10,
4917
  11,
4918
  12,
4919
  13,
4920
  14,
4921
  15,
4922
  16,
4923
  17,
4924
  18,
4925
  19,
4926
  20,
4927
  21,
4928
  22,
4929
  23,
4930
  24,
4931
  25,
4932
  26,
4933
  27,
4934
  28,
4935
  29,
4936
  30,
4937
  31,
4938
  0,
4939
  1,
4940
  2,
4941
  3,
4942
  4,
4943
  5,
4944
  6,
4945
  7,
4946
  8,
4947
  9,
4948
  10,
4949
  11,
4950
  12,
4951
  13,
4952
  14,
4953
  15,
4954
  16,
4955
  17,
4956
  18,
4957
  19,
4958
  20,
4959
  21,
4960
  22,
4961
  23,
4962
  24,
4963
  25,
4964
  26,
4965
  27,
4966
  28,
4967
  29,
4968
  30,
4969
  31,
4970
};
4971
12.3k
static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4972
12.3k
  RI->InitMCRegisterInfo(AArch64RegDesc, 661, RA, PC, AArch64MCRegisterClasses, 104, AArch64RegUnitRoots, 115, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 100,
4973
12.3k
AArch64SubRegIdxRanges, AArch64RegEncodingTable);
4974
12.3k
4975
12.3k
  switch (DwarfFlavour) {
4976
12.3k
  default:
4977
0
    llvm_unreachable("Unknown DWARF flavour");
4978
12.3k
  case 0:
4979
12.3k
    RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
4980
12.3k
    break;
4981
12.3k
  }
4982
12.3k
  switch (EHFlavour) {
4983
12.3k
  default:
4984
0
    llvm_unreachable("Unknown DWARF flavour");
4985
12.3k
  case 0:
4986
12.3k
    RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
4987
12.3k
    break;
4988
12.3k
  }
4989
12.3k
  switch (DwarfFlavour) {
4990
12.3k
  default:
4991
0
    llvm_unreachable("Unknown DWARF flavour");
4992
12.3k
  case 0:
4993
12.3k
    RI->mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
4994
12.3k
    break;
4995
12.3k
  }
4996
12.3k
  switch (EHFlavour) {
4997
12.3k
  default:
4998
0
    llvm_unreachable("Unknown DWARF flavour");
4999
12.3k
  case 0:
5000
12.3k
    RI->mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
5001
12.3k
    break;
5002
12.3k
  }
5003
12.3k
}
5004
5005
} // end namespace llvm
5006
5007
#endif // GET_REGINFO_MC_DESC
5008
5009
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5010
|*                                                                            *|
5011
|* Register Information Header Fragment                                       *|
5012
|*                                                                            *|
5013
|* Automatically generated file, do not edit!                                 *|
5014
|*                                                                            *|
5015
\*===----------------------------------------------------------------------===*/
5016
5017
5018
#ifdef GET_REGINFO_HEADER
5019
#undef GET_REGINFO_HEADER
5020
5021
#include "llvm/CodeGen/TargetRegisterInfo.h"
5022
5023
namespace llvm {
5024
5025
class AArch64FrameLowering;
5026
5027
struct AArch64GenRegisterInfo : public TargetRegisterInfo {
5028
  explicit AArch64GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
5029
      unsigned PC = 0, unsigned HwMode = 0);
5030
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
5031
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5032
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5033
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
5034
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
5035
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
5036
  unsigned getNumRegPressureSets() const override;
5037
  const char *getRegPressureSetName(unsigned Idx) const override;
5038
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
5039
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
5040
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
5041
  ArrayRef<const char *> getRegMaskNames() const override;
5042
  ArrayRef<const uint32_t *> getRegMasks() const override;
5043
  /// Devirtualized TargetFrameLowering.
5044
  static const AArch64FrameLowering *getFrameLowering(
5045
      const MachineFunction &MF);
5046
};
5047
5048
namespace AArch64 { // Register classes
5049
  extern const TargetRegisterClass FPR8RegClass;
5050
  extern const TargetRegisterClass FPR16RegClass;
5051
  extern const TargetRegisterClass PPRRegClass;
5052
  extern const TargetRegisterClass PPR_3bRegClass;
5053
  extern const TargetRegisterClass GPR32allRegClass;
5054
  extern const TargetRegisterClass FPR32RegClass;
5055
  extern const TargetRegisterClass GPR32RegClass;
5056
  extern const TargetRegisterClass GPR32spRegClass;
5057
  extern const TargetRegisterClass GPR32commonRegClass;
5058
  extern const TargetRegisterClass CCRRegClass;
5059
  extern const TargetRegisterClass GPR32sponlyRegClass;
5060
  extern const TargetRegisterClass WSeqPairsClassRegClass;
5061
  extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass;
5062
  extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
5063
  extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
5064
  extern const TargetRegisterClass GPR64allRegClass;
5065
  extern const TargetRegisterClass FPR64RegClass;
5066
  extern const TargetRegisterClass GPR64RegClass;
5067
  extern const TargetRegisterClass GPR64spRegClass;
5068
  extern const TargetRegisterClass GPR64commonRegClass;
5069
  extern const TargetRegisterClass tcGPR64RegClass;
5070
  extern const TargetRegisterClass rtcGPR64RegClass;
5071
  extern const TargetRegisterClass GPR64sponlyRegClass;
5072
  extern const TargetRegisterClass DDRegClass;
5073