Coverage Report

Created: 2018-09-25 00:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AArch64/AArch64GenRegisterInfo.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass AArch64MCRegisterClasses[];
17
18
namespace AArch64 {
19
enum {
20
  NoRegister,
21
  FFR = 1,
22
  FP = 2,
23
  LR = 3,
24
  NZCV = 4,
25
  SP = 5,
26
  WSP = 6,
27
  WZR = 7,
28
  XZR = 8,
29
  B0 = 9,
30
  B1 = 10,
31
  B2 = 11,
32
  B3 = 12,
33
  B4 = 13,
34
  B5 = 14,
35
  B6 = 15,
36
  B7 = 16,
37
  B8 = 17,
38
  B9 = 18,
39
  B10 = 19,
40
  B11 = 20,
41
  B12 = 21,
42
  B13 = 22,
43
  B14 = 23,
44
  B15 = 24,
45
  B16 = 25,
46
  B17 = 26,
47
  B18 = 27,
48
  B19 = 28,
49
  B20 = 29,
50
  B21 = 30,
51
  B22 = 31,
52
  B23 = 32,
53
  B24 = 33,
54
  B25 = 34,
55
  B26 = 35,
56
  B27 = 36,
57
  B28 = 37,
58
  B29 = 38,
59
  B30 = 39,
60
  B31 = 40,
61
  D0 = 41,
62
  D1 = 42,
63
  D2 = 43,
64
  D3 = 44,
65
  D4 = 45,
66
  D5 = 46,
67
  D6 = 47,
68
  D7 = 48,
69
  D8 = 49,
70
  D9 = 50,
71
  D10 = 51,
72
  D11 = 52,
73
  D12 = 53,
74
  D13 = 54,
75
  D14 = 55,
76
  D15 = 56,
77
  D16 = 57,
78
  D17 = 58,
79
  D18 = 59,
80
  D19 = 60,
81
  D20 = 61,
82
  D21 = 62,
83
  D22 = 63,
84
  D23 = 64,
85
  D24 = 65,
86
  D25 = 66,
87
  D26 = 67,
88
  D27 = 68,
89
  D28 = 69,
90
  D29 = 70,
91
  D30 = 71,
92
  D31 = 72,
93
  H0 = 73,
94
  H1 = 74,
95
  H2 = 75,
96
  H3 = 76,
97
  H4 = 77,
98
  H5 = 78,
99
  H6 = 79,
100
  H7 = 80,
101
  H8 = 81,
102
  H9 = 82,
103
  H10 = 83,
104
  H11 = 84,
105
  H12 = 85,
106
  H13 = 86,
107
  H14 = 87,
108
  H15 = 88,
109
  H16 = 89,
110
  H17 = 90,
111
  H18 = 91,
112
  H19 = 92,
113
  H20 = 93,
114
  H21 = 94,
115
  H22 = 95,
116
  H23 = 96,
117
  H24 = 97,
118
  H25 = 98,
119
  H26 = 99,
120
  H27 = 100,
121
  H28 = 101,
122
  H29 = 102,
123
  H30 = 103,
124
  H31 = 104,
125
  P0 = 105,
126
  P1 = 106,
127
  P2 = 107,
128
  P3 = 108,
129
  P4 = 109,
130
  P5 = 110,
131
  P6 = 111,
132
  P7 = 112,
133
  P8 = 113,
134
  P9 = 114,
135
  P10 = 115,
136
  P11 = 116,
137
  P12 = 117,
138
  P13 = 118,
139
  P14 = 119,
140
  P15 = 120,
141
  Q0 = 121,
142
  Q1 = 122,
143
  Q2 = 123,
144
  Q3 = 124,
145
  Q4 = 125,
146
  Q5 = 126,
147
  Q6 = 127,
148
  Q7 = 128,
149
  Q8 = 129,
150
  Q9 = 130,
151
  Q10 = 131,
152
  Q11 = 132,
153
  Q12 = 133,
154
  Q13 = 134,
155
  Q14 = 135,
156
  Q15 = 136,
157
  Q16 = 137,
158
  Q17 = 138,
159
  Q18 = 139,
160
  Q19 = 140,
161
  Q20 = 141,
162
  Q21 = 142,
163
  Q22 = 143,
164
  Q23 = 144,
165
  Q24 = 145,
166
  Q25 = 146,
167
  Q26 = 147,
168
  Q27 = 148,
169
  Q28 = 149,
170
  Q29 = 150,
171
  Q30 = 151,
172
  Q31 = 152,
173
  S0 = 153,
174
  S1 = 154,
175
  S2 = 155,
176
  S3 = 156,
177
  S4 = 157,
178
  S5 = 158,
179
  S6 = 159,
180
  S7 = 160,
181
  S8 = 161,
182
  S9 = 162,
183
  S10 = 163,
184
  S11 = 164,
185
  S12 = 165,
186
  S13 = 166,
187
  S14 = 167,
188
  S15 = 168,
189
  S16 = 169,
190
  S17 = 170,
191
  S18 = 171,
192
  S19 = 172,
193
  S20 = 173,
194
  S21 = 174,
195
  S22 = 175,
196
  S23 = 176,
197
  S24 = 177,
198
  S25 = 178,
199
  S26 = 179,
200
  S27 = 180,
201
  S28 = 181,
202
  S29 = 182,
203
  S30 = 183,
204
  S31 = 184,
205
  W0 = 185,
206
  W1 = 186,
207
  W2 = 187,
208
  W3 = 188,
209
  W4 = 189,
210
  W5 = 190,
211
  W6 = 191,
212
  W7 = 192,
213
  W8 = 193,
214
  W9 = 194,
215
  W10 = 195,
216
  W11 = 196,
217
  W12 = 197,
218
  W13 = 198,
219
  W14 = 199,
220
  W15 = 200,
221
  W16 = 201,
222
  W17 = 202,
223
  W18 = 203,
224
  W19 = 204,
225
  W20 = 205,
226
  W21 = 206,
227
  W22 = 207,
228
  W23 = 208,
229
  W24 = 209,
230
  W25 = 210,
231
  W26 = 211,
232
  W27 = 212,
233
  W28 = 213,
234
  W29 = 214,
235
  W30 = 215,
236
  X0 = 216,
237
  X1 = 217,
238
  X2 = 218,
239
  X3 = 219,
240
  X4 = 220,
241
  X5 = 221,
242
  X6 = 222,
243
  X7 = 223,
244
  X8 = 224,
245
  X9 = 225,
246
  X10 = 226,
247
  X11 = 227,
248
  X12 = 228,
249
  X13 = 229,
250
  X14 = 230,
251
  X15 = 231,
252
  X16 = 232,
253
  X17 = 233,
254
  X18 = 234,
255
  X19 = 235,
256
  X20 = 236,
257
  X21 = 237,
258
  X22 = 238,
259
  X23 = 239,
260
  X24 = 240,
261
  X25 = 241,
262
  X26 = 242,
263
  X27 = 243,
264
  X28 = 244,
265
  Z0 = 245,
266
  Z1 = 246,
267
  Z2 = 247,
268
  Z3 = 248,
269
  Z4 = 249,
270
  Z5 = 250,
271
  Z6 = 251,
272
  Z7 = 252,
273
  Z8 = 253,
274
  Z9 = 254,
275
  Z10 = 255,
276
  Z11 = 256,
277
  Z12 = 257,
278
  Z13 = 258,
279
  Z14 = 259,
280
  Z15 = 260,
281
  Z16 = 261,
282
  Z17 = 262,
283
  Z18 = 263,
284
  Z19 = 264,
285
  Z20 = 265,
286
  Z21 = 266,
287
  Z22 = 267,
288
  Z23 = 268,
289
  Z24 = 269,
290
  Z25 = 270,
291
  Z26 = 271,
292
  Z27 = 272,
293
  Z28 = 273,
294
  Z29 = 274,
295
  Z30 = 275,
296
  Z31 = 276,
297
  Z0_HI = 277,
298
  Z1_HI = 278,
299
  Z2_HI = 279,
300
  Z3_HI = 280,
301
  Z4_HI = 281,
302
  Z5_HI = 282,
303
  Z6_HI = 283,
304
  Z7_HI = 284,
305
  Z8_HI = 285,
306
  Z9_HI = 286,
307
  Z10_HI = 287,
308
  Z11_HI = 288,
309
  Z12_HI = 289,
310
  Z13_HI = 290,
311
  Z14_HI = 291,
312
  Z15_HI = 292,
313
  Z16_HI = 293,
314
  Z17_HI = 294,
315
  Z18_HI = 295,
316
  Z19_HI = 296,
317
  Z20_HI = 297,
318
  Z21_HI = 298,
319
  Z22_HI = 299,
320
  Z23_HI = 300,
321
  Z24_HI = 301,
322
  Z25_HI = 302,
323
  Z26_HI = 303,
324
  Z27_HI = 304,
325
  Z28_HI = 305,
326
  Z29_HI = 306,
327
  Z30_HI = 307,
328
  Z31_HI = 308,
329
  D0_D1 = 309,
330
  D1_D2 = 310,
331
  D2_D3 = 311,
332
  D3_D4 = 312,
333
  D4_D5 = 313,
334
  D5_D6 = 314,
335
  D6_D7 = 315,
336
  D7_D8 = 316,
337
  D8_D9 = 317,
338
  D9_D10 = 318,
339
  D10_D11 = 319,
340
  D11_D12 = 320,
341
  D12_D13 = 321,
342
  D13_D14 = 322,
343
  D14_D15 = 323,
344
  D15_D16 = 324,
345
  D16_D17 = 325,
346
  D17_D18 = 326,
347
  D18_D19 = 327,
348
  D19_D20 = 328,
349
  D20_D21 = 329,
350
  D21_D22 = 330,
351
  D22_D23 = 331,
352
  D23_D24 = 332,
353
  D24_D25 = 333,
354
  D25_D26 = 334,
355
  D26_D27 = 335,
356
  D27_D28 = 336,
357
  D28_D29 = 337,
358
  D29_D30 = 338,
359
  D30_D31 = 339,
360
  D31_D0 = 340,
361
  D0_D1_D2_D3 = 341,
362
  D1_D2_D3_D4 = 342,
363
  D2_D3_D4_D5 = 343,
364
  D3_D4_D5_D6 = 344,
365
  D4_D5_D6_D7 = 345,
366
  D5_D6_D7_D8 = 346,
367
  D6_D7_D8_D9 = 347,
368
  D7_D8_D9_D10 = 348,
369
  D8_D9_D10_D11 = 349,
370
  D9_D10_D11_D12 = 350,
371
  D10_D11_D12_D13 = 351,
372
  D11_D12_D13_D14 = 352,
373
  D12_D13_D14_D15 = 353,
374
  D13_D14_D15_D16 = 354,
375
  D14_D15_D16_D17 = 355,
376
  D15_D16_D17_D18 = 356,
377
  D16_D17_D18_D19 = 357,
378
  D17_D18_D19_D20 = 358,
379
  D18_D19_D20_D21 = 359,
380
  D19_D20_D21_D22 = 360,
381
  D20_D21_D22_D23 = 361,
382
  D21_D22_D23_D24 = 362,
383
  D22_D23_D24_D25 = 363,
384
  D23_D24_D25_D26 = 364,
385
  D24_D25_D26_D27 = 365,
386
  D25_D26_D27_D28 = 366,
387
  D26_D27_D28_D29 = 367,
388
  D27_D28_D29_D30 = 368,
389
  D28_D29_D30_D31 = 369,
390
  D29_D30_D31_D0 = 370,
391
  D30_D31_D0_D1 = 371,
392
  D31_D0_D1_D2 = 372,
393
  D0_D1_D2 = 373,
394
  D1_D2_D3 = 374,
395
  D2_D3_D4 = 375,
396
  D3_D4_D5 = 376,
397
  D4_D5_D6 = 377,
398
  D5_D6_D7 = 378,
399
  D6_D7_D8 = 379,
400
  D7_D8_D9 = 380,
401
  D8_D9_D10 = 381,
402
  D9_D10_D11 = 382,
403
  D10_D11_D12 = 383,
404
  D11_D12_D13 = 384,
405
  D12_D13_D14 = 385,
406
  D13_D14_D15 = 386,
407
  D14_D15_D16 = 387,
408
  D15_D16_D17 = 388,
409
  D16_D17_D18 = 389,
410
  D17_D18_D19 = 390,
411
  D18_D19_D20 = 391,
412
  D19_D20_D21 = 392,
413
  D20_D21_D22 = 393,
414
  D21_D22_D23 = 394,
415
  D22_D23_D24 = 395,
416
  D23_D24_D25 = 396,
417
  D24_D25_D26 = 397,
418
  D25_D26_D27 = 398,
419
  D26_D27_D28 = 399,
420
  D27_D28_D29 = 400,
421
  D28_D29_D30 = 401,
422
  D29_D30_D31 = 402,
423
  D30_D31_D0 = 403,
424
  D31_D0_D1 = 404,
425
  Q0_Q1 = 405,
426
  Q1_Q2 = 406,
427
  Q2_Q3 = 407,
428
  Q3_Q4 = 408,
429
  Q4_Q5 = 409,
430
  Q5_Q6 = 410,
431
  Q6_Q7 = 411,
432
  Q7_Q8 = 412,
433
  Q8_Q9 = 413,
434
  Q9_Q10 = 414,
435
  Q10_Q11 = 415,
436
  Q11_Q12 = 416,
437
  Q12_Q13 = 417,
438
  Q13_Q14 = 418,
439
  Q14_Q15 = 419,
440
  Q15_Q16 = 420,
441
  Q16_Q17 = 421,
442
  Q17_Q18 = 422,
443
  Q18_Q19 = 423,
444
  Q19_Q20 = 424,
445
  Q20_Q21 = 425,
446
  Q21_Q22 = 426,
447
  Q22_Q23 = 427,
448
  Q23_Q24 = 428,
449
  Q24_Q25 = 429,
450
  Q25_Q26 = 430,
451
  Q26_Q27 = 431,
452
  Q27_Q28 = 432,
453
  Q28_Q29 = 433,
454
  Q29_Q30 = 434,
455
  Q30_Q31 = 435,
456
  Q31_Q0 = 436,
457
  Q0_Q1_Q2_Q3 = 437,
458
  Q1_Q2_Q3_Q4 = 438,
459
  Q2_Q3_Q4_Q5 = 439,
460
  Q3_Q4_Q5_Q6 = 440,
461
  Q4_Q5_Q6_Q7 = 441,
462
  Q5_Q6_Q7_Q8 = 442,
463
  Q6_Q7_Q8_Q9 = 443,
464
  Q7_Q8_Q9_Q10 = 444,
465
  Q8_Q9_Q10_Q11 = 445,
466
  Q9_Q10_Q11_Q12 = 446,
467
  Q10_Q11_Q12_Q13 = 447,
468
  Q11_Q12_Q13_Q14 = 448,
469
  Q12_Q13_Q14_Q15 = 449,
470
  Q13_Q14_Q15_Q16 = 450,
471
  Q14_Q15_Q16_Q17 = 451,
472
  Q15_Q16_Q17_Q18 = 452,
473
  Q16_Q17_Q18_Q19 = 453,
474
  Q17_Q18_Q19_Q20 = 454,
475
  Q18_Q19_Q20_Q21 = 455,
476
  Q19_Q20_Q21_Q22 = 456,
477
  Q20_Q21_Q22_Q23 = 457,
478
  Q21_Q22_Q23_Q24 = 458,
479
  Q22_Q23_Q24_Q25 = 459,
480
  Q23_Q24_Q25_Q26 = 460,
481
  Q24_Q25_Q26_Q27 = 461,
482
  Q25_Q26_Q27_Q28 = 462,
483
  Q26_Q27_Q28_Q29 = 463,
484
  Q27_Q28_Q29_Q30 = 464,
485
  Q28_Q29_Q30_Q31 = 465,
486
  Q29_Q30_Q31_Q0 = 466,
487
  Q30_Q31_Q0_Q1 = 467,
488
  Q31_Q0_Q1_Q2 = 468,
489
  Q0_Q1_Q2 = 469,
490
  Q1_Q2_Q3 = 470,
491
  Q2_Q3_Q4 = 471,
492
  Q3_Q4_Q5 = 472,
493
  Q4_Q5_Q6 = 473,
494
  Q5_Q6_Q7 = 474,
495
  Q6_Q7_Q8 = 475,
496
  Q7_Q8_Q9 = 476,
497
  Q8_Q9_Q10 = 477,
498
  Q9_Q10_Q11 = 478,
499
  Q10_Q11_Q12 = 479,
500
  Q11_Q12_Q13 = 480,
501
  Q12_Q13_Q14 = 481,
502
  Q13_Q14_Q15 = 482,
503
  Q14_Q15_Q16 = 483,
504
  Q15_Q16_Q17 = 484,
505
  Q16_Q17_Q18 = 485,
506
  Q17_Q18_Q19 = 486,
507
  Q18_Q19_Q20 = 487,
508
  Q19_Q20_Q21 = 488,
509
  Q20_Q21_Q22 = 489,
510
  Q21_Q22_Q23 = 490,
511
  Q22_Q23_Q24 = 491,
512
  Q23_Q24_Q25 = 492,
513
  Q24_Q25_Q26 = 493,
514
  Q25_Q26_Q27 = 494,
515
  Q26_Q27_Q28 = 495,
516
  Q27_Q28_Q29 = 496,
517
  Q28_Q29_Q30 = 497,
518
  Q29_Q30_Q31 = 498,
519
  Q30_Q31_Q0 = 499,
520
  Q31_Q0_Q1 = 500,
521
  WZR_W0 = 501,
522
  W30_WZR = 502,
523
  W0_W1 = 503,
524
  W1_W2 = 504,
525
  W2_W3 = 505,
526
  W3_W4 = 506,
527
  W4_W5 = 507,
528
  W5_W6 = 508,
529
  W6_W7 = 509,
530
  W7_W8 = 510,
531
  W8_W9 = 511,
532
  W9_W10 = 512,
533
  W10_W11 = 513,
534
  W11_W12 = 514,
535
  W12_W13 = 515,
536
  W13_W14 = 516,
537
  W14_W15 = 517,
538
  W15_W16 = 518,
539
  W16_W17 = 519,
540
  W17_W18 = 520,
541
  W18_W19 = 521,
542
  W19_W20 = 522,
543
  W20_W21 = 523,
544
  W21_W22 = 524,
545
  W22_W23 = 525,
546
  W23_W24 = 526,
547
  W24_W25 = 527,
548
  W25_W26 = 528,
549
  W26_W27 = 529,
550
  W27_W28 = 530,
551
  W28_W29 = 531,
552
  W29_W30 = 532,
553
  FP_LR = 533,
554
  LR_XZR = 534,
555
  XZR_X0 = 535,
556
  X28_FP = 536,
557
  X0_X1 = 537,
558
  X1_X2 = 538,
559
  X2_X3 = 539,
560
  X3_X4 = 540,
561
  X4_X5 = 541,
562
  X5_X6 = 542,
563
  X6_X7 = 543,
564
  X7_X8 = 544,
565
  X8_X9 = 545,
566
  X9_X10 = 546,
567
  X10_X11 = 547,
568
  X11_X12 = 548,
569
  X12_X13 = 549,
570
  X13_X14 = 550,
571
  X14_X15 = 551,
572
  X15_X16 = 552,
573
  X16_X17 = 553,
574
  X17_X18 = 554,
575
  X18_X19 = 555,
576
  X19_X20 = 556,
577
  X20_X21 = 557,
578
  X21_X22 = 558,
579
  X22_X23 = 559,
580
  X23_X24 = 560,
581
  X24_X25 = 561,
582
  X25_X26 = 562,
583
  X26_X27 = 563,
584
  X27_X28 = 564,
585
  Z0_Z1 = 565,
586
  Z1_Z2 = 566,
587
  Z2_Z3 = 567,
588
  Z3_Z4 = 568,
589
  Z4_Z5 = 569,
590
  Z5_Z6 = 570,
591
  Z6_Z7 = 571,
592
  Z7_Z8 = 572,
593
  Z8_Z9 = 573,
594
  Z9_Z10 = 574,
595
  Z10_Z11 = 575,
596
  Z11_Z12 = 576,
597
  Z12_Z13 = 577,
598
  Z13_Z14 = 578,
599
  Z14_Z15 = 579,
600
  Z15_Z16 = 580,
601
  Z16_Z17 = 581,
602
  Z17_Z18 = 582,
603
  Z18_Z19 = 583,
604
  Z19_Z20 = 584,
605
  Z20_Z21 = 585,
606
  Z21_Z22 = 586,
607
  Z22_Z23 = 587,
608
  Z23_Z24 = 588,
609
  Z24_Z25 = 589,
610
  Z25_Z26 = 590,
611
  Z26_Z27 = 591,
612
  Z27_Z28 = 592,
613
  Z28_Z29 = 593,
614
  Z29_Z30 = 594,
615
  Z30_Z31 = 595,
616
  Z31_Z0 = 596,
617
  Z0_Z1_Z2_Z3 = 597,
618
  Z1_Z2_Z3_Z4 = 598,
619
  Z2_Z3_Z4_Z5 = 599,
620
  Z3_Z4_Z5_Z6 = 600,
621
  Z4_Z5_Z6_Z7 = 601,
622
  Z5_Z6_Z7_Z8 = 602,
623
  Z6_Z7_Z8_Z9 = 603,
624
  Z7_Z8_Z9_Z10 = 604,
625
  Z8_Z9_Z10_Z11 = 605,
626
  Z9_Z10_Z11_Z12 = 606,
627
  Z10_Z11_Z12_Z13 = 607,
628
  Z11_Z12_Z13_Z14 = 608,
629
  Z12_Z13_Z14_Z15 = 609,
630
  Z13_Z14_Z15_Z16 = 610,
631
  Z14_Z15_Z16_Z17 = 611,
632
  Z15_Z16_Z17_Z18 = 612,
633
  Z16_Z17_Z18_Z19 = 613,
634
  Z17_Z18_Z19_Z20 = 614,
635
  Z18_Z19_Z20_Z21 = 615,
636
  Z19_Z20_Z21_Z22 = 616,
637
  Z20_Z21_Z22_Z23 = 617,
638
  Z21_Z22_Z23_Z24 = 618,
639
  Z22_Z23_Z24_Z25 = 619,
640
  Z23_Z24_Z25_Z26 = 620,
641
  Z24_Z25_Z26_Z27 = 621,
642
  Z25_Z26_Z27_Z28 = 622,
643
  Z26_Z27_Z28_Z29 = 623,
644
  Z27_Z28_Z29_Z30 = 624,
645
  Z28_Z29_Z30_Z31 = 625,
646
  Z29_Z30_Z31_Z0 = 626,
647
  Z30_Z31_Z0_Z1 = 627,
648
  Z31_Z0_Z1_Z2 = 628,
649
  Z0_Z1_Z2 = 629,
650
  Z1_Z2_Z3 = 630,
651
  Z2_Z3_Z4 = 631,
652
  Z3_Z4_Z5 = 632,
653
  Z4_Z5_Z6 = 633,
654
  Z5_Z6_Z7 = 634,
655
  Z6_Z7_Z8 = 635,
656
  Z7_Z8_Z9 = 636,
657
  Z8_Z9_Z10 = 637,
658
  Z9_Z10_Z11 = 638,
659
  Z10_Z11_Z12 = 639,
660
  Z11_Z12_Z13 = 640,
661
  Z12_Z13_Z14 = 641,
662
  Z13_Z14_Z15 = 642,
663
  Z14_Z15_Z16 = 643,
664
  Z15_Z16_Z17 = 644,
665
  Z16_Z17_Z18 = 645,
666
  Z17_Z18_Z19 = 646,
667
  Z18_Z19_Z20 = 647,
668
  Z19_Z20_Z21 = 648,
669
  Z20_Z21_Z22 = 649,
670
  Z21_Z22_Z23 = 650,
671
  Z22_Z23_Z24 = 651,
672
  Z23_Z24_Z25 = 652,
673
  Z24_Z25_Z26 = 653,
674
  Z25_Z26_Z27 = 654,
675
  Z26_Z27_Z28 = 655,
676
  Z27_Z28_Z29 = 656,
677
  Z28_Z29_Z30 = 657,
678
  Z29_Z30_Z31 = 658,
679
  Z30_Z31_Z0 = 659,
680
  Z31_Z0_Z1 = 660,
681
  NUM_TARGET_REGS   // 661
682
};
683
} // end namespace AArch64
684
685
// Register classes
686
687
namespace AArch64 {
688
enum {
689
  FPR8RegClassID = 0,
690
  FPR16RegClassID = 1,
691
  PPRRegClassID = 2,
692
  PPR_3bRegClassID = 3,
693
  GPR32allRegClassID = 4,
694
  FPR32RegClassID = 5,
695
  GPR32RegClassID = 6,
696
  GPR32spRegClassID = 7,
697
  GPR32commonRegClassID = 8,
698
  CCRRegClassID = 9,
699
  GPR32sponlyRegClassID = 10,
700
  WSeqPairsClassRegClassID = 11,
701
  WSeqPairsClass_with_sube32_in_GPR32commonRegClassID = 12,
702
  WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 13,
703
  WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 14,
704
  GPR64allRegClassID = 15,
705
  FPR64RegClassID = 16,
706
  GPR64RegClassID = 17,
707
  GPR64spRegClassID = 18,
708
  GPR64commonRegClassID = 19,
709
  tcGPR64RegClassID = 20,
710
  GPR64sponlyRegClassID = 21,
711
  DDRegClassID = 22,
712
  XSeqPairsClassRegClassID = 23,
713
  XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID = 24,
714
  XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 25,
715
  XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 26,
716
  XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 27,
717
  XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 28,
718
  XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 29,
719
  FPR128RegClassID = 30,
720
  ZPRRegClassID = 31,
721
  FPR128_loRegClassID = 32,
722
  ZPR_4bRegClassID = 33,
723
  ZPR_3bRegClassID = 34,
724
  DDDRegClassID = 35,
725
  DDDDRegClassID = 36,
726
  QQRegClassID = 37,
727
  ZPR2RegClassID = 38,
728
  QQ_with_qsub0_in_FPR128_loRegClassID = 39,
729
  QQ_with_qsub1_in_FPR128_loRegClassID = 40,
730
  ZPR2_with_zsub1_in_ZPR_4bRegClassID = 41,
731
  ZPR2_with_zsub_in_FPR128_loRegClassID = 42,
732
  QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 43,
733
  ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 44,
734
  ZPR2_with_zsub0_in_ZPR_3bRegClassID = 45,
735
  ZPR2_with_zsub1_in_ZPR_3bRegClassID = 46,
736
  ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 47,
737
  QQQRegClassID = 48,
738
  ZPR3RegClassID = 49,
739
  QQQ_with_qsub0_in_FPR128_loRegClassID = 50,
740
  QQQ_with_qsub1_in_FPR128_loRegClassID = 51,
741
  QQQ_with_qsub2_in_FPR128_loRegClassID = 52,
742
  ZPR3_with_zsub1_in_ZPR_4bRegClassID = 53,
743
  ZPR3_with_zsub2_in_ZPR_4bRegClassID = 54,
744
  ZPR3_with_zsub_in_FPR128_loRegClassID = 55,
745
  QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 56,
746
  QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 57,
747
  ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 58,
748
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 59,
749
  QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 60,
750
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 61,
751
  ZPR3_with_zsub0_in_ZPR_3bRegClassID = 62,
752
  ZPR3_with_zsub1_in_ZPR_3bRegClassID = 63,
753
  ZPR3_with_zsub2_in_ZPR_3bRegClassID = 64,
754
  ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 65,
755
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 66,
756
  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 67,
757
  QQQQRegClassID = 68,
758
  ZPR4RegClassID = 69,
759
  QQQQ_with_qsub0_in_FPR128_loRegClassID = 70,
760
  QQQQ_with_qsub1_in_FPR128_loRegClassID = 71,
761
  QQQQ_with_qsub2_in_FPR128_loRegClassID = 72,
762
  QQQQ_with_qsub3_in_FPR128_loRegClassID = 73,
763
  ZPR4_with_zsub1_in_ZPR_4bRegClassID = 74,
764
  ZPR4_with_zsub2_in_ZPR_4bRegClassID = 75,
765
  ZPR4_with_zsub3_in_ZPR_4bRegClassID = 76,
766
  ZPR4_with_zsub_in_FPR128_loRegClassID = 77,
767
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 78,
768
  QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 79,
769
  QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 80,
770
  ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 81,
771
  ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 82,
772
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 83,
773
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 84,
774
  QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 85,
775
  ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 86,
776
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 87,
777
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 88,
778
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 89,
779
  ZPR4_with_zsub0_in_ZPR_3bRegClassID = 90,
780
  ZPR4_with_zsub1_in_ZPR_3bRegClassID = 91,
781
  ZPR4_with_zsub2_in_ZPR_3bRegClassID = 92,
782
  ZPR4_with_zsub3_in_ZPR_3bRegClassID = 93,
783
  ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 94,
784
  ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 95,
785
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 96,
786
  ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 97,
787
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 98,
788
  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 99,
789
790
  };
791
} // end namespace AArch64
792
793
794
// Register alternate name indices
795
796
namespace AArch64 {
797
enum {
798
  NoRegAltName, // 0
799
  vlist1, // 1
800
  vreg, // 2
801
  NUM_TARGET_REG_ALT_NAMES = 3
802
};
803
} // end namespace AArch64
804
805
806
// Subregister indices
807
808
namespace AArch64 {
809
enum {
810
  NoSubRegister,
811
  bsub, // 1
812
  dsub, // 2
813
  dsub0,  // 3
814
  dsub1,  // 4
815
  dsub2,  // 5
816
  dsub3,  // 6
817
  hsub, // 7
818
  qhisub, // 8
819
  qsub, // 9
820
  qsub0,  // 10
821
  qsub1,  // 11
822
  qsub2,  // 12
823
  qsub3,  // 13
824
  ssub, // 14
825
  sub_32, // 15
826
  sube32, // 16
827
  sube64, // 17
828
  subo32, // 18
829
  subo64, // 19
830
  zsub, // 20
831
  zsub0,  // 21
832
  zsub1,  // 22
833
  zsub2,  // 23
834
  zsub3,  // 24
835
  zsub_hi,  // 25
836
  dsub1_then_bsub,  // 26
837
  dsub1_then_hsub,  // 27
838
  dsub1_then_ssub,  // 28
839
  dsub3_then_bsub,  // 29
840
  dsub3_then_hsub,  // 30
841
  dsub3_then_ssub,  // 31
842
  dsub2_then_bsub,  // 32
843
  dsub2_then_hsub,  // 33
844
  dsub2_then_ssub,  // 34
845
  qsub1_then_bsub,  // 35
846
  qsub1_then_dsub,  // 36
847
  qsub1_then_hsub,  // 37
848
  qsub1_then_ssub,  // 38
849
  qsub3_then_bsub,  // 39
850
  qsub3_then_dsub,  // 40
851
  qsub3_then_hsub,  // 41
852
  qsub3_then_ssub,  // 42
853
  qsub2_then_bsub,  // 43
854
  qsub2_then_dsub,  // 44
855
  qsub2_then_hsub,  // 45
856
  qsub2_then_ssub,  // 46
857
  subo64_then_sub_32, // 47
858
  zsub1_then_bsub,  // 48
859
  zsub1_then_dsub,  // 49
860
  zsub1_then_hsub,  // 50
861
  zsub1_then_ssub,  // 51
862
  zsub1_then_zsub,  // 52
863
  zsub1_then_zsub_hi, // 53
864
  zsub3_then_bsub,  // 54
865
  zsub3_then_dsub,  // 55
866
  zsub3_then_hsub,  // 56
867
  zsub3_then_ssub,  // 57
868
  zsub3_then_zsub,  // 58
869
  zsub3_then_zsub_hi, // 59
870
  zsub2_then_bsub,  // 60
871
  zsub2_then_dsub,  // 61
872
  zsub2_then_hsub,  // 62
873
  zsub2_then_ssub,  // 63
874
  zsub2_then_zsub,  // 64
875
  zsub2_then_zsub_hi, // 65
876
  dsub0_dsub1,  // 66
877
  dsub0_dsub1_dsub2,  // 67
878
  dsub1_dsub2,  // 68
879
  dsub1_dsub2_dsub3,  // 69
880
  dsub2_dsub3,  // 70
881
  dsub_qsub1_then_dsub, // 71
882
  dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 72
883
  dsub_qsub1_then_dsub_qsub2_then_dsub, // 73
884
  qsub0_qsub1,  // 74
885
  qsub0_qsub1_qsub2,  // 75
886
  qsub1_qsub2,  // 76
887
  qsub1_qsub2_qsub3,  // 77
888
  qsub2_qsub3,  // 78
889
  qsub1_then_dsub_qsub2_then_dsub,  // 79
890
  qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,  // 80
891
  qsub2_then_dsub_qsub3_then_dsub,  // 81
892
  sub_32_subo64_then_sub_32,  // 82
893
  dsub_zsub1_then_dsub, // 83
894
  zsub_zsub1_then_zsub, // 84
895
  dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 85
896
  dsub_zsub1_then_dsub_zsub2_then_dsub, // 86
897
  zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 87
898
  zsub_zsub1_then_zsub_zsub2_then_zsub, // 88
899
  zsub0_zsub1,  // 89
900
  zsub0_zsub1_zsub2,  // 90
901
  zsub1_zsub2,  // 91
902
  zsub1_zsub2_zsub3,  // 92
903
  zsub2_zsub3,  // 93
904
  zsub1_then_dsub_zsub2_then_dsub,  // 94
905
  zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub,  // 95
906
  zsub1_then_zsub_zsub2_then_zsub,  // 96
907
  zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub,  // 97
908
  zsub2_then_dsub_zsub3_then_dsub,  // 98
909
  zsub2_then_zsub_zsub3_then_zsub,  // 99
910
  NUM_TARGET_SUBREGS
911
};
912
} // end namespace AArch64
913
914
} // end namespace llvm
915
916
#endif // GET_REGINFO_ENUM
917
918
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
919
|*                                                                            *|
920
|* MC Register Information                                                    *|
921
|*                                                                            *|
922
|* Automatically generated file, do not edit!                                 *|
923
|*                                                                            *|
924
\*===----------------------------------------------------------------------===*/
925
926
927
#ifdef GET_REGINFO_MC_DESC
928
#undef GET_REGINFO_MC_DESC
929
930
namespace llvm {
931
932
extern const MCPhysReg AArch64RegDiffLists[] = {
933
  /* 0 */ 64945, 1, 1, 1, 74, 1, 1, 1, 0,
934
  /* 9 */ 65105, 1, 1, 1, 0,
935
  /* 14 */ 65201, 1, 1, 1, 0,
936
  /* 19 */ 6, 29, 1, 1, 0,
937
  /* 24 */ 6, 29, 1, 1, 46, 29, 1, 1, 0,
938
  /* 33 */ 65324, 499, 30, 1, 1, 0,
939
  /* 39 */ 64913, 1, 1, 75, 1, 1, 0,
940
  /* 46 */ 65073, 1, 1, 0,
941
  /* 50 */ 65169, 1, 1, 0,
942
  /* 54 */ 6, 1, 29, 1, 0,
943
  /* 59 */ 6, 1, 29, 1, 46, 1, 29, 1, 0,
944
  /* 68 */ 6, 30, 1, 0,
945
  /* 72 */ 6, 30, 1, 46, 30, 1, 0,
946
  /* 79 */ 1, 493, 1, 32, 1, 0,
947
  /* 85 */ 31, 286, 1, 33, 1, 0,
948
  /* 91 */ 64977, 1, 76, 1, 0,
949
  /* 96 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0,
950
  /* 111 */ 320, 1, 0,
951
  /* 114 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0,
952
  /* 129 */ 526, 1, 0,
953
  /* 132 */ 530, 1, 0,
954
  /* 135 */ 65053, 1, 0,
955
  /* 138 */ 65087, 1, 0,
956
  /* 141 */ 65137, 1, 0,
957
  /* 144 */ 65218, 1, 0,
958
  /* 147 */ 65233, 1, 0,
959
  /* 150 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
960
  /* 183 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
961
  /* 203 */ 65504, 319, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
962
  /* 214 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
963
  /* 247 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
964
  /* 267 */ 65504, 320, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
965
  /* 278 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 128, 63, 65503, 34, 65503, 1, 0,
966
  /* 296 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
967
  /* 329 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
968
  /* 349 */ 65504, 319, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
969
  /* 360 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 97, 64, 65504, 63, 65503, 1, 0,
970
  /* 378 */ 65503, 1, 128, 65503, 1, 192, 65503, 1, 0,
971
  /* 387 */ 31, 285, 2, 32, 2, 0,
972
  /* 393 */ 319, 2, 0,
973
  /* 396 */ 65324, 529, 1, 1, 3, 0,
974
  /* 402 */ 2, 3, 0,
975
  /* 405 */ 531, 3, 0,
976
  /* 408 */ 65004, 3, 0,
977
  /* 411 */ 4, 0,
978
  /* 413 */ 5, 0,
979
  /* 415 */ 31, 286, 1, 5, 28, 0,
980
  /* 421 */ 292, 28, 0,
981
  /* 424 */ 6, 1, 1, 29, 0,
982
  /* 429 */ 6, 1, 1, 29, 46, 1, 1, 29, 0,
983
  /* 438 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
984
  /* 471 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
985
  /* 491 */ 65504, 319, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
986
  /* 502 */ 6, 1, 30, 0,
987
  /* 506 */ 6, 1, 30, 46, 1, 30, 0,
988
  /* 513 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 98, 63, 1, 65503, 1, 30, 0,
989
  /* 531 */ 6, 31, 0,
990
  /* 534 */ 6, 31, 46, 31, 0,
991
  /* 539 */ 65504, 31, 97, 65504, 31, 161, 65504, 31, 0,
992
  /* 548 */ 32, 0,
993
  /* 550 */ 34, 0,
994
  /* 552 */ 5, 49, 0,
995
  /* 555 */ 63936, 49, 0,
996
  /* 558 */ 65297, 77, 0,
997
  /* 561 */ 1, 81, 0,
998
  /* 564 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 31, 96, 0,
999
  /* 581 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 63, 96, 0,
1000
  /* 598 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 30, 96, 65504, 96, 96, 1, 65280, 96, 0,
1001
  /* 628 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 1, 65280, 96, 0,
1002
  /* 658 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 65505, 65280, 96, 0,
1003
  /* 688 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65441, 65311, 64, 32, 64, 65345, 96, 0,
1004
  /* 734 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65441, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
1005
  /* 780 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 29, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
1006
  /* 826 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
1007
  /* 872 */ 96, 160, 0,
1008
  /* 875 */ 65042, 178, 0,
1009
  /* 878 */ 212, 0,
1010
  /* 880 */ 65412, 65456, 112, 65456, 65472, 268, 0,
1011
  /* 887 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0,
1012
  /* 899 */ 65009, 65535, 209, 65505, 316, 0,
1013
  /* 905 */ 65005, 212, 65325, 212, 317, 0,
1014
  /* 911 */ 65244, 65505, 65325, 212, 317, 0,
1015
  /* 917 */ 65215, 65505, 32, 65505, 317, 0,
1016
  /* 923 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0,
1017
  /* 935 */ 65005, 212, 65329, 65535, 495, 0,
1018
  /* 941 */ 65323, 0,
1019
  /* 943 */ 65249, 65328, 0,
1020
  /* 946 */ 65342, 0,
1021
  /* 948 */ 65374, 0,
1022
  /* 950 */ 65389, 0,
1023
  /* 952 */ 65405, 0,
1024
  /* 954 */ 65421, 0,
1025
  /* 956 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0,
1026
  /* 977 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0,
1027
  /* 998 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0,
1028
  /* 1019 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
1029
  /* 1051 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0,
1030
  /* 1073 */ 65469, 0,
1031
  /* 1075 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0,
1032
  /* 1084 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0,
1033
  /* 1093 */ 65456, 112, 65456, 65472, 0,
1034
  /* 1098 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
1035
  /* 1130 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1036
  /* 1162 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1037
  /* 1194 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0,
1038
  /* 1216 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0,
1039
  /* 1238 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0,
1040
  /* 1260 */ 65501, 0,
1041
  /* 1262 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0,
1042
  /* 1277 */ 65533, 0,
1043
  /* 1279 */ 65535, 0,
1044
};
1045
1046
extern const LaneBitmask AArch64LaneMaskLists[] = {
1047
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
1048
  /* 2 */ LaneBitmask(0x00000080), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1049
  /* 5 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1050
  /* 10 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1051
  /* 14 */ LaneBitmask(0x00000400), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1052
  /* 17 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1053
  /* 22 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1054
  /* 26 */ LaneBitmask(0x00002000), LaneBitmask(0x00000008), LaneBitmask::getAll(),
1055
  /* 29 */ LaneBitmask(0x00000020), LaneBitmask(0x00000010), LaneBitmask::getAll(),
1056
  /* 32 */ LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
1057
  /* 35 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1058
  /* 38 */ LaneBitmask(0x00004000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1059
  /* 43 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1060
  /* 52 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1061
  /* 59 */ LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
1062
  /* 64 */ LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
1063
  /* 68 */ LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask::getAll(),
1064
  /* 73 */ LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask::getAll(),
1065
  /* 78 */ LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
1066
  /* 83 */ LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
1067
  /* 87 */ LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask::getAll(),
1068
  /* 92 */ LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask::getAll(),
1069
  /* 97 */ LaneBitmask(0x00000008), LaneBitmask(0x00002000), LaneBitmask::getAll(),
1070
  /* 100 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1071
  /* 105 */ LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1072
  /* 114 */ LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1073
  /* 121 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
1074
  /* 130 */ LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
1075
  /* 139 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
1076
};
1077
1078
extern const uint16_t AArch64SubRegIdxLists[] = {
1079
  /* 0 */ 2, 14, 7, 1, 0,
1080
  /* 5 */ 15, 0,
1081
  /* 7 */ 16, 18, 0,
1082
  /* 10 */ 20, 2, 14, 7, 1, 25, 0,
1083
  /* 17 */ 3, 14, 7, 1, 4, 28, 27, 26, 0,
1084
  /* 26 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 66, 68, 0,
1085
  /* 41 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 6, 31, 30, 29, 66, 67, 68, 69, 70, 0,
1086
  /* 63 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 71, 0,
1087
  /* 75 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 71, 73, 74, 76, 79, 0,
1088
  /* 96 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 13, 40, 42, 41, 39, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 0,
1089
  /* 128 */ 17, 15, 19, 47, 82, 0,
1090
  /* 134 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 83, 84, 0,
1091
  /* 151 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 83, 84, 86, 88, 89, 91, 94, 96, 0,
1092
  /* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0,
1093
};
1094
1095
extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = {
1096
  { 65535, 65535 },
1097
  { 0, 8 }, // bsub
1098
  { 0, 32 },  // dsub
1099
  { 0, 64 },  // dsub0
1100
  { 0, 64 },  // dsub1
1101
  { 0, 64 },  // dsub2
1102
  { 0, 64 },  // dsub3
1103
  { 0, 16 },  // hsub
1104
  { 0, 64 },  // qhisub
1105
  { 0, 64 },  // qsub
1106
  { 0, 128 }, // qsub0
1107
  { 0, 128 }, // qsub1
1108
  { 0, 128 }, // qsub2
1109
  { 0, 128 }, // qsub3
1110
  { 0, 32 },  // ssub
1111
  { 0, 32 },  // sub_32
1112
  { 0, 32 },  // sube32
1113
  { 0, 64 },  // sube64
1114
  { 0, 32 },  // subo32
1115
  { 0, 64 },  // subo64
1116
  { 0, 128 }, // zsub
1117
  { 65535, 128 }, // zsub0
1118
  { 65535, 128 }, // zsub1
1119
  { 65535, 128 }, // zsub2
1120
  { 65535, 128 }, // zsub3
1121
  { 0, 128 }, // zsub_hi
1122
  { 0, 8 }, // dsub1_then_bsub
1123
  { 0, 16 },  // dsub1_then_hsub
1124
  { 0, 32 },  // dsub1_then_ssub
1125
  { 0, 8 }, // dsub3_then_bsub
1126
  { 0, 16 },  // dsub3_then_hsub
1127
  { 0, 32 },  // dsub3_then_ssub
1128
  { 0, 8 }, // dsub2_then_bsub
1129
  { 0, 16 },  // dsub2_then_hsub
1130
  { 0, 32 },  // dsub2_then_ssub
1131
  { 0, 8 }, // qsub1_then_bsub
1132
  { 0, 32 },  // qsub1_then_dsub
1133
  { 0, 16 },  // qsub1_then_hsub
1134
  { 0, 32 },  // qsub1_then_ssub
1135
  { 0, 8 }, // qsub3_then_bsub
1136
  { 0, 32 },  // qsub3_then_dsub
1137
  { 0, 16 },  // qsub3_then_hsub
1138
  { 0, 32 },  // qsub3_then_ssub
1139
  { 0, 8 }, // qsub2_then_bsub
1140
  { 0, 32 },  // qsub2_then_dsub
1141
  { 0, 16 },  // qsub2_then_hsub
1142
  { 0, 32 },  // qsub2_then_ssub
1143
  { 0, 32 },  // subo64_then_sub_32
1144
  { 65535, 65535 }, // zsub1_then_bsub
1145
  { 65535, 65535 }, // zsub1_then_dsub
1146
  { 65535, 65535 }, // zsub1_then_hsub
1147
  { 65535, 65535 }, // zsub1_then_ssub
1148
  { 65535, 65535 }, // zsub1_then_zsub
1149
  { 65535, 65535 }, // zsub1_then_zsub_hi
1150
  { 65535, 65535 }, // zsub3_then_bsub
1151
  { 65535, 65535 }, // zsub3_then_dsub
1152
  { 65535, 65535 }, // zsub3_then_hsub
1153
  { 65535, 65535 }, // zsub3_then_ssub
1154
  { 65535, 65535 }, // zsub3_then_zsub
1155
  { 65535, 65535 }, // zsub3_then_zsub_hi
1156
  { 65535, 65535 }, // zsub2_then_bsub
1157
  { 65535, 65535 }, // zsub2_then_dsub
1158
  { 65535, 65535 }, // zsub2_then_hsub
1159
  { 65535, 65535 }, // zsub2_then_ssub
1160
  { 65535, 65535 }, // zsub2_then_zsub
1161
  { 65535, 65535 }, // zsub2_then_zsub_hi
1162
  { 65535, 128 }, // dsub0_dsub1
1163
  { 65535, 192 }, // dsub0_dsub1_dsub2
1164
  { 65535, 128 }, // dsub1_dsub2
1165
  { 65535, 192 }, // dsub1_dsub2_dsub3
1166
  { 65535, 128 }, // dsub2_dsub3
1167
  { 65535, 64 },  // dsub_qsub1_then_dsub
1168
  { 65535, 128 }, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
1169
  { 65535, 96 },  // dsub_qsub1_then_dsub_qsub2_then_dsub
1170
  { 65535, 256 }, // qsub0_qsub1
1171
  { 65535, 384 }, // qsub0_qsub1_qsub2
1172
  { 65535, 256 }, // qsub1_qsub2
1173
  { 65535, 384 }, // qsub1_qsub2_qsub3
1174
  { 65535, 256 }, // qsub2_qsub3
1175
  { 65535, 64 },  // qsub1_then_dsub_qsub2_then_dsub
1176
  { 65535, 96 },  // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
1177
  { 65535, 64 },  // qsub2_then_dsub_qsub3_then_dsub
1178
  { 65535, 64 },  // sub_32_subo64_then_sub_32
1179
  { 65535, 31 },  // dsub_zsub1_then_dsub
1180
  { 65535, 127 }, // zsub_zsub1_then_zsub
1181
  { 65535, 29 },  // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
1182
  { 65535, 30 },  // dsub_zsub1_then_dsub_zsub2_then_dsub
1183
  { 65535, 125 }, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
1184
  { 65535, 126 }, // zsub_zsub1_then_zsub_zsub2_then_zsub
1185
  { 65535, 256 }, // zsub0_zsub1
1186
  { 65535, 384 }, // zsub0_zsub1_zsub2
1187
  { 65535, 256 }, // zsub1_zsub2
1188
  { 65535, 384 }, // zsub1_zsub2_zsub3
1189
  { 65535, 256 }, // zsub2_zsub3
1190
  { 65535, 65534 }, // zsub1_then_dsub_zsub2_then_dsub
1191
  { 65535, 65533 }, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
1192
  { 65535, 65534 }, // zsub1_then_zsub_zsub2_then_zsub
1193
  { 65535, 65533 }, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
1194
  { 65535, 65534 }, // zsub2_then_dsub_zsub3_then_dsub
1195
  { 65535, 65534 }, // zsub2_then_zsub_zsub3_then_zsub
1196
};
1197
1198
extern const char AArch64RegStrings[] = {
1199
  /* 0 */ 'B', '1', '0', 0,
1200
  /* 4 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
1201
  /* 17 */ 'H', '1', '0', 0,
1202
  /* 21 */ 'P', '1', '0', 0,
1203
  /* 25 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
1204
  /* 38 */ 'S', '1', '0', 0,
1205
  /* 42 */ 'W', '9', '_', 'W', '1', '0', 0,
1206
  /* 49 */ 'X', '9', '_', 'X', '1', '0', 0,
1207
  /* 56 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0,
1208
  /* 69 */ 'B', '2', '0', 0,
1209
  /* 73 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
1210
  /* 89 */ 'H', '2', '0', 0,
1211
  /* 93 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
1212
  /* 109 */ 'S', '2', '0', 0,
1213
  /* 113 */ 'W', '1', '9', '_', 'W', '2', '0', 0,
1214
  /* 121 */ 'X', '1', '9', '_', 'X', '2', '0', 0,
1215
  /* 129 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0,
1216
  /* 145 */ 'B', '3', '0', 0,
1217
  /* 149 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
1218
  /* 165 */ 'H', '3', '0', 0,
1219
  /* 169 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
1220
  /* 185 */ 'S', '3', '0', 0,
1221
  /* 189 */ 'W', '2', '9', '_', 'W', '3', '0', 0,
1222
  /* 197 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0,
1223
  /* 213 */ 'B', '0', 0,
1224
  /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
1225
  /* 231 */ 'H', '0', 0,
1226
  /* 234 */ 'P', '0', 0,
1227
  /* 237 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
1228
  /* 252 */ 'S', '0', 0,
1229
  /* 255 */ 'W', 'Z', 'R', '_', 'W', '0', 0,
1230
  /* 262 */ 'X', 'Z', 'R', '_', 'X', '0', 0,
1231
  /* 269 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0,
1232
  /* 284 */ 'B', '1', '1', 0,
1233
  /* 288 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
1234
  /* 302 */ 'H', '1', '1', 0,
1235
  /* 306 */ 'P', '1', '1', 0,
1236
  /* 310 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
1237
  /* 324 */ 'S', '1', '1', 0,
1238
  /* 328 */ 'W', '1', '0', '_', 'W', '1', '1', 0,
1239
  /* 336 */ 'X', '1', '0', '_', 'X', '1', '1', 0,
1240
  /* 344 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0,
1241
  /* 358 */ 'B', '2', '1', 0,
1242
  /* 362 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
1243
  /* 378 */ 'H', '2', '1', 0,
1244
  /* 382 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
1245
  /* 398 */ 'S', '2', '1', 0,
1246
  /* 402 */ 'W', '2', '0', '_', 'W', '2', '1', 0,
1247
  /* 410 */ 'X', '2', '0', '_', 'X', '2', '1', 0,
1248
  /* 418 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0,
1249
  /* 434 */ 'B', '3', '1', 0,
1250
  /* 438 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
1251
  /* 454 */ 'H', '3', '1', 0,
1252
  /* 458 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
1253
  /* 474 */ 'S', '3', '1', 0,
1254
  /* 478 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0,
1255
  /* 494 */ 'B', '1', 0,
1256
  /* 497 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
1257
  /* 511 */ 'H', '1', 0,
1258
  /* 514 */ 'P', '1', 0,
1259
  /* 517 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
1260
  /* 531 */ 'S', '1', 0,
1261
  /* 534 */ 'W', '0', '_', 'W', '1', 0,
1262
  /* 540 */ 'X', '0', '_', 'X', '1', 0,
1263
  /* 546 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0,
1264
  /* 560 */ 'B', '1', '2', 0,
1265
  /* 564 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
1266
  /* 579 */ 'H', '1', '2', 0,
1267
  /* 583 */ 'P', '1', '2', 0,
1268
  /* 587 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
1269
  /* 602 */ 'S', '1', '2', 0,
1270
  /* 606 */ 'W', '1', '1', '_', 'W', '1', '2', 0,
1271
  /* 614 */ 'X', '1', '1', '_', 'X', '1', '2', 0,
1272
  /* 622 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0,
1273
  /* 637 */ 'B', '2', '2', 0,
1274
  /* 641 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
1275
  /* 657 */ 'H', '2', '2', 0,
1276
  /* 661 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
1277
  /* 677 */ 'S', '2', '2', 0,
1278
  /* 681 */ 'W', '2', '1', '_', 'W', '2', '2', 0,
1279
  /* 689 */ 'X', '2', '1', '_', 'X', '2', '2', 0,
1280
  /* 697 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0,
1281
  /* 713 */ 'B', '2', 0,
1282
  /* 716 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
1283
  /* 729 */ 'H', '2', 0,
1284
  /* 732 */ 'P', '2', 0,
1285
  /* 735 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
1286
  /* 748 */ 'S', '2', 0,
1287
  /* 751 */ 'W', '1', '_', 'W', '2', 0,
1288
  /* 757 */ 'X', '1', '_', 'X', '2', 0,
1289
  /* 763 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0,
1290
  /* 776 */ 'B', '1', '3', 0,
1291
  /* 780 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
1292
  /* 796 */ 'H', '1', '3', 0,
1293
  /* 800 */ 'P', '1', '3', 0,
1294
  /* 804 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
1295
  /* 820 */ 'S', '1', '3', 0,
1296
  /* 824 */ 'W', '1', '2', '_', 'W', '1', '3', 0,
1297
  /* 832 */ 'X', '1', '2', '_', 'X', '1', '3', 0,
1298
  /* 840 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0,
1299
  /* 856 */ 'B', '2', '3', 0,
1300
  /* 860 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
1301
  /* 876 */ 'H', '2', '3', 0,
1302
  /* 880 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
1303
  /* 896 */ 'S', '2', '3', 0,
1304
  /* 900 */ 'W', '2', '2', '_', 'W', '2', '3', 0,
1305
  /* 908 */ 'X', '2', '2', '_', 'X', '2', '3', 0,
1306
  /* 916 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0,
1307
  /* 932 */ 'B', '3', 0,
1308
  /* 935 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
1309
  /* 947 */ 'H', '3', 0,
1310
  /* 950 */ 'P', '3', 0,
1311
  /* 953 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
1312
  /* 965 */ 'S', '3', 0,
1313
  /* 968 */ 'W', '2', '_', 'W', '3', 0,
1314
  /* 974 */ 'X', '2', '_', 'X', '3', 0,
1315
  /* 980 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0,
1316
  /* 992 */ 'B', '1', '4', 0,
1317
  /* 996 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
1318
  /* 1012 */ 'H', '1', '4', 0,
1319
  /* 1016 */ 'P', '1', '4', 0,
1320
  /* 1020 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
1321
  /* 1036 */ 'S', '1', '4', 0,
1322
  /* 1040 */ 'W', '1', '3', '_', 'W', '1', '4', 0,
1323
  /* 1048 */ 'X', '1', '3', '_', 'X', '1', '4', 0,
1324
  /* 1056 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0,
1325
  /* 1072 */ 'B', '2', '4', 0,
1326
  /* 1076 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
1327
  /* 1092 */ 'H', '2', '4', 0,
1328
  /* 1096 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
1329
  /* 1112 */ 'S', '2', '4', 0,
1330
  /* 1116 */ 'W', '2', '3', '_', 'W', '2', '4', 0,
1331
  /* 1124 */ 'X', '2', '3', '_', 'X', '2', '4', 0,
1332
  /* 1132 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0,
1333
  /* 1148 */ 'B', '4', 0,
1334
  /* 1151 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
1335
  /* 1163 */ 'H', '4', 0,
1336
  /* 1166 */ 'P', '4', 0,
1337
  /* 1169 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
1338
  /* 1181 */ 'S', '4', 0,
1339
  /* 1184 */ 'W', '3', '_', 'W', '4', 0,
1340
  /* 1190 */ 'X', '3', '_', 'X', '4', 0,
1341
  /* 1196 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0,
1342
  /* 1208 */ 'B', '1', '5', 0,
1343
  /* 1212 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
1344
  /* 1228 */ 'H', '1', '5', 0,
1345
  /* 1232 */ 'P', '1', '5', 0,
1346
  /* 1236 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
1347
  /* 1252 */ 'S', '1', '5', 0,
1348
  /* 1256 */ 'W', '1', '4', '_', 'W', '1', '5', 0,
1349
  /* 1264 */ 'X', '1', '4', '_', 'X', '1', '5', 0,
1350
  /* 1272 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0,
1351
  /* 1288 */ 'B', '2', '5', 0,
1352
  /* 1292 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
1353
  /* 1308 */ 'H', '2', '5', 0,
1354
  /* 1312 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
1355
  /* 1328 */ 'S', '2', '5', 0,
1356
  /* 1332 */ 'W', '2', '4', '_', 'W', '2', '5', 0,
1357
  /* 1340 */ 'X', '2', '4', '_', 'X', '2', '5', 0,
1358
  /* 1348 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0,
1359
  /* 1364 */ 'B', '5', 0,
1360
  /* 1367 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
1361
  /* 1379 */ 'H', '5', 0,
1362
  /* 1382 */ 'P', '5', 0,
1363
  /* 1385 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
1364
  /* 1397 */ 'S', '5', 0,
1365
  /* 1400 */ 'W', '4', '_', 'W', '5', 0,
1366
  /* 1406 */ 'X', '4', '_', 'X', '5', 0,
1367
  /* 1412 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0,
1368
  /* 1424 */ 'B', '1', '6', 0,
1369
  /* 1428 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
1370
  /* 1444 */ 'H', '1', '6', 0,
1371
  /* 1448 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
1372
  /* 1464 */ 'S', '1', '6', 0,
1373
  /* 1468 */ 'W', '1', '5', '_', 'W', '1', '6', 0,
1374
  /* 1476 */ 'X', '1', '5', '_', 'X', '1', '6', 0,
1375
  /* 1484 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0,
1376
  /* 1500 */ 'B', '2', '6', 0,
1377
  /* 1504 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
1378
  /* 1520 */ 'H', '2', '6', 0,
1379
  /* 1524 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
1380
  /* 1540 */ 'S', '2', '6', 0,
1381
  /* 1544 */ 'W', '2', '5', '_', 'W', '2', '6', 0,
1382
  /* 1552 */ 'X', '2', '5', '_', 'X', '2', '6', 0,
1383
  /* 1560 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0,
1384
  /* 1576 */ 'B', '6', 0,
1385
  /* 1579 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
1386
  /* 1591 */ 'H', '6', 0,
1387
  /* 1594 */ 'P', '6', 0,
1388
  /* 1597 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
1389
  /* 1609 */ 'S', '6', 0,
1390
  /* 1612 */ 'W', '5', '_', 'W', '6', 0,
1391
  /* 1618 */ 'X', '5', '_', 'X', '6', 0,
1392
  /* 1624 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0,
1393
  /* 1636 */ 'B', '1', '7', 0,
1394
  /* 1640 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
1395
  /* 1656 */ 'H', '1', '7', 0,
1396
  /* 1660 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
1397
  /* 1676 */ 'S', '1', '7', 0,
1398
  /* 1680 */ 'W', '1', '6', '_', 'W', '1', '7', 0,
1399
  /* 1688 */ 'X', '1', '6', '_', 'X', '1', '7', 0,
1400
  /* 1696 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0,
1401
  /* 1712 */ 'B', '2', '7', 0,
1402
  /* 1716 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
1403
  /* 1732 */ 'H', '2', '7', 0,
1404
  /* 1736 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
1405
  /* 1752 */ 'S', '2', '7', 0,
1406
  /* 1756 */ 'W', '2', '6', '_', 'W', '2', '7', 0,
1407
  /* 1764 */ 'X', '2', '6', '_', 'X', '2', '7', 0,
1408
  /* 1772 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0,
1409
  /* 1788 */ 'B', '7', 0,
1410
  /* 1791 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
1411
  /* 1803 */ 'H', '7', 0,
1412
  /* 1806 */ 'P', '7', 0,
1413
  /* 1809 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
1414
  /* 1821 */ 'S', '7', 0,
1415
  /* 1824 */ 'W', '6', '_', 'W', '7', 0,
1416
  /* 1830 */ 'X', '6', '_', 'X', '7', 0,
1417
  /* 1836 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0,
1418
  /* 1848 */ 'B', '1', '8', 0,
1419
  /* 1852 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
1420
  /* 1868 */ 'H', '1', '8', 0,
1421
  /* 1872 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
1422
  /* 1888 */ 'S', '1', '8', 0,
1423
  /* 1892 */ 'W', '1', '7', '_', 'W', '1', '8', 0,
1424
  /* 1900 */ 'X', '1', '7', '_', 'X', '1', '8', 0,
1425
  /* 1908 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0,
1426
  /* 1924 */ 'B', '2', '8', 0,
1427
  /* 1928 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
1428
  /* 1944 */ 'H', '2', '8', 0,
1429
  /* 1948 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
1430
  /* 1964 */ 'S', '2', '8', 0,
1431
  /* 1968 */ 'W', '2', '7', '_', 'W', '2', '8', 0,
1432
  /* 1976 */ 'X', '2', '7', '_', 'X', '2', '8', 0,
1433
  /* 1984 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0,
1434
  /* 2000 */ 'B', '8', 0,
1435
  /* 2003 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
1436
  /* 2015 */ 'H', '8', 0,
1437
  /* 2018 */ 'P', '8', 0,
1438
  /* 2021 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
1439
  /* 2033 */ 'S', '8', 0,
1440
  /* 2036 */ 'W', '7', '_', 'W', '8', 0,
1441
  /* 2042 */ 'X', '7', '_', 'X', '8', 0,
1442
  /* 2048 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0,
1443
  /* 2060 */ 'B', '1', '9', 0,
1444
  /* 2064 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
1445
  /* 2080 */ 'H', '1', '9', 0,
1446
  /* 2084 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
1447
  /* 2100 */ 'S', '1', '9', 0,
1448
  /* 2104 */ 'W', '1', '8', '_', 'W', '1', '9', 0,
1449
  /* 2112 */ 'X', '1', '8', '_', 'X', '1', '9', 0,
1450
  /* 2120 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0,
1451
  /* 2136 */ 'B', '2', '9', 0,
1452
  /* 2140 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
1453
  /* 2156 */ 'H', '2', '9', 0,
1454
  /* 2160 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
1455
  /* 2176 */ 'S', '2', '9', 0,
1456
  /* 2180 */ 'W', '2', '8', '_', 'W', '2', '9', 0,
1457
  /* 2188 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0,
1458
  /* 2204 */ 'B', '9', 0,
1459
  /* 2207 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
1460
  /* 2219 */ 'H', '9', 0,
1461
  /* 2222 */ 'P', '9', 0,
1462
  /* 2225 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
1463
  /* 2237 */ 'S', '9', 0,
1464
  /* 2240 */ 'W', '8', '_', 'W', '9', 0,
1465
  /* 2246 */ 'X', '8', '_', 'X', '9', 0,
1466
  /* 2252 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0,
1467
  /* 2264 */ 'Z', '1', '0', '_', 'H', 'I', 0,
1468
  /* 2271 */ 'Z', '2', '0', '_', 'H', 'I', 0,
1469
  /* 2278 */ 'Z', '3', '0', '_', 'H', 'I', 0,
1470
  /* 2285 */ 'Z', '0', '_', 'H', 'I', 0,
1471
  /* 2291 */ 'Z', '1', '1', '_', 'H', 'I', 0,
1472
  /* 2298 */ 'Z', '2', '1', '_', 'H', 'I', 0,
1473
  /* 2305 */ 'Z', '3', '1', '_', 'H', 'I', 0,
1474
  /* 2312 */ 'Z', '1', '_', 'H', 'I', 0,
1475
  /* 2318 */ 'Z', '1', '2', '_', 'H', 'I', 0,
1476
  /* 2325 */ 'Z', '2', '2', '_', 'H', 'I', 0,
1477
  /* 2332 */ 'Z', '2', '_', 'H', 'I', 0,
1478
  /* 2338 */ 'Z', '1', '3', '_', 'H', 'I', 0,
1479
  /* 2345 */ 'Z', '2', '3', '_', 'H', 'I', 0,
1480
  /* 2352 */ 'Z', '3', '_', 'H', 'I', 0,
1481
  /* 2358 */ 'Z', '1', '4', '_', 'H', 'I', 0,
1482
  /* 2365 */ 'Z', '2', '4', '_', 'H', 'I', 0,
1483
  /* 2372 */ 'Z', '4', '_', 'H', 'I', 0,
1484
  /* 2378 */ 'Z', '1', '5', '_', 'H', 'I', 0,
1485
  /* 2385 */ 'Z', '2', '5', '_', 'H', 'I', 0,
1486
  /* 2392 */ 'Z', '5', '_', 'H', 'I', 0,
1487
  /* 2398 */ 'Z', '1', '6', '_', 'H', 'I', 0,
1488
  /* 2405 */ 'Z', '2', '6', '_', 'H', 'I', 0,
1489
  /* 2412 */ 'Z', '6', '_', 'H', 'I', 0,
1490
  /* 2418 */ 'Z', '1', '7', '_', 'H', 'I', 0,
1491
  /* 2425 */ 'Z', '2', '7', '_', 'H', 'I', 0,
1492
  /* 2432 */ 'Z', '7', '_', 'H', 'I', 0,
1493
  /* 2438 */ 'Z', '1', '8', '_', 'H', 'I', 0,
1494
  /* 2445 */ 'Z', '2', '8', '_', 'H', 'I', 0,
1495
  /* 2452 */ 'Z', '8', '_', 'H', 'I', 0,
1496
  /* 2458 */ 'Z', '1', '9', '_', 'H', 'I', 0,
1497
  /* 2465 */ 'Z', '2', '9', '_', 'H', 'I', 0,
1498
  /* 2472 */ 'Z', '9', '_', 'H', 'I', 0,
1499
  /* 2478 */ 'X', '2', '8', '_', 'F', 'P', 0,
1500
  /* 2485 */ 'W', 'S', 'P', 0,
1501
  /* 2489 */ 'F', 'F', 'R', 0,
1502
  /* 2493 */ 'F', 'P', '_', 'L', 'R', 0,
1503
  /* 2499 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0,
1504
  /* 2507 */ 'L', 'R', '_', 'X', 'Z', 'R', 0,
1505
  /* 2514 */ 'N', 'Z', 'C', 'V', 0,
1506
};
1507
1508
extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
1509
  { 3, 0, 0, 0, 0, 0 },
1510
  { 2489, 8, 8, 4, 20465, 0 },
1511
  { 2482, 878, 405, 5, 20465, 27 },
1512
  { 2496, 878, 132, 5, 20465, 27 },
1513
  { 2514, 8, 8, 4, 20465, 0 },
1514
  { 2486, 7, 8, 5, 6576, 27 },
1515
  { 2485, 8, 1279, 4, 6576, 0 },
1516
  { 2503, 8, 79, 4, 6608, 0 },
1517
  { 2510, 1279, 129, 5, 6608, 27 },
1518
  { 213, 8, 214, 4, 20433, 0 },
1519
  { 494, 8, 296, 4, 20433, 0 },
1520
  { 713, 8, 438, 4, 20433, 0 },
1521
  { 932, 8, 150, 4, 20433, 0 },
1522
  { 1148, 8, 150, 4, 20433, 0 },
1523
  { 1364, 8, 150, 4, 20433, 0 },
1524
  { 1576, 8, 150, 4, 20433, 0 },
1525
  { 1788, 8, 150, 4, 20433, 0 },
1526
  { 2000, 8, 150, 4, 20433, 0 },
1527
  { 2204, 8, 150, 4, 20433, 0 },
1528
  { 0, 8, 150, 4, 20433, 0 },
1529
  { 284, 8, 150, 4, 20433, 0 },
1530
  { 560, 8, 150, 4, 20433, 0 },
1531
  { 776, 8, 150, 4, 20433, 0 },
1532
  { 992, 8, 150, 4, 20433, 0 },
1533
  { 1208, 8, 150, 4, 20433, 0 },
1534
  { 1424, 8, 150, 4, 20433, 0 },
1535
  { 1636, 8, 150, 4, 20433, 0 },
1536
  { 1848, 8, 150, 4, 20433, 0 },
1537
  { 2060, 8, 150, 4, 20433, 0 },
1538
  { 69, 8, 150, 4, 20433, 0 },
1539
  { 358, 8, 150, 4, 20433, 0 },
1540
  { 637, 8, 150, 4, 20433, 0 },
1541
  { 856, 8, 150, 4, 20433, 0 },
1542
  { 1072, 8, 150, 4, 20433, 0 },
1543
  { 1288, 8, 150, 4, 20433, 0 },
1544
  { 1500, 8, 150, 4, 20433, 0 },
1545
  { 1712, 8, 150, 4, 20433, 0 },
1546
  { 1924, 8, 150, 4, 20433, 0 },
1547
  { 2136, 8, 150, 4, 20433, 0 },
1548
  { 145, 8, 150, 4, 20433, 0 },
1549
  { 434, 8, 150, 4, 20433, 0 },
1550
  { 228, 1080, 217, 1, 20161, 3 },
1551
  { 508, 1080, 299, 1, 20161, 3 },
1552
  { 726, 1080, 441, 1, 20161, 3 },
1553
  { 944, 1080, 153, 1, 20161, 3 },
1554
  { 1160, 1080, 153, 1, 20161, 3 },
1555
  { 1376, 1080, 153, 1, 20161, 3 },
1556
  { 1588, 1080, 153, 1, 20161, 3 },
1557
  { 1800, 1080, 153, 1, 20161, 3 },
1558
  { 2012, 1080, 153, 1, 20161, 3 },
1559
  { 2216, 1080, 153, 1, 20161, 3 },
1560
  { 13, 1080, 153, 1, 20161, 3 },
1561
  { 298, 1080, 153, 1, 20161, 3 },
1562
  { 575, 1080, 153, 1, 20161, 3 },
1563
  { 792, 1080, 153, 1, 20161, 3 },
1564
  { 1008, 1080, 153, 1, 20161, 3 },
1565
  { 1224, 1080, 153, 1, 20161, 3 },
1566
  { 1440, 1080, 153, 1, 20161, 3 },
1567
  { 1652, 1080, 153, 1, 20161, 3 },
1568
  { 1864, 1080, 153, 1, 20161, 3 },
1569
  { 2076, 1080, 153, 1, 20161, 3 },
1570
  { 85, 1080, 153, 1, 20161, 3 },
1571
  { 374, 1080, 153, 1, 20161, 3 },
1572
  { 653, 1080, 153, 1, 20161, 3 },
1573
  { 872, 1080, 153, 1, 20161, 3 },
1574
  { 1088, 1080, 153, 1, 20161, 3 },
1575
  { 1304, 1080, 153, 1, 20161, 3 },
1576
  { 1516, 1080, 153, 1, 20161, 3 },
1577
  { 1728, 1080, 153, 1, 20161, 3 },
1578
  { 1940, 1080, 153, 1, 20161, 3 },
1579
  { 2152, 1080, 153, 1, 20161, 3 },
1580
  { 161, 1080, 153, 1, 20161, 3 },
1581
  { 450, 1080, 153, 1, 20161, 3 },
1582
  { 231, 1082, 215, 3, 17169, 3 },
1583
  { 511, 1082, 297, 3, 17169, 3 },
1584
  { 729, 1082, 439, 3, 17169, 3 },
1585
  { 947, 1082, 151, 3, 17169, 3 },
1586
  { 1163, 1082, 151, 3, 17169, 3 },
1587
  { 1379, 1082, 151, 3, 17169, 3 },
1588
  { 1591, 1082, 151, 3, 17169, 3 },
1589
  { 1803, 1082, 151, 3, 17169, 3 },
1590
  { 2015, 1082, 151, 3, 17169, 3 },
1591
  { 2219, 1082, 151, 3, 17169, 3 },
1592
  { 17, 1082, 151, 3, 17169, 3 },
1593
  { 302, 1082, 151, 3, 17169, 3 },
1594
  { 579, 1082, 151, 3, 17169, 3 },
1595
  { 796, 1082, 151, 3, 17169, 3 },
1596
  { 1012, 1082, 151, 3, 17169, 3 },
1597
  { 1228, 1082, 151, 3, 17169, 3 },
1598
  { 1444, 1082, 151, 3, 17169, 3 },
1599
  { 1656, 1082, 151, 3, 17169, 3 },
1600
  { 1868, 1082, 151, 3, 17169, 3 },
1601
  { 2080, 1082, 151, 3, 17169, 3 },
1602
  { 89, 1082, 151, 3, 17169, 3 },
1603
  { 378, 1082, 151, 3, 17169, 3 },
1604
  { 657, 1082, 151, 3, 17169, 3 },
1605
  { 876, 1082, 151, 3, 17169, 3 },
1606
  { 1092, 1082, 151, 3, 17169, 3 },
1607
  { 1308, 1082, 151, 3, 17169, 3 },
1608
  { 1520, 1082, 151, 3, 17169, 3 },
1609
  { 1732, 1082, 151, 3, 17169, 3 },
1610
  { 1944, 1082, 151, 3, 17169, 3 },
1611
  { 2156, 1082, 151, 3, 17169, 3 },
1612
  { 165, 1082, 151, 3, 17169, 3 },
1613
  { 454, 1082, 151, 3, 17169, 3 },
1614
  { 234, 8, 8, 4, 17169, 0 },
1615
  { 514, 8, 8, 4, 17169, 0 },
1616
  { 732, 8, 8, 4, 17169, 0 },
1617
  { 950, 8, 8, 4, 17169, 0 },
1618
  { 1166, 8, 8, 4, 17169, 0 },
1619
  { 1382, 8, 8, 4, 17169, 0 },
1620
  { 1594, 8, 8, 4, 17169, 0 },
1621
  { 1806, 8, 8, 4, 17169, 0 },
1622
  { 2018, 8, 8, 4, 17169, 0 },
1623
  { 2222, 8, 8, 4, 17169, 0 },
1624
  { 21, 8, 8, 4, 17169, 0 },
1625
  { 306, 8, 8, 4, 17169, 0 },
1626
  { 583, 8, 8, 4, 17169, 0 },
1627
  { 800, 8, 8, 4, 17169, 0 },
1628
  { 1016, 8, 8, 4, 17169, 0 },
1629
  { 1232, 8, 8, 4, 17169, 0 },
1630
  { 249, 1093, 247, 0, 15265, 3 },
1631
  { 528, 1093, 329, 0, 15265, 3 },
1632
  { 745, 1093, 471, 0, 15265, 3 },
1633
  { 962, 1093, 183, 0, 15265, 3 },
1634
  { 1178, 1093, 183, 0, 15265, 3 },
1635
  { 1394, 1093, 183, 0, 15265, 3 },
1636
  { 1606, 1093, 183, 0, 15265, 3 },
1637
  { 1818, 1093, 183, 0, 15265, 3 },
1638
  { 2030, 1093, 183, 0, 15265, 3 },
1639
  { 2234, 1093, 183, 0, 15265, 3 },
1640
  { 34, 1093, 183, 0, 15265, 3 },
1641
  { 320, 1093, 183, 0, 15265, 3 },
1642
  { 598, 1093, 183, 0, 15265, 3 },
1643
  { 816, 1093, 183, 0, 15265, 3 },
1644
  { 1032, 1093, 183, 0, 15265, 3 },
1645
  { 1248, 1093, 183, 0, 15265, 3 },
1646
  { 1460, 1093, 183, 0, 15265, 3 },
1647
  { 1672, 1093, 183, 0, 15265, 3 },
1648
  { 1884, 1093, 183, 0, 15265, 3 },
1649
  { 2096, 1093, 183, 0, 15265, 3 },
1650
  { 105, 1093, 183, 0, 15265, 3 },
1651
  { 394, 1093, 183, 0, 15265, 3 },
1652
  { 673, 1093, 183, 0, 15265, 3 },
1653
  { 892, 1093, 183, 0, 15265, 3 },
1654
  { 1108, 1093, 183, 0, 15265, 3 },
1655
  { 1324, 1093, 183, 0, 15265, 3 },
1656
  { 1536, 1093, 183, 0, 15265, 3 },
1657
  { 1748, 1093, 183, 0, 15265, 3 },
1658
  { 1960, 1093, 183, 0, 15265, 3 },
1659
  { 2172, 1093, 183, 0, 15265, 3 },
1660
  { 181, 1093, 183, 0, 15265, 3 },
1661
  { 470, 1093, 183, 0, 15265, 3 },
1662
  { 252, 1081, 216, 2, 15201, 3 },
1663
  { 531, 1081, 298, 2, 15201, 3 },
1664
  { 748, 1081, 440, 2, 15201, 3 },
1665
  { 965, 1081, 152, 2, 15201, 3 },
1666
  { 1181, 1081, 152, 2, 15201, 3 },
1667
  { 1397, 1081, 152, 2, 15201, 3 },
1668
  { 1609, 1081, 152, 2, 15201, 3 },
1669
  { 1821, 1081, 152, 2, 15201, 3 },
1670
  { 2033, 1081, 152, 2, 15201, 3 },
1671
  { 2237, 1081, 152, 2, 15201, 3 },
1672
  { 38, 1081, 152, 2, 15201, 3 },
1673
  { 324, 1081, 152, 2, 15201, 3 },
1674
  { 602, 1081, 152, 2, 15201, 3 },
1675
  { 820, 1081, 152, 2, 15201, 3 },
1676
  { 1036, 1081, 152, 2, 15201, 3 },
1677
  { 1252, 1081, 152, 2, 15201, 3 },
1678
  { 1464, 1081, 152, 2, 15201, 3 },
1679
  { 1676, 1081, 152, 2, 15201, 3 },
1680
  { 1888, 1081, 152, 2, 15201, 3 },
1681
  { 2100, 1081, 152, 2, 15201, 3 },
1682
  { 109, 1081, 152, 2, 15201, 3 },
1683
  { 398, 1081, 152, 2, 15201, 3 },
1684
  { 677, 1081, 152, 2, 15201, 3 },
1685
  { 896, 1081, 152, 2, 15201, 3 },
1686
  { 1112, 1081, 152, 2, 15201, 3 },
1687
  { 1328, 1081, 152, 2, 15201, 3 },
1688
  { 1540, 1081, 152, 2, 15201, 3 },
1689
  { 1752, 1081, 152, 2, 15201, 3 },
1690
  { 1964, 1081, 152, 2, 15201, 3 },
1691
  { 2176, 1081, 152, 2, 15201, 3 },
1692
  { 185, 1081, 152, 2, 15201, 3 },
1693
  { 474, 1081, 152, 2, 15201, 3 },
1694
  { 259, 8, 387, 4, 15233, 0 },
1695
  { 537, 8, 85, 4, 15233, 0 },
1696
  { 754, 8, 85, 4, 15233, 0 },
1697
  { 971, 8, 85, 4, 15233, 0 },
1698
  { 1187, 8, 85, 4, 15233, 0 },
1699
  { 1403, 8, 85, 4, 15233, 0 },
1700
  { 1615, 8, 85, 4, 15233, 0 },
1701
  { 1827, 8, 85, 4, 15233, 0 },
1702
  { 2039, 8, 85, 4, 15233, 0 },
1703
  { 2243, 8, 85, 4, 15233, 0 },
1704
  { 45, 8, 85, 4, 15233, 0 },
1705
  { 332, 8, 85, 4, 15233, 0 },
1706
  { 610, 8, 85, 4, 15233, 0 },
1707
  { 828, 8, 85, 4, 15233, 0 },
1708
  { 1044, 8, 85, 4, 15233, 0 },
1709
  { 1260, 8, 85, 4, 15233, 0 },
1710
  { 1472, 8, 85, 4, 15233, 0 },
1711
  { 1684, 8, 85, 4, 15233, 0 },
1712
  { 1896, 8, 85, 4, 15233, 0 },
1713
  { 2108, 8, 85, 4, 15233, 0 },
1714
  { 117, 8, 85, 4, 15233, 0 },
1715
  { 406, 8, 85, 4, 15233, 0 },
1716
  { 685, 8, 85, 4, 15233, 0 },
1717
  { 904, 8, 85, 4, 15233, 0 },
1718
  { 1120, 8, 85, 4, 15233, 0 },
1719
  { 1336, 8, 85, 4, 15233, 0 },
1720
  { 1548, 8, 85, 4, 15233, 0 },
1721
  { 1760, 8, 85, 4, 15233, 0 },
1722
  { 1972, 8, 415, 4, 15233, 0 },
1723
  { 2184, 8, 396, 4, 15057, 0 },
1724
  { 193, 8, 33, 4, 15057, 0 },
1725
  { 266, 1275, 393, 5, 15169, 27 },
1726
  { 543, 1275, 111, 5, 15169, 27 },
1727
  { 760, 1275, 111, 5, 15169, 27 },
1728
  { 977, 1275, 111, 5, 15169, 27 },
1729
  { 1193, 1275, 111, 5, 15169, 27 },
1730
  { 1409, 1275, 111, 5, 15169, 27 },
1731
  { 1621, 1275, 111, 5, 15169, 27 },
1732
  { 1833, 1275, 111, 5, 15169, 27 },
1733
  { 2045, 1275, 111, 5, 15169, 27 },
1734
  { 2249, 1275, 111, 5, 15169, 27 },
1735
  { 52, 1275, 111, 5, 15169, 27 },
1736
  { 340, 1275, 111, 5, 15169, 27 },
1737
  { 618, 1275, 111, 5, 15169, 27 },
1738
  { 836, 1275, 111, 5, 15169, 27 },
1739
  { 1052, 1275, 111, 5, 15169, 27 },
1740
  { 1268, 1275, 111, 5, 15169, 27 },
1741
  { 1480, 1275, 111, 5, 15169, 27 },
1742
  { 1692, 1275, 111, 5, 15169, 27 },
1743
  { 1904, 1275, 111, 5, 15169, 27 },
1744
  { 2116, 1275, 111, 5, 15169, 27 },
1745
  { 125, 1275, 111, 5, 15169, 27 },
1746
  { 414, 1275, 111, 5, 15169, 27 },
1747
  { 693, 1275, 111, 5, 15169, 27 },
1748
  { 912, 1275, 111, 5, 15169, 27 },
1749
  { 1128, 1275, 111, 5, 15169, 27 },
1750
  { 1344, 1275, 111, 5, 15169, 27 },
1751
  { 1556, 1275, 111, 5, 15169, 27 },
1752
  { 1768, 1275, 111, 5, 15169, 27 },
1753
  { 1980, 1275, 421, 5, 15169, 27 },
1754
  { 281, 880, 268, 10, 8929, 35 },
1755
  { 557, 880, 350, 10, 8929, 35 },
1756
  { 773, 880, 492, 10, 8929, 35 },
1757
  { 989, 880, 204, 10, 8929, 35 },
1758
  { 1205, 880, 204, 10, 8929, 35 },
1759
  { 1421, 880, 204, 10, 8929, 35 },
1760
  { 1633, 880, 204, 10, 8929, 35 },
1761
  { 1845, 880, 204, 10, 8929, 35 },
1762
  { 2057, 880, 204, 10, 8929, 35 },
1763
  { 2261, 880, 204, 10, 8929, 35 },
1764
  { 65, 880, 204, 10, 8929, 35 },
1765
  { 354, 880, 204, 10, 8929, 35 },
1766
  { 633, 880, 204, 10, 8929, 35 },
1767
  { 852, 880, 204, 10, 8929, 35 },
1768
  { 1068, 880, 204, 10, 8929, 35 },
1769
  { 1284, 880, 204, 10, 8929, 35 },
1770
  { 1496, 880, 204, 10, 8929, 35 },
1771
  { 1708, 880, 204, 10, 8929, 35 },
1772
  { 1920, 880, 204, 10, 8929, 35 },
1773
  { 2132, 880, 204, 10, 8929, 35 },
1774
  { 141, 880, 204, 10, 8929, 35 },
1775
  { 430, 880, 204, 10, 8929, 35 },
1776
  { 709, 880, 204, 10, 8929, 35 },
1777
  { 928, 880, 204, 10, 8929, 35 },
1778
  { 1144, 880, 204, 10, 8929, 35 },
1779
  { 1360, 880, 204, 10, 8929, 35 },
1780
  { 1572, 880, 204, 10, 8929, 35 },
1781
  { 1784, 880, 204, 10, 8929, 35 },
1782
  { 1996, 880, 204, 10, 8929, 35 },
1783
  { 2200, 880, 204, 10, 8929, 35 },
1784
  { 209, 880, 204, 10, 8929, 35 },
1785
  { 490, 880, 204, 10, 8929, 35 },
1786
  { 2285, 8, 267, 4, 15137, 0 },
1787
  { 2312, 8, 349, 4, 15137, 0 },
1788
  { 2332, 8, 491, 4, 15137, 0 },
1789
  { 2352, 8, 203, 4, 15137, 0 },
1790
  { 2372, 8, 203, 4, 15137, 0 },
1791
  { 2392, 8, 203, 4, 15137, 0 },
1792
  { 2412, 8, 203, 4, 15137, 0 },
1793
  { 2432, 8, 203, 4, 15137, 0 },
1794
  { 2452, 8, 203, 4, 15137, 0 },
1795
  { 2472, 8, 203, 4, 15137, 0 },
1796
  { 2264, 8, 203, 4, 15137, 0 },
1797
  { 2291, 8, 203, 4, 15137, 0 },
1798
  { 2318, 8, 203, 4, 15137, 0 },
1799
  { 2338, 8, 203, 4, 15137, 0 },
1800
  { 2358, 8, 203, 4, 15137, 0 },
1801
  { 2378, 8, 203, 4, 15137, 0 },
1802
  { 2398, 8, 203, 4, 15137, 0 },
1803
  { 2418, 8, 203, 4, 15137, 0 },
1804
  { 2438, 8, 203, 4, 15137, 0 },
1805
  { 2458, 8, 203, 4, 15137, 0 },
1806
  { 2271, 8, 203, 4, 15137, 0 },
1807
  { 2298, 8, 203, 4, 15137, 0 },
1808
  { 2325, 8, 203, 4, 15137, 0 },
1809
  { 2345, 8, 203, 4, 15137, 0 },
1810
  { 2365, 8, 203, 4, 15137, 0 },
1811
  { 2385, 8, 203, 4, 15137, 0 },
1812
  { 2405, 8, 203, 4, 15137, 0 },
1813
  { 2425, 8, 203, 4, 15137, 0 },
1814
  { 2445, 8, 203, 4, 15137, 0 },
1815
  { 2465, 8, 203, 4, 15137, 0 },
1816
  { 2278, 8, 203, 4, 15137, 0 },
1817
  { 2305, 8, 203, 4, 15137, 0 },
1818
  { 505, 1084, 360, 17, 2353, 61 },
1819
  { 723, 1084, 513, 17, 2353, 61 },
1820
  { 941, 1084, 278, 17, 2353, 61 },
1821
  { 1157, 1084, 278, 17, 2353, 61 },
1822
  { 1373, 1084, 278, 17, 2353, 61 },
1823
  { 1585, 1084, 278, 17, 2353, 61 },
1824
  { 1797, 1084, 278, 17, 2353, 61 },
1825
  { 2009, 1084, 278, 17, 2353, 61 },
1826
  { 2213, 1084, 278, 17, 2353, 61 },
1827
  { 10, 1084, 278, 17, 2353, 61 },
1828
  { 294, 1084, 278, 17, 2353, 61 },
1829
  { 571, 1084, 278, 17, 2353, 61 },
1830
  { 788, 1084, 278, 17, 2353, 61 },
1831
  { 1004, 1084, 278, 17, 2353, 61 },
1832
  { 1220, 1084, 278, 17, 2353, 61 },
1833
  { 1436, 1084, 278, 17, 2353, 61 },
1834
  { 1648, 1084, 278, 17, 2353, 61 },
1835
  { 1860, 1084, 278, 17, 2353, 61 },
1836
  { 2072, 1084, 278, 17, 2353, 61 },
1837
  { 81, 1084, 278, 17, 2353, 61 },
1838
  { 370, 1084, 278, 17, 2353, 61 },
1839
  { 649, 1084, 278, 17, 2353, 61 },
1840
  { 868, 1084, 278, 17, 2353, 61 },
1841
  { 1084, 1084, 278, 17, 2353, 61 },
1842
  { 1300, 1084, 278, 17, 2353, 61 },
1843
  { 1512, 1084, 278, 17, 2353, 61 },
1844
  { 1724, 1084, 278, 17, 2353, 61 },
1845
  { 1936, 1084, 278, 17, 2353, 61 },
1846
  { 2148, 1084, 278, 17, 2353, 61 },
1847
  { 157, 1084, 278, 17, 2353, 61 },
1848
  { 446, 1084, 278, 17, 2353, 61 },
1849
  { 224, 1075, 278, 17, 8496, 2 },
1850
  { 935, 1216, 872, 41, 225, 68 },
1851
  { 1151, 1216, 872, 41, 225, 68 },
1852
  { 1367, 1216, 872, 41, 225, 68 },
1853
  { 1579, 1216, 872, 41, 225, 68 },
1854
  { 1791, 1216, 872, 41, 225, 68 },
1855
  { 2003, 1216, 872, 41, 225, 68 },
1856
  { 2207, 1216, 872, 41, 225, 68 },
1857
  { 4, 1216, 872, 41, 225, 68 },
1858
  { 288, 1216, 872, 41, 225, 68 },
1859
  { 564, 1216, 872, 41, 225, 68 },
1860
  { 780, 1216, 872, 41, 225, 68 },
1861
  { 996, 1216, 872, 41, 225, 68 },
1862
  { 1212, 1216, 872, 41, 225, 68 },
1863
  { 1428, 1216, 872, 41, 225, 68 },
1864
  { 1640, 1216, 872, 41, 225, 68 },
1865
  { 1852, 1216, 872, 41, 225, 68 },
1866
  { 2064, 1216, 872, 41, 225, 68 },
1867
  { 73, 1216, 872, 41, 225, 68 },
1868
  { 362, 1216, 872, 41, 225, 68 },
1869
  { 641, 1216, 872, 41, 225, 68 },
1870
  { 860, 1216, 872, 41, 225, 68 },
1871
  { 1076, 1216, 872, 41, 225, 68 },
1872
  { 1292, 1216, 872, 41, 225, 68 },
1873
  { 1504, 1216, 872, 41, 225, 68 },
1874
  { 1716, 1216, 872, 41, 225, 68 },
1875
  { 1928, 1216, 872, 41, 225, 68 },
1876
  { 2140, 1216, 872, 41, 225, 68 },
1877
  { 149, 1216, 872, 41, 225, 68 },
1878
  { 438, 1216, 872, 41, 225, 68 },
1879
  { 216, 1238, 872, 41, 304, 73 },
1880
  { 497, 1051, 872, 41, 864, 59 },
1881
  { 716, 1194, 872, 41, 6784, 5 },
1882
  { 720, 96, 539, 26, 801, 74 },
1883
  { 938, 96, 378, 26, 801, 74 },
1884
  { 1154, 96, 378, 26, 801, 74 },
1885
  { 1370, 96, 378, 26, 801, 74 },
1886
  { 1582, 96, 378, 26, 801, 74 },
1887
  { 1794, 96, 378, 26, 801, 74 },
1888
  { 2006, 96, 378, 26, 801, 74 },
1889
  { 2210, 96, 378, 26, 801, 74 },
1890
  { 7, 96, 378, 26, 801, 74 },
1891
  { 291, 96, 378, 26, 801, 74 },
1892
  { 567, 96, 378, 26, 801, 74 },
1893
  { 784, 96, 378, 26, 801, 74 },
1894
  { 1000, 96, 378, 26, 801, 74 },
1895
  { 1216, 96, 378, 26, 801, 74 },
1896
  { 1432, 96, 378, 26, 801, 74 },
1897
  { 1644, 96, 378, 26, 801, 74 },
1898
  { 1856, 96, 378, 26, 801, 74 },
1899
  { 2068, 96, 378, 26, 801, 74 },
1900
  { 77, 96, 378, 26, 801, 74 },
1901
  { 366, 96, 378, 26, 801, 74 },
1902
  { 645, 96, 378, 26, 801, 74 },
1903
  { 864, 96, 378, 26, 801, 74 },
1904
  { 1080, 96, 378, 26, 801, 74 },
1905
  { 1296, 96, 378, 26, 801, 74 },
1906
  { 1508, 96, 378, 26, 801, 74 },
1907
  { 1720, 96, 378, 26, 801, 74 },
1908
  { 1932, 96, 378, 26, 801, 74 },
1909
  { 2144, 96, 378, 26, 801, 74 },
1910
  { 153, 96, 378, 26, 801, 74 },
1911
  { 442, 96, 378, 26, 801, 74 },
1912
  { 220, 114, 378, 26, 1088, 64 },
1913
  { 501, 1262, 378, 26, 8032, 10 },
1914
  { 525, 887, 366, 63, 2257, 80 },
1915
  { 742, 887, 519, 63, 2257, 80 },
1916
  { 959, 887, 284, 63, 2257, 80 },
1917
  { 1175, 887, 284, 63, 2257, 80 },
1918
  { 1391, 887, 284, 63, 2257, 80 },
1919
  { 1603, 887, 284, 63, 2257, 80 },
1920
  { 1815, 887, 284, 63, 2257, 80 },
1921
  { 2027, 887, 284, 63, 2257, 80 },
1922
  { 2231, 887, 284, 63, 2257, 80 },
1923
  { 31, 887, 284, 63, 2257, 80 },
1924
  { 316, 887, 284, 63, 2257, 80 },
1925
  { 594, 887, 284, 63, 2257, 80 },
1926
  { 812, 887, 284, 63, 2257, 80 },
1927
  { 1028, 887, 284, 63, 2257, 80 },
1928
  { 1244, 887, 284, 63, 2257, 80 },
1929
  { 1456, 887, 284, 63, 2257, 80 },
1930
  { 1668, 887, 284, 63, 2257, 80 },
1931
  { 1880, 887, 284, 63, 2257, 80 },
1932
  { 2092, 887, 284, 63, 2257, 80 },
1933
  { 101, 887, 284, 63, 2257, 80 },
1934
  { 390, 887, 284, 63, 2257, 80 },
1935
  { 669, 887, 284, 63, 2257, 80 },
1936
  { 888, 887, 284, 63, 2257, 80 },
1937
  { 1104, 887, 284, 63, 2257, 80 },
1938
  { 1320, 887, 284, 63, 2257, 80 },
1939
  { 1532, 887, 284, 63, 2257, 80 },
1940
  { 1744, 887, 284, 63, 2257, 80 },
1941
  { 1956, 887, 284, 63, 2257, 80 },
1942
  { 2168, 887, 284, 63, 2257, 80 },
1943
  { 177, 887, 284, 63, 2257, 80 },
1944
  { 466, 887, 284, 63, 2257, 80 },
1945
  { 245, 923, 284, 63, 8496, 14 },
1946
  { 953, 1130, 873, 96, 145, 87 },
1947
  { 1169, 1130, 873, 96, 145, 87 },
1948
  { 1385, 1130, 873, 96, 145, 87 },
1949
  { 1597, 1130, 873, 96, 145, 87 },
1950
  { 1809, 1130, 873, 96, 145, 87 },
1951
  { 2021, 1130, 873, 96, 145, 87 },
1952
  { 2225, 1130, 873, 96, 145, 87 },
1953
  { 25, 1130, 873, 96, 145, 87 },
1954
  { 310, 1130, 873, 96, 145, 87 },
1955
  { 587, 1130, 873, 96, 145, 87 },
1956
  { 804, 1130, 873, 96, 145, 87 },
1957
  { 1020, 1130, 873, 96, 145, 87 },
1958
  { 1236, 1130, 873, 96, 145, 87 },
1959
  { 1448, 1130, 873, 96, 145, 87 },
1960
  { 1660, 1130, 873, 96, 145, 87 },
1961
  { 1872, 1130, 873, 96, 145, 87 },
1962
  { 2084, 1130, 873, 96, 145, 87 },
1963
  { 93, 1130, 873, 96, 145, 87 },
1964
  { 382, 1130, 873, 96, 145, 87 },
1965
  { 661, 1130, 873, 96, 145, 87 },
1966
  { 880, 1130, 873, 96, 145, 87 },
1967
  { 1096, 1130, 873, 96, 145, 87 },
1968
  { 1312, 1130, 873, 96, 145, 87 },
1969
  { 1524, 1130, 873, 96, 145, 87 },
1970
  { 1736, 1130, 873, 96, 145, 87 },
1971
  { 1948, 1130, 873, 96, 145, 87 },
1972
  { 2160, 1130, 873, 96, 145, 87 },
1973
  { 169, 1130, 873, 96, 145, 87 },
1974
  { 458, 1130, 873, 96, 145, 87 },
1975
  { 237, 1162, 873, 96, 304, 92 },
1976
  { 517, 1019, 873, 96, 864, 78 },
1977
  { 735, 1098, 873, 96, 6784, 17 },
1978
  { 739, 956, 542, 75, 737, 93 },
1979
  { 956, 956, 381, 75, 737, 93 },
1980
  { 1172, 956, 381, 75, 737, 93 },
1981
  { 1388, 956, 381, 75, 737, 93 },
1982
  { 1600, 956, 381, 75, 737, 93 },
1983
  { 1812, 956, 381, 75, 737, 93 },
1984
  { 2024, 956, 381, 75, 737, 93 },
1985
  { 2228, 956, 381, 75, 737, 93 },
1986
  { 28, 956, 381, 75, 737, 93 },
1987
  { 313, 956, 381, 75, 737, 93 },
1988
  { 590, 956, 381, 75, 737, 93 },
1989
  { 808, 956, 381, 75, 737, 93 },
1990
  { 1024, 956, 381, 75, 737, 93 },
1991
  { 1240, 956, 381, 75, 737, 93 },
1992
  { 1452, 956, 381, 75, 737, 93 },
1993
  { 1664, 956, 381, 75, 737, 93 },
1994
  { 1876, 956, 381, 75, 737, 93 },
1995
  { 2088, 956, 381, 75, 737, 93 },
1996
  { 97, 956, 381, 75, 737, 93 },
1997
  { 386, 956, 381, 75, 737, 93 },
1998
  { 665, 956, 381, 75, 737, 93 },
1999
  { 884, 956, 381, 75, 737, 93 },
2000
  { 1100, 956, 381, 75, 737, 93 },
2001
  { 1316, 956, 381, 75, 737, 93 },
2002
  { 1528, 956, 381, 75, 737, 93 },
2003
  { 1740, 956, 381, 75, 737, 93 },
2004
  { 1952, 956, 381, 75, 737, 93 },
2005
  { 2164, 956, 381, 75, 737, 93 },
2006
  { 173, 956, 381, 75, 737, 93 },
2007
  { 462, 956, 381, 75, 737, 93 },
2008
  { 241, 977, 381, 75, 1088, 83 },
2009
  { 521, 998, 381, 75, 8032, 22 },
2010
  { 255, 875, 550, 7, 8832, 32 },
2011
  { 2499, 943, 548, 7, 6432, 32 },
2012
  { 534, 144, 550, 7, 2209, 32 },
2013
  { 751, 144, 550, 7, 2209, 32 },
2014
  { 968, 144, 550, 7, 2209, 32 },
2015
  { 1184, 144, 550, 7, 2209, 32 },
2016
  { 1400, 144, 550, 7, 2209, 32 },
2017
  { 1612, 144, 550, 7, 2209, 32 },
2018
  { 1824, 144, 550, 7, 2209, 32 },
2019
  { 2036, 144, 550, 7, 2209, 32 },
2020
  { 2240, 144, 550, 7, 2209, 32 },
2021
  { 42, 144, 550, 7, 2209, 32 },
2022
  { 328, 144, 550, 7, 2209, 32 },
2023
  { 606, 144, 550, 7, 2209, 32 },
2024
  { 824, 144, 550, 7, 2209, 32 },
2025
  { 1040, 144, 550, 7, 2209, 32 },
2026
  { 1256, 144, 550, 7, 2209, 32 },
2027
  { 1468, 144, 550, 7, 2209, 32 },
2028
  { 1680, 144, 550, 7, 2209, 32 },
2029
  { 1892, 144, 550, 7, 2209, 32 },
2030
  { 2104, 144, 550, 7, 2209, 32 },
2031
  { 113, 144, 550, 7, 2209, 32 },
2032
  { 402, 144, 550, 7, 2209, 32 },
2033
  { 681, 144, 550, 7, 2209, 32 },
2034
  { 900, 144, 550, 7, 2209, 32 },
2035
  { 1116, 144, 550, 7, 2209, 32 },
2036
  { 1332, 144, 550, 7, 2209, 32 },
2037
  { 1544, 144, 550, 7, 2209, 32 },
2038
  { 1756, 144, 550, 7, 2209, 32 },
2039
  { 1968, 144, 550, 7, 2209, 32 },
2040
  { 2180, 144, 413, 7, 8976, 29 },
2041
  { 189, 144, 7, 7, 96, 32 },
2042
  { 2493, 905, 8, 128, 96, 97 },
2043
  { 2507, 935, 8, 128, 6529, 97 },
2044
  { 262, 899, 8, 128, 8883, 97 },
2045
  { 2478, 911, 8, 128, 8976, 26 },
2046
  { 540, 917, 8, 128, 2161, 97 },
2047
  { 757, 917, 8, 128, 2161, 97 },
2048
  { 974, 917, 8, 128, 2161, 97 },
2049
  { 1190, 917, 8, 128, 2161, 97 },
2050
  { 1406, 917, 8, 128, 2161, 97 },
2051
  { 1618, 917, 8, 128, 2161, 97 },
2052
  { 1830, 917, 8, 128, 2161, 97 },
2053
  { 2042, 917, 8, 128, 2161, 97 },
2054
  { 2246, 917, 8, 128, 2161, 97 },
2055
  { 49, 917, 8, 128, 2161, 97 },
2056
  { 336, 917, 8, 128, 2161, 97 },
2057
  { 614, 917, 8, 128, 2161, 97 },
2058
  { 832, 917, 8, 128, 2161, 97 },
2059
  { 1048, 917, 8, 128, 2161, 97 },
2060
  { 1264, 917, 8, 128, 2161, 97 },
2061
  { 1476, 917, 8, 128, 2161, 97 },
2062
  { 1688, 917, 8, 128, 2161, 97 },
2063
  { 1900, 917, 8, 128, 2161, 97 },
2064
  { 2112, 917, 8, 128, 2161, 97 },
2065
  { 121, 917, 8, 128, 2161, 97 },
2066
  { 410, 917, 8, 128, 2161, 97 },
2067
  { 689, 917, 8, 128, 2161, 97 },
2068
  { 908, 917, 8, 128, 2161, 97 },
2069
  { 1124, 917, 8, 128, 2161, 97 },
2070
  { 1340, 917, 8, 128, 2161, 97 },
2071
  { 1552, 917, 8, 128, 2161, 97 },
2072
  { 1764, 917, 8, 128, 2161, 97 },
2073
  { 1976, 917, 8, 128, 2161, 97 },
2074
  { 554, 564, 372, 134, 1457, 100 },
2075
  { 770, 564, 525, 134, 1457, 100 },
2076
  { 986, 564, 290, 134, 1457, 100 },
2077
  { 1202, 564, 290, 134, 1457, 100 },
2078
  { 1418, 564, 290, 134, 1457, 100 },
2079
  { 1630, 564, 290, 134, 1457, 100 },
2080
  { 1842, 564, 290, 134, 1457, 100 },
2081
  { 2054, 564, 290, 134, 1457, 100 },
2082
  { 2258, 564, 290, 134, 1457, 100 },
2083
  { 62, 564, 290, 134, 1457, 100 },
2084
  { 350, 564, 290, 134, 1457, 100 },
2085
  { 629, 564, 290, 134, 1457, 100 },
2086
  { 848, 564, 290, 134, 1457, 100 },
2087
  { 1064, 564, 290, 134, 1457, 100 },
2088
  { 1280, 564, 290, 134, 1457, 100 },
2089
  { 1492, 564, 290, 134, 1457, 100 },
2090
  { 1704, 564, 290, 134, 1457, 100 },
2091
  { 1916, 564, 290, 134, 1457, 100 },
2092
  { 2128, 564, 290, 134, 1457, 100 },
2093
  { 137, 564, 290, 134, 1457, 100 },
2094
  { 426, 564, 290, 134, 1457, 100 },
2095
  { 705, 564, 290, 134, 1457, 100 },
2096
  { 924, 564, 290, 134, 1457, 100 },
2097
  { 1140, 564, 290, 134, 1457, 100 },
2098
  { 1356, 564, 290, 134, 1457, 100 },
2099
  { 1568, 564, 290, 134, 1457, 100 },
2100
  { 1780, 564, 290, 134, 1457, 100 },
2101
  { 1992, 564, 290, 134, 1457, 100 },
2102
  { 2196, 564, 290, 134, 1457, 100 },
2103
  { 205, 564, 290, 134, 1457, 100 },
2104
  { 486, 564, 290, 134, 1457, 100 },
2105
  { 277, 581, 290, 134, 8544, 38 },
2106
  { 980, 780, 8, 181, 1, 121 },
2107
  { 1196, 780, 8, 181, 1, 121 },
2108
  { 1412, 780, 8, 181, 1, 121 },
2109
  { 1624, 780, 8, 181, 1, 121 },
2110
  { 1836, 780, 8, 181, 1, 121 },
2111
  { 2048, 780, 8, 181, 1, 121 },
2112
  { 2252, 780, 8, 181, 1, 121 },
2113
  { 56, 780, 8, 181, 1, 121 },
2114
  { 344, 780, 8, 181, 1, 121 },
2115
  { 622, 780, 8, 181, 1, 121 },
2116
  { 840, 780, 8, 181, 1, 121 },
2117
  { 1056, 780, 8, 181, 1, 121 },
2118
  { 1272, 780, 8, 181, 1, 121 },
2119
  { 1484, 780, 8, 181, 1, 121 },
2120
  { 1696, 780, 8, 181, 1, 121 },
2121
  { 1908, 780, 8, 181, 1, 121 },
2122
  { 2120, 780, 8, 181, 1, 121 },
2123
  { 129, 780, 8, 181, 1, 121 },
2124
  { 418, 780, 8, 181, 1, 121 },
2125
  { 697, 780, 8, 181, 1, 121 },
2126
  { 916, 780, 8, 181, 1, 121 },
2127
  { 1132, 780, 8, 181, 1, 121 },
2128
  { 1348, 780, 8, 181, 1, 121 },
2129
  { 1560, 780, 8, 181, 1, 121 },
2130
  { 1772, 780, 8, 181, 1, 121 },
2131
  { 1984, 780, 8, 181, 1, 121 },
2132
  { 2188, 780, 8, 181, 1, 121 },
2133
  { 197, 780, 8, 181, 1, 121 },
2134
  { 478, 780, 8, 181, 1, 121 },
2135
  { 269, 826, 8, 181, 384, 130 },
2136
  { 546, 688, 8, 181, 944, 105 },
2137
  { 763, 734, 8, 181, 6864, 43 },
2138
  { 767, 598, 545, 151, 625, 139 },
2139
  { 983, 598, 180, 151, 625, 139 },
2140
  { 1199, 598, 180, 151, 625, 139 },
2141
  { 1415, 598, 180, 151, 625, 139 },
2142
  { 1627, 598, 180, 151, 625, 139 },
2143
  { 1839, 598, 180, 151, 625, 139 },
2144
  { 2051, 598, 180, 151, 625, 139 },
2145
  { 2255, 598, 180, 151, 625, 139 },
2146
  { 59, 598, 180, 151, 625, 139 },
2147
  { 347, 598, 180, 151, 625, 139 },
2148
  { 625, 598, 180, 151, 625, 139 },
2149
  { 844, 598, 180, 151, 625, 139 },
2150
  { 1060, 598, 180, 151, 625, 139 },
2151
  { 1276, 598, 180, 151, 625, 139 },
2152
  { 1488, 598, 180, 151, 625, 139 },
2153
  { 1700, 598, 180, 151, 625, 139 },
2154
  { 1912, 598, 180, 151, 625, 139 },
2155
  { 2124, 598, 180, 151, 625, 139 },
2156
  { 133, 598, 180, 151, 625, 139 },
2157
  { 422, 598, 180, 151, 625, 139 },
2158
  { 701, 598, 180, 151, 625, 139 },
2159
  { 920, 598, 180, 151, 625, 139 },
2160
  { 1136, 598, 180, 151, 625, 139 },
2161
  { 1352, 598, 180, 151, 625, 139 },
2162
  { 1564, 598, 180, 151, 625, 139 },
2163
  { 1776, 598, 180, 151, 625, 139 },
2164
  { 1988, 598, 180, 151, 625, 139 },
2165
  { 2192, 598, 180, 151, 625, 139 },
2166
  { 201, 598, 180, 151, 625, 139 },
2167
  { 482, 598, 180, 151, 625, 139 },
2168
  { 273, 628, 180, 151, 1152, 114 },
2169
  { 550, 658, 180, 151, 8096, 52 },
2170
};
2171
2172
extern const MCPhysReg AArch64RegUnitRoots[][2] = {
2173
  { AArch64::FFR },
2174
  { AArch64::W29 },
2175
  { AArch64::W30 },
2176
  { AArch64::NZCV },
2177
  { AArch64::WSP },
2178
  { AArch64::WZR },
2179
  { AArch64::B0 },
2180
  { AArch64::B1 },
2181
  { AArch64::B2 },
2182
  { AArch64::B3 },
2183
  { AArch64::B4 },
2184
  { AArch64::B5 },
2185
  { AArch64::B6 },
2186
  { AArch64::B7 },
2187
  { AArch64::B8 },
2188
  { AArch64::B9 },
2189
  { AArch64::B10 },
2190
  { AArch64::B11 },
2191
  { AArch64::B12 },
2192
  { AArch64::B13 },
2193
  { AArch64::B14 },
2194
  { AArch64::B15 },
2195
  { AArch64::B16 },
2196
  { AArch64::B17 },
2197
  { AArch64::B18 },
2198
  { AArch64::B19 },
2199
  { AArch64::B20 },
2200
  { AArch64::B21 },
2201
  { AArch64::B22 },
2202
  { AArch64::B23 },
2203
  { AArch64::B24 },
2204
  { AArch64::B25 },
2205
  { AArch64::B26 },
2206
  { AArch64::B27 },
2207
  { AArch64::B28 },
2208
  { AArch64::B29 },
2209
  { AArch64::B30 },
2210
  { AArch64::B31 },
2211
  { AArch64::P0 },
2212
  { AArch64::P1 },
2213
  { AArch64::P2 },
2214
  { AArch64::P3 },
2215
  { AArch64::P4 },
2216
  { AArch64::P5 },
2217
  { AArch64::P6 },
2218
  { AArch64::P7 },
2219
  { AArch64::P8 },
2220
  { AArch64::P9 },
2221
  { AArch64::P10 },
2222
  { AArch64::P11 },
2223
  { AArch64::P12 },
2224
  { AArch64::P13 },
2225
  { AArch64::P14 },
2226
  { AArch64::P15 },
2227
  { AArch64::W0 },
2228
  { AArch64::W1 },
2229
  { AArch64::W2 },
2230
  { AArch64::W3 },
2231
  { AArch64::W4 },
2232
  { AArch64::W5 },
2233
  { AArch64::W6 },
2234
  { AArch64::W7 },
2235
  { AArch64::W8 },
2236
  { AArch64::W9 },
2237
  { AArch64::W10 },
2238
  { AArch64::W11 },
2239
  { AArch64::W12 },
2240
  { AArch64::W13 },
2241
  { AArch64::W14 },
2242
  { AArch64::W15 },
2243
  { AArch64::W16 },
2244
  { AArch64::W17 },
2245
  { AArch64::W18 },
2246
  { AArch64::W19 },
2247
  { AArch64::W20 },
2248
  { AArch64::W21 },
2249
  { AArch64::W22 },
2250
  { AArch64::W23 },
2251
  { AArch64::W24 },
2252
  { AArch64::W25 },
2253
  { AArch64::W26 },
2254
  { AArch64::W27 },
2255
  { AArch64::W28 },
2256
  { AArch64::Z0_HI },
2257
  { AArch64::Z1_HI },
2258
  { AArch64::Z2_HI },
2259
  { AArch64::Z3_HI },
2260
  { AArch64::Z4_HI },
2261
  { AArch64::Z5_HI },
2262
  { AArch64::Z6_HI },
2263
  { AArch64::Z7_HI },
2264
  { AArch64::Z8_HI },
2265
  { AArch64::Z9_HI },
2266
  { AArch64::Z10_HI },
2267
  { AArch64::Z11_HI },
2268
  { AArch64::Z12_HI },
2269
  { AArch64::Z13_HI },
2270
  { AArch64::Z14_HI },
2271
  { AArch64::Z15_HI },
2272
  { AArch64::Z16_HI },
2273
  { AArch64::Z17_HI },
2274
  { AArch64::Z18_HI },
2275
  { AArch64::Z19_HI },
2276
  { AArch64::Z20_HI },
2277
  { AArch64::Z21_HI },
2278
  { AArch64::Z22_HI },
2279
  { AArch64::Z23_HI },
2280
  { AArch64::Z24_HI },
2281
  { AArch64::Z25_HI },
2282
  { AArch64::Z26_HI },
2283
  { AArch64::Z27_HI },
2284
  { AArch64::Z28_HI },
2285
  { AArch64::Z29_HI },
2286
  { AArch64::Z30_HI },
2287
  { AArch64::Z31_HI },
2288
};
2289
2290
namespace {     // Register classes...
2291
  // FPR8 Register Class...
2292
  const MCPhysReg FPR8[] = {
2293
    AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, 
2294
  };
2295
2296
  // FPR8 Bit set.
2297
  const uint8_t FPR8Bits[] = {
2298
    0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2299
  };
2300
2301
  // FPR16 Register Class...
2302
  const MCPhysReg FPR16[] = {
2303
    AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, 
2304
  };
2305
2306
  // FPR16 Bit set.
2307
  const uint8_t FPR16Bits[] = {
2308
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2309
  };
2310
2311
  // PPR Register Class...
2312
  const MCPhysReg PPR[] = {
2313
    AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, 
2314
  };
2315
2316
  // PPR Bit set.
2317
  const uint8_t PPRBits[] = {
2318
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
2319
  };
2320
2321
  // PPR_3b Register Class...
2322
  const MCPhysReg PPR_3b[] = {
2323
    AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 
2324
  };
2325
2326
  // PPR_3b Bit set.
2327
  const uint8_t PPR_3bBits[] = {
2328
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
2329
  };
2330
2331
  // GPR32all Register Class...
2332
  const MCPhysReg GPR32all[] = {
2333
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP, 
2334
  };
2335
2336
  // GPR32all Bit set.
2337
  const uint8_t GPR32allBits[] = {
2338
    0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2339
  };
2340
2341
  // FPR32 Register Class...
2342
  const MCPhysReg FPR32[] = {
2343
    AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, 
2344
  };
2345
2346
  // FPR32 Bit set.
2347
  const uint8_t FPR32Bits[] = {
2348
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2349
  };
2350
2351
  // GPR32 Register Class...
2352
  const MCPhysReg GPR32[] = {
2353
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, 
2354
  };
2355
2356
  // GPR32 Bit set.
2357
  const uint8_t GPR32Bits[] = {
2358
    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2359
  };
2360
2361
  // GPR32sp Register Class...
2362
  const MCPhysReg GPR32sp[] = {
2363
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, 
2364
  };
2365
2366
  // GPR32sp Bit set.
2367
  const uint8_t GPR32spBits[] = {
2368
    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2369
  };
2370
2371
  // GPR32common Register Class...
2372
  const MCPhysReg GPR32common[] = {
2373
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, 
2374
  };
2375
2376
  // GPR32common Bit set.
2377
  const uint8_t GPR32commonBits[] = {
2378
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 
2379
  };
2380
2381
  // CCR Register Class...
2382
  const MCPhysReg CCR[] = {
2383
    AArch64::NZCV, 
2384
  };
2385
2386
  // CCR Bit set.
2387
  const uint8_t CCRBits[] = {
2388
    0x10, 
2389
  };
2390
2391
  // GPR32sponly Register Class...
2392
  const MCPhysReg GPR32sponly[] = {
2393
    AArch64::WSP, 
2394
  };
2395
2396
  // GPR32sponly Bit set.
2397
  const uint8_t GPR32sponlyBits[] = {
2398
    0x40, 
2399
  };
2400
2401
  // WSeqPairsClass Register Class...
2402
  const MCPhysReg WSeqPairsClass[] = {
2403
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, AArch64::WZR_W0, 
2404
  };
2405
2406
  // WSeqPairsClass Bit set.
2407
  const uint8_t WSeqPairsClassBits[] = {
2408
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2409
  };
2410
2411
  // WSeqPairsClass_with_sube32_in_GPR32common Register Class...
2412
  const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common[] = {
2413
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, 
2414
  };
2415
2416
  // WSeqPairsClass_with_sube32_in_GPR32common Bit set.
2417
  const uint8_t WSeqPairsClass_with_sube32_in_GPR32commonBits[] = {
2418
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, 
2419
  };
2420
2421
  // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
2422
  const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
2423
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::WZR_W0, 
2424
  };
2425
2426
  // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
2427
  const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
2428
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, 
2429
  };
2430
2431
  // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Register Class...
2432
  const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common[] = {
2433
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, 
2434
  };
2435
2436
  // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Bit set.
2437
  const uint8_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
2438
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 
2439
  };
2440
2441
  // GPR64all Register Class...
2442
  const MCPhysReg GPR64all[] = {
2443
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP, 
2444
  };
2445
2446
  // GPR64all Bit set.
2447
  const uint8_t GPR64allBits[] = {
2448
    0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2449
  };
2450
2451
  // FPR64 Register Class...
2452
  const MCPhysReg FPR64[] = {
2453
    AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 
2454
  };
2455
2456
  // FPR64 Bit set.
2457
  const uint8_t FPR64Bits[] = {
2458
    0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2459
  };
2460
2461
  // GPR64 Register Class...
2462
  const MCPhysReg GPR64[] = {
2463
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, 
2464
  };
2465
2466
  // GPR64 Bit set.
2467
  const uint8_t GPR64Bits[] = {
2468
    0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2469
  };
2470
2471
  // GPR64sp Register Class...
2472
  const MCPhysReg GPR64sp[] = {
2473
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, 
2474
  };
2475
2476
  // GPR64sp Bit set.
2477
  const uint8_t GPR64spBits[] = {
2478
    0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2479
  };
2480
2481
  // GPR64common Register Class...
2482
  const MCPhysReg GPR64common[] = {
2483
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, 
2484
  };
2485
2486
  // GPR64common Bit set.
2487
  const uint8_t GPR64commonBits[] = {
2488
    0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 
2489
  };
2490
2491
  // tcGPR64 Register Class...
2492
  const MCPhysReg tcGPR64[] = {
2493
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, 
2494
  };
2495
2496
  // tcGPR64 Bit set.
2497
  const uint8_t tcGPR64Bits[] = {
2498
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07, 
2499
  };
2500
2501
  // GPR64sponly Register Class...
2502
  const MCPhysReg GPR64sponly[] = {
2503
    AArch64::SP, 
2504
  };
2505
2506
  // GPR64sponly Bit set.
2507
  const uint8_t GPR64sponlyBits[] = {
2508
    0x20, 
2509
  };
2510
2511
  // DD Register Class...
2512
  const MCPhysReg DD[] = {
2513
    AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0, 
2514
  };
2515
2516
  // DD Bit set.
2517
  const uint8_t DDBits[] = {
2518
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2519
  };
2520
2521
  // XSeqPairsClass Register Class...
2522
  const MCPhysReg XSeqPairsClass[] = {
2523
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, AArch64::XZR_X0, 
2524
  };
2525
2526
  // XSeqPairsClass Bit set.
2527
  const uint8_t XSeqPairsClassBits[] = {
2528
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2529
  };
2530
2531
  // XSeqPairsClass_with_sub_32_in_GPR32common Register Class...
2532
  const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common[] = {
2533
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, 
2534
  };
2535
2536
  // XSeqPairsClass_with_sub_32_in_GPR32common Bit set.
2537
  const uint8_t XSeqPairsClass_with_sub_32_in_GPR32commonBits[] = {
2538
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0xff, 0x1f, 
2539
  };
2540
2541
  // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
2542
  const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
2543
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::XZR_X0, 
2544
  };
2545
2546
  // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
2547
  const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
2548
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, 
2549
  };
2550
2551
  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Register Class...
2552
  const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common[] = {
2553
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, 
2554
  };
2555
2556
  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Bit set.
2557
  const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
2558
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0xff, 0xff, 0xff, 0x1f, 
2559
  };
2560
2561
  // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
2562
  const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
2563
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, 
2564
  };
2565
2566
  // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
2567
  const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
2568
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x0f, 
2569
  };
2570
2571
  // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
2572
  const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
2573
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::XZR_X0, 
2574
  };
2575
2576
  // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
2577
  const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
2578
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xfe, 0xff, 0x07, 
2579
  };
2580
2581
  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
2582
  const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64[] = {
2583
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, 
2584
  };
2585
2586
  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
2587
  const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
2588
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x07, 
2589
  };
2590
2591
  // FPR128 Register Class...
2592
  const MCPhysReg FPR128[] = {
2593
    AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 
2594
  };
2595
2596
  // FPR128 Bit set.
2597
  const uint8_t FPR128Bits[] = {
2598
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2599
  };
2600
2601
  // ZPR Register Class...
2602
  const MCPhysReg ZPR[] = {
2603
    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31, 
2604
  };
2605
2606
  // ZPR Bit set.
2607
  const uint8_t ZPRBits[] = {
2608
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2609
  };
2610
2611
  // FPR128_lo Register Class...
2612
  const MCPhysReg FPR128_lo[] = {
2613
    AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, 
2614
  };
2615
2616
  // FPR128_lo Bit set.
2617
  const uint8_t FPR128_loBits[] = {
2618
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
2619
  };
2620
2621
  // ZPR_4b Register Class...
2622
  const MCPhysReg ZPR_4b[] = {
2623
    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 
2624
  };
2625
2626
  // ZPR_4b Bit set.
2627
  const uint8_t ZPR_4bBits[] = {
2628
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2629
  };
2630
2631
  // ZPR_3b Register Class...
2632
  const MCPhysReg ZPR_3b[] = {
2633
    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 
2634
  };
2635
2636
  // ZPR_3b Bit set.
2637
  const uint8_t ZPR_3bBits[] = {
2638
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2639
  };
2640
2641
  // DDD Register Class...
2642
  const MCPhysReg DDD[] = {
2643
    AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1, 
2644
  };
2645
2646
  // DDD Bit set.
2647
  const uint8_t DDDBits[] = {
2648
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2649
  };
2650
2651
  // DDDD Register Class...
2652
  const MCPhysReg DDDD[] = {
2653
    AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, 
2654
  };
2655
2656
  // DDDD Bit set.
2657
  const uint8_t DDDDBits[] = {
2658
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2659
  };
2660
2661
  // QQ Register Class...
2662
  const MCPhysReg QQ[] = {
2663
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0, 
2664
  };
2665
2666
  // QQ Bit set.
2667
  const uint8_t QQBits[] = {
2668
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2669
  };
2670
2671
  // ZPR2 Register Class...
2672
  const MCPhysReg ZPR2[] = {
2673
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0, 
2674
  };
2675
2676
  // ZPR2 Bit set.
2677
  const uint8_t ZPR2Bits[] = {
2678
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2679
  };
2680
2681
  // QQ_with_qsub0_in_FPR128_lo Register Class...
2682
  const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
2683
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 
2684
  };
2685
2686
  // QQ_with_qsub0_in_FPR128_lo Bit set.
2687
  const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
2688
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2689
  };
2690
2691
  // QQ_with_qsub1_in_FPR128_lo Register Class...
2692
  const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
2693
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0, 
2694
  };
2695
2696
  // QQ_with_qsub1_in_FPR128_lo Bit set.
2697
  const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
2698
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2699
  };
2700
2701
  // ZPR2_with_zsub1_in_ZPR_4b Register Class...
2702
  const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = {
2703
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z31_Z0, 
2704
  };
2705
2706
  // ZPR2_with_zsub1_in_ZPR_4b Bit set.
2707
  const uint8_t ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2708
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2709
  };
2710
2711
  // ZPR2_with_zsub_in_FPR128_lo Register Class...
2712
  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = {
2713
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 
2714
  };
2715
2716
  // ZPR2_with_zsub_in_FPR128_lo Bit set.
2717
  const uint8_t ZPR2_with_zsub_in_FPR128_loBits[] = {
2718
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2719
  };
2720
2721
  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
2722
  const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
2723
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, 
2724
  };
2725
2726
  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
2727
  const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
2728
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2729
  };
2730
2731
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Register Class...
2732
  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = {
2733
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, 
2734
  };
2735
2736
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Bit set.
2737
  const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2738
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2739
  };
2740
2741
  // ZPR2_with_zsub0_in_ZPR_3b Register Class...
2742
  const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = {
2743
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 
2744
  };
2745
2746
  // ZPR2_with_zsub0_in_ZPR_3b Bit set.
2747
  const uint8_t ZPR2_with_zsub0_in_ZPR_3bBits[] = {
2748
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2749
  };
2750
2751
  // ZPR2_with_zsub1_in_ZPR_3b Register Class...
2752
  const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = {
2753
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z31_Z0, 
2754
  };
2755
2756
  // ZPR2_with_zsub1_in_ZPR_3b Bit set.
2757
  const uint8_t ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2758
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
2759
  };
2760
2761
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Register Class...
2762
  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = {
2763
    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, 
2764
  };
2765
2766
  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Bit set.
2767
  const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2768
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
2769
  };
2770
2771
  // QQQ Register Class...
2772
  const MCPhysReg QQQ[] = {
2773
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
2774
  };
2775
2776
  // QQQ Bit set.
2777
  const uint8_t QQQBits[] = {
2778
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2779
  };
2780
2781
  // ZPR3 Register Class...
2782
  const MCPhysReg ZPR3[] = {
2783
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
2784
  };
2785
2786
  // ZPR3 Bit set.
2787
  const uint8_t ZPR3Bits[] = {
2788
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2789
  };
2790
2791
  // QQQ_with_qsub0_in_FPR128_lo Register Class...
2792
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
2793
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, 
2794
  };
2795
2796
  // QQQ_with_qsub0_in_FPR128_lo Bit set.
2797
  const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
2798
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2799
  };
2800
2801
  // QQQ_with_qsub1_in_FPR128_lo Register Class...
2802
  const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
2803
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1, 
2804
  };
2805
2806
  // QQQ_with_qsub1_in_FPR128_lo Bit set.
2807
  const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
2808
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2809
  };
2810
2811
  // QQQ_with_qsub2_in_FPR128_lo Register Class...
2812
  const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
2813
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
2814
  };
2815
2816
  // QQQ_with_qsub2_in_FPR128_lo Bit set.
2817
  const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
2818
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
2819
  };
2820
2821
  // ZPR3_with_zsub1_in_ZPR_4b Register Class...
2822
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = {
2823
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z31_Z0_Z1, 
2824
  };
2825
2826
  // ZPR3_with_zsub1_in_ZPR_4b Bit set.
2827
  const uint8_t ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2828
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
2829
  };
2830
2831
  // ZPR3_with_zsub2_in_ZPR_4b Register Class...
2832
  const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = {
2833
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
2834
  };
2835
2836
  // ZPR3_with_zsub2_in_ZPR_4b Bit set.
2837
  const uint8_t ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2838
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
2839
  };
2840
2841
  // ZPR3_with_zsub_in_FPR128_lo Register Class...
2842
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = {
2843
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, 
2844
  };
2845
2846
  // ZPR3_with_zsub_in_FPR128_lo Bit set.
2847
  const uint8_t ZPR3_with_zsub_in_FPR128_loBits[] = {
2848
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2849
  };
2850
2851
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
2852
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
2853
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 
2854
  };
2855
2856
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
2857
  const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
2858
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2859
  };
2860
2861
  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2862
  const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2863
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1, 
2864
  };
2865
2866
  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2867
  const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2868
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
2869
  };
2870
2871
  // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2872
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2873
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z31_Z0_Z1, 
2874
  };
2875
2876
  // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2877
  const uint8_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2878
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
2879
  };
2880
2881
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Register Class...
2882
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = {
2883
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 
2884
  };
2885
2886
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Bit set.
2887
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2888
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2889
  };
2890
2891
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2892
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2893
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, 
2894
  };
2895
2896
  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2897
  const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2898
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
2899
  };
2900
2901
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2902
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2903
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, 
2904
  };
2905
2906
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2907
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2908
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
2909
  };
2910
2911
  // ZPR3_with_zsub0_in_ZPR_3b Register Class...
2912
  const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = {
2913
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, 
2914
  };
2915
2916
  // ZPR3_with_zsub0_in_ZPR_3b Bit set.
2917
  const uint8_t ZPR3_with_zsub0_in_ZPR_3bBits[] = {
2918
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2919
  };
2920
2921
  // ZPR3_with_zsub1_in_ZPR_3b Register Class...
2922
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = {
2923
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z31_Z0_Z1, 
2924
  };
2925
2926
  // ZPR3_with_zsub1_in_ZPR_3b Bit set.
2927
  const uint8_t ZPR3_with_zsub1_in_ZPR_3bBits[] = {
2928
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
2929
  };
2930
2931
  // ZPR3_with_zsub2_in_ZPR_3b Register Class...
2932
  const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = {
2933
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, 
2934
  };
2935
2936
  // ZPR3_with_zsub2_in_ZPR_3b Bit set.
2937
  const uint8_t ZPR3_with_zsub2_in_ZPR_3bBits[] = {
2938
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, 
2939
  };
2940
2941
  // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
2942
  const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
2943
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z31_Z0_Z1, 
2944
  };
2945
2946
  // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
2947
  const uint8_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
2948
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, 
2949
  };
2950
2951
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Register Class...
2952
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = {
2953
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, 
2954
  };
2955
2956
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Bit set.
2957
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits[] = {
2958
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
2959
  };
2960
2961
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
2962
  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
2963
    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 
2964
  };
2965
2966
  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
2967
  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
2968
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 
2969
  };
2970
2971
  // QQQQ Register Class...
2972
  const MCPhysReg QQQQ[] = {
2973
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
2974
  };
2975
2976
  // QQQQ Bit set.
2977
  const uint8_t QQQQBits[] = {
2978
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2979
  };
2980
2981
  // ZPR4 Register Class...
2982
  const MCPhysReg ZPR4[] = {
2983
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
2984
  };
2985
2986
  // ZPR4 Bit set.
2987
  const uint8_t ZPR4Bits[] = {
2988
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2989
  };
2990
2991
  // QQQQ_with_qsub0_in_FPR128_lo Register Class...
2992
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
2993
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, 
2994
  };
2995
2996
  // QQQQ_with_qsub0_in_FPR128_lo Bit set.
2997
  const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
2998
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2999
  };
3000
3001
  // QQQQ_with_qsub1_in_FPR128_lo Register Class...
3002
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
3003
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2, 
3004
  };
3005
3006
  // QQQQ_with_qsub1_in_FPR128_lo Bit set.
3007
  const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
3008
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
3009
  };
3010
3011
  // QQQQ_with_qsub2_in_FPR128_lo Register Class...
3012
  const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
3013
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
3014
  };
3015
3016
  // QQQQ_with_qsub2_in_FPR128_lo Bit set.
3017
  const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
3018
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
3019
  };
3020
3021
  // QQQQ_with_qsub3_in_FPR128_lo Register Class...
3022
  const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
3023
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
3024
  };
3025
3026
  // QQQQ_with_qsub3_in_FPR128_lo Bit set.
3027
  const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
3028
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, 
3029
  };
3030
3031
  // ZPR4_with_zsub1_in_ZPR_4b Register Class...
3032
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = {
3033
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z31_Z0_Z1_Z2, 
3034
  };
3035
3036
  // ZPR4_with_zsub1_in_ZPR_4b Bit set.
3037
  const uint8_t ZPR4_with_zsub1_in_ZPR_4bBits[] = {
3038
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, 
3039
  };
3040
3041
  // ZPR4_with_zsub2_in_ZPR_4b Register Class...
3042
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = {
3043
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3044
  };
3045
3046
  // ZPR4_with_zsub2_in_ZPR_4b Bit set.
3047
  const uint8_t ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3048
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, 
3049
  };
3050
3051
  // ZPR4_with_zsub3_in_ZPR_4b Register Class...
3052
  const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = {
3053
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3054
  };
3055
3056
  // ZPR4_with_zsub3_in_ZPR_4b Bit set.
3057
  const uint8_t ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3058
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, 
3059
  };
3060
3061
  // ZPR4_with_zsub_in_FPR128_lo Register Class...
3062
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = {
3063
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, 
3064
  };
3065
3066
  // ZPR4_with_zsub_in_FPR128_lo Bit set.
3067
  const uint8_t ZPR4_with_zsub_in_FPR128_loBits[] = {
3068
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
3069
  };
3070
3071
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
3072
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
3073
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 
3074
  };
3075
3076
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
3077
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
3078
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
3079
  };
3080
3081
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
3082
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3083
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2, 
3084
  };
3085
3086
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
3087
  const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
3088
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
3089
  };
3090
3091
  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3092
  const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3093
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
3094
  };
3095
3096
  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3097
  const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3098
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, 
3099
  };
3100
3101
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
3102
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3103
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z31_Z0_Z1_Z2, 
3104
  };
3105
3106
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
3107
  const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3108
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, 
3109
  };
3110
3111
  // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3112
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3113
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3114
  };
3115
3116
  // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3117
  const uint8_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3118
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, 
3119
  };
3120
3121
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Register Class...
3122
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = {
3123
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 
3124
  };
3125
3126
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Bit set.
3127
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits[] = {
3128
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
3129
  };
3130
3131
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
3132
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3133
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, 
3134
  };
3135
3136
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
3137
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
3138
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
3139
  };
3140
3141
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3142
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3143
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2, 
3144
  };
3145
3146
  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3147
  const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3148
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, 
3149
  };
3150
3151
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3152
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3153
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z31_Z0_Z1_Z2, 
3154
  };
3155
3156
  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3157
  const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3158
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, 
3159
  };
3160
3161
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
3162
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3163
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, 
3164
  };
3165
3166
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
3167
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3168
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
3169
  };
3170
3171
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3172
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3173
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, 
3174
  };
3175
3176
  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3177
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3178
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 
3179
  };
3180
3181
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3182
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3183
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, 
3184
  };
3185
3186
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3187
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3188
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 
3189
  };
3190
3191
  // ZPR4_with_zsub0_in_ZPR_3b Register Class...
3192
  const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = {
3193
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, 
3194
  };
3195
3196
  // ZPR4_with_zsub0_in_ZPR_3b Bit set.
3197
  const uint8_t ZPR4_with_zsub0_in_ZPR_3bBits[] = {
3198
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
3199
  };
3200
3201
  // ZPR4_with_zsub1_in_ZPR_3b Register Class...
3202
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = {
3203
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z31_Z0_Z1_Z2, 
3204
  };
3205
3206
  // ZPR4_with_zsub1_in_ZPR_3b Bit set.
3207
  const uint8_t ZPR4_with_zsub1_in_ZPR_3bBits[] = {
3208
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, 
3209
  };
3210
3211
  // ZPR4_with_zsub2_in_ZPR_3b Register Class...
3212
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = {
3213
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3214
  };
3215
3216
  // ZPR4_with_zsub2_in_ZPR_3b Bit set.
3217
  const uint8_t ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3218
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, 
3219
  };
3220
3221
  // ZPR4_with_zsub3_in_ZPR_3b Register Class...
3222
  const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = {
3223
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3224
  };
3225
3226
  // ZPR4_with_zsub3_in_ZPR_3b Bit set.
3227
  const uint8_t ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3228
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x1c, 
3229
  };
3230
3231
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
3232
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3233
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z31_Z0_Z1_Z2, 
3234
  };
3235
3236
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
3237
  const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3238
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, 
3239
  };
3240
3241
  // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3242
  const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3243
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, 
3244
  };
3245
3246
  // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3247
  const uint8_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3248
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x18, 
3249
  };
3250
3251
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Register Class...
3252
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = {
3253
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, 
3254
  };
3255
3256
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Bit set.
3257
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits[] = {
3258
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
3259
  };
3260
3261
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3262
  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3263
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z31_Z0_Z1_Z2, 
3264
  };
3265
3266
  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3267
  const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3268
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x10, 
3269
  };
3270
3271
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
3272
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3273
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 
3274
  };
3275
3276
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
3277
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3278
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 
3279
  };
3280
3281
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3282
  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3283
    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, 
3284
  };
3285
3286
  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3287
  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3288
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 
3289
  };
3290
3291
} // end anonymous namespace
3292
3293
extern const char AArch64RegClassStrings[] = {
3294
  /* 0 */ 'F', 'P', 'R', '3', '2', 0,
3295
  /* 6 */ 'G', 'P', 'R', '3', '2', 0,
3296
  /* 12 */ 'Z', 'P', 'R', '2', 0,
3297
  /* 17 */ 'Z', 'P', 'R', '3', 0,
3298
  /* 22 */ 'F', 'P', 'R', '6', '4', 0,
3299
  /* 28 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3300
  /* 66 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3301
  /* 150 */ 'Z', 'P', 'R', '4', 0,
3302
  /* 155 */ 'F', 'P', 'R', '1', '6', 0,
3303
  /* 161 */ 'F', 'P', 'R', '1', '2', '8', 0,
3304
  /* 168 */ 'F', 'P', 'R', '8', 0,
3305
  /* 173 */ 'D', 'D', 'D', 'D', 0,
3306
  /* 178 */ 'Q', 'Q', 'Q', 'Q', 0,
3307
  /* 183 */ 'C', 'C', 'R', 0,
3308
  /* 187 */ 'P', 'P', 'R', 0,
3309
  /* 191 */ 'Z', 'P', 'R', 0,
3310
  /* 195 */ 'P', 'P', 'R', '_', '3', 'b', 0,
3311
  /* 202 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3312
  /* 228 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3313
  /* 254 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3314
  /* 280 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3315
  /* 338 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3316
  /* 396 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3317
  /* 454 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3318
  /* 510 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3319
  /* 568 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3320
  /* 624 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3321
  /* 682 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3322
  /* 738 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3323
  /* 794 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3324
  /* 852 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3325
  /* 910 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3326
  /* 968 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3327
  /* 1026 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3328
  /* 1082 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3329
  /* 1140 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3330
  /* 1196 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3331
  /* 1254 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3332
  /* 1310 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3333
  /* 1366 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3334
  /* 1424 */ 'G', 'P', 'R', '3', '2', 'a', 'l', 'l', 0,
3335
  /* 1433 */ 'G', 'P', 'R', '6', '4', 'a', 'l', 'l', 0,
3336
  /* 1442 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3337
  /* 1484 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3338
  /* 1526 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3339
  /* 1614 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3340
  /* 1702 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3341
  /* 1731 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3342
  /* 1793 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3343
  /* 1853 */ 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3344
  /* 1911 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3345
  /* 1973 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3346
  /* 2035 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3347
  /* 2095 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3348
  /* 2155 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3349
  /* 2217 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3350
  /* 2279 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3351
  /* 2341 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3352
  /* 2369 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3353
  /* 2397 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3354
  /* 2425 */ 'G', 'P', 'R', '3', '2', 's', 'p', 0,
3355
  /* 2433 */ 'G', 'P', 'R', '6', '4', 's', 'p', 0,
3356
  /* 2441 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
3357
  /* 2456 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
3358
  /* 2471 */ 'G', 'P', 'R', '3', '2', 's', 'p', 'o', 'n', 'l', 'y', 0,
3359
  /* 2483 */ 'G', 'P', 'R', '6', '4', 's', 'p', 'o', 'n', 'l', 'y', 0,
3360
};
3361
3362
extern const MCRegisterClass AArch64MCRegisterClasses[] = {
3363
  { FPR8, FPR8Bits, 168, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, true },
3364
  { FPR16, FPR16Bits, 155, 32, sizeof(FPR16Bits), AArch64::FPR16RegClassID, 1, true },
3365
  { PPR, PPRBits, 187, 16, sizeof(PPRBits), AArch64::PPRRegClassID, 1, true },
3366
  { PPR_3b, PPR_3bBits, 195, 8, sizeof(PPR_3bBits), AArch64::PPR_3bRegClassID, 1, true },
3367
  { GPR32all, GPR32allBits, 1424, 33, sizeof(GPR32allBits), AArch64::GPR32allRegClassID, 1, true },
3368
  { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64::FPR32RegClassID, 1, true },
3369
  { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 1, true },
3370
  { GPR32sp, GPR32spBits, 2425, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 1, true },
3371
  { GPR32common, GPR32commonBits, 1472, 31, sizeof(GPR32commonBits), AArch64::GPR32commonRegClassID, 1, true },
3372
  { CCR, CCRBits, 183, 1, sizeof(CCRBits), AArch64::CCRRegClassID, -1, false },
3373
  { GPR32sponly, GPR32sponlyBits, 2471, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 1, true },
3374
  { WSeqPairsClass, WSeqPairsClassBits, 2441, 32, sizeof(WSeqPairsClassBits), AArch64::WSeqPairsClassRegClassID, 1, true },
3375
  { WSeqPairsClass_with_sube32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32commonBits, 1484, 31, sizeof(WSeqPairsClass_with_sube32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClassID, 1, true },
3376
  { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, 1572, 31, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 1, true },
3377
  { WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits, 1526, 30, sizeof(WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 1, true },
3378
  { GPR64all, GPR64allBits, 1433, 33, sizeof(GPR64allBits), AArch64::GPR64allRegClassID, 1, true },
3379
  { FPR64, FPR64Bits, 22, 32, sizeof(FPR64Bits), AArch64::FPR64RegClassID, 1, true },
3380
  { GPR64, GPR64Bits, 60, 32, sizeof(GPR64Bits), AArch64::GPR64RegClassID, 1, true },
3381
  { GPR64sp, GPR64spBits, 2433, 32, sizeof(GPR64spBits), AArch64::GPR64spRegClassID, 1, true },
3382
  { GPR64common, GPR64commonBits, 1690, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 1, true },
3383
  { tcGPR64, tcGPR64Bits, 58, 19, sizeof(tcGPR64Bits), AArch64::tcGPR64RegClassID, 1, true },
3384
  { GPR64sponly, GPR64sponlyBits, 2483, 1, sizeof(GPR64sponlyBits), AArch64::GPR64sponlyRegClassID, 1, true },
3385
  { DD, DDBits, 175, 32, sizeof(DDBits), AArch64::DDRegClassID, 1, true },
3386
  { XSeqPairsClass, XSeqPairsClassBits, 2456, 32, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 1, true },
3387
  { XSeqPairsClass_with_sub_32_in_GPR32common, XSeqPairsClass_with_sub_32_in_GPR32commonBits, 1442, 31, sizeof(XSeqPairsClass_with_sub_32_in_GPR32commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID, 1, true },
3388
  { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, 1660, 31, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 1, true },
3389
  { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits, 1614, 30, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 1, true },
3390
  { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, 28, 19, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, 1, true },
3391
  { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, 112, 19, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 1, true },
3392
  { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits, 66, 18, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 1, true },
3393
  { FPR128, FPR128Bits, 161, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 1, true },
3394
  { ZPR, ZPRBits, 191, 32, sizeof(ZPRBits), AArch64::ZPRRegClassID, 1, true },
3395
  { FPR128_lo, FPR128_loBits, 1721, 16, sizeof(FPR128_loBits), AArch64::FPR128_loRegClassID, 1, true },
3396
  { ZPR_4b, ZPR_4bBits, 903, 16, sizeof(ZPR_4bBits), AArch64::ZPR_4bRegClassID, 1, true },
3397
  { ZPR_3b, ZPR_3bBits, 221, 8, sizeof(ZPR_3bBits), AArch64::ZPR_3bRegClassID, 1, true },
3398
  { DDD, DDDBits, 174, 32, sizeof(DDDBits), AArch64::DDDRegClassID, 1, true },
3399
  { DDDD, DDDDBits, 173, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 1, true },
3400
  { QQ, QQBits, 180, 32, sizeof(QQBits), AArch64::QQRegClassID, 1, true },
3401
  { ZPR2, ZPR2Bits, 12, 32, sizeof(ZPR2Bits), AArch64::ZPR2RegClassID, 1, true },
3402
  { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 1704, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3403
  { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 1766, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3404
  { ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub1_in_ZPR_4bBits, 884, 16, sizeof(ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3405
  { ZPR2_with_zsub_in_FPR128_lo, ZPR2_with_zsub_in_FPR128_loBits, 2341, 16, sizeof(ZPR2_with_zsub_in_FPR128_loBits), AArch64::ZPR2_with_zsub_in_FPR128_loRegClassID, 1, true },
3406
  { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 1853, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3407
  { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits, 852, 15, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3408
  { ZPR2_with_zsub0_in_ZPR_3b, ZPR2_with_zsub0_in_ZPR_3bBits, 202, 8, sizeof(ZPR2_with_zsub0_in_ZPR_3bBits), AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3409
  { ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub1_in_ZPR_3bBits, 312, 8, sizeof(ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3410
  { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits, 280, 7, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3411
  { QQQ, QQQBits, 179, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 1, true },
3412
  { ZPR3, ZPR3Bits, 17, 32, sizeof(ZPR3Bits), AArch64::ZPR3RegClassID, 1, true },
3413
  { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 1703, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3414
  { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 1765, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3415
  { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 1945, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3416
  { ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4bBits, 942, 16, sizeof(ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3417
  { ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub2_in_ZPR_4bBits, 1056, 16, sizeof(ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3418
  { ZPR3_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_loBits, 2369, 16, sizeof(ZPR3_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub_in_FPR128_loRegClassID, 1, true },
3419
  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 1793, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3420
  { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2095, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3421
  { ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1026, 15, sizeof(ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3422
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits, 910, 15, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3423
  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2035, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3424
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1082, 14, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3425
  { ZPR3_with_zsub0_in_ZPR_3b, ZPR3_with_zsub0_in_ZPR_3bBits, 228, 8, sizeof(ZPR3_with_zsub0_in_ZPR_3bBits), AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3426
  { ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3bBits, 370, 8, sizeof(ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3427
  { ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub2_in_ZPR_3bBits, 484, 8, sizeof(ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3428
  { ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits, 454, 7, sizeof(ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3429
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits, 338, 7, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3430
  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits, 510, 6, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3431
  { QQQQ, QQQQBits, 178, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 1, true },
3432
  { ZPR4, ZPR4Bits, 150, 32, sizeof(ZPR4Bits), AArch64::ZPR4RegClassID, 1, true },
3433
  { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 1702, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3434
  { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 1764, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3435
  { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 1944, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3436
  { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 2188, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3437
  { ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4bBits, 1000, 16, sizeof(ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3438
  { ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4bBits, 1170, 16, sizeof(ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3439
  { ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub3_in_ZPR_4bBits, 1284, 16, sizeof(ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3440
  { ZPR4_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_loBits, 2397, 16, sizeof(ZPR4_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub_in_FPR128_loRegClassID, 1, true },
3441
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 1731, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3442
  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 1973, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3443
  { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2279, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3444
  { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1140, 15, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3445
  { ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1310, 15, sizeof(ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3446
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits, 968, 15, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3447
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 1911, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3448
  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2217, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3449
  { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1254, 14, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3450
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1196, 14, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3451
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2155, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3452
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1366, 13, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3453
  { ZPR4_with_zsub0_in_ZPR_3b, ZPR4_with_zsub0_in_ZPR_3bBits, 254, 8, sizeof(ZPR4_with_zsub0_in_ZPR_3bBits), AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3454
  { ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3bBits, 428, 8, sizeof(ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3455
  { ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3bBits, 598, 8, sizeof(ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3456
  { ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub3_in_ZPR_3bBits, 712, 8, sizeof(ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3457
  { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits, 568, 7, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3458
  { ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 738, 7, sizeof(ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3459
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits, 396, 7, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3460
  { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 682, 6, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3461
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits, 624, 6, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3462
  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits, 794, 5, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3463
};
3464
3465
// AArch64 Dwarf<->LLVM register mappings.
3466
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
3467
  { 0U, AArch64::W0 },
3468
  { 1U, AArch64::W1 },
3469
  { 2U, AArch64::W2 },
3470
  { 3U, AArch64::W3 },
3471
  { 4U, AArch64::W4 },
3472
  { 5U, AArch64::W5 },
3473
  { 6U, AArch64::W6 },
3474
  { 7U, AArch64::W7 },
3475
  { 8U, AArch64::W8 },
3476
  { 9U, AArch64::W9 },
3477
  { 10U, AArch64::W10 },
3478
  { 11U, AArch64::W11 },
3479
  { 12U, AArch64::W12 },
3480
  { 13U, AArch64::W13 },
3481
  { 14U, AArch64::W14 },
3482
  { 15U, AArch64::W15 },
3483
  { 16U, AArch64::W16 },
3484
  { 17U, AArch64::W17 },
3485
  { 18U, AArch64::W18 },
3486
  { 19U, AArch64::W19 },
3487
  { 20U, AArch64::W20 },
3488
  { 21U, AArch64::W21 },
3489
  { 22U, AArch64::W22 },
3490
  { 23U, AArch64::W23 },
3491
  { 24U, AArch64::W24 },
3492
  { 25U, AArch64::W25 },
3493
  { 26U, AArch64::W26 },
3494
  { 27U, AArch64::W27 },
3495
  { 28U, AArch64::W28 },
3496
  { 29U, AArch64::W29 },
3497
  { 30U, AArch64::W30 },
3498
  { 31U, AArch64::WSP },
3499
  { 47U, AArch64::FFR },
3500
  { 48U, AArch64::P0 },
3501
  { 49U, AArch64::P1 },
3502
  { 50U, AArch64::P2 },
3503
  { 51U, AArch64::P3 },
3504
  { 52U, AArch64::P4 },
3505
  { 53U, AArch64::P5 },
3506
  { 54U, AArch64::P6 },
3507
  { 55U, AArch64::P7 },
3508
  { 56U, AArch64::P8 },
3509
  { 57U, AArch64::P9 },
3510
  { 58U, AArch64::P10 },
3511
  { 59U, AArch64::P11 },
3512
  { 60U, AArch64::P12 },
3513
  { 61U, AArch64::P13 },
3514
  { 62U, AArch64::P14 },
3515
  { 63U, AArch64::P15 },
3516
  { 64U, AArch64::B0 },
3517
  { 65U, AArch64::B1 },
3518
  { 66U, AArch64::B2 },
3519
  { 67U, AArch64::B3 },
3520
  { 68U, AArch64::B4 },
3521
  { 69U, AArch64::B5 },
3522
  { 70U, AArch64::B6 },
3523
  { 71U, AArch64::B7 },
3524
  { 72U, AArch64::B8 },
3525
  { 73U, AArch64::B9 },
3526
  { 74U, AArch64::B10 },
3527
  { 75U, AArch64::B11 },
3528
  { 76U, AArch64::B12 },
3529
  { 77U, AArch64::B13 },
3530
  { 78U, AArch64::B14 },
3531
  { 79U, AArch64::B15 },
3532
  { 80U, AArch64::B16 },
3533
  { 81U, AArch64::B17 },
3534
  { 82U, AArch64::B18 },
3535
  { 83U, AArch64::B19 },
3536
  { 84U, AArch64::B20 },
3537
  { 85U, AArch64::B21 },
3538
  { 86U, AArch64::B22 },
3539
  { 87U, AArch64::B23 },
3540
  { 88U, AArch64::B24 },
3541
  { 89U, AArch64::B25 },
3542
  { 90U, AArch64::B26 },
3543
  { 91U, AArch64::B27 },
3544
  { 92U, AArch64::B28 },
3545
  { 93U, AArch64::B29 },
3546
  { 94U, AArch64::B30 },
3547
  { 95U, AArch64::B31 },
3548
  { 96U, AArch64::Z0 },
3549
  { 97U, AArch64::Z1 },
3550
  { 98U, AArch64::Z2 },
3551
  { 99U, AArch64::Z3 },
3552
  { 100U, AArch64::Z4 },
3553
  { 101U, AArch64::Z5 },
3554
  { 102U, AArch64::Z6 },
3555
  { 103U, AArch64::Z7 },
3556
  { 104U, AArch64::Z8 },
3557
  { 105U, AArch64::Z9 },
3558
  { 106U, AArch64::Z10 },
3559
  { 107U, AArch64::Z11 },
3560
  { 108U, AArch64::Z12 },
3561
  { 109U, AArch64::Z13 },
3562
  { 110U, AArch64::Z14 },
3563
  { 111U, AArch64::Z15 },
3564
  { 112U, AArch64::Z16 },
3565
  { 113U, AArch64::Z17 },
3566
  { 114U, AArch64::Z18 },
3567
  { 115U, AArch64::Z19 },
3568
  { 116U, AArch64::Z20 },
3569
  { 117U, AArch64::Z21 },
3570
  { 118U, AArch64::Z22 },
3571
  { 119U, AArch64::Z23 },
3572
  { 120U, AArch64::Z24 },
3573
  { 121U, AArch64::Z25 },
3574
  { 122U, AArch64::Z26 },
3575
  { 123U, AArch64::Z27 },
3576
  { 124U, AArch64::Z28 },
3577
  { 125U, AArch64::Z29 },
3578
  { 126U, AArch64::Z30 },
3579
  { 127U, AArch64::Z31 },
3580
};
3581
extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = array_lengthof(AArch64DwarfFlavour0Dwarf2L);
3582
3583
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
3584
  { 0U, AArch64::W0 },
3585
  { 1U, AArch64::W1 },
3586
  { 2U, AArch64::W2 },
3587
  { 3U, AArch64::W3 },
3588
  { 4U, AArch64::W4 },
3589
  { 5U, AArch64::W5 },
3590
  { 6U, AArch64::W6 },
3591
  { 7U, AArch64::W7 },
3592
  { 8U, AArch64::W8 },
3593
  { 9U, AArch64::W9 },
3594
  { 10U, AArch64::W10 },
3595
  { 11U, AArch64::W11 },
3596
  { 12U, AArch64::W12 },
3597
  { 13U, AArch64::W13 },
3598
  { 14U, AArch64::W14 },
3599
  { 15U, AArch64::W15 },
3600
  { 16U, AArch64::W16 },
3601
  { 17U, AArch64::W17 },
3602
  { 18U, AArch64::W18 },
3603
  { 19U, AArch64::W19 },
3604
  { 20U, AArch64::W20 },
3605
  { 21U, AArch64::W21 },
3606
  { 22U, AArch64::W22 },
3607
  { 23U, AArch64::W23 },
3608
  { 24U, AArch64::W24 },
3609
  { 25U, AArch64::W25 },
3610
  { 26U, AArch64::W26 },
3611
  { 27U, AArch64::W27 },
3612
  { 28U, AArch64::W28 },
3613
  { 29U, AArch64::W29 },
3614
  { 30U, AArch64::W30 },
3615
  { 31U, AArch64::WSP },
3616
  { 47U, AArch64::FFR },
3617
  { 48U, AArch64::P0 },
3618
  { 49U, AArch64::P1 },
3619
  { 50U, AArch64::P2 },
3620
  { 51U, AArch64::P3 },
3621
  { 52U, AArch64::P4 },
3622
  { 53U, AArch64::P5 },
3623
  { 54U, AArch64::P6 },
3624
  { 55U, AArch64::P7 },
3625
  { 56U, AArch64::P8 },
3626
  { 57U, AArch64::P9 },
3627
  { 58U, AArch64::P10 },
3628
  { 59U, AArch64::P11 },
3629
  { 60U, AArch64::P12 },
3630
  { 61U, AArch64::P13 },
3631
  { 62U, AArch64::P14 },
3632
  { 63U, AArch64::P15 },
3633
  { 64U, AArch64::B0 },
3634
  { 65U, AArch64::B1 },
3635
  { 66U, AArch64::B2 },
3636
  { 67U, AArch64::B3 },
3637
  { 68U, AArch64::B4 },
3638
  { 69U, AArch64::B5 },
3639
  { 70U, AArch64::B6 },
3640
  { 71U, AArch64::B7 },
3641
  { 72U, AArch64::B8 },
3642
  { 73U, AArch64::B9 },
3643
  { 74U, AArch64::B10 },
3644
  { 75U, AArch64::B11 },
3645
  { 76U, AArch64::B12 },
3646
  { 77U, AArch64::B13 },
3647
  { 78U, AArch64::B14 },
3648
  { 79U, AArch64::B15 },
3649
  { 80U, AArch64::B16 },
3650
  { 81U, AArch64::B17 },
3651
  { 82U, AArch64::B18 },
3652
  { 83U, AArch64::B19 },
3653
  { 84U, AArch64::B20 },
3654
  { 85U, AArch64::B21 },
3655
  { 86U, AArch64::B22 },
3656
  { 87U, AArch64::B23 },
3657
  { 88U, AArch64::B24 },
3658
  { 89U, AArch64::B25 },
3659
  { 90U, AArch64::B26 },
3660
  { 91U, AArch64::B27 },
3661
  { 92U, AArch64::B28 },
3662
  { 93U, AArch64::B29 },
3663
  { 94U, AArch64::B30 },
3664
  { 95U, AArch64::B31 },
3665
  { 96U, AArch64::Z0 },
3666
  { 97U, AArch64::Z1 },
3667
  { 98U, AArch64::Z2 },
3668
  { 99U, AArch64::Z3 },
3669
  { 100U, AArch64::Z4 },
3670
  { 101U, AArch64::Z5 },
3671
  { 102U, AArch64::Z6 },
3672
  { 103U, AArch64::Z7 },
3673
  { 104U, AArch64::Z8 },
3674
  { 105U, AArch64::Z9 },
3675
  { 106U, AArch64::Z10 },
3676
  { 107U, AArch64::Z11 },
3677
  { 108U, AArch64::Z12 },
3678
  { 109U, AArch64::Z13 },
3679
  { 110U, AArch64::Z14 },
3680
  { 111U, AArch64::Z15 },
3681
  { 112U, AArch64::Z16 },
3682
  { 113U, AArch64::Z17 },
3683
  { 114U, AArch64::Z18 },
3684
  { 115U, AArch64::Z19 },
3685
  { 116U, AArch64::Z20 },
3686
  { 117U, AArch64::Z21 },
3687
  { 118U, AArch64::Z22 },
3688
  { 119U, AArch64::Z23 },
3689
  { 120U, AArch64::Z24 },
3690
  { 121U, AArch64::Z25 },
3691
  { 122U, AArch64::Z26 },
3692
  { 123U, AArch64::Z27 },
3693
  { 124U, AArch64::Z28 },
3694
  { 125U, AArch64::Z29 },
3695
  { 126U, AArch64::Z30 },
3696
  { 127U, AArch64::Z31 },
3697
};
3698
extern const unsigned AArch64EHFlavour0Dwarf2LSize = array_lengthof(AArch64EHFlavour0Dwarf2L);
3699
3700
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
3701
  { AArch64::FFR, 47U },
3702
  { AArch64::FP, 29U },
3703
  { AArch64::LR, 30U },
3704
  { AArch64::SP, 31U },
3705
  { AArch64::WSP, 31U },
3706
  { AArch64::WZR, 31U },
3707
  { AArch64::XZR, 31U },
3708
  { AArch64::B0, 64U },
3709
  { AArch64::B1, 65U },
3710
  { AArch64::B2, 66U },
3711
  { AArch64::B3, 67U },
3712
  { AArch64::B4, 68U },
3713
  { AArch64::B5, 69U },
3714
  { AArch64::B6, 70U },
3715
  { AArch64::B7, 71U },
3716
  { AArch64::B8, 72U },
3717
  { AArch64::B9, 73U },
3718
  { AArch64::B10, 74U },
3719
  { AArch64::B11, 75U },
3720
  { AArch64::B12, 76U },
3721
  { AArch64::B13, 77U },
3722
  { AArch64::B14, 78U },
3723
  { AArch64::B15, 79U },
3724
  { AArch64::B16, 80U },
3725
  { AArch64::B17, 81U },
3726
  { AArch64::B18, 82U },
3727
  { AArch64::B19, 83U },
3728
  { AArch64::B20, 84U },
3729
  { AArch64::B21, 85U },
3730
  { AArch64::B22, 86U },
3731
  { AArch64::B23, 87U },
3732
  { AArch64::B24, 88U },
3733
  { AArch64::B25, 89U },
3734
  { AArch64::B26, 90U },
3735
  { AArch64::B27, 91U },
3736
  { AArch64::B28, 92U },
3737
  { AArch64::B29, 93U },
3738
  { AArch64::B30, 94U },
3739
  { AArch64::B31, 95U },
3740
  { AArch64::D0, 64U },
3741
  { AArch64::D1, 65U },
3742
  { AArch64::D2, 66U },
3743
  { AArch64::D3, 67U },
3744
  { AArch64::D4, 68U },
3745
  { AArch64::D5, 69U },
3746
  { AArch64::D6, 70U },
3747
  { AArch64::D7, 71U },
3748
  { AArch64::D8, 72U },
3749
  { AArch64::D9, 73U },
3750
  { AArch64::D10, 74U },
3751
  { AArch64::D11, 75U },
3752
  { AArch64::D12, 76U },
3753
  { AArch64::D13, 77U },
3754
  { AArch64::D14, 78U },
3755
  { AArch64::D15, 79U },
3756
  { AArch64::D16, 80U },
3757
  { AArch64::D17, 81U },
3758
  { AArch64::D18, 82U },
3759
  { AArch64::D19, 83U },
3760
  { AArch64::D20, 84U },
3761
  { AArch64::D21, 85U },
3762
  { AArch64::D22, 86U },
3763
  { AArch64::D23, 87U },
3764
  { AArch64::D24, 88U },
3765
  { AArch64::D25, 89U },
3766
  { AArch64::D26, 90U },
3767
  { AArch64::D27, 91U },
3768
  { AArch64::D28, 92U },
3769
  { AArch64::D29, 93U },
3770
  { AArch64::D30, 94U },
3771
  { AArch64::D31, 95U },
3772
  { AArch64::H0, 64U },
3773
  { AArch64::H1, 65U },
3774
  { AArch64::H2, 66U },
3775
  { AArch64::H3, 67U },
3776
  { AArch64::H4, 68U },
3777
  { AArch64::H5, 69U },
3778
  { AArch64::H6, 70U },
3779
  { AArch64::H7, 71U },
3780
  { AArch64::H8, 72U },
3781
  { AArch64::H9, 73U },
3782
  { AArch64::H10, 74U },
3783
  { AArch64::H11, 75U },
3784
  { AArch64::H12, 76U },
3785
  { AArch64::H13, 77U },
3786
  { AArch64::H14, 78U },
3787
  { AArch64::H15, 79U },
3788
  { AArch64::H16, 80U },
3789
  { AArch64::H17, 81U },
3790
  { AArch64::H18, 82U },
3791
  { AArch64::H19, 83U },
3792
  { AArch64::H20, 84U },
3793
  { AArch64::H21, 85U },
3794
  { AArch64::H22, 86U },
3795
  { AArch64::H23, 87U },
3796
  { AArch64::H24, 88U },
3797
  { AArch64::H25, 89U },
3798
  { AArch64::H26, 90U },
3799
  { AArch64::H27, 91U },
3800
  { AArch64::H28, 92U },
3801
  { AArch64::H29, 93U },
3802
  { AArch64::H30, 94U },
3803
  { AArch64::H31, 95U },
3804
  { AArch64::P0, 48U },
3805
  { AArch64::P1, 49U },
3806
  { AArch64::P2, 50U },
3807
  { AArch64::P3, 51U },
3808
  { AArch64::P4, 52U },
3809
  { AArch64::P5, 53U },
3810
  { AArch64::P6, 54U },
3811
  { AArch64::P7, 55U },
3812
  { AArch64::P8, 56U },
3813
  { AArch64::P9, 57U },
3814
  { AArch64::P10, 58U },
3815
  { AArch64::P11, 59U },
3816
  { AArch64::P12, 60U },
3817
  { AArch64::P13, 61U },
3818
  { AArch64::P14, 62U },
3819
  { AArch64::P15, 63U },
3820
  { AArch64::Q0, 64U },
3821
  { AArch64::Q1, 65U },
3822
  { AArch64::Q2, 66U },
3823
  { AArch64::Q3, 67U },
3824
  { AArch64::Q4, 68U },
3825
  { AArch64::Q5, 69U },
3826
  { AArch64::Q6, 70U },
3827
  { AArch64::Q7, 71U },
3828
  { AArch64::Q8, 72U },
3829
  { AArch64::Q9, 73U },
3830
  { AArch64::Q10, 74U },
3831
  { AArch64::Q11, 75U },
3832
  { AArch64::Q12, 76U },
3833
  { AArch64::Q13, 77U },
3834
  { AArch64::Q14, 78U },
3835
  { AArch64::Q15, 79U },
3836
  { AArch64::Q16, 80U },
3837
  { AArch64::Q17, 81U },
3838
  { AArch64::Q18, 82U },
3839
  { AArch64::Q19, 83U },
3840
  { AArch64::Q20, 84U },
3841
  { AArch64::Q21, 85U },
3842
  { AArch64::Q22, 86U },
3843
  { AArch64::Q23, 87U },
3844
  { AArch64::Q24, 88U },
3845
  { AArch64::Q25, 89U },
3846
  { AArch64::Q26, 90U },
3847
  { AArch64::Q27, 91U },
3848
  { AArch64::Q28, 92U },
3849
  { AArch64::Q29, 93U },
3850
  { AArch64::Q30, 94U },
3851
  { AArch64::Q31, 95U },
3852
  { AArch64::S0, 64U },
3853
  { AArch64::S1, 65U },
3854
  { AArch64::S2, 66U },
3855
  { AArch64::S3, 67U },
3856
  { AArch64::S4, 68U },
3857
  { AArch64::S5, 69U },
3858
  { AArch64::S6, 70U },
3859
  { AArch64::S7, 71U },
3860
  { AArch64::S8, 72U },
3861
  { AArch64::S9, 73U },
3862
  { AArch64::S10, 74U },
3863
  { AArch64::S11, 75U },
3864
  { AArch64::S12, 76U },
3865
  { AArch64::S13, 77U },
3866
  { AArch64::S14, 78U },
3867
  { AArch64::S15, 79U },
3868
  { AArch64::S16, 80U },
3869
  { AArch64::S17, 81U },
3870
  { AArch64::S18, 82U },
3871
  { AArch64::S19, 83U },
3872
  { AArch64::S20, 84U },
3873
  { AArch64::S21, 85U },
3874
  { AArch64::S22, 86U },
3875
  { AArch64::S23, 87U },
3876
  { AArch64::S24, 88U },
3877
  { AArch64::S25, 89U },
3878
  { AArch64::S26, 90U },
3879
  { AArch64::S27, 91U },
3880
  { AArch64::S28, 92U },
3881
  { AArch64::S29, 93U },
3882
  { AArch64::S30, 94U },
3883
  { AArch64::S31, 95U },
3884
  { AArch64::W0, 0U },
3885
  { AArch64::W1, 1U },
3886
  { AArch64::W2, 2U },
3887
  { AArch64::W3, 3U },
3888
  { AArch64::W4, 4U },
3889
  { AArch64::W5, 5U },
3890
  { AArch64::W6, 6U },
3891
  { AArch64::W7, 7U },
3892
  { AArch64::W8, 8U },
3893
  { AArch64::W9, 9U },
3894
  { AArch64::W10, 10U },
3895
  { AArch64::W11, 11U },
3896
  { AArch64::W12, 12U },
3897
  { AArch64::W13, 13U },
3898
  { AArch64::W14, 14U },
3899
  { AArch64::W15, 15U },
3900
  { AArch64::W16, 16U },
3901
  { AArch64::W17, 17U },
3902
  { AArch64::W18, 18U },
3903
  { AArch64::W19, 19U },
3904
  { AArch64::W20, 20U },
3905
  { AArch64::W21, 21U },
3906
  { AArch64::W22, 22U },
3907
  { AArch64::W23, 23U },
3908
  { AArch64::W24, 24U },
3909
  { AArch64::W25, 25U },
3910
  { AArch64::W26, 26U },
3911
  { AArch64::W27, 27U },
3912
  { AArch64::W28, 28U },
3913
  { AArch64::W29, 29U },
3914
  { AArch64::W30, 30U },
3915
  { AArch64::X0, 0U },
3916
  { AArch64::X1, 1U },
3917
  { AArch64::X2, 2U },
3918
  { AArch64::X3, 3U },
3919
  { AArch64::X4, 4U },
3920
  { AArch64::X5, 5U },
3921
  { AArch64::X6, 6U },
3922
  { AArch64::X7, 7U },
3923
  { AArch64::X8, 8U },
3924
  { AArch64::X9, 9U },
3925
  { AArch64::X10, 10U },
3926
  { AArch64::X11, 11U },
3927
  { AArch64::X12, 12U },
3928
  { AArch64::X13, 13U },
3929
  { AArch64::X14, 14U },
3930
  { AArch64::X15, 15U },
3931
  { AArch64::X16, 16U },
3932
  { AArch64::X17, 17U },
3933
  { AArch64::X18, 18U },
3934
  { AArch64::X19, 19U },
3935
  { AArch64::X20, 20U },
3936
  { AArch64::X21, 21U },
3937
  { AArch64::X22, 22U },
3938
  { AArch64::X23, 23U },
3939
  { AArch64::X24, 24U },
3940
  { AArch64::X25, 25U },
3941
  { AArch64::X26, 26U },
3942
  { AArch64::X27, 27U },
3943
  { AArch64::X28, 28U },
3944
  { AArch64::Z0, 96U },
3945
  { AArch64::Z1, 97U },
3946
  { AArch64::Z2, 98U },
3947
  { AArch64::Z3, 99U },
3948
  { AArch64::Z4, 100U },
3949
  { AArch64::Z5, 101U },
3950
  { AArch64::Z6, 102U },
3951
  { AArch64::Z7, 103U },
3952
  { AArch64::Z8, 104U },
3953
  { AArch64::Z9, 105U },
3954
  { AArch64::Z10, 106U },
3955
  { AArch64::Z11, 107U },
3956
  { AArch64::Z12, 108U },
3957
  { AArch64::Z13, 109U },
3958
  { AArch64::Z14, 110U },
3959
  { AArch64::Z15, 111U },
3960
  { AArch64::Z16, 112U },
3961
  { AArch64::Z17, 113U },
3962
  { AArch64::Z18, 114U },
3963
  { AArch64::Z19, 115U },
3964
  { AArch64::Z20, 116U },
3965
  { AArch64::Z21, 117U },
3966
  { AArch64::Z22, 118U },
3967
  { AArch64::Z23, 119U },
3968
  { AArch64::Z24, 120U },
3969
  { AArch64::Z25, 121U },
3970
  { AArch64::Z26, 122U },
3971
  { AArch64::Z27, 123U },
3972
  { AArch64::Z28, 124U },
3973
  { AArch64::Z29, 125U },
3974
  { AArch64::Z30, 126U },
3975
  { AArch64::Z31, 127U },
3976
};
3977
extern const unsigned AArch64DwarfFlavour0L2DwarfSize = array_lengthof(AArch64DwarfFlavour0L2Dwarf);
3978
3979
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
3980
  { AArch64::FFR, 47U },
3981
  { AArch64::FP, 29U },
3982
  { AArch64::LR, 30U },
3983
  { AArch64::SP, 31U },
3984
  { AArch64::WSP, 31U },
3985
  { AArch64::WZR, 31U },
3986
  { AArch64::XZR, 31U },
3987
  { AArch64::B0, 64U },
3988
  { AArch64::B1, 65U },
3989
  { AArch64::B2, 66U },
3990
  { AArch64::B3, 67U },
3991
  { AArch64::B4, 68U },
3992
  { AArch64::B5, 69U },
3993
  { AArch64::B6, 70U },
3994
  { AArch64::B7, 71U },
3995
  { AArch64::B8, 72U },
3996
  { AArch64::B9, 73U },
3997
  { AArch64::B10, 74U },
3998
  { AArch64::B11, 75U },
3999
  { AArch64::B12, 76U },
4000
  { AArch64::B13, 77U },
4001
  { AArch64::B14, 78U },
4002
  { AArch64::B15, 79U },
4003
  { AArch64::B16, 80U },
4004
  { AArch64::B17, 81U },
4005
  { AArch64::B18, 82U },
4006
  { AArch64::B19, 83U },
4007
  { AArch64::B20, 84U },
4008
  { AArch64::B21, 85U },
4009
  { AArch64::B22, 86U },
4010
  { AArch64::B23, 87U },
4011
  { AArch64::B24, 88U },
4012
  { AArch64::B25, 89U },
4013
  { AArch64::B26, 90U },
4014
  { AArch64::B27, 91U },
4015
  { AArch64::B28, 92U },
4016
  { AArch64::B29, 93U },
4017
  { AArch64::B30, 94U },
4018
  { AArch64::B31, 95U },
4019
  { AArch64::D0, 64U },
4020
  { AArch64::D1, 65U },
4021
  { AArch64::D2, 66U },
4022
  { AArch64::D3, 67U },
4023
  { AArch64::D4, 68U },
4024
  { AArch64::D5, 69U },
4025
  { AArch64::D6, 70U },
4026
  { AArch64::D7, 71U },
4027
  { AArch64::D8, 72U },
4028
  { AArch64::D9, 73U },
4029
  { AArch64::D10, 74U },
4030
  { AArch64::D11, 75U },
4031
  { AArch64::D12, 76U },
4032
  { AArch64::D13, 77U },
4033
  { AArch64::D14, 78U },
4034
  { AArch64::D15, 79U },
4035
  { AArch64::D16, 80U },
4036
  { AArch64::D17, 81U },
4037
  { AArch64::D18, 82U },
4038
  { AArch64::D19, 83U },
4039
  { AArch64::D20, 84U },
4040
  { AArch64::D21, 85U },
4041
  { AArch64::D22, 86U },
4042
  { AArch64::D23, 87U },
4043
  { AArch64::D24, 88U },
4044
  { AArch64::D25, 89U },
4045
  { AArch64::D26, 90U },
4046
  { AArch64::D27, 91U },
4047
  { AArch64::D28, 92U },
4048
  { AArch64::D29, 93U },
4049
  { AArch64::D30, 94U },
4050
  { AArch64::D31, 95U },
4051
  { AArch64::H0, 64U },
4052
  { AArch64::H1, 65U },
4053
  { AArch64::H2, 66U },
4054
  { AArch64::H3, 67U },
4055
  { AArch64::H4, 68U },
4056
  { AArch64::H5, 69U },
4057
  { AArch64::H6, 70U },
4058
  { AArch64::H7, 71U },
4059
  { AArch64::H8, 72U },
4060
  { AArch64::H9, 73U },
4061
  { AArch64::H10, 74U },
4062
  { AArch64::H11, 75U },
4063
  { AArch64::H12, 76U },
4064
  { AArch64::H13, 77U },
4065
  { AArch64::H14, 78U },
4066
  { AArch64::H15, 79U },
4067
  { AArch64::H16, 80U },
4068
  { AArch64::H17, 81U },
4069
  { AArch64::H18, 82U },
4070
  { AArch64::H19, 83U },
4071
  { AArch64::H20, 84U },
4072
  { AArch64::H21, 85U },
4073
  { AArch64::H22, 86U },
4074
  { AArch64::H23, 87U },
4075
  { AArch64::H24, 88U },
4076
  { AArch64::H25, 89U },
4077
  { AArch64::H26, 90U },
4078
  { AArch64::H27, 91U },
4079
  { AArch64::H28, 92U },
4080
  { AArch64::H29, 93U },
4081
  { AArch64::H30, 94U },
4082
  { AArch64::H31, 95U },
4083
  { AArch64::P0, 48U },
4084
  { AArch64::P1, 49U },
4085
  { AArch64::P2, 50U },
4086
  { AArch64::P3, 51U },
4087
  { AArch64::P4, 52U },
4088
  { AArch64::P5, 53U },
4089
  { AArch64::P6, 54U },
4090
  { AArch64::P7, 55U },
4091
  { AArch64::P8, 56U },
4092
  { AArch64::P9, 57U },
4093
  { AArch64::P10, 58U },
4094
  { AArch64::P11, 59U },
4095
  { AArch64::P12, 60U },
4096
  { AArch64::P13, 61U },
4097
  { AArch64::P14, 62U },
4098
  { AArch64::P15, 63U },
4099
  { AArch64::Q0, 64U },
4100
  { AArch64::Q1, 65U },
4101
  { AArch64::Q2, 66U },
4102
  { AArch64::Q3, 67U },
4103
  { AArch64::Q4, 68U },
4104
  { AArch64::Q5, 69U },
4105
  { AArch64::Q6, 70U },
4106
  { AArch64::Q7, 71U },
4107
  { AArch64::Q8, 72U },
4108
  { AArch64::Q9, 73U },
4109
  { AArch64::Q10, 74U },
4110
  { AArch64::Q11, 75U },
4111
  { AArch64::Q12, 76U },
4112
  { AArch64::Q13, 77U },
4113
  { AArch64::Q14, 78U },
4114
  { AArch64::Q15, 79U },
4115
  { AArch64::Q16, 80U },
4116
  { AArch64::Q17, 81U },
4117
  { AArch64::Q18, 82U },
4118
  { AArch64::Q19, 83U },
4119
  { AArch64::Q20, 84U },
4120
  { AArch64::Q21, 85U },
4121
  { AArch64::Q22, 86U },
4122
  { AArch64::Q23, 87U },
4123
  { AArch64::Q24, 88U },
4124
  { AArch64::Q25, 89U },
4125
  { AArch64::Q26, 90U },
4126
  { AArch64::Q27, 91U },
4127
  { AArch64::Q28, 92U },
4128
  { AArch64::Q29, 93U },
4129
  { AArch64::Q30, 94U },
4130
  { AArch64::Q31, 95U },
4131
  { AArch64::S0, 64U },
4132
  { AArch64::S1, 65U },
4133
  { AArch64::S2, 66U },
4134
  { AArch64::S3, 67U },
4135
  { AArch64::S4, 68U },
4136
  { AArch64::S5, 69U },
4137
  { AArch64::S6, 70U },
4138
  { AArch64::S7, 71U },
4139
  { AArch64::S8, 72U },
4140
  { AArch64::S9, 73U },
4141
  { AArch64::S10, 74U },
4142
  { AArch64::S11, 75U },
4143
  { AArch64::S12, 76U },
4144
  { AArch64::S13, 77U },
4145
  { AArch64::S14, 78U },
4146
  { AArch64::S15, 79U },
4147
  { AArch64::S16, 80U },
4148
  { AArch64::S17, 81U },
4149
  { AArch64::S18, 82U },
4150
  { AArch64::S19, 83U },
4151
  { AArch64::S20, 84U },
4152
  { AArch64::S21, 85U },
4153
  { AArch64::S22, 86U },
4154
  { AArch64::S23, 87U },
4155
  { AArch64::S24, 88U },
4156
  { AArch64::S25, 89U },
4157
  { AArch64::S26, 90U },
4158
  { AArch64::S27, 91U },
4159
  { AArch64::S28, 92U },
4160
  { AArch64::S29, 93U },
4161
  { AArch64::S30, 94U },
4162
  { AArch64::S31, 95U },
4163
  { AArch64::W0, 0U },
4164
  { AArch64::W1, 1U },
4165
  { AArch64::W2, 2U },
4166
  { AArch64::W3, 3U },
4167
  { AArch64::W4, 4U },
4168
  { AArch64::W5, 5U },
4169
  { AArch64::W6, 6U },
4170
  { AArch64::W7, 7U },
4171
  { AArch64::W8, 8U },
4172
  { AArch64::W9, 9U },
4173
  { AArch64::W10, 10U },
4174
  { AArch64::W11, 11U },
4175
  { AArch64::W12, 12U },
4176
  { AArch64::W13, 13U },
4177
  { AArch64::W14, 14U },
4178
  { AArch64::W15, 15U },
4179
  { AArch64::W16, 16U },
4180
  { AArch64::W17, 17U },
4181
  { AArch64::W18, 18U },
4182
  { AArch64::W19, 19U },
4183
  { AArch64::W20, 20U },
4184
  { AArch64::W21, 21U },
4185
  { AArch64::W22, 22U },
4186
  { AArch64::W23, 23U },
4187
  { AArch64::W24, 24U },
4188
  { AArch64::W25, 25U },
4189
  { AArch64::W26, 26U },
4190
  { AArch64::W27, 27U },
4191
  { AArch64::W28, 28U },
4192
  { AArch64::W29, 29U },
4193
  { AArch64::W30, 30U },
4194
  { AArch64::X0, 0U },
4195
  { AArch64::X1, 1U },
4196
  { AArch64::X2, 2U },
4197
  { AArch64::X3, 3U },
4198
  { AArch64::X4, 4U },
4199
  { AArch64::X5, 5U },
4200
  { AArch64::X6, 6U },
4201
  { AArch64::X7, 7U },
4202
  { AArch64::X8, 8U },
4203
  { AArch64::X9, 9U },
4204
  { AArch64::X10, 10U },
4205
  { AArch64::X11, 11U },
4206
  { AArch64::X12, 12U },
4207
  { AArch64::X13, 13U },
4208
  { AArch64::X14, 14U },
4209
  { AArch64::X15, 15U },
4210
  { AArch64::X16, 16U },
4211
  { AArch64::X17, 17U },
4212
  { AArch64::X18, 18U },
4213
  { AArch64::X19, 19U },
4214
  { AArch64::X20, 20U },
4215
  { AArch64::X21, 21U },
4216
  { AArch64::X22, 22U },
4217
  { AArch64::X23, 23U },
4218
  { AArch64::X24, 24U },
4219
  { AArch64::X25, 25U },
4220
  { AArch64::X26, 26U },
4221
  { AArch64::X27, 27U },
4222
  { AArch64::X28, 28U },
4223
  { AArch64::Z0, 96U },
4224
  { AArch64::Z1, 97U },
4225
  { AArch64::Z2, 98U },
4226
  { AArch64::Z3, 99U },
4227
  { AArch64::Z4, 100U },
4228
  { AArch64::Z5, 101U },
4229
  { AArch64::Z6, 102U },
4230
  { AArch64::Z7, 103U },
4231
  { AArch64::Z8, 104U },
4232
  { AArch64::Z9, 105U },
4233
  { AArch64::Z10, 106U },
4234
  { AArch64::Z11, 107U },
4235
  { AArch64::Z12, 108U },
4236
  { AArch64::Z13, 109U },
4237
  { AArch64::Z14, 110U },
4238
  { AArch64::Z15, 111U },
4239
  { AArch64::Z16, 112U },
4240
  { AArch64::Z17, 113U },
4241
  { AArch64::Z18, 114U },
4242
  { AArch64::Z19, 115U },
4243
  { AArch64::Z20, 116U },
4244
  { AArch64::Z21, 117U },
4245
  { AArch64::Z22, 118U },
4246
  { AArch64::Z23, 119U },
4247
  { AArch64::Z24, 120U },
4248
  { AArch64::Z25, 121U },
4249
  { AArch64::Z26, 122U },
4250
  { AArch64::Z27, 123U },
4251
  { AArch64::Z28, 124U },
4252
  { AArch64::Z29, 125U },
4253
  { AArch64::Z30, 126U },
4254
  { AArch64::Z31, 127U },
4255
};
4256
extern const unsigned AArch64EHFlavour0L2DwarfSize = array_lengthof(AArch64EHFlavour0L2Dwarf);
4257
4258
extern const uint16_t AArch64RegEncodingTable[] = {
4259
  0,
4260
  0,
4261
  29,
4262
  30,
4263
  0,
4264
  31,
4265
  31,
4266
  31,
4267
  31,
4268
  0,
4269
  1,
4270
  2,
4271
  3,
4272
  4,
4273
  5,
4274
  6,
4275
  7,
4276
  8,
4277
  9,
4278
  10,
4279
  11,
4280
  12,
4281
  13,
4282
  14,
4283
  15,
4284
  16,
4285
  17,
4286
  18,
4287
  19,
4288
  20,
4289
  21,
4290
  22,
4291
  23,
4292
  24,
4293
  25,
4294
  26,
4295
  27,
4296
  28,
4297
  29,
4298
  30,
4299
  31,
4300
  0,
4301
  1,
4302
  2,
4303
  3,
4304
  4,
4305
  5,
4306
  6,
4307
  7,
4308
  8,
4309
  9,
4310
  10,
4311
  11,
4312
  12,
4313
  13,
4314
  14,
4315
  15,
4316
  16,
4317
  17,
4318
  18,
4319
  19,
4320
  20,
4321
  21,
4322
  22,
4323
  23,
4324
  24,
4325
  25,
4326
  26,
4327
  27,
4328
  28,
4329
  29,
4330
  30,
4331
  31,
4332
  0,
4333
  1,
4334
  2,
4335
  3,
4336
  4,
4337
  5,
4338
  6,
4339
  7,
4340
  8,
4341
  9,
4342
  10,
4343
  11,
4344
  12,
4345
  13,
4346
  14,
4347
  15,
4348
  16,
4349
  17,
4350
  18,
4351
  19,
4352
  20,
4353
  21,
4354
  22,
4355
  23,
4356
  24,
4357
  25,
4358
  26,
4359
  27,
4360
  28,
4361
  29,
4362
  30,
4363
  31,
4364
  0,
4365
  1,
4366
  2,
4367
  3,
4368
  4,
4369
  5,
4370
  6,
4371
  7,
4372
  8,
4373
  9,
4374
  10,
4375
  11,
4376
  12,
4377
  13,
4378
  14,
4379
  15,
4380
  0,
4381
  1,
4382
  2,
4383
  3,
4384
  4,
4385
  5,
4386
  6,
4387
  7,
4388
  8,
4389
  9,
4390
  10,
4391
  11,
4392
  12,
4393
  13,
4394
  14,
4395
  15,
4396
  16,
4397
  17,
4398
  18,
4399
  19,
4400
  20,
4401
  21,
4402
  22,
4403
  23,
4404
  24,
4405
  25,
4406
  26,
4407
  27,
4408
  28,
4409
  29,
4410
  30,
4411
  31,
4412
  0,
4413
  1,
4414
  2,
4415
  3,
4416
  4,
4417
  5,
4418
  6,
4419
  7,
4420
  8,
4421
  9,
4422
  10,
4423
  11,
4424
  12,
4425
  13,
4426
  14,
4427
  15,
4428
  16,
4429
  17,
4430
  18,
4431
  19,
4432
  20,
4433
  21,
4434
  22,
4435
  23,
4436
  24,
4437
  25,
4438
  26,
4439
  27,
4440
  28,
4441
  29,
4442
  30,
4443
  31,
4444
  0,
4445
  1,
4446
  2,
4447
  3,
4448
  4,
4449
  5,
4450
  6,
4451
  7,
4452
  8,
4453
  9,
4454
  10,
4455
  11,
4456
  12,
4457
  13,
4458
  14,
4459
  15,
4460
  16,
4461
  17,
4462
  18,
4463
  19,
4464
  20,
4465
  21,
4466
  22,
4467
  23,
4468
  24,
4469
  25,
4470
  26,
4471
  27,
4472
  28,
4473
  29,
4474
  30,
4475
  0,
4476
  1,
4477
  2,
4478
  3,
4479
  4,
4480
  5,
4481
  6,
4482
  7,
4483
  8,
4484
  9,
4485
  10,
4486
  11,
4487
  12,
4488
  13,
4489
  14,
4490
  15,
4491
  16,
4492
  17,
4493
  18,
4494
  19,
4495
  20,
4496
  21,
4497
  22,
4498
  23,
4499
  24,
4500
  25,
4501
  26,
4502
  27,
4503
  28,
4504
  0,
4505
  1,
4506
  2,
4507
  3,
4508
  4,
4509
  5,
4510
  6,
4511
  7,
4512
  8,
4513
  9,
4514
  10,
4515
  11,
4516
  12,
4517
  13,
4518
  14,
4519
  15,
4520
  16,
4521
  17,
4522
  18,
4523
  19,
4524
  20,
4525
  21,
4526
  22,
4527
  23,
4528
  24,
4529
  25,
4530
  26,
4531
  27,
4532
  28,
4533
  29,
4534
  30,
4535
  31,
4536
  0,
4537
  1,
4538
  2,
4539
  3,
4540
  4,
4541
  5,
4542
  6,
4543
  7,
4544
  8,
4545
  9,
4546
  10,
4547
  11,
4548
  12,
4549
  13,
4550
  14,
4551
  15,
4552
  16,
4553
  17,
4554
  18,
4555
  19,
4556
  20,
4557
  21,
4558
  22,
4559
  23,
4560
  24,
4561
  25,
4562
  26,
4563
  27,
4564
  28,
4565
  29,
4566
  30,
4567
  31,
4568
  0,
4569
  1,
4570
  2,
4571
  3,
4572
  4,
4573
  5,
4574
  6,
4575
  7,
4576
  8,
4577
  9,
4578
  10,
4579
  11,
4580
  12,
4581
  13,
4582
  14,
4583
  15,
4584
  16,
4585
  17,
4586
  18,
4587
  19,
4588
  20,
4589
  21,
4590
  22,
4591
  23,
4592
  24,
4593
  25,
4594
  26,
4595
  27,
4596
  28,
4597
  29,
4598
  30,
4599
  31,
4600
  0,
4601
  1,
4602
  2,
4603
  3,
4604
  4,
4605
  5,
4606
  6,
4607
  7,
4608
  8,
4609
  9,
4610
  10,
4611
  11,
4612
  12,
4613
  13,
4614
  14,
4615
  15,
4616
  16,
4617
  17,
4618
  18,
4619
  19,
4620
  20,
4621
  21,
4622
  22,
4623
  23,
4624
  24,
4625
  25,
4626
  26,
4627
  27,
4628
  28,
4629
  29,
4630
  30,
4631
  31,
4632
  0,
4633
  1,
4634
  2,
4635
  3,
4636
  4,
4637
  5,
4638
  6,
4639
  7,
4640
  8,
4641
  9,
4642
  10,
4643
  11,
4644
  12,
4645
  13,
4646
  14,
4647
  15,
4648
  16,
4649
  17,
4650
  18,
4651
  19,
4652
  20,
4653
  21,
4654
  22,
4655
  23,
4656
  24,
4657
  25,
4658
  26,
4659
  27,
4660
  28,
4661
  29,
4662
  30,
4663
  31,
4664
  0,
4665
  1,
4666
  2,
4667
  3,
4668
  4,
4669
  5,
4670
  6,
4671
  7,
4672
  8,
4673
  9,
4674
  10,
4675
  11,
4676
  12,
4677
  13,
4678
  14,
4679
  15,
4680
  16,
4681
  17,
4682
  18,
4683
  19,
4684
  20,
4685
  21,
4686
  22,
4687
  23,
4688
  24,
4689
  25,
4690
  26,
4691
  27,
4692
  28,
4693
  29,
4694
  30,
4695
  31,
4696
  0,
4697
  1,
4698
  2,
4699
  3,
4700
  4,
4701
  5,
4702
  6,
4703
  7,
4704
  8,
4705
  9,
4706
  10,
4707
  11,
4708
  12,
4709
  13,
4710
  14,
4711
  15,
4712
  16,
4713
  17,
4714
  18,
4715
  19,
4716
  20,
4717
  21,
4718
  22,
4719
  23,
4720
  24,
4721
  25,
4722
  26,
4723
  27,
4724
  28,
4725
  29,
4726
  30,
4727
  31,
4728
  0,
4729
  1,
4730
  2,
4731
  3,
4732
  4,
4733
  5,
4734
  6,
4735
  7,
4736
  8,
4737
  9,
4738
  10,
4739
  11,
4740
  12,
4741
  13,
4742
  14,
4743
  15,
4744
  16,
4745
  17,
4746
  18,
4747
  19,
4748
  20,
4749
  21,
4750
  22,
4751
  23,
4752
  24,
4753
  25,
4754
  26,
4755
  27,
4756
  28,
4757
  29,
4758
  30,
4759
  31,
4760
  31,
4761
  30,
4762
  0,
4763
  1,
4764
  2,
4765
  3,
4766
  4,
4767
  5,
4768
  6,
4769
  7,
4770
  8,
4771
  9,
4772
  10,
4773
  11,
4774
  12,
4775
  13,
4776
  14,
4777
  15,
4778
  16,
4779
  17,
4780
  18,
4781
  19,
4782
  20,
4783
  21,
4784
  22,
4785
  23,
4786
  24,
4787
  25,
4788
  26,
4789
  27,
4790
  28,
4791
  29,
4792
  29,
4793
  30,
4794
  31,
4795
  28,
4796
  0,
4797
  1,
4798
  2,
4799
  3,
4800
  4,
4801
  5,
4802
  6,
4803
  7,
4804
  8,
4805
  9,
4806
  10,
4807
  11,
4808
  12,
4809
  13,
4810
  14,
4811
  15,
4812
  16,
4813
  17,
4814
  18,
4815
  19,
4816
  20,
4817
  21,
4818
  22,
4819
  23,
4820
  24,
4821
  25,
4822
  26,
4823
  27,
4824
  0,
4825
  1,
4826
  2,
4827
  3,
4828
  4,
4829
  5,
4830
  6,
4831
  7,
4832
  8,
4833
  9,
4834
  10,
4835
  11,
4836
  12,
4837
  13,
4838
  14,
4839
  15,
4840
  16,
4841
  17,
4842
  18,
4843
  19,
4844
  20,
4845
  21,
4846
  22,
4847
  23,
4848
  24,
4849
  25,
4850
  26,
4851
  27,
4852
  28,
4853
  29,
4854
  30,
4855
  31,
4856
  0,
4857
  1,
4858
  2,
4859
  3,
4860
  4,
4861
  5,
4862
  6,
4863
  7,
4864
  8,
4865
  9,
4866
  10,
4867
  11,
4868
  12,
4869
  13,
4870
  14,
4871
  15,
4872
  16,
4873
  17,
4874
  18,
4875
  19,
4876
  20,
4877
  21,
4878
  22,
4879
  23,
4880
  24,
4881
  25,
4882
  26,
4883
  27,
4884
  28,
4885
  29,
4886
  30,
4887
  31,
4888
  0,
4889
  1,
4890
  2,
4891
  3,
4892
  4,
4893
  5,
4894
  6,
4895
  7,
4896
  8,
4897
  9,
4898
  10,
4899
  11,
4900
  12,
4901
  13,
4902
  14,
4903
  15,
4904
  16,
4905
  17,
4906
  18,
4907
  19,
4908
  20,
4909
  21,
4910
  22,
4911
  23,
4912
  24,
4913
  25,
4914
  26,
4915
  27,
4916
  28,
4917
  29,
4918
  30,
4919
  31,
4920
};
4921
12.0k
static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4922
12.0k
  RI->InitMCRegisterInfo(AArch64RegDesc, 661, RA, PC, AArch64MCRegisterClasses, 100, AArch64RegUnitRoots, 115, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 100,
4923
12.0k
AArch64SubRegIdxRanges, AArch64RegEncodingTable);
4924
12.0k
4925
12.0k
  switch (DwarfFlavour) {
4926
12.0k
  default:
4927
0
    llvm_unreachable("Unknown DWARF flavour");
4928
12.0k
  case 0:
4929
12.0k
    RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
4930
12.0k
    break;
4931
12.0k
  }
4932
12.0k
  switch (EHFlavour) {
4933
12.0k
  default:
4934
0
    llvm_unreachable("Unknown DWARF flavour");
4935
12.0k
  case 0:
4936
12.0k
    RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
4937
12.0k
    break;
4938
12.0k
  }
4939
12.0k
  switch (DwarfFlavour) {
4940
12.0k
  default:
4941
0
    llvm_unreachable("Unknown DWARF flavour");
4942
12.0k
  case 0:
4943
12.0k
    RI->mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
4944
12.0k
    break;
4945
12.0k
  }
4946
12.0k
  switch (EHFlavour) {
4947
12.0k
  default:
4948
0
    llvm_unreachable("Unknown DWARF flavour");
4949
12.0k
  case 0:
4950
12.0k
    RI->mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
4951
12.0k
    break;
4952
12.0k
  }
4953
12.0k
}
4954
4955
} // end namespace llvm
4956
4957
#endif // GET_REGINFO_MC_DESC
4958
4959
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4960
|*                                                                            *|
4961
|* Register Information Header Fragment                                       *|
4962
|*                                                                            *|
4963
|* Automatically generated file, do not edit!                                 *|
4964
|*                                                                            *|
4965
\*===----------------------------------------------------------------------===*/
4966
4967
4968
#ifdef GET_REGINFO_HEADER
4969
#undef GET_REGINFO_HEADER
4970
4971
#include "llvm/CodeGen/TargetRegisterInfo.h"
4972
4973
namespace llvm {
4974
4975
class AArch64FrameLowering;
4976
4977
struct AArch64GenRegisterInfo : public TargetRegisterInfo {
4978
  explicit AArch64GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
4979
      unsigned PC = 0, unsigned HwMode = 0);
4980
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
4981
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4982
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4983
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
4984
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
4985
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
4986
  unsigned getNumRegPressureSets() const override;
4987
  const char *getRegPressureSetName(unsigned Idx) const override;
4988
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
4989
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
4990
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
4991
  ArrayRef<const char *> getRegMaskNames() const override;
4992
  ArrayRef<const uint32_t *> getRegMasks() const override;
4993
  /// Devirtualized TargetFrameLowering.
4994
  static const AArch64FrameLowering *getFrameLowering(
4995
      const MachineFunction &MF);
4996
};
4997
4998
namespace AArch64 { // Register classes
4999
  extern const TargetRegisterClass FPR8RegClass;
5000
  extern const TargetRegisterClass FPR16RegClass;
5001
  extern const TargetRegisterClass PPRRegClass;
5002
  extern const TargetRegisterClass PPR_3bRegClass;
5003
  extern const TargetRegisterClass GPR32allRegClass;
5004
  extern const TargetRegisterClass FPR32RegClass;
5005
  extern const TargetRegisterClass GPR32RegClass;
5006
  extern const TargetRegisterClass GPR32spRegClass;
5007
  extern const TargetRegisterClass GPR32commonRegClass;
5008
  extern const TargetRegisterClass CCRRegClass;
5009
  extern const TargetRegisterClass GPR32sponlyRegClass;
5010
  extern const TargetRegisterClass WSeqPairsClassRegClass;
5011
  extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass;
5012
  extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
5013
  extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
5014
  extern const TargetRegisterClass GPR64allRegClass;
5015
  extern const TargetRegisterClass FPR64RegClass;
5016
  extern const TargetRegisterClass GPR64RegClass;
5017
  extern const TargetRegisterClass GPR64spRegClass;
5018
  extern const TargetRegisterClass GPR64commonRegClass;
5019
  extern const TargetRegisterClass tcGPR64RegClass;
5020
  extern const TargetRegisterClass GPR64sponlyRegClass;
5021
  extern const TargetRegisterClass DDRegClass;
5022
  extern const TargetRegisterClass XSeqPairsClassRegClass;
5023
  extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32commonRegClass;
5024
  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
5025
  extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
5026
  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass;
5027
  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
5028
  extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
5029
  extern const TargetRegisterClass FPR128RegClass;
5030
  extern const TargetRegisterClass ZPRRegClass;
5031
  extern const TargetRegisterClass FPR128_loRegClass;
5032
  extern const TargetRegisterClass ZPR_4bRegClass;
5033
  extern const TargetRegisterClass ZPR_3bRegClass;
5034
  extern const TargetRegisterClass DDDRegClass;
5035
  extern const TargetRegisterClass DDDDRegClass;
5036
  extern const TargetRegisterClass QQRegClass;
5037
  extern const TargetRegisterClass ZPR2RegClass;
5038
  extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass;
5039
  extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass;
5040
  extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_4bRegClass;
5041
  extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_loRegClass;
5042
  extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass;
5043
  extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass;
5044
  extern const TargetRegisterClass ZPR2_with_zsub0_in_ZPR_3bRegClass;
5045
  extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_3bRegClass;
5046
  extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass;
5047
  extern const TargetRegisterClass QQQRegClass;
5048
  extern const TargetRegisterClass ZPR3RegClass;
5049
  extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass;
5050
  extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass;
5051
  extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass;
5052
  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4bRegClass;
5053
  extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_4bRegClass;
5054
  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_loRegClass;
5055
  extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass;
5056
  extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
5057
  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass;
5058
  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass;
5059
  extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
5060
  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass;
5061
  extern const TargetRegisterClass ZPR3_with_zsub0_in_ZPR_3bRegClass;
5062
  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3bRegClass;
5063
  extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_3bRegClass;
5064
  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass;
5065
  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass;
5066
  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass;
5067
  extern const TargetRegisterClass QQQQRegClass;
5068
  extern const TargetRegisterClass ZPR4RegClass;
5069
  extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass;
5070
  extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass;
5071
  extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass;
5072
  extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass;
5073
  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4bRegClass;
5074
  extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4bRegClass;
5075
  extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_4bRegClass;
5076
  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_loRegClass;
5077
  extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass;
5078
  extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
5079
  extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
5080
  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass;