Coverage Report

Created: 2018-12-14 11:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenCallingConv.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Calling Convention Implementation Fragment                                 *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
10
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
11
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
12
static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
13
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
14
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
15
static bool CC_SI(unsigned ValNo, MVT ValVT,
16
                  MVT LocVT, CCValAssign::LocInfo LocInfo,
17
                  ISD::ArgFlagsTy ArgFlags, CCState &State);
18
static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
19
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
20
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
21
static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
22
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
23
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
24
25
26
static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
27
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
28
15.3k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
29
15.3k
30
15.3k
  if (static_cast<const GCNSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
31
15.3k
    if (!CC_SI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
32
15.3k
      return false;
33
0
  }
34
0
35
0
  if (static_cast<const GCNSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C) {
36
0
    if (!CC_AMDGPU_Func(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
37
0
      return false;
38
0
  }
39
0
40
0
  return true;  // CC didn't match.
41
0
}
42
43
44
static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
45
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
46
9.36k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
47
9.36k
48
9.36k
  if (ArgFlags.isByVal()) {
49
118
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
50
118
    return false;
51
118
  }
52
9.24k
53
9.24k
  if (LocVT == MVT::i1) {
54
30
    LocVT = MVT::i32;
55
30
    if (ArgFlags.isSExt())
56
7
        LocInfo = CCValAssign::SExt;
57
23
    else if (ArgFlags.isZExt())
58
7
        LocInfo = CCValAssign::ZExt;
59
16
    else
60
16
        LocInfo = CCValAssign::AExt;
61
30
  }
62
9.24k
63
9.24k
  if (LocVT == MVT::i1 ||
64
9.24k
      LocVT == MVT::i8 ||
65
9.24k
      LocVT == MVT::i16) {
66
249
    if (ArgFlags.isSExt() || 
ArgFlags.isZExt()238
) {
67
26
      LocVT = MVT::i32;
68
26
      if (ArgFlags.isSExt())
69
11
            LocInfo = CCValAssign::SExt;
70
15
      else if (ArgFlags.isZExt())
71
15
            LocInfo = CCValAssign::ZExt;
72
0
      else
73
0
            LocInfo = CCValAssign::AExt;
74
26
    }
75
249
  }
76
9.24k
77
9.24k
  if (LocVT == MVT::i32 ||
78
9.24k
      
LocVT == MVT::f322.95k
||
79
9.24k
      
LocVT == MVT::i161.83k
||
80
9.24k
      
LocVT == MVT::f161.61k
||
81
9.24k
      
LocVT == MVT::v2i161.08k
||
82
9.24k
      
LocVT == MVT::v2f16918
||
83
9.24k
      
LocVT == MVT::i1442
) {
84
8.80k
    static const MCPhysReg RegList1[] = {
85
8.80k
      AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
86
8.80k
    };
87
8.80k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
88
8.41k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
89
8.41k
      return false;
90
8.41k
    }
91
826
  }
92
826
93
826
  if (LocVT == MVT::i64 ||
94
826
      
LocVT == MVT::f64429
||
95
826
      
LocVT == MVT::v2i32384
||
96
826
      
LocVT == MVT::v2f32384
||
97
826
      
LocVT == MVT::v4i32384
||
98
826
      
LocVT == MVT::v4f32384
||
99
826
      
LocVT == MVT::v8i32384
||
100
826
      
LocVT == MVT::v8f32384
||
101
826
      
LocVT == MVT::v16i32384
||
102
826
      
LocVT == MVT::v16f32384
||
103
826
      
LocVT == MVT::v2i64384
||
104
826
      
LocVT == MVT::v2f64384
||
105
826
      
LocVT == MVT::v4i16384
||
106
826
      
LocVT == MVT::v4f16384
) {
107
442
    if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
108
419
        return false;
109
407
  }
110
407
111
407
  if (LocVT == MVT::i32 ||
112
407
      
LocVT == MVT::f32158
||
113
407
      
LocVT == MVT::v2i1665
||
114
407
      
LocVT == MVT::v2f1663
||
115
407
      
LocVT == MVT::i1661
||
116
407
      
LocVT == MVT::f1625
||
117
407
      
LocVT == MVT::i123
) {
118
384
    unsigned Offset2 = State.AllocateStack(4, 4);
119
384
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
120
384
    return false;
121
384
  }
122
23
123
23
  if (LocVT == MVT::i64 ||
124
23
      
LocVT == MVT::f6420
||
125
23
      
LocVT == MVT::v2i320
||
126
23
      
LocVT == MVT::v2f320
) {
127
23
    unsigned Offset3 = State.AllocateStack(8, 4);
128
23
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
129
23
    return false;
130
23
  }
131
0
132
0
  if (LocVT == MVT::v4i32 ||
133
0
      LocVT == MVT::v4f32 ||
134
0
      LocVT == MVT::v2i64 ||
135
0
      LocVT == MVT::v2f64) {
136
0
    unsigned Offset4 = State.AllocateStack(16, 4);
137
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
138
0
    return false;
139
0
  }
140
0
141
0
  if (LocVT == MVT::v8i32 ||
142
0
      LocVT == MVT::v8f32) {
143
0
    unsigned Offset5 = State.AllocateStack(32, 4);
144
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
145
0
    return false;
146
0
  }
147
0
148
0
  if (LocVT == MVT::v16i32 ||
149
0
      LocVT == MVT::v16f32) {
150
0
    unsigned Offset6 = State.AllocateStack(64, 4);
151
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
152
0
    return false;
153
0
  }
154
0
155
0
  return true;  // CC didn't match.
156
0
}
157
158
159
static bool CC_SI(unsigned ValNo, MVT ValVT,
160
                  MVT LocVT, CCValAssign::LocInfo LocInfo,
161
15.3k
                  ISD::ArgFlagsTy ArgFlags, CCState &State) {
162
15.3k
163
15.3k
  if (ArgFlags.isInReg()) {
164
10.4k
    if (LocVT == MVT::f32 ||
165
10.4k
        
LocVT == MVT::i3210.3k
||
166
10.4k
        
LocVT == MVT::f16308
||
167
10.4k
        
LocVT == MVT::v2i16307
||
168
10.4k
        
LocVT == MVT::v2f16306
) {
169
10.1k
      static const MCPhysReg RegList1[] = {
170
10.1k
        AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
171
10.1k
      };
172
10.1k
      if (unsigned Reg = State.AllocateReg(RegList1)) {
173
10.1k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
174
10.1k
        return false;
175
10.1k
      }
176
5.23k
    }
177
10.4k
  }
178
5.23k
179
5.23k
  if (ArgFlags.isInReg()) {
180
305
    if (LocVT == MVT::i64) {
181
305
      if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
182
305
            return false;
183
4.92k
    }
184
305
  }
185
4.92k
186
4.92k
  if (ArgFlags.isByVal()) {
187
150
    if (LocVT == MVT::i64) {
188
150
      if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
189
150
            return false;
190
4.77k
    }
191
150
  }
192
4.77k
193
4.77k
  if (!ArgFlags.isInReg()) {
194
4.77k
    if (LocVT == MVT::f32 ||
195
4.77k
        
LocVT == MVT::i322.16k
||
196
4.77k
        
LocVT == MVT::f16363
||
197
4.77k
        
LocVT == MVT::v2i16137
||
198
4.77k
        
LocVT == MVT::v2f165
) {
199
4.77k
      static const MCPhysReg RegList2[] = {
200
4.77k
        AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
201
4.77k
      };
202
4.77k
      if (unsigned Reg = State.AllocateReg(RegList2)) {
203
4.77k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
204
4.77k
        return false;
205
4.77k
      }
206
0
    }
207
4.77k
  }
208
0
209
0
  return true;  // CC didn't match.
210
0
}
211
212
213
static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
214
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
215
4.70k
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
216
4.70k
217
4.70k
  if (LocVT == MVT::i1) {
218
24
    LocVT = MVT::i32;
219
24
    if (ArgFlags.isSExt())
220
3
        LocInfo = CCValAssign::SExt;
221
21
    else if (ArgFlags.isZExt())
222
3
        LocInfo = CCValAssign::ZExt;
223
18
    else
224
18
        LocInfo = CCValAssign::AExt;
225
24
  }
226
4.70k
227
4.70k
  if (LocVT == MVT::i1 ||
228
4.70k
      LocVT == MVT::i16) {
229
176
    if (ArgFlags.isSExt() || 
ArgFlags.isZExt()172
) {
230
8
      LocVT = MVT::i32;
231
8
      if (ArgFlags.isSExt())
232
4
            LocInfo = CCValAssign::SExt;
233
4
      else if (ArgFlags.isZExt())
234
4
            LocInfo = CCValAssign::ZExt;
235
0
      else
236
0
            LocInfo = CCValAssign::AExt;
237
8
    }
238
176
  }
239
4.70k
240
4.70k
  if (LocVT == MVT::i32 ||
241
4.70k
      
LocVT == MVT::f322.29k
||
242
4.70k
      
LocVT == MVT::i161.12k
||
243
4.70k
      
LocVT == MVT::f16956
||
244
4.70k
      
LocVT == MVT::v2i16856
||
245
4.70k
      
LocVT == MVT::v2f16680
) {
246
4.45k
    static const MCPhysReg RegList1[] = {
247
4.45k
      AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
248
4.45k
    };
249
4.45k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
250
4.44k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
251
4.44k
      return false;
252
4.44k
    }
253
254
  }
254
254
255
254
  if (LocVT == MVT::i64 ||
256
254
      
LocVT == MVT::f6458
||
257
254
      
LocVT == MVT::v2i3212
||
258
254
      
LocVT == MVT::v2f3212
||
259
254
      
LocVT == MVT::v4i3212
||
260
254
      
LocVT == MVT::v4f3212
||
261
254
      
LocVT == MVT::v8i3212
||
262
254
      
LocVT == MVT::v8f3212
||
263
254
      
LocVT == MVT::v16i3212
||
264
254
      
LocVT == MVT::v16f3212
||
265
254
      
LocVT == MVT::v2i6412
||
266
254
      
LocVT == MVT::v2f6412
||
267
254
      
LocVT == MVT::v4i1612
||
268
254
      
LocVT == MVT::v4f1612
) {
269
242
    if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
270
242
        return false;
271
12
  }
272
12
273
12
  return true;  // CC didn't match.
274
12
}
275
276
277
static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
278
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
279
4.20k
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
280
4.20k
281
4.20k
  if (LocVT == MVT::i32) {
282
151
    static const MCPhysReg RegList1[] = {
283
151
      AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
284
151
    };
285
151
    if (unsigned Reg = State.AllocateReg(RegList1)) {
286
151
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
287
151
      return false;
288
151
    }
289
4.05k
  }
290
4.05k
291
4.05k
  if (LocVT == MVT::f32 ||
292
4.05k
      
LocVT == MVT::f16109
||
293
4.05k
      
LocVT == MVT::v2f1628
) {
294
4.05k
    static const MCPhysReg RegList2[] = {
295
4.05k
      AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
296
4.05k
    };
297
4.05k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
298
4.05k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
299
4.05k
      return false;
300
4.05k
    }
301
0
  }
302
0
303
0
  return true;  // CC didn't match.
304
0
}