Coverage Report

Created: 2019-03-24 22:13

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenCallingConv.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Calling Convention Implementation Fragment                                 *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
10
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
11
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
12
static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
13
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
14
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
15
static bool CC_SI(unsigned ValNo, MVT ValVT,
16
                  MVT LocVT, CCValAssign::LocInfo LocInfo,
17
                  ISD::ArgFlagsTy ArgFlags, CCState &State);
18
static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
19
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
20
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
21
static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
22
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
23
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
24
25
26
static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
27
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
28
18.0k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
29
18.0k
30
18.0k
  if (static_cast<const GCNSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
31
18.0k
    if (!CC_SI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
32
18.0k
      return false;
33
0
  }
34
0
35
0
  if (static_cast<const GCNSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C) {
36
0
    if (!CC_AMDGPU_Func(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
37
0
      return false;
38
0
  }
39
0
40
0
  return true;  // CC didn't match.
41
0
}
42
43
44
static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
45
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
46
10.3k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
47
10.3k
48
10.3k
  if (ArgFlags.isByVal()) {
49
129
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
50
129
    return false;
51
129
  }
52
10.2k
53
10.2k
  if (LocVT == MVT::i1) {
54
30
    LocVT = MVT::i32;
55
30
    if (ArgFlags.isSExt())
56
7
        LocInfo = CCValAssign::SExt;
57
23
    else if (ArgFlags.isZExt())
58
7
        LocInfo = CCValAssign::ZExt;
59
16
    else
60
16
        LocInfo = CCValAssign::AExt;
61
30
  }
62
10.2k
63
10.2k
  if (LocVT == MVT::i1 ||
64
10.2k
      LocVT == MVT::i8 ||
65
10.2k
      LocVT == MVT::i16) {
66
254
    if (ArgFlags.isSExt() || 
ArgFlags.isZExt()243
) {
67
26
      LocVT = MVT::i32;
68
26
      if (ArgFlags.isSExt())
69
11
            LocInfo = CCValAssign::SExt;
70
15
      else if (ArgFlags.isZExt())
71
15
            LocInfo = CCValAssign::ZExt;
72
0
      else
73
0
            LocInfo = CCValAssign::AExt;
74
26
    }
75
254
  }
76
10.2k
77
10.2k
  if (LocVT == MVT::i32 ||
78
10.2k
      
LocVT == MVT::f323.43k
||
79
10.2k
      
LocVT == MVT::i161.96k
||
80
10.2k
      
LocVT == MVT::f161.73k
||
81
10.2k
      
LocVT == MVT::v2i161.16k
||
82
10.2k
      
LocVT == MVT::v2f16992
||
83
10.2k
      
LocVT == MVT::i1516
) {
84
9.72k
    static const MCPhysReg RegList1[] = {
85
9.72k
      AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
86
9.72k
    };
87
9.72k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
88
9.24k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
89
9.24k
      return false;
90
9.24k
    }
91
996
  }
92
996
93
996
  if (LocVT == MVT::i64 ||
94
996
      
LocVT == MVT::f64533
||
95
996
      
LocVT == MVT::v2i32480
||
96
996
      
LocVT == MVT::v2f32480
||
97
996
      
LocVT == MVT::v3i32480
||
98
996
      
LocVT == MVT::v3f32480
||
99
996
      
LocVT == MVT::v4i32480
||
100
996
      
LocVT == MVT::v4f32480
||
101
996
      
LocVT == MVT::v5i32480
||
102
996
      
LocVT == MVT::v5f32480
||
103
996
      
LocVT == MVT::v8i32480
||
104
996
      
LocVT == MVT::v8f32480
||
105
996
      
LocVT == MVT::v16i32480
||
106
996
      
LocVT == MVT::v16f32480
||
107
996
      
LocVT == MVT::v2i64480
||
108
996
      
LocVT == MVT::v2f64480
||
109
996
      
LocVT == MVT::v4i16480
||
110
996
      
LocVT == MVT::v4f16480
) {
111
516
    if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
112
493
        return false;
113
503
  }
114
503
115
503
  if (LocVT == MVT::i32 ||
116
503
      
LocVT == MVT::f32206
||
117
503
      
LocVT == MVT::v2i1665
||
118
503
      
LocVT == MVT::v2f1663
||
119
503
      
LocVT == MVT::i1661
||
120
503
      
LocVT == MVT::f1625
||
121
503
      
LocVT == MVT::i123
) {
122
480
    unsigned Offset2 = State.AllocateStack(4, 4);
123
480
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
124
480
    return false;
125
480
  }
126
23
127
23
  if (LocVT == MVT::i64 ||
128
23
      
LocVT == MVT::f6420
||
129
23
      
LocVT == MVT::v2i320
||
130
23
      
LocVT == MVT::v2f320
) {
131
23
    unsigned Offset3 = State.AllocateStack(8, 4);
132
23
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
133
23
    return false;
134
23
  }
135
0
136
0
  if (LocVT == MVT::v3i32 ||
137
0
      LocVT == MVT::v3f32) {
138
0
    unsigned Offset4 = State.AllocateStack(12, 4);
139
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
140
0
    return false;
141
0
  }
142
0
143
0
  if (LocVT == MVT::v4i32 ||
144
0
      LocVT == MVT::v4f32 ||
145
0
      LocVT == MVT::v2i64 ||
146
0
      LocVT == MVT::v2f64) {
147
0
    unsigned Offset5 = State.AllocateStack(16, 4);
148
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
149
0
    return false;
150
0
  }
151
0
152
0
  if (LocVT == MVT::v5i32 ||
153
0
      LocVT == MVT::v5f32) {
154
0
    unsigned Offset6 = State.AllocateStack(20, 4);
155
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
156
0
    return false;
157
0
  }
158
0
159
0
  if (LocVT == MVT::v8i32 ||
160
0
      LocVT == MVT::v8f32) {
161
0
    unsigned Offset7 = State.AllocateStack(32, 4);
162
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
163
0
    return false;
164
0
  }
165
0
166
0
  if (LocVT == MVT::v16i32 ||
167
0
      LocVT == MVT::v16f32) {
168
0
    unsigned Offset8 = State.AllocateStack(64, 4);
169
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
170
0
    return false;
171
0
  }
172
0
173
0
  return true;  // CC didn't match.
174
0
}
175
176
177
static bool CC_SI(unsigned ValNo, MVT ValVT,
178
                  MVT LocVT, CCValAssign::LocInfo LocInfo,
179
18.0k
                  ISD::ArgFlagsTy ArgFlags, CCState &State) {
180
18.0k
181
18.0k
  if (ArgFlags.isInReg()) {
182
12.4k
    if (LocVT == MVT::f32 ||
183
12.4k
        
LocVT == MVT::i3212.3k
||
184
12.4k
        
LocVT == MVT::f16383
||
185
12.4k
        
LocVT == MVT::v2i16382
||
186
12.4k
        
LocVT == MVT::v2f16379
) {
187
12.1k
      static const MCPhysReg RegList1[] = {
188
12.1k
        AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
189
12.1k
      };
190
12.1k
      if (unsigned Reg = State.AllocateReg(RegList1)) {
191
12.1k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
192
12.1k
        return false;
193
12.1k
      }
194
5.93k
    }
195
12.4k
  }
196
5.93k
197
5.93k
  if (ArgFlags.isInReg()) {
198
376
    if (LocVT == MVT::i64) {
199
376
      if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
200
376
            return false;
201
5.56k
    }
202
376
  }
203
5.56k
204
5.56k
  if (ArgFlags.isByVal()) {
205
150
    if (LocVT == MVT::i64) {
206
150
      if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
207
150
            return false;
208
5.41k
    }
209
150
  }
210
5.41k
211
5.41k
  if (!ArgFlags.isInReg()) {
212
5.41k
    if (LocVT == MVT::f32 ||
213
5.41k
        
LocVT == MVT::i322.55k
||
214
5.41k
        
LocVT == MVT::f16375
||
215
5.41k
        
LocVT == MVT::v2i16137
||
216
5.41k
        
LocVT == MVT::v2f165
) {
217
5.41k
      static const MCPhysReg RegList2[] = {
218
5.41k
        AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
219
5.41k
      };
220
5.41k
      if (unsigned Reg = State.AllocateReg(RegList2)) {
221
5.41k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
222
5.41k
        return false;
223
5.41k
      }
224
0
    }
225
5.41k
  }
226
0
227
0
  return true;  // CC didn't match.
228
0
}
229
230
231
static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
232
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
233
4.91k
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
234
4.91k
235
4.91k
  if (LocVT == MVT::i1) {
236
24
    LocVT = MVT::i32;
237
24
    if (ArgFlags.isSExt())
238
3
        LocInfo = CCValAssign::SExt;
239
21
    else if (ArgFlags.isZExt())
240
3
        LocInfo = CCValAssign::ZExt;
241
18
    else
242
18
        LocInfo = CCValAssign::AExt;
243
24
  }
244
4.91k
245
4.91k
  if (LocVT == MVT::i1 ||
246
4.91k
      LocVT == MVT::i16) {
247
176
    if (ArgFlags.isSExt() || 
ArgFlags.isZExt()172
) {
248
8
      LocVT = MVT::i32;
249
8
      if (ArgFlags.isSExt())
250
4
            LocInfo = CCValAssign::SExt;
251
4
      else if (ArgFlags.isZExt())
252
4
            LocInfo = CCValAssign::ZExt;
253
0
      else
254
0
            LocInfo = CCValAssign::AExt;
255
8
    }
256
176
  }
257
4.91k
258
4.91k
  if (LocVT == MVT::i32 ||
259
4.91k
      
LocVT == MVT::f322.48k
||
260
4.91k
      
LocVT == MVT::i161.25k
||
261
4.91k
      
LocVT == MVT::f161.08k
||
262
4.91k
      
LocVT == MVT::v2i16982
||
263
4.91k
      
LocVT == MVT::v2f16750
) {
264
4.62k
    static const MCPhysReg RegList1[] = {
265
4.62k
      AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
266
4.62k
    };
267
4.62k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
268
4.61k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
269
4.61k
      return false;
270
4.61k
    }
271
304
  }
272
304
273
304
  if (LocVT == MVT::i64 ||
274
304
      
LocVT == MVT::f6474
||
275
304
      
LocVT == MVT::v2i3212
||
276
304
      
LocVT == MVT::v2f3212
||
277
304
      
LocVT == MVT::v4i3212
||
278
304
      
LocVT == MVT::v4f3212
||
279
304
      
LocVT == MVT::v8i3212
||
280
304
      
LocVT == MVT::v8f3212
||
281
304
      
LocVT == MVT::v16i3212
||
282
304
      
LocVT == MVT::v16f3212
||
283
304
      
LocVT == MVT::v2i6412
||
284
304
      
LocVT == MVT::v2f6412
||
285
304
      
LocVT == MVT::v4i1612
||
286
304
      
LocVT == MVT::v4f1612
) {
287
292
    if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
288
292
        return false;
289
12
  }
290
12
291
12
  return true;  // CC didn't match.
292
12
}
293
294
295
static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
296
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
297
4.82k
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
298
4.82k
299
4.82k
  if (LocVT == MVT::i32) {
300
157
    static const MCPhysReg RegList1[] = {
301
157
      AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
302
157
    };
303
157
    if (unsigned Reg = State.AllocateReg(RegList1)) {
304
157
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
305
157
      return false;
306
157
    }
307
4.66k
  }
308
4.66k
309
4.66k
  if (LocVT == MVT::f32 ||
310
4.66k
      
LocVT == MVT::f16133
||
311
4.66k
      
LocVT == MVT::v2f1628
) {
312
4.66k
    static const MCPhysReg RegList2[] = {
313
4.66k
      AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
314
4.66k
    };
315
4.66k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
316
4.66k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
317
4.66k
      return false;
318
4.66k
    }
319
0
  }
320
0
321
0
  return true;  // CC didn't match.
322
0
}