Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenCallingConv.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Calling Convention Implementation Fragment                                 *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
10
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
11
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
12
static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
13
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
14
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
15
static bool CC_SI(unsigned ValNo, MVT ValVT,
16
                  MVT LocVT, CCValAssign::LocInfo LocInfo,
17
                  ISD::ArgFlagsTy ArgFlags, CCState &State);
18
static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
19
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
20
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
21
static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
22
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
23
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
24
25
26
static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
27
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
28
10.2k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
29
10.2k
30
10.2k
  if (static_cast<const GCNSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
31
10.2k
    if (!CC_SI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
32
10.2k
      return false;
33
0
  }
34
0
35
0
  if (static_cast<const GCNSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C) {
36
0
    if (!CC_AMDGPU_Func(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
37
0
      return false;
38
0
  }
39
0
40
0
  return true;  // CC didn't match.
41
0
}
42
43
44
static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
45
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
46
5.15k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
47
5.15k
48
5.15k
  if (ArgFlags.isByVal()) {
49
98
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
50
98
    return false;
51
98
  }
52
5.05k
53
5.05k
  if (LocVT == MVT::i1) {
54
28
    LocVT = MVT::i32;
55
28
    if (ArgFlags.isSExt())
56
7
        LocInfo = CCValAssign::SExt;
57
21
    else if (ArgFlags.isZExt())
58
7
        LocInfo = CCValAssign::ZExt;
59
14
    else
60
14
        LocInfo = CCValAssign::AExt;
61
28
  }
62
5.05k
63
5.05k
  if (LocVT == MVT::i1 ||
64
5.05k
      LocVT == MVT::i8 ||
65
5.05k
      LocVT == MVT::i16) {
66
246
    if (ArgFlags.isSExt() || 
ArgFlags.isZExt()235
) {
67
26
      LocVT = MVT::i32;
68
26
      if (ArgFlags.isSExt())
69
11
            LocInfo = CCValAssign::SExt;
70
15
      else if (ArgFlags.isZExt())
71
15
            LocInfo = CCValAssign::ZExt;
72
0
      else
73
0
            LocInfo = CCValAssign::AExt;
74
26
    }
75
246
  }
76
5.05k
77
5.05k
  if (LocVT == MVT::i32 ||
78
5.05k
      
LocVT == MVT::f322.06k
||
79
5.05k
      
LocVT == MVT::i161.56k
||
80
5.05k
      
LocVT == MVT::f161.34k
||
81
5.05k
      
LocVT == MVT::v2i16885
||
82
5.05k
      
LocVT == MVT::v2f16872
||
83
5.05k
      
LocVT == MVT::i1765
) {
84
4.29k
    static const MCPhysReg RegList1[] = {
85
4.29k
      AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
86
4.29k
    };
87
4.29k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
88
4.11k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
89
4.11k
      return false;
90
4.11k
    }
91
945
  }
92
945
93
945
  if (LocVT == MVT::i64 ||
94
945
      
LocVT == MVT::f64603
||
95
945
      
LocVT == MVT::v2i32579
||
96
945
      
LocVT == MVT::v2f32562
||
97
945
      
LocVT == MVT::v4i32551
||
98
945
      
LocVT == MVT::v4f32534
||
99
945
      
LocVT == MVT::v8i32518
||
100
945
      
LocVT == MVT::v8f32505
||
101
945
      
LocVT == MVT::v16i32499
||
102
945
      
LocVT == MVT::v16f32413
||
103
945
      
LocVT == MVT::v2i64407
||
104
945
      
LocVT == MVT::v2f64358
||
105
945
      
LocVT == MVT::v4i16310
||
106
945
      
LocVT == MVT::v4f16250
) {
107
765
    if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
108
732
        return false;
109
213
  }
110
213
111
213
  if (LocVT == MVT::i32 ||
112
213
      
LocVT == MVT::f3278
||
113
213
      
LocVT == MVT::v2i1675
||
114
213
      
LocVT == MVT::v2f1673
||
115
213
      
LocVT == MVT::i1671
||
116
213
      
LocVT == MVT::f1635
||
117
213
      
LocVT == MVT::i133
) {
118
180
    unsigned Offset2 = State.AllocateStack(4, 4);
119
180
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
120
180
    return false;
121
180
  }
122
33
123
33
  if (LocVT == MVT::i64 ||
124
33
      
LocVT == MVT::f6430
||
125
33
      
LocVT == MVT::v2i3230
||
126
33
      
LocVT == MVT::v2f3227
) {
127
9
    unsigned Offset3 = State.AllocateStack(8, 4);
128
9
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
129
9
    return false;
130
9
  }
131
24
132
24
  if (LocVT == MVT::v4i32 ||
133
24
      
LocVT == MVT::v4f3221
||
134
24
      
LocVT == MVT::v2i6418
||
135
24
      
LocVT == MVT::v2f6415
) {
136
12
    unsigned Offset4 = State.AllocateStack(16, 4);
137
12
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
138
12
    return false;
139
12
  }
140
12
141
12
  if (LocVT == MVT::v8i32 ||
142
12
      
LocVT == MVT::v8f329
) {
143
6
    unsigned Offset5 = State.AllocateStack(32, 4);
144
6
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
145
6
    return false;
146
6
  }
147
6
148
6
  if (LocVT == MVT::v16i32 ||
149
6
      
LocVT == MVT::v16f323
) {
150
6
    unsigned Offset6 = State.AllocateStack(64, 4);
151
6
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
152
6
    return false;
153
6
  }
154
0
155
0
  return true;  // CC didn't match.
156
0
}
157
158
159
static bool CC_SI(unsigned ValNo, MVT ValVT,
160
                  MVT LocVT, CCValAssign::LocInfo LocInfo,
161
10.2k
                  ISD::ArgFlagsTy ArgFlags, CCState &State) {
162
10.2k
163
10.2k
  if (ArgFlags.isInReg()) {
164
6.98k
    if (LocVT == MVT::f32 ||
165
6.98k
        
LocVT == MVT::i326.92k
||
166
6.98k
        
LocVT == MVT::f16143
) {
167
6.84k
      static const MCPhysReg RegList1[] = {
168
6.84k
        AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
169
6.84k
      };
170
6.84k
      if (unsigned Reg = State.AllocateReg(RegList1)) {
171
6.84k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
172
6.84k
        return false;
173
6.84k
      }
174
3.40k
    }
175
6.98k
  }
176
3.40k
177
3.40k
  if (ArgFlags.isInReg()) {
178
142
    if (LocVT == MVT::i64) {
179
142
      if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
180
142
            return false;
181
3.25k
    }
182
142
  }
183
3.25k
184
3.25k
  if (ArgFlags.isByVal()) {
185
166
    if (LocVT == MVT::i64) {
186
117
      if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
187
117
            return false;
188
3.14k
    }
189
166
  }
190
3.14k
191
3.14k
  if (!ArgFlags.isInReg()) {
192
3.14k
    if (LocVT == MVT::f32 ||
193
3.14k
        
LocVT == MVT::i321.38k
||
194
3.14k
        
LocVT == MVT::f1624
) {
195
3.14k
      static const MCPhysReg RegList2[] = {
196
3.14k
        AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
197
3.14k
      };
198
3.14k
      if (unsigned Reg = State.AllocateReg(RegList2)) {
199
3.14k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
200
3.14k
        return false;
201
3.14k
      }
202
0
    }
203
3.14k
  }
204
0
205
0
  return true;  // CC didn't match.
206
0
}
207
208
209
static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
210
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
211
2.06k
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
212
2.06k
213
2.06k
  if (LocVT == MVT::i1) {
214
18
    LocVT = MVT::i32;
215
18
    if (ArgFlags.isSExt())
216
3
        LocInfo = CCValAssign::SExt;
217
15
    else if (ArgFlags.isZExt())
218
3
        LocInfo = CCValAssign::ZExt;
219
12
    else
220
12
        LocInfo = CCValAssign::AExt;
221
18
  }
222
2.06k
223
2.06k
  if (LocVT == MVT::i1 ||
224
2.06k
      LocVT == MVT::i16) {
225
196
    if (ArgFlags.isSExt() || 
ArgFlags.isZExt()192
) {
226
8
      LocVT = MVT::i32;
227
8
      if (ArgFlags.isSExt())
228
4
            LocInfo = CCValAssign::SExt;
229
4
      else if (ArgFlags.isZExt())
230
4
            LocInfo = CCValAssign::ZExt;
231
0
      else
232
0
            LocInfo = CCValAssign::AExt;
233
8
    }
234
196
  }
235
2.06k
236
2.06k
  if (LocVT == MVT::i32 ||
237
2.06k
      
LocVT == MVT::f321.44k
||
238
2.06k
      
LocVT == MVT::i16898
||
239
2.06k
      
LocVT == MVT::f16710
||
240
2.06k
      
LocVT == MVT::v2i16666
||
241
2.06k
      
LocVT == MVT::v2f16592
) {
242
1.53k
    static const MCPhysReg RegList1[] = {
243
1.53k
      AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
244
1.53k
    };
245
1.53k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
246
1.52k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
247
1.52k
      return false;
248
1.52k
    }
249
541
  }
250
541
251
541
  if (LocVT == MVT::i64 ||
252
541
      
LocVT == MVT::f64379
||
253
541
      
LocVT == MVT::v2i32351
||
254
541
      
LocVT == MVT::v2f32335
||
255
541
      
LocVT == MVT::v4i32295
||
256
541
      
LocVT == MVT::v4f32271
||
257
541
      
LocVT == MVT::v8i32265
||
258
541
      
LocVT == MVT::v8f32241
||
259
541
      
LocVT == MVT::v16i32241
||
260
541
      
LocVT == MVT::v16f32187
||
261
541
      
LocVT == MVT::v2i64187
||
262
541
      
LocVT == MVT::v2f6497
||
263
541
      
LocVT == MVT::v4i1685
||
264
541
      
LocVT == MVT::v4f1641
) {
265
532
    if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
266
529
        return false;
267
12
  }
268
12
269
12
  return true;  // CC didn't match.
270
12
}
271
272
273
static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
274
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
275
2.65k
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
276
2.65k
277
2.65k
  if (LocVT == MVT::i32) {
278
151
    static const MCPhysReg RegList1[] = {
279
151
      AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
280
151
    };
281
151
    if (unsigned Reg = State.AllocateReg(RegList1)) {
282
151
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
283
151
      return false;
284
151
    }
285
2.50k
  }
286
2.50k
287
2.50k
  if (LocVT == MVT::f32 ||
288
2.50k
      
LocVT == MVT::f1643
) {
289
2.50k
    static const MCPhysReg RegList2[] = {
290
2.50k
      AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
291
2.50k
    };
292
2.50k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
293
2.50k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
294
2.50k
      return false;
295
2.50k
    }
296
0
  }
297
0
298
0
  return true;  // CC didn't match.
299
0
}