Coverage Report

Created: 2018-07-20 23:04

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the AMDGPU target                          *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 32;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(AMDGPUInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(AMDGPUInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static AMDGPUInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static AMDGPUInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(3),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_isSICIBit = 15,
37
  Feature_isVIBit = 5,
38
  Feature_isGFX9Bit = 4,
39
  Feature_isCIVIBit = 6,
40
  Feature_HasFlatAddressSpaceBit = 7,
41
  Feature_HasFlatGlobalInstsBit = 8,
42
  Feature_HasUnpackedD16VMemBit = 19,
43
  Feature_HasPackedD16VMemBit = 20,
44
  Feature_D16PreservesUnusedBitsBit = 18,
45
  Feature_LDSRequiresM0InitBit = 30,
46
  Feature_NotLDSRequiresM0InitBit = 31,
47
  Feature_Has16BitInstsBit = 2,
48
  Feature_HasVOP3PInstsBit = 22,
49
  Feature_HasMadMixInstsBit = 13,
50
  Feature_has16BankLDSBit = 11,
51
  Feature_has32BankLDSBit = 10,
52
  Feature_HasFmaMixInstsBit = 14,
53
  Feature_HasDLInstsBit = 29,
54
  Feature_EnableLateCFGStructurizeBit = 12,
55
  Feature_TruePredicateBit = 0,
56
  Feature_FP16DenormalsBit = 24,
57
  Feature_FP32DenormalsBit = 26,
58
  Feature_FP64DenormalsBit = 28,
59
  Feature_NoFP16DenormalsBit = 23,
60
  Feature_NoFP32DenormalsBit = 25,
61
  Feature_NoFP64DenormalsBit = 27,
62
  Feature_UnsafeFPMathBit = 21,
63
  Feature_isCIBit = 17,
64
  Feature_isCIOnlyBit = 16,
65
  Feature_isVIOnlyBit = 3,
66
  Feature_isGCNBit = 1,
67
  Feature_isSIBit = 9,
68
};
69
70
PredicateBitset AMDGPUInstructionSelector::
71
2.28k
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const {
72
2.28k
  PredicateBitset Features;
73
2.28k
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||
Subtarget->getGeneration() == 1.33k
AMDGPUSubtarget1.33k
::SEA_ISLANDS)
74
1.17k
    Features[Feature_isSICIBit] = 1;
75
2.28k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
76
1.11k
    Features[Feature_isVIBit] = 1;
77
2.28k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9)
78
275
    Features[Feature_isGFX9Bit] = 1;
79
2.28k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
80
1.33k
    Features[Feature_isCIVIBit] = 1;
81
2.28k
  if (Subtarget->hasFlatAddressSpace())
82
1.47k
    Features[Feature_HasFlatAddressSpaceBit] = 1;
83
2.28k
  if (Subtarget->hasFlatGlobalInsts())
84
275
    Features[Feature_HasFlatGlobalInstsBit] = 1;
85
2.28k
  if (Subtarget->hasUnpackedD16VMem())
86
823
    Features[Feature_HasUnpackedD16VMemBit] = 1;
87
2.28k
  if (!Subtarget->hasUnpackedD16VMem())
88
1.45k
    Features[Feature_HasPackedD16VMemBit] = 1;
89
2.28k
  if (Subtarget->d16PreservesUnusedBits())
90
254
    Features[Feature_D16PreservesUnusedBitsBit] = 1;
91
2.28k
  if (Subtarget->ldsRequiresM0Init())
92
2.00k
    Features[Feature_LDSRequiresM0InitBit] = 1;
93
2.28k
  if (!Subtarget->ldsRequiresM0Init())
94
275
    Features[Feature_NotLDSRequiresM0InitBit] = 1;
95
2.28k
  if (Subtarget->has16BitInsts())
96
1.11k
    Features[Feature_Has16BitInstsBit] = 1;
97
2.28k
  if (Subtarget->hasVOP3PInsts())
98
275
    Features[Feature_HasVOP3PInstsBit] = 1;
99
2.28k
  if (Subtarget->hasMadMixInsts())
100
252
    Features[Feature_HasMadMixInstsBit] = 1;
101
2.28k
  if (Subtarget->getLDSBankCount() == 16)
102
19
    Features[Feature_has16BankLDSBit] = 1;
103
2.28k
  if (Subtarget->getLDSBankCount() == 32)
104
2.26k
    Features[Feature_has32BankLDSBit] = 1;
105
2.28k
  if (Subtarget->hasFmaMixInsts())
106
23
    Features[Feature_HasFmaMixInstsBit] = 1;
107
2.28k
  if (Subtarget->hasDLInsts())
108
21
    Features[Feature_HasDLInstsBit] = 1;
109
2.28k
  if (EnableLateStructurizeCFG)
110
0
    Features[Feature_EnableLateCFGStructurizeBit] = 1;
111
2.28k
  if (true)
112
2.28k
    Features[Feature_TruePredicateBit] = 1;
113
2.28k
  if (Subtarget->hasFP16Denormals())
114
2.24k
    Features[Feature_FP16DenormalsBit] = 1;
115
2.28k
  if (Subtarget->hasFP32Denormals())
116
56
    Features[Feature_FP32DenormalsBit] = 1;
117
2.28k
  if (Subtarget->hasFP64Denormals())
118
2.24k
    Features[Feature_FP64DenormalsBit] = 1;
119
2.28k
  if (!Subtarget->hasFP16Denormals())
120
35
    Features[Feature_NoFP16DenormalsBit] = 1;
121
2.28k
  if (!Subtarget->hasFP32Denormals())
122
2.22k
    Features[Feature_NoFP32DenormalsBit] = 1;
123
2.28k
  if (!Subtarget->hasFP64Denormals())
124
35
    Features[Feature_NoFP64DenormalsBit] = 1;
125
2.28k
  if (TM.Options.UnsafeFPMath)
126
39
    Features[Feature_UnsafeFPMathBit] = 1;
127
2.28k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
128
1.33k
    Features[Feature_isCIBit] = 1;
129
2.28k
  if (Subtarget->getGeneration() ==AMDGPUSubtarget::SEA_ISLANDS)
130
221
    Features[Feature_isCIOnlyBit] = 1;
131
2.28k
  if (Subtarget->getGeneration() ==AMDGPUSubtarget::VOLCANIC_ISLANDS)
132
837
    Features[Feature_isVIOnlyBit] = 1;
133
2.28k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
134
2.28k
    Features[Feature_isGCNBit] = 1;
135
2.28k
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
136
949
    Features[Feature_isSIBit] = 1;
137
2.28k
  return Features;
138
2.28k
}
139
140
PredicateBitset AMDGPUInstructionSelector::
141
53
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget, const MachineFunction *MF) const {
142
53
  PredicateBitset Features;
143
53
  return Features;
144
53
}
145
146
// LLT Objects.
147
enum {
148
  GILLT_s1,
149
  GILLT_s16,
150
  GILLT_s32,
151
  GILLT_s64,
152
  GILLT_v2s16,
153
  GILLT_v2s32,
154
  GILLT_v2s64,
155
  GILLT_v4s16,
156
  GILLT_v4s32,
157
  GILLT_v8s32,
158
  GILLT_v16s32,
159
};
160
const static size_t NumTypeObjects = 11;
161
const static LLT TypeObjects[] = {
162
  LLT::scalar(1),
163
  LLT::scalar(16),
164
  LLT::scalar(32),
165
  LLT::scalar(64),
166
  LLT::vector(2, 16),
167
  LLT::vector(2, 32),
168
  LLT::vector(2, 64),
169
  LLT::vector(4, 16),
170
  LLT::vector(4, 32),
171
  LLT::vector(8, 32),
172
  LLT::vector(16, 32),
173
};
174
175
// Feature bitsets.
176
enum {
177
  GIFBS_Invalid,
178
  GIFBS_Has16BitInsts,
179
  GIFBS_TruePredicate_isCIVI,
180
  GIFBS_TruePredicate_isGCN,
181
  GIFBS_TruePredicate_isSI,
182
  GIFBS_TruePredicate_isSICI,
183
  GIFBS_TruePredicate_isVI,
184
};
185
const static PredicateBitset FeatureBitsets[] {
186
  {}, // GIFBS_Invalid
187
  {Feature_Has16BitInstsBit, },
188
  {Feature_TruePredicateBit, Feature_isCIVIBit, },
189
  {Feature_TruePredicateBit, Feature_isGCNBit, },
190
  {Feature_TruePredicateBit, Feature_isSIBit, },
191
  {Feature_TruePredicateBit, Feature_isSICIBit, },
192
  {Feature_TruePredicateBit, Feature_isVIBit, },
193
};
194
195
// ComplexPattern predicates.
196
enum {
197
  GICP_Invalid,
198
  GICP_gi_vcsrc,
199
  GICP_gi_vop3mods,
200
  GICP_gi_vop3mods0,
201
  GICP_gi_vop3omods,
202
  GICP_gi_vsrc0,
203
};
204
// See constructor for table contents
205
206
// PatFrag predicates.
207
enum {
208
  GIPFP_I64_Predicate_NegSubInlineConst16 = GIPFP_I64_Invalid + 1,
209
  GIPFP_I64_Predicate_NegSubInlineConst32,
210
};
211
0
bool AMDGPUInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
212
0
  switch (PredicateID) {
213
0
  case GIPFP_I64_Predicate_NegSubInlineConst16: {
214
0
    
215
0
  return Imm < -16 && Imm >= -64;
216
0
217
0
    llvm_unreachable("ImmediateCode should have returned");
218
0
    return false;
219
0
  }
220
0
  case GIPFP_I64_Predicate_NegSubInlineConst32: {
221
0
    
222
0
  return Imm < -16 && Imm >= -64;
223
0
224
0
    llvm_unreachable("ImmediateCode should have returned");
225
0
    return false;
226
0
  }
227
0
  }
228
0
  llvm_unreachable("Unknown predicate");
229
0
  return false;
230
0
}
231
0
bool AMDGPUInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
232
0
  llvm_unreachable("Unknown predicate");
233
0
  return false;
234
0
}
235
0
bool AMDGPUInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
236
0
  llvm_unreachable("Unknown predicate");
237
0
  return false;
238
0
}
239
0
bool AMDGPUInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
240
0
  const MachineFunction &MF = *MI.getParent()->getParent();
241
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
242
0
  (void)MRI;
243
0
  llvm_unreachable("Unknown predicate");
244
0
  return false;
245
0
}
246
247
AMDGPUInstructionSelector::ComplexMatcherMemFn
248
AMDGPUInstructionSelector::ComplexPredicateFns[] = {
249
  nullptr, // GICP_Invalid
250
  &AMDGPUInstructionSelector::selectVCSRC, // gi_vcsrc
251
  &AMDGPUInstructionSelector::selectVOP3Mods, // gi_vop3mods
252
  &AMDGPUInstructionSelector::selectVOP3Mods0, // gi_vop3mods0
253
  &AMDGPUInstructionSelector::selectVOP3OMods, // gi_vop3omods
254
  &AMDGPUInstructionSelector::selectVSRC0, // gi_vsrc0
255
};
256
257
// Custom renderers.
258
enum {
259
  GICR_Invalid,
260
};
261
AMDGPUInstructionSelector::CustomRendererFn
262
AMDGPUInstructionSelector::CustomRenderers[] = {
263
  nullptr, // GICP_Invalid
264
};
265
266
53
bool AMDGPUInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
267
53
  MachineFunction &MF = *I.getParent()->getParent();
268
53
  MachineRegisterInfo &MRI = MF.getRegInfo();
269
53
  // FIXME: This should be computed on a per-function basis rather than per-insn.
270
53
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
271
53
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
272
53
  NewMIVector OutMIs;
273
53
  State.MIs.clear();
274
53
  State.MIs.push_back(&I);
275
53
276
53
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
277
53
    return true;
278
53
  }
279
0
280
0
  return false;
281
0
}
282
283
53
const int64_t *AMDGPUInstructionSelector::getMatchTable() const {
284
53
  constexpr static int64_t MatchTable0[] = {
285
53
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 120, /*)*//*default:*//*Label 29*/ 10319,
286
53
    /*TargetOpcode::G_ADD*//*Label 0*/ 91,
287
53
    /*TargetOpcode::G_SUB*//*Label 1*/ 323,
288
53
    /*TargetOpcode::G_MUL*//*Label 2*/ 394, 0, 0, 0, 0,
289
53
    /*TargetOpcode::G_AND*//*Label 3*/ 422,
290
53
    /*TargetOpcode::G_OR*//*Label 4*/ 485,
291
53
    /*TargetOpcode::G_XOR*//*Label 5*/ 2331, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
292
53
    /*TargetOpcode::G_BITCAST*//*Label 6*/ 2448, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
293
53
    /*TargetOpcode::G_INTRINSIC*//*Label 7*/ 4590,
294
53
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 8*/ 7070, 0, 0,
295
53
    /*TargetOpcode::G_CONSTANT*//*Label 9*/ 7369, 0, 0, 0,
296
53
    /*TargetOpcode::G_SEXT*//*Label 10*/ 7426,
297
53
    /*TargetOpcode::G_ZEXT*//*Label 11*/ 7572,
298
53
    /*TargetOpcode::G_SHL*//*Label 12*/ 7718,
299
53
    /*TargetOpcode::G_LSHR*//*Label 13*/ 7781,
300
53
    /*TargetOpcode::G_ASHR*//*Label 14*/ 7844, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
301
53
    /*TargetOpcode::G_FADD*//*Label 15*/ 8048,
302
53
    /*TargetOpcode::G_FSUB*//*Label 16*/ 8394,
303
53
    /*TargetOpcode::G_FMUL*//*Label 17*/ 8525,
304
53
    /*TargetOpcode::G_FMA*//*Label 18*/ 8871, 0, 0,
305
53
    /*TargetOpcode::G_FPOW*//*Label 19*/ 9115, 0,
306
53
    /*TargetOpcode::G_FEXP2*//*Label 20*/ 9188, 0,
307
53
    /*TargetOpcode::G_FLOG2*//*Label 21*/ 9285, 0,
308
53
    /*TargetOpcode::G_FPEXT*//*Label 22*/ 9382,
309
53
    /*TargetOpcode::G_FPTRUNC*//*Label 23*/ 9479,
310
53
    /*TargetOpcode::G_FPTOSI*//*Label 24*/ 9576,
311
53
    /*TargetOpcode::G_FPTOUI*//*Label 25*/ 9810,
312
53
    /*TargetOpcode::G_SITOFP*//*Label 26*/ 10044,
313
53
    /*TargetOpcode::G_UITOFP*//*Label 27*/ 10174, 0, 0, 0,
314
53
    /*TargetOpcode::G_BR*//*Label 28*/ 10304,
315
53
    // Label 0: @91
316
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 33*/ 322,
317
53
    /*GILLT_s16*//*Label 30*/ 100,
318
53
    /*GILLT_s32*//*Label 31*/ 260,
319
53
    /*GILLT_s64*//*Label 32*/ 295,
320
53
    // Label 30: @100
321
53
    GIM_Try, /*On fail goto*//*Label 34*/ 259,
322
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
323
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
324
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
325
53
      GIM_Try, /*On fail goto*//*Label 35*/ 162, // Rule ID 886 //
326
53
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
327
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
328
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
329
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
330
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
331
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
332
53
        // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
333
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
334
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
335
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
336
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
337
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
338
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
339
53
        GIR_EraseFromParent, /*InsnID*/0,
340
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
341
53
        // GIR_Coverage, 886,
342
53
        GIR_Done,
343
53
      // Label 35: @162
344
53
      GIM_Try, /*On fail goto*//*Label 36*/ 210, // Rule ID 889 //
345
53
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
346
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
347
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
348
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
349
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
350
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
351
53
        // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_I16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
352
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_I16,
353
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
354
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
355
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
356
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
357
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
358
53
        GIR_EraseFromParent, /*InsnID*/0,
359
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
360
53
        // GIR_Coverage, 889,
361
53
        GIR_Done,
362
53
      // Label 36: @210
363
53
      GIM_Try, /*On fail goto*//*Label 37*/ 258, // Rule ID 1836 //
364
53
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
365
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
366
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
367
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
368
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
369
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
370
53
        // (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
371
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
372
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
373
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
374
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
375
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
376
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
377
53
        GIR_EraseFromParent, /*InsnID*/0,
378
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
379
53
        // GIR_Coverage, 1836,
380
53
        GIR_Done,
381
53
      // Label 37: @258
382
53
      GIM_Reject,
383
53
    // Label 34: @259
384
53
    GIM_Reject,
385
53
    // Label 31: @260
386
53
    GIM_Try, /*On fail goto*//*Label 38*/ 294, // Rule ID 440 //
387
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
388
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
389
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
390
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
391
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
392
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
393
53
      // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)  =>  (S_ADD_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
394
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ADD_I32,
395
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
396
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
397
53
      // GIR_Coverage, 440,
398
53
      GIR_Done,
399
53
    // Label 38: @294
400
53
    GIM_Reject,
401
53
    // Label 32: @295
402
53
    GIM_Try, /*On fail goto*//*Label 39*/ 321, // Rule ID 633 //
403
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
404
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
405
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
406
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
407
53
      // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_ADD_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
408
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ADD_U64_PSEUDO,
409
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
410
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
411
53
      // GIR_Coverage, 633,
412
53
      GIR_Done,
413
53
    // Label 39: @321
414
53
    GIM_Reject,
415
53
    // Label 33: @322
416
53
    GIM_Reject,
417
53
    // Label 1: @323
418
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 42*/ 393,
419
53
    /*GILLT_s32*//*Label 40*/ 331,
420
53
    /*GILLT_s64*//*Label 41*/ 366,
421
53
    // Label 40: @331
422
53
    GIM_Try, /*On fail goto*//*Label 43*/ 365, // Rule ID 441 //
423
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
424
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
425
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
426
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
427
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
428
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
429
53
      // (sub:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)  =>  (S_SUB_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
430
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_SUB_I32,
431
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
432
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
433
53
      // GIR_Coverage, 441,
434
53
      GIR_Done,
435
53
    // Label 43: @365
436
53
    GIM_Reject,
437
53
    // Label 41: @366
438
53
    GIM_Try, /*On fail goto*//*Label 44*/ 392, // Rule ID 634 //
439
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
440
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
441
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
442
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
443
53
      // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_SUB_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
444
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_SUB_U64_PSEUDO,
445
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
446
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
447
53
      // GIR_Coverage, 634,
448
53
      GIR_Done,
449
53
    // Label 44: @392
450
53
    GIM_Reject,
451
53
    // Label 42: @393
452
53
    GIM_Reject,
453
53
    // Label 2: @394
454
53
    GIM_Try, /*On fail goto*//*Label 45*/ 421, // Rule ID 463 //
455
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
456
53
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
457
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
458
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
459
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
460
53
      // (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_MUL_I32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
461
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_MUL_I32,
462
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
463
53
      // GIR_Coverage, 463,
464
53
      GIR_Done,
465
53
    // Label 45: @421
466
53
    GIM_Reject,
467
53
    // Label 3: @422
468
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 48*/ 484,
469
53
    /*GILLT_s32*//*Label 46*/ 430,
470
53
    /*GILLT_s64*//*Label 47*/ 457,
471
53
    // Label 46: @430
472
53
    GIM_Try, /*On fail goto*//*Label 49*/ 456, // Rule ID 448 //
473
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
474
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
475
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
476
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
477
53
      // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_AND_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
478
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_AND_B32,
479
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
480
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
481
53
      // GIR_Coverage, 448,
482
53
      GIR_Done,
483
53
    // Label 49: @456
484
53
    GIM_Reject,
485
53
    // Label 47: @457
486
53
    GIM_Try, /*On fail goto*//*Label 50*/ 483, // Rule ID 449 //
487
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
488
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
489
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
490
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
491
53
      // (and:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_AND_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
492
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_AND_B64,
493
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
494
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
495
53
      // GIR_Coverage, 449,
496
53
      GIR_Done,
497
53
    // Label 50: @483
498
53
    GIM_Reject,
499
53
    // Label 48: @484
500
53
    GIM_Reject,
501
53
    // Label 4: @485
502
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 53*/ 2330,
503
53
    /*GILLT_s32*//*Label 51*/ 493,
504
53
    /*GILLT_s64*//*Label 52*/ 2303,
505
53
    // Label 51: @493
506
53
    GIM_Try, /*On fail goto*//*Label 54*/ 2302,
507
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
508
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
509
53
      GIM_Try, /*On fail goto*//*Label 55*/ 608, // Rule ID 1814 //
510
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
511
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
512
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
513
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
514
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
515
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
516
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
517
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
518
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
519
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
520
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
521
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
522
53
        // MIs[3] x
523
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
524
53
        // MIs[3] z
525
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
526
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
527
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
528
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
529
53
        // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
530
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
531
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
532
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
533
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
534
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
535
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
536
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
537
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
538
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
539
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
540
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
541
53
        GIR_EraseFromParent, /*InsnID*/0,
542
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
543
53
        // GIR_Coverage, 1814,
544
53
        GIR_Done,
545
53
      // Label 55: @608
546
53
      GIM_Try, /*On fail goto*//*Label 56*/ 713, // Rule ID 1815 //
547
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
548
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
549
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
550
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
551
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
552
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
553
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
554
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
555
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
556
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
557
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
558
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
559
53
        // MIs[3] z
560
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
561
53
        // MIs[3] x
562
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
563
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
564
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
565
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
566
53
        // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
567
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
568
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
569
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
570
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
571
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
572
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
573
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
574
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
575
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
576
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
577
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
578
53
        GIR_EraseFromParent, /*InsnID*/0,
579
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
580
53
        // GIR_Coverage, 1815,
581
53
        GIR_Done,
582
53
      // Label 56: @713
583
53
      GIM_Try, /*On fail goto*//*Label 57*/ 818, // Rule ID 1816 //
584
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
585
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
586
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
587
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
588
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
589
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
590
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
591
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
592
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
593
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
594
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
595
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
596
53
        // MIs[3] x
597
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
598
53
        // MIs[3] z
599
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
600
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
601
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
602
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
603
53
        // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
604
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
605
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
606
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
607
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
608
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
609
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
610
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
611
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
612
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
613
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
614
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
615
53
        GIR_EraseFromParent, /*InsnID*/0,
616
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
617
53
        // GIR_Coverage, 1816,
618
53
        GIR_Done,
619
53
      // Label 57: @818
620
53
      GIM_Try, /*On fail goto*//*Label 58*/ 923, // Rule ID 1817 //
621
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
622
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
623
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
624
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
625
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
626
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
627
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
628
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
629
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
630
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
631
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
632
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
633
53
        // MIs[3] z
634
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
635
53
        // MIs[3] x
636
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
637
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
638
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
639
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
640
53
        // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
641
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
642
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
643
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
644
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
645
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
646
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
647
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
648
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
649
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
650
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
651
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
652
53
        GIR_EraseFromParent, /*InsnID*/0,
653
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
654
53
        // GIR_Coverage, 1817,
655
53
        GIR_Done,
656
53
      // Label 58: @923
657
53
      GIM_Try, /*On fail goto*//*Label 59*/ 1028, // Rule ID 1810 //
658
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
659
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
660
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
661
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
662
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
663
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
664
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
665
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
666
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
667
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
668
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
669
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
670
53
        // MIs[3] x
671
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
672
53
        // MIs[3] z
673
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
674
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
675
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
676
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
677
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
678
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
679
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
680
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
681
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
682
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
683
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
684
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
685
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
686
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
687
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
688
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
689
53
        GIR_EraseFromParent, /*InsnID*/0,
690
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
691
53
        // GIR_Coverage, 1810,
692
53
        GIR_Done,
693
53
      // Label 59: @1028
694
53
      GIM_Try, /*On fail goto*//*Label 60*/ 1133, // Rule ID 1811 //
695
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
696
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
697
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
698
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
699
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
700
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
701
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
702
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
703
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
704
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
705
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
706
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
707
53
        // MIs[3] z
708
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
709
53
        // MIs[3] x
710
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
711
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
712
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
713
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
714
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
715
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
716
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
717
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
718
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
719
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
720
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
721
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
722
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
723
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
724
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
725
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
726
53
        GIR_EraseFromParent, /*InsnID*/0,
727
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
728
53
        // GIR_Coverage, 1811,
729
53
        GIR_Done,
730
53
      // Label 60: @1133
731
53
      GIM_Try, /*On fail goto*//*Label 61*/ 1238, // Rule ID 1812 //
732
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
733
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
734
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
735
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
736
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
737
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
738
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
739
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
740
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
741
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
742
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
743
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
744
53
        // MIs[3] x
745
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
746
53
        // MIs[3] z
747
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
748
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
749
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
750
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
751
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
752
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
753
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
754
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
755
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
756
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
757
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
758
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
759
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
760
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
761
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
762
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
763
53
        GIR_EraseFromParent, /*InsnID*/0,
764
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
765
53
        // GIR_Coverage, 1812,
766
53
        GIR_Done,
767
53
      // Label 61: @1238
768
53
      GIM_Try, /*On fail goto*//*Label 62*/ 1343, // Rule ID 1813 //
769
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
770
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
771
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
772
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
773
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
774
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
775
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
776
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
777
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
778
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
779
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
780
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
781
53
        // MIs[3] z
782
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
783
53
        // MIs[3] x
784
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
785
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
786
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
787
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
788
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
789
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
790
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
791
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
792
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
793
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
794
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
795
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
796
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
797
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
798
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
799
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
800
53
        GIR_EraseFromParent, /*InsnID*/0,
801
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
802
53
        // GIR_Coverage, 1813,
803
53
        GIR_Done,
804
53
      // Label 62: @1343
805
53
      GIM_Try, /*On fail goto*//*Label 63*/ 1448, // Rule ID 1804 //
806
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
807
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
808
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
809
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
810
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
811
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
812
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
813
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
814
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
815
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
816
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
817
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
818
53
        // MIs[3] x
819
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
820
53
        // MIs[3] z
821
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
822
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
823
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
824
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
825
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
826
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
827
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
828
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
829
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
830
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
831
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
832
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
833
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
834
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
835
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
836
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
837
53
        GIR_EraseFromParent, /*InsnID*/0,
838
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
839
53
        // GIR_Coverage, 1804,
840
53
        GIR_Done,
841
53
      // Label 63: @1448
842
53
      GIM_Try, /*On fail goto*//*Label 64*/ 1553, // Rule ID 1805 //
843
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
844
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
845
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
846
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
847
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
848
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
849
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
850
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
851
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
852
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
853
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
854
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
855
53
        // MIs[3] z
856
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
857
53
        // MIs[3] x
858
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
859
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
860
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
861
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
862
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
863
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
864
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
865
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
866
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
867
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
868
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
869
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
870
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
871
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
872
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
873
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
874
53
        GIR_EraseFromParent, /*InsnID*/0,
875
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
876
53
        // GIR_Coverage, 1805,
877
53
        GIR_Done,
878
53
      // Label 64: @1553
879
53
      GIM_Try, /*On fail goto*//*Label 65*/ 1658, // Rule ID 1808 //
880
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
881
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
882
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
883
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
884
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
885
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
886
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
887
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
888
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
889
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
890
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
891
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
892
53
        // MIs[3] x
893
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
894
53
        // MIs[3] z
895
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
896
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
897
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
898
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
899
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
900
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
901
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
902
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
903
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
904
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
905
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
906
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
907
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
908
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
909
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
910
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
911
53
        GIR_EraseFromParent, /*InsnID*/0,
912
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
913
53
        // GIR_Coverage, 1808,
914
53
        GIR_Done,
915
53
      // Label 65: @1658
916
53
      GIM_Try, /*On fail goto*//*Label 66*/ 1763, // Rule ID 1809 //
917
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
918
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
919
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
920
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
921
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
922
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
923
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
924
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
925
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
926
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
927
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
928
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
929
53
        // MIs[3] z
930
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
931
53
        // MIs[3] x
932
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
933
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
934
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
935
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
936
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
937
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
938
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
939
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
940
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
941
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
942
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
943
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
944
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
945
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
946
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
947
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
948
53
        GIR_EraseFromParent, /*InsnID*/0,
949
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
950
53
        // GIR_Coverage, 1809,
951
53
        GIR_Done,
952
53
      // Label 66: @1763
953
53
      GIM_Try, /*On fail goto*//*Label 67*/ 1868, // Rule ID 787 //
954
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
955
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
956
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
957
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
958
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
959
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
960
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
961
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
962
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
963
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
964
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
965
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
966
53
        // MIs[3] x
967
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
968
53
        // MIs[3] z
969
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
970
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
971
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
972
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
973
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
974
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
975
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
976
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
977
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
978
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
979
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
980
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
981
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
982
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
983
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
984
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
985
53
        GIR_EraseFromParent, /*InsnID*/0,
986
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
987
53
        // GIR_Coverage, 787,
988
53
        GIR_Done,
989
53
      // Label 67: @1868
990
53
      GIM_Try, /*On fail goto*//*Label 68*/ 1973, // Rule ID 1803 //
991
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
992
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
993
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
994
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
995
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
996
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
997
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
998
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
999
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1000
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1001
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1002
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
1003
53
        // MIs[3] z
1004
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
1005
53
        // MIs[3] x
1006
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
1007
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1008
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1009
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1010
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
1011
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
1012
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1013
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1014
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
1015
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
1016
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1017
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1018
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1019
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1020
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
1021
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
1022
53
        GIR_EraseFromParent, /*InsnID*/0,
1023
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1024
53
        // GIR_Coverage, 1803,
1025
53
        GIR_Done,
1026
53
      // Label 68: @1973
1027
53
      GIM_Try, /*On fail goto*//*Label 69*/ 2078, // Rule ID 1806 //
1028
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1029
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1030
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1031
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1032
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1033
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1034
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1035
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
1036
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1037
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1038
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1039
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
1040
53
        // MIs[3] x
1041
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
1042
53
        // MIs[3] z
1043
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
1044
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1045
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1046
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1047
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
1048
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
1049
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1050
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1051
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
1052
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
1053
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1054
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1055
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1056
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1057
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
1058
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
1059
53
        GIR_EraseFromParent, /*InsnID*/0,
1060
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1061
53
        // GIR_Coverage, 1806,
1062
53
        GIR_Done,
1063
53
      // Label 69: @2078
1064
53
      GIM_Try, /*On fail goto*//*Label 70*/ 2183, // Rule ID 1807 //
1065
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1066
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1067
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1068
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1069
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1070
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1071
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1072
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
1073
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1074
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1075
53
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1076
53
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
1077
53
        // MIs[3] z
1078
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
1079
53
        // MIs[3] x
1080
53
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
1081
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1082
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1083
53
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1084
53
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
1085
53
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
1086
53
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1087
53
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1088
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
1089
53
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
1090
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1091
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1092
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1093
53
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1094
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
1095
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
1096
53
        GIR_EraseFromParent, /*InsnID*/0,
1097
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1098
53
        // GIR_Coverage, 1807,
1099
53
        GIR_Done,
1100
53
      // Label 70: @2183
1101
53
      GIM_Try, /*On fail goto*//*Label 71*/ 2220, // Rule ID 1740 //
1102
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1103
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1104
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
1105
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vsrc0,
1106
53
        // (or:{ *:[i32] } (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0), VGPR_32:{ *:[i32] }:$src1)  =>  (V_OR_B32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1107
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
1108
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1109
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
1110
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1111
53
        GIR_EraseFromParent, /*InsnID*/0,
1112
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1113
53
        // GIR_Coverage, 1740,
1114
53
        GIR_Done,
1115
53
      // Label 71: @2220
1116
53
      GIM_Try, /*On fail goto*//*Label 72*/ 2257, // Rule ID 1945 //
1117
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1118
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1119
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1120
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
1121
53
        // (or:{ *:[i32] } VGPR_32:{ *:[i32] }:$src1, (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_OR_B32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1122
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
1123
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1124
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
1125
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1126
53
        GIR_EraseFromParent, /*InsnID*/0,
1127
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1128
53
        // GIR_Coverage, 1945,
1129
53
        GIR_Done,
1130
53
      // Label 72: @2257
1131
53
      GIM_Try, /*On fail goto*//*Label 73*/ 2283, // Rule ID 1739 //
1132
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1133
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1134
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1135
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
1136
53
        // (or:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)  =>  (S_OR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1137
53
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
1138
53
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
1139
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1140
53
        // GIR_Coverage, 1739,
1141
53
        GIR_Done,
1142
53
      // Label 73: @2283
1143
53
      GIM_Try, /*On fail goto*//*Label 74*/ 2301, // Rule ID 450 //
1144
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1145
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1146
53
        // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_OR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1147
53
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
1148
53
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
1149
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1150
53
        // GIR_Coverage, 450,
1151
53
        GIR_Done,
1152
53
      // Label 74: @2301
1153
53
      GIM_Reject,
1154
53
    // Label 54: @2302
1155
53
    GIM_Reject,
1156
53
    // Label 52: @2303
1157
53
    GIM_Try, /*On fail goto*//*Label 75*/ 2329, // Rule ID 451 //
1158
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1159
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1160
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1161
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
1162
53
      // (or:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_OR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
1163
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_OR_B64,
1164
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
1165
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1166
53
      // GIR_Coverage, 451,
1167
53
      GIR_Done,
1168
53
    // Label 75: @2329
1169
53
    GIM_Reject,
1170
53
    // Label 53: @2330
1171
53
    GIM_Reject,
1172
53
    // Label 5: @2331
1173
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 78*/ 2447,
1174
53
    /*GILLT_s32*//*Label 76*/ 2339,
1175
53
    /*GILLT_s64*//*Label 77*/ 2393,
1176
53
    // Label 76: @2339
1177
53
    GIM_Try, /*On fail goto*//*Label 79*/ 2392,
1178
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1179
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1180
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1181
53
      GIM_Try, /*On fail goto*//*Label 80*/ 2377, // Rule ID 428 //
1182
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1183
53
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1184
53
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })  =>  (S_NOT_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
1185
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B32,
1186
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
1187
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1188
53
        GIR_EraseFromParent, /*InsnID*/0,
1189
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1190
53
        // GIR_Coverage, 428,
1191
53
        GIR_Done,
1192
53
      // Label 80: @2377
1193
53
      GIM_Try, /*On fail goto*//*Label 81*/ 2391, // Rule ID 452 //
1194
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1195
53
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_XOR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1196
53
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_XOR_B32,
1197
53
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
1198
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1199
53
        // GIR_Coverage, 452,
1200
53
        GIR_Done,
1201
53
      // Label 81: @2391
1202
53
      GIM_Reject,
1203
53
    // Label 79: @2392
1204
53
    GIM_Reject,
1205
53
    // Label 77: @2393
1206
53
    GIM_Try, /*On fail goto*//*Label 82*/ 2446,
1207
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1208
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1209
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
1210
53
      GIM_Try, /*On fail goto*//*Label 83*/ 2431, // Rule ID 429 //
1211
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1212
53
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1213
53
        // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, -1:{ *:[i64] })  =>  (S_NOT_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0)
1214
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B64,
1215
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
1216
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1217
53
        GIR_EraseFromParent, /*InsnID*/0,
1218
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1219
53
        // GIR_Coverage, 429,
1220
53
        GIR_Done,
1221
53
      // Label 83: @2431
1222
53
      GIM_Try, /*On fail goto*//*Label 84*/ 2445, // Rule ID 453 //
1223
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1224
53
        // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_XOR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
1225
53
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_XOR_B64,
1226
53
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
1227
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1228
53
        // GIR_Coverage, 453,
1229
53
        GIR_Done,
1230
53
      // Label 84: @2445
1231
53
      GIM_Reject,
1232
53
    // Label 82: @2446
1233
53
    GIM_Reject,
1234
53
    // Label 78: @2447
1235
53
    GIM_Reject,
1236
53
    // Label 6: @2448
1237
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 95*/ 4589,
1238
53
    /*GILLT_s16*//*Label 85*/ 2464,
1239
53
    /*GILLT_s32*//*Label 86*/ 2592,
1240
53
    /*GILLT_s64*//*Label 87*/ 2865,
1241
53
    /*GILLT_v2s16*//*Label 88*/ 3206,
1242
53
    /*GILLT_v2s32*//*Label 89*/ 3411,
1243
53
    /*GILLT_v2s64*//*Label 90*/ 3786,
1244
53
    /*GILLT_v4s16*//*Label 91*/ 3957,
1245
53
    /*GILLT_v4s32*//*Label 92*/ 4230,
1246
53
    /*GILLT_v8s32*//*Label 93*/ 4401,
1247
53
    /*GILLT_v16s32*//*Label 94*/ 4529,
1248
53
    // Label 85: @2464
1249
53
    GIM_Try, /*On fail goto*//*Label 96*/ 2591,
1250
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
1251
53
      GIM_Try, /*On fail goto*//*Label 97*/ 2500, // Rule ID 1435 //
1252
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1253
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1254
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1255
53
        // (bitconvert:{ *:[i16] } VGPR_32:{ *:[f16] }:$src0)  =>  VGPR_32:{ *:[i16] }:$src0
1256
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1257
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1258
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1259
53
        GIR_EraseFromParent, /*InsnID*/0,
1260
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1261
53
        // GIR_Coverage, 1435,
1262
53
        GIR_Done,
1263
53
      // Label 97: @2500
1264
53
      GIM_Try, /*On fail goto*//*Label 98*/ 2530, // Rule ID 1436 //
1265
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1266
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1267
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1268
53
        // (bitconvert:{ *:[f16] } VGPR_32:{ *:[i16] }:$src0)  =>  VGPR_32:{ *:[f16] }:$src0
1269
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1270
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1271
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1272
53
        GIR_EraseFromParent, /*InsnID*/0,
1273
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1274
53
        // GIR_Coverage, 1436,
1275
53
        GIR_Done,
1276
53
      // Label 98: @2530
1277
53
      GIM_Try, /*On fail goto*//*Label 99*/ 2560, // Rule ID 1437 //
1278
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1279
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1280
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1281
53
        // (bitconvert:{ *:[i16] } SReg_32:{ *:[f16] }:$src0)  =>  SReg_32:{ *:[i16] }:$src0
1282
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1283
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1284
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1285
53
        GIR_EraseFromParent, /*InsnID*/0,
1286
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1287
53
        // GIR_Coverage, 1437,
1288
53
        GIR_Done,
1289
53
      // Label 99: @2560
1290
53
      GIM_Try, /*On fail goto*//*Label 100*/ 2590, // Rule ID 1438 //
1291
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1292
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1293
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1294
53
        // (bitconvert:{ *:[f16] } SReg_32:{ *:[i16] }:$src0)  =>  SReg_32:{ *:[f16] }:$src0
1295
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1296
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1297
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1298
53
        GIR_EraseFromParent, /*InsnID*/0,
1299
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1300
53
        // GIR_Coverage, 1438,
1301
53
        GIR_Done,
1302
53
      // Label 100: @2590
1303
53
      GIM_Reject,
1304
53
    // Label 96: @2591
1305
53
    GIM_Reject,
1306
53
    // Label 86: @2592
1307
53
    GIM_Try, /*On fail goto*//*Label 101*/ 2626, // Rule ID 1439 //
1308
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1309
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1310
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1311
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1312
53
      // (bitconvert:{ *:[i32] } VGPR_32:{ *:[f32] }:$src0)  =>  VGPR_32:{ *:[i32] }:$src0
1313
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1314
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1315
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1316
53
      GIR_EraseFromParent, /*InsnID*/0,
1317
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1318
53
      // GIR_Coverage, 1439,
1319
53
      GIR_Done,
1320
53
    // Label 101: @2626
1321
53
    GIM_Try, /*On fail goto*//*Label 102*/ 2660, // Rule ID 1440 //
1322
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1323
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1324
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1325
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1326
53
      // (bitconvert:{ *:[f32] } VGPR_32:{ *:[i32] }:$src0)  =>  VGPR_32:{ *:[f32] }:$src0
1327
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1328
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1329
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1330
53
      GIR_EraseFromParent, /*InsnID*/0,
1331
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1332
53
      // GIR_Coverage, 1440,
1333
53
      GIR_Done,
1334
53
    // Label 102: @2660
1335
53
    GIM_Try, /*On fail goto*//*Label 103*/ 2694, // Rule ID 1441 //
1336
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1337
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1338
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1339
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1340
53
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1341
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1342
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1343
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1344
53
      GIR_EraseFromParent, /*InsnID*/0,
1345
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1346
53
      // GIR_Coverage, 1441,
1347
53
      GIR_Done,
1348
53
    // Label 103: @2694
1349
53
    GIM_Try, /*On fail goto*//*Label 104*/ 2728, // Rule ID 1442 //
1350
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1351
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1352
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1353
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1354
53
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1355
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1356
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1357
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1358
53
      GIR_EraseFromParent, /*InsnID*/0,
1359
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1360
53
      // GIR_Coverage, 1442,
1361
53
      GIR_Done,
1362
53
    // Label 104: @2728
1363
53
    GIM_Try, /*On fail goto*//*Label 105*/ 2762, // Rule ID 1444 //
1364
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1365
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1366
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1367
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1368
53
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1369
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1370
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1371
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1372
53
      GIR_EraseFromParent, /*InsnID*/0,
1373
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1374
53
      // GIR_Coverage, 1444,
1375
53
      GIR_Done,
1376
53
    // Label 105: @2762
1377
53
    GIM_Try, /*On fail goto*//*Label 106*/ 2796, // Rule ID 1446 //
1378
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1379
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1380
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1381
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1382
53
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1383
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1384
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1385
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1386
53
      GIR_EraseFromParent, /*InsnID*/0,
1387
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1388
53
      // GIR_Coverage, 1446,
1389
53
      GIR_Done,
1390
53
    // Label 106: @2796
1391
53
    GIM_Try, /*On fail goto*//*Label 107*/ 2830, // Rule ID 1450 //
1392
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1393
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1394
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1395
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1396
53
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1397
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1398
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1399
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1400
53
      GIR_EraseFromParent, /*InsnID*/0,
1401
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1402
53
      // GIR_Coverage, 1450,
1403
53
      GIR_Done,
1404
53
    // Label 107: @2830
1405
53
    GIM_Try, /*On fail goto*//*Label 108*/ 2864, // Rule ID 1452 //
1406
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1407
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1408
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1409
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1410
53
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1411
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1412
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1413
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1414
53
      GIR_EraseFromParent, /*InsnID*/0,
1415
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1416
53
      // GIR_Coverage, 1452,
1417
53
      GIR_Done,
1418
53
    // Label 108: @2864
1419
53
    GIM_Reject,
1420
53
    // Label 87: @2865
1421
53
    GIM_Try, /*On fail goto*//*Label 109*/ 2899, // Rule ID 1453 //
1422
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1423
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1424
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1425
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1426
53
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1427
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1428
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1429
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1430
53
      GIR_EraseFromParent, /*InsnID*/0,
1431
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1432
53
      // GIR_Coverage, 1453,
1433
53
      GIR_Done,
1434
53
    // Label 109: @2899
1435
53
    GIM_Try, /*On fail goto*//*Label 110*/ 2933, // Rule ID 1454 //
1436
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1437
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1438
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1439
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1440
53
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1441
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1442
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1443
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1444
53
      GIR_EraseFromParent, /*InsnID*/0,
1445
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1446
53
      // GIR_Coverage, 1454,
1447
53
      GIR_Done,
1448
53
    // Label 110: @2933
1449
53
    GIM_Try, /*On fail goto*//*Label 111*/ 2967, // Rule ID 1457 //
1450
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1451
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1452
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1453
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1454
53
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1455
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1456
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1457
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1458
53
      GIR_EraseFromParent, /*InsnID*/0,
1459
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1460
53
      // GIR_Coverage, 1457,
1461
53
      GIR_Done,
1462
53
    // Label 111: @2967
1463
53
    GIM_Try, /*On fail goto*//*Label 112*/ 3001, // Rule ID 1459 //
1464
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1465
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1466
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1467
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1468
53
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1469
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1470
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1471
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1472
53
      GIR_EraseFromParent, /*InsnID*/0,
1473
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1474
53
      // GIR_Coverage, 1459,
1475
53
      GIR_Done,
1476
53
    // Label 112: @3001
1477
53
    GIM_Try, /*On fail goto*//*Label 113*/ 3035, // Rule ID 1461 //
1478
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1479
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1480
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1481
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1482
53
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1483
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1484
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1485
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1486
53
      GIR_EraseFromParent, /*InsnID*/0,
1487
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1488
53
      // GIR_Coverage, 1461,
1489
53
      GIR_Done,
1490
53
    // Label 113: @3035
1491
53
    GIM_Try, /*On fail goto*//*Label 114*/ 3069, // Rule ID 1463 //
1492
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1493
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1494
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1495
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1496
53
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1497
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1498
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1499
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1500
53
      GIR_EraseFromParent, /*InsnID*/0,
1501
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1502
53
      // GIR_Coverage, 1463,
1503
53
      GIR_Done,
1504
53
    // Label 114: @3069
1505
53
    GIM_Try, /*On fail goto*//*Label 115*/ 3103, // Rule ID 1476 //
1506
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1507
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1508
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1509
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1510
53
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1511
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1512
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1513
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1514
53
      GIR_EraseFromParent, /*InsnID*/0,
1515
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1516
53
      // GIR_Coverage, 1476,
1517
53
      GIR_Done,
1518
53
    // Label 115: @3103
1519
53
    GIM_Try, /*On fail goto*//*Label 116*/ 3137, // Rule ID 1477 //
1520
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1521
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1522
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1523
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1524
53
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1525
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1526
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1527
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1528
53
      GIR_EraseFromParent, /*InsnID*/0,
1529
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1530
53
      // GIR_Coverage, 1477,
1531
53
      GIR_Done,
1532
53
    // Label 116: @3137
1533
53
    GIM_Try, /*On fail goto*//*Label 117*/ 3171, // Rule ID 1480 //
1534
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1535
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1536
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1537
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1538
53
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1539
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1540
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1541
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1542
53
      GIR_EraseFromParent, /*InsnID*/0,
1543
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1544
53
      // GIR_Coverage, 1480,
1545
53
      GIR_Done,
1546
53
    // Label 117: @3171
1547
53
    GIM_Try, /*On fail goto*//*Label 118*/ 3205, // Rule ID 1481 //
1548
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1549
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1550
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1551
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1552
53
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1553
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1554
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1555
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1556
53
      GIR_EraseFromParent, /*InsnID*/0,
1557
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1558
53
      // GIR_Coverage, 1481,
1559
53
      GIR_Done,
1560
53
    // Label 118: @3205
1561
53
    GIM_Reject,
1562
53
    // Label 88: @3206
1563
53
    GIM_Try, /*On fail goto*//*Label 119*/ 3240, // Rule ID 1443 //
1564
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1565
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1566
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1567
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1568
53
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1569
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1570
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1571
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1572
53
      GIR_EraseFromParent, /*InsnID*/0,
1573
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1574
53
      // GIR_Coverage, 1443,
1575
53
      GIR_Done,
1576
53
    // Label 119: @3240
1577
53
    GIM_Try, /*On fail goto*//*Label 120*/ 3274, // Rule ID 1445 //
1578
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1579
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1580
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1581
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1582
53
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1583
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1584
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1585
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1586
53
      GIR_EraseFromParent, /*InsnID*/0,
1587
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1588
53
      // GIR_Coverage, 1445,
1589
53
      GIR_Done,
1590
53
    // Label 120: @3274
1591
53
    GIM_Try, /*On fail goto*//*Label 121*/ 3308, // Rule ID 1447 //
1592
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1593
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1594
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1595
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1596
53
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1597
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1598
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1599
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1600
53
      GIR_EraseFromParent, /*InsnID*/0,
1601
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1602
53
      // GIR_Coverage, 1447,
1603
53
      GIR_Done,
1604
53
    // Label 121: @3308
1605
53
    GIM_Try, /*On fail goto*//*Label 122*/ 3342, // Rule ID 1448 //
1606
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1607
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1608
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1609
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1610
53
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1611
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1612
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1613
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1614
53
      GIR_EraseFromParent, /*InsnID*/0,
1615
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1616
53
      // GIR_Coverage, 1448,
1617
53
      GIR_Done,
1618
53
    // Label 122: @3342
1619
53
    GIM_Try, /*On fail goto*//*Label 123*/ 3376, // Rule ID 1449 //
1620
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1621
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1622
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1623
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1624
53
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1625
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1626
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1627
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1628
53
      GIR_EraseFromParent, /*InsnID*/0,
1629
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1630
53
      // GIR_Coverage, 1449,
1631
53
      GIR_Done,
1632
53
    // Label 123: @3376
1633
53
    GIM_Try, /*On fail goto*//*Label 124*/ 3410, // Rule ID 1451 //
1634
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1635
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1636
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1637
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1638
53
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1639
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1640
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1641
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1642
53
      GIR_EraseFromParent, /*InsnID*/0,
1643
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1644
53
      // GIR_Coverage, 1451,
1645
53
      GIR_Done,
1646
53
    // Label 124: @3410
1647
53
    GIM_Reject,
1648
53
    // Label 89: @3411
1649
53
    GIM_Try, /*On fail goto*//*Label 125*/ 3445, // Rule ID 1455 //
1650
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1651
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1652
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1653
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1654
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1655
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1656
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1657
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1658
53
      GIR_EraseFromParent, /*InsnID*/0,
1659
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1660
53
      // GIR_Coverage, 1455,
1661
53
      GIR_Done,
1662
53
    // Label 125: @3445
1663
53
    GIM_Try, /*On fail goto*//*Label 126*/ 3479, // Rule ID 1456 //
1664
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1665
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1666
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1667
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1668
53
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1669
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1670
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1671
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1672
53
      GIR_EraseFromParent, /*InsnID*/0,
1673
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1674
53
      // GIR_Coverage, 1456,
1675
53
      GIR_Done,
1676
53
    // Label 126: @3479
1677
53
    GIM_Try, /*On fail goto*//*Label 127*/ 3513, // Rule ID 1458 //
1678
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1679
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1680
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1681
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1682
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1683
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1684
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1685
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1686
53
      GIR_EraseFromParent, /*InsnID*/0,
1687
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1688
53
      // GIR_Coverage, 1458,
1689
53
      GIR_Done,
1690
53
    // Label 127: @3513
1691
53
    GIM_Try, /*On fail goto*//*Label 128*/ 3547, // Rule ID 1460 //
1692
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1693
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1694
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1695
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1696
53
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1697
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1698
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1699
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1700
53
      GIR_EraseFromParent, /*InsnID*/0,
1701
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1702
53
      // GIR_Coverage, 1460,
1703
53
      GIR_Done,
1704
53
    // Label 128: @3547
1705
53
    GIM_Try, /*On fail goto*//*Label 129*/ 3581, // Rule ID 1462 //
1706
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1707
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1708
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1709
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1710
53
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1711
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1712
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1713
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1714
53
      GIR_EraseFromParent, /*InsnID*/0,
1715
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1716
53
      // GIR_Coverage, 1462,
1717
53
      GIR_Done,
1718
53
    // Label 129: @3581
1719
53
    GIM_Try, /*On fail goto*//*Label 130*/ 3615, // Rule ID 1464 //
1720
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1721
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1722
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1723
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1724
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1725
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1726
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1727
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1728
53
      GIR_EraseFromParent, /*InsnID*/0,
1729
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1730
53
      // GIR_Coverage, 1464,
1731
53
      GIR_Done,
1732
53
    // Label 130: @3615
1733
53
    GIM_Try, /*On fail goto*//*Label 131*/ 3649, // Rule ID 1465 //
1734
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1735
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1736
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1737
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1738
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1739
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1740
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1741
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1742
53
      GIR_EraseFromParent, /*InsnID*/0,
1743
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1744
53
      // GIR_Coverage, 1465,
1745
53
      GIR_Done,
1746
53
    // Label 131: @3649
1747
53
    GIM_Try, /*On fail goto*//*Label 132*/ 3683, // Rule ID 1467 //
1748
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1749
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1750
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1751
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1752
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1753
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1754
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1755
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1756
53
      GIR_EraseFromParent, /*InsnID*/0,
1757
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1758
53
      // GIR_Coverage, 1467,
1759
53
      GIR_Done,
1760
53
    // Label 132: @3683
1761
53
    GIM_Try, /*On fail goto*//*Label 133*/ 3717, // Rule ID 1468 //
1762
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1763
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1764
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1765
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1766
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1767
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1768
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1769
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1770
53
      GIR_EraseFromParent, /*InsnID*/0,
1771
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1772
53
      // GIR_Coverage, 1468,
1773
53
      GIR_Done,
1774
53
    // Label 133: @3717
1775
53
    GIM_Try, /*On fail goto*//*Label 134*/ 3751, // Rule ID 1470 //
1776
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1777
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1778
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1779
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1780
53
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1781
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1782
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1783
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1784
53
      GIR_EraseFromParent, /*InsnID*/0,
1785
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1786
53
      // GIR_Coverage, 1470,
1787
53
      GIR_Done,
1788
53
    // Label 134: @3751
1789
53
    GIM_Try, /*On fail goto*//*Label 135*/ 3785, // Rule ID 1472 //
1790
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1791
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1792
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1793
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1794
53
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1795
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1796
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1797
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1798
53
      GIR_EraseFromParent, /*InsnID*/0,
1799
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1800
53
      // GIR_Coverage, 1472,
1801
53
      GIR_Done,
1802
53
    // Label 135: @3785
1803
53
    GIM_Reject,
1804
53
    // Label 90: @3786
1805
53
    GIM_Try, /*On fail goto*//*Label 136*/ 3820, // Rule ID 1484 //
1806
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1807
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1808
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_128RegClassID,
1809
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_128RegClassID,
1810
53
      // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
1811
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1812
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1813
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1814
53
      GIR_EraseFromParent, /*InsnID*/0,
1815
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_128*/21,
1816
53
      // GIR_Coverage, 1484,
1817
53
      GIR_Done,
1818
53
    // Label 136: @3820
1819
53
    GIM_Try, /*On fail goto*//*Label 137*/ 3854, // Rule ID 1486 //
1820
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1821
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1822
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1823
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1824
53
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1825
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1826
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1827
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1828
53
      GIR_EraseFromParent, /*InsnID*/0,
1829
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1830
53
      // GIR_Coverage, 1486,
1831
53
      GIR_Done,
1832
53
    // Label 137: @3854
1833
53
    GIM_Try, /*On fail goto*//*Label 138*/ 3888, // Rule ID 1487 //
1834
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1835
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1836
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1837
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1838
53
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1839
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1840
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1841
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1842
53
      GIR_EraseFromParent, /*InsnID*/0,
1843
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1844
53
      // GIR_Coverage, 1487,
1845
53
      GIR_Done,
1846
53
    // Label 138: @3888
1847
53
    GIM_Try, /*On fail goto*//*Label 139*/ 3922, // Rule ID 1490 //
1848
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1849
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1850
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1851
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1852
53
      // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
1853
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1854
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1855
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1856
53
      GIR_EraseFromParent, /*InsnID*/0,
1857
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1858
53
      // GIR_Coverage, 1490,
1859
53
      GIR_Done,
1860
53
    // Label 139: @3922
1861
53
    GIM_Try, /*On fail goto*//*Label 140*/ 3956, // Rule ID 1491 //
1862
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1863
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1864
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1865
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1866
53
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1867
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1868
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1869
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1870
53
      GIR_EraseFromParent, /*InsnID*/0,
1871
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1872
53
      // GIR_Coverage, 1491,
1873
53
      GIR_Done,
1874
53
    // Label 140: @3956
1875
53
    GIM_Reject,
1876
53
    // Label 91: @3957
1877
53
    GIM_Try, /*On fail goto*//*Label 141*/ 3991, // Rule ID 1466 //
1878
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1879
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1880
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1881
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1882
53
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1883
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1884
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1885
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1886
53
      GIR_EraseFromParent, /*InsnID*/0,
1887
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1888
53
      // GIR_Coverage, 1466,
1889
53
      GIR_Done,
1890
53
    // Label 141: @3991
1891
53
    GIM_Try, /*On fail goto*//*Label 142*/ 4025, // Rule ID 1469 //
1892
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1893
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1894
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1895
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1896
53
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1897
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1898
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1899
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1900
53
      GIR_EraseFromParent, /*InsnID*/0,
1901
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1902
53
      // GIR_Coverage, 1469,
1903
53
      GIR_Done,
1904
53
    // Label 142: @4025
1905
53
    GIM_Try, /*On fail goto*//*Label 143*/ 4059, // Rule ID 1471 //
1906
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1907
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1908
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1909
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1910
53
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1911
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1912
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1913
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1914
53
      GIR_EraseFromParent, /*InsnID*/0,
1915
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1916
53
      // GIR_Coverage, 1471,
1917
53
      GIR_Done,
1918
53
    // Label 143: @4059
1919
53
    GIM_Try, /*On fail goto*//*Label 144*/ 4093, // Rule ID 1473 //
1920
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1921
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1922
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1923
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1924
53
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1925
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1926
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1927
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1928
53
      GIR_EraseFromParent, /*InsnID*/0,
1929
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1930
53
      // GIR_Coverage, 1473,
1931
53
      GIR_Done,
1932
53
    // Label 144: @4093
1933
53
    GIM_Try, /*On fail goto*//*Label 145*/ 4127, // Rule ID 1474 //
1934
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1935
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1936
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1937
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1938
53
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1939
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1940
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1941
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1942
53
      GIR_EraseFromParent, /*InsnID*/0,
1943
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1944
53
      // GIR_Coverage, 1474,
1945
53
      GIR_Done,
1946
53
    // Label 145: @4127
1947
53
    GIM_Try, /*On fail goto*//*Label 146*/ 4161, // Rule ID 1475 //
1948
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1949
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1950
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1951
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1952
53
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1953
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1954
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1955
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1956
53
      GIR_EraseFromParent, /*InsnID*/0,
1957
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1958
53
      // GIR_Coverage, 1475,
1959
53
      GIR_Done,
1960
53
    // Label 146: @4161
1961
53
    GIM_Try, /*On fail goto*//*Label 147*/ 4195, // Rule ID 1478 //
1962
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1963
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1964
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1965
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1966
53
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1967
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1968
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1969
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1970
53
      GIR_EraseFromParent, /*InsnID*/0,
1971
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1972
53
      // GIR_Coverage, 1478,
1973
53
      GIR_Done,
1974
53
    // Label 147: @4195
1975
53
    GIM_Try, /*On fail goto*//*Label 148*/ 4229, // Rule ID 1479 //
1976
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1977
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1978
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1979
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1980
53
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1981
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1982
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1983
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1984
53
      GIR_EraseFromParent, /*InsnID*/0,
1985
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1986
53
      // GIR_Coverage, 1479,
1987
53
      GIR_Done,
1988
53
    // Label 148: @4229
1989
53
    GIM_Reject,
1990
53
    // Label 92: @4230
1991
53
    GIM_Try, /*On fail goto*//*Label 149*/ 4264, // Rule ID 1482 //
1992
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1993
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1994
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1995
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1996
53
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
1997
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1998
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1999
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2000
53
      GIR_EraseFromParent, /*InsnID*/0,
2001
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
2002
53
      // GIR_Coverage, 1482,
2003
53
      GIR_Done,
2004
53
    // Label 149: @4264
2005
53
    GIM_Try, /*On fail goto*//*Label 150*/ 4298, // Rule ID 1483 //
2006
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2007
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2008
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
2009
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
2010
53
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
2011
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2012
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2013
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2014
53
      GIR_EraseFromParent, /*InsnID*/0,
2015
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
2016
53
      // GIR_Coverage, 1483,
2017
53
      GIR_Done,
2018
53
    // Label 150: @4298
2019
53
    GIM_Try, /*On fail goto*//*Label 151*/ 4332, // Rule ID 1485 //
2020
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2021
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2022
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_128RegClassID,
2023
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_128RegClassID,
2024
53
      // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
2025
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2026
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2027
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2028
53
      GIR_EraseFromParent, /*InsnID*/0,
2029
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_128*/21,
2030
53
      // GIR_Coverage, 1485,
2031
53
      GIR_Done,
2032
53
    // Label 151: @4332
2033
53
    GIM_Try, /*On fail goto*//*Label 152*/ 4366, // Rule ID 1488 //
2034
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2035
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2036
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
2037
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
2038
53
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
2039
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2040
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2041
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2042
53
      GIR_EraseFromParent, /*InsnID*/0,
2043
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
2044
53
      // GIR_Coverage, 1488,
2045
53
      GIR_Done,
2046
53
    // Label 152: @4366
2047
53
    GIM_Try, /*On fail goto*//*Label 153*/ 4400, // Rule ID 1489 //
2048
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2049
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2050
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
2051
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
2052
53
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
2053
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2054
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2055
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2056
53
      GIR_EraseFromParent, /*InsnID*/0,
2057
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
2058
53
      // GIR_Coverage, 1489,
2059
53
      GIR_Done,
2060
53
    // Label 153: @4400
2061
53
    GIM_Reject,
2062
53
    // Label 93: @4401
2063
53
    GIM_Try, /*On fail goto*//*Label 154*/ 4528,
2064
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
2065
53
      GIM_Try, /*On fail goto*//*Label 155*/ 4437, // Rule ID 1492 //
2066
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2067
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_256RegClassID,
2068
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_256RegClassID,
2069
53
        // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v8f32] }:$src0)  =>  SReg_256:{ *:[v8i32] }:$src0
2070
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2071
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2072
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2073
53
        GIR_EraseFromParent, /*InsnID*/0,
2074
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_256*/26,
2075
53
        // GIR_Coverage, 1492,
2076
53
        GIR_Done,
2077
53
      // Label 155: @4437
2078
53
      GIM_Try, /*On fail goto*//*Label 156*/ 4467, // Rule ID 1493 //
2079
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2080
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_256RegClassID,
2081
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_256RegClassID,
2082
53
        // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v8i32] }:$src0)  =>  SReg_256:{ *:[v8f32] }:$src0
2083
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2084
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2085
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2086
53
        GIR_EraseFromParent, /*InsnID*/0,
2087
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_256*/26,
2088
53
        // GIR_Coverage, 1493,
2089
53
        GIR_Done,
2090
53
      // Label 156: @4467
2091
53
      GIM_Try, /*On fail goto*//*Label 157*/ 4497, // Rule ID 1494 //
2092
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2093
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_256RegClassID,
2094
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_256RegClassID,
2095
53
        // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
2096
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2097
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2098
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2099
53
        GIR_EraseFromParent, /*InsnID*/0,
2100
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_256*/25,
2101
53
        // GIR_Coverage, 1494,
2102
53
        GIR_Done,
2103
53
      // Label 157: @4497
2104
53
      GIM_Try, /*On fail goto*//*Label 158*/ 4527, // Rule ID 1495 //
2105
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2106
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_256RegClassID,
2107
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_256RegClassID,
2108
53
        // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
2109
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2110
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2111
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2112
53
        GIR_EraseFromParent, /*InsnID*/0,
2113
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_256*/25,
2114
53
        // GIR_Coverage, 1495,
2115
53
        GIR_Done,
2116
53
      // Label 158: @4527
2117
53
      GIM_Reject,
2118
53
    // Label 154: @4528
2119
53
    GIM_Reject,
2120
53
    // Label 94: @4529
2121
53
    GIM_Try, /*On fail goto*//*Label 159*/ 4588,
2122
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
2123
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_512RegClassID,
2124
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_512RegClassID,
2125
53
      GIM_Try, /*On fail goto*//*Label 160*/ 4565, // Rule ID 1496 //
2126
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2127
53
        // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
2128
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2129
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2130
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2131
53
        GIR_EraseFromParent, /*InsnID*/0,
2132
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_512*/29,
2133
53
        // GIR_Coverage, 1496,
2134
53
        GIR_Done,
2135
53
      // Label 160: @4565
2136
53
      GIM_Try, /*On fail goto*//*Label 161*/ 4587, // Rule ID 1497 //
2137
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2138
53
        // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
2139
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2140
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2141
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2142
53
        GIR_EraseFromParent, /*InsnID*/0,
2143
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_512*/29,
2144
53
        // GIR_Coverage, 1497,
2145
53
        GIR_Done,
2146
53
      // Label 161: @4587
2147
53
      GIM_Reject,
2148
53
    // Label 159: @4588
2149
53
    GIM_Reject,
2150
53
    // Label 95: @4589
2151
53
    GIM_Reject,
2152
53
    // Label 7: @4590
2153
53
    GIM_Try, /*On fail goto*//*Label 162*/ 4680,
2154
53
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
2155
53
      GIM_Try, /*On fail goto*//*Label 163*/ 4623, // Rule ID 438 //
2156
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2157
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_getpc,
2158
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2159
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2160
53
        // (intrinsic_wo_chain:{ *:[i64] } 930:{ *:[iPTR] })  =>  (S_GETPC_B64:{ *:[i64] })
2161
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_GETPC_B64,
2162
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2163
53
        GIR_EraseFromParent, /*InsnID*/0,
2164
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2165
53
        // GIR_Coverage, 438,
2166
53
        GIR_Done,
2167
53
      // Label 163: @4623
2168
53
      GIM_Try, /*On fail goto*//*Label 164*/ 4651, // Rule ID 635 //
2169
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2170
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_groupstaticsize,
2171
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2172
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2173
53
        // (intrinsic_wo_chain:{ *:[i32] } 433:{ *:[iPTR] })  =>  (GET_GROUPSTATICSIZE:{ *:[i32] })
2174
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GET_GROUPSTATICSIZE,
2175
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2176
53
        GIR_EraseFromParent, /*InsnID*/0,
2177
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2178
53
        // GIR_Coverage, 635,
2179
53
        GIR_Done,
2180
53
      // Label 164: @4651
2181
53
      GIM_Try, /*On fail goto*//*Label 165*/ 4679, // Rule ID 644 //
2182
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2183
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_ps_live,
2184
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
2185
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2186
53
        // (intrinsic_wo_chain:{ *:[i1] } 914:{ *:[iPTR] })  =>  (SI_PS_LIVE:{ *:[i1] })
2187
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_PS_LIVE,
2188
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2189
53
        GIR_EraseFromParent, /*InsnID*/0,
2190
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2191
53
        // GIR_Coverage, 644,
2192
53
        GIR_Done,
2193
53
      // Label 165: @4679
2194
53
      GIM_Reject,
2195
53
    // Label 162: @4680
2196
53
    GIM_Try, /*On fail goto*//*Label 166*/ 5151,
2197
53
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2198
53
      GIM_Try, /*On fail goto*//*Label 167*/ 4721, // Rule ID 262 //
2199
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2200
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_readfirstlane,
2201
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2202
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2203
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2204
53
        // (intrinsic_wo_chain:{ *:[i32] } 919:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
2205
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READFIRSTLANE_B32,
2206
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2207
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2208
53
        GIR_EraseFromParent, /*InsnID*/0,
2209
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2210
53
        // GIR_Coverage, 262,
2211
53
        GIR_Done,
2212
53
      // Label 167: @4721
2213
53
      GIM_Try, /*On fail goto*//*Label 168*/ 4757, // Rule ID 430 //
2214
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2215
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_wqm_vote,
2216
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
2217
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
2218
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2219
53
        // (intrinsic_wo_chain:{ *:[i1] } 966:{ *:[iPTR] }, i1:{ *:[i1] }:$src0)  =>  (S_WQM_B64:{ *:[i1] }:{ *:[i1] } i1:{ *:[i1] }:$src0)
2220
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_WQM_B64,
2221
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2222
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2223
53
        GIR_EraseFromParent, /*InsnID*/0,
2224
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2225
53
        // GIR_Coverage, 430,
2226
53
        GIR_Done,
2227
53
      // Label 168: @4757
2228
53
      GIM_Try, /*On fail goto*//*Label 169*/ 4793, // Rule ID 641 //
2229
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2230
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_break,
2231
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2232
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2233
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2234
53
        // (intrinsic_wo_chain:{ *:[i64] } 377:{ *:[iPTR] }, i64:{ *:[i64] }:$src)  =>  (SI_BREAK:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src)
2235
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_BREAK,
2236
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2237
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2238
53
        GIR_EraseFromParent, /*InsnID*/0,
2239
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2240
53
        // GIR_Coverage, 641,
2241
53
        GIR_Done,
2242
53
      // Label 169: @4793
2243
53
      GIM_Try, /*On fail goto*//*Label 170*/ 4844, // Rule ID 297 //
2244
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2245
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2246
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2247
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2248
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2249
53
        // (intrinsic_wo_chain:{ *:[i32] } 431:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2250
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F64_e64,
2251
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2252
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2253
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2254
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2255
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2256
53
        GIR_EraseFromParent, /*InsnID*/0,
2257
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2258
53
        // GIR_Coverage, 297,
2259
53
        GIR_Done,
2260
53
      // Label 170: @4844
2261
53
      GIM_Try, /*On fail goto*//*Label 171*/ 4895, // Rule ID 298 //
2262
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2263
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2264
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2265
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2266
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2267
53
        // (intrinsic_wo_chain:{ *:[f64] } 432:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2268
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F64_e64,
2269
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2270
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2271
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2272
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2273
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2274
53
        GIR_EraseFromParent, /*InsnID*/0,
2275
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2276
53
        // GIR_Coverage, 298,
2277
53
        GIR_Done,
2278
53
      // Label 171: @4895
2279
53
      GIM_Try, /*On fail goto*//*Label 172*/ 4946, // Rule ID 300 //
2280
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2281
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2282
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2283
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2284
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2285
53
        // (intrinsic_wo_chain:{ *:[i32] } 431:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2286
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F32_e64,
2287
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2288
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2289
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2290
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2291
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2292
53
        GIR_EraseFromParent, /*InsnID*/0,
2293
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2294
53
        // GIR_Coverage, 300,
2295
53
        GIR_Done,
2296
53
      // Label 172: @4946
2297
53
      GIM_Try, /*On fail goto*//*Label 173*/ 4997, // Rule ID 301 //
2298
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2299
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2300
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2301
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2302
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2303
53
        // (intrinsic_wo_chain:{ *:[f32] } 432:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2304
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F32_e64,
2305
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2306
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2307
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2308
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2309
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2310
53
        GIR_EraseFromParent, /*InsnID*/0,
2311
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2312
53
        // GIR_Coverage, 301,
2313
53
        GIR_Done,
2314
53
      // Label 173: @4997
2315
53
      GIM_Try, /*On fail goto*//*Label 174*/ 5048, // Rule ID 302 //
2316
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_log_clamp,
2317
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2318
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2319
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2320
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2321
53
        // (intrinsic_wo_chain:{ *:[f32] } 906:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_CLAMP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2322
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_CLAMP_F32_e64,
2323
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2324
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2325
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2326
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2327
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2328
53
        GIR_EraseFromParent, /*InsnID*/0,
2329
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2330
53
        // GIR_Coverage, 302,
2331
53
        GIR_Done,
2332
53
      // Label 174: @5048
2333
53
      GIM_Try, /*On fail goto*//*Label 175*/ 5099, // Rule ID 322 //
2334
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2335
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
2336
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2337
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2338
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2339
53
        // (intrinsic_wo_chain:{ *:[f16] } 432:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2340
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F16_e64,
2341
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2342
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2343
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2344
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2345
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2346
53
        GIR_EraseFromParent, /*InsnID*/0,
2347
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2348
53
        // GIR_Coverage, 322,
2349
53
        GIR_Done,
2350
53
      // Label 175: @5099
2351
53
      GIM_Try, /*On fail goto*//*Label 176*/ 5150, // Rule ID 323 //
2352
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2353
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
2354
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2355
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2356
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2357
53
        // (intrinsic_wo_chain:{ *:[i16] } 431:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2358
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I16_F16_e64,
2359
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2360
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2361
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2362
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2363
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2364
53
        GIR_EraseFromParent, /*InsnID*/0,
2365
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2366
53
        // GIR_Coverage, 323,
2367
53
        GIR_Done,
2368
53
      // Label 176: @5150
2369
53
      GIM_Reject,
2370
53
    // Label 166: @5151
2371
53
    GIM_Try, /*On fail goto*//*Label 177*/ 6057,
2372
53
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
2373
53
      GIM_Try, /*On fail goto*//*Label 178*/ 5226, // Rule ID 1747 //
2374
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2375
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2376
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2377
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2378
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2379
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2380
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2381
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2382
53
        // (intrinsic_wo_chain:{ *:[f64] } 131:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2383
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
2384
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2385
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2386
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2387
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2388
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2389
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2390
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
2391
53
        GIR_EraseFromParent, /*InsnID*/0,
2392
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2393
53
        // GIR_Coverage, 1747,
2394
53
        GIR_Done,
2395
53
      // Label 178: @5226
2396
53
      GIM_Try, /*On fail goto*//*Label 179*/ 5296, // Rule ID 1750 //
2397
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2398
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2399
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2400
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2401
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2402
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2403
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2404
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2405
53
        // (intrinsic_wo_chain:{ *:[f64] } 138:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2406
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
2407
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2408
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2409
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2410
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2411
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2412
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2413
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
2414
53
        GIR_EraseFromParent, /*InsnID*/0,
2415
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2416
53
        // GIR_Coverage, 1750,
2417
53
        GIR_Done,
2418
53
      // Label 179: @5296
2419
53
      GIM_Try, /*On fail goto*//*Label 180*/ 5366, // Rule ID 1946 //
2420
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2421
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2422
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2423
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2424
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2425
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2426
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods,
2427
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods0,
2428
53
        // (intrinsic_wo_chain:{ *:[f64] } 131:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods))  =>  (V_MAX_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2429
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
2430
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2431
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
2432
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
2433
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
2434
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
2435
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
2436
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omods
2437
53
        GIR_EraseFromParent, /*InsnID*/0,
2438
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2439
53
        // GIR_Coverage, 1946,
2440
53
        GIR_Done,
2441
53
      // Label 180: @5366
2442
53
      GIM_Try, /*On fail goto*//*Label 181*/ 5436, // Rule ID 1947 //
2443
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2444
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2445
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2446
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2447
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2448
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2449
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods,
2450
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods0,
2451
53
        // (intrinsic_wo_chain:{ *:[f64] } 138:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods))  =>  (V_MIN_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2452
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
2453
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2454
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
2455
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
2456
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
2457
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
2458
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
2459
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omods
2460
53
        GIR_EraseFromParent, /*InsnID*/0,
2461
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2462
53
        // GIR_Coverage, 1947,
2463
53
        GIR_Done,
2464
53
      // Label 181: @5436
2465
53
      GIM_Try, /*On fail goto*//*Label 182*/ 5489, // Rule ID 1737 //
2466
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2467
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pkrtz,
2468
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
2469
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2470
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2471
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2472
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
2473
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
2474
53
        // (intrinsic_wo_chain:{ *:[v2f16] } 407:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_CVT_PKRTZ_F16_F32_e32:{ *:[v2f16] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2475
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PKRTZ_F16_F32_e32,
2476
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2477
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2478
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2479
53
        GIR_EraseFromParent, /*InsnID*/0,
2480
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2481
53
        // GIR_Coverage, 1737,
2482
53
        GIR_Done,
2483
53
      // Label 182: @5489
2484
53
      GIM_Try, /*On fail goto*//*Label 183*/ 5542, // Rule ID 1745 //
2485
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2486
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2487
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2488
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2489
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2490
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2491
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
2492
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
2493
53
        // (intrinsic_wo_chain:{ *:[f32] } 131:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_MAX_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2494
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e32,
2495
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2496
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2497
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2498
53
        GIR_EraseFromParent, /*InsnID*/0,
2499
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2500
53
        // GIR_Coverage, 1745,
2501
53
        GIR_Done,
2502
53
      // Label 183: @5542
2503
53
      GIM_Try, /*On fail goto*//*Label 184*/ 5595, // Rule ID 1748 //
2504
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2505
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2506
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2507
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2508
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2509
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2510
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
2511
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
2512
53
        // (intrinsic_wo_chain:{ *:[f32] } 138:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_MIN_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2513
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e32,
2514
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2515
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2516
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2517
53
        GIR_EraseFromParent, /*InsnID*/0,
2518
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2519
53
        // GIR_Coverage, 1748,
2520
53
        GIR_Done,
2521
53
      // Label 184: @5595
2522
53
      GIM_Try, /*On fail goto*//*Label 185*/ 5648, // Rule ID 1738 //
2523
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2524
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pkrtz,
2525
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
2526
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2527
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2528
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2529
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
2530
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
2531
53
        // (intrinsic_wo_chain:{ *:[v2f16] } 407:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_CVT_PKRTZ_F16_F32_e32:{ *:[v2f16] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2532
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PKRTZ_F16_F32_e32,
2533
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2534
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2535
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2536
53
        GIR_EraseFromParent, /*InsnID*/0,
2537
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2538
53
        // GIR_Coverage, 1738,
2539
53
        GIR_Done,
2540
53
      // Label 185: @5648
2541
53
      GIM_Try, /*On fail goto*//*Label 186*/ 5701, // Rule ID 1746 //
2542
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2543
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2544
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2545
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2546
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2547
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2548
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
2549
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
2550
53
        // (intrinsic_wo_chain:{ *:[f32] } 131:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_MAX_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2551
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e32,
2552
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2553
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2554
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2555
53
        GIR_EraseFromParent, /*InsnID*/0,
2556
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2557
53
        // GIR_Coverage, 1746,
2558
53
        GIR_Done,
2559
53
      // Label 186: @5701
2560
53
      GIM_Try, /*On fail goto*//*Label 187*/ 5754, // Rule ID 1749 //
2561
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2562
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2563
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2564
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2565
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2566
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2567
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
2568
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
2569
53
        // (intrinsic_wo_chain:{ *:[f32] } 138:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_MIN_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2570
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e32,
2571
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2572
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2573
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2574
53
        GIR_EraseFromParent, /*InsnID*/0,
2575
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2576
53
        // GIR_Coverage, 1749,
2577
53
        GIR_Done,
2578
53
      // Label 187: @5754
2579
53
      GIM_Try, /*On fail goto*//*Label 188*/ 5796, // Rule ID 339 //
2580
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_readlane,
2581
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2582
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2583
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2584
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2585
53
        // (intrinsic_wo_chain:{ *:[i32] } 920:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2586
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READLANE_B32,
2587
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2588
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2589
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2590
53
        GIR_EraseFromParent, /*InsnID*/0,
2591
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2592
53
        // GIR_Coverage, 339,
2593
53
        GIR_Done,
2594
53
      // Label 188: @5796
2595
53
      GIM_Try, /*On fail goto*//*Label 189*/ 5840, // Rule ID 631 //
2596
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2597
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_set_inactive,
2598
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2599
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2600
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2601
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2602
53
        // (intrinsic_wo_chain:{ *:[i32] } 946:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)
2603
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B32,
2604
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2605
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2606
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
2607
53
        GIR_EraseFromParent, /*InsnID*/0,
2608
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2609
53
        // GIR_Coverage, 631,
2610
53
        GIR_Done,
2611
53
      // Label 189: @5840
2612
53
      GIM_Try, /*On fail goto*//*Label 190*/ 5884, // Rule ID 632 //
2613
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2614
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_set_inactive,
2615
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2616
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2617
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2618
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2619
53
        // (intrinsic_wo_chain:{ *:[i64] } 946:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)  =>  (V_SET_INACTIVE_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)
2620
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B64,
2621
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2622
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2623
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
2624
53
        GIR_EraseFromParent, /*InsnID*/0,
2625
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2626
53
        // GIR_Coverage, 632,
2627
53
        GIR_Done,
2628
53
      // Label 190: @5884
2629
53
      GIM_Try, /*On fail goto*//*Label 191*/ 5928, // Rule ID 642 //
2630
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2631
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_if_break,
2632
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2633
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
2634
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2635
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2636
53
        // (intrinsic_wo_chain:{ *:[i64] } 436:{ *:[iPTR] }, i1:{ *:[i1] }:$vcc, i64:{ *:[i64] }:$src)  =>  (SI_IF_BREAK:{ *:[i64] }:{ *:[i1] } i1:{ *:[i1] }:$vcc, i64:{ *:[i64] }:$src)
2637
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_IF_BREAK,
2638
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2639
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vcc
2640
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
2641
53
        GIR_EraseFromParent, /*InsnID*/0,
2642
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2643
53
        // GIR_Coverage, 642,
2644
53
        GIR_Done,
2645
53
      // Label 191: @5928
2646
53
      GIM_Try, /*On fail goto*//*Label 192*/ 5972, // Rule ID 643 //
2647
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2648
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_else_break,
2649
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2650
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2651
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2652
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2653
53
        // (intrinsic_wo_chain:{ *:[i64] } 420:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (SI_ELSE_BREAK:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
2654
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_ELSE_BREAK,
2655
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2656
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2657
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2658
53
        GIR_EraseFromParent, /*InsnID*/0,
2659
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2660
53
        // GIR_Coverage, 643,
2661
53
        GIR_Done,
2662
53
      // Label 192: @5972
2663
53
      GIM_Try, /*On fail goto*//*Label 193*/ 6014, // Rule ID 341 //
2664
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mbcnt_lo,
2665
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2666
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2667
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2668
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2669
53
        // (intrinsic_wo_chain:{ *:[i32] } 909:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_LO_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2670
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_LO_U32_B32_e64,
2671
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2672
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2673
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2674
53
        GIR_EraseFromParent, /*InsnID*/0,
2675
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2676
53
        // GIR_Coverage, 341,
2677
53
        GIR_Done,
2678
53
      // Label 193: @6014
2679
53
      GIM_Try, /*On fail goto*//*Label 194*/ 6056, // Rule ID 342 //
2680
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mbcnt_hi,
2681
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2682
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2683
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2684
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2685
53
        // (intrinsic_wo_chain:{ *:[i32] } 908:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_HI_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2686
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_HI_U32_B32_e64,
2687
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2688
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2689
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2690
53
        GIR_EraseFromParent, /*InsnID*/0,
2691
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2692
53
        // GIR_Coverage, 342,
2693
53
        GIR_Done,
2694
53
      // Label 194: @6056
2695
53
      GIM_Reject,
2696
53
    // Label 177: @6057
2697
53
    GIM_Try, /*On fail goto*//*Label 195*/ 7069,
2698
53
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
2699
53
      GIM_Try, /*On fail goto*//*Label 196*/ 6112, // Rule ID 340 //
2700
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_writelane,
2701
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2702
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2703
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2704
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2705
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2706
53
        // (intrinsic_wo_chain:{ *:[i32] } 967:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)  =>  (V_WRITELANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)
2707
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_WRITELANE_B32,
2708
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2709
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2710
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2711
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vdst_in
2712
53
        GIR_EraseFromParent, /*InsnID*/0,
2713
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2714
53
        // GIR_Coverage, 340,
2715
53
        GIR_Done,
2716
53
      // Label 196: @6112
2717
53
      GIM_Try, /*On fail goto*//*Label 197*/ 6167, // Rule ID 894 //
2718
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2719
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_u8,
2720
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2721
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2722
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2723
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2724
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2725
53
        // (intrinsic_wo_chain:{ *:[i32] } 941:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2726
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U8,
2727
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2728
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2729
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2730
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2731
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2732
53
        GIR_EraseFromParent, /*InsnID*/0,
2733
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2734
53
        // GIR_Coverage, 894,
2735
53
        GIR_Done,
2736
53
      // Label 197: @6167
2737
53
      GIM_Try, /*On fail goto*//*Label 198*/ 6222, // Rule ID 895 //
2738
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2739
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_hi_u8,
2740
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2741
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2742
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2743
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2744
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2745
53
        // (intrinsic_wo_chain:{ *:[i32] } 939:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_HI_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2746
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_HI_U8,
2747
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2748
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2749
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2750
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2751
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2752
53
        GIR_EraseFromParent, /*InsnID*/0,
2753
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2754
53
        // GIR_Coverage, 895,
2755
53
        GIR_Done,
2756
53
      // Label 198: @6222
2757
53
      GIM_Try, /*On fail goto*//*Label 199*/ 6277, // Rule ID 896 //
2758
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2759
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_u16,
2760
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2761
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2762
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2763
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2764
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2765
53
        // (intrinsic_wo_chain:{ *:[i32] } 940:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U16:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2766
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U16,
2767
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2768
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2769
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2770
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2771
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2772
53
        GIR_EraseFromParent, /*InsnID*/0,
2773
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2774
53
        // GIR_Coverage, 896,
2775
53
        GIR_Done,
2776
53
      // Label 199: @6277
2777
53
      GIM_Try, /*On fail goto*//*Label 200*/ 6332, // Rule ID 897 //
2778
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2779
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_msad_u8,
2780
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2781
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2782
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2783
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2784
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2785
53
        // (intrinsic_wo_chain:{ *:[i32] } 913:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_MSAD_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2786
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MSAD_U8,
2787
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2788
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2789
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2790
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2791
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2792
53
        GIR_EraseFromParent, /*InsnID*/0,
2793
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2794
53
        // GIR_Coverage, 897,
2795
53
        GIR_Done,
2796
53
      // Label 200: @6332
2797
53
      GIM_Try, /*On fail goto*//*Label 201*/ 6387, // Rule ID 898 //
2798
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2799
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mqsad_pk_u16_u8,
2800
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2801
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2802
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2803
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
2804
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2805
53
        // (intrinsic_wo_chain:{ *:[i64] } 911:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_MQSAD_PK_U16_U8:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
2806
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_PK_U16_U8,
2807
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2808
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2809
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2810
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2811
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2812
53
        GIR_EraseFromParent, /*InsnID*/0,
2813
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2814
53
        // GIR_Coverage, 898,
2815
53
        GIR_Done,
2816
53
      // Label 201: @6387
2817
53
      GIM_Try, /*On fail goto*//*Label 202*/ 6442, // Rule ID 899 //
2818
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2819
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_qsad_pk_u16_u8,
2820
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2821
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2822
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2823
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
2824
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2825
53
        // (intrinsic_wo_chain:{ *:[i64] } 915:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_QSAD_PK_U16_U8:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
2826
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_QSAD_PK_U16_U8,
2827
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2828
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2829
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2830
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2831
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2832
53
        GIR_EraseFromParent, /*InsnID*/0,
2833
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2834
53
        // GIR_Coverage, 899,
2835
53
        GIR_Done,
2836
53
      // Label 202: @6442
2837
53
      GIM_Try, /*On fail goto*//*Label 203*/ 6497, // Rule ID 900 //
2838
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2839
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mqsad_u32_u8,
2840
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
2841
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2842
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2843
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
2844
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
2845
53
        // (intrinsic_wo_chain:{ *:[v4i32] } 912:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2)  =>  (V_MQSAD_U32_U8:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] })
2846
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_U32_U8,
2847
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2848
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2849
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2850
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2851
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2852
53
        GIR_EraseFromParent, /*InsnID*/0,
2853
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2854
53
        // GIR_Coverage, 900,
2855
53
        GIR_Done,
2856
53
      // Label 203: @6497
2857
53
      GIM_Try, /*On fail goto*//*Label 204*/ 6582, // Rule ID 369 //
2858
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubeid,
2859
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2860
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2861
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2862
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2863
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2864
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2865
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2866
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2867
53
        // (intrinsic_wo_chain:{ *:[f32] } 398:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEID_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2868
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEID_F32,
2869
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2870
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2871
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2872
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2873
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2874
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2875
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2876
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2877
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2878
53
        GIR_EraseFromParent, /*InsnID*/0,
2879
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2880
53
        // GIR_Coverage, 369,
2881
53
        GIR_Done,
2882
53
      // Label 204: @6582
2883
53
      GIM_Try, /*On fail goto*//*Label 205*/ 6667, // Rule ID 370 //
2884
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubesc,
2885
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2886
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2887
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2888
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2889
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2890
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2891
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2892
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2893
53
        // (intrinsic_wo_chain:{ *:[f32] } 400:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBESC_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2894
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBESC_F32,
2895
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2896
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2897
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2898
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2899
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2900
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2901
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2902
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2903
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2904
53
        GIR_EraseFromParent, /*InsnID*/0,
2905
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2906
53
        // GIR_Coverage, 370,
2907
53
        GIR_Done,
2908
53
      // Label 205: @6667
2909
53
      GIM_Try, /*On fail goto*//*Label 206*/ 6752, // Rule ID 371 //
2910
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubetc,
2911
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2912
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2913
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2914
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2915
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2916
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2917
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2918
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2919
53
        // (intrinsic_wo_chain:{ *:[f32] } 401:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBETC_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2920
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBETC_F32,
2921
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2922
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2923
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2924
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2925
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2926
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2927
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2928
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2929
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2930
53
        GIR_EraseFromParent, /*InsnID*/0,
2931
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2932
53
        // GIR_Coverage, 371,
2933
53
        GIR_Done,
2934
53
      // Label 206: @6752
2935
53
      GIM_Try, /*On fail goto*//*Label 207*/ 6837, // Rule ID 372 //
2936
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubema,
2937
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2938
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2939
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2940
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2941
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2942
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2943
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2944
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2945
53
        // (intrinsic_wo_chain:{ *:[f32] } 399:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEMA_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2946
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEMA_F32,
2947
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2948
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2949
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2950
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2951
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2952
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2953
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2954
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2955
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2956
53
        GIR_EraseFromParent, /*InsnID*/0,
2957
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2958
53
        // GIR_Coverage, 372,
2959
53
        GIR_Done,
2960
53
      // Label 207: @6837
2961
53
      GIM_Try, /*On fail goto*//*Label 208*/ 6918, // Rule ID 387 //
2962
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pk_u8_f32,
2963
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2964
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2965
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2966
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2967
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2968
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2969
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2970
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2971
53
        // (intrinsic_wo_chain:{ *:[i32] } 404:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CVT_PK_U8_F32:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
2972
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PK_U8_F32,
2973
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2974
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2975
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2976
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2977
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2978
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2979
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2980
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2981
53
        GIR_EraseFromParent, /*InsnID*/0,
2982
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2983
53
        // GIR_Coverage, 387,
2984
53
        GIR_Done,
2985
53
      // Label 208: @6918
2986
53
      GIM_Try, /*On fail goto*//*Label 209*/ 6968, // Rule ID 359 //
2987
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_lerp,
2988
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2989
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2990
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2991
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2992
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2993
53
        // (intrinsic_wo_chain:{ *:[i32] } 905:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_LERP_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
2994
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LERP_U8,
2995
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2996
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2997
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2998
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2999
53
        GIR_EraseFromParent, /*InsnID*/0,
3000
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3001
53
        // GIR_Coverage, 359,
3002
53
        GIR_Done,
3003
53
      // Label 209: @6968
3004
53
      GIM_Try, /*On fail goto*//*Label 210*/ 7018, // Rule ID 376 //
3005
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_alignbit,
3006
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3007
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3008
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
3009
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
3010
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3011
53
        // (intrinsic_wo_chain:{ *:[i32] } 373:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBIT_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
3012
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBIT_B32,
3013
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3014
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
3015
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
3016
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
3017
53
        GIR_EraseFromParent, /*InsnID*/0,
3018
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3019
53
        // GIR_Coverage, 376,
3020
53
        GIR_Done,
3021
53
      // Label 210: @7018
3022
53
      GIM_Try, /*On fail goto*//*Label 211*/ 7068, // Rule ID 377 //
3023
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_alignbyte,
3024
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3025
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3026
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
3027
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
3028
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3029
53
        // (intrinsic_wo_chain:{ *:[i32] } 374:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBYTE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
3030
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBYTE_B32,
3031
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3032
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
3033
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
3034
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
3035
53
        GIR_EraseFromParent, /*InsnID*/0,
3036
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3037
53
        // GIR_Coverage, 377,
3038
53
        GIR_Done,
3039
53
      // Label 211: @7068
3040
53
      GIM_Reject,
3041
53
    // Label 195: @7069
3042
53
    GIM_Reject,
3043
53
    // Label 8: @7070
3044
53
    GIM_Try, /*On fail goto*//*Label 212*/ 7090, // Rule ID 481 //
3045
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3046
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_barrier,
3047
53
      // (intrinsic_void 924:{ *:[iPTR] })  =>  (S_BARRIER)
3048
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_BARRIER,
3049
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3050
53
      GIR_EraseFromParent, /*InsnID*/0,
3051
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3052
53
      // GIR_Coverage, 481,
3053
53
      GIR_Done,
3054
53
    // Label 212: @7090
3055
53
    GIM_Try, /*On fail goto*//*Label 213*/ 7110, // Rule ID 488 //
3056
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3057
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_inv,
3058
53
      // (intrinsic_void 925:{ *:[iPTR] })  =>  (S_DCACHE_INV)
3059
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV,
3060
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3061
53
      GIR_EraseFromParent, /*InsnID*/0,
3062
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3063
53
      // GIR_Coverage, 488,
3064
53
      GIR_Done,
3065
53
    // Label 213: @7110
3066
53
    GIM_Try, /*On fail goto*//*Label 214*/ 7130, // Rule ID 489 //
3067
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isCIVI,
3068
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_inv_vol,
3069
53
      // (intrinsic_void 926:{ *:[iPTR] })  =>  (S_DCACHE_INV_VOL)
3070
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV_VOL,
3071
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3072
53
      GIR_EraseFromParent, /*InsnID*/0,
3073
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3074
53
      // GIR_Coverage, 489,
3075
53
      GIR_Done,
3076
53
    // Label 214: @7130
3077
53
    GIM_Try, /*On fail goto*//*Label 215*/ 7150, // Rule ID 490 //
3078
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
3079
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_wb,
3080
53
      // (intrinsic_void 927:{ *:[iPTR] })  =>  (S_DCACHE_WB)
3081
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB,
3082
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3083
53
      GIR_EraseFromParent, /*InsnID*/0,
3084
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3085
53
      // GIR_Coverage, 490,
3086
53
      GIR_Done,
3087
53
    // Label 215: @7150
3088
53
    GIM_Try, /*On fail goto*//*Label 216*/ 7170, // Rule ID 491 //
3089
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
3090
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_wb_vol,
3091
53
      // (intrinsic_void 928:{ *:[iPTR] })  =>  (S_DCACHE_WB_VOL)
3092
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB_VOL,
3093
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3094
53
      GIR_EraseFromParent, /*InsnID*/0,
3095
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3096
53
      // GIR_Coverage, 491,
3097
53
      GIR_Done,
3098
53
    // Label 216: @7170
3099
53
    GIM_Try, /*On fail goto*//*Label 217*/ 7190, // Rule ID 621 //
3100
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isSI,
3101
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1_sc,
3102
53
      // (intrinsic_void 394:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_SC)
3103
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_SC,
3104
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3105
53
      GIR_EraseFromParent, /*InsnID*/0,
3106
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3107
53
      // GIR_Coverage, 621,
3108
53
      GIR_Done,
3109
53
    // Label 217: @7190
3110
53
    GIM_Try, /*On fail goto*//*Label 218*/ 7210, // Rule ID 622 //
3111
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3112
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1,
3113
53
      // (intrinsic_void 393:{ *:[iPTR] })  =>  (BUFFER_WBINVL1)
3114
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1,
3115
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3116
53
      GIR_EraseFromParent, /*InsnID*/0,
3117
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3118
53
      // GIR_Coverage, 622,
3119
53
      GIR_Done,
3120
53
    // Label 218: @7210
3121
53
    GIM_Try, /*On fail goto*//*Label 219*/ 7230, // Rule ID 623 //
3122
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isCIVI,
3123
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1_vol,
3124
53
      // (intrinsic_void 395:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_VOL)
3125
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_VOL,
3126
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3127
53
      GIR_EraseFromParent, /*InsnID*/0,
3128
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3129
53
      // GIR_Coverage, 623,
3130
53
      GIR_Done,
3131
53
    // Label 219: @7230
3132
53
    GIM_Try, /*On fail goto*//*Label 220*/ 7250, // Rule ID 636 //
3133
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3134
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_wave_barrier,
3135
53
      // (intrinsic_void 958:{ *:[iPTR] })  =>  (WAVE_BARRIER)
3136
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::WAVE_BARRIER,
3137
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3138
53
      GIR_EraseFromParent, /*InsnID*/0,
3139
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3140
53
      // GIR_Coverage, 636,
3141
53
      GIR_Done,
3142
53
    // Label 220: @7250
3143
53
    GIM_Try, /*On fail goto*//*Label 221*/ 7270, // Rule ID 645 //
3144
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3145
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_unreachable,
3146
53
      // (intrinsic_void 956:{ *:[iPTR] })  =>  (SI_MASKED_UNREACHABLE)
3147
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_MASKED_UNREACHABLE,
3148
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3149
53
      GIR_EraseFromParent, /*InsnID*/0,
3150
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3151
53
      // GIR_Coverage, 645,
3152
53
      GIR_Done,
3153
53
    // Label 221: @7270
3154
53
    GIM_Try, /*On fail goto*//*Label 222*/ 7368,
3155
53
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
3156
53
      GIM_Try, /*On fail goto*//*Label 223*/ 7307, // Rule ID 487 //
3157
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3158
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_memtime,
3159
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
3160
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64_XEXECRegClassID,
3161
53
        // (intrinsic_w_chain:{ *:[i64] } 934:{ *:[iPTR] })  =>  (S_MEMTIME:{ *:[i64] })
3162
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMTIME,
3163
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3164
53
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3165
53
        GIR_EraseFromParent, /*InsnID*/0,
3166
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3167
53
        // GIR_Coverage, 487,
3168
53
        GIR_Done,
3169
53
      // Label 223: @7307
3170
53
      GIM_Try, /*On fail goto*//*Label 224*/ 7339, // Rule ID 492 //
3171
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
3172
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_memrealtime,
3173
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
3174
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64_XEXECRegClassID,
3175
53
        // (intrinsic_w_chain:{ *:[i64] } 933:{ *:[iPTR] })  =>  (S_MEMREALTIME:{ *:[i64] })
3176
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMREALTIME,
3177
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3178
53
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3179
53
        GIR_EraseFromParent, /*InsnID*/0,
3180
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3181
53
        // GIR_Coverage, 492,
3182
53
        GIR_Done,
3183
53
      // Label 224: @7339
3184
53
      GIM_Try, /*On fail goto*//*Label 225*/ 7367, // Rule ID 640 //
3185
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3186
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_end_cf,
3187
53
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3188
53
        // (intrinsic_void 421:{ *:[iPTR] }, i64:{ *:[i64] }:$saved)  =>  (SI_END_CF i64:{ *:[i64] }:$saved)
3189
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_END_CF,
3190
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // saved
3191
53
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3192
53
        GIR_EraseFromParent, /*InsnID*/0,
3193
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3194
53
        // GIR_Coverage, 640,
3195
53
        GIR_Done,
3196
53
      // Label 225: @7367
3197
53
      GIM_Reject,
3198
53
    // Label 222: @7368
3199
53
    GIM_Reject,
3200
53
    // Label 9: @7369
3201
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 228*/ 7425,
3202
53
    /*GILLT_s16*//*Label 226*/ 7377,
3203
53
    /*GILLT_s32*//*Label 227*/ 7401,
3204
53
    // Label 226: @7377
3205
53
    GIM_Try, /*On fail goto*//*Label 229*/ 7400, // Rule ID 912 //
3206
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3207
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3208
53
      // MIs[0] Operand 1
3209
53
      // No operand predicates
3210
53
      // (imm:{ *:[i16] }):$imm  =>  (S_MOV_B32:{ *:[i16] } (imm:{ *:[i16] }):$imm)
3211
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
3212
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3213
53
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
3214
53
      GIR_EraseFromParent, /*InsnID*/0,
3215
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3216
53
      // GIR_Coverage, 912,
3217
53
      GIR_Done,
3218
53
    // Label 229: @7400
3219
53
    GIM_Reject,
3220
53
    // Label 227: @7401
3221
53
    GIM_Try, /*On fail goto*//*Label 230*/ 7424, // Rule ID 1522 //
3222
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3223
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3224
53
      // MIs[0] Operand 1
3225
53
      // No operand predicates
3226
53
      // (imm:{ *:[i32] }):$imm  =>  (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
3227
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
3228
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3229
53
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
3230
53
      GIR_EraseFromParent, /*InsnID*/0,
3231
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3232
53
      // GIR_Coverage, 1522,
3233
53
      GIR_Done,
3234
53
    // Label 230: @7424
3235
53
    GIM_Reject,
3236
53
    // Label 228: @7425
3237
53
    GIM_Reject,
3238
53
    // Label 10: @7426
3239
53
    GIM_Try, /*On fail goto*//*Label 231*/ 7571,
3240
53
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3241
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3242
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3243
53
      GIM_Try, /*On fail goto*//*Label 232*/ 7505, // Rule ID 890 //
3244
53
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
3245
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3246
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3247
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
3248
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
3249
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3250
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_MUL,
3251
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
3252
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
3253
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3254
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3255
53
        // (sext:{ *:[i32] } (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MAD_I16:{ *:[i32] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
3256
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_I16,
3257
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3258
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
3259
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
3260
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
3261
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3262
53
        GIR_EraseFromParent, /*InsnID*/0,
3263
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3264
53
        // GIR_Coverage, 890,
3265
53
        GIR_Done,
3266
53
      // Label 232: @7505
3267
53
      GIM_Try, /*On fail goto*//*Label 233*/ 7570, // Rule ID 1839 //
3268
53
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
3269
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3270
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3271
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
3272
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
3273
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
3274
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_MUL,
3275
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
3276
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
3277
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3278
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3279
53
        // (sext:{ *:[i32] } (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MAD_I16:{ *:[i32] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
3280
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_I16,
3281
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3282
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
3283
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
3284
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
3285
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3286
53
        GIR_EraseFromParent, /*InsnID*/0,
3287
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3288
53
        // GIR_Coverage, 1839,
3289
53
        GIR_Done,
3290
53
      // Label 233: @7570
3291
53
      GIM_Reject,
3292
53
    // Label 231: @7571
3293
53
    GIM_Reject,
3294
53
    // Label 11: @7572
3295
53
    GIM_Try, /*On fail goto*//*Label 234*/ 7717,
3296
53
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3297
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3298
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3299
53
      GIM_Try, /*On fail goto*//*Label 235*/ 7651, // Rule ID 887 //
3300
53
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
3301
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3302
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3303
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
3304
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
3305
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3306
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_MUL,
3307
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
3308
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
3309
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3310
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3311
53
        // (zext:{ *:[i32] } (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MAD_U16:{ *:[i32] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
3312
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
3313
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3314
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
3315
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
3316
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
3317
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3318
53
        GIR_EraseFromParent, /*InsnID*/0,
3319
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3320
53
        // GIR_Coverage, 887,
3321
53
        GIR_Done,
3322
53
      // Label 235: @7651
3323
53
      GIM_Try, /*On fail goto*//*Label 236*/ 7716, // Rule ID 1837 //
3324
53
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
3325
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3326
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3327
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
3328
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
3329
53
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
3330
53
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_MUL,
3331
53
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
3332
53
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
3333
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3334
53
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3335
53
        // (zext:{ *:[i32] } (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MAD_U16:{ *:[i32] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
3336
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
3337
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3338
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
3339
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
3340
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
3341
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3342
53
        GIR_EraseFromParent, /*InsnID*/0,
3343
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3344
53
        // GIR_Coverage, 1837,
3345
53
        GIR_Done,
3346
53
      // Label 236: @7716
3347
53
      GIM_Reject,
3348
53
    // Label 234: @7717
3349
53
    GIM_Reject,
3350
53
    // Label 12: @7718
3351
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 239*/ 7780,
3352
53
    /*GILLT_s32*//*Label 237*/ 7726,
3353
53
    /*GILLT_s64*//*Label 238*/ 7753,
3354
53
    // Label 237: @7726
3355
53
    GIM_Try, /*On fail goto*//*Label 240*/ 7752, // Rule ID 456 //
3356
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3357
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3358
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3359
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3360
53
      // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_LSHL_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3361
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_LSHL_B32,
3362
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3363
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3364
53
      // GIR_Coverage, 456,
3365
53
      GIR_Done,
3366
53
    // Label 240: @7752
3367
53
    GIM_Reject,
3368
53
    // Label 238: @7753
3369
53
    GIM_Try, /*On fail goto*//*Label 241*/ 7779, // Rule ID 457 //
3370
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3371
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3372
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3373
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3374
53
      // (shl:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_LSHL_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
3375
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_LSHL_B64,
3376
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3377
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3378
53
      // GIR_Coverage, 457,
3379
53
      GIR_Done,
3380
53
    // Label 241: @7779
3381
53
    GIM_Reject,
3382
53
    // Label 239: @7780
3383
53
    GIM_Reject,
3384
53
    // Label 13: @7781
3385
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 244*/ 7843,
3386
53
    /*GILLT_s32*//*Label 242*/ 7789,
3387
53
    /*GILLT_s64*//*Label 243*/ 7816,
3388
53
    // Label 242: @7789
3389
53
    GIM_Try, /*On fail goto*//*Label 245*/ 7815, // Rule ID 458 //
3390
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3391
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3392
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3393
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3394
53
      // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_LSHR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3395
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_LSHR_B32,
3396
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3397
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3398
53
      // GIR_Coverage, 458,
3399
53
      GIR_Done,
3400
53
    // Label 245: @7815
3401
53
    GIM_Reject,
3402
53
    // Label 243: @7816
3403
53
    GIM_Try, /*On fail goto*//*Label 246*/ 7842, // Rule ID 459 //
3404
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3405
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3406
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3407
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3408
53
      // (srl:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_LSHR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
3409
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_LSHR_B64,
3410
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3411
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3412
53
      // GIR_Coverage, 459,
3413
53
      GIR_Done,
3414
53
    // Label 246: @7842
3415
53
    GIM_Reject,
3416
53
    // Label 244: @7843
3417
53
    GIM_Reject,
3418
53
    // Label 14: @7844
3419
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 249*/ 8047,
3420
53
    /*GILLT_s32*//*Label 247*/ 7852,
3421
53
    /*GILLT_s64*//*Label 248*/ 8020,
3422
53
    // Label 247: @7852
3423
53
    GIM_Try, /*On fail goto*//*Label 250*/ 8019,
3424
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3425
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3426
53
      GIM_Try, /*On fail goto*//*Label 251*/ 7899, // Rule ID 1742 //
3427
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isSICI,
3428
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3429
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
3430
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vsrc0,
3431
53
        // (sra:{ *:[i32] } (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0), VGPR_32:{ *:[i32] }:$src1)  =>  (V_ASHR_I32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3432
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHR_I32_e32,
3433
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3434
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3435
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3436
53
        GIR_EraseFromParent, /*InsnID*/0,
3437
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3438
53
        // GIR_Coverage, 1742,
3439
53
        GIR_Done,
3440
53
      // Label 251: @7899
3441
53
      GIM_Try, /*On fail goto*//*Label 252*/ 7936, // Rule ID 1743 //
3442
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3443
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3444
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
3445
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
3446
53
        // (sra:{ *:[i32] } VGPR_32:{ *:[i32] }:$src1, (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_ASHRREV_I32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3447
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I32_e32,
3448
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3449
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3450
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3451
53
        GIR_EraseFromParent, /*InsnID*/0,
3452
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3453
53
        // GIR_Coverage, 1743,
3454
53
        GIR_Done,
3455
53
      // Label 252: @7936
3456
53
      GIM_Try, /*On fail goto*//*Label 253*/ 7974, // Rule ID 1744 //
3457
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3458
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3459
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vcsrc,
3460
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vcsrc,
3461
53
        // (sra:{ *:[i32] } (sd_vcsrc:{ *:[i32] } i32:{ *:[i32] }:$src0), (sd_vcsrc:{ *:[i32] } i32:{ *:[i32] }:$src1))  =>  (V_ASHRREV_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)
3462
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I32_e64,
3463
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3464
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3465
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3466
53
        GIR_EraseFromParent, /*InsnID*/0,
3467
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3468
53
        // GIR_Coverage, 1744,
3469
53
        GIR_Done,
3470
53
      // Label 253: @7974
3471
53
      GIM_Try, /*On fail goto*//*Label 254*/ 7992, // Rule ID 460 //
3472
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3473
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3474
53
        // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3475
53
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ASHR_I32,
3476
53
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3477
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3478
53
        // GIR_Coverage, 460,
3479
53
        GIR_Done,
3480
53
      // Label 254: @7992
3481
53
      GIM_Try, /*On fail goto*//*Label 255*/ 8018, // Rule ID 1741 //
3482
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3483
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3484
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
3485
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
3486
53
        // (sra:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)  =>  (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3487
53
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ASHR_I32,
3488
53
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3489
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3490
53
        // GIR_Coverage, 1741,
3491
53
        GIR_Done,
3492
53
      // Label 255: @8018
3493
53
      GIM_Reject,
3494
53
    // Label 250: @8019
3495
53
    GIM_Reject,
3496
53
    // Label 248: @8020
3497
53
    GIM_Try, /*On fail goto*//*Label 256*/ 8046, // Rule ID 461 //
3498
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3499
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3500
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3501
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3502
53
      // (sra:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_ASHR_I64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
3503
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ASHR_I64,
3504
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3505
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3506
53
      // GIR_Coverage, 461,
3507
53
      GIR_Done,
3508
53
    // Label 256: @8046
3509
53
    GIM_Reject,
3510
53
    // Label 249: @8047
3511
53
    GIM_Reject,
3512
53
    // Label 15: @8048
3513
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 260*/ 8393,
3514
53
    /*GILLT_s16*//*Label 257*/ 8057,
3515
53
    /*GILLT_s32*//*Label 258*/ 8169,
3516
53
    /*GILLT_s64*//*Label 259*/ 8281,
3517
53
    // Label 257: @8057
3518
53
    GIM_Try, /*On fail goto*//*Label 261*/ 8168,
3519
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3520
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3521
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3522
53
      GIM_Try, /*On fail goto*//*Label 262*/ 8119, // Rule ID 352 //
3523
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3524
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3525
53
        // (fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3526
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
3527
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3528
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3529
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3530
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3531
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3532
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3533
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3534
53
        GIR_EraseFromParent, /*InsnID*/0,
3535
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3536
53
        // GIR_Coverage, 352,
3537
53
        GIR_Done,
3538
53
      // Label 262: @8119
3539
53
      GIM_Try, /*On fail goto*//*Label 263*/ 8167, // Rule ID 1757 //
3540
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3541
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3542
53
        // (fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3543
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
3544
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3545
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3546
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3547
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3548
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3549
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3550
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3551
53
        GIR_EraseFromParent, /*InsnID*/0,
3552
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3553
53
        // GIR_Coverage, 1757,
3554
53
        GIR_Done,
3555
53
      // Label 263: @8167
3556
53
      GIM_Reject,
3557
53
    // Label 261: @8168
3558
53
    GIM_Reject,
3559
53
    // Label 258: @8169
3560
53
    GIM_Try, /*On fail goto*//*Label 264*/ 8280,
3561
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3562
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3563
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3564
53
      GIM_Try, /*On fail goto*//*Label 265*/ 8231, // Rule ID 329 //
3565
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3566
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3567
53
        // (fadd:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3568
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
3569
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3570
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3571
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3572
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3573
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3574
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3575
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3576
53
        GIR_EraseFromParent, /*InsnID*/0,
3577
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3578
53
        // GIR_Coverage, 329,
3579
53
        GIR_Done,
3580
53
      // Label 265: @8231
3581
53
      GIM_Try, /*On fail goto*//*Label 266*/ 8279, // Rule ID 1752 //
3582
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3583
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3584
53
        // (fadd:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3585
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
3586
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3587
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3588
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3589
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3590
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3591
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3592
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3593
53
        GIR_EraseFromParent, /*InsnID*/0,
3594
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3595
53
        // GIR_Coverage, 1752,
3596
53
        GIR_Done,
3597
53
      // Label 266: @8279
3598
53
      GIM_Reject,
3599
53
    // Label 264: @8280
3600
53
    GIM_Reject,
3601
53
    // Label 259: @8281
3602
53
    GIM_Try, /*On fail goto*//*Label 267*/ 8392,
3603
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3604
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3605
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3606
53
      GIM_Try, /*On fail goto*//*Label 268*/ 8343, // Rule ID 361 //
3607
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3608
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3609
53
        // (fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3610
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
3611
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3612
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3613
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3614
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3615
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3616
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3617
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3618
53
        GIR_EraseFromParent, /*InsnID*/0,
3619
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3620
53
        // GIR_Coverage, 361,
3621
53
        GIR_Done,
3622
53
      // Label 268: @8343
3623
53
      GIM_Try, /*On fail goto*//*Label 269*/ 8391, // Rule ID 1761 //
3624
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3625
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3626
53
        // (fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3627
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
3628
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3629
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3630
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3631
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3632
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3633
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3634
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3635
53
        GIR_EraseFromParent, /*InsnID*/0,
3636
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3637
53
        // GIR_Coverage, 1761,
3638
53
        GIR_Done,
3639
53
      // Label 269: @8391
3640
53
      GIM_Reject,
3641
53
    // Label 267: @8392
3642
53
    GIM_Reject,
3643
53
    // Label 260: @8393
3644
53
    GIM_Reject,
3645
53
    // Label 16: @8394
3646
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 272*/ 8524,
3647
53
    /*GILLT_s16*//*Label 270*/ 8402,
3648
53
    /*GILLT_s32*//*Label 271*/ 8463,
3649
53
    // Label 270: @8402
3650
53
    GIM_Try, /*On fail goto*//*Label 273*/ 8462, // Rule ID 353 //
3651
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3652
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3653
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3654
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3655
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3656
53
      // (fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3657
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F16_e64,
3658
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3659
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3660
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3661
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3662
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3663
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3664
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3665
53
      GIR_EraseFromParent, /*InsnID*/0,
3666
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3667
53
      // GIR_Coverage, 353,
3668
53
      GIR_Done,
3669
53
    // Label 273: @8462
3670
53
    GIM_Reject,
3671
53
    // Label 271: @8463
3672
53
    GIM_Try, /*On fail goto*//*Label 274*/ 8523, // Rule ID 330 //
3673
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3674
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3675
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3676
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3677
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3678
53
      // (fsub:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3679
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F32_e64,
3680
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3681
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3682
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3683
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3684
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3685
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3686
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3687
53
      GIR_EraseFromParent, /*InsnID*/0,
3688
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3689
53
      // GIR_Coverage, 330,
3690
53
      GIR_Done,
3691
53
    // Label 274: @8523
3692
53
    GIM_Reject,
3693
53
    // Label 272: @8524
3694
53
    GIM_Reject,
3695
53
    // Label 17: @8525
3696
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 278*/ 8870,
3697
53
    /*GILLT_s16*//*Label 275*/ 8534,
3698
53
    /*GILLT_s32*//*Label 276*/ 8646,
3699
53
    /*GILLT_s64*//*Label 277*/ 8758,
3700
53
    // Label 275: @8534
3701
53
    GIM_Try, /*On fail goto*//*Label 279*/ 8645,
3702
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3703
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3704
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3705
53
      GIM_Try, /*On fail goto*//*Label 280*/ 8596, // Rule ID 354 //
3706
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3707
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3708
53
        // (fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3709
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
3710
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3711
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3712
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3713
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3714
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3715
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3716
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3717
53
        GIR_EraseFromParent, /*InsnID*/0,
3718
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3719
53
        // GIR_Coverage, 354,
3720
53
        GIR_Done,
3721
53
      // Label 280: @8596
3722
53
      GIM_Try, /*On fail goto*//*Label 281*/ 8644, // Rule ID 1758 //
3723
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3724
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3725
53
        // (fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3726
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
3727
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3728
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3729
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3730
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3731
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3732
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3733
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3734
53
        GIR_EraseFromParent, /*InsnID*/0,
3735
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3736
53
        // GIR_Coverage, 1758,
3737
53
        GIR_Done,
3738
53
      // Label 281: @8644
3739
53
      GIM_Reject,
3740
53
    // Label 279: @8645
3741
53
    GIM_Reject,
3742
53
    // Label 276: @8646
3743
53
    GIM_Try, /*On fail goto*//*Label 282*/ 8757,
3744
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3745
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3746
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3747
53
      GIM_Try, /*On fail goto*//*Label 283*/ 8708, // Rule ID 332 //
3748
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3749
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3750
53
        // (fmul:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3751
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
3752
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3753
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3754
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3755
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3756
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3757
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3758
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3759
53
        GIR_EraseFromParent, /*InsnID*/0,
3760
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3761
53
        // GIR_Coverage, 332,
3762
53
        GIR_Done,
3763
53
      // Label 283: @8708
3764
53
      GIM_Try, /*On fail goto*//*Label 284*/ 8756, // Rule ID 1754 //
3765
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3766
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3767
53
        // (fmul:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3768
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
3769
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3770
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3771
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3772
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3773
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3774
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3775
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3776
53
        GIR_EraseFromParent, /*InsnID*/0,
3777
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3778
53
        // GIR_Coverage, 1754,
3779
53
        GIR_Done,
3780
53
      // Label 284: @8756
3781
53
      GIM_Reject,
3782
53
    // Label 282: @8757
3783
53
    GIM_Reject,
3784
53
    // Label 277: @8758
3785
53
    GIM_Try, /*On fail goto*//*Label 285*/ 8869,
3786
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3787
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3788
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3789
53
      GIM_Try, /*On fail goto*//*Label 286*/ 8820, // Rule ID 362 //
3790
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3791
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3792
53
        // (fmul:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3793
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
3794
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3795
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3796
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3797
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3798
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3799
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3800
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3801
53
        GIR_EraseFromParent, /*InsnID*/0,
3802
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3803
53
        // GIR_Coverage, 362,
3804
53
        GIR_Done,
3805
53
      // Label 286: @8820
3806
53
      GIM_Try, /*On fail goto*//*Label 287*/ 8868, // Rule ID 1762 //
3807
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3808
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3809
53
        // (fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3810
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
3811
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3812
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3813
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3814
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3815
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3816
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3817
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3818
53
        GIR_EraseFromParent, /*InsnID*/0,
3819
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3820
53
        // GIR_Coverage, 1762,
3821
53
        GIR_Done,
3822
53
      // Label 287: @8868
3823
53
      GIM_Reject,
3824
53
    // Label 285: @8869
3825
53
    GIM_Reject,
3826
53
    // Label 278: @8870
3827
53
    GIM_Reject,
3828
53
    // Label 18: @8871
3829
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 291*/ 9114,
3830
53
    /*GILLT_s16*//*Label 288*/ 8880,
3831
53
    /*GILLT_s32*//*Label 289*/ 8958,
3832
53
    /*GILLT_s64*//*Label 290*/ 9036,
3833
53
    // Label 288: @8880
3834
53
    GIM_Try, /*On fail goto*//*Label 292*/ 8957, // Rule ID 395 //
3835
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3836
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3837
53
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
3838
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3839
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3840
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3841
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3842
53
      // (fma:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F16:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3843
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F16,
3844
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3845
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3846
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3847
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3848
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3849
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3850
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3851
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3852
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3853
53
      GIR_EraseFromParent, /*InsnID*/0,
3854
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3855
53
      // GIR_Coverage, 395,
3856
53
      GIR_Done,
3857
53
    // Label 292: @8957
3858
53
    GIM_Reject,
3859
53
    // Label 289: @8958
3860
53
    GIM_Try, /*On fail goto*//*Label 293*/ 9035, // Rule ID 358 //
3861
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3862
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3863
53
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
3864
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3865
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3866
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3867
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3868
53
      // (fma:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3869
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F32,
3870
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3871
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3872
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3873
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3874
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3875
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3876
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3877
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3878
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3879
53
      GIR_EraseFromParent, /*InsnID*/0,
3880
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3881
53
      // GIR_Coverage, 358,
3882
53
      GIR_Done,
3883
53
    // Label 293: @9035
3884
53
    GIM_Reject,
3885
53
    // Label 290: @9036
3886
53
    GIM_Try, /*On fail goto*//*Label 294*/ 9113, // Rule ID 360 //
3887
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3888
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3889
53
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
3890
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3891
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3892
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3893
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3894
53
      // (fma:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3895
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F64,
3896
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3897
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3898
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3899
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3900
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3901
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3902
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3903
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3904
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3905
53
      GIR_EraseFromParent, /*InsnID*/0,
3906
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3907
53
      // GIR_Coverage, 360,
3908
53
      GIR_Done,
3909
53
    // Label 294: @9113
3910
53
    GIM_Reject,
3911
53
    // Label 291: @9114
3912
53
    GIM_Reject,
3913
53
    // Label 19: @9115
3914
53
    GIM_Try, /*On fail goto*//*Label 295*/ 9187, // Rule ID 1530 //
3915
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3916
53
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3917
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3918
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3919
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3920
53
      // (fpow:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)  =>  (V_EXP_F32_e32:{ *:[f32] } (V_MUL_LEGACY_F32_e32:{ *:[i16] } f32:{ *:[f32] }:$src1, (V_LOG_F32_e32:{ *:[i16] } f32:{ *:[f32] }:$src0)))
3921
53
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
3922
53
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
3923
53
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/AMDGPU::V_LOG_F32_e32,
3924
53
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3925
53
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src0
3926
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3927
53
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_MUL_LEGACY_F32_e32,
3928
53
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3929
53
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src1
3930
53
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3931
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3932
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e32,
3933
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3934
53
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3935
53
      GIR_EraseFromParent, /*InsnID*/0,
3936
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3937
53
      // GIR_Coverage, 1530,
3938
53
      GIR_Done,
3939
53
    // Label 295: @9187
3940
53
    GIM_Reject,
3941
53
    // Label 20: @9188
3942
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 298*/ 9284,
3943
53
    /*GILLT_s16*//*Label 296*/ 9196,
3944
53
    /*GILLT_s32*//*Label 297*/ 9240,
3945
53
    // Label 296: @9196
3946
53
    GIM_Try, /*On fail goto*//*Label 299*/ 9239, // Rule ID 319 //
3947
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3948
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3949
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3950
53
      // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3951
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F16_e64,
3952
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3953
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3954
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3955
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3956
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3957
53
      GIR_EraseFromParent, /*InsnID*/0,
3958
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3959
53
      // GIR_Coverage, 319,
3960
53
      GIR_Done,
3961
53
    // Label 299: @9239
3962
53
    GIM_Reject,
3963
53
    // Label 297: @9240
3964
53
    GIM_Try, /*On fail goto*//*Label 300*/ 9283, // Rule ID 286 //
3965
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3966
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3967
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3968
53
      // (fexp2:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3969
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e64,
3970
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3971
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3972
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3973
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3974
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3975
53
      GIR_EraseFromParent, /*InsnID*/0,
3976
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3977
53
      // GIR_Coverage, 286,
3978
53
      GIR_Done,
3979
53
    // Label 300: @9283
3980
53
    GIM_Reject,
3981
53
    // Label 298: @9284
3982
53
    GIM_Reject,
3983
53
    // Label 21: @9285
3984
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 303*/ 9381,
3985
53
    /*GILLT_s16*//*Label 301*/ 9293,
3986
53
    /*GILLT_s32*//*Label 302*/ 9337,
3987
53
    // Label 301: @9293
3988
53
    GIM_Try, /*On fail goto*//*Label 304*/ 9336, // Rule ID 318 //
3989
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3990
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3991
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3992
53
      // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3993
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F16_e64,
3994
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3995
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3996
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3997
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3998
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3999
53
      GIR_EraseFromParent, /*InsnID*/0,
4000
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4001
53
      // GIR_Coverage, 318,
4002
53
      GIR_Done,
4003
53
    // Label 304: @9336
4004
53
    GIM_Reject,
4005
53
    // Label 302: @9337
4006
53
    GIM_Try, /*On fail goto*//*Label 305*/ 9380, // Rule ID 287 //
4007
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4008
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4009
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4010
53
      // (flog2:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4011
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F32_e64,
4012
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4013
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4014
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4015
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4016
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4017
53
      GIR_EraseFromParent, /*InsnID*/0,
4018
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4019
53
      // GIR_Coverage, 287,
4020
53
      GIR_Done,
4021
53
    // Label 305: @9380
4022
53
    GIM_Reject,
4023
53
    // Label 303: @9381
4024
53
    GIM_Reject,
4025
53
    // Label 22: @9382
4026
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 308*/ 9478,
4027
53
    /*GILLT_s32*//*Label 306*/ 9390,
4028
53
    /*GILLT_s64*//*Label 307*/ 9434,
4029
53
    // Label 306: @9390
4030
53
    GIM_Try, /*On fail goto*//*Label 309*/ 9433, // Rule ID 270 //
4031
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4032
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4033
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4034
53
      // (fpextend:{ *:[f32] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4035
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F16_e64,
4036
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4037
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4038
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4039
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4040
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4041
53
      GIR_EraseFromParent, /*InsnID*/0,
4042
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4043
53
      // GIR_Coverage, 270,
4044
53
      GIR_Done,
4045
53
    // Label 309: @9433
4046
53
    GIM_Reject,
4047
53
    // Label 307: @9434
4048
53
    GIM_Try, /*On fail goto*//*Label 310*/ 9477, // Rule ID 274 //
4049
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4050
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4051
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4052
53
      // (fpextend:{ *:[f64] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_F32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4053
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_F32_e64,
4054
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4055
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4056
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4057
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4058
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4059
53
      GIR_EraseFromParent, /*InsnID*/0,
4060
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4061
53
      // GIR_Coverage, 274,
4062
53
      GIR_Done,
4063
53
    // Label 310: @9477
4064
53
    GIM_Reject,
4065
53
    // Label 308: @9478
4066
53
    GIM_Reject,
4067
53
    // Label 23: @9479
4068
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 313*/ 9575,
4069
53
    /*GILLT_s16*//*Label 311*/ 9487,
4070
53
    /*GILLT_s32*//*Label 312*/ 9531,
4071
53
    // Label 311: @9487
4072
53
    GIM_Try, /*On fail goto*//*Label 314*/ 9530, // Rule ID 269 //
4073
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4074
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4075
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4076
53
      // (fpround:{ *:[f16] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_F32_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4077
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_F32_e64,
4078
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4079
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4080
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4081
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4082
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4083
53
      GIR_EraseFromParent, /*InsnID*/0,
4084
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4085
53
      // GIR_Coverage, 269,
4086
53
      GIR_Done,
4087
53
    // Label 314: @9530
4088
53
    GIM_Reject,
4089
53
    // Label 312: @9531
4090
53
    GIM_Try, /*On fail goto*//*Label 315*/ 9574, // Rule ID 273 //
4091
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4092
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4093
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4094
53
      // (fpround:{ *:[f32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F64_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4095
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F64_e64,
4096
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4097
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4098
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4099
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4100
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4101
53
      GIR_EraseFromParent, /*InsnID*/0,
4102
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4103
53
      // GIR_Coverage, 273,
4104
53
      GIR_Done,
4105
53
    // Label 315: @9574
4106
53
    GIM_Reject,
4107
53
    // Label 313: @9575
4108
53
    GIM_Reject,
4109
53
    // Label 24: @9576
4110
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 319*/ 9809,
4111
53
    /*GILLT_s1*//*Label 316*/ 9585,
4112
53
    /*GILLT_s16*//*Label 317*/ 9678,
4113
53
    /*GILLT_s32*//*Label 318*/ 9722,
4114
53
    // Label 316: @9585
4115
53
    GIM_Try, /*On fail goto*//*Label 320*/ 9631, // Rule ID 1572 //
4116
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
4117
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4118
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
4119
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
4120
53
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 3212836864:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
4121
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
4122
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
4123
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4124
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/3212836864,
4125
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4126
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4127
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4128
53
      GIR_EraseFromParent, /*InsnID*/0,
4129
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4130
53
      // GIR_Coverage, 1572,
4131
53
      GIR_Done,
4132
53
    // Label 320: @9631
4133
53
    GIM_Try, /*On fail goto*//*Label 321*/ 9677, // Rule ID 1574 //
4134
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
4135
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4136
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
4137
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
4138
53
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, -4616189618054758400:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
4139
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
4140
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
4141
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4142
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/-4616189618054758400,
4143
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4144
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4145
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4146
53
      GIR_EraseFromParent, /*InsnID*/0,
4147
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4148
53
      // GIR_Coverage, 1574,
4149
53
      GIR_Done,
4150
53
    // Label 321: @9677
4151
53
    GIM_Reject,
4152
53
    // Label 317: @9678
4153
53
    GIM_Try, /*On fail goto*//*Label 322*/ 9721, // Rule ID 314 //
4154
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4155
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4156
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4157
53
      // (fp_to_sint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4158
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I16_F16_e64,
4159
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4160
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4161
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4162
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4163
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4164
53
      GIR_EraseFromParent, /*InsnID*/0,
4165
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4166
53
      // GIR_Coverage, 314,
4167
53
      GIR_Done,
4168
53
    // Label 322: @9721
4169
53
    GIM_Reject,
4170
53
    // Label 318: @9722
4171
53
    GIM_Try, /*On fail goto*//*Label 323*/ 9765, // Rule ID 263 //
4172
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4173
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4174
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4175
53
      // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4176
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F64_e64,
4177
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4178
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4179
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4180
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4181
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4182
53
      GIR_EraseFromParent, /*InsnID*/0,
4183
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4184
53
      // GIR_Coverage, 263,
4185
53
      GIR_Done,
4186
53
    // Label 323: @9765
4187
53
    GIM_Try, /*On fail goto*//*Label 324*/ 9808, // Rule ID 268 //
4188
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4189
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4190
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4191
53
      // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4192
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F32_e64,
4193
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4194
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4195
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4196
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4197
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4198
53
      GIR_EraseFromParent, /*InsnID*/0,
4199
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4200
53
      // GIR_Coverage, 268,
4201
53
      GIR_Done,
4202
53
    // Label 324: @9808
4203
53
    GIM_Reject,
4204
53
    // Label 319: @9809
4205
53
    GIM_Reject,
4206
53
    // Label 25: @9810
4207
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 328*/ 10043,
4208
53
    /*GILLT_s1*//*Label 325*/ 9819,
4209
53
    /*GILLT_s16*//*Label 326*/ 9912,
4210
53
    /*GILLT_s32*//*Label 327*/ 9956,
4211
53
    // Label 325: @9819
4212
53
    GIM_Try, /*On fail goto*//*Label 329*/ 9865, // Rule ID 1571 //
4213
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
4214
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4215
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
4216
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
4217
53
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 1065353216:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
4218
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
4219
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
4220
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4221
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/1065353216,
4222
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4223
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4224
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4225
53
      GIR_EraseFromParent, /*InsnID*/0,
4226
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4227
53
      // GIR_Coverage, 1571,
4228
53
      GIR_Done,
4229
53
    // Label 329: @9865
4230
53
    GIM_Try, /*On fail goto*//*Label 330*/ 9911, // Rule ID 1573 //
4231
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
4232
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4233
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
4234
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
4235
53
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, 4607182418800017408:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
4236
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
4237
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
4238
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4239
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/4607182418800017408,
4240
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4241
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4242
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4243
53
      GIR_EraseFromParent, /*InsnID*/0,
4244
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4245
53
      // GIR_Coverage, 1573,
4246
53
      GIR_Done,
4247
53
    // Label 330: @9911
4248
53
    GIM_Reject,
4249
53
    // Label 326: @9912
4250
53
    GIM_Try, /*On fail goto*//*Label 331*/ 9955, // Rule ID 313 //
4251
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4252
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4253
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4254
53
      // (fp_to_uint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4255
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U16_F16_e64,
4256
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4257
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4258
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4259
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4260
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4261
53
      GIR_EraseFromParent, /*InsnID*/0,
4262
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4263
53
      // GIR_Coverage, 313,
4264
53
      GIR_Done,
4265
53
    // Label 331: @9955
4266
53
    GIM_Reject,
4267
53
    // Label 327: @9956
4268
53
    GIM_Try, /*On fail goto*//*Label 332*/ 9999, // Rule ID 267 //
4269
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4270
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4271
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4272
53
      // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4273
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F32_e64,
4274
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4275
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4276
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4277
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4278
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4279
53
      GIR_EraseFromParent, /*InsnID*/0,
4280
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4281
53
      // GIR_Coverage, 267,
4282
53
      GIR_Done,
4283
53
    // Label 332: @9999
4284
53
    GIM_Try, /*On fail goto*//*Label 333*/ 10042, // Rule ID 279 //
4285
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4286
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4287
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4288
53
      // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4289
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F64_e64,
4290
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4291
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4292
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4293
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4294
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4295
53
      GIR_EraseFromParent, /*InsnID*/0,
4296
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4297
53
      // GIR_Coverage, 279,
4298
53
      GIR_Done,
4299
53
    // Label 333: @10042
4300
53
    GIM_Reject,
4301
53
    // Label 328: @10043
4302
53
    GIM_Reject,
4303
53
    // Label 26: @10044
4304
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 337*/ 10173,
4305
53
    /*GILLT_s16*//*Label 334*/ 10053,
4306
53
    /*GILLT_s32*//*Label 335*/ 10093,
4307
53
    /*GILLT_s64*//*Label 336*/ 10133,
4308
53
    // Label 334: @10053
4309
53
    GIM_Try, /*On fail goto*//*Label 338*/ 10092, // Rule ID 312 //
4310
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4311
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4312
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4313
53
      // (sint_to_fp:{ *:[f16] } (VOP3OMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_I16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4314
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_I16_e64,
4315
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4316
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4317
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4318
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4319
53
      GIR_EraseFromParent, /*InsnID*/0,
4320
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4321
53
      // GIR_Coverage, 312,
4322
53
      GIR_Done,
4323
53
    // Label 338: @10092
4324
53
    GIM_Reject,
4325
53
    // Label 335: @10093
4326
53
    GIM_Try, /*On fail goto*//*Label 339*/ 10132, // Rule ID 265 //
4327
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4328
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4329
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4330
53
      // (sint_to_fp:{ *:[f32] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_I32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4331
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_I32_e64,
4332
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4333
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4334
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4335
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4336
53
      GIR_EraseFromParent, /*InsnID*/0,
4337
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4338
53
      // GIR_Coverage, 265,
4339
53
      GIR_Done,
4340
53
    // Label 339: @10132
4341
53
    GIM_Reject,
4342
53
    // Label 336: @10133
4343
53
    GIM_Try, /*On fail goto*//*Label 340*/ 10172, // Rule ID 264 //
4344
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4345
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4346
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4347
53
      // (sint_to_fp:{ *:[f64] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_I32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4348
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_I32_e64,
4349
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4350
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4351
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4352
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4353
53
      GIR_EraseFromParent, /*InsnID*/0,
4354
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4355
53
      // GIR_Coverage, 264,
4356
53
      GIR_Done,
4357
53
    // Label 340: @10172
4358
53
    GIM_Reject,
4359
53
    // Label 337: @10173
4360
53
    GIM_Reject,
4361
53
    // Label 27: @10174
4362
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 344*/ 10303,
4363
53
    /*GILLT_s16*//*Label 341*/ 10183,
4364
53
    /*GILLT_s32*//*Label 342*/ 10223,
4365
53
    /*GILLT_s64*//*Label 343*/ 10263,
4366
53
    // Label 341: @10183
4367
53
    GIM_Try, /*On fail goto*//*Label 345*/ 10222, // Rule ID 311 //
4368
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4369
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4370
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4371
53
      // (uint_to_fp:{ *:[f16] } (VOP3OMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_U16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4372
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_U16_e64,
4373
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4374
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4375
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4376
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4377
53
      GIR_EraseFromParent, /*InsnID*/0,
4378
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4379
53
      // GIR_Coverage, 311,
4380
53
      GIR_Done,
4381
53
    // Label 345: @10222
4382
53
    GIM_Reject,
4383
53
    // Label 342: @10223
4384
53
    GIM_Try, /*On fail goto*//*Label 346*/ 10262, // Rule ID 266 //
4385
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4386
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4387
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4388
53
      // (uint_to_fp:{ *:[f32] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_U32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4389
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_U32_e64,
4390
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4391
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4392
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4393
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4394
53
      GIR_EraseFromParent, /*InsnID*/0,
4395
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4396
53
      // GIR_Coverage, 266,
4397
53
      GIR_Done,
4398
53
    // Label 346: @10262
4399
53
    GIM_Reject,
4400
53
    // Label 343: @10263
4401
53
    GIM_Try, /*On fail goto*//*Label 347*/ 10302, // Rule ID 280 //
4402
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4403
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4404
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4405
53
      // (uint_to_fp:{ *:[f64] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_U32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4406
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_U32_e64,
4407
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4408
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4409
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4410
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4411
53
      GIR_EraseFromParent, /*InsnID*/0,
4412
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4413
53
      // GIR_Coverage, 280,
4414
53
      GIR_Done,
4415
53
    // Label 347: @10302
4416
53
    GIM_Reject,
4417
53
    // Label 344: @10303
4418
53
    GIM_Reject,
4419
53
    // Label 28: @10304
4420
53
    GIM_Try, /*On fail goto*//*Label 348*/ 10318, // Rule ID 480 //
4421
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
4422
53
      // MIs[0] simm16
4423
53
      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
4424
53
      // (br (bb:{ *:[Other] }):$simm16)  =>  (S_BRANCH (bb:{ *:[Other] }):$simm16)
4425
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_BRANCH,
4426
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4427
53
      // GIR_Coverage, 480,
4428
53
      GIR_Done,
4429
53
    // Label 348: @10318
4430
53
    GIM_Reject,
4431
53
    // Label 29: @10319
4432
53
    GIM_Reject,
4433
53
    };
4434
53
  return MatchTable0;
4435
53
}
4436
#endif // ifdef GET_GLOBALISEL_IMPL
4437
#ifdef GET_GLOBALISEL_PREDICATES_DECL
4438
PredicateBitset AvailableModuleFeatures;
4439
mutable PredicateBitset AvailableFunctionFeatures;
4440
53
PredicateBitset getAvailableFeatures() const {
4441
53
  return AvailableModuleFeatures | AvailableFunctionFeatures;
4442
53
}
4443
PredicateBitset
4444
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const;
4445
PredicateBitset
4446
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget,
4447
                                 const MachineFunction *MF) const;
4448
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
4449
#ifdef GET_GLOBALISEL_PREDICATES_INIT
4450
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
4451
AvailableFunctionFeatures()
4452
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT