Coverage Report

Created: 2018-09-23 22:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the AMDGPU target                          *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 33;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(AMDGPUInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(AMDGPUInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static AMDGPUInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static AMDGPUInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(3),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_isSICIBit = 3,
37
  Feature_isVIBit = 2,
38
  Feature_isGFX9Bit = 6,
39
  Feature_isCIVIBit = 7,
40
  Feature_HasFlatAddressSpaceBit = 8,
41
  Feature_HasFlatGlobalInstsBit = 9,
42
  Feature_HasUnpackedD16VMemBit = 21,
43
  Feature_HasPackedD16VMemBit = 22,
44
  Feature_D16PreservesUnusedBitsBit = 20,
45
  Feature_LDSRequiresM0InitBit = 31,
46
  Feature_NotLDSRequiresM0InitBit = 32,
47
  Feature_HasAddNoCarryInstsBit = 14,
48
  Feature_Has16BitInstsBit = 4,
49
  Feature_HasVOP3PInstsBit = 24,
50
  Feature_HasMadMixInstsBit = 15,
51
  Feature_has16BankLDSBit = 12,
52
  Feature_has32BankLDSBit = 11,
53
  Feature_HasFmaMixInstsBit = 16,
54
  Feature_HasDLInstsBit = 17,
55
  Feature_EnableLateCFGStructurizeBit = 13,
56
  Feature_TruePredicateBit = 0,
57
  Feature_FP16DenormalsBit = 26,
58
  Feature_FP32DenormalsBit = 28,
59
  Feature_FP64DenormalsBit = 30,
60
  Feature_NoFP16DenormalsBit = 25,
61
  Feature_NoFP32DenormalsBit = 27,
62
  Feature_NoFP64DenormalsBit = 29,
63
  Feature_UnsafeFPMathBit = 23,
64
  Feature_isCIBit = 19,
65
  Feature_isCIOnlyBit = 18,
66
  Feature_isVIOnlyBit = 5,
67
  Feature_isGCNBit = 1,
68
  Feature_isSIBit = 10,
69
};
70
71
PredicateBitset AMDGPUInstructionSelector::
72
2.42k
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const {
73
2.42k
  PredicateBitset Features;
74
2.42k
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||
Subtarget->getGeneration() == 1.43k
AMDGPUSubtarget1.43k
::SEA_ISLANDS)
75
1.21k
    Features[Feature_isSICIBit] = 1;
76
2.42k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
77
1.20k
    Features[Feature_isVIBit] = 1;
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2.42k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9)
79
312
    Features[Feature_isGFX9Bit] = 1;
80
2.42k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
81
1.43k
    Features[Feature_isCIVIBit] = 1;
82
2.42k
  if (Subtarget->hasFlatAddressSpace())
83
1.58k
    Features[Feature_HasFlatAddressSpaceBit] = 1;
84
2.42k
  if (Subtarget->hasFlatGlobalInsts())
85
312
    Features[Feature_HasFlatGlobalInstsBit] = 1;
86
2.42k
  if (Subtarget->hasUnpackedD16VMem())
87
870
    Features[Feature_HasUnpackedD16VMemBit] = 1;
88
2.42k
  if (!Subtarget->hasUnpackedD16VMem())
89
1.55k
    Features[Feature_HasPackedD16VMemBit] = 1;
90
2.42k
  if (Subtarget->d16PreservesUnusedBits())
91
287
    Features[Feature_D16PreservesUnusedBitsBit] = 1;
92
2.42k
  if (Subtarget->ldsRequiresM0Init())
93
2.11k
    Features[Feature_LDSRequiresM0InitBit] = 1;
94
2.42k
  if (!Subtarget->ldsRequiresM0Init())
95
312
    Features[Feature_NotLDSRequiresM0InitBit] = 1;
96
2.42k
  if (Subtarget->hasAddNoCarry())
97
312
    Features[Feature_HasAddNoCarryInstsBit] = 1;
98
2.42k
  if (Subtarget->has16BitInsts())
99
1.20k
    Features[Feature_Has16BitInstsBit] = 1;
100
2.42k
  if (Subtarget->hasVOP3PInsts())
101
312
    Features[Feature_HasVOP3PInstsBit] = 1;
102
2.42k
  if (Subtarget->hasMadMixInsts())
103
285
    Features[Feature_HasMadMixInstsBit] = 1;
104
2.42k
  if (Subtarget->getLDSBankCount() == 16)
105
27
    Features[Feature_has16BankLDSBit] = 1;
106
2.42k
  if (Subtarget->getLDSBankCount() == 32)
107
2.39k
    Features[Feature_has32BankLDSBit] = 1;
108
2.42k
  if (Subtarget->hasFmaMixInsts())
109
27
    Features[Feature_HasFmaMixInstsBit] = 1;
110
2.42k
  if (Subtarget->hasDLInsts())
111
25
    Features[Feature_HasDLInstsBit] = 1;
112
2.42k
  if (EnableLateStructurizeCFG)
113
0
    Features[Feature_EnableLateCFGStructurizeBit] = 1;
114
2.42k
  if (true)
115
2.42k
    Features[Feature_TruePredicateBit] = 1;
116
2.42k
  if (Subtarget->hasFP16Denormals())
117
2.38k
    Features[Feature_FP16DenormalsBit] = 1;
118
2.42k
  if (Subtarget->hasFP32Denormals())
119
61
    Features[Feature_FP32DenormalsBit] = 1;
120
2.42k
  if (Subtarget->hasFP64Denormals())
121
2.38k
    Features[Feature_FP64DenormalsBit] = 1;
122
2.42k
  if (!Subtarget->hasFP16Denormals())
123
39
    Features[Feature_NoFP16DenormalsBit] = 1;
124
2.42k
  if (!Subtarget->hasFP32Denormals())
125
2.36k
    Features[Feature_NoFP32DenormalsBit] = 1;
126
2.42k
  if (!Subtarget->hasFP64Denormals())
127
39
    Features[Feature_NoFP64DenormalsBit] = 1;
128
2.42k
  if (TM.Options.UnsafeFPMath)
129
36
    Features[Feature_UnsafeFPMathBit] = 1;
130
2.42k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
131
1.43k
    Features[Feature_isCIBit] = 1;
132
2.42k
  if (Subtarget->getGeneration() ==AMDGPUSubtarget::SEA_ISLANDS)
133
231
    Features[Feature_isCIOnlyBit] = 1;
134
2.42k
  if (Subtarget->getGeneration() ==AMDGPUSubtarget::VOLCANIC_ISLANDS)
135
892
    Features[Feature_isVIOnlyBit] = 1;
136
2.42k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
137
2.42k
    Features[Feature_isGCNBit] = 1;
138
2.42k
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
139
988
    Features[Feature_isSIBit] = 1;
140
2.42k
  return Features;
141
2.42k
}
142
143
PredicateBitset AMDGPUInstructionSelector::
144
53
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget, const MachineFunction *MF) const {
145
53
  PredicateBitset Features;
146
53
  return Features;
147
53
}
148
149
// LLT Objects.
150
enum {
151
  GILLT_s1,
152
  GILLT_s16,
153
  GILLT_s32,
154
  GILLT_s64,
155
  GILLT_v2s16,
156
  GILLT_v2s32,
157
  GILLT_v2s64,
158
  GILLT_v4s16,
159
  GILLT_v4s32,
160
  GILLT_v8s32,
161
  GILLT_v16s32,
162
};
163
const static size_t NumTypeObjects = 11;
164
const static LLT TypeObjects[] = {
165
  LLT::scalar(1),
166
  LLT::scalar(16),
167
  LLT::scalar(32),
168
  LLT::scalar(64),
169
  LLT::vector(2, 16),
170
  LLT::vector(2, 32),
171
  LLT::vector(2, 64),
172
  LLT::vector(4, 16),
173
  LLT::vector(4, 32),
174
  LLT::vector(8, 32),
175
  LLT::vector(16, 32),
176
};
177
178
// Feature bitsets.
179
enum {
180
  GIFBS_Invalid,
181
  GIFBS_Has16BitInsts,
182
  GIFBS_isGCN,
183
  GIFBS_isSICI,
184
  GIFBS_TruePredicate_isCIVI,
185
  GIFBS_TruePredicate_isGCN,
186
  GIFBS_TruePredicate_isSI,
187
  GIFBS_TruePredicate_isSICI,
188
  GIFBS_TruePredicate_isVI,
189
};
190
const static PredicateBitset FeatureBitsets[] {
191
  {}, // GIFBS_Invalid
192
  {Feature_Has16BitInstsBit, },
193
  {Feature_isGCNBit, },
194
  {Feature_isSICIBit, },
195
  {Feature_TruePredicateBit, Feature_isCIVIBit, },
196
  {Feature_TruePredicateBit, Feature_isGCNBit, },
197
  {Feature_TruePredicateBit, Feature_isSIBit, },
198
  {Feature_TruePredicateBit, Feature_isSICIBit, },
199
  {Feature_TruePredicateBit, Feature_isVIBit, },
200
};
201
202
// ComplexPattern predicates.
203
enum {
204
  GICP_Invalid,
205
  GICP_gi_vcsrc,
206
  GICP_gi_vop3mods,
207
  GICP_gi_vop3mods0,
208
  GICP_gi_vop3omods,
209
  GICP_gi_vsrc0,
210
};
211
// See constructor for table contents
212
213
// PatFrag predicates.
214
enum {
215
  GIPFP_I64_Predicate_NegSubInlineConst16 = GIPFP_I64_Invalid + 1,
216
  GIPFP_I64_Predicate_NegSubInlineConst32,
217
};
218
0
bool AMDGPUInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
219
0
  switch (PredicateID) {
220
0
  case GIPFP_I64_Predicate_NegSubInlineConst16: {
221
0
    
222
0
  return Imm < -16 && Imm >= -64;
223
0
224
0
    llvm_unreachable("ImmediateCode should have returned");
225
0
    return false;
226
0
  }
227
0
  case GIPFP_I64_Predicate_NegSubInlineConst32: {
228
0
    
229
0
  return Imm < -16 && Imm >= -64;
230
0
231
0
    llvm_unreachable("ImmediateCode should have returned");
232
0
    return false;
233
0
  }
234
0
  }
235
0
  llvm_unreachable("Unknown predicate");
236
0
  return false;
237
0
}
238
0
bool AMDGPUInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
239
0
  llvm_unreachable("Unknown predicate");
240
0
  return false;
241
0
}
242
0
bool AMDGPUInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
243
0
  llvm_unreachable("Unknown predicate");
244
0
  return false;
245
0
}
246
0
bool AMDGPUInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
247
0
  const MachineFunction &MF = *MI.getParent()->getParent();
248
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
249
0
  (void)MRI;
250
0
  llvm_unreachable("Unknown predicate");
251
0
  return false;
252
0
}
253
254
AMDGPUInstructionSelector::ComplexMatcherMemFn
255
AMDGPUInstructionSelector::ComplexPredicateFns[] = {
256
  nullptr, // GICP_Invalid
257
  &AMDGPUInstructionSelector::selectVCSRC, // gi_vcsrc
258
  &AMDGPUInstructionSelector::selectVOP3Mods, // gi_vop3mods
259
  &AMDGPUInstructionSelector::selectVOP3Mods0, // gi_vop3mods0
260
  &AMDGPUInstructionSelector::selectVOP3OMods, // gi_vop3omods
261
  &AMDGPUInstructionSelector::selectVSRC0, // gi_vsrc0
262
};
263
264
// Custom renderers.
265
enum {
266
  GICR_Invalid,
267
};
268
AMDGPUInstructionSelector::CustomRendererFn
269
AMDGPUInstructionSelector::CustomRenderers[] = {
270
  nullptr, // GICP_Invalid
271
};
272
273
53
bool AMDGPUInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
274
53
  MachineFunction &MF = *I.getParent()->getParent();
275
53
  MachineRegisterInfo &MRI = MF.getRegInfo();
276
53
  // FIXME: This should be computed on a per-function basis rather than per-insn.
277
53
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
278
53
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
279
53
  NewMIVector OutMIs;
280
53
  State.MIs.clear();
281
53
  State.MIs.push_back(&I);
282
53
283
53
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
284
53
    return true;
285
53
  }
286
0
287
0
  return false;
288
0
}
289
290
53
const int64_t *AMDGPUInstructionSelector::getMatchTable() const {
291
53
  constexpr static int64_t MatchTable0[] = {
292
53
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 134, /*)*//*default:*//*Label 28*/ 9869,
293
53
    /*TargetOpcode::G_ADD*//*Label 0*/ 105,
294
53
    /*TargetOpcode::G_SUB*//*Label 1*/ 302,
295
53
    /*TargetOpcode::G_MUL*//*Label 2*/ 333, 0, 0, 0, 0,
296
53
    /*TargetOpcode::G_AND*//*Label 3*/ 361,
297
53
    /*TargetOpcode::G_OR*//*Label 4*/ 392,
298
53
    /*TargetOpcode::G_XOR*//*Label 5*/ 2141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
299
53
    /*TargetOpcode::G_BITCAST*//*Label 6*/ 2245, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
300
53
    /*TargetOpcode::G_INTRINSIC*//*Label 7*/ 4387,
301
53
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 8*/ 6875, 0, 0,
302
53
    /*TargetOpcode::G_CONSTANT*//*Label 9*/ 7174, 0, 0, 0, 0, 0,
303
53
    /*TargetOpcode::G_SHL*//*Label 10*/ 7231,
304
53
    /*TargetOpcode::G_LSHR*//*Label 11*/ 7294,
305
53
    /*TargetOpcode::G_ASHR*//*Label 12*/ 7357, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
306
53
    /*TargetOpcode::G_FADD*//*Label 13*/ 7561,
307
53
    /*TargetOpcode::G_FSUB*//*Label 14*/ 7911,
308
53
    /*TargetOpcode::G_FMUL*//*Label 15*/ 8044,
309
53
    /*TargetOpcode::G_FMA*//*Label 16*/ 8394, 0, 0,
310
53
    /*TargetOpcode::G_FPOW*//*Label 17*/ 8638, 0,
311
53
    /*TargetOpcode::G_FEXP2*//*Label 18*/ 8711, 0,
312
53
    /*TargetOpcode::G_FLOG2*//*Label 19*/ 8808, 0,
313
53
    /*TargetOpcode::G_FPEXT*//*Label 20*/ 8905,
314
53
    /*TargetOpcode::G_FPTRUNC*//*Label 21*/ 9002,
315
53
    /*TargetOpcode::G_FPTOSI*//*Label 22*/ 9099,
316
53
    /*TargetOpcode::G_FPTOUI*//*Label 23*/ 9333,
317
53
    /*TargetOpcode::G_SITOFP*//*Label 24*/ 9567,
318
53
    /*TargetOpcode::G_UITOFP*//*Label 25*/ 9697, 0, 0, 0,
319
53
    /*TargetOpcode::G_BR*//*Label 26*/ 9827, 0, 0, 0, 0, 0, 0, 0,
320
53
    /*TargetOpcode::G_CTPOP*//*Label 27*/ 9842,
321
53
    // Label 0: @105
322
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 31*/ 301,
323
53
    /*GILLT_s16*//*Label 29*/ 114, 0,
324
53
    /*GILLT_s64*//*Label 30*/ 274,
325
53
    // Label 29: @114
326
53
    GIM_Try, /*On fail goto*//*Label 32*/ 273,
327
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
328
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
329
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
330
53
      GIM_Try, /*On fail goto*//*Label 33*/ 176, // Rule ID 953 //
331
53
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
332
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
333
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
334
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
335
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
336
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
337
53
        // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
338
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
339
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
340
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
341
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
342
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
343
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
344
53
        GIR_EraseFromParent, /*InsnID*/0,
345
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
346
53
        // GIR_Coverage, 953,
347
53
        GIR_Done,
348
53
      // Label 33: @176
349
53
      GIM_Try, /*On fail goto*//*Label 34*/ 224, // Rule ID 954 //
350
53
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
351
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
352
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
353
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
354
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
355
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
356
53
        // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_I16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
357
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_I16,
358
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
359
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
360
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
361
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
362
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
363
53
        GIR_EraseFromParent, /*InsnID*/0,
364
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
365
53
        // GIR_Coverage, 954,
366
53
        GIR_Done,
367
53
      // Label 34: @224
368
53
      GIM_Try, /*On fail goto*//*Label 35*/ 272, // Rule ID 2001 //
369
53
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
370
53
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
371
53
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
372
53
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
373
53
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
374
53
        GIM_CheckIsSafeToFold, /*InsnID*/1,
375
53
        // (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
376
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
377
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
378
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
379
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
380
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
381
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
382
53
        GIR_EraseFromParent, /*InsnID*/0,
383
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
384
53
        // GIR_Coverage, 2001,
385
53
        GIR_Done,
386
53
      // Label 35: @272
387
53
      GIM_Reject,
388
53
    // Label 32: @273
389
53
    GIM_Reject,
390
53
    // Label 30: @274
391
53
    GIM_Try, /*On fail goto*//*Label 36*/ 300, // Rule ID 650 //
392
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
393
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
394
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
395
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
396
53
      // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_ADD_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
397
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ADD_U64_PSEUDO,
398
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
399
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
400
53
      // GIR_Coverage, 650,
401
53
      GIR_Done,
402
53
    // Label 36: @300
403
53
    GIM_Reject,
404
53
    // Label 31: @301
405
53
    GIM_Reject,
406
53
    // Label 1: @302
407
53
    GIM_Try, /*On fail goto*//*Label 37*/ 332, // Rule ID 651 //
408
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
409
53
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
410
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
411
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
412
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
413
53
      // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_SUB_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
414
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_SUB_U64_PSEUDO,
415
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
416
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
417
53
      // GIR_Coverage, 651,
418
53
      GIR_Done,
419
53
    // Label 37: @332
420
53
    GIM_Reject,
421
53
    // Label 2: @333
422
53
    GIM_Try, /*On fail goto*//*Label 38*/ 360, // Rule ID 35 //
423
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
424
53
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
425
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
426
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
427
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
428
53
      // (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_MUL_I32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
429
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_MUL_I32,
430
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
431
53
      // GIR_Coverage, 35,
432
53
      GIR_Done,
433
53
    // Label 38: @360
434
53
    GIM_Reject,
435
53
    // Label 3: @361
436
53
    GIM_Try, /*On fail goto*//*Label 39*/ 391, // Rule ID 411 //
437
53
      GIM_CheckFeatures, GIFBS_isGCN,
438
53
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
439
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
440
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
441
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
442
53
      // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_AND_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
443
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_AND_B32_e64,
444
53
      GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
445
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
446
53
      // GIR_Coverage, 411,
447
53
      GIR_Done,
448
53
    // Label 39: @391
449
53
    GIM_Reject,
450
53
    // Label 4: @392
451
53
    GIM_Try, /*On fail goto*//*Label 40*/ 2140,
452
53
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
453
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
454
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
455
53
      GIM_Try, /*On fail goto*//*Label 41*/ 2095,
456
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
457
53
        GIM_Try, /*On fail goto*//*Label 42*/ 513, // Rule ID 1978 //
458
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
459
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
460
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
461
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
462
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
463
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
464
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
465
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
466
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
467
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
468
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
469
53
          // MIs[3] x
470
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
471
53
          // MIs[3] z
472
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
473
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
474
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
475
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
476
53
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
477
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
478
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
479
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
480
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
481
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
482
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
483
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
484
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
485
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
486
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
487
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
488
53
          GIR_EraseFromParent, /*InsnID*/0,
489
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
490
53
          // GIR_Coverage, 1978,
491
53
          GIR_Done,
492
53
        // Label 42: @513
493
53
        GIM_Try, /*On fail goto*//*Label 43*/ 614, // Rule ID 1979 //
494
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
495
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
496
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
497
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
498
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
499
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
500
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
501
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
502
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
503
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
504
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
505
53
          // MIs[3] z
506
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
507
53
          // MIs[3] x
508
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
509
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
510
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
511
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
512
53
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
513
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
514
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
515
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
516
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
517
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
518
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
519
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
520
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
521
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
522
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
523
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
524
53
          GIR_EraseFromParent, /*InsnID*/0,
525
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
526
53
          // GIR_Coverage, 1979,
527
53
          GIR_Done,
528
53
        // Label 43: @614
529
53
        GIM_Try, /*On fail goto*//*Label 44*/ 715, // Rule ID 1980 //
530
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
531
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
532
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
533
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
534
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
535
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
536
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
537
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
538
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
539
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
540
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
541
53
          // MIs[3] x
542
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
543
53
          // MIs[3] z
544
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
545
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
546
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
547
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
548
53
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
549
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
550
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
551
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
552
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
553
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
554
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
555
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
556
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
557
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
558
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
559
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
560
53
          GIR_EraseFromParent, /*InsnID*/0,
561
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
562
53
          // GIR_Coverage, 1980,
563
53
          GIR_Done,
564
53
        // Label 44: @715
565
53
        GIM_Try, /*On fail goto*//*Label 45*/ 816, // Rule ID 1981 //
566
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
567
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
568
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
569
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
570
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
571
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
572
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
573
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
574
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
575
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
576
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
577
53
          // MIs[3] z
578
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
579
53
          // MIs[3] x
580
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
581
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
582
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
583
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
584
53
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
585
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
586
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
587
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
588
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
589
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
590
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
591
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
592
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
593
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
594
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
595
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
596
53
          GIR_EraseFromParent, /*InsnID*/0,
597
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
598
53
          // GIR_Coverage, 1981,
599
53
          GIR_Done,
600
53
        // Label 45: @816
601
53
        GIM_Try, /*On fail goto*//*Label 46*/ 917, // Rule ID 1974 //
602
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
603
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
604
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
605
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
606
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
607
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
608
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
609
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
610
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
611
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
612
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
613
53
          // MIs[3] x
614
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
615
53
          // MIs[3] z
616
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
617
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
618
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
619
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
620
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
621
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
622
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
623
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
624
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
625
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
626
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
627
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
628
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
629
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
630
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
631
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
632
53
          GIR_EraseFromParent, /*InsnID*/0,
633
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
634
53
          // GIR_Coverage, 1974,
635
53
          GIR_Done,
636
53
        // Label 46: @917
637
53
        GIM_Try, /*On fail goto*//*Label 47*/ 1018, // Rule ID 1975 //
638
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
639
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
640
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
641
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
642
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
643
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
644
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
645
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
646
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
647
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
648
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
649
53
          // MIs[3] z
650
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
651
53
          // MIs[3] x
652
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
653
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
654
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
655
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
656
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
657
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
658
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
659
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
660
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
661
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
662
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
663
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
664
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
665
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
666
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
667
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
668
53
          GIR_EraseFromParent, /*InsnID*/0,
669
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
670
53
          // GIR_Coverage, 1975,
671
53
          GIR_Done,
672
53
        // Label 47: @1018
673
53
        GIM_Try, /*On fail goto*//*Label 48*/ 1119, // Rule ID 1976 //
674
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
675
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
676
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
677
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
678
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
679
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
680
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
681
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
682
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
683
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
684
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
685
53
          // MIs[3] x
686
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
687
53
          // MIs[3] z
688
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
689
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
690
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
691
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
692
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
693
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
694
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
695
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
696
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
697
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
698
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
699
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
700
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
701
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
702
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
703
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
704
53
          GIR_EraseFromParent, /*InsnID*/0,
705
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
706
53
          // GIR_Coverage, 1976,
707
53
          GIR_Done,
708
53
        // Label 48: @1119
709
53
        GIM_Try, /*On fail goto*//*Label 49*/ 1220, // Rule ID 1977 //
710
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
711
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
712
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
713
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
714
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
715
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
716
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
717
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
718
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
719
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
720
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
721
53
          // MIs[3] z
722
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
723
53
          // MIs[3] x
724
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
725
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
726
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
727
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
728
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
729
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
730
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
731
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
732
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
733
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
734
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
735
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
736
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
737
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
738
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
739
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
740
53
          GIR_EraseFromParent, /*InsnID*/0,
741
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
742
53
          // GIR_Coverage, 1977,
743
53
          GIR_Done,
744
53
        // Label 49: @1220
745
53
        GIM_Try, /*On fail goto*//*Label 50*/ 1321, // Rule ID 1968 //
746
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
747
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
748
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
749
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
750
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
751
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
752
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
753
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
754
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
755
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
756
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
757
53
          // MIs[3] x
758
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
759
53
          // MIs[3] z
760
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
761
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
762
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
763
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
764
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
765
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
766
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
767
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
768
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
769
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
770
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
771
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
772
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
773
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
774
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
775
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
776
53
          GIR_EraseFromParent, /*InsnID*/0,
777
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
778
53
          // GIR_Coverage, 1968,
779
53
          GIR_Done,
780
53
        // Label 50: @1321
781
53
        GIM_Try, /*On fail goto*//*Label 51*/ 1422, // Rule ID 1969 //
782
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
783
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
784
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
785
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
786
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
787
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
788
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
789
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
790
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
791
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
792
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
793
53
          // MIs[3] z
794
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
795
53
          // MIs[3] x
796
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
797
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
798
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
799
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
800
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
801
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
802
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
803
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
804
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
805
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
806
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
807
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
808
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
809
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
810
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
811
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
812
53
          GIR_EraseFromParent, /*InsnID*/0,
813
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
814
53
          // GIR_Coverage, 1969,
815
53
          GIR_Done,
816
53
        // Label 51: @1422
817
53
        GIM_Try, /*On fail goto*//*Label 52*/ 1523, // Rule ID 1972 //
818
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
819
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
820
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
821
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
822
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
823
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
824
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
825
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
826
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
827
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
828
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
829
53
          // MIs[3] x
830
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
831
53
          // MIs[3] z
832
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
833
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
834
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
835
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
836
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
837
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
838
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
839
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
840
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
841
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
842
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
843
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
844
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
845
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
846
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
847
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
848
53
          GIR_EraseFromParent, /*InsnID*/0,
849
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
850
53
          // GIR_Coverage, 1972,
851
53
          GIR_Done,
852
53
        // Label 52: @1523
853
53
        GIM_Try, /*On fail goto*//*Label 53*/ 1624, // Rule ID 1973 //
854
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
855
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
856
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
857
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
858
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
859
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
860
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
861
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
862
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
863
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
864
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
865
53
          // MIs[3] z
866
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
867
53
          // MIs[3] x
868
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
869
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
870
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
871
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
872
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
873
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
874
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
875
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
876
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
877
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
878
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
879
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
880
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
881
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
882
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
883
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
884
53
          GIR_EraseFromParent, /*InsnID*/0,
885
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
886
53
          // GIR_Coverage, 1973,
887
53
          GIR_Done,
888
53
        // Label 53: @1624
889
53
        GIM_Try, /*On fail goto*//*Label 54*/ 1725, // Rule ID 804 //
890
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
891
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
892
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
893
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
894
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
895
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
896
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
897
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
898
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
899
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
900
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
901
53
          // MIs[3] x
902
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
903
53
          // MIs[3] z
904
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
905
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
906
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
907
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
908
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
909
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
910
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
911
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
912
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
913
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
914
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
915
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
916
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
917
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
918
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
919
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
920
53
          GIR_EraseFromParent, /*InsnID*/0,
921
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
922
53
          // GIR_Coverage, 804,
923
53
          GIR_Done,
924
53
        // Label 54: @1725
925
53
        GIM_Try, /*On fail goto*//*Label 55*/ 1826, // Rule ID 1967 //
926
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
927
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
928
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
929
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
930
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
931
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
932
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
933
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
934
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
935
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
936
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
937
53
          // MIs[3] z
938
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
939
53
          // MIs[3] x
940
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
941
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
942
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
943
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
944
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
945
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
946
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
947
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
948
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
949
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
950
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
951
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
952
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
953
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
954
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
955
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
956
53
          GIR_EraseFromParent, /*InsnID*/0,
957
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
958
53
          // GIR_Coverage, 1967,
959
53
          GIR_Done,
960
53
        // Label 55: @1826
961
53
        GIM_Try, /*On fail goto*//*Label 56*/ 1927, // Rule ID 1970 //
962
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
963
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
964
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
965
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
966
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
967
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
968
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
969
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
970
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
971
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
972
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
973
53
          // MIs[3] x
974
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
975
53
          // MIs[3] z
976
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
977
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
978
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
979
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
980
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
981
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
982
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
983
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
984
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
985
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
986
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
987
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
988
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
989
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
990
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
991
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
992
53
          GIR_EraseFromParent, /*InsnID*/0,
993
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
994
53
          // GIR_Coverage, 1970,
995
53
          GIR_Done,
996
53
        // Label 56: @1927
997
53
        GIM_Try, /*On fail goto*//*Label 57*/ 2028, // Rule ID 1971 //
998
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
999
53
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1000
53
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1001
53
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1002
53
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1003
53
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1004
53
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
1005
53
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1006
53
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1007
53
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1008
53
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
1009
53
          // MIs[3] z
1010
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
1011
53
          // MIs[3] x
1012
53
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
1013
53
          GIM_CheckIsSafeToFold, /*InsnID*/1,
1014
53
          GIM_CheckIsSafeToFold, /*InsnID*/2,
1015
53
          GIM_CheckIsSafeToFold, /*InsnID*/3,
1016
53
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
1017
53
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
1018
53
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1019
53
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1020
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
1021
53
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
1022
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1023
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1024
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1025
53
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1026
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
1027
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
1028
53
          GIR_EraseFromParent, /*InsnID*/0,
1029
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1030
53
          // GIR_Coverage, 1971,
1031
53
          GIR_Done,
1032
53
        // Label 57: @2028
1033
53
        GIM_Try, /*On fail goto*//*Label 58*/ 2061, // Rule ID 1904 //
1034
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1035
53
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
1036
53
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vsrc0,
1037
53
          // (or:{ *:[i32] } (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0), VGPR_32:{ *:[i32] }:$src1)  =>  (V_OR_B32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1038
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
1039
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1040
53
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
1041
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1042
53
          GIR_EraseFromParent, /*InsnID*/0,
1043
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1044
53
          // GIR_Coverage, 1904,
1045
53
          GIR_Done,
1046
53
        // Label 58: @2061
1047
53
        GIM_Try, /*On fail goto*//*Label 59*/ 2094, // Rule ID 2391 //
1048
53
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1049
53
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1050
53
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
1051
53
          // (or:{ *:[i32] } VGPR_32:{ *:[i32] }:$src1, (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_OR_B32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1052
53
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
1053
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1054
53
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
1055
53
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1056
53
          GIR_EraseFromParent, /*InsnID*/0,
1057
53
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1058
53
          // GIR_Coverage, 2391,
1059
53
          GIR_Done,
1060
53
        // Label 59: @2094
1061
53
        GIM_Reject,
1062
53
      // Label 41: @2095
1063
53
      GIM_Try, /*On fail goto*//*Label 60*/ 2121, // Rule ID 1903 //
1064
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1065
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1066
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1067
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
1068
53
        // (or:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)  =>  (S_OR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1069
53
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
1070
53
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
1071
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1072
53
        // GIR_Coverage, 1903,
1073
53
        GIR_Done,
1074
53
      // Label 60: @2121
1075
53
      GIM_Try, /*On fail goto*//*Label 61*/ 2139, // Rule ID 413 //
1076
53
        GIM_CheckFeatures, GIFBS_isGCN,
1077
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1078
53
        // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_OR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1079
53
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e64,
1080
53
        GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
1081
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1082
53
        // GIR_Coverage, 413,
1083
53
        GIR_Done,
1084
53
      // Label 61: @2139
1085
53
      GIM_Reject,
1086
53
    // Label 40: @2140
1087
53
    GIM_Reject,
1088
53
    // Label 5: @2141
1089
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 64*/ 2244,
1090
53
    /*GILLT_s32*//*Label 62*/ 2149,
1091
53
    /*GILLT_s64*//*Label 63*/ 2207,
1092
53
    // Label 62: @2149
1093
53
    GIM_Try, /*On fail goto*//*Label 65*/ 2206,
1094
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1095
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1096
53
      GIM_Try, /*On fail goto*//*Label 66*/ 2187, // Rule ID 0 //
1097
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1098
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1099
53
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1100
53
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })  =>  (S_NOT_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
1101
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B32,
1102
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
1103
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1104
53
        GIR_EraseFromParent, /*InsnID*/0,
1105
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1106
53
        // GIR_Coverage, 0,
1107
53
        GIR_Done,
1108
53
      // Label 66: @2187
1109
53
      GIM_Try, /*On fail goto*//*Label 67*/ 2205, // Rule ID 415 //
1110
53
        GIM_CheckFeatures, GIFBS_isGCN,
1111
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1112
53
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_XOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1113
53
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1114
53
        GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
1115
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1116
53
        // GIR_Coverage, 415,
1117
53
        GIR_Done,
1118
53
      // Label 67: @2205
1119
53
      GIM_Reject,
1120
53
    // Label 65: @2206
1121
53
    GIM_Reject,
1122
53
    // Label 63: @2207
1123
53
    GIM_Try, /*On fail goto*//*Label 68*/ 2243, // Rule ID 1 //
1124
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1125
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1126
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1127
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
1128
53
      GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1129
53
      // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, -1:{ *:[i64] })  =>  (S_NOT_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0)
1130
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B64,
1131
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
1132
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1133
53
      GIR_EraseFromParent, /*InsnID*/0,
1134
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1135
53
      // GIR_Coverage, 1,
1136
53
      GIR_Done,
1137
53
    // Label 68: @2243
1138
53
    GIM_Reject,
1139
53
    // Label 64: @2244
1140
53
    GIM_Reject,
1141
53
    // Label 6: @2245
1142
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 79*/ 4386,
1143
53
    /*GILLT_s16*//*Label 69*/ 2261,
1144
53
    /*GILLT_s32*//*Label 70*/ 2389,
1145
53
    /*GILLT_s64*//*Label 71*/ 2662,
1146
53
    /*GILLT_v2s16*//*Label 72*/ 3003,
1147
53
    /*GILLT_v2s32*//*Label 73*/ 3208,
1148
53
    /*GILLT_v2s64*//*Label 74*/ 3583,
1149
53
    /*GILLT_v4s16*//*Label 75*/ 3754,
1150
53
    /*GILLT_v4s32*//*Label 76*/ 4027,
1151
53
    /*GILLT_v8s32*//*Label 77*/ 4198,
1152
53
    /*GILLT_v16s32*//*Label 78*/ 4326,
1153
53
    // Label 69: @2261
1154
53
    GIM_Try, /*On fail goto*//*Label 80*/ 2388,
1155
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
1156
53
      GIM_Try, /*On fail goto*//*Label 81*/ 2297, // Rule ID 1591 //
1157
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1158
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1159
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1160
53
        // (bitconvert:{ *:[i16] } VGPR_32:{ *:[f16] }:$src0)  =>  VGPR_32:{ *:[i16] }:$src0
1161
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1162
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1163
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1164
53
        GIR_EraseFromParent, /*InsnID*/0,
1165
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1166
53
        // GIR_Coverage, 1591,
1167
53
        GIR_Done,
1168
53
      // Label 81: @2297
1169
53
      GIM_Try, /*On fail goto*//*Label 82*/ 2327, // Rule ID 1592 //
1170
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1171
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1172
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1173
53
        // (bitconvert:{ *:[f16] } VGPR_32:{ *:[i16] }:$src0)  =>  VGPR_32:{ *:[f16] }:$src0
1174
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1175
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1176
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1177
53
        GIR_EraseFromParent, /*InsnID*/0,
1178
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1179
53
        // GIR_Coverage, 1592,
1180
53
        GIR_Done,
1181
53
      // Label 82: @2327
1182
53
      GIM_Try, /*On fail goto*//*Label 83*/ 2357, // Rule ID 1593 //
1183
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1184
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1185
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1186
53
        // (bitconvert:{ *:[i16] } SReg_32:{ *:[f16] }:$src0)  =>  SReg_32:{ *:[i16] }:$src0
1187
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1188
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1189
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1190
53
        GIR_EraseFromParent, /*InsnID*/0,
1191
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1192
53
        // GIR_Coverage, 1593,
1193
53
        GIR_Done,
1194
53
      // Label 83: @2357
1195
53
      GIM_Try, /*On fail goto*//*Label 84*/ 2387, // Rule ID 1594 //
1196
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1197
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1198
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1199
53
        // (bitconvert:{ *:[f16] } SReg_32:{ *:[i16] }:$src0)  =>  SReg_32:{ *:[f16] }:$src0
1200
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1201
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1202
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1203
53
        GIR_EraseFromParent, /*InsnID*/0,
1204
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1205
53
        // GIR_Coverage, 1594,
1206
53
        GIR_Done,
1207
53
      // Label 84: @2387
1208
53
      GIM_Reject,
1209
53
    // Label 80: @2388
1210
53
    GIM_Reject,
1211
53
    // Label 70: @2389
1212
53
    GIM_Try, /*On fail goto*//*Label 85*/ 2423, // Rule ID 1595 //
1213
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1214
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1215
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1216
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1217
53
      // (bitconvert:{ *:[i32] } VGPR_32:{ *:[f32] }:$src0)  =>  VGPR_32:{ *:[i32] }:$src0
1218
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1219
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1220
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1221
53
      GIR_EraseFromParent, /*InsnID*/0,
1222
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1223
53
      // GIR_Coverage, 1595,
1224
53
      GIR_Done,
1225
53
    // Label 85: @2423
1226
53
    GIM_Try, /*On fail goto*//*Label 86*/ 2457, // Rule ID 1596 //
1227
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1228
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1229
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1230
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1231
53
      // (bitconvert:{ *:[f32] } VGPR_32:{ *:[i32] }:$src0)  =>  VGPR_32:{ *:[f32] }:$src0
1232
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1233
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1234
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1235
53
      GIR_EraseFromParent, /*InsnID*/0,
1236
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1237
53
      // GIR_Coverage, 1596,
1238
53
      GIR_Done,
1239
53
    // Label 86: @2457
1240
53
    GIM_Try, /*On fail goto*//*Label 87*/ 2491, // Rule ID 1597 //
1241
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1242
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1243
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1244
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1245
53
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1246
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1247
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1248
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1249
53
      GIR_EraseFromParent, /*InsnID*/0,
1250
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1251
53
      // GIR_Coverage, 1597,
1252
53
      GIR_Done,
1253
53
    // Label 87: @2491
1254
53
    GIM_Try, /*On fail goto*//*Label 88*/ 2525, // Rule ID 1598 //
1255
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1256
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1257
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1258
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1259
53
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1260
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1261
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1262
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1263
53
      GIR_EraseFromParent, /*InsnID*/0,
1264
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1265
53
      // GIR_Coverage, 1598,
1266
53
      GIR_Done,
1267
53
    // Label 88: @2525
1268
53
    GIM_Try, /*On fail goto*//*Label 89*/ 2559, // Rule ID 1600 //
1269
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1270
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1271
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1272
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1273
53
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1274
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1275
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1276
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1277
53
      GIR_EraseFromParent, /*InsnID*/0,
1278
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1279
53
      // GIR_Coverage, 1600,
1280
53
      GIR_Done,
1281
53
    // Label 89: @2559
1282
53
    GIM_Try, /*On fail goto*//*Label 90*/ 2593, // Rule ID 1602 //
1283
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1284
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1285
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1286
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1287
53
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1288
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1289
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1290
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1291
53
      GIR_EraseFromParent, /*InsnID*/0,
1292
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1293
53
      // GIR_Coverage, 1602,
1294
53
      GIR_Done,
1295
53
    // Label 90: @2593
1296
53
    GIM_Try, /*On fail goto*//*Label 91*/ 2627, // Rule ID 1606 //
1297
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1298
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1299
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1300
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1301
53
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1302
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1303
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1304
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1305
53
      GIR_EraseFromParent, /*InsnID*/0,
1306
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1307
53
      // GIR_Coverage, 1606,
1308
53
      GIR_Done,
1309
53
    // Label 91: @2627
1310
53
    GIM_Try, /*On fail goto*//*Label 92*/ 2661, // Rule ID 1608 //
1311
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1312
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1313
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1314
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1315
53
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1316
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1317
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1318
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1319
53
      GIR_EraseFromParent, /*InsnID*/0,
1320
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1321
53
      // GIR_Coverage, 1608,
1322
53
      GIR_Done,
1323
53
    // Label 92: @2661
1324
53
    GIM_Reject,
1325
53
    // Label 71: @2662
1326
53
    GIM_Try, /*On fail goto*//*Label 93*/ 2696, // Rule ID 1609 //
1327
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1328
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1329
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1330
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1331
53
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1332
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1333
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1334
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1335
53
      GIR_EraseFromParent, /*InsnID*/0,
1336
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1337
53
      // GIR_Coverage, 1609,
1338
53
      GIR_Done,
1339
53
    // Label 93: @2696
1340
53
    GIM_Try, /*On fail goto*//*Label 94*/ 2730, // Rule ID 1610 //
1341
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1342
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1343
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1344
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1345
53
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1346
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1347
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1348
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1349
53
      GIR_EraseFromParent, /*InsnID*/0,
1350
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1351
53
      // GIR_Coverage, 1610,
1352
53
      GIR_Done,
1353
53
    // Label 94: @2730
1354
53
    GIM_Try, /*On fail goto*//*Label 95*/ 2764, // Rule ID 1613 //
1355
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1356
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1357
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1358
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1359
53
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1360
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1361
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1362
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1363
53
      GIR_EraseFromParent, /*InsnID*/0,
1364
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1365
53
      // GIR_Coverage, 1613,
1366
53
      GIR_Done,
1367
53
    // Label 95: @2764
1368
53
    GIM_Try, /*On fail goto*//*Label 96*/ 2798, // Rule ID 1615 //
1369
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1370
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1371
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1372
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1373
53
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1374
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1375
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1376
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1377
53
      GIR_EraseFromParent, /*InsnID*/0,
1378
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1379
53
      // GIR_Coverage, 1615,
1380
53
      GIR_Done,
1381
53
    // Label 96: @2798
1382
53
    GIM_Try, /*On fail goto*//*Label 97*/ 2832, // Rule ID 1617 //
1383
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1384
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1385
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1386
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1387
53
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1388
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1389
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1390
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1391
53
      GIR_EraseFromParent, /*InsnID*/0,
1392
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1393
53
      // GIR_Coverage, 1617,
1394
53
      GIR_Done,
1395
53
    // Label 97: @2832
1396
53
    GIM_Try, /*On fail goto*//*Label 98*/ 2866, // Rule ID 1619 //
1397
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1398
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1399
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1400
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1401
53
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1402
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1403
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1404
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1405
53
      GIR_EraseFromParent, /*InsnID*/0,
1406
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1407
53
      // GIR_Coverage, 1619,
1408
53
      GIR_Done,
1409
53
    // Label 98: @2866
1410
53
    GIM_Try, /*On fail goto*//*Label 99*/ 2900, // Rule ID 1632 //
1411
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1412
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1413
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1414
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1415
53
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1416
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1417
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1418
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1419
53
      GIR_EraseFromParent, /*InsnID*/0,
1420
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1421
53
      // GIR_Coverage, 1632,
1422
53
      GIR_Done,
1423
53
    // Label 99: @2900
1424
53
    GIM_Try, /*On fail goto*//*Label 100*/ 2934, // Rule ID 1633 //
1425
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1426
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1427
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1428
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1429
53
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1430
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1431
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1432
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1433
53
      GIR_EraseFromParent, /*InsnID*/0,
1434
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1435
53
      // GIR_Coverage, 1633,
1436
53
      GIR_Done,
1437
53
    // Label 100: @2934
1438
53
    GIM_Try, /*On fail goto*//*Label 101*/ 2968, // Rule ID 1636 //
1439
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1440
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1441
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1442
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1443
53
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1444
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1445
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1446
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1447
53
      GIR_EraseFromParent, /*InsnID*/0,
1448
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1449
53
      // GIR_Coverage, 1636,
1450
53
      GIR_Done,
1451
53
    // Label 101: @2968
1452
53
    GIM_Try, /*On fail goto*//*Label 102*/ 3002, // Rule ID 1637 //
1453
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1454
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1455
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1456
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1457
53
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1458
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1459
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1460
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1461
53
      GIR_EraseFromParent, /*InsnID*/0,
1462
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1463
53
      // GIR_Coverage, 1637,
1464
53
      GIR_Done,
1465
53
    // Label 102: @3002
1466
53
    GIM_Reject,
1467
53
    // Label 72: @3003
1468
53
    GIM_Try, /*On fail goto*//*Label 103*/ 3037, // Rule ID 1599 //
1469
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1470
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1471
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1472
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1473
53
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1474
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1475
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1476
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1477
53
      GIR_EraseFromParent, /*InsnID*/0,
1478
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1479
53
      // GIR_Coverage, 1599,
1480
53
      GIR_Done,
1481
53
    // Label 103: @3037
1482
53
    GIM_Try, /*On fail goto*//*Label 104*/ 3071, // Rule ID 1601 //
1483
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1484
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1485
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1486
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1487
53
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1488
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1489
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1490
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1491
53
      GIR_EraseFromParent, /*InsnID*/0,
1492
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1493
53
      // GIR_Coverage, 1601,
1494
53
      GIR_Done,
1495
53
    // Label 104: @3071
1496
53
    GIM_Try, /*On fail goto*//*Label 105*/ 3105, // Rule ID 1603 //
1497
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1498
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1499
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1500
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1501
53
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1502
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1503
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1504
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1505
53
      GIR_EraseFromParent, /*InsnID*/0,
1506
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1507
53
      // GIR_Coverage, 1603,
1508
53
      GIR_Done,
1509
53
    // Label 105: @3105
1510
53
    GIM_Try, /*On fail goto*//*Label 106*/ 3139, // Rule ID 1604 //
1511
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1512
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1513
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1514
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1515
53
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1516
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1517
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1518
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1519
53
      GIR_EraseFromParent, /*InsnID*/0,
1520
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1521
53
      // GIR_Coverage, 1604,
1522
53
      GIR_Done,
1523
53
    // Label 106: @3139
1524
53
    GIM_Try, /*On fail goto*//*Label 107*/ 3173, // Rule ID 1605 //
1525
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1526
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1527
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1528
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1529
53
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1530
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1531
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1532
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1533
53
      GIR_EraseFromParent, /*InsnID*/0,
1534
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1535
53
      // GIR_Coverage, 1605,
1536
53
      GIR_Done,
1537
53
    // Label 107: @3173
1538
53
    GIM_Try, /*On fail goto*//*Label 108*/ 3207, // Rule ID 1607 //
1539
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1540
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1541
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1542
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1543
53
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1544
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1545
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1546
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1547
53
      GIR_EraseFromParent, /*InsnID*/0,
1548
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1549
53
      // GIR_Coverage, 1607,
1550
53
      GIR_Done,
1551
53
    // Label 108: @3207
1552
53
    GIM_Reject,
1553
53
    // Label 73: @3208
1554
53
    GIM_Try, /*On fail goto*//*Label 109*/ 3242, // Rule ID 1611 //
1555
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1556
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1557
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1558
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1559
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1560
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1561
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1562
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1563
53
      GIR_EraseFromParent, /*InsnID*/0,
1564
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1565
53
      // GIR_Coverage, 1611,
1566
53
      GIR_Done,
1567
53
    // Label 109: @3242
1568
53
    GIM_Try, /*On fail goto*//*Label 110*/ 3276, // Rule ID 1612 //
1569
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1570
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1571
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1572
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1573
53
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1574
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1575
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1576
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1577
53
      GIR_EraseFromParent, /*InsnID*/0,
1578
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1579
53
      // GIR_Coverage, 1612,
1580
53
      GIR_Done,
1581
53
    // Label 110: @3276
1582
53
    GIM_Try, /*On fail goto*//*Label 111*/ 3310, // Rule ID 1614 //
1583
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1584
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1585
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1586
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1587
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1588
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1589
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1590
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1591
53
      GIR_EraseFromParent, /*InsnID*/0,
1592
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1593
53
      // GIR_Coverage, 1614,
1594
53
      GIR_Done,
1595
53
    // Label 111: @3310
1596
53
    GIM_Try, /*On fail goto*//*Label 112*/ 3344, // Rule ID 1616 //
1597
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1598
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1599
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1600
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1601
53
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1602
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1603
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1604
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1605
53
      GIR_EraseFromParent, /*InsnID*/0,
1606
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1607
53
      // GIR_Coverage, 1616,
1608
53
      GIR_Done,
1609
53
    // Label 112: @3344
1610
53
    GIM_Try, /*On fail goto*//*Label 113*/ 3378, // Rule ID 1618 //
1611
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1612
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1613
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1614
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1615
53
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1616
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1617
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1618
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1619
53
      GIR_EraseFromParent, /*InsnID*/0,
1620
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1621
53
      // GIR_Coverage, 1618,
1622
53
      GIR_Done,
1623
53
    // Label 113: @3378
1624
53
    GIM_Try, /*On fail goto*//*Label 114*/ 3412, // Rule ID 1620 //
1625
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1626
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1627
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1628
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1629
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1630
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1631
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1632
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1633
53
      GIR_EraseFromParent, /*InsnID*/0,
1634
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1635
53
      // GIR_Coverage, 1620,
1636
53
      GIR_Done,
1637
53
    // Label 114: @3412
1638
53
    GIM_Try, /*On fail goto*//*Label 115*/ 3446, // Rule ID 1621 //
1639
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1640
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1641
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1642
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1643
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1644
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1645
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1646
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1647
53
      GIR_EraseFromParent, /*InsnID*/0,
1648
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1649
53
      // GIR_Coverage, 1621,
1650
53
      GIR_Done,
1651
53
    // Label 115: @3446
1652
53
    GIM_Try, /*On fail goto*//*Label 116*/ 3480, // Rule ID 1623 //
1653
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1654
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1655
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1656
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1657
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1658
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1659
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1660
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1661
53
      GIR_EraseFromParent, /*InsnID*/0,
1662
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1663
53
      // GIR_Coverage, 1623,
1664
53
      GIR_Done,
1665
53
    // Label 116: @3480
1666
53
    GIM_Try, /*On fail goto*//*Label 117*/ 3514, // Rule ID 1624 //
1667
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1668
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1669
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1670
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1671
53
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1672
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1673
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1674
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1675
53
      GIR_EraseFromParent, /*InsnID*/0,
1676
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1677
53
      // GIR_Coverage, 1624,
1678
53
      GIR_Done,
1679
53
    // Label 117: @3514
1680
53
    GIM_Try, /*On fail goto*//*Label 118*/ 3548, // Rule ID 1626 //
1681
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1682
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1683
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1684
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1685
53
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1686
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1687
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1688
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1689
53
      GIR_EraseFromParent, /*InsnID*/0,
1690
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1691
53
      // GIR_Coverage, 1626,
1692
53
      GIR_Done,
1693
53
    // Label 118: @3548
1694
53
    GIM_Try, /*On fail goto*//*Label 119*/ 3582, // Rule ID 1628 //
1695
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1696
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1697
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1698
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1699
53
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1700
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1701
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1702
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1703
53
      GIR_EraseFromParent, /*InsnID*/0,
1704
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1705
53
      // GIR_Coverage, 1628,
1706
53
      GIR_Done,
1707
53
    // Label 119: @3582
1708
53
    GIM_Reject,
1709
53
    // Label 74: @3583
1710
53
    GIM_Try, /*On fail goto*//*Label 120*/ 3617, // Rule ID 1640 //
1711
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1712
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1713
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_128RegClassID,
1714
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_128RegClassID,
1715
53
      // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
1716
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1717
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1718
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1719
53
      GIR_EraseFromParent, /*InsnID*/0,
1720
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_128*/21,
1721
53
      // GIR_Coverage, 1640,
1722
53
      GIR_Done,
1723
53
    // Label 120: @3617
1724
53
    GIM_Try, /*On fail goto*//*Label 121*/ 3651, // Rule ID 1642 //
1725
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1726
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1727
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1728
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1729
53
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1730
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1731
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1732
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1733
53
      GIR_EraseFromParent, /*InsnID*/0,
1734
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1735
53
      // GIR_Coverage, 1642,
1736
53
      GIR_Done,
1737
53
    // Label 121: @3651
1738
53
    GIM_Try, /*On fail goto*//*Label 122*/ 3685, // Rule ID 1643 //
1739
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1740
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1741
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1742
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1743
53
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1744
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1745
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1746
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1747
53
      GIR_EraseFromParent, /*InsnID*/0,
1748
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1749
53
      // GIR_Coverage, 1643,
1750
53
      GIR_Done,
1751
53
    // Label 122: @3685
1752
53
    GIM_Try, /*On fail goto*//*Label 123*/ 3719, // Rule ID 1646 //
1753
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1754
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1755
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1756
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1757
53
      // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
1758
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1759
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1760
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1761
53
      GIR_EraseFromParent, /*InsnID*/0,
1762
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1763
53
      // GIR_Coverage, 1646,
1764
53
      GIR_Done,
1765
53
    // Label 123: @3719
1766
53
    GIM_Try, /*On fail goto*//*Label 124*/ 3753, // Rule ID 1647 //
1767
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1768
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1769
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1770
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1771
53
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1772
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1773
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1774
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1775
53
      GIR_EraseFromParent, /*InsnID*/0,
1776
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1777
53
      // GIR_Coverage, 1647,
1778
53
      GIR_Done,
1779
53
    // Label 124: @3753
1780
53
    GIM_Reject,
1781
53
    // Label 75: @3754
1782
53
    GIM_Try, /*On fail goto*//*Label 125*/ 3788, // Rule ID 1622 //
1783
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1784
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1785
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1786
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1787
53
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1788
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1789
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1790
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1791
53
      GIR_EraseFromParent, /*InsnID*/0,
1792
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1793
53
      // GIR_Coverage, 1622,
1794
53
      GIR_Done,
1795
53
    // Label 125: @3788
1796
53
    GIM_Try, /*On fail goto*//*Label 126*/ 3822, // Rule ID 1625 //
1797
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1798
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1799
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1800
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1801
53
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1802
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1803
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1804
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1805
53
      GIR_EraseFromParent, /*InsnID*/0,
1806
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1807
53
      // GIR_Coverage, 1625,
1808
53
      GIR_Done,
1809
53
    // Label 126: @3822
1810
53
    GIM_Try, /*On fail goto*//*Label 127*/ 3856, // Rule ID 1627 //
1811
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1812
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1813
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1814
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1815
53
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1816
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1817
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1818
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1819
53
      GIR_EraseFromParent, /*InsnID*/0,
1820
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1821
53
      // GIR_Coverage, 1627,
1822
53
      GIR_Done,
1823
53
    // Label 127: @3856
1824
53
    GIM_Try, /*On fail goto*//*Label 128*/ 3890, // Rule ID 1629 //
1825
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1826
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1827
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1828
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1829
53
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1830
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1831
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1832
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1833
53
      GIR_EraseFromParent, /*InsnID*/0,
1834
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1835
53
      // GIR_Coverage, 1629,
1836
53
      GIR_Done,
1837
53
    // Label 128: @3890
1838
53
    GIM_Try, /*On fail goto*//*Label 129*/ 3924, // Rule ID 1630 //
1839
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1840
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1841
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1842
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1843
53
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1844
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1845
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1846
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1847
53
      GIR_EraseFromParent, /*InsnID*/0,
1848
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1849
53
      // GIR_Coverage, 1630,
1850
53
      GIR_Done,
1851
53
    // Label 129: @3924
1852
53
    GIM_Try, /*On fail goto*//*Label 130*/ 3958, // Rule ID 1631 //
1853
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1854
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1855
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1856
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1857
53
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1858
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1859
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1860
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1861
53
      GIR_EraseFromParent, /*InsnID*/0,
1862
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1863
53
      // GIR_Coverage, 1631,
1864
53
      GIR_Done,
1865
53
    // Label 130: @3958
1866
53
    GIM_Try, /*On fail goto*//*Label 131*/ 3992, // Rule ID 1634 //
1867
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1868
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1869
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1870
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1871
53
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1872
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1873
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1874
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1875
53
      GIR_EraseFromParent, /*InsnID*/0,
1876
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1877
53
      // GIR_Coverage, 1634,
1878
53
      GIR_Done,
1879
53
    // Label 131: @3992
1880
53
    GIM_Try, /*On fail goto*//*Label 132*/ 4026, // Rule ID 1635 //
1881
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1882
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1883
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1884
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1885
53
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1886
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1887
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1888
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1889
53
      GIR_EraseFromParent, /*InsnID*/0,
1890
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1891
53
      // GIR_Coverage, 1635,
1892
53
      GIR_Done,
1893
53
    // Label 132: @4026
1894
53
    GIM_Reject,
1895
53
    // Label 76: @4027
1896
53
    GIM_Try, /*On fail goto*//*Label 133*/ 4061, // Rule ID 1638 //
1897
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1898
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1899
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1900
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1901
53
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
1902
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1903
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1904
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1905
53
      GIR_EraseFromParent, /*InsnID*/0,
1906
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1907
53
      // GIR_Coverage, 1638,
1908
53
      GIR_Done,
1909
53
    // Label 133: @4061
1910
53
    GIM_Try, /*On fail goto*//*Label 134*/ 4095, // Rule ID 1639 //
1911
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1912
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1913
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1914
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1915
53
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
1916
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1917
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1918
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1919
53
      GIR_EraseFromParent, /*InsnID*/0,
1920
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1921
53
      // GIR_Coverage, 1639,
1922
53
      GIR_Done,
1923
53
    // Label 134: @4095
1924
53
    GIM_Try, /*On fail goto*//*Label 135*/ 4129, // Rule ID 1641 //
1925
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1926
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1927
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_128RegClassID,
1928
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_128RegClassID,
1929
53
      // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
1930
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1931
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1932
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1933
53
      GIR_EraseFromParent, /*InsnID*/0,
1934
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_128*/21,
1935
53
      // GIR_Coverage, 1641,
1936
53
      GIR_Done,
1937
53
    // Label 135: @4129
1938
53
    GIM_Try, /*On fail goto*//*Label 136*/ 4163, // Rule ID 1644 //
1939
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1940
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1941
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1942
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1943
53
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
1944
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1945
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1946
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1947
53
      GIR_EraseFromParent, /*InsnID*/0,
1948
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1949
53
      // GIR_Coverage, 1644,
1950
53
      GIR_Done,
1951
53
    // Label 136: @4163
1952
53
    GIM_Try, /*On fail goto*//*Label 137*/ 4197, // Rule ID 1645 //
1953
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1954
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1955
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1956
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1957
53
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
1958
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1959
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1960
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1961
53
      GIR_EraseFromParent, /*InsnID*/0,
1962
53
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1963
53
      // GIR_Coverage, 1645,
1964
53
      GIR_Done,
1965
53
    // Label 137: @4197
1966
53
    GIM_Reject,
1967
53
    // Label 77: @4198
1968
53
    GIM_Try, /*On fail goto*//*Label 138*/ 4325,
1969
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
1970
53
      GIM_Try, /*On fail goto*//*Label 139*/ 4234, // Rule ID 1648 //
1971
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1972
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_256RegClassID,
1973
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_256RegClassID,
1974
53
        // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v8f32] }:$src0)  =>  SReg_256:{ *:[v8i32] }:$src0
1975
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1976
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1977
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1978
53
        GIR_EraseFromParent, /*InsnID*/0,
1979
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_256*/26,
1980
53
        // GIR_Coverage, 1648,
1981
53
        GIR_Done,
1982
53
      // Label 139: @4234
1983
53
      GIM_Try, /*On fail goto*//*Label 140*/ 4264, // Rule ID 1649 //
1984
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1985
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_256RegClassID,
1986
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_256RegClassID,
1987
53
        // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v8i32] }:$src0)  =>  SReg_256:{ *:[v8f32] }:$src0
1988
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1989
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1990
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1991
53
        GIR_EraseFromParent, /*InsnID*/0,
1992
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_256*/26,
1993
53
        // GIR_Coverage, 1649,
1994
53
        GIR_Done,
1995
53
      // Label 140: @4264
1996
53
      GIM_Try, /*On fail goto*//*Label 141*/ 4294, // Rule ID 1650 //
1997
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1998
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_256RegClassID,
1999
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_256RegClassID,
2000
53
        // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
2001
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2002
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2003
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2004
53
        GIR_EraseFromParent, /*InsnID*/0,
2005
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_256*/25,
2006
53
        // GIR_Coverage, 1650,
2007
53
        GIR_Done,
2008
53
      // Label 141: @4294
2009
53
      GIM_Try, /*On fail goto*//*Label 142*/ 4324, // Rule ID 1651 //
2010
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2011
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_256RegClassID,
2012
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_256RegClassID,
2013
53
        // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
2014
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2015
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2016
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2017
53
        GIR_EraseFromParent, /*InsnID*/0,
2018
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_256*/25,
2019
53
        // GIR_Coverage, 1651,
2020
53
        GIR_Done,
2021
53
      // Label 142: @4324
2022
53
      GIM_Reject,
2023
53
    // Label 138: @4325
2024
53
    GIM_Reject,
2025
53
    // Label 78: @4326
2026
53
    GIM_Try, /*On fail goto*//*Label 143*/ 4385,
2027
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
2028
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_512RegClassID,
2029
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_512RegClassID,
2030
53
      GIM_Try, /*On fail goto*//*Label 144*/ 4362, // Rule ID 1652 //
2031
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2032
53
        // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
2033
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2034
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2035
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2036
53
        GIR_EraseFromParent, /*InsnID*/0,
2037
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_512*/29,
2038
53
        // GIR_Coverage, 1652,
2039
53
        GIR_Done,
2040
53
      // Label 144: @4362
2041
53
      GIM_Try, /*On fail goto*//*Label 145*/ 4384, // Rule ID 1653 //
2042
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2043
53
        // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
2044
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2045
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2046
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2047
53
        GIR_EraseFromParent, /*InsnID*/0,
2048
53
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_512*/29,
2049
53
        // GIR_Coverage, 1653,
2050
53
        GIR_Done,
2051
53
      // Label 145: @4384
2052
53
      GIM_Reject,
2053
53
    // Label 143: @4385
2054
53
    GIM_Reject,
2055
53
    // Label 79: @4386
2056
53
    GIM_Reject,
2057
53
    // Label 7: @4387
2058
53
    GIM_Try, /*On fail goto*//*Label 146*/ 4477,
2059
53
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
2060
53
      GIM_Try, /*On fail goto*//*Label 147*/ 4420, // Rule ID 10 //
2061
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2062
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_getpc,
2063
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2064
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2065
53
        // (intrinsic_wo_chain:{ *:[i64] } 948:{ *:[iPTR] })  =>  (S_GETPC_B64:{ *:[i64] })
2066
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_GETPC_B64,
2067
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2068
53
        GIR_EraseFromParent, /*InsnID*/0,
2069
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2070
53
        // GIR_Coverage, 10,
2071
53
        GIR_Done,
2072
53
      // Label 147: @4420
2073
53
      GIM_Try, /*On fail goto*//*Label 148*/ 4448, // Rule ID 652 //
2074
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2075
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_groupstaticsize,
2076
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2077
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2078
53
        // (intrinsic_wo_chain:{ *:[i32] } 433:{ *:[iPTR] })  =>  (GET_GROUPSTATICSIZE:{ *:[i32] })
2079
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GET_GROUPSTATICSIZE,
2080
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2081
53
        GIR_EraseFromParent, /*InsnID*/0,
2082
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2083
53
        // GIR_Coverage, 652,
2084
53
        GIR_Done,
2085
53
      // Label 148: @4448
2086
53
      GIM_Try, /*On fail goto*//*Label 149*/ 4476, // Rule ID 661 //
2087
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2088
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_ps_live,
2089
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
2090
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2091
53
        // (intrinsic_wo_chain:{ *:[i1] } 914:{ *:[iPTR] })  =>  (SI_PS_LIVE:{ *:[i1] })
2092
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_PS_LIVE,
2093
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2094
53
        GIR_EraseFromParent, /*InsnID*/0,
2095
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2096
53
        // GIR_Coverage, 661,
2097
53
        GIR_Done,
2098
53
      // Label 149: @4476
2099
53
      GIM_Reject,
2100
53
    // Label 146: @4477
2101
53
    GIM_Try, /*On fail goto*//*Label 150*/ 4948,
2102
53
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2103
53
      GIM_Try, /*On fail goto*//*Label 151*/ 4518, // Rule ID 2 //
2104
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2105
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_wqm_vote,
2106
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
2107
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
2108
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2109
53
        // (intrinsic_wo_chain:{ *:[i1] } 1001:{ *:[iPTR] }, i1:{ *:[i1] }:$src0)  =>  (S_WQM_B64:{ *:[i1] }:{ *:[i1] } i1:{ *:[i1] }:$src0)
2110
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_WQM_B64,
2111
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2112
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2113
53
        GIR_EraseFromParent, /*InsnID*/0,
2114
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2115
53
        // GIR_Coverage, 2,
2116
53
        GIR_Done,
2117
53
      // Label 151: @4518
2118
53
      GIM_Try, /*On fail goto*//*Label 152*/ 4554, // Rule ID 321 //
2119
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2120
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_readfirstlane,
2121
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2122
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2123
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2124
53
        // (intrinsic_wo_chain:{ *:[i32] } 936:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
2125
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READFIRSTLANE_B32,
2126
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2127
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2128
53
        GIR_EraseFromParent, /*InsnID*/0,
2129
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2130
53
        // GIR_Coverage, 321,
2131
53
        GIR_Done,
2132
53
      // Label 152: @4554
2133
53
      GIM_Try, /*On fail goto*//*Label 153*/ 4590, // Rule ID 658 //
2134
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2135
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_break,
2136
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2137
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2138
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2139
53
        // (intrinsic_wo_chain:{ *:[i64] } 377:{ *:[iPTR] }, i64:{ *:[i64] }:$src)  =>  (SI_BREAK:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src)
2140
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_BREAK,
2141
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2142
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2143
53
        GIR_EraseFromParent, /*InsnID*/0,
2144
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2145
53
        // GIR_Coverage, 658,
2146
53
        GIR_Done,
2147
53
      // Label 153: @4590
2148
53
      GIM_Try, /*On fail goto*//*Label 154*/ 4641, // Rule ID 356 //
2149
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2150
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2151
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2152
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2153
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2154
53
        // (intrinsic_wo_chain:{ *:[i32] } 431:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2155
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F64_e64,
2156
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2157
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2158
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2159
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2160
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2161
53
        GIR_EraseFromParent, /*InsnID*/0,
2162
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2163
53
        // GIR_Coverage, 356,
2164
53
        GIR_Done,
2165
53
      // Label 154: @4641
2166
53
      GIM_Try, /*On fail goto*//*Label 155*/ 4692, // Rule ID 357 //
2167
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2168
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2169
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2170
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2171
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2172
53
        // (intrinsic_wo_chain:{ *:[f64] } 432:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2173
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F64_e64,
2174
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2175
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2176
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2177
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2178
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2179
53
        GIR_EraseFromParent, /*InsnID*/0,
2180
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2181
53
        // GIR_Coverage, 357,
2182
53
        GIR_Done,
2183
53
      // Label 155: @4692
2184
53
      GIM_Try, /*On fail goto*//*Label 156*/ 4743, // Rule ID 359 //
2185
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2186
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2187
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2188
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2189
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2190
53
        // (intrinsic_wo_chain:{ *:[i32] } 431:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2191
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F32_e64,
2192
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2193
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2194
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2195
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2196
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2197
53
        GIR_EraseFromParent, /*InsnID*/0,
2198
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2199
53
        // GIR_Coverage, 359,
2200
53
        GIR_Done,
2201
53
      // Label 156: @4743
2202
53
      GIM_Try, /*On fail goto*//*Label 157*/ 4794, // Rule ID 360 //
2203
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2204
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2205
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2206
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2207
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2208
53
        // (intrinsic_wo_chain:{ *:[f32] } 432:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2209
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F32_e64,
2210
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2211
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2212
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2213
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2214
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2215
53
        GIR_EraseFromParent, /*InsnID*/0,
2216
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2217
53
        // GIR_Coverage, 360,
2218
53
        GIR_Done,
2219
53
      // Label 157: @4794
2220
53
      GIM_Try, /*On fail goto*//*Label 158*/ 4845, // Rule ID 361 //
2221
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_log_clamp,
2222
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2223
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2224
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2225
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2226
53
        // (intrinsic_wo_chain:{ *:[f32] } 906:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_CLAMP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2227
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_CLAMP_F32_e64,
2228
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2229
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2230
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2231
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2232
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2233
53
        GIR_EraseFromParent, /*InsnID*/0,
2234
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2235
53
        // GIR_Coverage, 361,
2236
53
        GIR_Done,
2237
53
      // Label 158: @4845
2238
53
      GIM_Try, /*On fail goto*//*Label 159*/ 4896, // Rule ID 381 //
2239
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2240
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
2241
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2242
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2243
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2244
53
        // (intrinsic_wo_chain:{ *:[f16] } 432:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2245
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F16_e64,
2246
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2247
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2248
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2249
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2250
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2251
53
        GIR_EraseFromParent, /*InsnID*/0,
2252
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2253
53
        // GIR_Coverage, 381,
2254
53
        GIR_Done,
2255
53
      // Label 159: @4896
2256
53
      GIM_Try, /*On fail goto*//*Label 160*/ 4947, // Rule ID 382 //
2257
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2258
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
2259
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2260
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2261
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2262
53
        // (intrinsic_wo_chain:{ *:[i16] } 431:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2263
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I16_F16_e64,
2264
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2265
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2266
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2267
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2268
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2269
53
        GIR_EraseFromParent, /*InsnID*/0,
2270
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2271
53
        // GIR_Coverage, 382,
2272
53
        GIR_Done,
2273
53
      // Label 160: @4947
2274
53
      GIM_Reject,
2275
53
    // Label 150: @4948
2276
53
    GIM_Try, /*On fail goto*//*Label 161*/ 5860,
2277
53
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
2278
53
      GIM_Try, /*On fail goto*//*Label 162*/ 5023, // Rule ID 1911 //
2279
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2280
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2281
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2282
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2283
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2284
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2285
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2286
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2287
53
        // (intrinsic_wo_chain:{ *:[f64] } 131:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2288
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
2289
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2290
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2291
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2292
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2293
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2294
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2295
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
2296
53
        GIR_EraseFromParent, /*InsnID*/0,
2297
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2298
53
        // GIR_Coverage, 1911,
2299
53
        GIR_Done,
2300
53
      // Label 162: @5023
2301
53
      GIM_Try, /*On fail goto*//*Label 163*/ 5093, // Rule ID 1914 //
2302
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2303
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2304
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2305
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2306
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2307
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2308
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2309
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2310
53
        // (intrinsic_wo_chain:{ *:[f64] } 138:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2311
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
2312
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2313
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2314
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2315
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2316
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2317
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2318
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
2319
53
        GIR_EraseFromParent, /*InsnID*/0,
2320
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2321
53
        // GIR_Coverage, 1914,
2322
53
        GIR_Done,
2323
53
      // Label 163: @5093
2324
53
      GIM_Try, /*On fail goto*//*Label 164*/ 5163, // Rule ID 2392 //
2325
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2326
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2327
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2328
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2329
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2330
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2331
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods,
2332
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods0,
2333
53
        // (intrinsic_wo_chain:{ *:[f64] } 131:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods))  =>  (V_MAX_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2334
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
2335
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2336
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
2337
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
2338
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
2339
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
2340
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
2341
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omods
2342
53
        GIR_EraseFromParent, /*InsnID*/0,
2343
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2344
53
        // GIR_Coverage, 2392,
2345
53
        GIR_Done,
2346
53
      // Label 164: @5163
2347
53
      GIM_Try, /*On fail goto*//*Label 165*/ 5233, // Rule ID 2393 //
2348
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2349
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2350
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2351
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2352
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2353
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2354
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods,
2355
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods0,
2356
53
        // (intrinsic_wo_chain:{ *:[f64] } 138:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods))  =>  (V_MIN_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2357
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
2358
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2359
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
2360
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
2361
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
2362
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
2363
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
2364
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omods
2365
53
        GIR_EraseFromParent, /*InsnID*/0,
2366
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2367
53
        // GIR_Coverage, 2393,
2368
53
        GIR_Done,
2369
53
      // Label 165: @5233
2370
53
      GIM_Try, /*On fail goto*//*Label 166*/ 5286, // Rule ID 1901 //
2371
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2372
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pkrtz,
2373
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
2374
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2375
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2376
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2377
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
2378
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
2379
53
        // (intrinsic_wo_chain:{ *:[v2f16] } 407:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_CVT_PKRTZ_F16_F32_e32:{ *:[v2f16] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2380
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PKRTZ_F16_F32_e32,
2381
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2382
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2383
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2384
53
        GIR_EraseFromParent, /*InsnID*/0,
2385
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2386
53
        // GIR_Coverage, 1901,
2387
53
        GIR_Done,
2388
53
      // Label 166: @5286
2389
53
      GIM_Try, /*On fail goto*//*Label 167*/ 5339, // Rule ID 1909 //
2390
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2391
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2392
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2393
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2394
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2395
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2396
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
2397
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
2398
53
        // (intrinsic_wo_chain:{ *:[f32] } 131:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_MAX_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2399
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e32,
2400
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2401
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2402
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2403
53
        GIR_EraseFromParent, /*InsnID*/0,
2404
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2405
53
        // GIR_Coverage, 1909,
2406
53
        GIR_Done,
2407
53
      // Label 167: @5339
2408
53
      GIM_Try, /*On fail goto*//*Label 168*/ 5392, // Rule ID 1912 //
2409
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2410
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2411
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2412
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2413
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2414
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2415
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
2416
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
2417
53
        // (intrinsic_wo_chain:{ *:[f32] } 138:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_MIN_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2418
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e32,
2419
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2420
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2421
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2422
53
        GIR_EraseFromParent, /*InsnID*/0,
2423
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2424
53
        // GIR_Coverage, 1912,
2425
53
        GIR_Done,
2426
53
      // Label 168: @5392
2427
53
      GIM_Try, /*On fail goto*//*Label 169*/ 5445, // Rule ID 1902 //
2428
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2429
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pkrtz,
2430
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
2431
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2432
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2433
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2434
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
2435
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
2436
53
        // (intrinsic_wo_chain:{ *:[v2f16] } 407:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_CVT_PKRTZ_F16_F32_e32:{ *:[v2f16] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2437
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PKRTZ_F16_F32_e32,
2438
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2439
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2440
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2441
53
        GIR_EraseFromParent, /*InsnID*/0,
2442
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2443
53
        // GIR_Coverage, 1902,
2444
53
        GIR_Done,
2445
53
      // Label 169: @5445
2446
53
      GIM_Try, /*On fail goto*//*Label 170*/ 5498, // Rule ID 1910 //
2447
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2448
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2449
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2450
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2451
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2452
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2453
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
2454
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
2455
53
        // (intrinsic_wo_chain:{ *:[f32] } 131:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_MAX_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2456
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e32,
2457
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2458
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2459
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2460
53
        GIR_EraseFromParent, /*InsnID*/0,
2461
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2462
53
        // GIR_Coverage, 1910,
2463
53
        GIR_Done,
2464
53
      // Label 170: @5498
2465
53
      GIM_Try, /*On fail goto*//*Label 171*/ 5551, // Rule ID 1913 //
2466
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2467
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2468
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2469
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2470
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2471
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2472
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
2473
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
2474
53
        // (intrinsic_wo_chain:{ *:[f32] } 138:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_MIN_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2475
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e32,
2476
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2477
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2478
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2479
53
        GIR_EraseFromParent, /*InsnID*/0,
2480
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2481
53
        // GIR_Coverage, 1913,
2482
53
        GIR_Done,
2483
53
      // Label 171: @5551
2484
53
      GIM_Try, /*On fail goto*//*Label 172*/ 5595, // Rule ID 416 //
2485
53
        GIM_CheckFeatures, GIFBS_isGCN,
2486
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_readlane,
2487
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2488
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2489
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2490
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2491
53
        // (intrinsic_wo_chain:{ *:[i32] } 937:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2492
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READLANE_B32,
2493
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2494
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2495
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2496
53
        GIR_EraseFromParent, /*InsnID*/0,
2497
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2498
53
        // GIR_Coverage, 416,
2499
53
        GIR_Done,
2500
53
      // Label 172: @5595
2501
53
      GIM_Try, /*On fail goto*//*Label 173*/ 5639, // Rule ID 648 //
2502
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2503
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_set_inactive,
2504
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2505
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2506
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2507
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2508
53
        // (intrinsic_wo_chain:{ *:[i32] } 964:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)
2509
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B32,
2510
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2511
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2512
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
2513
53
        GIR_EraseFromParent, /*InsnID*/0,
2514
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2515
53
        // GIR_Coverage, 648,
2516
53
        GIR_Done,
2517
53
      // Label 173: @5639
2518
53
      GIM_Try, /*On fail goto*//*Label 174*/ 5683, // Rule ID 649 //
2519
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2520
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_set_inactive,
2521
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2522
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2523
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2524
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2525
53
        // (intrinsic_wo_chain:{ *:[i64] } 964:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)  =>  (V_SET_INACTIVE_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)
2526
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B64,
2527
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2528
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2529
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
2530
53
        GIR_EraseFromParent, /*InsnID*/0,
2531
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2532
53
        // GIR_Coverage, 649,
2533
53
        GIR_Done,
2534
53
      // Label 174: @5683
2535
53
      GIM_Try, /*On fail goto*//*Label 175*/ 5727, // Rule ID 659 //
2536
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2537
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_if_break,
2538
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2539
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
2540
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2541
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2542
53
        // (intrinsic_wo_chain:{ *:[i64] } 436:{ *:[iPTR] }, i1:{ *:[i1] }:$vcc, i64:{ *:[i64] }:$src)  =>  (SI_IF_BREAK:{ *:[i64] }:{ *:[i1] } i1:{ *:[i1] }:$vcc, i64:{ *:[i64] }:$src)
2543
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_IF_BREAK,
2544
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2545
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vcc
2546
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
2547
53
        GIR_EraseFromParent, /*InsnID*/0,
2548
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2549
53
        // GIR_Coverage, 659,
2550
53
        GIR_Done,
2551
53
      // Label 175: @5727
2552
53
      GIM_Try, /*On fail goto*//*Label 176*/ 5771, // Rule ID 660 //
2553
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2554
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_else_break,
2555
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2556
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2557
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2558
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2559
53
        // (intrinsic_wo_chain:{ *:[i64] } 420:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (SI_ELSE_BREAK:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
2560
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_ELSE_BREAK,
2561
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2562
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2563
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2564
53
        GIR_EraseFromParent, /*InsnID*/0,
2565
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2566
53
        // GIR_Coverage, 660,
2567
53
        GIR_Done,
2568
53
      // Label 176: @5771
2569
53
      GIM_Try, /*On fail goto*//*Label 177*/ 5815, // Rule ID 418 //
2570
53
        GIM_CheckFeatures, GIFBS_isGCN,
2571
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mbcnt_lo,
2572
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2573
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2574
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2575
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2576
53
        // (intrinsic_wo_chain:{ *:[i32] } 909:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_LO_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2577
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_LO_U32_B32_e64,
2578
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2579
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2580
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2581
53
        GIR_EraseFromParent, /*InsnID*/0,
2582
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2583
53
        // GIR_Coverage, 418,
2584
53
        GIR_Done,
2585
53
      // Label 177: @5815
2586
53
      GIM_Try, /*On fail goto*//*Label 178*/ 5859, // Rule ID 419 //
2587
53
        GIM_CheckFeatures, GIFBS_isGCN,
2588
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mbcnt_hi,
2589
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2590
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2591
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2592
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2593
53
        // (intrinsic_wo_chain:{ *:[i32] } 908:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_HI_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2594
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_HI_U32_B32_e64,
2595
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2596
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2597
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2598
53
        GIR_EraseFromParent, /*InsnID*/0,
2599
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2600
53
        // GIR_Coverage, 419,
2601
53
        GIR_Done,
2602
53
      // Label 178: @5859
2603
53
      GIM_Reject,
2604
53
    // Label 161: @5860
2605
53
    GIM_Try, /*On fail goto*//*Label 179*/ 6874,
2606
53
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
2607
53
      GIM_Try, /*On fail goto*//*Label 180*/ 5917, // Rule ID 417 //
2608
53
        GIM_CheckFeatures, GIFBS_isGCN,
2609
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_writelane,
2610
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2611
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2612
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2613
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2614
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2615
53
        // (intrinsic_wo_chain:{ *:[i32] } 1002:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)  =>  (V_WRITELANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)
2616
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_WRITELANE_B32,
2617
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2618
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2619
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2620
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vdst_in
2621
53
        GIR_EraseFromParent, /*InsnID*/0,
2622
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2623
53
        // GIR_Coverage, 417,
2624
53
        GIR_Done,
2625
53
      // Label 180: @5917
2626
53
      GIM_Try, /*On fail goto*//*Label 181*/ 5972, // Rule ID 957 //
2627
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2628
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_u8,
2629
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2630
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2631
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2632
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2633
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2634
53
        // (intrinsic_wo_chain:{ *:[i32] } 959:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2635
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U8,
2636
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2637
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2638
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2639
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2640
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2641
53
        GIR_EraseFromParent, /*InsnID*/0,
2642
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2643
53
        // GIR_Coverage, 957,
2644
53
        GIR_Done,
2645
53
      // Label 181: @5972
2646
53
      GIM_Try, /*On fail goto*//*Label 182*/ 6027, // Rule ID 958 //
2647
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2648
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_hi_u8,
2649
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2650
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2651
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2652
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2653
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2654
53
        // (intrinsic_wo_chain:{ *:[i32] } 957:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_HI_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2655
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_HI_U8,
2656
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2657
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2658
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2659
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2660
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2661
53
        GIR_EraseFromParent, /*InsnID*/0,
2662
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2663
53
        // GIR_Coverage, 958,
2664
53
        GIR_Done,
2665
53
      // Label 182: @6027
2666
53
      GIM_Try, /*On fail goto*//*Label 183*/ 6082, // Rule ID 959 //
2667
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2668
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_u16,
2669
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2670
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2671
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2672
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2673
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2674
53
        // (intrinsic_wo_chain:{ *:[i32] } 958:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U16:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2675
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U16,
2676
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2677
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2678
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2679
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2680
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2681
53
        GIR_EraseFromParent, /*InsnID*/0,
2682
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2683
53
        // GIR_Coverage, 959,
2684
53
        GIR_Done,
2685
53
      // Label 183: @6082
2686
53
      GIM_Try, /*On fail goto*//*Label 184*/ 6137, // Rule ID 960 //
2687
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2688
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_msad_u8,
2689
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2690
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2691
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2692
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2693
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2694
53
        // (intrinsic_wo_chain:{ *:[i32] } 913:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_MSAD_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2695
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MSAD_U8,
2696
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2697
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2698
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2699
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2700
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2701
53
        GIR_EraseFromParent, /*InsnID*/0,
2702
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2703
53
        // GIR_Coverage, 960,
2704
53
        GIR_Done,
2705
53
      // Label 184: @6137
2706
53
      GIM_Try, /*On fail goto*//*Label 185*/ 6192, // Rule ID 961 //
2707
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2708
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mqsad_pk_u16_u8,
2709
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2710
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2711
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2712
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
2713
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2714
53
        // (intrinsic_wo_chain:{ *:[i64] } 911:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_MQSAD_PK_U16_U8:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
2715
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_PK_U16_U8,
2716
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2717
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2718
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2719
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2720
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2721
53
        GIR_EraseFromParent, /*InsnID*/0,
2722
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2723
53
        // GIR_Coverage, 961,
2724
53
        GIR_Done,
2725
53
      // Label 185: @6192
2726
53
      GIM_Try, /*On fail goto*//*Label 186*/ 6247, // Rule ID 962 //
2727
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2728
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_qsad_pk_u16_u8,
2729
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2730
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2731
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2732
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
2733
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2734
53
        // (intrinsic_wo_chain:{ *:[i64] } 915:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_QSAD_PK_U16_U8:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
2735
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_QSAD_PK_U16_U8,
2736
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2737
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2738
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2739
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2740
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2741
53
        GIR_EraseFromParent, /*InsnID*/0,
2742
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2743
53
        // GIR_Coverage, 962,
2744
53
        GIR_Done,
2745
53
      // Label 186: @6247
2746
53
      GIM_Try, /*On fail goto*//*Label 187*/ 6302, // Rule ID 963 //
2747
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2748
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mqsad_u32_u8,
2749
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
2750
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2751
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2752
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
2753
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
2754
53
        // (intrinsic_wo_chain:{ *:[v4i32] } 912:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2)  =>  (V_MQSAD_U32_U8:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] })
2755
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_U32_U8,
2756
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2757
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2758
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2759
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2760
53
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2761
53
        GIR_EraseFromParent, /*InsnID*/0,
2762
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2763
53
        // GIR_Coverage, 963,
2764
53
        GIR_Done,
2765
53
      // Label 187: @6302
2766
53
      GIM_Try, /*On fail goto*//*Label 188*/ 6387, // Rule ID 452 //
2767
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubeid,
2768
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2769
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2770
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2771
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2772
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2773
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2774
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2775
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2776
53
        // (intrinsic_wo_chain:{ *:[f32] } 398:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEID_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2777
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEID_F32,
2778
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2779
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2780
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2781
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2782
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2783
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2784
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2785
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2786
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2787
53
        GIR_EraseFromParent, /*InsnID*/0,
2788
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2789
53
        // GIR_Coverage, 452,
2790
53
        GIR_Done,
2791
53
      // Label 188: @6387
2792
53
      GIM_Try, /*On fail goto*//*Label 189*/ 6472, // Rule ID 453 //
2793
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubesc,
2794
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2795
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2796
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2797
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2798
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2799
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2800
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2801
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2802
53
        // (intrinsic_wo_chain:{ *:[f32] } 400:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBESC_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2803
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBESC_F32,
2804
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2805
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2806
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2807
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2808
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2809
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2810
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2811
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2812
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2813
53
        GIR_EraseFromParent, /*InsnID*/0,
2814
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2815
53
        // GIR_Coverage, 453,
2816
53
        GIR_Done,
2817
53
      // Label 189: @6472
2818
53
      GIM_Try, /*On fail goto*//*Label 190*/ 6557, // Rule ID 454 //
2819
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubetc,
2820
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2821
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2822
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2823
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2824
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2825
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2826
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2827
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2828
53
        // (intrinsic_wo_chain:{ *:[f32] } 401:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBETC_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2829
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBETC_F32,
2830
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2831
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2832
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2833
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2834
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2835
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2836
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2837
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2838
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2839
53
        GIR_EraseFromParent, /*InsnID*/0,
2840
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2841
53
        // GIR_Coverage, 454,
2842
53
        GIR_Done,
2843
53
      // Label 190: @6557
2844
53
      GIM_Try, /*On fail goto*//*Label 191*/ 6642, // Rule ID 455 //
2845
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubema,
2846
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2847
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2848
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2849
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2850
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2851
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2852
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2853
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2854
53
        // (intrinsic_wo_chain:{ *:[f32] } 399:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEMA_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2855
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEMA_F32,
2856
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2857
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2858
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2859
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2860
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2861
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2862
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2863
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2864
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2865
53
        GIR_EraseFromParent, /*InsnID*/0,
2866
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2867
53
        // GIR_Coverage, 455,
2868
53
        GIR_Done,
2869
53
      // Label 191: @6642
2870
53
      GIM_Try, /*On fail goto*//*Label 192*/ 6723, // Rule ID 470 //
2871
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pk_u8_f32,
2872
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2873
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2874
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2875
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2876
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2877
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2878
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2879
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2880
53
        // (intrinsic_wo_chain:{ *:[i32] } 404:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CVT_PK_U8_F32:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
2881
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PK_U8_F32,
2882
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2883
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2884
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2885
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2886
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2887
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2888
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2889
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2890
53
        GIR_EraseFromParent, /*InsnID*/0,
2891
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2892
53
        // GIR_Coverage, 470,
2893
53
        GIR_Done,
2894
53
      // Label 192: @6723
2895
53
      GIM_Try, /*On fail goto*//*Label 193*/ 6773, // Rule ID 442 //
2896
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_lerp,
2897
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2898
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2899
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2900
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2901
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2902
53
        // (intrinsic_wo_chain:{ *:[i32] } 905:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_LERP_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
2903
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LERP_U8,
2904
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2905
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2906
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2907
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2908
53
        GIR_EraseFromParent, /*InsnID*/0,
2909
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2910
53
        // GIR_Coverage, 442,
2911
53
        GIR_Done,
2912
53
      // Label 193: @6773
2913
53
      GIM_Try, /*On fail goto*//*Label 194*/ 6823, // Rule ID 459 //
2914
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_alignbit,
2915
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2916
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2917
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2918
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2919
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2920
53
        // (intrinsic_wo_chain:{ *:[i32] } 373:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBIT_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
2921
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBIT_B32,
2922
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2923
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2924
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2925
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2926
53
        GIR_EraseFromParent, /*InsnID*/0,
2927
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2928
53
        // GIR_Coverage, 459,
2929
53
        GIR_Done,
2930
53
      // Label 194: @6823
2931
53
      GIM_Try, /*On fail goto*//*Label 195*/ 6873, // Rule ID 460 //
2932
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_alignbyte,
2933
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2934
53
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2935
53
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2936
53
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2937
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2938
53
        // (intrinsic_wo_chain:{ *:[i32] } 374:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBYTE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
2939
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBYTE_B32,
2940
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2941
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2942
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2943
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2944
53
        GIR_EraseFromParent, /*InsnID*/0,
2945
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2946
53
        // GIR_Coverage, 460,
2947
53
        GIR_Done,
2948
53
      // Label 195: @6873
2949
53
      GIM_Reject,
2950
53
    // Label 179: @6874
2951
53
    GIM_Reject,
2952
53
    // Label 8: @6875
2953
53
    GIM_Try, /*On fail goto*//*Label 196*/ 6895, // Rule ID 53 //
2954
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2955
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_barrier,
2956
53
      // (intrinsic_void 941:{ *:[iPTR] })  =>  (S_BARRIER)
2957
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_BARRIER,
2958
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2959
53
      GIR_EraseFromParent, /*InsnID*/0,
2960
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2961
53
      // GIR_Coverage, 53,
2962
53
      GIR_Done,
2963
53
    // Label 196: @6895
2964
53
    GIM_Try, /*On fail goto*//*Label 197*/ 6915, // Rule ID 505 //
2965
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2966
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_inv,
2967
53
      // (intrinsic_void 943:{ *:[iPTR] })  =>  (S_DCACHE_INV)
2968
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV,
2969
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2970
53
      GIR_EraseFromParent, /*InsnID*/0,
2971
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2972
53
      // GIR_Coverage, 505,
2973
53
      GIR_Done,
2974
53
    // Label 197: @6915
2975
53
    GIM_Try, /*On fail goto*//*Label 198*/ 6935, // Rule ID 506 //
2976
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isCIVI,
2977
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_inv_vol,
2978
53
      // (intrinsic_void 944:{ *:[iPTR] })  =>  (S_DCACHE_INV_VOL)
2979
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV_VOL,
2980
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2981
53
      GIR_EraseFromParent, /*InsnID*/0,
2982
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2983
53
      // GIR_Coverage, 506,
2984
53
      GIR_Done,
2985
53
    // Label 198: @6935
2986
53
    GIM_Try, /*On fail goto*//*Label 199*/ 6955, // Rule ID 507 //
2987
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
2988
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_wb,
2989
53
      // (intrinsic_void 945:{ *:[iPTR] })  =>  (S_DCACHE_WB)
2990
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB,
2991
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2992
53
      GIR_EraseFromParent, /*InsnID*/0,
2993
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2994
53
      // GIR_Coverage, 507,
2995
53
      GIR_Done,
2996
53
    // Label 199: @6955
2997
53
    GIM_Try, /*On fail goto*//*Label 200*/ 6975, // Rule ID 508 //
2998
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
2999
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_wb_vol,
3000
53
      // (intrinsic_void 946:{ *:[iPTR] })  =>  (S_DCACHE_WB_VOL)
3001
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB_VOL,
3002
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3003
53
      GIR_EraseFromParent, /*InsnID*/0,
3004
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3005
53
      // GIR_Coverage, 508,
3006
53
      GIR_Done,
3007
53
    // Label 200: @6975
3008
53
    GIM_Try, /*On fail goto*//*Label 201*/ 6995, // Rule ID 638 //
3009
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isSI,
3010
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1_sc,
3011
53
      // (intrinsic_void 394:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_SC)
3012
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_SC,
3013
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3014
53
      GIR_EraseFromParent, /*InsnID*/0,
3015
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3016
53
      // GIR_Coverage, 638,
3017
53
      GIR_Done,
3018
53
    // Label 201: @6995
3019
53
    GIM_Try, /*On fail goto*//*Label 202*/ 7015, // Rule ID 639 //
3020
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3021
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1,
3022
53
      // (intrinsic_void 393:{ *:[iPTR] })  =>  (BUFFER_WBINVL1)
3023
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1,
3024
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3025
53
      GIR_EraseFromParent, /*InsnID*/0,
3026
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3027
53
      // GIR_Coverage, 639,
3028
53
      GIR_Done,
3029
53
    // Label 202: @7015
3030
53
    GIM_Try, /*On fail goto*//*Label 203*/ 7035, // Rule ID 640 //
3031
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isCIVI,
3032
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1_vol,
3033
53
      // (intrinsic_void 395:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_VOL)
3034
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_VOL,
3035
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3036
53
      GIR_EraseFromParent, /*InsnID*/0,
3037
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3038
53
      // GIR_Coverage, 640,
3039
53
      GIR_Done,
3040
53
    // Label 203: @7035
3041
53
    GIM_Try, /*On fail goto*//*Label 204*/ 7055, // Rule ID 653 //
3042
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3043
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_wave_barrier,
3044
53
      // (intrinsic_void 993:{ *:[iPTR] })  =>  (WAVE_BARRIER)
3045
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::WAVE_BARRIER,
3046
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3047
53
      GIR_EraseFromParent, /*InsnID*/0,
3048
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3049
53
      // GIR_Coverage, 653,
3050
53
      GIR_Done,
3051
53
    // Label 204: @7055
3052
53
    GIM_Try, /*On fail goto*//*Label 205*/ 7075, // Rule ID 662 //
3053
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3054
53
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_unreachable,
3055
53
      // (intrinsic_void 991:{ *:[iPTR] })  =>  (SI_MASKED_UNREACHABLE)
3056
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_MASKED_UNREACHABLE,
3057
53
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3058
53
      GIR_EraseFromParent, /*InsnID*/0,
3059
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3060
53
      // GIR_Coverage, 662,
3061
53
      GIR_Done,
3062
53
    // Label 205: @7075
3063
53
    GIM_Try, /*On fail goto*//*Label 206*/ 7173,
3064
53
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
3065
53
      GIM_Try, /*On fail goto*//*Label 207*/ 7112, // Rule ID 504 //
3066
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3067
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_memtime,
3068
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
3069
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64_XEXECRegClassID,
3070
53
        // (intrinsic_w_chain:{ *:[i64] } 952:{ *:[iPTR] })  =>  (S_MEMTIME:{ *:[i64] })
3071
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMTIME,
3072
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3073
53
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3074
53
        GIR_EraseFromParent, /*InsnID*/0,
3075
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3076
53
        // GIR_Coverage, 504,
3077
53
        GIR_Done,
3078
53
      // Label 207: @7112
3079
53
      GIM_Try, /*On fail goto*//*Label 208*/ 7144, // Rule ID 509 //
3080
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
3081
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_memrealtime,
3082
53
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
3083
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64_XEXECRegClassID,
3084
53
        // (intrinsic_w_chain:{ *:[i64] } 951:{ *:[iPTR] })  =>  (S_MEMREALTIME:{ *:[i64] })
3085
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMREALTIME,
3086
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3087
53
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3088
53
        GIR_EraseFromParent, /*InsnID*/0,
3089
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3090
53
        // GIR_Coverage, 509,
3091
53
        GIR_Done,
3092
53
      // Label 208: @7144
3093
53
      GIM_Try, /*On fail goto*//*Label 209*/ 7172, // Rule ID 657 //
3094
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3095
53
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_end_cf,
3096
53
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3097
53
        // (intrinsic_void 421:{ *:[iPTR] }, i64:{ *:[i64] }:$saved)  =>  (SI_END_CF i64:{ *:[i64] }:$saved)
3098
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_END_CF,
3099
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // saved
3100
53
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3101
53
        GIR_EraseFromParent, /*InsnID*/0,
3102
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3103
53
        // GIR_Coverage, 657,
3104
53
        GIR_Done,
3105
53
      // Label 209: @7172
3106
53
      GIM_Reject,
3107
53
    // Label 206: @7173
3108
53
    GIM_Reject,
3109
53
    // Label 9: @7174
3110
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 212*/ 7230,
3111
53
    /*GILLT_s16*//*Label 210*/ 7182,
3112
53
    /*GILLT_s32*//*Label 211*/ 7206,
3113
53
    // Label 210: @7182
3114
53
    GIM_Try, /*On fail goto*//*Label 213*/ 7205, // Rule ID 815 //
3115
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3116
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3117
53
      // MIs[0] Operand 1
3118
53
      // No operand predicates
3119
53
      // (imm:{ *:[i16] }):$imm  =>  (S_MOV_B32:{ *:[i16] } (imm:{ *:[i16] }):$imm)
3120
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
3121
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3122
53
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
3123
53
      GIR_EraseFromParent, /*InsnID*/0,
3124
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3125
53
      // GIR_Coverage, 815,
3126
53
      GIR_Done,
3127
53
    // Label 213: @7205
3128
53
    GIM_Reject,
3129
53
    // Label 211: @7206
3130
53
    GIM_Try, /*On fail goto*//*Label 214*/ 7229, // Rule ID 1678 //
3131
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3132
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3133
53
      // MIs[0] Operand 1
3134
53
      // No operand predicates
3135
53
      // (imm:{ *:[i32] }):$imm  =>  (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
3136
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
3137
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3138
53
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
3139
53
      GIR_EraseFromParent, /*InsnID*/0,
3140
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3141
53
      // GIR_Coverage, 1678,
3142
53
      GIR_Done,
3143
53
    // Label 214: @7229
3144
53
    GIM_Reject,
3145
53
    // Label 212: @7230
3146
53
    GIM_Reject,
3147
53
    // Label 10: @7231
3148
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 217*/ 7293,
3149
53
    /*GILLT_s32*//*Label 215*/ 7239,
3150
53
    /*GILLT_s64*//*Label 216*/ 7266,
3151
53
    // Label 215: @7239
3152
53
    GIM_Try, /*On fail goto*//*Label 218*/ 7265, // Rule ID 433 //
3153
53
      GIM_CheckFeatures, GIFBS_isSICI,
3154
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3155
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3156
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3157
53
      // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3158
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_LSHL_B32_e64,
3159
53
      GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
3160
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3161
53
      // GIR_Coverage, 433,
3162
53
      GIR_Done,
3163
53
    // Label 218: @7265
3164
53
    GIM_Reject,
3165
53
    // Label 216: @7266
3166
53
    GIM_Try, /*On fail goto*//*Label 219*/ 7292, // Rule ID 29 //
3167
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3168
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3169
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3170
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3171
53
      // (shl:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_LSHL_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
3172
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_LSHL_B64,
3173
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3174
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3175
53
      // GIR_Coverage, 29,
3176
53
      GIR_Done,
3177
53
    // Label 219: @7292
3178
53
    GIM_Reject,
3179
53
    // Label 217: @7293
3180
53
    GIM_Reject,
3181
53
    // Label 11: @7294
3182
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 222*/ 7356,
3183
53
    /*GILLT_s32*//*Label 220*/ 7302,
3184
53
    /*GILLT_s64*//*Label 221*/ 7329,
3185
53
    // Label 220: @7302
3186
53
    GIM_Try, /*On fail goto*//*Label 223*/ 7328, // Rule ID 429 //
3187
53
      GIM_CheckFeatures, GIFBS_isSICI,
3188
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3189
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3190
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3191
53
      // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3192
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_LSHR_B32_e64,
3193
53
      GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
3194
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3195
53
      // GIR_Coverage, 429,
3196
53
      GIR_Done,
3197
53
    // Label 223: @7328
3198
53
    GIM_Reject,
3199
53
    // Label 221: @7329
3200
53
    GIM_Try, /*On fail goto*//*Label 224*/ 7355, // Rule ID 31 //
3201
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3202
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3203
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3204
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3205
53
      // (srl:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_LSHR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
3206
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_LSHR_B64,
3207
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3208
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3209
53
      // GIR_Coverage, 31,
3210
53
      GIR_Done,
3211
53
    // Label 224: @7355
3212
53
    GIM_Reject,
3213
53
    // Label 222: @7356
3214
53
    GIM_Reject,
3215
53
    // Label 12: @7357
3216
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 227*/ 7560,
3217
53
    /*GILLT_s32*//*Label 225*/ 7365,
3218
53
    /*GILLT_s64*//*Label 226*/ 7533,
3219
53
    // Label 225: @7365
3220
53
    GIM_Try, /*On fail goto*//*Label 228*/ 7532,
3221
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3222
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3223
53
      GIM_Try, /*On fail goto*//*Label 229*/ 7412, // Rule ID 1906 //
3224
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isSICI,
3225
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3226
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
3227
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vsrc0,
3228
53
        // (sra:{ *:[i32] } (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0), VGPR_32:{ *:[i32] }:$src1)  =>  (V_ASHR_I32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3229
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHR_I32_e32,
3230
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3231
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3232
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3233
53
        GIR_EraseFromParent, /*InsnID*/0,
3234
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3235
53
        // GIR_Coverage, 1906,
3236
53
        GIR_Done,
3237
53
      // Label 229: @7412
3238
53
      GIM_Try, /*On fail goto*//*Label 230*/ 7449, // Rule ID 1907 //
3239
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3240
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3241
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
3242
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
3243
53
        // (sra:{ *:[i32] } VGPR_32:{ *:[i32] }:$src1, (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_ASHRREV_I32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3244
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I32_e32,
3245
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3246
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3247
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3248
53
        GIR_EraseFromParent, /*InsnID*/0,
3249
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3250
53
        // GIR_Coverage, 1907,
3251
53
        GIR_Done,
3252
53
      // Label 230: @7449
3253
53
      GIM_Try, /*On fail goto*//*Label 231*/ 7487, // Rule ID 1908 //
3254
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3255
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3256
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vcsrc,
3257
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vcsrc,
3258
53
        // (sra:{ *:[i32] } (sd_vcsrc:{ *:[i32] } i32:{ *:[i32] }:$src0), (sd_vcsrc:{ *:[i32] } i32:{ *:[i32] }:$src1))  =>  (V_ASHRREV_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)
3259
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I32_e64,
3260
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3261
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3262
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3263
53
        GIR_EraseFromParent, /*InsnID*/0,
3264
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3265
53
        // GIR_Coverage, 1908,
3266
53
        GIR_Done,
3267
53
      // Label 231: @7487
3268
53
      GIM_Try, /*On fail goto*//*Label 232*/ 7513, // Rule ID 1905 //
3269
53
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3270
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3271
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
3272
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
3273
53
        // (sra:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)  =>  (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3274
53
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ASHR_I32,
3275
53
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3276
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3277
53
        // GIR_Coverage, 1905,
3278
53
        GIR_Done,
3279
53
      // Label 232: @7513
3280
53
      GIM_Try, /*On fail goto*//*Label 233*/ 7531, // Rule ID 431 //
3281
53
        GIM_CheckFeatures, GIFBS_isSICI,
3282
53
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3283
53
        // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3284
53
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_ASHR_I32_e64,
3285
53
        GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
3286
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3287
53
        // GIR_Coverage, 431,
3288
53
        GIR_Done,
3289
53
      // Label 233: @7531
3290
53
      GIM_Reject,
3291
53
    // Label 228: @7532
3292
53
    GIM_Reject,
3293
53
    // Label 226: @7533
3294
53
    GIM_Try, /*On fail goto*//*Label 234*/ 7559, // Rule ID 33 //
3295
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3296
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3297
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3298
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3299
53
      // (sra:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_ASHR_I64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
3300
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ASHR_I64,
3301
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3302
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3303
53
      // GIR_Coverage, 33,
3304
53
      GIR_Done,
3305
53
    // Label 234: @7559
3306
53
    GIM_Reject,
3307
53
    // Label 227: @7560
3308
53
    GIM_Reject,
3309
53
    // Label 13: @7561
3310
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 238*/ 7910,
3311
53
    /*GILLT_s16*//*Label 235*/ 7570,
3312
53
    /*GILLT_s32*//*Label 236*/ 7682,
3313
53
    /*GILLT_s64*//*Label 237*/ 7798,
3314
53
    // Label 235: @7570
3315
53
    GIM_Try, /*On fail goto*//*Label 239*/ 7681,
3316
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3317
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3318
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3319
53
      GIM_Try, /*On fail goto*//*Label 240*/ 7632, // Rule ID 435 //
3320
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3321
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3322
53
        // (fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3323
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
3324
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3325
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3326
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3327
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3328
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3329
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3330
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3331
53
        GIR_EraseFromParent, /*InsnID*/0,
3332
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3333
53
        // GIR_Coverage, 435,
3334
53
        GIR_Done,
3335
53
      // Label 240: @7632
3336
53
      GIM_Try, /*On fail goto*//*Label 241*/ 7680, // Rule ID 1921 //
3337
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3338
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3339
53
        // (fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3340
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
3341
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3342
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3343
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3344
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3345
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3346
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3347
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3348
53
        GIR_EraseFromParent, /*InsnID*/0,
3349
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3350
53
        // GIR_Coverage, 1921,
3351
53
        GIR_Done,
3352
53
      // Label 241: @7680
3353
53
      GIM_Reject,
3354
53
    // Label 239: @7681
3355
53
    GIM_Reject,
3356
53
    // Label 236: @7682
3357
53
    GIM_Try, /*On fail goto*//*Label 242*/ 7797,
3358
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3359
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3360
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3361
53
      GIM_Try, /*On fail goto*//*Label 243*/ 7746, // Rule ID 388 //
3362
53
        GIM_CheckFeatures, GIFBS_isGCN,
3363
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3364
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3365
53
        // (fadd:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3366
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
3367
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3368
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3369
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3370
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3371
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3372
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3373
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3374
53
        GIR_EraseFromParent, /*InsnID*/0,
3375
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3376
53
        // GIR_Coverage, 388,
3377
53
        GIR_Done,
3378
53
      // Label 243: @7746
3379
53
      GIM_Try, /*On fail goto*//*Label 244*/ 7796, // Rule ID 1916 //
3380
53
        GIM_CheckFeatures, GIFBS_isGCN,
3381
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3382
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3383
53
        // (fadd:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3384
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
3385
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3386
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3387
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3388
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3389
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3390
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3391
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3392
53
        GIR_EraseFromParent, /*InsnID*/0,
3393
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3394
53
        // GIR_Coverage, 1916,
3395
53
        GIR_Done,
3396
53
      // Label 244: @7796
3397
53
      GIM_Reject,
3398
53
    // Label 242: @7797
3399
53
    GIM_Reject,
3400
53
    // Label 237: @7798
3401
53
    GIM_Try, /*On fail goto*//*Label 245*/ 7909,
3402
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3403
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3404
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3405
53
      GIM_Try, /*On fail goto*//*Label 246*/ 7860, // Rule ID 444 //
3406
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3407
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3408
53
        // (fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3409
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
3410
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3411
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3412
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3413
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3414
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3415
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3416
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3417
53
        GIR_EraseFromParent, /*InsnID*/0,
3418
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3419
53
        // GIR_Coverage, 444,
3420
53
        GIR_Done,
3421
53
      // Label 246: @7860
3422
53
      GIM_Try, /*On fail goto*//*Label 247*/ 7908, // Rule ID 1925 //
3423
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3424
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3425
53
        // (fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3426
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
3427
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3428
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3429
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3430
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3431
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3432
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3433
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3434
53
        GIR_EraseFromParent, /*InsnID*/0,
3435
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3436
53
        // GIR_Coverage, 1925,
3437
53
        GIR_Done,
3438
53
      // Label 247: @7908
3439
53
      GIM_Reject,
3440
53
    // Label 245: @7909
3441
53
    GIM_Reject,
3442
53
    // Label 238: @7910
3443
53
    GIM_Reject,
3444
53
    // Label 14: @7911
3445
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 250*/ 8043,
3446
53
    /*GILLT_s16*//*Label 248*/ 7919,
3447
53
    /*GILLT_s32*//*Label 249*/ 7980,
3448
53
    // Label 248: @7919
3449
53
    GIM_Try, /*On fail goto*//*Label 251*/ 7979, // Rule ID 436 //
3450
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3451
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3452
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3453
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3454
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3455
53
      // (fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3456
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F16_e64,
3457
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3458
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3459
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3460
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3461
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3462
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3463
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3464
53
      GIR_EraseFromParent, /*InsnID*/0,
3465
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3466
53
      // GIR_Coverage, 436,
3467
53
      GIR_Done,
3468
53
    // Label 251: @7979
3469
53
    GIM_Reject,
3470
53
    // Label 249: @7980
3471
53
    GIM_Try, /*On fail goto*//*Label 252*/ 8042, // Rule ID 389 //
3472
53
      GIM_CheckFeatures, GIFBS_isGCN,
3473
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3474
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3475
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3476
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3477
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3478
53
      // (fsub:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3479
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F32_e64,
3480
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3481
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3482
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3483
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3484
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3485
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3486
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3487
53
      GIR_EraseFromParent, /*InsnID*/0,
3488
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3489
53
      // GIR_Coverage, 389,
3490
53
      GIR_Done,
3491
53
    // Label 252: @8042
3492
53
    GIM_Reject,
3493
53
    // Label 250: @8043
3494
53
    GIM_Reject,
3495
53
    // Label 15: @8044
3496
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 256*/ 8393,
3497
53
    /*GILLT_s16*//*Label 253*/ 8053,
3498
53
    /*GILLT_s32*//*Label 254*/ 8165,
3499
53
    /*GILLT_s64*//*Label 255*/ 8281,
3500
53
    // Label 253: @8053
3501
53
    GIM_Try, /*On fail goto*//*Label 257*/ 8164,
3502
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3503
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3504
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3505
53
      GIM_Try, /*On fail goto*//*Label 258*/ 8115, // Rule ID 437 //
3506
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3507
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3508
53
        // (fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3509
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
3510
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3511
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3512
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3513
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3514
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3515
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3516
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3517
53
        GIR_EraseFromParent, /*InsnID*/0,
3518
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3519
53
        // GIR_Coverage, 437,
3520
53
        GIR_Done,
3521
53
      // Label 258: @8115
3522
53
      GIM_Try, /*On fail goto*//*Label 259*/ 8163, // Rule ID 1922 //
3523
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3524
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3525
53
        // (fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3526
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
3527
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3528
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3529
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3530
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3531
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3532
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3533
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3534
53
        GIR_EraseFromParent, /*InsnID*/0,
3535
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3536
53
        // GIR_Coverage, 1922,
3537
53
        GIR_Done,
3538
53
      // Label 259: @8163
3539
53
      GIM_Reject,
3540
53
    // Label 257: @8164
3541
53
    GIM_Reject,
3542
53
    // Label 254: @8165
3543
53
    GIM_Try, /*On fail goto*//*Label 260*/ 8280,
3544
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3545
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3546
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3547
53
      GIM_Try, /*On fail goto*//*Label 261*/ 8229, // Rule ID 391 //
3548
53
        GIM_CheckFeatures, GIFBS_isGCN,
3549
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3550
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3551
53
        // (fmul:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3552
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
3553
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3554
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3555
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3556
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3557
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3558
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3559
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3560
53
        GIR_EraseFromParent, /*InsnID*/0,
3561
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3562
53
        // GIR_Coverage, 391,
3563
53
        GIR_Done,
3564
53
      // Label 261: @8229
3565
53
      GIM_Try, /*On fail goto*//*Label 262*/ 8279, // Rule ID 1918 //
3566
53
        GIM_CheckFeatures, GIFBS_isGCN,
3567
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3568
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3569
53
        // (fmul:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3570
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
3571
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3572
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3573
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3574
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3575
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3576
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3577
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3578
53
        GIR_EraseFromParent, /*InsnID*/0,
3579
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3580
53
        // GIR_Coverage, 1918,
3581
53
        GIR_Done,
3582
53
      // Label 262: @8279
3583
53
      GIM_Reject,
3584
53
    // Label 260: @8280
3585
53
    GIM_Reject,
3586
53
    // Label 255: @8281
3587
53
    GIM_Try, /*On fail goto*//*Label 263*/ 8392,
3588
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3589
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3590
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3591
53
      GIM_Try, /*On fail goto*//*Label 264*/ 8343, // Rule ID 445 //
3592
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3593
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3594
53
        // (fmul:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3595
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
3596
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3597
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3598
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3599
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3600
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3601
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3602
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3603
53
        GIR_EraseFromParent, /*InsnID*/0,
3604
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3605
53
        // GIR_Coverage, 445,
3606
53
        GIR_Done,
3607
53
      // Label 264: @8343
3608
53
      GIM_Try, /*On fail goto*//*Label 265*/ 8391, // Rule ID 1926 //
3609
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3610
53
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3611
53
        // (fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3612
53
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
3613
53
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3614
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3615
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3616
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3617
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3618
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3619
53
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3620
53
        GIR_EraseFromParent, /*InsnID*/0,
3621
53
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3622
53
        // GIR_Coverage, 1926,
3623
53
        GIR_Done,
3624
53
      // Label 265: @8391
3625
53
      GIM_Reject,
3626
53
    // Label 263: @8392
3627
53
    GIM_Reject,
3628
53
    // Label 256: @8393
3629
53
    GIM_Reject,
3630
53
    // Label 16: @8394
3631
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 269*/ 8637,
3632
53
    /*GILLT_s16*//*Label 266*/ 8403,
3633
53
    /*GILLT_s32*//*Label 267*/ 8481,
3634
53
    /*GILLT_s64*//*Label 268*/ 8559,
3635
53
    // Label 266: @8403
3636
53
    GIM_Try, /*On fail goto*//*Label 270*/ 8480, // Rule ID 478 //
3637
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3638
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3639
53
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
3640
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3641
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3642
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3643
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3644
53
      // (fma:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F16:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3645
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F16,
3646
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3647
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3648
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3649
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3650
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3651
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3652
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3653
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3654
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3655
53
      GIR_EraseFromParent, /*InsnID*/0,
3656
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3657
53
      // GIR_Coverage, 478,
3658
53
      GIR_Done,
3659
53
    // Label 270: @8480
3660
53
    GIM_Reject,
3661
53
    // Label 267: @8481
3662
53
    GIM_Try, /*On fail goto*//*Label 271*/ 8558, // Rule ID 441 //
3663
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3664
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3665
53
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
3666
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3667
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3668
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3669
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3670
53
      // (fma:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3671
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F32,
3672
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3673
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3674
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3675
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3676
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3677
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3678
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3679
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3680
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3681
53
      GIR_EraseFromParent, /*InsnID*/0,
3682
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3683
53
      // GIR_Coverage, 441,
3684
53
      GIR_Done,
3685
53
    // Label 271: @8558
3686
53
    GIM_Reject,
3687
53
    // Label 268: @8559
3688
53
    GIM_Try, /*On fail goto*//*Label 272*/ 8636, // Rule ID 443 //
3689
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3690
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3691
53
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
3692
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3693
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3694
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3695
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3696
53
      // (fma:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3697
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F64,
3698
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3699
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3700
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3701
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3702
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3703
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3704
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3705
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3706
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3707
53
      GIR_EraseFromParent, /*InsnID*/0,
3708
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3709
53
      // GIR_Coverage, 443,
3710
53
      GIR_Done,
3711
53
    // Label 272: @8636
3712
53
    GIM_Reject,
3713
53
    // Label 269: @8637
3714
53
    GIM_Reject,
3715
53
    // Label 17: @8638
3716
53
    GIM_Try, /*On fail goto*//*Label 273*/ 8710, // Rule ID 1686 //
3717
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3718
53
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3719
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3720
53
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3721
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3722
53
      // (fpow:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)  =>  (V_EXP_F32_e32:{ *:[f32] } (V_MUL_LEGACY_F32_e32:{ *:[i16] } f32:{ *:[f32] }:$src1, (V_LOG_F32_e32:{ *:[i16] } f32:{ *:[f32] }:$src0)))
3723
53
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
3724
53
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
3725
53
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/AMDGPU::V_LOG_F32_e32,
3726
53
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3727
53
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src0
3728
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3729
53
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_MUL_LEGACY_F32_e32,
3730
53
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3731
53
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src1
3732
53
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3733
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3734
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e32,
3735
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3736
53
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3737
53
      GIR_EraseFromParent, /*InsnID*/0,
3738
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3739
53
      // GIR_Coverage, 1686,
3740
53
      GIR_Done,
3741
53
    // Label 273: @8710
3742
53
    GIM_Reject,
3743
53
    // Label 18: @8711
3744
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 276*/ 8807,
3745
53
    /*GILLT_s16*//*Label 274*/ 8719,
3746
53
    /*GILLT_s32*//*Label 275*/ 8763,
3747
53
    // Label 274: @8719
3748
53
    GIM_Try, /*On fail goto*//*Label 277*/ 8762, // Rule ID 378 //
3749
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3750
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3751
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3752
53
      // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3753
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F16_e64,
3754
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3755
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3756
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3757
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3758
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3759
53
      GIR_EraseFromParent, /*InsnID*/0,
3760
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3761
53
      // GIR_Coverage, 378,
3762
53
      GIR_Done,
3763
53
    // Label 277: @8762
3764
53
    GIM_Reject,
3765
53
    // Label 275: @8763
3766
53
    GIM_Try, /*On fail goto*//*Label 278*/ 8806, // Rule ID 345 //
3767
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3768
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3769
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3770
53
      // (fexp2:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3771
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e64,
3772
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3773
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3774
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3775
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3776
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3777
53
      GIR_EraseFromParent, /*InsnID*/0,
3778
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3779
53
      // GIR_Coverage, 345,
3780
53
      GIR_Done,
3781
53
    // Label 278: @8806
3782
53
    GIM_Reject,
3783
53
    // Label 276: @8807
3784
53
    GIM_Reject,
3785
53
    // Label 19: @8808
3786
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 281*/ 8904,
3787
53
    /*GILLT_s16*//*Label 279*/ 8816,
3788
53
    /*GILLT_s32*//*Label 280*/ 8860,
3789
53
    // Label 279: @8816
3790
53
    GIM_Try, /*On fail goto*//*Label 282*/ 8859, // Rule ID 377 //
3791
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3792
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3793
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3794
53
      // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3795
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F16_e64,
3796
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3797
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3798
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3799
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3800
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3801
53
      GIR_EraseFromParent, /*InsnID*/0,
3802
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3803
53
      // GIR_Coverage, 377,
3804
53
      GIR_Done,
3805
53
    // Label 282: @8859
3806
53
    GIM_Reject,
3807
53
    // Label 280: @8860
3808
53
    GIM_Try, /*On fail goto*//*Label 283*/ 8903, // Rule ID 346 //
3809
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3810
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3811
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3812
53
      // (flog2:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3813
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F32_e64,
3814
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3815
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3816
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3817
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3818
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3819
53
      GIR_EraseFromParent, /*InsnID*/0,
3820
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3821
53
      // GIR_Coverage, 346,
3822
53
      GIR_Done,
3823
53
    // Label 283: @8903
3824
53
    GIM_Reject,
3825
53
    // Label 281: @8904
3826
53
    GIM_Reject,
3827
53
    // Label 20: @8905
3828
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 286*/ 9001,
3829
53
    /*GILLT_s32*//*Label 284*/ 8913,
3830
53
    /*GILLT_s64*//*Label 285*/ 8957,
3831
53
    // Label 284: @8913
3832
53
    GIM_Try, /*On fail goto*//*Label 287*/ 8956, // Rule ID 329 //
3833
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3834
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3835
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3836
53
      // (fpextend:{ *:[f32] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3837
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F16_e64,
3838
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3839
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3840
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3841
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3842
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3843
53
      GIR_EraseFromParent, /*InsnID*/0,
3844
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3845
53
      // GIR_Coverage, 329,
3846
53
      GIR_Done,
3847
53
    // Label 287: @8956
3848
53
    GIM_Reject,
3849
53
    // Label 285: @8957
3850
53
    GIM_Try, /*On fail goto*//*Label 288*/ 9000, // Rule ID 333 //
3851
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3852
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3853
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3854
53
      // (fpextend:{ *:[f64] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_F32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3855
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_F32_e64,
3856
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3857
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3858
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3859
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3860
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3861
53
      GIR_EraseFromParent, /*InsnID*/0,
3862
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3863
53
      // GIR_Coverage, 333,
3864
53
      GIR_Done,
3865
53
    // Label 288: @9000
3866
53
    GIM_Reject,
3867
53
    // Label 286: @9001
3868
53
    GIM_Reject,
3869
53
    // Label 21: @9002
3870
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 291*/ 9098,
3871
53
    /*GILLT_s16*//*Label 289*/ 9010,
3872
53
    /*GILLT_s32*//*Label 290*/ 9054,
3873
53
    // Label 289: @9010
3874
53
    GIM_Try, /*On fail goto*//*Label 292*/ 9053, // Rule ID 328 //
3875
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3876
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3877
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3878
53
      // (fpround:{ *:[f16] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_F32_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3879
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_F32_e64,
3880
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3881
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3882
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3883
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3884
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3885
53
      GIR_EraseFromParent, /*InsnID*/0,
3886
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3887
53
      // GIR_Coverage, 328,
3888
53
      GIR_Done,
3889
53
    // Label 292: @9053
3890
53
    GIM_Reject,
3891
53
    // Label 290: @9054
3892
53
    GIM_Try, /*On fail goto*//*Label 293*/ 9097, // Rule ID 332 //
3893
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3894
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3895
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3896
53
      // (fpround:{ *:[f32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F64_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3897
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F64_e64,
3898
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3899
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3900
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3901
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3902
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3903
53
      GIR_EraseFromParent, /*InsnID*/0,
3904
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3905
53
      // GIR_Coverage, 332,
3906
53
      GIR_Done,
3907
53
    // Label 293: @9097
3908
53
    GIM_Reject,
3909
53
    // Label 291: @9098
3910
53
    GIM_Reject,
3911
53
    // Label 22: @9099
3912
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 297*/ 9332,
3913
53
    /*GILLT_s1*//*Label 294*/ 9108,
3914
53
    /*GILLT_s16*//*Label 295*/ 9201,
3915
53
    /*GILLT_s32*//*Label 296*/ 9245,
3916
53
    // Label 294: @9108
3917
53
    GIM_Try, /*On fail goto*//*Label 298*/ 9154, // Rule ID 1728 //
3918
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3919
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3920
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3921
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3922
53
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 3212836864:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
3923
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
3924
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3925
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3926
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/3212836864,
3927
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3928
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3929
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3930
53
      GIR_EraseFromParent, /*InsnID*/0,
3931
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3932
53
      // GIR_Coverage, 1728,
3933
53
      GIR_Done,
3934
53
    // Label 298: @9154
3935
53
    GIM_Try, /*On fail goto*//*Label 299*/ 9200, // Rule ID 1730 //
3936
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3937
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3938
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3939
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3940
53
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, -4616189618054758400:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
3941
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
3942
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3943
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3944
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/-4616189618054758400,
3945
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3946
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3947
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3948
53
      GIR_EraseFromParent, /*InsnID*/0,
3949
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3950
53
      // GIR_Coverage, 1730,
3951
53
      GIR_Done,
3952
53
    // Label 299: @9200
3953
53
    GIM_Reject,
3954
53
    // Label 295: @9201
3955
53
    GIM_Try, /*On fail goto*//*Label 300*/ 9244, // Rule ID 373 //
3956
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3957
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3958
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3959
53
      // (fp_to_sint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3960
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I16_F16_e64,
3961
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3962
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3963
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3964
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3965
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3966
53
      GIR_EraseFromParent, /*InsnID*/0,
3967
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3968
53
      // GIR_Coverage, 373,
3969
53
      GIR_Done,
3970
53
    // Label 300: @9244
3971
53
    GIM_Reject,
3972
53
    // Label 296: @9245
3973
53
    GIM_Try, /*On fail goto*//*Label 301*/ 9288, // Rule ID 322 //
3974
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3975
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3976
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3977
53
      // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3978
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F64_e64,
3979
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3980
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3981
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3982
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3983
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3984
53
      GIR_EraseFromParent, /*InsnID*/0,
3985
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3986
53
      // GIR_Coverage, 322,
3987
53
      GIR_Done,
3988
53
    // Label 301: @9288
3989
53
    GIM_Try, /*On fail goto*//*Label 302*/ 9331, // Rule ID 327 //
3990
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3991
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3992
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3993
53
      // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3994
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F32_e64,
3995
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3996
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3997
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3998
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3999
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4000
53
      GIR_EraseFromParent, /*InsnID*/0,
4001
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4002
53
      // GIR_Coverage, 327,
4003
53
      GIR_Done,
4004
53
    // Label 302: @9331
4005
53
    GIM_Reject,
4006
53
    // Label 297: @9332
4007
53
    GIM_Reject,
4008
53
    // Label 23: @9333
4009
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 306*/ 9566,
4010
53
    /*GILLT_s1*//*Label 303*/ 9342,
4011
53
    /*GILLT_s16*//*Label 304*/ 9435,
4012
53
    /*GILLT_s32*//*Label 305*/ 9479,
4013
53
    // Label 303: @9342
4014
53
    GIM_Try, /*On fail goto*//*Label 307*/ 9388, // Rule ID 1727 //
4015
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
4016
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4017
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
4018
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
4019
53
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 1065353216:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
4020
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
4021
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
4022
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4023
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/1065353216,
4024
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4025
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4026
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4027
53
      GIR_EraseFromParent, /*InsnID*/0,
4028
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4029
53
      // GIR_Coverage, 1727,
4030
53
      GIR_Done,
4031
53
    // Label 307: @9388
4032
53
    GIM_Try, /*On fail goto*//*Label 308*/ 9434, // Rule ID 1729 //
4033
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
4034
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4035
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
4036
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
4037
53
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, 4607182418800017408:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
4038
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
4039
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
4040
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4041
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/4607182418800017408,
4042
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4043
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4044
53
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4045
53
      GIR_EraseFromParent, /*InsnID*/0,
4046
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4047
53
      // GIR_Coverage, 1729,
4048
53
      GIR_Done,
4049
53
    // Label 308: @9434
4050
53
    GIM_Reject,
4051
53
    // Label 304: @9435
4052
53
    GIM_Try, /*On fail goto*//*Label 309*/ 9478, // Rule ID 372 //
4053
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4054
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4055
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4056
53
      // (fp_to_uint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4057
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U16_F16_e64,
4058
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4059
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4060
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4061
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4062
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4063
53
      GIR_EraseFromParent, /*InsnID*/0,
4064
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4065
53
      // GIR_Coverage, 372,
4066
53
      GIR_Done,
4067
53
    // Label 309: @9478
4068
53
    GIM_Reject,
4069
53
    // Label 305: @9479
4070
53
    GIM_Try, /*On fail goto*//*Label 310*/ 9522, // Rule ID 326 //
4071
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4072
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4073
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4074
53
      // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4075
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F32_e64,
4076
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4077
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4078
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4079
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4080
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4081
53
      GIR_EraseFromParent, /*InsnID*/0,
4082
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4083
53
      // GIR_Coverage, 326,
4084
53
      GIR_Done,
4085
53
    // Label 310: @9522
4086
53
    GIM_Try, /*On fail goto*//*Label 311*/ 9565, // Rule ID 338 //
4087
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4088
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4089
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4090
53
      // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4091
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F64_e64,
4092
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4093
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4094
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4095
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4096
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4097
53
      GIR_EraseFromParent, /*InsnID*/0,
4098
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4099
53
      // GIR_Coverage, 338,
4100
53
      GIR_Done,
4101
53
    // Label 311: @9565
4102
53
    GIM_Reject,
4103
53
    // Label 306: @9566
4104
53
    GIM_Reject,
4105
53
    // Label 24: @9567
4106
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 315*/ 9696,
4107
53
    /*GILLT_s16*//*Label 312*/ 9576,
4108
53
    /*GILLT_s32*//*Label 313*/ 9616,
4109
53
    /*GILLT_s64*//*Label 314*/ 9656,
4110
53
    // Label 312: @9576
4111
53
    GIM_Try, /*On fail goto*//*Label 316*/ 9615, // Rule ID 371 //
4112
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4113
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4114
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4115
53
      // (sint_to_fp:{ *:[f16] } (VOP3OMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_I16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4116
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_I16_e64,
4117
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4118
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4119
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4120
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4121
53
      GIR_EraseFromParent, /*InsnID*/0,
4122
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4123
53
      // GIR_Coverage, 371,
4124
53
      GIR_Done,
4125
53
    // Label 316: @9615
4126
53
    GIM_Reject,
4127
53
    // Label 313: @9616
4128
53
    GIM_Try, /*On fail goto*//*Label 317*/ 9655, // Rule ID 324 //
4129
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4130
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4131
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4132
53
      // (sint_to_fp:{ *:[f32] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_I32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4133
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_I32_e64,
4134
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4135
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4136
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4137
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4138
53
      GIR_EraseFromParent, /*InsnID*/0,
4139
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4140
53
      // GIR_Coverage, 324,
4141
53
      GIR_Done,
4142
53
    // Label 317: @9655
4143
53
    GIM_Reject,
4144
53
    // Label 314: @9656
4145
53
    GIM_Try, /*On fail goto*//*Label 318*/ 9695, // Rule ID 323 //
4146
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4147
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4148
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4149
53
      // (sint_to_fp:{ *:[f64] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_I32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4150
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_I32_e64,
4151
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4152
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4153
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4154
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4155
53
      GIR_EraseFromParent, /*InsnID*/0,
4156
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4157
53
      // GIR_Coverage, 323,
4158
53
      GIR_Done,
4159
53
    // Label 318: @9695
4160
53
    GIM_Reject,
4161
53
    // Label 315: @9696
4162
53
    GIM_Reject,
4163
53
    // Label 25: @9697
4164
53
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 322*/ 9826,
4165
53
    /*GILLT_s16*//*Label 319*/ 9706,
4166
53
    /*GILLT_s32*//*Label 320*/ 9746,
4167
53
    /*GILLT_s64*//*Label 321*/ 9786,
4168
53
    // Label 319: @9706
4169
53
    GIM_Try, /*On fail goto*//*Label 323*/ 9745, // Rule ID 370 //
4170
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4171
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4172
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4173
53
      // (uint_to_fp:{ *:[f16] } (VOP3OMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_U16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4174
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_U16_e64,
4175
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4176
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4177
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4178
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4179
53
      GIR_EraseFromParent, /*InsnID*/0,
4180
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4181
53
      // GIR_Coverage, 370,
4182
53
      GIR_Done,
4183
53
    // Label 323: @9745
4184
53
    GIM_Reject,
4185
53
    // Label 320: @9746
4186
53
    GIM_Try, /*On fail goto*//*Label 324*/ 9785, // Rule ID 325 //
4187
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4188
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4189
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4190
53
      // (uint_to_fp:{ *:[f32] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_U32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4191
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_U32_e64,
4192
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4193
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4194
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4195
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4196
53
      GIR_EraseFromParent, /*InsnID*/0,
4197
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4198
53
      // GIR_Coverage, 325,
4199
53
      GIR_Done,
4200
53
    // Label 324: @9785
4201
53
    GIM_Reject,
4202
53
    // Label 321: @9786
4203
53
    GIM_Try, /*On fail goto*//*Label 325*/ 9825, // Rule ID 339 //
4204
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4205
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4206
53
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4207
53
      // (uint_to_fp:{ *:[f64] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_U32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4208
53
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_U32_e64,
4209
53
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4210
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4211
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4212
53
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4213
53
      GIR_EraseFromParent, /*InsnID*/0,
4214
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4215
53
      // GIR_Coverage, 339,
4216
53
      GIR_Done,
4217
53
    // Label 325: @9825
4218
53
    GIM_Reject,
4219
53
    // Label 322: @9826
4220
53
    GIM_Reject,
4221
53
    // Label 26: @9827
4222
53
    GIM_Try, /*On fail goto*//*Label 326*/ 9841, // Rule ID 52 //
4223
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
4224
53
      // MIs[0] simm16
4225
53
      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
4226
53
      // (br (bb:{ *:[Other] }):$simm16)  =>  (S_BRANCH (bb:{ *:[Other] }):$simm16)
4227
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_BRANCH,
4228
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4229
53
      // GIR_Coverage, 52,
4230
53
      GIR_Done,
4231
53
    // Label 326: @9841
4232
53
    GIM_Reject,
4233
53
    // Label 27: @9842
4234
53
    GIM_Try, /*On fail goto*//*Label 327*/ 9868, // Rule ID 4 //
4235
53
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
4236
53
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4237
53
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4238
53
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
4239
53
      // (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0)  =>  (S_BCNT1_I32_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
4240
53
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_BCNT1_I32_B32,
4241
53
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
4242
53
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4243
53
      // GIR_Coverage, 4,
4244
53
      GIR_Done,
4245
53
    // Label 327: @9868
4246
53
    GIM_Reject,
4247
53
    // Label 28: @9869
4248
53
    GIM_Reject,
4249
53
    };
4250
53
  return MatchTable0;
4251
53
}
4252
#endif // ifdef GET_GLOBALISEL_IMPL
4253
#ifdef GET_GLOBALISEL_PREDICATES_DECL
4254
PredicateBitset AvailableModuleFeatures;
4255
mutable PredicateBitset AvailableFunctionFeatures;
4256
53
PredicateBitset getAvailableFeatures() const {
4257
53
  return AvailableModuleFeatures | AvailableFunctionFeatures;
4258
53
}
4259
PredicateBitset
4260
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const;
4261
PredicateBitset
4262
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget,
4263
                                 const MachineFunction *MF) const;
4264
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
4265
#ifdef GET_GLOBALISEL_PREDICATES_INIT
4266
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
4267
AvailableFunctionFeatures()
4268
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT