Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc
Line
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the AMDGPU target                          *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 32;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(AMDGPUInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(AMDGPUInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static AMDGPUInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static AMDGPUInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(3),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_isSICIBit = 3,
37
  Feature_isVIBit = 2,
38
  Feature_isGFX9Bit = 6,
39
  Feature_isCIVIBit = 7,
40
  Feature_HasFlatAddressSpaceBit = 8,
41
  Feature_HasFlatGlobalInstsBit = 9,
42
  Feature_HasUnpackedD16VMemBit = 20,
43
  Feature_HasPackedD16VMemBit = 21,
44
  Feature_D16PreservesUnusedBitsBit = 19,
45
  Feature_LDSRequiresM0InitBit = 30,
46
  Feature_NotLDSRequiresM0InitBit = 31,
47
  Feature_HasAddNoCarryInstsBit = 14,
48
  Feature_Has16BitInstsBit = 4,
49
  Feature_HasVOP3PInstsBit = 23,
50
  Feature_HasMadMixInstsBit = 15,
51
  Feature_has16BankLDSBit = 12,
52
  Feature_has32BankLDSBit = 11,
53
  Feature_HasFmaMixInstsBit = 16,
54
  Feature_HasDLInstsBit = 17,
55
  Feature_EnableLateCFGStructurizeBit = 13,
56
  Feature_TruePredicateBit = 0,
57
  Feature_FP16DenormalsBit = 25,
58
  Feature_FP32DenormalsBit = 27,
59
  Feature_FP64DenormalsBit = 29,
60
  Feature_NoFP16DenormalsBit = 24,
61
  Feature_NoFP32DenormalsBit = 26,
62
  Feature_NoFP64DenormalsBit = 28,
63
  Feature_UnsafeFPMathBit = 22,
64
  Feature_isCIOnlyBit = 18,
65
  Feature_isVIOnlyBit = 5,
66
  Feature_isGCNBit = 1,
67
  Feature_isSIBit = 10,
68
};
69
70
PredicateBitset AMDGPUInstructionSelector::
71
2.54k
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const {
72
2.54k
  PredicateBitset Features;
73
2.54k
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||
Subtarget->getGeneration() == 1.52k
AMDGPUSubtarget1.52k
::SEA_ISLANDS)
74
1.26k
    Features[Feature_isSICIBit] = 1;
75
2.54k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
76
1.28k
    Features[Feature_isVIBit] = 1;
77
2.54k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9)
78
359
    Features[Feature_isGFX9Bit] = 1;
79
2.54k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
80
1.52k
    Features[Feature_isCIVIBit] = 1;
81
2.54k
  if (Subtarget->hasFlatAddressSpace())
82
1.69k
    Features[Feature_HasFlatAddressSpaceBit] = 1;
83
2.54k
  if (Subtarget->hasFlatGlobalInsts())
84
359
    Features[Feature_HasFlatGlobalInstsBit] = 1;
85
2.54k
  if (Subtarget->hasUnpackedD16VMem())
86
899
    Features[Feature_HasUnpackedD16VMemBit] = 1;
87
2.54k
  if (!Subtarget->hasUnpackedD16VMem())
88
1.64k
    Features[Feature_HasPackedD16VMemBit] = 1;
89
2.54k
  if (Subtarget->hasD16LoadStore() && 
!Subtarget->isSRAMECCEnabled()359
)
90
326
    Features[Feature_D16PreservesUnusedBitsBit] = 1;
91
2.54k
  if (Subtarget->ldsRequiresM0Init())
92
2.18k
    Features[Feature_LDSRequiresM0InitBit] = 1;
93
2.54k
  if (!Subtarget->ldsRequiresM0Init())
94
359
    Features[Feature_NotLDSRequiresM0InitBit] = 1;
95
2.54k
  if (Subtarget->hasAddNoCarry())
96
359
    Features[Feature_HasAddNoCarryInstsBit] = 1;
97
2.54k
  if (Subtarget->has16BitInsts())
98
1.28k
    Features[Feature_Has16BitInstsBit] = 1;
99
2.54k
  if (Subtarget->hasVOP3PInsts())
100
359
    Features[Feature_HasVOP3PInstsBit] = 1;
101
2.54k
  if (Subtarget->hasMadMixInsts())
102
322
    Features[Feature_HasMadMixInstsBit] = 1;
103
2.54k
  if (Subtarget->getLDSBankCount() == 16)
104
33
    Features[Feature_has16BankLDSBit] = 1;
105
2.54k
  if (Subtarget->getLDSBankCount() == 32)
106
2.50k
    Features[Feature_has32BankLDSBit] = 1;
107
2.54k
  if (Subtarget->hasFmaMixInsts())
108
37
    Features[Feature_HasFmaMixInstsBit] = 1;
109
2.54k
  if (Subtarget->hasDLInsts())
110
32
    Features[Feature_HasDLInstsBit] = 1;
111
2.54k
  if (EnableLateStructurizeCFG)
112
0
    Features[Feature_EnableLateCFGStructurizeBit] = 1;
113
2.54k
  if (true)
114
2.54k
    Features[Feature_TruePredicateBit] = 1;
115
2.54k
  if (Subtarget->hasFP16Denormals())
116
2.50k
    Features[Feature_FP16DenormalsBit] = 1;
117
2.54k
  if (Subtarget->hasFP32Denormals())
118
61
    Features[Feature_FP32DenormalsBit] = 1;
119
2.54k
  if (Subtarget->hasFP64Denormals())
120
2.50k
    Features[Feature_FP64DenormalsBit] = 1;
121
2.54k
  if (!Subtarget->hasFP16Denormals())
122
40
    Features[Feature_NoFP16DenormalsBit] = 1;
123
2.54k
  if (!Subtarget->hasFP32Denormals())
124
2.48k
    Features[Feature_NoFP32DenormalsBit] = 1;
125
2.54k
  if (!Subtarget->hasFP64Denormals())
126
40
    Features[Feature_NoFP64DenormalsBit] = 1;
127
2.54k
  if (TM.Options.UnsafeFPMath)
128
36
    Features[Feature_UnsafeFPMathBit] = 1;
129
2.54k
  if (Subtarget->getGeneration() ==AMDGPUSubtarget::SEA_ISLANDS)
130
245
    Features[Feature_isCIOnlyBit] = 1;
131
2.54k
  if (Subtarget->getGeneration() ==AMDGPUSubtarget::VOLCANIC_ISLANDS)
132
923
    Features[Feature_isVIOnlyBit] = 1;
133
2.54k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
134
2.54k
    Features[Feature_isGCNBit] = 1;
135
2.54k
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
136
1.01k
    Features[Feature_isSIBit] = 1;
137
2.54k
  return Features;
138
2.54k
}
139
140
PredicateBitset AMDGPUInstructionSelector::
141
56
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget, const MachineFunction *MF) const {
142
56
  PredicateBitset Features;
143
56
  return Features;
144
56
}
145
146
// LLT Objects.
147
enum {
148
  GILLT_s1,
149
  GILLT_s16,
150
  GILLT_s32,
151
  GILLT_s64,
152
  GILLT_v2s16,
153
  GILLT_v2s32,
154
  GILLT_v2s64,
155
  GILLT_v4s16,
156
  GILLT_v4s32,
157
  GILLT_v8s32,
158
  GILLT_v16s32,
159
};
160
const static size_t NumTypeObjects = 11;
161
const static LLT TypeObjects[] = {
162
  LLT::scalar(1),
163
  LLT::scalar(16),
164
  LLT::scalar(32),
165
  LLT::scalar(64),
166
  LLT::vector(2, 16),
167
  LLT::vector(2, 32),
168
  LLT::vector(2, 64),
169
  LLT::vector(4, 16),
170
  LLT::vector(4, 32),
171
  LLT::vector(8, 32),
172
  LLT::vector(16, 32),
173
};
174
175
// Feature bitsets.
176
enum {
177
  GIFBS_Invalid,
178
  GIFBS_Has16BitInsts,
179
  GIFBS_isGCN,
180
  GIFBS_isSICI,
181
  GIFBS_TruePredicate_isCIVI,
182
  GIFBS_TruePredicate_isGCN,
183
  GIFBS_TruePredicate_isSI,
184
  GIFBS_TruePredicate_isSICI,
185
  GIFBS_TruePredicate_isVI,
186
};
187
const static PredicateBitset FeatureBitsets[] {
188
  {}, // GIFBS_Invalid
189
  {Feature_Has16BitInstsBit, },
190
  {Feature_isGCNBit, },
191
  {Feature_isSICIBit, },
192
  {Feature_TruePredicateBit, Feature_isCIVIBit, },
193
  {Feature_TruePredicateBit, Feature_isGCNBit, },
194
  {Feature_TruePredicateBit, Feature_isSIBit, },
195
  {Feature_TruePredicateBit, Feature_isSICIBit, },
196
  {Feature_TruePredicateBit, Feature_isVIBit, },
197
};
198
199
// ComplexPattern predicates.
200
enum {
201
  GICP_Invalid,
202
  GICP_gi_vcsrc,
203
  GICP_gi_vop3mods,
204
  GICP_gi_vop3mods0,
205
  GICP_gi_vop3omods,
206
  GICP_gi_vsrc0,
207
};
208
// See constructor for table contents
209
210
// PatFrag predicates.
211
enum {
212
  GIPFP_I64_Predicate_NegSubInlineConst16 = GIPFP_I64_Invalid + 1,
213
  GIPFP_I64_Predicate_NegSubInlineConst32,
214
};
215
0
bool AMDGPUInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
216
0
  switch (PredicateID) {
217
0
  case GIPFP_I64_Predicate_NegSubInlineConst16: {
218
0
    
219
0
  return Imm < -16 && Imm >= -64;
220
0
221
0
    llvm_unreachable("ImmediateCode should have returned");
222
0
    return false;
223
0
  }
224
0
  case GIPFP_I64_Predicate_NegSubInlineConst32: {
225
0
    
226
0
  return Imm < -16 && Imm >= -64;
227
0
228
0
    llvm_unreachable("ImmediateCode should have returned");
229
0
    return false;
230
0
  }
231
0
  }
232
0
  llvm_unreachable("Unknown predicate");
233
0
  return false;
234
0
}
235
0
bool AMDGPUInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
236
0
  llvm_unreachable("Unknown predicate");
237
0
  return false;
238
0
}
239
0
bool AMDGPUInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
240
0
  llvm_unreachable("Unknown predicate");
241
0
  return false;
242
0
}
243
0
bool AMDGPUInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
244
0
  const MachineFunction &MF = *MI.getParent()->getParent();
245
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
246
0
  (void)MRI;
247
0
  llvm_unreachable("Unknown predicate");
248
0
  return false;
249
0
}
250
251
AMDGPUInstructionSelector::ComplexMatcherMemFn
252
AMDGPUInstructionSelector::ComplexPredicateFns[] = {
253
  nullptr, // GICP_Invalid
254
  &AMDGPUInstructionSelector::selectVCSRC, // gi_vcsrc
255
  &AMDGPUInstructionSelector::selectVOP3Mods, // gi_vop3mods
256
  &AMDGPUInstructionSelector::selectVOP3Mods0, // gi_vop3mods0
257
  &AMDGPUInstructionSelector::selectVOP3OMods, // gi_vop3omods
258
  &AMDGPUInstructionSelector::selectVSRC0, // gi_vsrc0
259
};
260
261
// Custom renderers.
262
enum {
263
  GICR_Invalid,
264
};
265
AMDGPUInstructionSelector::CustomRendererFn
266
AMDGPUInstructionSelector::CustomRenderers[] = {
267
  nullptr, // GICP_Invalid
268
};
269
270
56
bool AMDGPUInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
271
56
  MachineFunction &MF = *I.getParent()->getParent();
272
56
  MachineRegisterInfo &MRI = MF.getRegInfo();
273
56
  // FIXME: This should be computed on a per-function basis rather than per-insn.
274
56
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
275
56
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
276
56
  NewMIVector OutMIs;
277
56
  State.MIs.clear();
278
56
  State.MIs.push_back(&I);
279
56
280
56
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
281
56
    return true;
282
56
  }
283
0
284
0
  return false;
285
0
}
286
287
56
const int64_t *AMDGPUInstructionSelector::getMatchTable() const {
288
56
  constexpr static int64_t MatchTable0[] = {
289
56
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 134, /*)*//*default:*//*Label 28*/ 9652,
290
56
    /*TargetOpcode::G_ADD*//*Label 0*/ 105,
291
56
    /*TargetOpcode::G_SUB*//*Label 1*/ 302,
292
56
    /*TargetOpcode::G_MUL*//*Label 2*/ 333, 0, 0, 0, 0,
293
56
    /*TargetOpcode::G_AND*//*Label 3*/ 361,
294
56
    /*TargetOpcode::G_OR*//*Label 4*/ 392,
295
56
    /*TargetOpcode::G_XOR*//*Label 5*/ 2141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
296
56
    /*TargetOpcode::G_BITCAST*//*Label 6*/ 2245, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
297
56
    /*TargetOpcode::G_INTRINSIC*//*Label 7*/ 4387,
298
56
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 8*/ 6759, 0, 0,
299
56
    /*TargetOpcode::G_CONSTANT*//*Label 9*/ 7058, 0, 0, 0, 0, 0,
300
56
    /*TargetOpcode::G_SHL*//*Label 10*/ 7115,
301
56
    /*TargetOpcode::G_LSHR*//*Label 11*/ 7146,
302
56
    /*TargetOpcode::G_ASHR*//*Label 12*/ 7177, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
303
56
    /*TargetOpcode::G_FADD*//*Label 13*/ 7344,
304
56
    /*TargetOpcode::G_FSUB*//*Label 14*/ 7694,
305
56
    /*TargetOpcode::G_FMUL*//*Label 15*/ 7827,
306
56
    /*TargetOpcode::G_FMA*//*Label 16*/ 8177, 0, 0,
307
56
    /*TargetOpcode::G_FPOW*//*Label 17*/ 8421, 0,
308
56
    /*TargetOpcode::G_FEXP2*//*Label 18*/ 8494, 0,
309
56
    /*TargetOpcode::G_FLOG2*//*Label 19*/ 8591, 0,
310
56
    /*TargetOpcode::G_FPEXT*//*Label 20*/ 8688,
311
56
    /*TargetOpcode::G_FPTRUNC*//*Label 21*/ 8785,
312
56
    /*TargetOpcode::G_FPTOSI*//*Label 22*/ 8882,
313
56
    /*TargetOpcode::G_FPTOUI*//*Label 23*/ 9116,
314
56
    /*TargetOpcode::G_SITOFP*//*Label 24*/ 9350,
315
56
    /*TargetOpcode::G_UITOFP*//*Label 25*/ 9480, 0, 0, 0,
316
56
    /*TargetOpcode::G_BR*//*Label 26*/ 9610, 0, 0, 0, 0, 0, 0, 0,
317
56
    /*TargetOpcode::G_CTPOP*//*Label 27*/ 9625,
318
56
    // Label 0: @105
319
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 31*/ 301,
320
56
    /*GILLT_s16*//*Label 29*/ 114, 0,
321
56
    /*GILLT_s64*//*Label 30*/ 274,
322
56
    // Label 29: @114
323
56
    GIM_Try, /*On fail goto*//*Label 32*/ 273,
324
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
325
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
326
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
327
56
      GIM_Try, /*On fail goto*//*Label 33*/ 176, // Rule ID 966 //
328
56
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
329
56
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
330
56
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
331
56
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
332
56
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
333
56
        GIM_CheckIsSafeToFold, /*InsnID*/1,
334
56
        // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
335
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
336
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
337
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
338
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
339
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
340
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
341
56
        GIR_EraseFromParent, /*InsnID*/0,
342
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
343
56
        // GIR_Coverage, 966,
344
56
        GIR_Done,
345
56
      // Label 33: @176
346
56
      GIM_Try, /*On fail goto*//*Label 34*/ 224, // Rule ID 967 //
347
56
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
348
56
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
349
56
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
350
56
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
351
56
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
352
56
        GIM_CheckIsSafeToFold, /*InsnID*/1,
353
56
        // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_I16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
354
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_I16,
355
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
356
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
357
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
358
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
359
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
360
56
        GIR_EraseFromParent, /*InsnID*/0,
361
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
362
56
        // GIR_Coverage, 967,
363
56
        GIR_Done,
364
56
      // Label 34: @224
365
56
      GIM_Try, /*On fail goto*//*Label 35*/ 272, // Rule ID 2092 //
366
56
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
367
56
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
368
56
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
369
56
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
370
56
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
371
56
        GIM_CheckIsSafeToFold, /*InsnID*/1,
372
56
        // (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
373
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
374
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
375
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
376
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
377
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
378
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
379
56
        GIR_EraseFromParent, /*InsnID*/0,
380
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
381
56
        // GIR_Coverage, 2092,
382
56
        GIR_Done,
383
56
      // Label 35: @272
384
56
      GIM_Reject,
385
56
    // Label 32: @273
386
56
    GIM_Reject,
387
56
    // Label 30: @274
388
56
    GIM_Try, /*On fail goto*//*Label 36*/ 300, // Rule ID 661 //
389
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
390
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
391
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
392
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
393
56
      // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_ADD_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
394
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ADD_U64_PSEUDO,
395
56
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
396
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
397
56
      // GIR_Coverage, 661,
398
56
      GIR_Done,
399
56
    // Label 36: @300
400
56
    GIM_Reject,
401
56
    // Label 31: @301
402
56
    GIM_Reject,
403
56
    // Label 1: @302
404
56
    GIM_Try, /*On fail goto*//*Label 37*/ 332, // Rule ID 662 //
405
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
406
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
407
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
408
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
409
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
410
56
      // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_SUB_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
411
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_SUB_U64_PSEUDO,
412
56
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
413
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
414
56
      // GIR_Coverage, 662,
415
56
      GIR_Done,
416
56
    // Label 37: @332
417
56
    GIM_Reject,
418
56
    // Label 2: @333
419
56
    GIM_Try, /*On fail goto*//*Label 38*/ 360, // Rule ID 35 //
420
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
421
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
422
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
423
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
424
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
425
56
      // (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_MUL_I32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
426
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_MUL_I32,
427
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
428
56
      // GIR_Coverage, 35,
429
56
      GIR_Done,
430
56
    // Label 38: @360
431
56
    GIM_Reject,
432
56
    // Label 3: @361
433
56
    GIM_Try, /*On fail goto*//*Label 39*/ 391, // Rule ID 413 //
434
56
      GIM_CheckFeatures, GIFBS_isGCN,
435
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
436
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
437
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
438
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
439
56
      // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_AND_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
440
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_AND_B32_e64,
441
56
      GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
442
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
443
56
      // GIR_Coverage, 413,
444
56
      GIR_Done,
445
56
    // Label 39: @391
446
56
    GIM_Reject,
447
56
    // Label 4: @392
448
56
    GIM_Try, /*On fail goto*//*Label 40*/ 2140,
449
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
450
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
451
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
452
56
      GIM_Try, /*On fail goto*//*Label 41*/ 2095,
453
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
454
56
        GIM_Try, /*On fail goto*//*Label 42*/ 513, // Rule ID 2039 //
455
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
456
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
457
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
458
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
459
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
460
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
461
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
462
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
463
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
464
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
465
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
466
56
          // MIs[3] x
467
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
468
56
          // MIs[3] z
469
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
470
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
471
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
472
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
473
56
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
474
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
475
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
476
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
477
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
478
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
479
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
480
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
481
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
482
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
483
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
484
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
485
56
          GIR_EraseFromParent, /*InsnID*/0,
486
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
487
56
          // GIR_Coverage, 2039,
488
56
          GIR_Done,
489
56
        // Label 42: @513
490
56
        GIM_Try, /*On fail goto*//*Label 43*/ 614, // Rule ID 2040 //
491
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
492
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
493
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
494
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
495
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
496
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
497
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
498
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
499
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
500
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
501
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
502
56
          // MIs[3] z
503
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
504
56
          // MIs[3] x
505
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
506
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
507
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
508
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
509
56
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
510
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
511
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
512
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
513
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
514
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
515
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
516
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
517
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
518
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
519
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
520
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
521
56
          GIR_EraseFromParent, /*InsnID*/0,
522
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
523
56
          // GIR_Coverage, 2040,
524
56
          GIR_Done,
525
56
        // Label 43: @614
526
56
        GIM_Try, /*On fail goto*//*Label 44*/ 715, // Rule ID 2041 //
527
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
528
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
529
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
530
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
531
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
532
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
533
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
534
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
535
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
536
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
537
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
538
56
          // MIs[3] x
539
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
540
56
          // MIs[3] z
541
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
542
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
543
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
544
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
545
56
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
546
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
547
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
548
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
549
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
550
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
551
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
552
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
553
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
554
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
555
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
556
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
557
56
          GIR_EraseFromParent, /*InsnID*/0,
558
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
559
56
          // GIR_Coverage, 2041,
560
56
          GIR_Done,
561
56
        // Label 44: @715
562
56
        GIM_Try, /*On fail goto*//*Label 45*/ 816, // Rule ID 2042 //
563
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
564
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
565
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
566
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
567
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
568
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
569
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
570
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
571
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
572
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
573
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
574
56
          // MIs[3] z
575
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
576
56
          // MIs[3] x
577
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
578
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
579
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
580
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
581
56
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
582
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
583
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
584
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
585
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
586
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
587
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
588
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
589
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
590
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
591
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
592
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
593
56
          GIR_EraseFromParent, /*InsnID*/0,
594
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
595
56
          // GIR_Coverage, 2042,
596
56
          GIR_Done,
597
56
        // Label 45: @816
598
56
        GIM_Try, /*On fail goto*//*Label 46*/ 917, // Rule ID 2035 //
599
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
600
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
601
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
602
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
603
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
604
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
605
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
606
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
607
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
608
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
609
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
610
56
          // MIs[3] x
611
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
612
56
          // MIs[3] z
613
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
614
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
615
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
616
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
617
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
618
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
619
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
620
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
621
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
622
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
623
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
624
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
625
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
626
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
627
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
628
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
629
56
          GIR_EraseFromParent, /*InsnID*/0,
630
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
631
56
          // GIR_Coverage, 2035,
632
56
          GIR_Done,
633
56
        // Label 46: @917
634
56
        GIM_Try, /*On fail goto*//*Label 47*/ 1018, // Rule ID 2036 //
635
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
636
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
637
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
638
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
639
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
640
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
641
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
642
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
643
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
644
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
645
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
646
56
          // MIs[3] z
647
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
648
56
          // MIs[3] x
649
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
650
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
651
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
652
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
653
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
654
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
655
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
656
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
657
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
658
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
659
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
660
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
661
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
662
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
663
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
664
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
665
56
          GIR_EraseFromParent, /*InsnID*/0,
666
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
667
56
          // GIR_Coverage, 2036,
668
56
          GIR_Done,
669
56
        // Label 47: @1018
670
56
        GIM_Try, /*On fail goto*//*Label 48*/ 1119, // Rule ID 2037 //
671
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
672
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
673
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
674
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
675
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
676
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
677
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
678
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
679
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
680
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
681
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
682
56
          // MIs[3] x
683
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
684
56
          // MIs[3] z
685
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
686
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
687
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
688
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
689
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
690
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
691
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
692
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
693
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
694
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
695
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
696
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
697
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
698
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
699
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
700
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
701
56
          GIR_EraseFromParent, /*InsnID*/0,
702
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
703
56
          // GIR_Coverage, 2037,
704
56
          GIR_Done,
705
56
        // Label 48: @1119
706
56
        GIM_Try, /*On fail goto*//*Label 49*/ 1220, // Rule ID 2038 //
707
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
708
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
709
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
710
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
711
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
712
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
713
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
714
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
715
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
716
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
717
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
718
56
          // MIs[3] z
719
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
720
56
          // MIs[3] x
721
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
722
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
723
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
724
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
725
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
726
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
727
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
728
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
729
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
730
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
731
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
732
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
733
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
734
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
735
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
736
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
737
56
          GIR_EraseFromParent, /*InsnID*/0,
738
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
739
56
          // GIR_Coverage, 2038,
740
56
          GIR_Done,
741
56
        // Label 49: @1220
742
56
        GIM_Try, /*On fail goto*//*Label 50*/ 1321, // Rule ID 2029 //
743
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
744
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
745
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
746
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
747
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
748
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
749
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
750
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
751
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
752
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
753
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
754
56
          // MIs[3] x
755
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
756
56
          // MIs[3] z
757
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
758
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
759
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
760
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
761
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
762
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
763
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
764
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
765
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
766
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
767
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
768
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
769
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
770
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
771
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
772
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
773
56
          GIR_EraseFromParent, /*InsnID*/0,
774
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
775
56
          // GIR_Coverage, 2029,
776
56
          GIR_Done,
777
56
        // Label 50: @1321
778
56
        GIM_Try, /*On fail goto*//*Label 51*/ 1422, // Rule ID 2030 //
779
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
780
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
781
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
782
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
783
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
784
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
785
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
786
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
787
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
788
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
789
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
790
56
          // MIs[3] z
791
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
792
56
          // MIs[3] x
793
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
794
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
795
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
796
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
797
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
798
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
799
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
800
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
801
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
802
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
803
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
804
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
805
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
806
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
807
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
808
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
809
56
          GIR_EraseFromParent, /*InsnID*/0,
810
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
811
56
          // GIR_Coverage, 2030,
812
56
          GIR_Done,
813
56
        // Label 51: @1422
814
56
        GIM_Try, /*On fail goto*//*Label 52*/ 1523, // Rule ID 2033 //
815
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
816
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
817
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
818
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
819
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
820
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
821
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
822
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
823
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
824
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
825
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
826
56
          // MIs[3] x
827
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
828
56
          // MIs[3] z
829
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
830
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
831
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
832
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
833
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
834
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
835
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
836
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
837
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
838
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
839
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
840
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
841
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
842
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
843
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
844
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
845
56
          GIR_EraseFromParent, /*InsnID*/0,
846
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
847
56
          // GIR_Coverage, 2033,
848
56
          GIR_Done,
849
56
        // Label 52: @1523
850
56
        GIM_Try, /*On fail goto*//*Label 53*/ 1624, // Rule ID 2034 //
851
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
852
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
853
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
854
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
855
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
856
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
857
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
858
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
859
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
860
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
861
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
862
56
          // MIs[3] z
863
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
864
56
          // MIs[3] x
865
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
866
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
867
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
868
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
869
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
870
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
871
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
872
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
873
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
874
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
875
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
876
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
877
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
878
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
879
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
880
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
881
56
          GIR_EraseFromParent, /*InsnID*/0,
882
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
883
56
          // GIR_Coverage, 2034,
884
56
          GIR_Done,
885
56
        // Label 53: @1624
886
56
        GIM_Try, /*On fail goto*//*Label 54*/ 1725, // Rule ID 812 //
887
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
888
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
889
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
890
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
891
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
892
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
893
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
894
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
895
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
896
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
897
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
898
56
          // MIs[3] x
899
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
900
56
          // MIs[3] z
901
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
902
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
903
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
904
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
905
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
906
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
907
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
908
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
909
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
910
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
911
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
912
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
913
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
914
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
915
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
916
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
917
56
          GIR_EraseFromParent, /*InsnID*/0,
918
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
919
56
          // GIR_Coverage, 812,
920
56
          GIR_Done,
921
56
        // Label 54: @1725
922
56
        GIM_Try, /*On fail goto*//*Label 55*/ 1826, // Rule ID 2028 //
923
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
924
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
925
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
926
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
927
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
928
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
929
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
930
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
931
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
932
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
933
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
934
56
          // MIs[3] z
935
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
936
56
          // MIs[3] x
937
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
938
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
939
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
940
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
941
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
942
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
943
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
944
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
945
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
946
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
947
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
948
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
949
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
950
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
951
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
952
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
953
56
          GIR_EraseFromParent, /*InsnID*/0,
954
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
955
56
          // GIR_Coverage, 2028,
956
56
          GIR_Done,
957
56
        // Label 55: @1826
958
56
        GIM_Try, /*On fail goto*//*Label 56*/ 1927, // Rule ID 2031 //
959
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
960
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
961
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
962
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
963
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
964
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
965
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
966
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
967
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
968
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
969
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
970
56
          // MIs[3] x
971
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
972
56
          // MIs[3] z
973
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
974
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
975
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
976
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
977
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
978
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
979
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
980
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
981
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
982
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
983
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
984
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
985
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
986
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
987
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
988
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
989
56
          GIR_EraseFromParent, /*InsnID*/0,
990
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
991
56
          // GIR_Coverage, 2031,
992
56
          GIR_Done,
993
56
        // Label 56: @1927
994
56
        GIM_Try, /*On fail goto*//*Label 57*/ 2028, // Rule ID 2032 //
995
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
996
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
997
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
998
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
999
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1000
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1001
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
1002
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1003
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1004
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1005
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
1006
56
          // MIs[3] z
1007
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
1008
56
          // MIs[3] x
1009
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
1010
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
1011
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
1012
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
1013
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
1014
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
1015
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1016
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1017
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
1018
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
1019
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1020
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1021
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1022
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1023
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
1024
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
1025
56
          GIR_EraseFromParent, /*InsnID*/0,
1026
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1027
56
          // GIR_Coverage, 2032,
1028
56
          GIR_Done,
1029
56
        // Label 57: @2028
1030
56
        GIM_Try, /*On fail goto*//*Label 58*/ 2061, // Rule ID 1958 //
1031
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1032
56
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
1033
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vsrc0,
1034
56
          // (or:{ *:[i32] } (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0), VGPR_32:{ *:[i32] }:$src1)  =>  (V_OR_B32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1035
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
1036
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1037
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
1038
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1039
56
          GIR_EraseFromParent, /*InsnID*/0,
1040
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1041
56
          // GIR_Coverage, 1958,
1042
56
          GIR_Done,
1043
56
        // Label 58: @2061
1044
56
        GIM_Try, /*On fail goto*//*Label 59*/ 2094, // Rule ID 3220 //
1045
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1046
56
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1047
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
1048
56
          // (or:{ *:[i32] } VGPR_32:{ *:[i32] }:$src1, (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_OR_B32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1049
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
1050
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1051
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
1052
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1053
56
          GIR_EraseFromParent, /*InsnID*/0,
1054
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1055
56
          // GIR_Coverage, 3220,
1056
56
          GIR_Done,
1057
56
        // Label 59: @2094
1058
56
        GIM_Reject,
1059
56
      // Label 41: @2095
1060
56
      GIM_Try, /*On fail goto*//*Label 60*/ 2121, // Rule ID 1957 //
1061
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1062
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1063
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1064
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
1065
56
        // (or:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)  =>  (S_OR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1066
56
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
1067
56
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
1068
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1069
56
        // GIR_Coverage, 1957,
1070
56
        GIR_Done,
1071
56
      // Label 60: @2121
1072
56
      GIM_Try, /*On fail goto*//*Label 61*/ 2139, // Rule ID 415 //
1073
56
        GIM_CheckFeatures, GIFBS_isGCN,
1074
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1075
56
        // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_OR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1076
56
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e64,
1077
56
        GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
1078
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1079
56
        // GIR_Coverage, 415,
1080
56
        GIR_Done,
1081
56
      // Label 61: @2139
1082
56
      GIM_Reject,
1083
56
    // Label 40: @2140
1084
56
    GIM_Reject,
1085
56
    // Label 5: @2141
1086
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 64*/ 2244,
1087
56
    /*GILLT_s32*//*Label 62*/ 2149,
1088
56
    /*GILLT_s64*//*Label 63*/ 2207,
1089
56
    // Label 62: @2149
1090
56
    GIM_Try, /*On fail goto*//*Label 65*/ 2206,
1091
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1092
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1093
56
      GIM_Try, /*On fail goto*//*Label 66*/ 2187, // Rule ID 0 //
1094
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1095
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1096
56
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1097
56
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })  =>  (S_NOT_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
1098
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B32,
1099
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
1100
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1101
56
        GIR_EraseFromParent, /*InsnID*/0,
1102
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1103
56
        // GIR_Coverage, 0,
1104
56
        GIR_Done,
1105
56
      // Label 66: @2187
1106
56
      GIM_Try, /*On fail goto*//*Label 67*/ 2205, // Rule ID 417 //
1107
56
        GIM_CheckFeatures, GIFBS_isGCN,
1108
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1109
56
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_XOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1110
56
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1111
56
        GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
1112
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1113
56
        // GIR_Coverage, 417,
1114
56
        GIR_Done,
1115
56
      // Label 67: @2205
1116
56
      GIM_Reject,
1117
56
    // Label 65: @2206
1118
56
    GIM_Reject,
1119
56
    // Label 63: @2207
1120
56
    GIM_Try, /*On fail goto*//*Label 68*/ 2243, // Rule ID 1 //
1121
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1122
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1123
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1124
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
1125
56
      GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1126
56
      // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, -1:{ *:[i64] })  =>  (S_NOT_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0)
1127
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B64,
1128
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
1129
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1130
56
      GIR_EraseFromParent, /*InsnID*/0,
1131
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1132
56
      // GIR_Coverage, 1,
1133
56
      GIR_Done,
1134
56
    // Label 68: @2243
1135
56
    GIM_Reject,
1136
56
    // Label 64: @2244
1137
56
    GIM_Reject,
1138
56
    // Label 6: @2245
1139
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 79*/ 4386,
1140
56
    /*GILLT_s16*//*Label 69*/ 2261,
1141
56
    /*GILLT_s32*//*Label 70*/ 2389,
1142
56
    /*GILLT_s64*//*Label 71*/ 2662,
1143
56
    /*GILLT_v2s16*//*Label 72*/ 3003,
1144
56
    /*GILLT_v2s32*//*Label 73*/ 3208,
1145
56
    /*GILLT_v2s64*//*Label 74*/ 3583,
1146
56
    /*GILLT_v4s16*//*Label 75*/ 3754,
1147
56
    /*GILLT_v4s32*//*Label 76*/ 4027,
1148
56
    /*GILLT_v8s32*//*Label 77*/ 4198,
1149
56
    /*GILLT_v16s32*//*Label 78*/ 4326,
1150
56
    // Label 69: @2261
1151
56
    GIM_Try, /*On fail goto*//*Label 80*/ 2388,
1152
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
1153
56
      GIM_Try, /*On fail goto*//*Label 81*/ 2297, // Rule ID 1609 //
1154
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1155
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1156
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1157
56
        // (bitconvert:{ *:[i16] } VGPR_32:{ *:[f16] }:$src0)  =>  VGPR_32:{ *:[i16] }:$src0
1158
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1159
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1160
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1161
56
        GIR_EraseFromParent, /*InsnID*/0,
1162
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1163
56
        // GIR_Coverage, 1609,
1164
56
        GIR_Done,
1165
56
      // Label 81: @2297
1166
56
      GIM_Try, /*On fail goto*//*Label 82*/ 2327, // Rule ID 1610 //
1167
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1168
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1169
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1170
56
        // (bitconvert:{ *:[f16] } VGPR_32:{ *:[i16] }:$src0)  =>  VGPR_32:{ *:[f16] }:$src0
1171
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1172
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1173
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1174
56
        GIR_EraseFromParent, /*InsnID*/0,
1175
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1176
56
        // GIR_Coverage, 1610,
1177
56
        GIR_Done,
1178
56
      // Label 82: @2327
1179
56
      GIM_Try, /*On fail goto*//*Label 83*/ 2357, // Rule ID 1611 //
1180
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1181
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1182
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1183
56
        // (bitconvert:{ *:[i16] } SReg_32:{ *:[f16] }:$src0)  =>  SReg_32:{ *:[i16] }:$src0
1184
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1185
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1186
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1187
56
        GIR_EraseFromParent, /*InsnID*/0,
1188
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1189
56
        // GIR_Coverage, 1611,
1190
56
        GIR_Done,
1191
56
      // Label 83: @2357
1192
56
      GIM_Try, /*On fail goto*//*Label 84*/ 2387, // Rule ID 1612 //
1193
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1194
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1195
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1196
56
        // (bitconvert:{ *:[f16] } SReg_32:{ *:[i16] }:$src0)  =>  SReg_32:{ *:[f16] }:$src0
1197
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1198
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1199
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1200
56
        GIR_EraseFromParent, /*InsnID*/0,
1201
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1202
56
        // GIR_Coverage, 1612,
1203
56
        GIR_Done,
1204
56
      // Label 84: @2387
1205
56
      GIM_Reject,
1206
56
    // Label 80: @2388
1207
56
    GIM_Reject,
1208
56
    // Label 70: @2389
1209
56
    GIM_Try, /*On fail goto*//*Label 85*/ 2423, // Rule ID 1613 //
1210
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1211
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1212
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1213
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1214
56
      // (bitconvert:{ *:[i32] } VGPR_32:{ *:[f32] }:$src0)  =>  VGPR_32:{ *:[i32] }:$src0
1215
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1216
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1217
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1218
56
      GIR_EraseFromParent, /*InsnID*/0,
1219
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1220
56
      // GIR_Coverage, 1613,
1221
56
      GIR_Done,
1222
56
    // Label 85: @2423
1223
56
    GIM_Try, /*On fail goto*//*Label 86*/ 2457, // Rule ID 1614 //
1224
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1225
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1226
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1227
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1228
56
      // (bitconvert:{ *:[f32] } VGPR_32:{ *:[i32] }:$src0)  =>  VGPR_32:{ *:[f32] }:$src0
1229
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1230
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1231
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1232
56
      GIR_EraseFromParent, /*InsnID*/0,
1233
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1234
56
      // GIR_Coverage, 1614,
1235
56
      GIR_Done,
1236
56
    // Label 86: @2457
1237
56
    GIM_Try, /*On fail goto*//*Label 87*/ 2491, // Rule ID 1615 //
1238
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1239
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1240
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1241
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1242
56
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1243
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1244
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1245
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1246
56
      GIR_EraseFromParent, /*InsnID*/0,
1247
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1248
56
      // GIR_Coverage, 1615,
1249
56
      GIR_Done,
1250
56
    // Label 87: @2491
1251
56
    GIM_Try, /*On fail goto*//*Label 88*/ 2525, // Rule ID 1616 //
1252
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1253
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1254
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1255
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1256
56
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1257
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1258
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1259
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1260
56
      GIR_EraseFromParent, /*InsnID*/0,
1261
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1262
56
      // GIR_Coverage, 1616,
1263
56
      GIR_Done,
1264
56
    // Label 88: @2525
1265
56
    GIM_Try, /*On fail goto*//*Label 89*/ 2559, // Rule ID 1618 //
1266
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1267
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1268
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1269
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1270
56
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1271
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1272
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1273
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1274
56
      GIR_EraseFromParent, /*InsnID*/0,
1275
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1276
56
      // GIR_Coverage, 1618,
1277
56
      GIR_Done,
1278
56
    // Label 89: @2559
1279
56
    GIM_Try, /*On fail goto*//*Label 90*/ 2593, // Rule ID 1620 //
1280
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1281
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1282
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1283
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1284
56
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1285
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1286
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1287
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1288
56
      GIR_EraseFromParent, /*InsnID*/0,
1289
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1290
56
      // GIR_Coverage, 1620,
1291
56
      GIR_Done,
1292
56
    // Label 90: @2593
1293
56
    GIM_Try, /*On fail goto*//*Label 91*/ 2627, // Rule ID 1624 //
1294
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1295
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1296
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1297
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1298
56
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1299
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1300
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1301
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1302
56
      GIR_EraseFromParent, /*InsnID*/0,
1303
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1304
56
      // GIR_Coverage, 1624,
1305
56
      GIR_Done,
1306
56
    // Label 91: @2627
1307
56
    GIM_Try, /*On fail goto*//*Label 92*/ 2661, // Rule ID 1626 //
1308
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1309
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1310
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1311
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1312
56
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1313
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1314
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1315
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1316
56
      GIR_EraseFromParent, /*InsnID*/0,
1317
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1318
56
      // GIR_Coverage, 1626,
1319
56
      GIR_Done,
1320
56
    // Label 92: @2661
1321
56
    GIM_Reject,
1322
56
    // Label 71: @2662
1323
56
    GIM_Try, /*On fail goto*//*Label 93*/ 2696, // Rule ID 1627 //
1324
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1325
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1326
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1327
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1328
56
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1329
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1330
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1331
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1332
56
      GIR_EraseFromParent, /*InsnID*/0,
1333
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1334
56
      // GIR_Coverage, 1627,
1335
56
      GIR_Done,
1336
56
    // Label 93: @2696
1337
56
    GIM_Try, /*On fail goto*//*Label 94*/ 2730, // Rule ID 1628 //
1338
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1339
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1340
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1341
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1342
56
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1343
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1344
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1345
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1346
56
      GIR_EraseFromParent, /*InsnID*/0,
1347
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1348
56
      // GIR_Coverage, 1628,
1349
56
      GIR_Done,
1350
56
    // Label 94: @2730
1351
56
    GIM_Try, /*On fail goto*//*Label 95*/ 2764, // Rule ID 1631 //
1352
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1353
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1354
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1355
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1356
56
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1357
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1358
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1359
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1360
56
      GIR_EraseFromParent, /*InsnID*/0,
1361
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1362
56
      // GIR_Coverage, 1631,
1363
56
      GIR_Done,
1364
56
    // Label 95: @2764
1365
56
    GIM_Try, /*On fail goto*//*Label 96*/ 2798, // Rule ID 1633 //
1366
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1367
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1368
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1369
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1370
56
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1371
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1372
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1373
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1374
56
      GIR_EraseFromParent, /*InsnID*/0,
1375
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1376
56
      // GIR_Coverage, 1633,
1377
56
      GIR_Done,
1378
56
    // Label 96: @2798
1379
56
    GIM_Try, /*On fail goto*//*Label 97*/ 2832, // Rule ID 1635 //
1380
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1381
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1382
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1383
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1384
56
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1385
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1386
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1387
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1388
56
      GIR_EraseFromParent, /*InsnID*/0,
1389
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1390
56
      // GIR_Coverage, 1635,
1391
56
      GIR_Done,
1392
56
    // Label 97: @2832
1393
56
    GIM_Try, /*On fail goto*//*Label 98*/ 2866, // Rule ID 1637 //
1394
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1395
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1396
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1397
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1398
56
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1399
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1400
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1401
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1402
56
      GIR_EraseFromParent, /*InsnID*/0,
1403
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1404
56
      // GIR_Coverage, 1637,
1405
56
      GIR_Done,
1406
56
    // Label 98: @2866
1407
56
    GIM_Try, /*On fail goto*//*Label 99*/ 2900, // Rule ID 1650 //
1408
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1409
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1410
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1411
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1412
56
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1413
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1414
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1415
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1416
56
      GIR_EraseFromParent, /*InsnID*/0,
1417
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1418
56
      // GIR_Coverage, 1650,
1419
56
      GIR_Done,
1420
56
    // Label 99: @2900
1421
56
    GIM_Try, /*On fail goto*//*Label 100*/ 2934, // Rule ID 1651 //
1422
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1423
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1424
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1425
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1426
56
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1427
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1428
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1429
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1430
56
      GIR_EraseFromParent, /*InsnID*/0,
1431
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1432
56
      // GIR_Coverage, 1651,
1433
56
      GIR_Done,
1434
56
    // Label 100: @2934
1435
56
    GIM_Try, /*On fail goto*//*Label 101*/ 2968, // Rule ID 1654 //
1436
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1437
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1438
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1439
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1440
56
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1441
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1442
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1443
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1444
56
      GIR_EraseFromParent, /*InsnID*/0,
1445
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1446
56
      // GIR_Coverage, 1654,
1447
56
      GIR_Done,
1448
56
    // Label 101: @2968
1449
56
    GIM_Try, /*On fail goto*//*Label 102*/ 3002, // Rule ID 1655 //
1450
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1451
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1452
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1453
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1454
56
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1455
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1456
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1457
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1458
56
      GIR_EraseFromParent, /*InsnID*/0,
1459
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1460
56
      // GIR_Coverage, 1655,
1461
56
      GIR_Done,
1462
56
    // Label 102: @3002
1463
56
    GIM_Reject,
1464
56
    // Label 72: @3003
1465
56
    GIM_Try, /*On fail goto*//*Label 103*/ 3037, // Rule ID 1617 //
1466
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1467
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1468
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1469
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1470
56
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1471
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1472
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1473
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1474
56
      GIR_EraseFromParent, /*InsnID*/0,
1475
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1476
56
      // GIR_Coverage, 1617,
1477
56
      GIR_Done,
1478
56
    // Label 103: @3037
1479
56
    GIM_Try, /*On fail goto*//*Label 104*/ 3071, // Rule ID 1619 //
1480
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1481
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1482
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1483
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1484
56
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1485
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1486
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1487
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1488
56
      GIR_EraseFromParent, /*InsnID*/0,
1489
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1490
56
      // GIR_Coverage, 1619,
1491
56
      GIR_Done,
1492
56
    // Label 104: @3071
1493
56
    GIM_Try, /*On fail goto*//*Label 105*/ 3105, // Rule ID 1621 //
1494
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1495
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1496
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1497
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1498
56
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1499
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1500
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1501
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1502
56
      GIR_EraseFromParent, /*InsnID*/0,
1503
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1504
56
      // GIR_Coverage, 1621,
1505
56
      GIR_Done,
1506
56
    // Label 105: @3105
1507
56
    GIM_Try, /*On fail goto*//*Label 106*/ 3139, // Rule ID 1622 //
1508
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1509
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1510
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1511
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1512
56
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1513
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1514
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1515
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1516
56
      GIR_EraseFromParent, /*InsnID*/0,
1517
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1518
56
      // GIR_Coverage, 1622,
1519
56
      GIR_Done,
1520
56
    // Label 106: @3139
1521
56
    GIM_Try, /*On fail goto*//*Label 107*/ 3173, // Rule ID 1623 //
1522
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1523
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1524
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1525
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1526
56
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1527
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1528
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1529
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1530
56
      GIR_EraseFromParent, /*InsnID*/0,
1531
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1532
56
      // GIR_Coverage, 1623,
1533
56
      GIR_Done,
1534
56
    // Label 107: @3173
1535
56
    GIM_Try, /*On fail goto*//*Label 108*/ 3207, // Rule ID 1625 //
1536
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1537
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1538
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1539
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1540
56
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1541
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1542
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1543
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1544
56
      GIR_EraseFromParent, /*InsnID*/0,
1545
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1546
56
      // GIR_Coverage, 1625,
1547
56
      GIR_Done,
1548
56
    // Label 108: @3207
1549
56
    GIM_Reject,
1550
56
    // Label 73: @3208
1551
56
    GIM_Try, /*On fail goto*//*Label 109*/ 3242, // Rule ID 1629 //
1552
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1553
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1554
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1555
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1556
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1557
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1558
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1559
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1560
56
      GIR_EraseFromParent, /*InsnID*/0,
1561
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1562
56
      // GIR_Coverage, 1629,
1563
56
      GIR_Done,
1564
56
    // Label 109: @3242
1565
56
    GIM_Try, /*On fail goto*//*Label 110*/ 3276, // Rule ID 1630 //
1566
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1567
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1568
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1569
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1570
56
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1571
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1572
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1573
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1574
56
      GIR_EraseFromParent, /*InsnID*/0,
1575
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1576
56
      // GIR_Coverage, 1630,
1577
56
      GIR_Done,
1578
56
    // Label 110: @3276
1579
56
    GIM_Try, /*On fail goto*//*Label 111*/ 3310, // Rule ID 1632 //
1580
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1581
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1582
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1583
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1584
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1585
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1586
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1587
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1588
56
      GIR_EraseFromParent, /*InsnID*/0,
1589
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1590
56
      // GIR_Coverage, 1632,
1591
56
      GIR_Done,
1592
56
    // Label 111: @3310
1593
56
    GIM_Try, /*On fail goto*//*Label 112*/ 3344, // Rule ID 1634 //
1594
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1595
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1596
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1597
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1598
56
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1599
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1600
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1601
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1602
56
      GIR_EraseFromParent, /*InsnID*/0,
1603
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1604
56
      // GIR_Coverage, 1634,
1605
56
      GIR_Done,
1606
56
    // Label 112: @3344
1607
56
    GIM_Try, /*On fail goto*//*Label 113*/ 3378, // Rule ID 1636 //
1608
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1609
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1610
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1611
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1612
56
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1613
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1614
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1615
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1616
56
      GIR_EraseFromParent, /*InsnID*/0,
1617
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1618
56
      // GIR_Coverage, 1636,
1619
56
      GIR_Done,
1620
56
    // Label 113: @3378
1621
56
    GIM_Try, /*On fail goto*//*Label 114*/ 3412, // Rule ID 1638 //
1622
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1623
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1624
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1625
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1626
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1627
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1628
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1629
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1630
56
      GIR_EraseFromParent, /*InsnID*/0,
1631
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1632
56
      // GIR_Coverage, 1638,
1633
56
      GIR_Done,
1634
56
    // Label 114: @3412
1635
56
    GIM_Try, /*On fail goto*//*Label 115*/ 3446, // Rule ID 1639 //
1636
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1637
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1638
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1639
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1640
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1641
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1642
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1643
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1644
56
      GIR_EraseFromParent, /*InsnID*/0,
1645
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1646
56
      // GIR_Coverage, 1639,
1647
56
      GIR_Done,
1648
56
    // Label 115: @3446
1649
56
    GIM_Try, /*On fail goto*//*Label 116*/ 3480, // Rule ID 1641 //
1650
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1651
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1652
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1653
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1654
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1655
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1656
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1657
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1658
56
      GIR_EraseFromParent, /*InsnID*/0,
1659
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1660
56
      // GIR_Coverage, 1641,
1661
56
      GIR_Done,
1662
56
    // Label 116: @3480
1663
56
    GIM_Try, /*On fail goto*//*Label 117*/ 3514, // Rule ID 1642 //
1664
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1665
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1666
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1667
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1668
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1669
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1670
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1671
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1672
56
      GIR_EraseFromParent, /*InsnID*/0,
1673
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1674
56
      // GIR_Coverage, 1642,
1675
56
      GIR_Done,
1676
56
    // Label 117: @3514
1677
56
    GIM_Try, /*On fail goto*//*Label 118*/ 3548, // Rule ID 1644 //
1678
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1679
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1680
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1681
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1682
56
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1683
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1684
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1685
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1686
56
      GIR_EraseFromParent, /*InsnID*/0,
1687
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1688
56
      // GIR_Coverage, 1644,
1689
56
      GIR_Done,
1690
56
    // Label 118: @3548
1691
56
    GIM_Try, /*On fail goto*//*Label 119*/ 3582, // Rule ID 1646 //
1692
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1693
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1694
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1695
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1696
56
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1697
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1698
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1699
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1700
56
      GIR_EraseFromParent, /*InsnID*/0,
1701
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1702
56
      // GIR_Coverage, 1646,
1703
56
      GIR_Done,
1704
56
    // Label 119: @3582
1705
56
    GIM_Reject,
1706
56
    // Label 74: @3583
1707
56
    GIM_Try, /*On fail goto*//*Label 120*/ 3617, // Rule ID 1658 //
1708
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1709
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1710
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_128RegClassID,
1711
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_128RegClassID,
1712
56
      // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
1713
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1714
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1715
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1716
56
      GIR_EraseFromParent, /*InsnID*/0,
1717
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_128*/21,
1718
56
      // GIR_Coverage, 1658,
1719
56
      GIR_Done,
1720
56
    // Label 120: @3617
1721
56
    GIM_Try, /*On fail goto*//*Label 121*/ 3651, // Rule ID 1660 //
1722
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1723
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1724
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1725
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1726
56
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1727
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1728
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1729
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1730
56
      GIR_EraseFromParent, /*InsnID*/0,
1731
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1732
56
      // GIR_Coverage, 1660,
1733
56
      GIR_Done,
1734
56
    // Label 121: @3651
1735
56
    GIM_Try, /*On fail goto*//*Label 122*/ 3685, // Rule ID 1661 //
1736
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1737
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1738
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1739
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1740
56
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1741
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1742
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1743
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1744
56
      GIR_EraseFromParent, /*InsnID*/0,
1745
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1746
56
      // GIR_Coverage, 1661,
1747
56
      GIR_Done,
1748
56
    // Label 122: @3685
1749
56
    GIM_Try, /*On fail goto*//*Label 123*/ 3719, // Rule ID 1664 //
1750
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1751
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1752
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1753
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1754
56
      // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
1755
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1756
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1757
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1758
56
      GIR_EraseFromParent, /*InsnID*/0,
1759
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1760
56
      // GIR_Coverage, 1664,
1761
56
      GIR_Done,
1762
56
    // Label 123: @3719
1763
56
    GIM_Try, /*On fail goto*//*Label 124*/ 3753, // Rule ID 1665 //
1764
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1765
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1766
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1767
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1768
56
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1769
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1770
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1771
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1772
56
      GIR_EraseFromParent, /*InsnID*/0,
1773
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1774
56
      // GIR_Coverage, 1665,
1775
56
      GIR_Done,
1776
56
    // Label 124: @3753
1777
56
    GIM_Reject,
1778
56
    // Label 75: @3754
1779
56
    GIM_Try, /*On fail goto*//*Label 125*/ 3788, // Rule ID 1640 //
1780
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1781
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1782
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1783
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1784
56
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1785
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1786
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1787
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1788
56
      GIR_EraseFromParent, /*InsnID*/0,
1789
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1790
56
      // GIR_Coverage, 1640,
1791
56
      GIR_Done,
1792
56
    // Label 125: @3788
1793
56
    GIM_Try, /*On fail goto*//*Label 126*/ 3822, // Rule ID 1643 //
1794
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1795
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1796
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1797
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1798
56
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1799
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1800
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1801
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1802
56
      GIR_EraseFromParent, /*InsnID*/0,
1803
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1804
56
      // GIR_Coverage, 1643,
1805
56
      GIR_Done,
1806
56
    // Label 126: @3822
1807
56
    GIM_Try, /*On fail goto*//*Label 127*/ 3856, // Rule ID 1645 //
1808
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1809
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1810
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1811
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1812
56
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1813
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1814
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1815
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1816
56
      GIR_EraseFromParent, /*InsnID*/0,
1817
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1818
56
      // GIR_Coverage, 1645,
1819
56
      GIR_Done,
1820
56
    // Label 127: @3856
1821
56
    GIM_Try, /*On fail goto*//*Label 128*/ 3890, // Rule ID 1647 //
1822
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1823
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1824
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1825
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1826
56
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1827
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1828
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1829
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1830
56
      GIR_EraseFromParent, /*InsnID*/0,
1831
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1832
56
      // GIR_Coverage, 1647,
1833
56
      GIR_Done,
1834
56
    // Label 128: @3890
1835
56
    GIM_Try, /*On fail goto*//*Label 129*/ 3924, // Rule ID 1648 //
1836
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1837
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1838
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1839
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1840
56
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1841
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1842
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1843
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1844
56
      GIR_EraseFromParent, /*InsnID*/0,
1845
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1846
56
      // GIR_Coverage, 1648,
1847
56
      GIR_Done,
1848
56
    // Label 129: @3924
1849
56
    GIM_Try, /*On fail goto*//*Label 130*/ 3958, // Rule ID 1649 //
1850
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1851
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1852
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1853
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1854
56
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1855
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1856
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1857
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1858
56
      GIR_EraseFromParent, /*InsnID*/0,
1859
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1860
56
      // GIR_Coverage, 1649,
1861
56
      GIR_Done,
1862
56
    // Label 130: @3958
1863
56
    GIM_Try, /*On fail goto*//*Label 131*/ 3992, // Rule ID 1652 //
1864
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1865
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1866
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1867
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1868
56
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1869
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1870
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1871
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1872
56
      GIR_EraseFromParent, /*InsnID*/0,
1873
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1874
56
      // GIR_Coverage, 1652,
1875
56
      GIR_Done,
1876
56
    // Label 131: @3992
1877
56
    GIM_Try, /*On fail goto*//*Label 132*/ 4026, // Rule ID 1653 //
1878
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1879
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1880
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1881
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1882
56
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1883
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1884
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1885
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1886
56
      GIR_EraseFromParent, /*InsnID*/0,
1887
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
1888
56
      // GIR_Coverage, 1653,
1889
56
      GIR_Done,
1890
56
    // Label 132: @4026
1891
56
    GIM_Reject,
1892
56
    // Label 76: @4027
1893
56
    GIM_Try, /*On fail goto*//*Label 133*/ 4061, // Rule ID 1656 //
1894
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1895
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1896
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1897
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1898
56
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
1899
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1900
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1901
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1902
56
      GIR_EraseFromParent, /*InsnID*/0,
1903
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1904
56
      // GIR_Coverage, 1656,
1905
56
      GIR_Done,
1906
56
    // Label 133: @4061
1907
56
    GIM_Try, /*On fail goto*//*Label 134*/ 4095, // Rule ID 1657 //
1908
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1909
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1910
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1911
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1912
56
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
1913
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1914
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1915
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1916
56
      GIR_EraseFromParent, /*InsnID*/0,
1917
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1918
56
      // GIR_Coverage, 1657,
1919
56
      GIR_Done,
1920
56
    // Label 134: @4095
1921
56
    GIM_Try, /*On fail goto*//*Label 135*/ 4129, // Rule ID 1659 //
1922
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1923
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1924
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_128RegClassID,
1925
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_128RegClassID,
1926
56
      // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
1927
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1928
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1929
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1930
56
      GIR_EraseFromParent, /*InsnID*/0,
1931
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_128*/21,
1932
56
      // GIR_Coverage, 1659,
1933
56
      GIR_Done,
1934
56
    // Label 135: @4129
1935
56
    GIM_Try, /*On fail goto*//*Label 136*/ 4163, // Rule ID 1662 //
1936
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1937
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1938
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1939
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1940
56
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
1941
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1942
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1943
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1944
56
      GIR_EraseFromParent, /*InsnID*/0,
1945
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1946
56
      // GIR_Coverage, 1662,
1947
56
      GIR_Done,
1948
56
    // Label 136: @4163
1949
56
    GIM_Try, /*On fail goto*//*Label 137*/ 4197, // Rule ID 1663 //
1950
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1951
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1952
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1953
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1954
56
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
1955
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1956
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1957
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1958
56
      GIR_EraseFromParent, /*InsnID*/0,
1959
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
1960
56
      // GIR_Coverage, 1663,
1961
56
      GIR_Done,
1962
56
    // Label 137: @4197
1963
56
    GIM_Reject,
1964
56
    // Label 77: @4198
1965
56
    GIM_Try, /*On fail goto*//*Label 138*/ 4325,
1966
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
1967
56
      GIM_Try, /*On fail goto*//*Label 139*/ 4234, // Rule ID 1666 //
1968
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1969
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_256RegClassID,
1970
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_256RegClassID,
1971
56
        // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v8f32] }:$src0)  =>  SReg_256:{ *:[v8i32] }:$src0
1972
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1973
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1974
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1975
56
        GIR_EraseFromParent, /*InsnID*/0,
1976
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_256*/26,
1977
56
        // GIR_Coverage, 1666,
1978
56
        GIR_Done,
1979
56
      // Label 139: @4234
1980
56
      GIM_Try, /*On fail goto*//*Label 140*/ 4264, // Rule ID 1667 //
1981
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1982
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_256RegClassID,
1983
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_256RegClassID,
1984
56
        // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v8i32] }:$src0)  =>  SReg_256:{ *:[v8f32] }:$src0
1985
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1986
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1987
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1988
56
        GIR_EraseFromParent, /*InsnID*/0,
1989
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_256*/26,
1990
56
        // GIR_Coverage, 1667,
1991
56
        GIR_Done,
1992
56
      // Label 140: @4264
1993
56
      GIM_Try, /*On fail goto*//*Label 141*/ 4294, // Rule ID 1668 //
1994
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
1995
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_256RegClassID,
1996
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_256RegClassID,
1997
56
        // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
1998
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1999
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2000
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2001
56
        GIR_EraseFromParent, /*InsnID*/0,
2002
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_256*/25,
2003
56
        // GIR_Coverage, 1668,
2004
56
        GIR_Done,
2005
56
      // Label 141: @4294
2006
56
      GIM_Try, /*On fail goto*//*Label 142*/ 4324, // Rule ID 1669 //
2007
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2008
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_256RegClassID,
2009
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_256RegClassID,
2010
56
        // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
2011
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2012
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2013
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2014
56
        GIR_EraseFromParent, /*InsnID*/0,
2015
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_256*/25,
2016
56
        // GIR_Coverage, 1669,
2017
56
        GIR_Done,
2018
56
      // Label 142: @4324
2019
56
      GIM_Reject,
2020
56
    // Label 138: @4325
2021
56
    GIM_Reject,
2022
56
    // Label 78: @4326
2023
56
    GIM_Try, /*On fail goto*//*Label 143*/ 4385,
2024
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
2025
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_512RegClassID,
2026
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_512RegClassID,
2027
56
      GIM_Try, /*On fail goto*//*Label 144*/ 4362, // Rule ID 1670 //
2028
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2029
56
        // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
2030
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2031
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2032
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2033
56
        GIR_EraseFromParent, /*InsnID*/0,
2034
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_512*/29,
2035
56
        // GIR_Coverage, 1670,
2036
56
        GIR_Done,
2037
56
      // Label 144: @4362
2038
56
      GIM_Try, /*On fail goto*//*Label 145*/ 4384, // Rule ID 1671 //
2039
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2040
56
        // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
2041
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2042
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2043
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2044
56
        GIR_EraseFromParent, /*InsnID*/0,
2045
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_512*/29,
2046
56
        // GIR_Coverage, 1671,
2047
56
        GIR_Done,
2048
56
      // Label 145: @4384
2049
56
      GIM_Reject,
2050
56
    // Label 143: @4385
2051
56
    GIM_Reject,
2052
56
    // Label 79: @4386
2053
56
    GIM_Reject,
2054
56
    // Label 7: @4387
2055
56
    GIM_Try, /*On fail goto*//*Label 146*/ 4477,
2056
56
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
2057
56
      GIM_Try, /*On fail goto*//*Label 147*/ 4420, // Rule ID 10 //
2058
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2059
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_getpc,
2060
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2061
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2062
56
        // (intrinsic_wo_chain:{ *:[i64] } 965:{ *:[iPTR] })  =>  (S_GETPC_B64:{ *:[i64] })
2063
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_GETPC_B64,
2064
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2065
56
        GIR_EraseFromParent, /*InsnID*/0,
2066
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2067
56
        // GIR_Coverage, 10,
2068
56
        GIR_Done,
2069
56
      // Label 147: @4420
2070
56
      GIM_Try, /*On fail goto*//*Label 148*/ 4448, // Rule ID 663 //
2071
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2072
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_groupstaticsize,
2073
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2074
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2075
56
        // (intrinsic_wo_chain:{ *:[i32] } 450:{ *:[iPTR] })  =>  (GET_GROUPSTATICSIZE:{ *:[i32] })
2076
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GET_GROUPSTATICSIZE,
2077
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2078
56
        GIR_EraseFromParent, /*InsnID*/0,
2079
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2080
56
        // GIR_Coverage, 663,
2081
56
        GIR_Done,
2082
56
      // Label 148: @4448
2083
56
      GIM_Try, /*On fail goto*//*Label 149*/ 4476, // Rule ID 670 //
2084
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2085
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_ps_live,
2086
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
2087
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2088
56
        // (intrinsic_wo_chain:{ *:[i1] } 931:{ *:[iPTR] })  =>  (SI_PS_LIVE:{ *:[i1] })
2089
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_PS_LIVE,
2090
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2091
56
        GIR_EraseFromParent, /*InsnID*/0,
2092
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2093
56
        // GIR_Coverage, 670,
2094
56
        GIR_Done,
2095
56
      // Label 149: @4476
2096
56
      GIM_Reject,
2097
56
    // Label 146: @4477
2098
56
    GIM_Try, /*On fail goto*//*Label 150*/ 4912,
2099
56
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2100
56
      GIM_Try, /*On fail goto*//*Label 151*/ 4518, // Rule ID 2 //
2101
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2102
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_wqm_vote,
2103
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
2104
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
2105
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2106
56
        // (intrinsic_wo_chain:{ *:[i1] } 1018:{ *:[iPTR] }, i1:{ *:[i1] }:$src0)  =>  (S_WQM_B64:{ *:[i1] }:{ *:[i1] } i1:{ *:[i1] }:$src0)
2107
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_WQM_B64,
2108
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2109
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2110
56
        GIR_EraseFromParent, /*InsnID*/0,
2111
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2112
56
        // GIR_Coverage, 2,
2113
56
        GIR_Done,
2114
56
      // Label 151: @4518
2115
56
      GIM_Try, /*On fail goto*//*Label 152*/ 4554, // Rule ID 321 //
2116
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2117
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_readfirstlane,
2118
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2119
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2120
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2121
56
        // (intrinsic_wo_chain:{ *:[i32] } 953:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
2122
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READFIRSTLANE_B32,
2123
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2124
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2125
56
        GIR_EraseFromParent, /*InsnID*/0,
2126
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2127
56
        // GIR_Coverage, 321,
2128
56
        GIR_Done,
2129
56
      // Label 152: @4554
2130
56
      GIM_Try, /*On fail goto*//*Label 153*/ 4605, // Rule ID 356 //
2131
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2132
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2133
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2134
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2135
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2136
56
        // (intrinsic_wo_chain:{ *:[i32] } 448:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2137
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F64_e64,
2138
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2139
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2140
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2141
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2142
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2143
56
        GIR_EraseFromParent, /*InsnID*/0,
2144
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2145
56
        // GIR_Coverage, 356,
2146
56
        GIR_Done,
2147
56
      // Label 153: @4605
2148
56
      GIM_Try, /*On fail goto*//*Label 154*/ 4656, // Rule ID 357 //
2149
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2150
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2151
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2152
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2153
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2154
56
        // (intrinsic_wo_chain:{ *:[f64] } 449:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2155
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F64_e64,
2156
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2157
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2158
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2159
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2160
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2161
56
        GIR_EraseFromParent, /*InsnID*/0,
2162
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2163
56
        // GIR_Coverage, 357,
2164
56
        GIR_Done,
2165
56
      // Label 154: @4656
2166
56
      GIM_Try, /*On fail goto*//*Label 155*/ 4707, // Rule ID 359 //
2167
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2168
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2169
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2170
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2171
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2172
56
        // (intrinsic_wo_chain:{ *:[i32] } 448:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2173
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F32_e64,
2174
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2175
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2176
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2177
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2178
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2179
56
        GIR_EraseFromParent, /*InsnID*/0,
2180
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2181
56
        // GIR_Coverage, 359,
2182
56
        GIR_Done,
2183
56
      // Label 155: @4707
2184
56
      GIM_Try, /*On fail goto*//*Label 156*/ 4758, // Rule ID 360 //
2185
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2186
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2187
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2188
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2189
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2190
56
        // (intrinsic_wo_chain:{ *:[f32] } 449:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2191
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F32_e64,
2192
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2193
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2194
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2195
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2196
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2197
56
        GIR_EraseFromParent, /*InsnID*/0,
2198
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2199
56
        // GIR_Coverage, 360,
2200
56
        GIR_Done,
2201
56
      // Label 156: @4758
2202
56
      GIM_Try, /*On fail goto*//*Label 157*/ 4809, // Rule ID 361 //
2203
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_log_clamp,
2204
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2205
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2206
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2207
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2208
56
        // (intrinsic_wo_chain:{ *:[f32] } 923:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_CLAMP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2209
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_CLAMP_F32_e64,
2210
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2211
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2212
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2213
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2214
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2215
56
        GIR_EraseFromParent, /*InsnID*/0,
2216
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2217
56
        // GIR_Coverage, 361,
2218
56
        GIR_Done,
2219
56
      // Label 157: @4809
2220
56
      GIM_Try, /*On fail goto*//*Label 158*/ 4860, // Rule ID 381 //
2221
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2222
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
2223
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2224
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2225
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2226
56
        // (intrinsic_wo_chain:{ *:[f16] } 449:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2227
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F16_e64,
2228
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2229
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2230
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2231
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2232
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2233
56
        GIR_EraseFromParent, /*InsnID*/0,
2234
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2235
56
        // GIR_Coverage, 381,
2236
56
        GIR_Done,
2237
56
      // Label 158: @4860
2238
56
      GIM_Try, /*On fail goto*//*Label 159*/ 4911, // Rule ID 382 //
2239
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2240
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
2241
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2242
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2243
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2244
56
        // (intrinsic_wo_chain:{ *:[i16] } 448:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2245
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I16_F16_e64,
2246
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2247
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2248
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2249
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2250
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2251
56
        GIR_EraseFromParent, /*InsnID*/0,
2252
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2253
56
        // GIR_Coverage, 382,
2254
56
        GIR_Done,
2255
56
      // Label 159: @4911
2256
56
      GIM_Reject,
2257
56
    // Label 150: @4912
2258
56
    GIM_Try, /*On fail goto*//*Label 160*/ 5744,
2259
56
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
2260
56
      GIM_Try, /*On fail goto*//*Label 161*/ 4987, // Rule ID 1963 //
2261
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2262
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pkrtz,
2263
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
2264
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2265
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2266
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2267
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2268
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2269
56
        // (intrinsic_wo_chain:{ *:[v2f16] } 425:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_CVT_PKRTZ_F16_F32_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2270
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PKRTZ_F16_F32_e64,
2271
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2272
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2273
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2274
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2275
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2276
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2277
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
2278
56
        GIR_EraseFromParent, /*InsnID*/0,
2279
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2280
56
        // GIR_Coverage, 1963,
2281
56
        GIR_Done,
2282
56
      // Label 161: @4987
2283
56
      GIM_Try, /*On fail goto*//*Label 162*/ 5057, // Rule ID 1964 //
2284
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2285
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2286
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2287
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2288
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2289
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2290
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2291
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2292
56
        // (intrinsic_wo_chain:{ *:[f64] } 139:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2293
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
2294
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2295
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2296
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2297
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2298
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2299
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2300
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
2301
56
        GIR_EraseFromParent, /*InsnID*/0,
2302
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2303
56
        // GIR_Coverage, 1964,
2304
56
        GIR_Done,
2305
56
      // Label 162: @5057
2306
56
      GIM_Try, /*On fail goto*//*Label 163*/ 5127, // Rule ID 1967 //
2307
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2308
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2309
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2310
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2311
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2312
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2313
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2314
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2315
56
        // (intrinsic_wo_chain:{ *:[f64] } 147:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2316
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
2317
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2318
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2319
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2320
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2321
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2322
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2323
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
2324
56
        GIR_EraseFromParent, /*InsnID*/0,
2325
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2326
56
        // GIR_Coverage, 1967,
2327
56
        GIR_Done,
2328
56
      // Label 163: @5127
2329
56
      GIM_Try, /*On fail goto*//*Label 164*/ 5197, // Rule ID 3221 //
2330
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2331
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2332
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2333
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2334
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2335
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2336
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods,
2337
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods0,
2338
56
        // (intrinsic_wo_chain:{ *:[f64] } 139:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods))  =>  (V_MAX_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2339
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
2340
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2341
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
2342
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
2343
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
2344
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
2345
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
2346
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omods
2347
56
        GIR_EraseFromParent, /*InsnID*/0,
2348
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2349
56
        // GIR_Coverage, 3221,
2350
56
        GIR_Done,
2351
56
      // Label 164: @5197
2352
56
      GIM_Try, /*On fail goto*//*Label 165*/ 5267, // Rule ID 3222 //
2353
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2354
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2355
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2356
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2357
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2358
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2359
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods,
2360
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods0,
2361
56
        // (intrinsic_wo_chain:{ *:[f64] } 147:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods))  =>  (V_MIN_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2362
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
2363
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2364
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
2365
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
2366
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
2367
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
2368
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
2369
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omods
2370
56
        GIR_EraseFromParent, /*InsnID*/0,
2371
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2372
56
        // GIR_Coverage, 3222,
2373
56
        GIR_Done,
2374
56
      // Label 165: @5267
2375
56
      GIM_Try, /*On fail goto*//*Label 166*/ 5320, // Rule ID 1955 //
2376
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2377
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2378
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2379
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2380
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2381
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2382
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
2383
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
2384
56
        // (intrinsic_wo_chain:{ *:[f32] } 139:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_MAX_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2385
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e32,
2386
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2387
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2388
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2389
56
        GIR_EraseFromParent, /*InsnID*/0,
2390
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2391
56
        // GIR_Coverage, 1955,
2392
56
        GIR_Done,
2393
56
      // Label 166: @5320
2394
56
      GIM_Try, /*On fail goto*//*Label 167*/ 5373, // Rule ID 1965 //
2395
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2396
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2397
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2398
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2399
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2400
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2401
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
2402
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
2403
56
        // (intrinsic_wo_chain:{ *:[f32] } 147:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_MIN_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2404
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e32,
2405
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2406
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2407
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2408
56
        GIR_EraseFromParent, /*InsnID*/0,
2409
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2410
56
        // GIR_Coverage, 1965,
2411
56
        GIR_Done,
2412
56
      // Label 167: @5373
2413
56
      GIM_Try, /*On fail goto*//*Label 168*/ 5426, // Rule ID 1956 //
2414
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2415
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2416
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2417
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2418
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2419
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2420
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
2421
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
2422
56
        // (intrinsic_wo_chain:{ *:[f32] } 139:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_MAX_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2423
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e32,
2424
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2425
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2426
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2427
56
        GIR_EraseFromParent, /*InsnID*/0,
2428
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2429
56
        // GIR_Coverage, 1956,
2430
56
        GIR_Done,
2431
56
      // Label 168: @5426
2432
56
      GIM_Try, /*On fail goto*//*Label 169*/ 5479, // Rule ID 1966 //
2433
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2434
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2435
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2436
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2437
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2438
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2439
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
2440
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
2441
56
        // (intrinsic_wo_chain:{ *:[f32] } 147:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_MIN_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2442
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e32,
2443
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2444
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2445
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2446
56
        GIR_EraseFromParent, /*InsnID*/0,
2447
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2448
56
        // GIR_Coverage, 1966,
2449
56
        GIR_Done,
2450
56
      // Label 169: @5479
2451
56
      GIM_Try, /*On fail goto*//*Label 170*/ 5523, // Rule ID 418 //
2452
56
        GIM_CheckFeatures, GIFBS_isGCN,
2453
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_readlane,
2454
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2455
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2456
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2457
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2458
56
        // (intrinsic_wo_chain:{ *:[i32] } 954:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2459
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READLANE_B32,
2460
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2461
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2462
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2463
56
        GIR_EraseFromParent, /*InsnID*/0,
2464
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2465
56
        // GIR_Coverage, 418,
2466
56
        GIR_Done,
2467
56
      // Label 170: @5523
2468
56
      GIM_Try, /*On fail goto*//*Label 171*/ 5567, // Rule ID 659 //
2469
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2470
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_set_inactive,
2471
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2472
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2473
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2474
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2475
56
        // (intrinsic_wo_chain:{ *:[i32] } 981:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)
2476
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B32,
2477
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2478
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2479
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
2480
56
        GIR_EraseFromParent, /*InsnID*/0,
2481
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2482
56
        // GIR_Coverage, 659,
2483
56
        GIR_Done,
2484
56
      // Label 171: @5567
2485
56
      GIM_Try, /*On fail goto*//*Label 172*/ 5611, // Rule ID 660 //
2486
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2487
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_set_inactive,
2488
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2489
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2490
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2491
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2492
56
        // (intrinsic_wo_chain:{ *:[i64] } 981:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)  =>  (V_SET_INACTIVE_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)
2493
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B64,
2494
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2495
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2496
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
2497
56
        GIR_EraseFromParent, /*InsnID*/0,
2498
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2499
56
        // GIR_Coverage, 660,
2500
56
        GIR_Done,
2501
56
      // Label 172: @5611
2502
56
      GIM_Try, /*On fail goto*//*Label 173*/ 5655, // Rule ID 669 //
2503
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2504
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_if_break,
2505
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2506
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
2507
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2508
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2509
56
        // (intrinsic_wo_chain:{ *:[i64] } 453:{ *:[iPTR] }, i1:{ *:[i1] }:$vcc, i64:{ *:[i64] }:$src)  =>  (SI_IF_BREAK:{ *:[i64] }:{ *:[i1] } i1:{ *:[i1] }:$vcc, i64:{ *:[i64] }:$src)
2510
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_IF_BREAK,
2511
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2512
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vcc
2513
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
2514
56
        GIR_EraseFromParent, /*InsnID*/0,
2515
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2516
56
        // GIR_Coverage, 669,
2517
56
        GIR_Done,
2518
56
      // Label 173: @5655
2519
56
      GIM_Try, /*On fail goto*//*Label 174*/ 5699, // Rule ID 420 //
2520
56
        GIM_CheckFeatures, GIFBS_isGCN,
2521
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mbcnt_lo,
2522
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2523
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2524
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2525
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2526
56
        // (intrinsic_wo_chain:{ *:[i32] } 926:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_LO_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2527
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_LO_U32_B32_e64,
2528
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2529
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2530
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2531
56
        GIR_EraseFromParent, /*InsnID*/0,
2532
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2533
56
        // GIR_Coverage, 420,
2534
56
        GIR_Done,
2535
56
      // Label 174: @5699
2536
56
      GIM_Try, /*On fail goto*//*Label 175*/ 5743, // Rule ID 421 //
2537
56
        GIM_CheckFeatures, GIFBS_isGCN,
2538
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mbcnt_hi,
2539
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2540
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2541
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2542
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2543
56
        // (intrinsic_wo_chain:{ *:[i32] } 925:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_HI_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2544
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_HI_U32_B32_e64,
2545
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2546
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2547
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2548
56
        GIR_EraseFromParent, /*InsnID*/0,
2549
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2550
56
        // GIR_Coverage, 421,
2551
56
        GIR_Done,
2552
56
      // Label 175: @5743
2553
56
      GIM_Reject,
2554
56
    // Label 160: @5744
2555
56
    GIM_Try, /*On fail goto*//*Label 176*/ 6758,
2556
56
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
2557
56
      GIM_Try, /*On fail goto*//*Label 177*/ 5801, // Rule ID 419 //
2558
56
        GIM_CheckFeatures, GIFBS_isGCN,
2559
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_writelane,
2560
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2561
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2562
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2563
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2564
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2565
56
        // (intrinsic_wo_chain:{ *:[i32] } 1019:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)  =>  (V_WRITELANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)
2566
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_WRITELANE_B32,
2567
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2568
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2569
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2570
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vdst_in
2571
56
        GIR_EraseFromParent, /*InsnID*/0,
2572
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2573
56
        // GIR_Coverage, 419,
2574
56
        GIR_Done,
2575
56
      // Label 177: @5801
2576
56
      GIM_Try, /*On fail goto*//*Label 178*/ 5856, // Rule ID 970 //
2577
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2578
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_u8,
2579
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2580
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2581
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2582
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2583
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2584
56
        // (intrinsic_wo_chain:{ *:[i32] } 976:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2585
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U8,
2586
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2587
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2588
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2589
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2590
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2591
56
        GIR_EraseFromParent, /*InsnID*/0,
2592
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2593
56
        // GIR_Coverage, 970,
2594
56
        GIR_Done,
2595
56
      // Label 178: @5856
2596
56
      GIM_Try, /*On fail goto*//*Label 179*/ 5911, // Rule ID 971 //
2597
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2598
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_hi_u8,
2599
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2600
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2601
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2602
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2603
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2604
56
        // (intrinsic_wo_chain:{ *:[i32] } 974:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_HI_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2605
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_HI_U8,
2606
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2607
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2608
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2609
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2610
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2611
56
        GIR_EraseFromParent, /*InsnID*/0,
2612
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2613
56
        // GIR_Coverage, 971,
2614
56
        GIR_Done,
2615
56
      // Label 179: @5911
2616
56
      GIM_Try, /*On fail goto*//*Label 180*/ 5966, // Rule ID 972 //
2617
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2618
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_u16,
2619
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2620
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2621
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2622
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2623
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2624
56
        // (intrinsic_wo_chain:{ *:[i32] } 975:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U16:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2625
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U16,
2626
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2627
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2628
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2629
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2630
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2631
56
        GIR_EraseFromParent, /*InsnID*/0,
2632
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2633
56
        // GIR_Coverage, 972,
2634
56
        GIR_Done,
2635
56
      // Label 180: @5966
2636
56
      GIM_Try, /*On fail goto*//*Label 181*/ 6021, // Rule ID 973 //
2637
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2638
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_msad_u8,
2639
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2640
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2641
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2642
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2643
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2644
56
        // (intrinsic_wo_chain:{ *:[i32] } 930:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_MSAD_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2645
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MSAD_U8,
2646
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2647
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2648
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2649
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2650
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2651
56
        GIR_EraseFromParent, /*InsnID*/0,
2652
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2653
56
        // GIR_Coverage, 973,
2654
56
        GIR_Done,
2655
56
      // Label 181: @6021
2656
56
      GIM_Try, /*On fail goto*//*Label 182*/ 6076, // Rule ID 974 //
2657
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2658
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mqsad_pk_u16_u8,
2659
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2660
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2661
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2662
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
2663
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2664
56
        // (intrinsic_wo_chain:{ *:[i64] } 928:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_MQSAD_PK_U16_U8:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
2665
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_PK_U16_U8,
2666
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2667
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2668
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2669
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2670
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2671
56
        GIR_EraseFromParent, /*InsnID*/0,
2672
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2673
56
        // GIR_Coverage, 974,
2674
56
        GIR_Done,
2675
56
      // Label 182: @6076
2676
56
      GIM_Try, /*On fail goto*//*Label 183*/ 6131, // Rule ID 975 //
2677
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2678
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_qsad_pk_u16_u8,
2679
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2680
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2681
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2682
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
2683
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2684
56
        // (intrinsic_wo_chain:{ *:[i64] } 932:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_QSAD_PK_U16_U8:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
2685
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_QSAD_PK_U16_U8,
2686
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2687
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2688
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2689
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2690
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2691
56
        GIR_EraseFromParent, /*InsnID*/0,
2692
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2693
56
        // GIR_Coverage, 975,
2694
56
        GIR_Done,
2695
56
      // Label 183: @6131
2696
56
      GIM_Try, /*On fail goto*//*Label 184*/ 6186, // Rule ID 976 //
2697
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2698
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mqsad_u32_u8,
2699
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
2700
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2701
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2702
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
2703
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
2704
56
        // (intrinsic_wo_chain:{ *:[v4i32] } 929:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2)  =>  (V_MQSAD_U32_U8:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] })
2705
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_U32_U8,
2706
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2707
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2708
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2709
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2710
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2711
56
        GIR_EraseFromParent, /*InsnID*/0,
2712
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2713
56
        // GIR_Coverage, 976,
2714
56
        GIR_Done,
2715
56
      // Label 184: @6186
2716
56
      GIM_Try, /*On fail goto*//*Label 185*/ 6271, // Rule ID 458 //
2717
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubeid,
2718
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2719
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2720
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2721
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2722
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2723
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2724
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2725
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2726
56
        // (intrinsic_wo_chain:{ *:[f32] } 416:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEID_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2727
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEID_F32,
2728
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2729
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2730
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2731
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2732
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2733
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2734
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2735
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2736
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2737
56
        GIR_EraseFromParent, /*InsnID*/0,
2738
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2739
56
        // GIR_Coverage, 458,
2740
56
        GIR_Done,
2741
56
      // Label 185: @6271
2742
56
      GIM_Try, /*On fail goto*//*Label 186*/ 6356, // Rule ID 459 //
2743
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubesc,
2744
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2745
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2746
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2747
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2748
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2749
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2750
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2751
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2752
56
        // (intrinsic_wo_chain:{ *:[f32] } 418:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBESC_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2753
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBESC_F32,
2754
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2755
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2756
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2757
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2758
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2759
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2760
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2761
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2762
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2763
56
        GIR_EraseFromParent, /*InsnID*/0,
2764
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2765
56
        // GIR_Coverage, 459,
2766
56
        GIR_Done,
2767
56
      // Label 186: @6356
2768
56
      GIM_Try, /*On fail goto*//*Label 187*/ 6441, // Rule ID 460 //
2769
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubetc,
2770
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2771
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2772
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2773
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2774
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2775
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2776
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2777
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2778
56
        // (intrinsic_wo_chain:{ *:[f32] } 419:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBETC_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2779
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBETC_F32,
2780
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2781
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2782
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2783
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2784
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2785
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2786
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2787
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2788
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2789
56
        GIR_EraseFromParent, /*InsnID*/0,
2790
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2791
56
        // GIR_Coverage, 460,
2792
56
        GIR_Done,
2793
56
      // Label 187: @6441
2794
56
      GIM_Try, /*On fail goto*//*Label 188*/ 6526, // Rule ID 461 //
2795
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubema,
2796
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2797
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2798
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2799
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2800
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2801
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2802
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2803
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2804
56
        // (intrinsic_wo_chain:{ *:[f32] } 417:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEMA_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2805
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEMA_F32,
2806
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2807
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2808
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2809
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2810
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2811
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2812
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2813
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2814
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2815
56
        GIR_EraseFromParent, /*InsnID*/0,
2816
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2817
56
        // GIR_Coverage, 461,
2818
56
        GIR_Done,
2819
56
      // Label 188: @6526
2820
56
      GIM_Try, /*On fail goto*//*Label 189*/ 6607, // Rule ID 476 //
2821
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pk_u8_f32,
2822
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2823
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2824
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2825
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2826
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2827
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2828
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2829
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2830
56
        // (intrinsic_wo_chain:{ *:[i32] } 422:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CVT_PK_U8_F32:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
2831
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PK_U8_F32,
2832
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2833
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2834
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2835
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2836
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2837
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2838
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2839
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2840
56
        GIR_EraseFromParent, /*InsnID*/0,
2841
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2842
56
        // GIR_Coverage, 476,
2843
56
        GIR_Done,
2844
56
      // Label 189: @6607
2845
56
      GIM_Try, /*On fail goto*//*Label 190*/ 6657, // Rule ID 446 //
2846
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_lerp,
2847
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2848
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2849
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2850
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2851
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2852
56
        // (intrinsic_wo_chain:{ *:[i32] } 922:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_LERP_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
2853
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LERP_U8,
2854
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2855
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2856
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2857
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2858
56
        GIR_EraseFromParent, /*InsnID*/0,
2859
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2860
56
        // GIR_Coverage, 446,
2861
56
        GIR_Done,
2862
56
      // Label 190: @6657
2863
56
      GIM_Try, /*On fail goto*//*Label 191*/ 6707, // Rule ID 465 //
2864
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_alignbit,
2865
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2866
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2867
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2868
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2869
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2870
56
        // (intrinsic_wo_chain:{ *:[i32] } 392:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBIT_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
2871
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBIT_B32,
2872
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2873
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2874
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2875
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2876
56
        GIR_EraseFromParent, /*InsnID*/0,
2877
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2878
56
        // GIR_Coverage, 465,
2879
56
        GIR_Done,
2880
56
      // Label 191: @6707
2881
56
      GIM_Try, /*On fail goto*//*Label 192*/ 6757, // Rule ID 466 //
2882
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_alignbyte,
2883
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2884
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2885
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2886
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2887
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2888
56
        // (intrinsic_wo_chain:{ *:[i32] } 393:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBYTE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
2889
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBYTE_B32,
2890
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2891
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2892
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2893
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2894
56
        GIR_EraseFromParent, /*InsnID*/0,
2895
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2896
56
        // GIR_Coverage, 466,
2897
56
        GIR_Done,
2898
56
      // Label 192: @6757
2899
56
      GIM_Reject,
2900
56
    // Label 176: @6758
2901
56
    GIM_Reject,
2902
56
    // Label 8: @6759
2903
56
    GIM_Try, /*On fail goto*//*Label 193*/ 6779, // Rule ID 53 //
2904
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2905
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_barrier,
2906
56
      // (intrinsic_void 958:{ *:[iPTR] })  =>  (S_BARRIER)
2907
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_BARRIER,
2908
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2909
56
      GIR_EraseFromParent, /*InsnID*/0,
2910
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2911
56
      // GIR_Coverage, 53,
2912
56
      GIR_Done,
2913
56
    // Label 193: @6779
2914
56
    GIM_Try, /*On fail goto*//*Label 194*/ 6799, // Rule ID 516 //
2915
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2916
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_inv,
2917
56
      // (intrinsic_void 960:{ *:[iPTR] })  =>  (S_DCACHE_INV)
2918
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV,
2919
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2920
56
      GIR_EraseFromParent, /*InsnID*/0,
2921
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2922
56
      // GIR_Coverage, 516,
2923
56
      GIR_Done,
2924
56
    // Label 194: @6799
2925
56
    GIM_Try, /*On fail goto*//*Label 195*/ 6819, // Rule ID 517 //
2926
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isCIVI,
2927
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_inv_vol,
2928
56
      // (intrinsic_void 961:{ *:[iPTR] })  =>  (S_DCACHE_INV_VOL)
2929
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV_VOL,
2930
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2931
56
      GIR_EraseFromParent, /*InsnID*/0,
2932
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2933
56
      // GIR_Coverage, 517,
2934
56
      GIR_Done,
2935
56
    // Label 195: @6819
2936
56
    GIM_Try, /*On fail goto*//*Label 196*/ 6839, // Rule ID 518 //
2937
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
2938
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_wb,
2939
56
      // (intrinsic_void 962:{ *:[iPTR] })  =>  (S_DCACHE_WB)
2940
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB,
2941
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2942
56
      GIR_EraseFromParent, /*InsnID*/0,
2943
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2944
56
      // GIR_Coverage, 518,
2945
56
      GIR_Done,
2946
56
    // Label 196: @6839
2947
56
    GIM_Try, /*On fail goto*//*Label 197*/ 6859, // Rule ID 519 //
2948
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
2949
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_wb_vol,
2950
56
      // (intrinsic_void 963:{ *:[iPTR] })  =>  (S_DCACHE_WB_VOL)
2951
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB_VOL,
2952
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2953
56
      GIR_EraseFromParent, /*InsnID*/0,
2954
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2955
56
      // GIR_Coverage, 519,
2956
56
      GIR_Done,
2957
56
    // Label 197: @6859
2958
56
    GIM_Try, /*On fail goto*//*Label 198*/ 6879, // Rule ID 649 //
2959
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isSI,
2960
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1_sc,
2961
56
      // (intrinsic_void 412:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_SC)
2962
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_SC,
2963
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2964
56
      GIR_EraseFromParent, /*InsnID*/0,
2965
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2966
56
      // GIR_Coverage, 649,
2967
56
      GIR_Done,
2968
56
    // Label 198: @6879
2969
56
    GIM_Try, /*On fail goto*//*Label 199*/ 6899, // Rule ID 650 //
2970
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2971
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1,
2972
56
      // (intrinsic_void 411:{ *:[iPTR] })  =>  (BUFFER_WBINVL1)
2973
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1,
2974
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2975
56
      GIR_EraseFromParent, /*InsnID*/0,
2976
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2977
56
      // GIR_Coverage, 650,
2978
56
      GIR_Done,
2979
56
    // Label 199: @6899
2980
56
    GIM_Try, /*On fail goto*//*Label 200*/ 6919, // Rule ID 651 //
2981
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isCIVI,
2982
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1_vol,
2983
56
      // (intrinsic_void 413:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_VOL)
2984
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_VOL,
2985
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2986
56
      GIR_EraseFromParent, /*InsnID*/0,
2987
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2988
56
      // GIR_Coverage, 651,
2989
56
      GIR_Done,
2990
56
    // Label 200: @6919
2991
56
    GIM_Try, /*On fail goto*//*Label 201*/ 6939, // Rule ID 664 //
2992
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
2993
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_wave_barrier,
2994
56
      // (intrinsic_void 1010:{ *:[iPTR] })  =>  (WAVE_BARRIER)
2995
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::WAVE_BARRIER,
2996
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2997
56
      GIR_EraseFromParent, /*InsnID*/0,
2998
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2999
56
      // GIR_Coverage, 664,
3000
56
      GIR_Done,
3001
56
    // Label 201: @6939
3002
56
    GIM_Try, /*On fail goto*//*Label 202*/ 6959, // Rule ID 671 //
3003
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3004
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_unreachable,
3005
56
      // (intrinsic_void 1008:{ *:[iPTR] })  =>  (SI_MASKED_UNREACHABLE)
3006
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_MASKED_UNREACHABLE,
3007
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3008
56
      GIR_EraseFromParent, /*InsnID*/0,
3009
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3010
56
      // GIR_Coverage, 671,
3011
56
      GIR_Done,
3012
56
    // Label 202: @6959
3013
56
    GIM_Try, /*On fail goto*//*Label 203*/ 7057,
3014
56
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
3015
56
      GIM_Try, /*On fail goto*//*Label 204*/ 6996, // Rule ID 515 //
3016
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3017
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_memtime,
3018
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
3019
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64_XEXECRegClassID,
3020
56
        // (intrinsic_w_chain:{ *:[i64] } 969:{ *:[iPTR] })  =>  (S_MEMTIME:{ *:[i64] })
3021
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMTIME,
3022
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3023
56
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3024
56
        GIR_EraseFromParent, /*InsnID*/0,
3025
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3026
56
        // GIR_Coverage, 515,
3027
56
        GIR_Done,
3028
56
      // Label 204: @6996
3029
56
      GIM_Try, /*On fail goto*//*Label 205*/ 7028, // Rule ID 520 //
3030
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
3031
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_memrealtime,
3032
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
3033
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64_XEXECRegClassID,
3034
56
        // (intrinsic_w_chain:{ *:[i64] } 968:{ *:[iPTR] })  =>  (S_MEMREALTIME:{ *:[i64] })
3035
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMREALTIME,
3036
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3037
56
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3038
56
        GIR_EraseFromParent, /*InsnID*/0,
3039
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3040
56
        // GIR_Coverage, 520,
3041
56
        GIR_Done,
3042
56
      // Label 205: @7028
3043
56
      GIM_Try, /*On fail goto*//*Label 206*/ 7056, // Rule ID 668 //
3044
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3045
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_end_cf,
3046
56
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3047
56
        // (intrinsic_void 438:{ *:[iPTR] }, i64:{ *:[i64] }:$saved)  =>  (SI_END_CF i64:{ *:[i64] }:$saved)
3048
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_END_CF,
3049
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // saved
3050
56
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3051
56
        GIR_EraseFromParent, /*InsnID*/0,
3052
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3053
56
        // GIR_Coverage, 668,
3054
56
        GIR_Done,
3055
56
      // Label 206: @7056
3056
56
      GIM_Reject,
3057
56
    // Label 203: @7057
3058
56
    GIM_Reject,
3059
56
    // Label 9: @7058
3060
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 209*/ 7114,
3061
56
    /*GILLT_s16*//*Label 207*/ 7066,
3062
56
    /*GILLT_s32*//*Label 208*/ 7090,
3063
56
    // Label 207: @7066
3064
56
    GIM_Try, /*On fail goto*//*Label 210*/ 7089, // Rule ID 825 //
3065
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3066
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3067
56
      // MIs[0] Operand 1
3068
56
      // No operand predicates
3069
56
      // (imm:{ *:[i16] }):$imm  =>  (S_MOV_B32:{ *:[i16] } (imm:{ *:[i16] }):$imm)
3070
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
3071
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3072
56
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
3073
56
      GIR_EraseFromParent, /*InsnID*/0,
3074
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3075
56
      // GIR_Coverage, 825,
3076
56
      GIR_Done,
3077
56
    // Label 210: @7089
3078
56
    GIM_Reject,
3079
56
    // Label 208: @7090
3080
56
    GIM_Try, /*On fail goto*//*Label 211*/ 7113, // Rule ID 1696 //
3081
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3082
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3083
56
      // MIs[0] Operand 1
3084
56
      // No operand predicates
3085
56
      // (imm:{ *:[i32] }):$imm  =>  (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
3086
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
3087
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3088
56
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
3089
56
      GIR_EraseFromParent, /*InsnID*/0,
3090
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3091
56
      // GIR_Coverage, 1696,
3092
56
      GIR_Done,
3093
56
    // Label 211: @7113
3094
56
    GIM_Reject,
3095
56
    // Label 209: @7114
3096
56
    GIM_Reject,
3097
56
    // Label 10: @7115
3098
56
    GIM_Try, /*On fail goto*//*Label 212*/ 7145, // Rule ID 435 //
3099
56
      GIM_CheckFeatures, GIFBS_isSICI,
3100
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3101
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3102
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3103
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3104
56
      // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3105
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_LSHL_B32_e64,
3106
56
      GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
3107
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3108
56
      // GIR_Coverage, 435,
3109
56
      GIR_Done,
3110
56
    // Label 212: @7145
3111
56
    GIM_Reject,
3112
56
    // Label 11: @7146
3113
56
    GIM_Try, /*On fail goto*//*Label 213*/ 7176, // Rule ID 431 //
3114
56
      GIM_CheckFeatures, GIFBS_isSICI,
3115
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3116
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3117
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3118
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3119
56
      // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3120
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_LSHR_B32_e64,
3121
56
      GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
3122
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3123
56
      // GIR_Coverage, 431,
3124
56
      GIR_Done,
3125
56
    // Label 213: @7176
3126
56
    GIM_Reject,
3127
56
    // Label 12: @7177
3128
56
    GIM_Try, /*On fail goto*//*Label 214*/ 7343,
3129
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3130
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3131
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3132
56
      GIM_Try, /*On fail goto*//*Label 215*/ 7298,
3133
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3134
56
        GIM_Try, /*On fail goto*//*Label 216*/ 7230, // Rule ID 1960 //
3135
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isSICI,
3136
56
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
3137
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vsrc0,
3138
56
          // (sra:{ *:[i32] } (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0), VGPR_32:{ *:[i32] }:$src1)  =>  (V_ASHR_I32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3139
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHR_I32_e32,
3140
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3141
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3142
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3143
56
          GIR_EraseFromParent, /*InsnID*/0,
3144
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3145
56
          // GIR_Coverage, 1960,
3146
56
          GIR_Done,
3147
56
        // Label 216: @7230
3148
56
        GIM_Try, /*On fail goto*//*Label 217*/ 7263, // Rule ID 1961 //
3149
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3150
56
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
3151
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
3152
56
          // (sra:{ *:[i32] } VGPR_32:{ *:[i32] }:$src1, (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_ASHRREV_I32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3153
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I32_e32,
3154
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3155
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3156
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3157
56
          GIR_EraseFromParent, /*InsnID*/0,
3158
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3159
56
          // GIR_Coverage, 1961,
3160
56
          GIR_Done,
3161
56
        // Label 217: @7263
3162
56
        GIM_Try, /*On fail goto*//*Label 218*/ 7297, // Rule ID 1962 //
3163
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3164
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vcsrc,
3165
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vcsrc,
3166
56
          // (sra:{ *:[i32] } (sd_vcsrc:{ *:[i32] } i32:{ *:[i32] }:$src0), (sd_vcsrc:{ *:[i32] } i32:{ *:[i32] }:$src1))  =>  (V_ASHRREV_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)
3167
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I32_e64,
3168
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3169
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3170
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3171
56
          GIR_EraseFromParent, /*InsnID*/0,
3172
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3173
56
          // GIR_Coverage, 1962,
3174
56
          GIR_Done,
3175
56
        // Label 218: @7297
3176
56
        GIM_Reject,
3177
56
      // Label 215: @7298
3178
56
      GIM_Try, /*On fail goto*//*Label 219*/ 7324, // Rule ID 1959 //
3179
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3180
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3181
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
3182
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
3183
56
        // (sra:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)  =>  (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3184
56
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ASHR_I32,
3185
56
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3186
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3187
56
        // GIR_Coverage, 1959,
3188
56
        GIR_Done,
3189
56
      // Label 219: @7324
3190
56
      GIM_Try, /*On fail goto*//*Label 220*/ 7342, // Rule ID 433 //
3191
56
        GIM_CheckFeatures, GIFBS_isSICI,
3192
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3193
56
        // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3194
56
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_ASHR_I32_e64,
3195
56
        GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
3196
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3197
56
        // GIR_Coverage, 433,
3198
56
        GIR_Done,
3199
56
      // Label 220: @7342
3200
56
      GIM_Reject,
3201
56
    // Label 214: @7343
3202
56
    GIM_Reject,
3203
56
    // Label 13: @7344
3204
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 224*/ 7693,
3205
56
    /*GILLT_s16*//*Label 221*/ 7353,
3206
56
    /*GILLT_s32*//*Label 222*/ 7465,
3207
56
    /*GILLT_s64*//*Label 223*/ 7581,
3208
56
    // Label 221: @7353
3209
56
    GIM_Try, /*On fail goto*//*Label 225*/ 7464,
3210
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3211
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3212
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3213
56
      GIM_Try, /*On fail goto*//*Label 226*/ 7415, // Rule ID 437 //
3214
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3215
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3216
56
        // (fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3217
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
3218
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3219
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3220
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3221
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3222
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3223
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3224
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3225
56
        GIR_EraseFromParent, /*InsnID*/0,
3226
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3227
56
        // GIR_Coverage, 437,
3228
56
        GIR_Done,
3229
56
      // Label 226: @7415
3230
56
      GIM_Try, /*On fail goto*//*Label 227*/ 7463, // Rule ID 1976 //
3231
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3232
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3233
56
        // (fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3234
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
3235
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3236
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3237
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3238
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3239
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3240
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3241
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3242
56
        GIR_EraseFromParent, /*InsnID*/0,
3243
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3244
56
        // GIR_Coverage, 1976,
3245
56
        GIR_Done,
3246
56
      // Label 227: @7463
3247
56
      GIM_Reject,
3248
56
    // Label 225: @7464
3249
56
    GIM_Reject,
3250
56
    // Label 222: @7465
3251
56
    GIM_Try, /*On fail goto*//*Label 228*/ 7580,
3252
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3253
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3254
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3255
56
      GIM_Try, /*On fail goto*//*Label 229*/ 7529, // Rule ID 388 //
3256
56
        GIM_CheckFeatures, GIFBS_isGCN,
3257
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3258
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3259
56
        // (fadd:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3260
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
3261
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3262
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3263
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3264
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3265
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3266
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3267
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3268
56
        GIR_EraseFromParent, /*InsnID*/0,
3269
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3270
56
        // GIR_Coverage, 388,
3271
56
        GIR_Done,
3272
56
      // Label 229: @7529
3273
56
      GIM_Try, /*On fail goto*//*Label 230*/ 7579, // Rule ID 1969 //
3274
56
        GIM_CheckFeatures, GIFBS_isGCN,
3275
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3276
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3277
56
        // (fadd:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3278
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
3279
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3280
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3281
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3282
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3283
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3284
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3285
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3286
56
        GIR_EraseFromParent, /*InsnID*/0,
3287
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3288
56
        // GIR_Coverage, 1969,
3289
56
        GIR_Done,
3290
56
      // Label 230: @7579
3291
56
      GIM_Reject,
3292
56
    // Label 228: @7580
3293
56
    GIM_Reject,
3294
56
    // Label 223: @7581
3295
56
    GIM_Try, /*On fail goto*//*Label 231*/ 7692,
3296
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3297
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3298
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3299
56
      GIM_Try, /*On fail goto*//*Label 232*/ 7643, // Rule ID 448 //
3300
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3301
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3302
56
        // (fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3303
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
3304
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3305
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3306
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3307
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3308
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3309
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3310
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3311
56
        GIR_EraseFromParent, /*InsnID*/0,
3312
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3313
56
        // GIR_Coverage, 448,
3314
56
        GIR_Done,
3315
56
      // Label 232: @7643
3316
56
      GIM_Try, /*On fail goto*//*Label 233*/ 7691, // Rule ID 1982 //
3317
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3318
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3319
56
        // (fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3320
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
3321
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3322
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3323
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3324
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3325
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3326
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3327
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3328
56
        GIR_EraseFromParent, /*InsnID*/0,
3329
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3330
56
        // GIR_Coverage, 1982,
3331
56
        GIR_Done,
3332
56
      // Label 233: @7691
3333
56
      GIM_Reject,
3334
56
    // Label 231: @7692
3335
56
    GIM_Reject,
3336
56
    // Label 224: @7693
3337
56
    GIM_Reject,
3338
56
    // Label 14: @7694
3339
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 236*/ 7826,
3340
56
    /*GILLT_s16*//*Label 234*/ 7702,
3341
56
    /*GILLT_s32*//*Label 235*/ 7763,
3342
56
    // Label 234: @7702
3343
56
    GIM_Try, /*On fail goto*//*Label 237*/ 7762, // Rule ID 438 //
3344
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3345
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3346
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3347
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3348
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3349
56
      // (fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3350
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F16_e64,
3351
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3352
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3353
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3354
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3355
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3356
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3357
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3358
56
      GIR_EraseFromParent, /*InsnID*/0,
3359
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3360
56
      // GIR_Coverage, 438,
3361
56
      GIR_Done,
3362
56
    // Label 237: @7762
3363
56
    GIM_Reject,
3364
56
    // Label 235: @7763
3365
56
    GIM_Try, /*On fail goto*//*Label 238*/ 7825, // Rule ID 389 //
3366
56
      GIM_CheckFeatures, GIFBS_isGCN,
3367
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3368
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3369
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3370
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3371
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3372
56
      // (fsub:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3373
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F32_e64,
3374
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3375
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3376
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3377
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3378
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3379
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3380
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3381
56
      GIR_EraseFromParent, /*InsnID*/0,
3382
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3383
56
      // GIR_Coverage, 389,
3384
56
      GIR_Done,
3385
56
    // Label 238: @7825
3386
56
    GIM_Reject,
3387
56
    // Label 236: @7826
3388
56
    GIM_Reject,
3389
56
    // Label 15: @7827
3390
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 242*/ 8176,
3391
56
    /*GILLT_s16*//*Label 239*/ 7836,
3392
56
    /*GILLT_s32*//*Label 240*/ 7948,
3393
56
    /*GILLT_s64*//*Label 241*/ 8064,
3394
56
    // Label 239: @7836
3395
56
    GIM_Try, /*On fail goto*//*Label 243*/ 7947,
3396
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3397
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3398
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3399
56
      GIM_Try, /*On fail goto*//*Label 244*/ 7898, // Rule ID 439 //
3400
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3401
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3402
56
        // (fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3403
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
3404
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3405
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3406
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3407
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3408
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3409
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3410
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3411
56
        GIR_EraseFromParent, /*InsnID*/0,
3412
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3413
56
        // GIR_Coverage, 439,
3414
56
        GIR_Done,
3415
56
      // Label 244: @7898
3416
56
      GIM_Try, /*On fail goto*//*Label 245*/ 7946, // Rule ID 1977 //
3417
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3418
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3419
56
        // (fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3420
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
3421
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3422
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3423
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3424
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3425
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3426
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3427
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3428
56
        GIR_EraseFromParent, /*InsnID*/0,
3429
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3430
56
        // GIR_Coverage, 1977,
3431
56
        GIR_Done,
3432
56
      // Label 245: @7946
3433
56
      GIM_Reject,
3434
56
    // Label 243: @7947
3435
56
    GIM_Reject,
3436
56
    // Label 240: @7948
3437
56
    GIM_Try, /*On fail goto*//*Label 246*/ 8063,
3438
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3439
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3440
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3441
56
      GIM_Try, /*On fail goto*//*Label 247*/ 8012, // Rule ID 391 //
3442
56
        GIM_CheckFeatures, GIFBS_isGCN,
3443
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3444
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3445
56
        // (fmul:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3446
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
3447
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3448
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3449
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3450
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3451
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3452
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3453
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3454
56
        GIR_EraseFromParent, /*InsnID*/0,
3455
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3456
56
        // GIR_Coverage, 391,
3457
56
        GIR_Done,
3458
56
      // Label 247: @8012
3459
56
      GIM_Try, /*On fail goto*//*Label 248*/ 8062, // Rule ID 1971 //
3460
56
        GIM_CheckFeatures, GIFBS_isGCN,
3461
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3462
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3463
56
        // (fmul:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3464
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
3465
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3466
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3467
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3468
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3469
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3470
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3471
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3472
56
        GIR_EraseFromParent, /*InsnID*/0,
3473
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3474
56
        // GIR_Coverage, 1971,
3475
56
        GIR_Done,
3476
56
      // Label 248: @8062
3477
56
      GIM_Reject,
3478
56
    // Label 246: @8063
3479
56
    GIM_Reject,
3480
56
    // Label 241: @8064
3481
56
    GIM_Try, /*On fail goto*//*Label 249*/ 8175,
3482
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3483
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3484
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3485
56
      GIM_Try, /*On fail goto*//*Label 250*/ 8126, // Rule ID 449 //
3486
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3487
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3488
56
        // (fmul:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3489
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
3490
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3491
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3492
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3493
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3494
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3495
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3496
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3497
56
        GIR_EraseFromParent, /*InsnID*/0,
3498
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3499
56
        // GIR_Coverage, 449,
3500
56
        GIR_Done,
3501
56
      // Label 250: @8126
3502
56
      GIM_Try, /*On fail goto*//*Label 251*/ 8174, // Rule ID 1983 //
3503
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3504
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3505
56
        // (fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3506
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
3507
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3508
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3509
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3510
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3511
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3512
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3513
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3514
56
        GIR_EraseFromParent, /*InsnID*/0,
3515
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3516
56
        // GIR_Coverage, 1983,
3517
56
        GIR_Done,
3518
56
      // Label 251: @8174
3519
56
      GIM_Reject,
3520
56
    // Label 249: @8175
3521
56
    GIM_Reject,
3522
56
    // Label 242: @8176
3523
56
    GIM_Reject,
3524
56
    // Label 16: @8177
3525
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 255*/ 8420,
3526
56
    /*GILLT_s16*//*Label 252*/ 8186,
3527
56
    /*GILLT_s32*//*Label 253*/ 8264,
3528
56
    /*GILLT_s64*//*Label 254*/ 8342,
3529
56
    // Label 252: @8186
3530
56
    GIM_Try, /*On fail goto*//*Label 256*/ 8263, // Rule ID 487 //
3531
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3532
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3533
56
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
3534
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3535
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3536
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3537
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3538
56
      // (fma:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F16:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3539
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F16,
3540
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3541
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3542
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3543
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3544
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3545
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3546
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3547
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3548
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3549
56
      GIR_EraseFromParent, /*InsnID*/0,
3550
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3551
56
      // GIR_Coverage, 487,
3552
56
      GIR_Done,
3553
56
    // Label 256: @8263
3554
56
    GIM_Reject,
3555
56
    // Label 253: @8264
3556
56
    GIM_Try, /*On fail goto*//*Label 257*/ 8341, // Rule ID 445 //
3557
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3558
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3559
56
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
3560
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3561
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3562
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3563
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3564
56
      // (fma:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3565
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F32,
3566
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3567
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3568
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3569
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3570
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3571
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3572
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3573
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3574
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3575
56
      GIR_EraseFromParent, /*InsnID*/0,
3576
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3577
56
      // GIR_Coverage, 445,
3578
56
      GIR_Done,
3579
56
    // Label 257: @8341
3580
56
    GIM_Reject,
3581
56
    // Label 254: @8342
3582
56
    GIM_Try, /*On fail goto*//*Label 258*/ 8419, // Rule ID 447 //
3583
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3584
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3585
56
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
3586
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3587
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3588
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3589
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3590
56
      // (fma:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3591
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F64,
3592
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3593
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3594
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3595
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3596
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3597
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3598
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3599
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3600
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3601
56
      GIR_EraseFromParent, /*InsnID*/0,
3602
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3603
56
      // GIR_Coverage, 447,
3604
56
      GIR_Done,
3605
56
    // Label 258: @8419
3606
56
    GIM_Reject,
3607
56
    // Label 255: @8420
3608
56
    GIM_Reject,
3609
56
    // Label 17: @8421
3610
56
    GIM_Try, /*On fail goto*//*Label 259*/ 8493, // Rule ID 1704 //
3611
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3612
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3613
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3614
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3615
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3616
56
      // (fpow:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)  =>  (V_EXP_F32_e32:{ *:[f32] } (V_MUL_LEGACY_F32_e32:{ *:[i16] } f32:{ *:[f32] }:$src1, (V_LOG_F32_e32:{ *:[i16] } f32:{ *:[f32] }:$src0)))
3617
56
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
3618
56
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
3619
56
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/AMDGPU::V_LOG_F32_e32,
3620
56
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3621
56
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src0
3622
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3623
56
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_MUL_LEGACY_F32_e32,
3624
56
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3625
56
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src1
3626
56
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3627
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3628
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e32,
3629
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3630
56
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3631
56
      GIR_EraseFromParent, /*InsnID*/0,
3632
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3633
56
      // GIR_Coverage, 1704,
3634
56
      GIR_Done,
3635
56
    // Label 259: @8493
3636
56
    GIM_Reject,
3637
56
    // Label 18: @8494
3638
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 262*/ 8590,
3639
56
    /*GILLT_s16*//*Label 260*/ 8502,
3640
56
    /*GILLT_s32*//*Label 261*/ 8546,
3641
56
    // Label 260: @8502
3642
56
    GIM_Try, /*On fail goto*//*Label 263*/ 8545, // Rule ID 378 //
3643
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3644
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3645
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3646
56
      // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3647
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F16_e64,
3648
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3649
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3650
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3651
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3652
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3653
56
      GIR_EraseFromParent, /*InsnID*/0,
3654
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3655
56
      // GIR_Coverage, 378,
3656
56
      GIR_Done,
3657
56
    // Label 263: @8545
3658
56
    GIM_Reject,
3659
56
    // Label 261: @8546
3660
56
    GIM_Try, /*On fail goto*//*Label 264*/ 8589, // Rule ID 345 //
3661
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3662
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3663
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3664
56
      // (fexp2:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3665
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e64,
3666
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3667
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3668
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3669
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3670
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3671
56
      GIR_EraseFromParent, /*InsnID*/0,
3672
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3673
56
      // GIR_Coverage, 345,
3674
56
      GIR_Done,
3675
56
    // Label 264: @8589
3676
56
    GIM_Reject,
3677
56
    // Label 262: @8590
3678
56
    GIM_Reject,
3679
56
    // Label 19: @8591
3680
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 267*/ 8687,
3681
56
    /*GILLT_s16*//*Label 265*/ 8599,
3682
56
    /*GILLT_s32*//*Label 266*/ 8643,
3683
56
    // Label 265: @8599
3684
56
    GIM_Try, /*On fail goto*//*Label 268*/ 8642, // Rule ID 377 //
3685
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3686
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3687
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3688
56
      // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3689
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F16_e64,
3690
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3691
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3692
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3693
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3694
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3695
56
      GIR_EraseFromParent, /*InsnID*/0,
3696
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3697
56
      // GIR_Coverage, 377,
3698
56
      GIR_Done,
3699
56
    // Label 268: @8642
3700
56
    GIM_Reject,
3701
56
    // Label 266: @8643
3702
56
    GIM_Try, /*On fail goto*//*Label 269*/ 8686, // Rule ID 346 //
3703
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3704
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3705
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3706
56
      // (flog2:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3707
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F32_e64,
3708
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3709
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3710
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3711
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3712
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3713
56
      GIR_EraseFromParent, /*InsnID*/0,
3714
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3715
56
      // GIR_Coverage, 346,
3716
56
      GIR_Done,
3717
56
    // Label 269: @8686
3718
56
    GIM_Reject,
3719
56
    // Label 267: @8687
3720
56
    GIM_Reject,
3721
56
    // Label 20: @8688
3722
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 272*/ 8784,
3723
56
    /*GILLT_s32*//*Label 270*/ 8696,
3724
56
    /*GILLT_s64*//*Label 271*/ 8740,
3725
56
    // Label 270: @8696
3726
56
    GIM_Try, /*On fail goto*//*Label 273*/ 8739, // Rule ID 329 //
3727
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3728
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3729
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3730
56
      // (fpextend:{ *:[f32] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3731
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F16_e64,
3732
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3733
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3734
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3735
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3736
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3737
56
      GIR_EraseFromParent, /*InsnID*/0,
3738
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3739
56
      // GIR_Coverage, 329,
3740
56
      GIR_Done,
3741
56
    // Label 273: @8739
3742
56
    GIM_Reject,
3743
56
    // Label 271: @8740
3744
56
    GIM_Try, /*On fail goto*//*Label 274*/ 8783, // Rule ID 333 //
3745
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3746
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3747
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3748
56
      // (fpextend:{ *:[f64] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_F32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3749
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_F32_e64,
3750
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3751
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3752
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3753
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3754
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3755
56
      GIR_EraseFromParent, /*InsnID*/0,
3756
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3757
56
      // GIR_Coverage, 333,
3758
56
      GIR_Done,
3759
56
    // Label 274: @8783
3760
56
    GIM_Reject,
3761
56
    // Label 272: @8784
3762
56
    GIM_Reject,
3763
56
    // Label 21: @8785
3764
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 277*/ 8881,
3765
56
    /*GILLT_s16*//*Label 275*/ 8793,
3766
56
    /*GILLT_s32*//*Label 276*/ 8837,
3767
56
    // Label 275: @8793
3768
56
    GIM_Try, /*On fail goto*//*Label 278*/ 8836, // Rule ID 328 //
3769
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3770
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3771
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3772
56
      // (fpround:{ *:[f16] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_F32_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3773
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_F32_e64,
3774
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3775
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3776
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3777
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3778
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3779
56
      GIR_EraseFromParent, /*InsnID*/0,
3780
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3781
56
      // GIR_Coverage, 328,
3782
56
      GIR_Done,
3783
56
    // Label 278: @8836
3784
56
    GIM_Reject,
3785
56
    // Label 276: @8837
3786
56
    GIM_Try, /*On fail goto*//*Label 279*/ 8880, // Rule ID 332 //
3787
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3788
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3789
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3790
56
      // (fpround:{ *:[f32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F64_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3791
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F64_e64,
3792
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3793
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3794
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3795
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3796
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3797
56
      GIR_EraseFromParent, /*InsnID*/0,
3798
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3799
56
      // GIR_Coverage, 332,
3800
56
      GIR_Done,
3801
56
    // Label 279: @8880
3802
56
    GIM_Reject,
3803
56
    // Label 277: @8881
3804
56
    GIM_Reject,
3805
56
    // Label 22: @8882
3806
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 283*/ 9115,
3807
56
    /*GILLT_s1*//*Label 280*/ 8891,
3808
56
    /*GILLT_s16*//*Label 281*/ 8984,
3809
56
    /*GILLT_s32*//*Label 282*/ 9028,
3810
56
    // Label 280: @8891
3811
56
    GIM_Try, /*On fail goto*//*Label 284*/ 8937, // Rule ID 1746 //
3812
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3813
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3814
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3815
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3816
56
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 3212836864:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
3817
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
3818
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3819
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3820
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/3212836864,
3821
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3822
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3823
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3824
56
      GIR_EraseFromParent, /*InsnID*/0,
3825
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3826
56
      // GIR_Coverage, 1746,
3827
56
      GIR_Done,
3828
56
    // Label 284: @8937
3829
56
    GIM_Try, /*On fail goto*//*Label 285*/ 8983, // Rule ID 1748 //
3830
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3831
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3832
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3833
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3834
56
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, -4616189618054758400:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
3835
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
3836
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3837
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3838
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/-4616189618054758400,
3839
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3840
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3841
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3842
56
      GIR_EraseFromParent, /*InsnID*/0,
3843
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3844
56
      // GIR_Coverage, 1748,
3845
56
      GIR_Done,
3846
56
    // Label 285: @8983
3847
56
    GIM_Reject,
3848
56
    // Label 281: @8984
3849
56
    GIM_Try, /*On fail goto*//*Label 286*/ 9027, // Rule ID 373 //
3850
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3851
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3852
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3853
56
      // (fp_to_sint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3854
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I16_F16_e64,
3855
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3856
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3857
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3858
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3859
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3860
56
      GIR_EraseFromParent, /*InsnID*/0,
3861
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3862
56
      // GIR_Coverage, 373,
3863
56
      GIR_Done,
3864
56
    // Label 286: @9027
3865
56
    GIM_Reject,
3866
56
    // Label 282: @9028
3867
56
    GIM_Try, /*On fail goto*//*Label 287*/ 9071, // Rule ID 322 //
3868
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3869
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3870
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3871
56
      // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3872
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F64_e64,
3873
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3874
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3875
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3876
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3877
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3878
56
      GIR_EraseFromParent, /*InsnID*/0,
3879
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3880
56
      // GIR_Coverage, 322,
3881
56
      GIR_Done,
3882
56
    // Label 287: @9071
3883
56
    GIM_Try, /*On fail goto*//*Label 288*/ 9114, // Rule ID 327 //
3884
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3885
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3886
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3887
56
      // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3888
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F32_e64,
3889
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3890
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3891
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3892
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3893
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3894
56
      GIR_EraseFromParent, /*InsnID*/0,
3895
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3896
56
      // GIR_Coverage, 327,
3897
56
      GIR_Done,
3898
56
    // Label 288: @9114
3899
56
    GIM_Reject,
3900
56
    // Label 283: @9115
3901
56
    GIM_Reject,
3902
56
    // Label 23: @9116
3903
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 292*/ 9349,
3904
56
    /*GILLT_s1*//*Label 289*/ 9125,
3905
56
    /*GILLT_s16*//*Label 290*/ 9218,
3906
56
    /*GILLT_s32*//*Label 291*/ 9262,
3907
56
    // Label 289: @9125
3908
56
    GIM_Try, /*On fail goto*//*Label 293*/ 9171, // Rule ID 1745 //
3909
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3910
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3911
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3912
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3913
56
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 1065353216:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
3914
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
3915
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3916
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3917
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/1065353216,
3918
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3919
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3920
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3921
56
      GIR_EraseFromParent, /*InsnID*/0,
3922
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3923
56
      // GIR_Coverage, 1745,
3924
56
      GIR_Done,
3925
56
    // Label 293: @9171
3926
56
    GIM_Try, /*On fail goto*//*Label 294*/ 9217, // Rule ID 1747 //
3927
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
3928
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3929
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3930
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3931
56
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, 4607182418800017408:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
3932
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
3933
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3934
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3935
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/4607182418800017408,
3936
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3937
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3938
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3939
56
      GIR_EraseFromParent, /*InsnID*/0,
3940
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3941
56
      // GIR_Coverage, 1747,
3942
56
      GIR_Done,
3943
56
    // Label 294: @9217
3944
56
    GIM_Reject,
3945
56
    // Label 290: @9218
3946
56
    GIM_Try, /*On fail goto*//*Label 295*/ 9261, // Rule ID 372 //
3947
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3948
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3949
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3950
56
      // (fp_to_uint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3951
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U16_F16_e64,
3952
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3953
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3954
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3955
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3956
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3957
56
      GIR_EraseFromParent, /*InsnID*/0,
3958
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3959
56
      // GIR_Coverage, 372,
3960
56
      GIR_Done,
3961
56
    // Label 295: @9261
3962
56
    GIM_Reject,
3963
56
    // Label 291: @9262
3964
56
    GIM_Try, /*On fail goto*//*Label 296*/ 9305, // Rule ID 326 //
3965
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3966
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3967
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3968
56
      // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3969
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F32_e64,
3970
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3971
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3972
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3973
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3974
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3975
56
      GIR_EraseFromParent, /*InsnID*/0,
3976
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3977
56
      // GIR_Coverage, 326,
3978
56
      GIR_Done,
3979
56
    // Label 296: @9305
3980
56
    GIM_Try, /*On fail goto*//*Label 297*/ 9348, // Rule ID 338 //
3981
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3982
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3983
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3984
56
      // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3985
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F64_e64,
3986
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3987
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3988
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3989
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3990
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3991
56
      GIR_EraseFromParent, /*InsnID*/0,
3992
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3993
56
      // GIR_Coverage, 338,
3994
56
      GIR_Done,
3995
56
    // Label 297: @9348
3996
56
    GIM_Reject,
3997
56
    // Label 292: @9349
3998
56
    GIM_Reject,
3999
56
    // Label 24: @9350
4000
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 301*/ 9479,
4001
56
    /*GILLT_s16*//*Label 298*/ 9359,
4002
56
    /*GILLT_s32*//*Label 299*/ 9399,
4003
56
    /*GILLT_s64*//*Label 300*/ 9439,
4004
56
    // Label 298: @9359
4005
56
    GIM_Try, /*On fail goto*//*Label 302*/ 9398, // Rule ID 371 //
4006
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4007
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4008
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4009
56
      // (sint_to_fp:{ *:[f16] } (VOP3OMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_I16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4010
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_I16_e64,
4011
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4012
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4013
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4014
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4015
56
      GIR_EraseFromParent, /*InsnID*/0,
4016
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4017
56
      // GIR_Coverage, 371,
4018
56
      GIR_Done,
4019
56
    // Label 302: @9398
4020
56
    GIM_Reject,
4021
56
    // Label 299: @9399
4022
56
    GIM_Try, /*On fail goto*//*Label 303*/ 9438, // Rule ID 324 //
4023
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4024
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4025
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4026
56
      // (sint_to_fp:{ *:[f32] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_I32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4027
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_I32_e64,
4028
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4029
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4030
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4031
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4032
56
      GIR_EraseFromParent, /*InsnID*/0,
4033
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4034
56
      // GIR_Coverage, 324,
4035
56
      GIR_Done,
4036
56
    // Label 303: @9438
4037
56
    GIM_Reject,
4038
56
    // Label 300: @9439
4039
56
    GIM_Try, /*On fail goto*//*Label 304*/ 9478, // Rule ID 323 //
4040
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4041
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4042
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4043
56
      // (sint_to_fp:{ *:[f64] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_I32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4044
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_I32_e64,
4045
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4046
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4047
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4048
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4049
56
      GIR_EraseFromParent, /*InsnID*/0,
4050
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4051
56
      // GIR_Coverage, 323,
4052
56
      GIR_Done,
4053
56
    // Label 304: @9478
4054
56
    GIM_Reject,
4055
56
    // Label 301: @9479
4056
56
    GIM_Reject,
4057
56
    // Label 25: @9480
4058
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 308*/ 9609,
4059
56
    /*GILLT_s16*//*Label 305*/ 9489,
4060
56
    /*GILLT_s32*//*Label 306*/ 9529,
4061
56
    /*GILLT_s64*//*Label 307*/ 9569,
4062
56
    // Label 305: @9489
4063
56
    GIM_Try, /*On fail goto*//*Label 309*/ 9528, // Rule ID 370 //
4064
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4065
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4066
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4067
56
      // (uint_to_fp:{ *:[f16] } (VOP3OMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_U16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4068
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_U16_e64,
4069
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4070
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4071
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4072
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4073
56
      GIR_EraseFromParent, /*InsnID*/0,
4074
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4075
56
      // GIR_Coverage, 370,
4076
56
      GIR_Done,
4077
56
    // Label 309: @9528
4078
56
    GIM_Reject,
4079
56
    // Label 306: @9529
4080
56
    GIM_Try, /*On fail goto*//*Label 310*/ 9568, // Rule ID 325 //
4081
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4082
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4083
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4084
56
      // (uint_to_fp:{ *:[f32] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_U32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4085
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_U32_e64,
4086
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4087
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4088
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4089
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4090
56
      GIR_EraseFromParent, /*InsnID*/0,
4091
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4092
56
      // GIR_Coverage, 325,
4093
56
      GIR_Done,
4094
56
    // Label 310: @9568
4095
56
    GIM_Reject,
4096
56
    // Label 307: @9569
4097
56
    GIM_Try, /*On fail goto*//*Label 311*/ 9608, // Rule ID 339 //
4098
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4099
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4100
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4101
56
      // (uint_to_fp:{ *:[f64] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_U32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4102
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_U32_e64,
4103
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4104
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4105
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4106
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4107
56
      GIR_EraseFromParent, /*InsnID*/0,
4108
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4109
56
      // GIR_Coverage, 339,
4110
56
      GIR_Done,
4111
56
    // Label 311: @9608
4112
56
    GIM_Reject,
4113
56
    // Label 308: @9609
4114
56
    GIM_Reject,
4115
56
    // Label 26: @9610
4116
56
    GIM_Try, /*On fail goto*//*Label 312*/ 9624, // Rule ID 52 //
4117
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
4118
56
      // MIs[0] simm16
4119
56
      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
4120
56
      // (br (bb:{ *:[Other] }):$simm16)  =>  (S_BRANCH (bb:{ *:[Other] }):$simm16)
4121
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_BRANCH,
4122
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4123
56
      // GIR_Coverage, 52,
4124
56
      GIR_Done,
4125
56
    // Label 312: @9624
4126
56
    GIM_Reject,
4127
56
    // Label 27: @9625
4128
56
    GIM_Try, /*On fail goto*//*Label 313*/ 9651, // Rule ID 4 //
4129
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
4130
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4131
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4132
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
4133
56
      // (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0)  =>  (S_BCNT1_I32_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
4134
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_BCNT1_I32_B32,
4135
56
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
4136
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4137
56
      // GIR_Coverage, 4,
4138
56
      GIR_Done,
4139
56
    // Label 313: @9651
4140
56
    GIM_Reject,
4141
56
    // Label 28: @9652
4142
56
    GIM_Reject,
4143
56
    };
4144
56
  return MatchTable0;
4145
56
}
4146
#endif // ifdef GET_GLOBALISEL_IMPL
4147
#ifdef GET_GLOBALISEL_PREDICATES_DECL
4148
PredicateBitset AvailableModuleFeatures;
4149
mutable PredicateBitset AvailableFunctionFeatures;
4150
56
PredicateBitset getAvailableFeatures() const {
4151
56
  return AvailableModuleFeatures | AvailableFunctionFeatures;
4152
56
}
4153
PredicateBitset
4154
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const;
4155
PredicateBitset
4156
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget,
4157
                                 const MachineFunction *MF) const;
4158
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
4159
#ifdef GET_GLOBALISEL_PREDICATES_INIT
4160
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
4161
AvailableFunctionFeatures()
4162
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT