Coverage Report

Created: 2019-02-15 18:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the AMDGPU target                          *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 33;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(AMDGPUInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(AMDGPUInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static AMDGPUInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static AMDGPUInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(3),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_isSICIBit = 2,
37
  Feature_isVIBit = 1,
38
  Feature_isGFX9Bit = 5,
39
  Feature_isCIVIBit = 6,
40
  Feature_HasFlatAddressSpaceBit = 7,
41
  Feature_HasFlatGlobalInstsBit = 8,
42
  Feature_HasUnpackedD16VMemBit = 20,
43
  Feature_HasPackedD16VMemBit = 21,
44
  Feature_D16PreservesUnusedBitsBit = 19,
45
  Feature_LDSRequiresM0InitBit = 31,
46
  Feature_NotLDSRequiresM0InitBit = 32,
47
  Feature_HasAddNoCarryInstsBit = 13,
48
  Feature_Has16BitInstsBit = 3,
49
  Feature_HasVOP3PInstsBit = 23,
50
  Feature_HasMadMixInstsBit = 14,
51
  Feature_has16BankLDSBit = 11,
52
  Feature_has32BankLDSBit = 10,
53
  Feature_HasFmaMixInstsBit = 15,
54
  Feature_HasDLInstsBit = 30,
55
  Feature_HasDot1InstsBit = 17,
56
  Feature_HasDot2InstsBit = 16,
57
  Feature_EnableLateCFGStructurizeBit = 12,
58
  Feature_TruePredicateBit = 0,
59
  Feature_FP16DenormalsBit = 25,
60
  Feature_FP32DenormalsBit = 27,
61
  Feature_FP64DenormalsBit = 29,
62
  Feature_NoFP16DenormalsBit = 24,
63
  Feature_NoFP32DenormalsBit = 26,
64
  Feature_NoFP64DenormalsBit = 28,
65
  Feature_UnsafeFPMathBit = 22,
66
  Feature_isCIOnlyBit = 18,
67
  Feature_isVIOnlyBit = 4,
68
  Feature_isSIBit = 9,
69
};
70
71
PredicateBitset AMDGPUInstructionSelector::
72
2.90k
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const {
73
2.90k
  PredicateBitset Features;
74
2.90k
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||
Subtarget->getGeneration() == 1.78k
AMDGPUSubtarget1.78k
::SEA_ISLANDS)
75
1.38k
    Features[Feature_isSICIBit] = 1;
76
2.90k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
77
1.52k
    Features[Feature_isVIBit] = 1;
78
2.90k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9)
79
420
    Features[Feature_isGFX9Bit] = 1;
80
2.90k
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
81
1.78k
    Features[Feature_isCIVIBit] = 1;
82
2.90k
  if (Subtarget->hasFlatAddressSpace())
83
1.97k
    Features[Feature_HasFlatAddressSpaceBit] = 1;
84
2.90k
  if (Subtarget->hasFlatGlobalInsts())
85
420
    Features[Feature_HasFlatGlobalInstsBit] = 1;
86
2.90k
  if (Subtarget->hasUnpackedD16VMem())
87
1.07k
    Features[Feature_HasUnpackedD16VMemBit] = 1;
88
2.90k
  if (!Subtarget->hasUnpackedD16VMem())
89
1.83k
    Features[Feature_HasPackedD16VMemBit] = 1;
90
2.90k
  if (Subtarget->hasD16LoadStore() && 
!Subtarget->isSRAMECCEnabled()420
)
91
385
    Features[Feature_D16PreservesUnusedBitsBit] = 1;
92
2.90k
  if (Subtarget->ldsRequiresM0Init())
93
2.48k
    Features[Feature_LDSRequiresM0InitBit] = 1;
94
2.90k
  if (!Subtarget->ldsRequiresM0Init())
95
420
    Features[Feature_NotLDSRequiresM0InitBit] = 1;
96
2.90k
  if (Subtarget->hasAddNoCarry())
97
420
    Features[Feature_HasAddNoCarryInstsBit] = 1;
98
2.90k
  if (Subtarget->has16BitInsts())
99
1.52k
    Features[Feature_Has16BitInstsBit] = 1;
100
2.90k
  if (Subtarget->hasVOP3PInsts())
101
420
    Features[Feature_HasVOP3PInstsBit] = 1;
102
2.90k
  if (Subtarget->hasMadMixInsts())
103
381
    Features[Feature_HasMadMixInstsBit] = 1;
104
2.90k
  if (Subtarget->getLDSBankCount() == 16)
105
34
    Features[Feature_has16BankLDSBit] = 1;
106
2.90k
  if (Subtarget->getLDSBankCount() == 32)
107
2.87k
    Features[Feature_has32BankLDSBit] = 1;
108
2.90k
  if (Subtarget->hasFmaMixInsts())
109
39
    Features[Feature_HasFmaMixInstsBit] = 1;
110
2.90k
  if (Subtarget->hasDLInsts())
111
34
    Features[Feature_HasDLInstsBit] = 1;
112
2.90k
  if (Subtarget->hasDot1Insts())
113
34
    Features[Feature_HasDot1InstsBit] = 1;
114
2.90k
  if (Subtarget->hasDot2Insts())
115
34
    Features[Feature_HasDot2InstsBit] = 1;
116
2.90k
  if (EnableLateStructurizeCFG)
117
0
    Features[Feature_EnableLateCFGStructurizeBit] = 1;
118
2.90k
  if (true)
119
2.90k
    Features[Feature_TruePredicateBit] = 1;
120
2.90k
  if (Subtarget->hasFP16Denormals())
121
2.86k
    Features[Feature_FP16DenormalsBit] = 1;
122
2.90k
  if (Subtarget->hasFP32Denormals())
123
62
    Features[Feature_FP32DenormalsBit] = 1;
124
2.90k
  if (Subtarget->hasFP64Denormals())
125
2.86k
    Features[Feature_FP64DenormalsBit] = 1;
126
2.90k
  if (!Subtarget->hasFP16Denormals())
127
40
    Features[Feature_NoFP16DenormalsBit] = 1;
128
2.90k
  if (!Subtarget->hasFP32Denormals())
129
2.84k
    Features[Feature_NoFP32DenormalsBit] = 1;
130
2.90k
  if (!Subtarget->hasFP64Denormals())
131
40
    Features[Feature_NoFP64DenormalsBit] = 1;
132
2.90k
  if (TM.Options.UnsafeFPMath)
133
36
    Features[Feature_UnsafeFPMathBit] = 1;
134
2.90k
  if (Subtarget->getGeneration() ==AMDGPUSubtarget::SEA_ISLANDS)
135
265
    Features[Feature_isCIOnlyBit] = 1;
136
2.90k
  if (Subtarget->getGeneration() ==AMDGPUSubtarget::VOLCANIC_ISLANDS)
137
1.10k
    Features[Feature_isVIOnlyBit] = 1;
138
2.90k
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
139
1.12k
    Features[Feature_isSIBit] = 1;
140
2.90k
  return Features;
141
2.90k
}
142
143
PredicateBitset AMDGPUInstructionSelector::
144
56
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget, const MachineFunction *MF) const {
145
56
  PredicateBitset Features;
146
56
  return Features;
147
56
}
148
149
// LLT Objects.
150
enum {
151
  GILLT_s1,
152
  GILLT_s16,
153
  GILLT_s32,
154
  GILLT_s64,
155
  GILLT_v2s16,
156
  GILLT_v2s32,
157
  GILLT_v2s64,
158
  GILLT_v4s16,
159
  GILLT_v4s32,
160
  GILLT_v8s32,
161
  GILLT_v16s32,
162
};
163
const static size_t NumTypeObjects = 11;
164
const static LLT TypeObjects[] = {
165
  LLT::scalar(1),
166
  LLT::scalar(16),
167
  LLT::scalar(32),
168
  LLT::scalar(64),
169
  LLT::vector(2, 16),
170
  LLT::vector(2, 32),
171
  LLT::vector(2, 64),
172
  LLT::vector(4, 16),
173
  LLT::vector(4, 32),
174
  LLT::vector(8, 32),
175
  LLT::vector(16, 32),
176
};
177
178
// Feature bitsets.
179
enum {
180
  GIFBS_Invalid,
181
  GIFBS_Has16BitInsts,
182
  GIFBS_isSICI,
183
  GIFBS_Has16BitInsts_isVIOnly,
184
  GIFBS_TruePredicate_TruePredicate,
185
  GIFBS_TruePredicate_isCIVI,
186
  GIFBS_TruePredicate_isSI,
187
  GIFBS_TruePredicate_isSICI,
188
  GIFBS_TruePredicate_isVI,
189
};
190
const static PredicateBitset FeatureBitsets[] {
191
  {}, // GIFBS_Invalid
192
  {Feature_Has16BitInstsBit, },
193
  {Feature_isSICIBit, },
194
  {Feature_Has16BitInstsBit, Feature_isVIOnlyBit, },
195
  {Feature_TruePredicateBit, Feature_TruePredicateBit, },
196
  {Feature_TruePredicateBit, Feature_isCIVIBit, },
197
  {Feature_TruePredicateBit, Feature_isSIBit, },
198
  {Feature_TruePredicateBit, Feature_isSICIBit, },
199
  {Feature_TruePredicateBit, Feature_isVIBit, },
200
};
201
202
// ComplexPattern predicates.
203
enum {
204
  GICP_Invalid,
205
  GICP_gi_vcsrc,
206
  GICP_gi_vop3mods,
207
  GICP_gi_vop3mods0,
208
  GICP_gi_vop3omods,
209
  GICP_gi_vsrc0,
210
};
211
// See constructor for table contents
212
213
// PatFrag predicates.
214
enum {
215
  GIPFP_I64_Predicate_NegSubInlineConst16 = GIPFP_I64_Invalid + 1,
216
  GIPFP_I64_Predicate_NegSubInlineConst32,
217
};
218
0
bool AMDGPUInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
219
0
  switch (PredicateID) {
220
0
  case GIPFP_I64_Predicate_NegSubInlineConst16: {
221
0
    
222
0
  return Imm < -16 && Imm >= -64;
223
0
224
0
    llvm_unreachable("ImmediateCode should have returned");
225
0
    return false;
226
0
  }
227
0
  case GIPFP_I64_Predicate_NegSubInlineConst32: {
228
0
    
229
0
  return Imm < -16 && Imm >= -64;
230
0
231
0
    llvm_unreachable("ImmediateCode should have returned");
232
0
    return false;
233
0
  }
234
0
  }
235
0
  llvm_unreachable("Unknown predicate");
236
0
  return false;
237
0
}
238
0
bool AMDGPUInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
239
0
  llvm_unreachable("Unknown predicate");
240
0
  return false;
241
0
}
242
0
bool AMDGPUInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
243
0
  llvm_unreachable("Unknown predicate");
244
0
  return false;
245
0
}
246
0
bool AMDGPUInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
247
0
  const MachineFunction &MF = *MI.getParent()->getParent();
248
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
249
0
  (void)MRI;
250
0
  llvm_unreachable("Unknown predicate");
251
0
  return false;
252
0
}
253
254
AMDGPUInstructionSelector::ComplexMatcherMemFn
255
AMDGPUInstructionSelector::ComplexPredicateFns[] = {
256
  nullptr, // GICP_Invalid
257
  &AMDGPUInstructionSelector::selectVCSRC, // gi_vcsrc
258
  &AMDGPUInstructionSelector::selectVOP3Mods, // gi_vop3mods
259
  &AMDGPUInstructionSelector::selectVOP3Mods0, // gi_vop3mods0
260
  &AMDGPUInstructionSelector::selectVOP3OMods, // gi_vop3omods
261
  &AMDGPUInstructionSelector::selectVSRC0, // gi_vsrc0
262
};
263
264
// Custom renderers.
265
enum {
266
  GICR_Invalid,
267
};
268
AMDGPUInstructionSelector::CustomRendererFn
269
AMDGPUInstructionSelector::CustomRenderers[] = {
270
  nullptr, // GICP_Invalid
271
};
272
273
56
bool AMDGPUInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
274
56
  MachineFunction &MF = *I.getParent()->getParent();
275
56
  MachineRegisterInfo &MRI = MF.getRegInfo();
276
56
  // FIXME: This should be computed on a per-function basis rather than per-insn.
277
56
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
278
56
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
279
56
  NewMIVector OutMIs;
280
56
  State.MIs.clear();
281
56
  State.MIs.push_back(&I);
282
56
283
56
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
284
56
    return true;
285
56
  }
286
0
287
0
  return false;
288
0
}
289
290
56
const int64_t *AMDGPUInstructionSelector::getMatchTable() const {
291
56
  constexpr static int64_t MatchTable0[] = {
292
56
    GIM_SwitchOpcode, /*MI*/0, /*[*/35, 146, /*)*//*default:*//*Label 31*/ 10299,
293
56
    /*TargetOpcode::G_ADD*//*Label 0*/ 116,
294
56
    /*TargetOpcode::G_SUB*//*Label 1*/ 313,
295
56
    /*TargetOpcode::G_MUL*//*Label 2*/ 344, 0, 0, 0, 0,
296
56
    /*TargetOpcode::G_AND*//*Label 3*/ 372,
297
56
    /*TargetOpcode::G_OR*//*Label 4*/ 401,
298
56
    /*TargetOpcode::G_XOR*//*Label 5*/ 2148, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
299
56
    /*TargetOpcode::G_BITCAST*//*Label 6*/ 2250, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
300
56
    /*TargetOpcode::G_INTRINSIC*//*Label 7*/ 4460,
301
56
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 8*/ 6824, 0, 0,
302
56
    /*TargetOpcode::G_CONSTANT*//*Label 9*/ 7123, 0, 0, 0, 0, 0,
303
56
    /*TargetOpcode::G_SHL*//*Label 10*/ 7180,
304
56
    /*TargetOpcode::G_LSHR*//*Label 11*/ 7211,
305
56
    /*TargetOpcode::G_ASHR*//*Label 12*/ 7242, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
306
56
    /*TargetOpcode::G_FADD*//*Label 13*/ 7409,
307
56
    /*TargetOpcode::G_FSUB*//*Label 14*/ 7755,
308
56
    /*TargetOpcode::G_FMUL*//*Label 15*/ 7886,
309
56
    /*TargetOpcode::G_FMA*//*Label 16*/ 8232, 0, 0,
310
56
    /*TargetOpcode::G_FPOW*//*Label 17*/ 8478, 0,
311
56
    /*TargetOpcode::G_FEXP2*//*Label 18*/ 8551, 0,
312
56
    /*TargetOpcode::G_FLOG2*//*Label 19*/ 8648, 0, 0,
313
56
    /*TargetOpcode::G_FPEXT*//*Label 20*/ 8745,
314
56
    /*TargetOpcode::G_FPTRUNC*//*Label 21*/ 8842,
315
56
    /*TargetOpcode::G_FPTOSI*//*Label 22*/ 8939,
316
56
    /*TargetOpcode::G_FPTOUI*//*Label 23*/ 9173,
317
56
    /*TargetOpcode::G_SITOFP*//*Label 24*/ 9407,
318
56
    /*TargetOpcode::G_UITOFP*//*Label 25*/ 9537, 0, 0, 0, 0,
319
56
    /*TargetOpcode::G_BR*//*Label 26*/ 9667, 0, 0, 0, 0, 0, 0, 0,
320
56
    /*TargetOpcode::G_CTPOP*//*Label 27*/ 9682, 0,
321
56
    /*TargetOpcode::G_FCEIL*//*Label 28*/ 9709, 0, 0,
322
56
    /*TargetOpcode::G_FSQRT*//*Label 29*/ 9851,
323
56
    /*TargetOpcode::G_FFLOOR*//*Label 30*/ 9993,
324
56
    // Label 0: @116
325
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 34*/ 312,
326
56
    /*GILLT_s16*//*Label 32*/ 125, 0,
327
56
    /*GILLT_s64*//*Label 33*/ 285,
328
56
    // Label 32: @125
329
56
    GIM_Try, /*On fail goto*//*Label 35*/ 284,
330
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
331
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
332
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
333
56
      GIM_Try, /*On fail goto*//*Label 36*/ 187, // Rule ID 978 //
334
56
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
335
56
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
336
56
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
337
56
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
338
56
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
339
56
        GIM_CheckIsSafeToFold, /*InsnID*/1,
340
56
        // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
341
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
342
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
343
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
344
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
345
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
346
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
347
56
        GIR_EraseFromParent, /*InsnID*/0,
348
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
349
56
        // GIR_Coverage, 978,
350
56
        GIR_Done,
351
56
      // Label 36: @187
352
56
      GIM_Try, /*On fail goto*//*Label 37*/ 235, // Rule ID 979 //
353
56
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
354
56
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
355
56
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
356
56
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
357
56
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
358
56
        GIM_CheckIsSafeToFold, /*InsnID*/1,
359
56
        // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_I16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
360
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_I16,
361
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
362
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
363
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
364
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
365
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
366
56
        GIR_EraseFromParent, /*InsnID*/0,
367
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
368
56
        // GIR_Coverage, 979,
369
56
        GIR_Done,
370
56
      // Label 37: @235
371
56
      GIM_Try, /*On fail goto*//*Label 38*/ 283, // Rule ID 2124 //
372
56
        GIM_CheckFeatures, GIFBS_Has16BitInsts,
373
56
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
374
56
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
375
56
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
376
56
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
377
56
        GIM_CheckIsSafeToFold, /*InsnID*/1,
378
56
        // (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
379
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
380
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
381
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
382
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
383
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
384
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
385
56
        GIR_EraseFromParent, /*InsnID*/0,
386
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
387
56
        // GIR_Coverage, 2124,
388
56
        GIR_Done,
389
56
      // Label 38: @283
390
56
      GIM_Reject,
391
56
    // Label 35: @284
392
56
    GIM_Reject,
393
56
    // Label 33: @285
394
56
    GIM_Try, /*On fail goto*//*Label 39*/ 311, // Rule ID 673 //
395
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
396
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
397
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
398
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
399
56
      // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_ADD_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
400
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ADD_U64_PSEUDO,
401
56
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
402
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
403
56
      // GIR_Coverage, 673,
404
56
      GIR_Done,
405
56
    // Label 39: @311
406
56
    GIM_Reject,
407
56
    // Label 34: @312
408
56
    GIM_Reject,
409
56
    // Label 1: @313
410
56
    GIM_Try, /*On fail goto*//*Label 40*/ 343, // Rule ID 674 //
411
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
412
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
413
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
414
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
415
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
416
56
      // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_SUB_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
417
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_SUB_U64_PSEUDO,
418
56
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
419
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
420
56
      // GIR_Coverage, 674,
421
56
      GIR_Done,
422
56
    // Label 40: @343
423
56
    GIM_Reject,
424
56
    // Label 2: @344
425
56
    GIM_Try, /*On fail goto*//*Label 41*/ 371, // Rule ID 43 //
426
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
427
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
428
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
429
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
430
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
431
56
      // (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_MUL_I32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
432
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_MUL_I32,
433
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
434
56
      // GIR_Coverage, 43,
435
56
      GIR_Done,
436
56
    // Label 41: @371
437
56
    GIM_Reject,
438
56
    // Label 3: @372
439
56
    GIM_Try, /*On fail goto*//*Label 42*/ 400, // Rule ID 421 //
440
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
441
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
442
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
443
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
444
56
      // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_AND_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
445
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_AND_B32_e64,
446
56
      GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
447
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
448
56
      // GIR_Coverage, 421,
449
56
      GIR_Done,
450
56
    // Label 42: @400
451
56
    GIM_Reject,
452
56
    // Label 4: @401
453
56
    GIM_Try, /*On fail goto*//*Label 43*/ 2147,
454
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
455
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
456
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
457
56
      GIM_Try, /*On fail goto*//*Label 44*/ 2104,
458
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
459
56
        GIM_Try, /*On fail goto*//*Label 45*/ 522, // Rule ID 2071 //
460
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
461
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
462
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
463
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
464
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
465
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
466
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
467
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
468
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
469
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
470
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
471
56
          // MIs[3] x
472
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
473
56
          // MIs[3] z
474
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
475
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
476
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
477
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
478
56
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
479
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
480
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
481
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
482
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
483
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
484
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
485
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
486
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
487
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
488
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
489
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
490
56
          GIR_EraseFromParent, /*InsnID*/0,
491
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
492
56
          // GIR_Coverage, 2071,
493
56
          GIR_Done,
494
56
        // Label 45: @522
495
56
        GIM_Try, /*On fail goto*//*Label 46*/ 623, // Rule ID 2072 //
496
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
497
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
498
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
499
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
500
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
501
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
502
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
503
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
504
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
505
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
506
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
507
56
          // MIs[3] z
508
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
509
56
          // MIs[3] x
510
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
511
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
512
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
513
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
514
56
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
515
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
516
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
517
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
518
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
519
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
520
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
521
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
522
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
523
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
524
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
525
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
526
56
          GIR_EraseFromParent, /*InsnID*/0,
527
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
528
56
          // GIR_Coverage, 2072,
529
56
          GIR_Done,
530
56
        // Label 46: @623
531
56
        GIM_Try, /*On fail goto*//*Label 47*/ 724, // Rule ID 2073 //
532
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
533
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
534
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
535
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
536
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
537
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
538
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
539
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
540
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
541
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
542
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
543
56
          // MIs[3] x
544
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
545
56
          // MIs[3] z
546
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
547
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
548
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
549
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
550
56
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
551
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
552
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
553
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
554
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
555
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
556
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
557
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
558
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
559
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
560
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
561
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
562
56
          GIR_EraseFromParent, /*InsnID*/0,
563
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
564
56
          // GIR_Coverage, 2073,
565
56
          GIR_Done,
566
56
        // Label 47: @724
567
56
        GIM_Try, /*On fail goto*//*Label 48*/ 825, // Rule ID 2074 //
568
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
569
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
570
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
571
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
572
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
573
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
574
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
575
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
576
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
577
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
578
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
579
56
          // MIs[3] z
580
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
581
56
          // MIs[3] x
582
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
583
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
584
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
585
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
586
56
          // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
587
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
588
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
589
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
590
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
591
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
592
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
593
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
594
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
595
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
596
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
597
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
598
56
          GIR_EraseFromParent, /*InsnID*/0,
599
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
600
56
          // GIR_Coverage, 2074,
601
56
          GIR_Done,
602
56
        // Label 48: @825
603
56
        GIM_Try, /*On fail goto*//*Label 49*/ 926, // Rule ID 2067 //
604
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
605
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
606
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
607
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
608
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
609
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
610
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
611
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
612
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
613
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
614
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
615
56
          // MIs[3] x
616
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
617
56
          // MIs[3] z
618
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
619
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
620
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
621
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
622
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
623
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
624
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
625
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
626
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
627
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
628
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
629
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
630
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
631
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
632
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
633
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
634
56
          GIR_EraseFromParent, /*InsnID*/0,
635
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
636
56
          // GIR_Coverage, 2067,
637
56
          GIR_Done,
638
56
        // Label 49: @926
639
56
        GIM_Try, /*On fail goto*//*Label 50*/ 1027, // Rule ID 2068 //
640
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
641
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
642
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
643
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
644
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
645
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
646
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
647
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
648
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
649
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
650
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
651
56
          // MIs[3] z
652
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
653
56
          // MIs[3] x
654
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
655
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
656
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
657
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
658
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
659
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
660
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
661
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
662
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
663
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
664
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
665
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
666
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
667
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
668
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
669
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
670
56
          GIR_EraseFromParent, /*InsnID*/0,
671
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
672
56
          // GIR_Coverage, 2068,
673
56
          GIR_Done,
674
56
        // Label 50: @1027
675
56
        GIM_Try, /*On fail goto*//*Label 51*/ 1128, // Rule ID 2069 //
676
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
677
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
678
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
679
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
680
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
681
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
682
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
683
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
684
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
685
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
686
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
687
56
          // MIs[3] x
688
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
689
56
          // MIs[3] z
690
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
691
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
692
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
693
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
694
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
695
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
696
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
697
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
698
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
699
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
700
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
701
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
702
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
703
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
704
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
705
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
706
56
          GIR_EraseFromParent, /*InsnID*/0,
707
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
708
56
          // GIR_Coverage, 2069,
709
56
          GIR_Done,
710
56
        // Label 51: @1128
711
56
        GIM_Try, /*On fail goto*//*Label 52*/ 1229, // Rule ID 2070 //
712
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
713
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
714
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
715
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
716
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
717
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
718
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
719
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
720
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
721
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
722
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
723
56
          // MIs[3] z
724
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
725
56
          // MIs[3] x
726
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
727
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
728
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
729
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
730
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
731
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
732
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
733
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
734
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
735
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
736
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
737
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
738
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
739
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
740
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
741
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
742
56
          GIR_EraseFromParent, /*InsnID*/0,
743
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
744
56
          // GIR_Coverage, 2070,
745
56
          GIR_Done,
746
56
        // Label 52: @1229
747
56
        GIM_Try, /*On fail goto*//*Label 53*/ 1330, // Rule ID 2061 //
748
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
749
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
750
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
751
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
752
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
753
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
754
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
755
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
756
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
757
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
758
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
759
56
          // MIs[3] x
760
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
761
56
          // MIs[3] z
762
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
763
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
764
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
765
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
766
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
767
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
768
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
769
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
770
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
771
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
772
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
773
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
774
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
775
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
776
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
777
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
778
56
          GIR_EraseFromParent, /*InsnID*/0,
779
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
780
56
          // GIR_Coverage, 2061,
781
56
          GIR_Done,
782
56
        // Label 53: @1330
783
56
        GIM_Try, /*On fail goto*//*Label 54*/ 1431, // Rule ID 2062 //
784
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
785
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
786
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
787
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
788
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
789
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
790
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
791
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
792
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
793
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
794
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
795
56
          // MIs[3] z
796
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
797
56
          // MIs[3] x
798
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
799
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
800
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
801
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
802
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
803
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
804
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
805
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
806
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
807
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
808
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
809
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
810
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
811
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
812
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
813
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
814
56
          GIR_EraseFromParent, /*InsnID*/0,
815
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
816
56
          // GIR_Coverage, 2062,
817
56
          GIR_Done,
818
56
        // Label 54: @1431
819
56
        GIM_Try, /*On fail goto*//*Label 55*/ 1532, // Rule ID 2065 //
820
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
821
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
822
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
823
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
824
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
825
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
826
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
827
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
828
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
829
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
830
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
831
56
          // MIs[3] x
832
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
833
56
          // MIs[3] z
834
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
835
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
836
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
837
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
838
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
839
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
840
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
841
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
842
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
843
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
844
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
845
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
846
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
847
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
848
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
849
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
850
56
          GIR_EraseFromParent, /*InsnID*/0,
851
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
852
56
          // GIR_Coverage, 2065,
853
56
          GIR_Done,
854
56
        // Label 55: @1532
855
56
        GIM_Try, /*On fail goto*//*Label 56*/ 1633, // Rule ID 2066 //
856
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
857
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
858
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
859
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
860
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
861
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
862
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
863
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
864
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
865
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
866
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
867
56
          // MIs[3] z
868
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
869
56
          // MIs[3] x
870
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
871
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
872
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
873
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
874
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
875
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
876
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
877
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
878
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
879
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
880
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
881
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
882
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
883
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
884
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
885
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
886
56
          GIR_EraseFromParent, /*InsnID*/0,
887
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
888
56
          // GIR_Coverage, 2066,
889
56
          GIR_Done,
890
56
        // Label 56: @1633
891
56
        GIM_Try, /*On fail goto*//*Label 57*/ 1734, // Rule ID 824 //
892
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
893
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
894
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
895
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
896
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
897
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
898
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
899
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
900
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
901
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
902
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
903
56
          // MIs[3] x
904
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
905
56
          // MIs[3] z
906
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
907
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
908
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
909
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
910
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
911
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
912
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
913
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
914
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
915
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
916
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
917
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
918
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
919
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
920
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
921
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
922
56
          GIR_EraseFromParent, /*InsnID*/0,
923
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
924
56
          // GIR_Coverage, 824,
925
56
          GIR_Done,
926
56
        // Label 57: @1734
927
56
        GIM_Try, /*On fail goto*//*Label 58*/ 1835, // Rule ID 2060 //
928
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
929
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
930
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
931
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
932
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
933
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
934
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
935
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
936
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
937
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
938
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
939
56
          // MIs[3] z
940
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
941
56
          // MIs[3] x
942
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
943
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
944
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
945
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
946
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
947
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
948
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
949
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
950
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
951
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
952
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
953
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
954
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
955
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
956
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
957
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
958
56
          GIR_EraseFromParent, /*InsnID*/0,
959
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
960
56
          // GIR_Coverage, 2060,
961
56
          GIR_Done,
962
56
        // Label 58: @1835
963
56
        GIM_Try, /*On fail goto*//*Label 59*/ 1936, // Rule ID 2063 //
964
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
965
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
966
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
967
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
968
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
969
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
970
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
971
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
972
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
973
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
974
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
975
56
          // MIs[3] x
976
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
977
56
          // MIs[3] z
978
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
979
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
980
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
981
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
982
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
983
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
984
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
985
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
986
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
987
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
988
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
989
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
990
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
991
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
992
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
993
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
994
56
          GIR_EraseFromParent, /*InsnID*/0,
995
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
996
56
          // GIR_Coverage, 2063,
997
56
          GIR_Done,
998
56
        // Label 59: @1936
999
56
        GIM_Try, /*On fail goto*//*Label 60*/ 2037, // Rule ID 2064 //
1000
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1001
56
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1002
56
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1003
56
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1004
56
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1005
56
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1006
56
          GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
1007
56
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1008
56
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1009
56
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1010
56
          GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
1011
56
          // MIs[3] z
1012
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
1013
56
          // MIs[3] x
1014
56
          GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
1015
56
          GIM_CheckIsSafeToFold, /*InsnID*/1,
1016
56
          GIM_CheckIsSafeToFold, /*InsnID*/2,
1017
56
          GIM_CheckIsSafeToFold, /*InsnID*/3,
1018
56
          // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
1019
56
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
1020
56
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1021
56
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1022
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
1023
56
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
1024
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1025
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
1026
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1027
56
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1028
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
1029
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
1030
56
          GIR_EraseFromParent, /*InsnID*/0,
1031
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1032
56
          // GIR_Coverage, 2064,
1033
56
          GIR_Done,
1034
56
        // Label 60: @2037
1035
56
        GIM_Try, /*On fail goto*//*Label 61*/ 2070, // Rule ID 1986 //
1036
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1037
56
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
1038
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vsrc0,
1039
56
          // (or:{ *:[i32] } (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0), VGPR_32:{ *:[i32] }:$src1)  =>  (V_OR_B32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1040
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
1041
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1042
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
1043
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1044
56
          GIR_EraseFromParent, /*InsnID*/0,
1045
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1046
56
          // GIR_Coverage, 1986,
1047
56
          GIR_Done,
1048
56
        // Label 61: @2070
1049
56
        GIM_Try, /*On fail goto*//*Label 62*/ 2103, // Rule ID 3258 //
1050
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1051
56
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1052
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
1053
56
          // (or:{ *:[i32] } VGPR_32:{ *:[i32] }:$src1, (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_OR_B32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1054
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
1055
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
1056
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
1057
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1058
56
          GIR_EraseFromParent, /*InsnID*/0,
1059
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1060
56
          // GIR_Coverage, 3258,
1061
56
          GIR_Done,
1062
56
        // Label 62: @2103
1063
56
        GIM_Reject,
1064
56
      // Label 44: @2104
1065
56
      GIM_Try, /*On fail goto*//*Label 63*/ 2130, // Rule ID 1985 //
1066
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1067
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1068
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1069
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
1070
56
        // (or:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)  =>  (S_OR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1071
56
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
1072
56
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
1073
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1074
56
        // GIR_Coverage, 1985,
1075
56
        GIR_Done,
1076
56
      // Label 63: @2130
1077
56
      GIM_Try, /*On fail goto*//*Label 64*/ 2146, // Rule ID 423 //
1078
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1079
56
        // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_OR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1080
56
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e64,
1081
56
        GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
1082
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1083
56
        // GIR_Coverage, 423,
1084
56
        GIR_Done,
1085
56
      // Label 64: @2146
1086
56
      GIM_Reject,
1087
56
    // Label 43: @2147
1088
56
    GIM_Reject,
1089
56
    // Label 5: @2148
1090
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 67*/ 2249,
1091
56
    /*GILLT_s32*//*Label 65*/ 2156,
1092
56
    /*GILLT_s64*//*Label 66*/ 2212,
1093
56
    // Label 65: @2156
1094
56
    GIM_Try, /*On fail goto*//*Label 68*/ 2211,
1095
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1096
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1097
56
      GIM_Try, /*On fail goto*//*Label 69*/ 2194, // Rule ID 0 //
1098
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1099
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1100
56
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1101
56
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })  =>  (S_NOT_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
1102
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B32,
1103
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
1104
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1105
56
        GIR_EraseFromParent, /*InsnID*/0,
1106
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1107
56
        // GIR_Coverage, 0,
1108
56
        GIR_Done,
1109
56
      // Label 69: @2194
1110
56
      GIM_Try, /*On fail goto*//*Label 70*/ 2210, // Rule ID 425 //
1111
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1112
56
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_XOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
1113
56
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_XOR_B32_e64,
1114
56
        GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
1115
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1116
56
        // GIR_Coverage, 425,
1117
56
        GIR_Done,
1118
56
      // Label 70: @2210
1119
56
      GIM_Reject,
1120
56
    // Label 68: @2211
1121
56
    GIM_Reject,
1122
56
    // Label 66: @2212
1123
56
    GIM_Try, /*On fail goto*//*Label 71*/ 2248, // Rule ID 1 //
1124
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1125
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1126
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1127
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
1128
56
      GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1129
56
      // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, -1:{ *:[i64] })  =>  (S_NOT_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0)
1130
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B64,
1131
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
1132
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1133
56
      GIR_EraseFromParent, /*InsnID*/0,
1134
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1135
56
      // GIR_Coverage, 1,
1136
56
      GIR_Done,
1137
56
    // Label 71: @2248
1138
56
    GIM_Reject,
1139
56
    // Label 67: @2249
1140
56
    GIM_Reject,
1141
56
    // Label 6: @2250
1142
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 82*/ 4459,
1143
56
    /*GILLT_s16*//*Label 72*/ 2266,
1144
56
    /*GILLT_s32*//*Label 73*/ 2394,
1145
56
    /*GILLT_s64*//*Label 74*/ 2667,
1146
56
    /*GILLT_v2s16*//*Label 75*/ 3008,
1147
56
    /*GILLT_v2s32*//*Label 76*/ 3213,
1148
56
    /*GILLT_v2s64*//*Label 77*/ 3588,
1149
56
    /*GILLT_v4s16*//*Label 78*/ 3759,
1150
56
    /*GILLT_v4s32*//*Label 79*/ 4100,
1151
56
    /*GILLT_v8s32*//*Label 80*/ 4271,
1152
56
    /*GILLT_v16s32*//*Label 81*/ 4399,
1153
56
    // Label 72: @2266
1154
56
    GIM_Try, /*On fail goto*//*Label 83*/ 2393,
1155
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
1156
56
      GIM_Try, /*On fail goto*//*Label 84*/ 2302, // Rule ID 1632 //
1157
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1158
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1159
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1160
56
        // (bitconvert:{ *:[i16] } VGPR_32:{ *:[f16] }:$src0)  =>  VGPR_32:{ *:[i16] }:$src0
1161
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1162
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1163
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1164
56
        GIR_EraseFromParent, /*InsnID*/0,
1165
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1166
56
        // GIR_Coverage, 1632,
1167
56
        GIR_Done,
1168
56
      // Label 84: @2302
1169
56
      GIM_Try, /*On fail goto*//*Label 85*/ 2332, // Rule ID 1633 //
1170
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1171
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1172
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1173
56
        // (bitconvert:{ *:[f16] } VGPR_32:{ *:[i16] }:$src0)  =>  VGPR_32:{ *:[f16] }:$src0
1174
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1175
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1176
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1177
56
        GIR_EraseFromParent, /*InsnID*/0,
1178
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1179
56
        // GIR_Coverage, 1633,
1180
56
        GIR_Done,
1181
56
      // Label 85: @2332
1182
56
      GIM_Try, /*On fail goto*//*Label 86*/ 2362, // Rule ID 1634 //
1183
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1184
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1185
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1186
56
        // (bitconvert:{ *:[i16] } SReg_32:{ *:[f16] }:$src0)  =>  SReg_32:{ *:[i16] }:$src0
1187
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1188
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1189
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1190
56
        GIR_EraseFromParent, /*InsnID*/0,
1191
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1192
56
        // GIR_Coverage, 1634,
1193
56
        GIR_Done,
1194
56
      // Label 86: @2362
1195
56
      GIM_Try, /*On fail goto*//*Label 87*/ 2392, // Rule ID 1635 //
1196
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1197
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1198
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1199
56
        // (bitconvert:{ *:[f16] } SReg_32:{ *:[i16] }:$src0)  =>  SReg_32:{ *:[f16] }:$src0
1200
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1201
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1202
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1203
56
        GIR_EraseFromParent, /*InsnID*/0,
1204
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1205
56
        // GIR_Coverage, 1635,
1206
56
        GIR_Done,
1207
56
      // Label 87: @2392
1208
56
      GIM_Reject,
1209
56
    // Label 83: @2393
1210
56
    GIM_Reject,
1211
56
    // Label 73: @2394
1212
56
    GIM_Try, /*On fail goto*//*Label 88*/ 2428, // Rule ID 1636 //
1213
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1214
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1215
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1216
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1217
56
      // (bitconvert:{ *:[i32] } VGPR_32:{ *:[f32] }:$src0)  =>  VGPR_32:{ *:[i32] }:$src0
1218
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1219
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1220
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1221
56
      GIR_EraseFromParent, /*InsnID*/0,
1222
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1223
56
      // GIR_Coverage, 1636,
1224
56
      GIR_Done,
1225
56
    // Label 88: @2428
1226
56
    GIM_Try, /*On fail goto*//*Label 89*/ 2462, // Rule ID 1637 //
1227
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1228
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1229
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
1230
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
1231
56
      // (bitconvert:{ *:[f32] } VGPR_32:{ *:[i32] }:$src0)  =>  VGPR_32:{ *:[f32] }:$src0
1232
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1233
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1234
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1235
56
      GIR_EraseFromParent, /*InsnID*/0,
1236
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
1237
56
      // GIR_Coverage, 1637,
1238
56
      GIR_Done,
1239
56
    // Label 89: @2462
1240
56
    GIM_Try, /*On fail goto*//*Label 90*/ 2496, // Rule ID 1638 //
1241
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1242
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1243
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1244
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1245
56
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1246
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1247
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1248
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1249
56
      GIR_EraseFromParent, /*InsnID*/0,
1250
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1251
56
      // GIR_Coverage, 1638,
1252
56
      GIR_Done,
1253
56
    // Label 90: @2496
1254
56
    GIM_Try, /*On fail goto*//*Label 91*/ 2530, // Rule ID 1639 //
1255
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1256
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1257
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1258
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1259
56
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1260
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1261
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1262
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1263
56
      GIR_EraseFromParent, /*InsnID*/0,
1264
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1265
56
      // GIR_Coverage, 1639,
1266
56
      GIR_Done,
1267
56
    // Label 91: @2530
1268
56
    GIM_Try, /*On fail goto*//*Label 92*/ 2564, // Rule ID 1641 //
1269
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1270
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1271
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1272
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1273
56
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1274
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1275
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1276
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1277
56
      GIR_EraseFromParent, /*InsnID*/0,
1278
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1279
56
      // GIR_Coverage, 1641,
1280
56
      GIR_Done,
1281
56
    // Label 92: @2564
1282
56
    GIM_Try, /*On fail goto*//*Label 93*/ 2598, // Rule ID 1643 //
1283
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1284
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1285
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1286
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1287
56
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
1288
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1289
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1290
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1291
56
      GIR_EraseFromParent, /*InsnID*/0,
1292
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1293
56
      // GIR_Coverage, 1643,
1294
56
      GIR_Done,
1295
56
    // Label 93: @2598
1296
56
    GIM_Try, /*On fail goto*//*Label 94*/ 2632, // Rule ID 1647 //
1297
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1298
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1299
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1300
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1301
56
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1302
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1303
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1304
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1305
56
      GIR_EraseFromParent, /*InsnID*/0,
1306
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1307
56
      // GIR_Coverage, 1647,
1308
56
      GIR_Done,
1309
56
    // Label 94: @2632
1310
56
    GIM_Try, /*On fail goto*//*Label 95*/ 2666, // Rule ID 1649 //
1311
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1312
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1313
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1314
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1315
56
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
1316
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1317
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1318
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1319
56
      GIR_EraseFromParent, /*InsnID*/0,
1320
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1321
56
      // GIR_Coverage, 1649,
1322
56
      GIR_Done,
1323
56
    // Label 95: @2666
1324
56
    GIM_Reject,
1325
56
    // Label 74: @2667
1326
56
    GIM_Try, /*On fail goto*//*Label 96*/ 2701, // Rule ID 1650 //
1327
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1328
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1329
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1330
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1331
56
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1332
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1333
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1334
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1335
56
      GIR_EraseFromParent, /*InsnID*/0,
1336
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1337
56
      // GIR_Coverage, 1650,
1338
56
      GIR_Done,
1339
56
    // Label 96: @2701
1340
56
    GIM_Try, /*On fail goto*//*Label 97*/ 2735, // Rule ID 1651 //
1341
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1342
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1343
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1344
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1345
56
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1346
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1347
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1348
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1349
56
      GIR_EraseFromParent, /*InsnID*/0,
1350
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1351
56
      // GIR_Coverage, 1651,
1352
56
      GIR_Done,
1353
56
    // Label 97: @2735
1354
56
    GIM_Try, /*On fail goto*//*Label 98*/ 2769, // Rule ID 1654 //
1355
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1356
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1357
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1358
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1359
56
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1360
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1361
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1362
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1363
56
      GIR_EraseFromParent, /*InsnID*/0,
1364
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1365
56
      // GIR_Coverage, 1654,
1366
56
      GIR_Done,
1367
56
    // Label 98: @2769
1368
56
    GIM_Try, /*On fail goto*//*Label 99*/ 2803, // Rule ID 1656 //
1369
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1370
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1371
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1372
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1373
56
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1374
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1375
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1376
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1377
56
      GIR_EraseFromParent, /*InsnID*/0,
1378
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1379
56
      // GIR_Coverage, 1656,
1380
56
      GIR_Done,
1381
56
    // Label 99: @2803
1382
56
    GIM_Try, /*On fail goto*//*Label 100*/ 2837, // Rule ID 1658 //
1383
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1384
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1385
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1386
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1387
56
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1388
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1389
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1390
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1391
56
      GIR_EraseFromParent, /*InsnID*/0,
1392
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1393
56
      // GIR_Coverage, 1658,
1394
56
      GIR_Done,
1395
56
    // Label 100: @2837
1396
56
    GIM_Try, /*On fail goto*//*Label 101*/ 2871, // Rule ID 1660 //
1397
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1398
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1399
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1400
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1401
56
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1402
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1403
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1404
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1405
56
      GIR_EraseFromParent, /*InsnID*/0,
1406
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1407
56
      // GIR_Coverage, 1660,
1408
56
      GIR_Done,
1409
56
    // Label 101: @2871
1410
56
    GIM_Try, /*On fail goto*//*Label 102*/ 2905, // Rule ID 1675 //
1411
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1412
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1413
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1414
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1415
56
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1416
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1417
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1418
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1419
56
      GIR_EraseFromParent, /*InsnID*/0,
1420
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1421
56
      // GIR_Coverage, 1675,
1422
56
      GIR_Done,
1423
56
    // Label 102: @2905
1424
56
    GIM_Try, /*On fail goto*//*Label 103*/ 2939, // Rule ID 1676 //
1425
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1426
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1427
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1428
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1429
56
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
1430
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1431
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1432
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1433
56
      GIR_EraseFromParent, /*InsnID*/0,
1434
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1435
56
      // GIR_Coverage, 1676,
1436
56
      GIR_Done,
1437
56
    // Label 103: @2939
1438
56
    GIM_Try, /*On fail goto*//*Label 104*/ 2973, // Rule ID 1679 //
1439
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1440
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1441
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1442
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1443
56
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1444
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1445
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1446
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1447
56
      GIR_EraseFromParent, /*InsnID*/0,
1448
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1449
56
      // GIR_Coverage, 1679,
1450
56
      GIR_Done,
1451
56
    // Label 104: @2973
1452
56
    GIM_Try, /*On fail goto*//*Label 105*/ 3007, // Rule ID 1680 //
1453
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1454
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1455
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1456
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1457
56
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
1458
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1459
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1460
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1461
56
      GIR_EraseFromParent, /*InsnID*/0,
1462
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1463
56
      // GIR_Coverage, 1680,
1464
56
      GIR_Done,
1465
56
    // Label 105: @3007
1466
56
    GIM_Reject,
1467
56
    // Label 75: @3008
1468
56
    GIM_Try, /*On fail goto*//*Label 106*/ 3042, // Rule ID 1640 //
1469
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1470
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1471
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1472
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1473
56
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1474
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1475
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1476
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1477
56
      GIR_EraseFromParent, /*InsnID*/0,
1478
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1479
56
      // GIR_Coverage, 1640,
1480
56
      GIR_Done,
1481
56
    // Label 106: @3042
1482
56
    GIM_Try, /*On fail goto*//*Label 107*/ 3076, // Rule ID 1642 //
1483
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1484
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1485
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1486
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1487
56
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1488
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1489
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1490
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1491
56
      GIR_EraseFromParent, /*InsnID*/0,
1492
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1493
56
      // GIR_Coverage, 1642,
1494
56
      GIR_Done,
1495
56
    // Label 107: @3076
1496
56
    GIM_Try, /*On fail goto*//*Label 108*/ 3110, // Rule ID 1644 //
1497
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1498
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1499
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1500
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1501
56
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1502
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1503
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1504
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1505
56
      GIR_EraseFromParent, /*InsnID*/0,
1506
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1507
56
      // GIR_Coverage, 1644,
1508
56
      GIR_Done,
1509
56
    // Label 108: @3110
1510
56
    GIM_Try, /*On fail goto*//*Label 109*/ 3144, // Rule ID 1645 //
1511
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1512
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1513
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1514
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1515
56
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1516
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1517
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1518
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1519
56
      GIR_EraseFromParent, /*InsnID*/0,
1520
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1521
56
      // GIR_Coverage, 1645,
1522
56
      GIR_Done,
1523
56
    // Label 109: @3144
1524
56
    GIM_Try, /*On fail goto*//*Label 110*/ 3178, // Rule ID 1646 //
1525
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1526
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1527
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1528
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1529
56
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
1530
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1531
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1532
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1533
56
      GIR_EraseFromParent, /*InsnID*/0,
1534
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1535
56
      // GIR_Coverage, 1646,
1536
56
      GIR_Done,
1537
56
    // Label 110: @3178
1538
56
    GIM_Try, /*On fail goto*//*Label 111*/ 3212, // Rule ID 1648 //
1539
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1540
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1541
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
1542
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
1543
56
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
1544
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1545
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1546
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1547
56
      GIR_EraseFromParent, /*InsnID*/0,
1548
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
1549
56
      // GIR_Coverage, 1648,
1550
56
      GIR_Done,
1551
56
    // Label 111: @3212
1552
56
    GIM_Reject,
1553
56
    // Label 76: @3213
1554
56
    GIM_Try, /*On fail goto*//*Label 112*/ 3247, // Rule ID 1652 //
1555
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1556
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1557
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1558
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1559
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1560
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1561
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1562
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1563
56
      GIR_EraseFromParent, /*InsnID*/0,
1564
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1565
56
      // GIR_Coverage, 1652,
1566
56
      GIR_Done,
1567
56
    // Label 112: @3247
1568
56
    GIM_Try, /*On fail goto*//*Label 113*/ 3281, // Rule ID 1653 //
1569
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1570
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1571
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1572
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1573
56
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1574
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1575
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1576
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1577
56
      GIR_EraseFromParent, /*InsnID*/0,
1578
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1579
56
      // GIR_Coverage, 1653,
1580
56
      GIR_Done,
1581
56
    // Label 113: @3281
1582
56
    GIM_Try, /*On fail goto*//*Label 114*/ 3315, // Rule ID 1655 //
1583
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1584
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1585
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1586
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1587
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1588
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1589
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1590
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1591
56
      GIR_EraseFromParent, /*InsnID*/0,
1592
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1593
56
      // GIR_Coverage, 1655,
1594
56
      GIR_Done,
1595
56
    // Label 114: @3315
1596
56
    GIM_Try, /*On fail goto*//*Label 115*/ 3349, // Rule ID 1657 //
1597
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1598
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1599
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1600
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1601
56
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1602
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1603
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1604
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1605
56
      GIR_EraseFromParent, /*InsnID*/0,
1606
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1607
56
      // GIR_Coverage, 1657,
1608
56
      GIR_Done,
1609
56
    // Label 115: @3349
1610
56
    GIM_Try, /*On fail goto*//*Label 116*/ 3383, // Rule ID 1659 //
1611
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1612
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1613
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1614
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1615
56
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1616
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1617
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1618
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1619
56
      GIR_EraseFromParent, /*InsnID*/0,
1620
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1621
56
      // GIR_Coverage, 1659,
1622
56
      GIR_Done,
1623
56
    // Label 116: @3383
1624
56
    GIM_Try, /*On fail goto*//*Label 117*/ 3417, // Rule ID 1661 //
1625
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1626
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1627
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1628
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1629
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1630
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1631
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1632
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1633
56
      GIR_EraseFromParent, /*InsnID*/0,
1634
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1635
56
      // GIR_Coverage, 1661,
1636
56
      GIR_Done,
1637
56
    // Label 117: @3417
1638
56
    GIM_Try, /*On fail goto*//*Label 118*/ 3451, // Rule ID 1664 //
1639
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1640
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1641
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1642
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1643
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1644
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1645
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1646
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1647
56
      GIR_EraseFromParent, /*InsnID*/0,
1648
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1649
56
      // GIR_Coverage, 1664,
1650
56
      GIR_Done,
1651
56
    // Label 118: @3451
1652
56
    GIM_Try, /*On fail goto*//*Label 119*/ 3485, // Rule ID 1666 //
1653
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1654
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1655
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1656
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1657
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1658
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1659
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1660
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1661
56
      GIR_EraseFromParent, /*InsnID*/0,
1662
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1663
56
      // GIR_Coverage, 1666,
1664
56
      GIR_Done,
1665
56
    // Label 119: @3485
1666
56
    GIM_Try, /*On fail goto*//*Label 120*/ 3519, // Rule ID 1667 //
1667
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1668
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1669
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1670
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1671
56
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
1672
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1673
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1674
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1675
56
      GIR_EraseFromParent, /*InsnID*/0,
1676
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1677
56
      // GIR_Coverage, 1667,
1678
56
      GIR_Done,
1679
56
    // Label 120: @3519
1680
56
    GIM_Try, /*On fail goto*//*Label 121*/ 3553, // Rule ID 1669 //
1681
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1682
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1683
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1684
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1685
56
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1686
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1687
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1688
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1689
56
      GIR_EraseFromParent, /*InsnID*/0,
1690
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1691
56
      // GIR_Coverage, 1669,
1692
56
      GIR_Done,
1693
56
    // Label 121: @3553
1694
56
    GIM_Try, /*On fail goto*//*Label 122*/ 3587, // Rule ID 1671 //
1695
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1696
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1697
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1698
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1699
56
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
1700
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1701
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1702
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1703
56
      GIR_EraseFromParent, /*InsnID*/0,
1704
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1705
56
      // GIR_Coverage, 1671,
1706
56
      GIR_Done,
1707
56
    // Label 122: @3587
1708
56
    GIM_Reject,
1709
56
    // Label 77: @3588
1710
56
    GIM_Try, /*On fail goto*//*Label 123*/ 3622, // Rule ID 1683 //
1711
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1712
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1713
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_128RegClassID,
1714
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_128RegClassID,
1715
56
      // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
1716
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1717
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1718
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1719
56
      GIR_EraseFromParent, /*InsnID*/0,
1720
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_128*/22,
1721
56
      // GIR_Coverage, 1683,
1722
56
      GIR_Done,
1723
56
    // Label 123: @3622
1724
56
    GIM_Try, /*On fail goto*//*Label 124*/ 3656, // Rule ID 1685 //
1725
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1726
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1727
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1728
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1729
56
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1730
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1731
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1732
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1733
56
      GIR_EraseFromParent, /*InsnID*/0,
1734
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/21,
1735
56
      // GIR_Coverage, 1685,
1736
56
      GIR_Done,
1737
56
    // Label 124: @3656
1738
56
    GIM_Try, /*On fail goto*//*Label 125*/ 3690, // Rule ID 1686 //
1739
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1740
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1741
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1742
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1743
56
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1744
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1745
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1746
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1747
56
      GIR_EraseFromParent, /*InsnID*/0,
1748
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/21,
1749
56
      // GIR_Coverage, 1686,
1750
56
      GIR_Done,
1751
56
    // Label 125: @3690
1752
56
    GIM_Try, /*On fail goto*//*Label 126*/ 3724, // Rule ID 1689 //
1753
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1754
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1755
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1756
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1757
56
      // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
1758
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1759
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1760
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1761
56
      GIR_EraseFromParent, /*InsnID*/0,
1762
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/21,
1763
56
      // GIR_Coverage, 1689,
1764
56
      GIR_Done,
1765
56
    // Label 126: @3724
1766
56
    GIM_Try, /*On fail goto*//*Label 127*/ 3758, // Rule ID 1690 //
1767
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1768
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1769
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1770
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1771
56
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
1772
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1773
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1774
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1775
56
      GIR_EraseFromParent, /*InsnID*/0,
1776
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/21,
1777
56
      // GIR_Coverage, 1690,
1778
56
      GIR_Done,
1779
56
    // Label 127: @3758
1780
56
    GIM_Reject,
1781
56
    // Label 78: @3759
1782
56
    GIM_Try, /*On fail goto*//*Label 128*/ 3793, // Rule ID 1662 //
1783
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1784
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1785
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1786
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1787
56
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1788
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1789
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1790
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1791
56
      GIR_EraseFromParent, /*InsnID*/0,
1792
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1793
56
      // GIR_Coverage, 1662,
1794
56
      GIR_Done,
1795
56
    // Label 128: @3793
1796
56
    GIM_Try, /*On fail goto*//*Label 129*/ 3827, // Rule ID 1663 //
1797
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1798
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1799
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1800
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1801
56
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1802
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1803
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1804
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1805
56
      GIR_EraseFromParent, /*InsnID*/0,
1806
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1807
56
      // GIR_Coverage, 1663,
1808
56
      GIR_Done,
1809
56
    // Label 129: @3827
1810
56
    GIM_Try, /*On fail goto*//*Label 130*/ 3861, // Rule ID 1665 //
1811
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1812
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1813
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1814
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1815
56
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1816
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1817
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1818
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1819
56
      GIR_EraseFromParent, /*InsnID*/0,
1820
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1821
56
      // GIR_Coverage, 1665,
1822
56
      GIR_Done,
1823
56
    // Label 130: @3861
1824
56
    GIM_Try, /*On fail goto*//*Label 131*/ 3895, // Rule ID 1668 //
1825
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1826
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1827
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1828
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1829
56
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1830
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1831
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1832
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1833
56
      GIR_EraseFromParent, /*InsnID*/0,
1834
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1835
56
      // GIR_Coverage, 1668,
1836
56
      GIR_Done,
1837
56
    // Label 131: @3895
1838
56
    GIM_Try, /*On fail goto*//*Label 132*/ 3929, // Rule ID 1670 //
1839
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1840
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1841
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1842
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1843
56
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1844
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1845
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1846
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1847
56
      GIR_EraseFromParent, /*InsnID*/0,
1848
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1849
56
      // GIR_Coverage, 1670,
1850
56
      GIR_Done,
1851
56
    // Label 132: @3929
1852
56
    GIM_Try, /*On fail goto*//*Label 133*/ 3963, // Rule ID 1672 //
1853
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1854
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1855
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1856
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1857
56
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1858
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1859
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1860
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1861
56
      GIR_EraseFromParent, /*InsnID*/0,
1862
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1863
56
      // GIR_Coverage, 1672,
1864
56
      GIR_Done,
1865
56
    // Label 133: @3963
1866
56
    GIM_Try, /*On fail goto*//*Label 134*/ 3997, // Rule ID 1673 //
1867
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1868
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1869
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1870
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1871
56
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1872
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1873
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1874
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1875
56
      GIR_EraseFromParent, /*InsnID*/0,
1876
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1877
56
      // GIR_Coverage, 1673,
1878
56
      GIR_Done,
1879
56
    // Label 134: @3997
1880
56
    GIM_Try, /*On fail goto*//*Label 135*/ 4031, // Rule ID 1674 //
1881
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1882
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1883
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1884
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1885
56
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1886
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1887
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1888
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1889
56
      GIR_EraseFromParent, /*InsnID*/0,
1890
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1891
56
      // GIR_Coverage, 1674,
1892
56
      GIR_Done,
1893
56
    // Label 135: @4031
1894
56
    GIM_Try, /*On fail goto*//*Label 136*/ 4065, // Rule ID 1677 //
1895
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1896
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1897
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1898
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1899
56
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
1900
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1901
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1902
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1903
56
      GIR_EraseFromParent, /*InsnID*/0,
1904
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1905
56
      // GIR_Coverage, 1677,
1906
56
      GIR_Done,
1907
56
    // Label 136: @4065
1908
56
    GIM_Try, /*On fail goto*//*Label 137*/ 4099, // Rule ID 1678 //
1909
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1910
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1911
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
1912
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
1913
56
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
1914
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1915
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1916
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1917
56
      GIR_EraseFromParent, /*InsnID*/0,
1918
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/15,
1919
56
      // GIR_Coverage, 1678,
1920
56
      GIR_Done,
1921
56
    // Label 137: @4099
1922
56
    GIM_Reject,
1923
56
    // Label 79: @4100
1924
56
    GIM_Try, /*On fail goto*//*Label 138*/ 4134, // Rule ID 1681 //
1925
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1926
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1927
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1928
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1929
56
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
1930
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1931
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1932
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1933
56
      GIR_EraseFromParent, /*InsnID*/0,
1934
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/21,
1935
56
      // GIR_Coverage, 1681,
1936
56
      GIR_Done,
1937
56
    // Label 138: @4134
1938
56
    GIM_Try, /*On fail goto*//*Label 139*/ 4168, // Rule ID 1682 //
1939
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1940
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1941
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1942
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1943
56
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
1944
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1945
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1946
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1947
56
      GIR_EraseFromParent, /*InsnID*/0,
1948
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/21,
1949
56
      // GIR_Coverage, 1682,
1950
56
      GIR_Done,
1951
56
    // Label 139: @4168
1952
56
    GIM_Try, /*On fail goto*//*Label 140*/ 4202, // Rule ID 1684 //
1953
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1954
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1955
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_128RegClassID,
1956
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_128RegClassID,
1957
56
      // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
1958
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1959
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1960
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1961
56
      GIR_EraseFromParent, /*InsnID*/0,
1962
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_128*/22,
1963
56
      // GIR_Coverage, 1684,
1964
56
      GIR_Done,
1965
56
    // Label 140: @4202
1966
56
    GIM_Try, /*On fail goto*//*Label 141*/ 4236, // Rule ID 1687 //
1967
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1968
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1969
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1970
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1971
56
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
1972
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1973
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1974
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1975
56
      GIR_EraseFromParent, /*InsnID*/0,
1976
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/21,
1977
56
      // GIR_Coverage, 1687,
1978
56
      GIR_Done,
1979
56
    // Label 141: @4236
1980
56
    GIM_Try, /*On fail goto*//*Label 142*/ 4270, // Rule ID 1688 //
1981
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
1982
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1983
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
1984
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
1985
56
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
1986
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1987
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1988
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
1989
56
      GIR_EraseFromParent, /*InsnID*/0,
1990
56
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/21,
1991
56
      // GIR_Coverage, 1688,
1992
56
      GIR_Done,
1993
56
    // Label 142: @4270
1994
56
    GIM_Reject,
1995
56
    // Label 80: @4271
1996
56
    GIM_Try, /*On fail goto*//*Label 143*/ 4398,
1997
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
1998
56
      GIM_Try, /*On fail goto*//*Label 144*/ 4307, // Rule ID 1691 //
1999
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2000
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_256RegClassID,
2001
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_256RegClassID,
2002
56
        // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v8f32] }:$src0)  =>  SReg_256:{ *:[v8i32] }:$src0
2003
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2004
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2005
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2006
56
        GIR_EraseFromParent, /*InsnID*/0,
2007
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_256*/27,
2008
56
        // GIR_Coverage, 1691,
2009
56
        GIR_Done,
2010
56
      // Label 144: @4307
2011
56
      GIM_Try, /*On fail goto*//*Label 145*/ 4337, // Rule ID 1692 //
2012
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2013
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_256RegClassID,
2014
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_256RegClassID,
2015
56
        // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v8i32] }:$src0)  =>  SReg_256:{ *:[v8f32] }:$src0
2016
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2017
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2018
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2019
56
        GIR_EraseFromParent, /*InsnID*/0,
2020
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_256*/27,
2021
56
        // GIR_Coverage, 1692,
2022
56
        GIR_Done,
2023
56
      // Label 145: @4337
2024
56
      GIM_Try, /*On fail goto*//*Label 146*/ 4367, // Rule ID 1693 //
2025
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2026
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_256RegClassID,
2027
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_256RegClassID,
2028
56
        // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
2029
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2030
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2031
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2032
56
        GIR_EraseFromParent, /*InsnID*/0,
2033
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_256*/26,
2034
56
        // GIR_Coverage, 1693,
2035
56
        GIR_Done,
2036
56
      // Label 146: @4367
2037
56
      GIM_Try, /*On fail goto*//*Label 147*/ 4397, // Rule ID 1694 //
2038
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2039
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_256RegClassID,
2040
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_256RegClassID,
2041
56
        // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
2042
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2043
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2044
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2045
56
        GIR_EraseFromParent, /*InsnID*/0,
2046
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_256*/26,
2047
56
        // GIR_Coverage, 1694,
2048
56
        GIR_Done,
2049
56
      // Label 147: @4397
2050
56
      GIM_Reject,
2051
56
    // Label 143: @4398
2052
56
    GIM_Reject,
2053
56
    // Label 81: @4399
2054
56
    GIM_Try, /*On fail goto*//*Label 148*/ 4458,
2055
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
2056
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_512RegClassID,
2057
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_512RegClassID,
2058
56
      GIM_Try, /*On fail goto*//*Label 149*/ 4435, // Rule ID 1695 //
2059
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2060
56
        // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
2061
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2062
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2063
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2064
56
        GIR_EraseFromParent, /*InsnID*/0,
2065
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_512*/30,
2066
56
        // GIR_Coverage, 1695,
2067
56
        GIR_Done,
2068
56
      // Label 149: @4435
2069
56
      GIM_Try, /*On fail goto*//*Label 150*/ 4457, // Rule ID 1696 //
2070
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2071
56
        // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
2072
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2073
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2074
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
2075
56
        GIR_EraseFromParent, /*InsnID*/0,
2076
56
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_512*/30,
2077
56
        // GIR_Coverage, 1696,
2078
56
        GIR_Done,
2079
56
      // Label 150: @4457
2080
56
      GIM_Reject,
2081
56
    // Label 148: @4458
2082
56
    GIM_Reject,
2083
56
    // Label 82: @4459
2084
56
    GIM_Reject,
2085
56
    // Label 7: @4460
2086
56
    GIM_Try, /*On fail goto*//*Label 151*/ 4550,
2087
56
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
2088
56
      GIM_Try, /*On fail goto*//*Label 152*/ 4493, // Rule ID 10 //
2089
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2090
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_getpc,
2091
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2092
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2093
56
        // (intrinsic_wo_chain:{ *:[i64] } 1006:{ *:[iPTR] })  =>  (S_GETPC_B64:{ *:[i64] })
2094
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_GETPC_B64,
2095
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2096
56
        GIR_EraseFromParent, /*InsnID*/0,
2097
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2098
56
        // GIR_Coverage, 10,
2099
56
        GIR_Done,
2100
56
      // Label 152: @4493
2101
56
      GIM_Try, /*On fail goto*//*Label 153*/ 4521, // Rule ID 675 //
2102
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2103
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_groupstaticsize,
2104
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2105
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2106
56
        // (intrinsic_wo_chain:{ *:[i32] } 489:{ *:[iPTR] })  =>  (GET_GROUPSTATICSIZE:{ *:[i32] })
2107
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GET_GROUPSTATICSIZE,
2108
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2109
56
        GIR_EraseFromParent, /*InsnID*/0,
2110
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2111
56
        // GIR_Coverage, 675,
2112
56
        GIR_Done,
2113
56
      // Label 153: @4521
2114
56
      GIM_Try, /*On fail goto*//*Label 154*/ 4549, // Rule ID 682 //
2115
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2116
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_ps_live,
2117
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
2118
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2119
56
        // (intrinsic_wo_chain:{ *:[i1] } 972:{ *:[iPTR] })  =>  (SI_PS_LIVE:{ *:[i1] })
2120
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_PS_LIVE,
2121
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2122
56
        GIR_EraseFromParent, /*InsnID*/0,
2123
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2124
56
        // GIR_Coverage, 682,
2125
56
        GIR_Done,
2126
56
      // Label 154: @4549
2127
56
      GIM_Reject,
2128
56
    // Label 151: @4550
2129
56
    GIM_Try, /*On fail goto*//*Label 155*/ 4985,
2130
56
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2131
56
      GIM_Try, /*On fail goto*//*Label 156*/ 4591, // Rule ID 2 //
2132
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2133
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_wqm_vote,
2134
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
2135
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
2136
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2137
56
        // (intrinsic_wo_chain:{ *:[i1] } 1059:{ *:[iPTR] }, i1:{ *:[i1] }:$src0)  =>  (S_WQM_B64:{ *:[i1] }:{ *:[i1] } i1:{ *:[i1] }:$src0)
2138
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_WQM_B64,
2139
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
2140
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2141
56
        GIR_EraseFromParent, /*InsnID*/0,
2142
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2143
56
        // GIR_Coverage, 2,
2144
56
        GIR_Done,
2145
56
      // Label 156: @4591
2146
56
      GIM_Try, /*On fail goto*//*Label 157*/ 4627, // Rule ID 329 //
2147
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2148
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_readfirstlane,
2149
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2150
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2151
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2152
56
        // (intrinsic_wo_chain:{ *:[i32] } 994:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
2153
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READFIRSTLANE_B32,
2154
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2155
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2156
56
        GIR_EraseFromParent, /*InsnID*/0,
2157
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2158
56
        // GIR_Coverage, 329,
2159
56
        GIR_Done,
2160
56
      // Label 157: @4627
2161
56
      GIM_Try, /*On fail goto*//*Label 158*/ 4678, // Rule ID 364 //
2162
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2163
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2164
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2165
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2166
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2167
56
        // (intrinsic_wo_chain:{ *:[i32] } 487:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2168
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F64_e64,
2169
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2170
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2171
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2172
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2173
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2174
56
        GIR_EraseFromParent, /*InsnID*/0,
2175
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2176
56
        // GIR_Coverage, 364,
2177
56
        GIR_Done,
2178
56
      // Label 158: @4678
2179
56
      GIM_Try, /*On fail goto*//*Label 159*/ 4729, // Rule ID 365 //
2180
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2181
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2182
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2183
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2184
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2185
56
        // (intrinsic_wo_chain:{ *:[f64] } 488:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2186
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F64_e64,
2187
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2188
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2189
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2190
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2191
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2192
56
        GIR_EraseFromParent, /*InsnID*/0,
2193
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2194
56
        // GIR_Coverage, 365,
2195
56
        GIR_Done,
2196
56
      // Label 159: @4729
2197
56
      GIM_Try, /*On fail goto*//*Label 160*/ 4780, // Rule ID 367 //
2198
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2199
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2200
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2201
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2202
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2203
56
        // (intrinsic_wo_chain:{ *:[i32] } 487:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2204
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F32_e64,
2205
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2206
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2207
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2208
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2209
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2210
56
        GIR_EraseFromParent, /*InsnID*/0,
2211
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2212
56
        // GIR_Coverage, 367,
2213
56
        GIR_Done,
2214
56
      // Label 160: @4780
2215
56
      GIM_Try, /*On fail goto*//*Label 161*/ 4831, // Rule ID 368 //
2216
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2217
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2218
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2219
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2220
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2221
56
        // (intrinsic_wo_chain:{ *:[f32] } 488:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2222
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F32_e64,
2223
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2224
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2225
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2226
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2227
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2228
56
        GIR_EraseFromParent, /*InsnID*/0,
2229
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2230
56
        // GIR_Coverage, 368,
2231
56
        GIR_Done,
2232
56
      // Label 161: @4831
2233
56
      GIM_Try, /*On fail goto*//*Label 162*/ 4882, // Rule ID 369 //
2234
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_log_clamp,
2235
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2236
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2237
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2238
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2239
56
        // (intrinsic_wo_chain:{ *:[f32] } 964:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_CLAMP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2240
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_CLAMP_F32_e64,
2241
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2242
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2243
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2244
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2245
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2246
56
        GIR_EraseFromParent, /*InsnID*/0,
2247
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2248
56
        // GIR_Coverage, 369,
2249
56
        GIR_Done,
2250
56
      // Label 162: @4882
2251
56
      GIM_Try, /*On fail goto*//*Label 163*/ 4933, // Rule ID 389 //
2252
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
2253
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
2254
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2255
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2256
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2257
56
        // (intrinsic_wo_chain:{ *:[f16] } 488:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2258
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F16_e64,
2259
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2260
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2261
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2262
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2263
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2264
56
        GIR_EraseFromParent, /*InsnID*/0,
2265
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2266
56
        // GIR_Coverage, 389,
2267
56
        GIR_Done,
2268
56
      // Label 163: @4933
2269
56
      GIM_Try, /*On fail goto*//*Label 164*/ 4984, // Rule ID 390 //
2270
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
2271
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
2272
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2273
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2274
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2275
56
        // (intrinsic_wo_chain:{ *:[i16] } 487:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2276
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I16_F16_e64,
2277
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2278
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2279
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2280
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2281
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2282
56
        GIR_EraseFromParent, /*InsnID*/0,
2283
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2284
56
        // GIR_Coverage, 390,
2285
56
        GIR_Done,
2286
56
      // Label 164: @4984
2287
56
      GIM_Reject,
2288
56
    // Label 155: @4985
2289
56
    GIM_Try, /*On fail goto*//*Label 165*/ 5811,
2290
56
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
2291
56
      GIM_Try, /*On fail goto*//*Label 166*/ 5060, // Rule ID 1991 //
2292
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2293
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pkrtz,
2294
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
2295
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2296
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2297
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2298
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2299
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2300
56
        // (intrinsic_wo_chain:{ *:[v2f16] } 460:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_CVT_PKRTZ_F16_F32_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2301
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PKRTZ_F16_F32_e64,
2302
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2303
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2304
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2305
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2306
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2307
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2308
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
2309
56
        GIR_EraseFromParent, /*InsnID*/0,
2310
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2311
56
        // GIR_Coverage, 1991,
2312
56
        GIR_Done,
2313
56
      // Label 166: @5060
2314
56
      GIM_Try, /*On fail goto*//*Label 167*/ 5130, // Rule ID 1992 //
2315
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2316
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2317
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2318
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2319
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2320
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2321
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2322
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2323
56
        // (intrinsic_wo_chain:{ *:[f64] } 142:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2324
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
2325
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2326
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2327
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2328
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2329
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2330
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2331
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
2332
56
        GIR_EraseFromParent, /*InsnID*/0,
2333
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2334
56
        // GIR_Coverage, 1992,
2335
56
        GIR_Done,
2336
56
      // Label 167: @5130
2337
56
      GIM_Try, /*On fail goto*//*Label 168*/ 5200, // Rule ID 1995 //
2338
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2339
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2340
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2341
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2342
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2343
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2344
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2345
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2346
56
        // (intrinsic_wo_chain:{ *:[f64] } 150:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2347
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
2348
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2349
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2350
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2351
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2352
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2353
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2354
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
2355
56
        GIR_EraseFromParent, /*InsnID*/0,
2356
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2357
56
        // GIR_Coverage, 1995,
2358
56
        GIR_Done,
2359
56
      // Label 168: @5200
2360
56
      GIM_Try, /*On fail goto*//*Label 169*/ 5270, // Rule ID 3259 //
2361
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2362
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2363
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2364
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2365
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2366
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2367
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods,
2368
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods0,
2369
56
        // (intrinsic_wo_chain:{ *:[f64] } 142:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods))  =>  (V_MAX_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2370
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
2371
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2372
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
2373
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
2374
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
2375
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
2376
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
2377
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omods
2378
56
        GIR_EraseFromParent, /*InsnID*/0,
2379
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2380
56
        // GIR_Coverage, 3259,
2381
56
        GIR_Done,
2382
56
      // Label 169: @5270
2383
56
      GIM_Try, /*On fail goto*//*Label 170*/ 5340, // Rule ID 3260 //
2384
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2385
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2386
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2387
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2388
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2389
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2390
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods,
2391
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods0,
2392
56
        // (intrinsic_wo_chain:{ *:[f64] } 150:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods))  =>  (V_MIN_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
2393
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
2394
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2395
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
2396
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
2397
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
2398
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
2399
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
2400
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omods
2401
56
        GIR_EraseFromParent, /*InsnID*/0,
2402
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2403
56
        // GIR_Coverage, 3260,
2404
56
        GIR_Done,
2405
56
      // Label 170: @5340
2406
56
      GIM_Try, /*On fail goto*//*Label 171*/ 5393, // Rule ID 1983 //
2407
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2408
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2409
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2410
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2411
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2412
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2413
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
2414
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
2415
56
        // (intrinsic_wo_chain:{ *:[f32] } 142:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_MAX_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2416
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e32,
2417
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2418
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2419
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2420
56
        GIR_EraseFromParent, /*InsnID*/0,
2421
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2422
56
        // GIR_Coverage, 1983,
2423
56
        GIR_Done,
2424
56
      // Label 171: @5393
2425
56
      GIM_Try, /*On fail goto*//*Label 172*/ 5446, // Rule ID 1993 //
2426
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2427
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2428
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2429
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2430
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2431
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2432
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
2433
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
2434
56
        // (intrinsic_wo_chain:{ *:[f32] } 150:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_MIN_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2435
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e32,
2436
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2437
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2438
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2439
56
        GIR_EraseFromParent, /*InsnID*/0,
2440
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2441
56
        // GIR_Coverage, 1993,
2442
56
        GIR_Done,
2443
56
      // Label 172: @5446
2444
56
      GIM_Try, /*On fail goto*//*Label 173*/ 5499, // Rule ID 1984 //
2445
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2446
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
2447
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2448
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2449
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2450
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2451
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
2452
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
2453
56
        // (intrinsic_wo_chain:{ *:[f32] } 142:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_MAX_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2454
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e32,
2455
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2456
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2457
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2458
56
        GIR_EraseFromParent, /*InsnID*/0,
2459
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2460
56
        // GIR_Coverage, 1984,
2461
56
        GIR_Done,
2462
56
      // Label 173: @5499
2463
56
      GIM_Try, /*On fail goto*//*Label 174*/ 5552, // Rule ID 1994 //
2464
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2465
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
2466
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2467
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2468
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2469
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2470
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
2471
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
2472
56
        // (intrinsic_wo_chain:{ *:[f32] } 150:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_MIN_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
2473
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e32,
2474
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2475
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2476
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2477
56
        GIR_EraseFromParent, /*InsnID*/0,
2478
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2479
56
        // GIR_Coverage, 1994,
2480
56
        GIR_Done,
2481
56
      // Label 174: @5552
2482
56
      GIM_Try, /*On fail goto*//*Label 175*/ 5594, // Rule ID 426 //
2483
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_readlane,
2484
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2485
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2486
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2487
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
2488
56
        // (intrinsic_wo_chain:{ *:[i32] } 995:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2489
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READLANE_B32,
2490
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2491
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2492
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2493
56
        GIR_EraseFromParent, /*InsnID*/0,
2494
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2495
56
        // GIR_Coverage, 426,
2496
56
        GIR_Done,
2497
56
      // Label 175: @5594
2498
56
      GIM_Try, /*On fail goto*//*Label 176*/ 5638, // Rule ID 671 //
2499
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2500
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_set_inactive,
2501
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2502
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2503
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2504
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2505
56
        // (intrinsic_wo_chain:{ *:[i32] } 1022:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)
2506
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B32,
2507
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2508
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2509
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
2510
56
        GIR_EraseFromParent, /*InsnID*/0,
2511
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2512
56
        // GIR_Coverage, 671,
2513
56
        GIR_Done,
2514
56
      // Label 176: @5638
2515
56
      GIM_Try, /*On fail goto*//*Label 177*/ 5682, // Rule ID 672 //
2516
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2517
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_set_inactive,
2518
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2519
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2520
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2521
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2522
56
        // (intrinsic_wo_chain:{ *:[i64] } 1022:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)  =>  (V_SET_INACTIVE_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)
2523
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B64,
2524
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2525
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2526
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
2527
56
        GIR_EraseFromParent, /*InsnID*/0,
2528
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2529
56
        // GIR_Coverage, 672,
2530
56
        GIR_Done,
2531
56
      // Label 177: @5682
2532
56
      GIM_Try, /*On fail goto*//*Label 178*/ 5726, // Rule ID 681 //
2533
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2534
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_if_break,
2535
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2536
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
2537
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
2538
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
2539
56
        // (intrinsic_wo_chain:{ *:[i64] } 492:{ *:[iPTR] }, i1:{ *:[i1] }:$vcc, i64:{ *:[i64] }:$src)  =>  (SI_IF_BREAK:{ *:[i64] }:{ *:[i1] } i1:{ *:[i1] }:$vcc, i64:{ *:[i64] }:$src)
2540
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_IF_BREAK,
2541
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2542
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vcc
2543
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
2544
56
        GIR_EraseFromParent, /*InsnID*/0,
2545
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2546
56
        // GIR_Coverage, 681,
2547
56
        GIR_Done,
2548
56
      // Label 178: @5726
2549
56
      GIM_Try, /*On fail goto*//*Label 179*/ 5768, // Rule ID 428 //
2550
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mbcnt_lo,
2551
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2552
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2553
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2554
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2555
56
        // (intrinsic_wo_chain:{ *:[i32] } 967:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_LO_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2556
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_LO_U32_B32_e64,
2557
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2558
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2559
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2560
56
        GIR_EraseFromParent, /*InsnID*/0,
2561
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2562
56
        // GIR_Coverage, 428,
2563
56
        GIR_Done,
2564
56
      // Label 179: @5768
2565
56
      GIM_Try, /*On fail goto*//*Label 180*/ 5810, // Rule ID 429 //
2566
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mbcnt_hi,
2567
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2568
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2569
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2570
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2571
56
        // (intrinsic_wo_chain:{ *:[i32] } 966:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_HI_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
2572
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_HI_U32_B32_e64,
2573
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2574
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2575
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2576
56
        GIR_EraseFromParent, /*InsnID*/0,
2577
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2578
56
        // GIR_Coverage, 429,
2579
56
        GIR_Done,
2580
56
      // Label 180: @5810
2581
56
      GIM_Reject,
2582
56
    // Label 165: @5811
2583
56
    GIM_Try, /*On fail goto*//*Label 181*/ 6823,
2584
56
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
2585
56
      GIM_Try, /*On fail goto*//*Label 182*/ 5866, // Rule ID 427 //
2586
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_writelane,
2587
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2588
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2589
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2590
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2591
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2592
56
        // (intrinsic_wo_chain:{ *:[i32] } 1060:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)  =>  (V_WRITELANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)
2593
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_WRITELANE_B32,
2594
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2595
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2596
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2597
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vdst_in
2598
56
        GIR_EraseFromParent, /*InsnID*/0,
2599
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2600
56
        // GIR_Coverage, 427,
2601
56
        GIR_Done,
2602
56
      // Label 182: @5866
2603
56
      GIM_Try, /*On fail goto*//*Label 183*/ 5921, // Rule ID 989 //
2604
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2605
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_u8,
2606
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2607
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2608
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2609
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2610
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2611
56
        // (intrinsic_wo_chain:{ *:[i32] } 1017:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2612
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U8,
2613
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2614
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2615
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2616
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2617
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2618
56
        GIR_EraseFromParent, /*InsnID*/0,
2619
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2620
56
        // GIR_Coverage, 989,
2621
56
        GIR_Done,
2622
56
      // Label 183: @5921
2623
56
      GIM_Try, /*On fail goto*//*Label 184*/ 5976, // Rule ID 990 //
2624
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2625
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_hi_u8,
2626
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2627
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2628
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2629
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2630
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2631
56
        // (intrinsic_wo_chain:{ *:[i32] } 1015:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_HI_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2632
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_HI_U8,
2633
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2634
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2635
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2636
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2637
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2638
56
        GIR_EraseFromParent, /*InsnID*/0,
2639
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2640
56
        // GIR_Coverage, 990,
2641
56
        GIR_Done,
2642
56
      // Label 184: @5976
2643
56
      GIM_Try, /*On fail goto*//*Label 185*/ 6031, // Rule ID 991 //
2644
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2645
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_u16,
2646
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2647
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2648
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2649
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2650
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2651
56
        // (intrinsic_wo_chain:{ *:[i32] } 1016:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U16:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2652
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U16,
2653
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2654
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2655
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2656
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2657
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2658
56
        GIR_EraseFromParent, /*InsnID*/0,
2659
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2660
56
        // GIR_Coverage, 991,
2661
56
        GIR_Done,
2662
56
      // Label 185: @6031
2663
56
      GIM_Try, /*On fail goto*//*Label 186*/ 6086, // Rule ID 992 //
2664
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2665
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_msad_u8,
2666
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2667
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2668
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2669
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2670
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2671
56
        // (intrinsic_wo_chain:{ *:[i32] } 971:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_MSAD_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
2672
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MSAD_U8,
2673
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2674
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2675
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2676
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2677
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2678
56
        GIR_EraseFromParent, /*InsnID*/0,
2679
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2680
56
        // GIR_Coverage, 992,
2681
56
        GIR_Done,
2682
56
      // Label 186: @6086
2683
56
      GIM_Try, /*On fail goto*//*Label 187*/ 6141, // Rule ID 993 //
2684
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2685
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mqsad_pk_u16_u8,
2686
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2687
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2688
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2689
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
2690
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2691
56
        // (intrinsic_wo_chain:{ *:[i64] } 969:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_MQSAD_PK_U16_U8:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
2692
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_PK_U16_U8,
2693
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2694
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2695
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2696
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2697
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2698
56
        GIR_EraseFromParent, /*InsnID*/0,
2699
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2700
56
        // GIR_Coverage, 993,
2701
56
        GIR_Done,
2702
56
      // Label 187: @6141
2703
56
      GIM_Try, /*On fail goto*//*Label 188*/ 6196, // Rule ID 994 //
2704
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2705
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_qsad_pk_u16_u8,
2706
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2707
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2708
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2709
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
2710
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
2711
56
        // (intrinsic_wo_chain:{ *:[i64] } 973:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_QSAD_PK_U16_U8:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
2712
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_QSAD_PK_U16_U8,
2713
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2714
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2715
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2716
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2717
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2718
56
        GIR_EraseFromParent, /*InsnID*/0,
2719
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2720
56
        // GIR_Coverage, 994,
2721
56
        GIR_Done,
2722
56
      // Label 188: @6196
2723
56
      GIM_Try, /*On fail goto*//*Label 189*/ 6251, // Rule ID 995 //
2724
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2725
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mqsad_u32_u8,
2726
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
2727
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2728
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2729
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
2730
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
2731
56
        // (intrinsic_wo_chain:{ *:[v4i32] } 970:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2)  =>  (V_MQSAD_U32_U8:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] })
2732
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_U32_U8,
2733
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2734
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2735
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2736
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2737
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
2738
56
        GIR_EraseFromParent, /*InsnID*/0,
2739
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2740
56
        // GIR_Coverage, 995,
2741
56
        GIR_Done,
2742
56
      // Label 189: @6251
2743
56
      GIM_Try, /*On fail goto*//*Label 190*/ 6336, // Rule ID 466 //
2744
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubeid,
2745
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2746
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2747
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2748
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2749
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2750
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2751
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2752
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2753
56
        // (intrinsic_wo_chain:{ *:[f32] } 451:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEID_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2754
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEID_F32,
2755
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2756
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2757
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2758
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2759
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2760
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2761
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2762
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2763
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2764
56
        GIR_EraseFromParent, /*InsnID*/0,
2765
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2766
56
        // GIR_Coverage, 466,
2767
56
        GIR_Done,
2768
56
      // Label 190: @6336
2769
56
      GIM_Try, /*On fail goto*//*Label 191*/ 6421, // Rule ID 467 //
2770
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubesc,
2771
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2772
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2773
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2774
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2775
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2776
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2777
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2778
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2779
56
        // (intrinsic_wo_chain:{ *:[f32] } 453:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBESC_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2780
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBESC_F32,
2781
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2782
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2783
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2784
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2785
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2786
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2787
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2788
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2789
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2790
56
        GIR_EraseFromParent, /*InsnID*/0,
2791
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2792
56
        // GIR_Coverage, 467,
2793
56
        GIR_Done,
2794
56
      // Label 191: @6421
2795
56
      GIM_Try, /*On fail goto*//*Label 192*/ 6506, // Rule ID 468 //
2796
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubetc,
2797
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2798
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2799
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2800
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2801
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2802
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2803
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2804
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2805
56
        // (intrinsic_wo_chain:{ *:[f32] } 454:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBETC_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2806
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBETC_F32,
2807
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2808
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2809
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2810
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2811
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2812
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2813
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2814
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2815
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2816
56
        GIR_EraseFromParent, /*InsnID*/0,
2817
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2818
56
        // GIR_Coverage, 468,
2819
56
        GIR_Done,
2820
56
      // Label 192: @6506
2821
56
      GIM_Try, /*On fail goto*//*Label 193*/ 6591, // Rule ID 469 //
2822
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubema,
2823
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2824
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2825
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2826
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2827
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2828
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2829
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2830
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2831
56
        // (intrinsic_wo_chain:{ *:[f32] } 452:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEMA_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
2832
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEMA_F32,
2833
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2834
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2835
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2836
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2837
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2838
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2839
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2840
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2841
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
2842
56
        GIR_EraseFromParent, /*InsnID*/0,
2843
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2844
56
        // GIR_Coverage, 469,
2845
56
        GIR_Done,
2846
56
      // Label 193: @6591
2847
56
      GIM_Try, /*On fail goto*//*Label 194*/ 6672, // Rule ID 484 //
2848
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pk_u8_f32,
2849
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2850
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2851
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2852
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2853
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2854
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
2855
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
2856
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
2857
56
        // (intrinsic_wo_chain:{ *:[i32] } 457:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CVT_PK_U8_F32:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
2858
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PK_U8_F32,
2859
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2860
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
2861
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
2862
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
2863
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
2864
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
2865
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
2866
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
2867
56
        GIR_EraseFromParent, /*InsnID*/0,
2868
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2869
56
        // GIR_Coverage, 484,
2870
56
        GIR_Done,
2871
56
      // Label 194: @6672
2872
56
      GIM_Try, /*On fail goto*//*Label 195*/ 6722, // Rule ID 454 //
2873
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_lerp,
2874
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2875
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2876
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2877
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2878
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2879
56
        // (intrinsic_wo_chain:{ *:[i32] } 963:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_LERP_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
2880
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LERP_U8,
2881
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2882
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2883
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2884
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2885
56
        GIR_EraseFromParent, /*InsnID*/0,
2886
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2887
56
        // GIR_Coverage, 454,
2888
56
        GIR_Done,
2889
56
      // Label 195: @6722
2890
56
      GIM_Try, /*On fail goto*//*Label 196*/ 6772, // Rule ID 473 //
2891
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_alignbit,
2892
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2893
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2894
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2895
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2896
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2897
56
        // (intrinsic_wo_chain:{ *:[i32] } 427:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBIT_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
2898
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBIT_B32,
2899
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2900
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2901
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2902
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2903
56
        GIR_EraseFromParent, /*InsnID*/0,
2904
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2905
56
        // GIR_Coverage, 473,
2906
56
        GIR_Done,
2907
56
      // Label 196: @6772
2908
56
      GIM_Try, /*On fail goto*//*Label 197*/ 6822, // Rule ID 474 //
2909
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_alignbyte,
2910
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
2911
56
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2912
56
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
2913
56
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
2914
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
2915
56
        // (intrinsic_wo_chain:{ *:[i32] } 428:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBYTE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
2916
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBYTE_B32,
2917
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
2918
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
2919
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
2920
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
2921
56
        GIR_EraseFromParent, /*InsnID*/0,
2922
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2923
56
        // GIR_Coverage, 474,
2924
56
        GIR_Done,
2925
56
      // Label 197: @6822
2926
56
      GIM_Reject,
2927
56
    // Label 181: @6823
2928
56
    GIM_Reject,
2929
56
    // Label 8: @6824
2930
56
    GIM_Try, /*On fail goto*//*Label 198*/ 6844, // Rule ID 61 //
2931
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2932
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_barrier,
2933
56
      // (intrinsic_void 999:{ *:[iPTR] })  =>  (S_BARRIER)
2934
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_BARRIER,
2935
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2936
56
      GIR_EraseFromParent, /*InsnID*/0,
2937
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2938
56
      // GIR_Coverage, 61,
2939
56
      GIR_Done,
2940
56
    // Label 198: @6844
2941
56
    GIM_Try, /*On fail goto*//*Label 199*/ 6864, // Rule ID 528 //
2942
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2943
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_inv,
2944
56
      // (intrinsic_void 1001:{ *:[iPTR] })  =>  (S_DCACHE_INV)
2945
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV,
2946
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2947
56
      GIR_EraseFromParent, /*InsnID*/0,
2948
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2949
56
      // GIR_Coverage, 528,
2950
56
      GIR_Done,
2951
56
    // Label 199: @6864
2952
56
    GIM_Try, /*On fail goto*//*Label 200*/ 6884, // Rule ID 529 //
2953
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isCIVI,
2954
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_inv_vol,
2955
56
      // (intrinsic_void 1002:{ *:[iPTR] })  =>  (S_DCACHE_INV_VOL)
2956
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV_VOL,
2957
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2958
56
      GIR_EraseFromParent, /*InsnID*/0,
2959
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2960
56
      // GIR_Coverage, 529,
2961
56
      GIR_Done,
2962
56
    // Label 200: @6884
2963
56
    GIM_Try, /*On fail goto*//*Label 201*/ 6904, // Rule ID 530 //
2964
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
2965
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_wb,
2966
56
      // (intrinsic_void 1003:{ *:[iPTR] })  =>  (S_DCACHE_WB)
2967
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB,
2968
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2969
56
      GIR_EraseFromParent, /*InsnID*/0,
2970
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2971
56
      // GIR_Coverage, 530,
2972
56
      GIR_Done,
2973
56
    // Label 201: @6904
2974
56
    GIM_Try, /*On fail goto*//*Label 202*/ 6924, // Rule ID 531 //
2975
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
2976
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_wb_vol,
2977
56
      // (intrinsic_void 1004:{ *:[iPTR] })  =>  (S_DCACHE_WB_VOL)
2978
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB_VOL,
2979
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2980
56
      GIR_EraseFromParent, /*InsnID*/0,
2981
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2982
56
      // GIR_Coverage, 531,
2983
56
      GIR_Done,
2984
56
    // Label 202: @6924
2985
56
    GIM_Try, /*On fail goto*//*Label 203*/ 6944, // Rule ID 661 //
2986
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isSI,
2987
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1_sc,
2988
56
      // (intrinsic_void 447:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_SC)
2989
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_SC,
2990
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
2991
56
      GIR_EraseFromParent, /*InsnID*/0,
2992
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2993
56
      // GIR_Coverage, 661,
2994
56
      GIR_Done,
2995
56
    // Label 203: @6944
2996
56
    GIM_Try, /*On fail goto*//*Label 204*/ 6964, // Rule ID 662 //
2997
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
2998
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1,
2999
56
      // (intrinsic_void 446:{ *:[iPTR] })  =>  (BUFFER_WBINVL1)
3000
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1,
3001
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3002
56
      GIR_EraseFromParent, /*InsnID*/0,
3003
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3004
56
      // GIR_Coverage, 662,
3005
56
      GIR_Done,
3006
56
    // Label 204: @6964
3007
56
    GIM_Try, /*On fail goto*//*Label 205*/ 6984, // Rule ID 663 //
3008
56
      GIM_CheckFeatures, GIFBS_TruePredicate_isCIVI,
3009
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1_vol,
3010
56
      // (intrinsic_void 448:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_VOL)
3011
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_VOL,
3012
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3013
56
      GIR_EraseFromParent, /*InsnID*/0,
3014
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3015
56
      // GIR_Coverage, 663,
3016
56
      GIR_Done,
3017
56
    // Label 205: @6984
3018
56
    GIM_Try, /*On fail goto*//*Label 206*/ 7004, // Rule ID 676 //
3019
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3020
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_wave_barrier,
3021
56
      // (intrinsic_void 1051:{ *:[iPTR] })  =>  (WAVE_BARRIER)
3022
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::WAVE_BARRIER,
3023
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3024
56
      GIR_EraseFromParent, /*InsnID*/0,
3025
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3026
56
      // GIR_Coverage, 676,
3027
56
      GIR_Done,
3028
56
    // Label 206: @7004
3029
56
    GIM_Try, /*On fail goto*//*Label 207*/ 7024, // Rule ID 683 //
3030
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3031
56
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_unreachable,
3032
56
      // (intrinsic_void 1049:{ *:[iPTR] })  =>  (SI_MASKED_UNREACHABLE)
3033
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_MASKED_UNREACHABLE,
3034
56
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3035
56
      GIR_EraseFromParent, /*InsnID*/0,
3036
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3037
56
      // GIR_Coverage, 683,
3038
56
      GIR_Done,
3039
56
    // Label 207: @7024
3040
56
    GIM_Try, /*On fail goto*//*Label 208*/ 7122,
3041
56
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
3042
56
      GIM_Try, /*On fail goto*//*Label 209*/ 7061, // Rule ID 527 //
3043
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3044
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_memtime,
3045
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
3046
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64_XEXECRegClassID,
3047
56
        // (intrinsic_w_chain:{ *:[i64] } 1010:{ *:[iPTR] })  =>  (S_MEMTIME:{ *:[i64] })
3048
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMTIME,
3049
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3050
56
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3051
56
        GIR_EraseFromParent, /*InsnID*/0,
3052
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3053
56
        // GIR_Coverage, 527,
3054
56
        GIR_Done,
3055
56
      // Label 209: @7061
3056
56
      GIM_Try, /*On fail goto*//*Label 210*/ 7093, // Rule ID 532 //
3057
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
3058
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_memrealtime,
3059
56
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
3060
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64_XEXECRegClassID,
3061
56
        // (intrinsic_w_chain:{ *:[i64] } 1009:{ *:[iPTR] })  =>  (S_MEMREALTIME:{ *:[i64] })
3062
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMREALTIME,
3063
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3064
56
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3065
56
        GIR_EraseFromParent, /*InsnID*/0,
3066
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3067
56
        // GIR_Coverage, 532,
3068
56
        GIR_Done,
3069
56
      // Label 210: @7093
3070
56
      GIM_Try, /*On fail goto*//*Label 211*/ 7121, // Rule ID 680 //
3071
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3072
56
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_end_cf,
3073
56
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3074
56
        // (intrinsic_void 477:{ *:[iPTR] }, i64:{ *:[i64] }:$saved)  =>  (SI_END_CF i64:{ *:[i64] }:$saved)
3075
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_END_CF,
3076
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // saved
3077
56
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
3078
56
        GIR_EraseFromParent, /*InsnID*/0,
3079
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3080
56
        // GIR_Coverage, 680,
3081
56
        GIR_Done,
3082
56
      // Label 211: @7121
3083
56
      GIM_Reject,
3084
56
    // Label 208: @7122
3085
56
    GIM_Reject,
3086
56
    // Label 9: @7123
3087
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 214*/ 7179,
3088
56
    /*GILLT_s16*//*Label 212*/ 7131,
3089
56
    /*GILLT_s32*//*Label 213*/ 7155,
3090
56
    // Label 212: @7131
3091
56
    GIM_Try, /*On fail goto*//*Label 215*/ 7154, // Rule ID 837 //
3092
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3093
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3094
56
      // MIs[0] Operand 1
3095
56
      // No operand predicates
3096
56
      // (imm:{ *:[i16] }):$imm  =>  (S_MOV_B32:{ *:[i16] } (imm:{ *:[i16] }):$imm)
3097
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
3098
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3099
56
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
3100
56
      GIR_EraseFromParent, /*InsnID*/0,
3101
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3102
56
      // GIR_Coverage, 837,
3103
56
      GIR_Done,
3104
56
    // Label 215: @7154
3105
56
    GIM_Reject,
3106
56
    // Label 213: @7155
3107
56
    GIM_Try, /*On fail goto*//*Label 216*/ 7178, // Rule ID 1721 //
3108
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3109
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3110
56
      // MIs[0] Operand 1
3111
56
      // No operand predicates
3112
56
      // (imm:{ *:[i32] }):$imm  =>  (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
3113
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
3114
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3115
56
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
3116
56
      GIR_EraseFromParent, /*InsnID*/0,
3117
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3118
56
      // GIR_Coverage, 1721,
3119
56
      GIR_Done,
3120
56
    // Label 216: @7178
3121
56
    GIM_Reject,
3122
56
    // Label 214: @7179
3123
56
    GIM_Reject,
3124
56
    // Label 10: @7180
3125
56
    GIM_Try, /*On fail goto*//*Label 217*/ 7210, // Rule ID 443 //
3126
56
      GIM_CheckFeatures, GIFBS_isSICI,
3127
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3128
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3129
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3130
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3131
56
      // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3132
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_LSHL_B32_e64,
3133
56
      GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
3134
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3135
56
      // GIR_Coverage, 443,
3136
56
      GIR_Done,
3137
56
    // Label 217: @7210
3138
56
    GIM_Reject,
3139
56
    // Label 11: @7211
3140
56
    GIM_Try, /*On fail goto*//*Label 218*/ 7241, // Rule ID 439 //
3141
56
      GIM_CheckFeatures, GIFBS_isSICI,
3142
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3143
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3144
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3145
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3146
56
      // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3147
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_LSHR_B32_e64,
3148
56
      GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
3149
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3150
56
      // GIR_Coverage, 439,
3151
56
      GIR_Done,
3152
56
    // Label 218: @7241
3153
56
    GIM_Reject,
3154
56
    // Label 12: @7242
3155
56
    GIM_Try, /*On fail goto*//*Label 219*/ 7408,
3156
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3157
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3158
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3159
56
      GIM_Try, /*On fail goto*//*Label 220*/ 7363,
3160
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3161
56
        GIM_Try, /*On fail goto*//*Label 221*/ 7295, // Rule ID 1988 //
3162
56
          GIM_CheckFeatures, GIFBS_TruePredicate_isSICI,
3163
56
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
3164
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vsrc0,
3165
56
          // (sra:{ *:[i32] } (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0), VGPR_32:{ *:[i32] }:$src1)  =>  (V_ASHR_I32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3166
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHR_I32_e32,
3167
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3168
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3169
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3170
56
          GIR_EraseFromParent, /*InsnID*/0,
3171
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3172
56
          // GIR_Coverage, 1988,
3173
56
          GIR_Done,
3174
56
        // Label 221: @7295
3175
56
        GIM_Try, /*On fail goto*//*Label 222*/ 7328, // Rule ID 1989 //
3176
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3177
56
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
3178
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
3179
56
          // (sra:{ *:[i32] } VGPR_32:{ *:[i32] }:$src1, (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_ASHRREV_I32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3180
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I32_e32,
3181
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3182
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3183
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3184
56
          GIR_EraseFromParent, /*InsnID*/0,
3185
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3186
56
          // GIR_Coverage, 1989,
3187
56
          GIR_Done,
3188
56
        // Label 222: @7328
3189
56
        GIM_Try, /*On fail goto*//*Label 223*/ 7362, // Rule ID 1990 //
3190
56
          GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3191
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vcsrc,
3192
56
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vcsrc,
3193
56
          // (sra:{ *:[i32] } (sd_vcsrc:{ *:[i32] } i32:{ *:[i32] }:$src0), (sd_vcsrc:{ *:[i32] } i32:{ *:[i32] }:$src1))  =>  (V_ASHRREV_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)
3194
56
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I32_e64,
3195
56
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3196
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3197
56
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3198
56
          GIR_EraseFromParent, /*InsnID*/0,
3199
56
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3200
56
          // GIR_Coverage, 1990,
3201
56
          GIR_Done,
3202
56
        // Label 223: @7362
3203
56
        GIM_Reject,
3204
56
      // Label 220: @7363
3205
56
      GIM_Try, /*On fail goto*//*Label 224*/ 7389, // Rule ID 1987 //
3206
56
        GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3207
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
3208
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
3209
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
3210
56
        // (sra:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)  =>  (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3211
56
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ASHR_I32,
3212
56
        GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
3213
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3214
56
        // GIR_Coverage, 1987,
3215
56
        GIR_Done,
3216
56
      // Label 224: @7389
3217
56
      GIM_Try, /*On fail goto*//*Label 225*/ 7407, // Rule ID 441 //
3218
56
        GIM_CheckFeatures, GIFBS_isSICI,
3219
56
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3220
56
        // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
3221
56
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_ASHR_I32_e64,
3222
56
        GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
3223
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3224
56
        // GIR_Coverage, 441,
3225
56
        GIR_Done,
3226
56
      // Label 225: @7407
3227
56
      GIM_Reject,
3228
56
    // Label 219: @7408
3229
56
    GIM_Reject,
3230
56
    // Label 13: @7409
3231
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 229*/ 7754,
3232
56
    /*GILLT_s16*//*Label 226*/ 7418,
3233
56
    /*GILLT_s32*//*Label 227*/ 7530,
3234
56
    /*GILLT_s64*//*Label 228*/ 7642,
3235
56
    // Label 226: @7418
3236
56
    GIM_Try, /*On fail goto*//*Label 230*/ 7529,
3237
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3238
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3239
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3240
56
      GIM_Try, /*On fail goto*//*Label 231*/ 7480, // Rule ID 445 //
3241
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3242
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3243
56
        // (fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3244
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
3245
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3246
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3247
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3248
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3249
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3250
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3251
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3252
56
        GIR_EraseFromParent, /*InsnID*/0,
3253
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3254
56
        // GIR_Coverage, 445,
3255
56
        GIR_Done,
3256
56
      // Label 231: @7480
3257
56
      GIM_Try, /*On fail goto*//*Label 232*/ 7528, // Rule ID 2008 //
3258
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3259
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3260
56
        // (fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3261
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
3262
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3263
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3264
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3265
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3266
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3267
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3268
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3269
56
        GIR_EraseFromParent, /*InsnID*/0,
3270
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3271
56
        // GIR_Coverage, 2008,
3272
56
        GIR_Done,
3273
56
      // Label 232: @7528
3274
56
      GIM_Reject,
3275
56
    // Label 230: @7529
3276
56
    GIM_Reject,
3277
56
    // Label 227: @7530
3278
56
    GIM_Try, /*On fail goto*//*Label 233*/ 7641,
3279
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3280
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3281
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3282
56
      GIM_Try, /*On fail goto*//*Label 234*/ 7592, // Rule ID 396 //
3283
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3284
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3285
56
        // (fadd:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3286
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
3287
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3288
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3289
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3290
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3291
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3292
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3293
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3294
56
        GIR_EraseFromParent, /*InsnID*/0,
3295
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3296
56
        // GIR_Coverage, 396,
3297
56
        GIR_Done,
3298
56
      // Label 234: @7592
3299
56
      GIM_Try, /*On fail goto*//*Label 235*/ 7640, // Rule ID 2001 //
3300
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3301
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3302
56
        // (fadd:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3303
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
3304
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3305
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3306
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3307
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3308
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3309
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3310
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3311
56
        GIR_EraseFromParent, /*InsnID*/0,
3312
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3313
56
        // GIR_Coverage, 2001,
3314
56
        GIR_Done,
3315
56
      // Label 235: @7640
3316
56
      GIM_Reject,
3317
56
    // Label 233: @7641
3318
56
    GIM_Reject,
3319
56
    // Label 228: @7642
3320
56
    GIM_Try, /*On fail goto*//*Label 236*/ 7753,
3321
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3322
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3323
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3324
56
      GIM_Try, /*On fail goto*//*Label 237*/ 7704, // Rule ID 456 //
3325
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3326
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3327
56
        // (fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3328
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
3329
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3330
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3331
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3332
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3333
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3334
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3335
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3336
56
        GIR_EraseFromParent, /*InsnID*/0,
3337
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3338
56
        // GIR_Coverage, 456,
3339
56
        GIR_Done,
3340
56
      // Label 237: @7704
3341
56
      GIM_Try, /*On fail goto*//*Label 238*/ 7752, // Rule ID 2014 //
3342
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3343
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3344
56
        // (fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3345
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
3346
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3347
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3348
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3349
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3350
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3351
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3352
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3353
56
        GIR_EraseFromParent, /*InsnID*/0,
3354
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3355
56
        // GIR_Coverage, 2014,
3356
56
        GIR_Done,
3357
56
      // Label 238: @7752
3358
56
      GIM_Reject,
3359
56
    // Label 236: @7753
3360
56
    GIM_Reject,
3361
56
    // Label 229: @7754
3362
56
    GIM_Reject,
3363
56
    // Label 14: @7755
3364
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 241*/ 7885,
3365
56
    /*GILLT_s16*//*Label 239*/ 7763,
3366
56
    /*GILLT_s32*//*Label 240*/ 7824,
3367
56
    // Label 239: @7763
3368
56
    GIM_Try, /*On fail goto*//*Label 242*/ 7823, // Rule ID 446 //
3369
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3370
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3371
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3372
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3373
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3374
56
      // (fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3375
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F16_e64,
3376
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3377
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3378
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3379
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3380
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3381
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3382
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3383
56
      GIR_EraseFromParent, /*InsnID*/0,
3384
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3385
56
      // GIR_Coverage, 446,
3386
56
      GIR_Done,
3387
56
    // Label 242: @7823
3388
56
    GIM_Reject,
3389
56
    // Label 240: @7824
3390
56
    GIM_Try, /*On fail goto*//*Label 243*/ 7884, // Rule ID 397 //
3391
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3392
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3393
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3394
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3395
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3396
56
      // (fsub:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3397
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F32_e64,
3398
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3399
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3400
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3401
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3402
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3403
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3404
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3405
56
      GIR_EraseFromParent, /*InsnID*/0,
3406
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3407
56
      // GIR_Coverage, 397,
3408
56
      GIR_Done,
3409
56
    // Label 243: @7884
3410
56
    GIM_Reject,
3411
56
    // Label 241: @7885
3412
56
    GIM_Reject,
3413
56
    // Label 15: @7886
3414
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 247*/ 8231,
3415
56
    /*GILLT_s16*//*Label 244*/ 7895,
3416
56
    /*GILLT_s32*//*Label 245*/ 8007,
3417
56
    /*GILLT_s64*//*Label 246*/ 8119,
3418
56
    // Label 244: @7895
3419
56
    GIM_Try, /*On fail goto*//*Label 248*/ 8006,
3420
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3421
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3422
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3423
56
      GIM_Try, /*On fail goto*//*Label 249*/ 7957, // Rule ID 447 //
3424
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3425
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3426
56
        // (fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3427
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
3428
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3429
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3430
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3431
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3432
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3433
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3434
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3435
56
        GIR_EraseFromParent, /*InsnID*/0,
3436
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3437
56
        // GIR_Coverage, 447,
3438
56
        GIR_Done,
3439
56
      // Label 249: @7957
3440
56
      GIM_Try, /*On fail goto*//*Label 250*/ 8005, // Rule ID 2009 //
3441
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3442
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3443
56
        // (fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3444
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
3445
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3446
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3447
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3448
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3449
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3450
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3451
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3452
56
        GIR_EraseFromParent, /*InsnID*/0,
3453
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3454
56
        // GIR_Coverage, 2009,
3455
56
        GIR_Done,
3456
56
      // Label 250: @8005
3457
56
      GIM_Reject,
3458
56
    // Label 248: @8006
3459
56
    GIM_Reject,
3460
56
    // Label 245: @8007
3461
56
    GIM_Try, /*On fail goto*//*Label 251*/ 8118,
3462
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3463
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3464
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3465
56
      GIM_Try, /*On fail goto*//*Label 252*/ 8069, // Rule ID 399 //
3466
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3467
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3468
56
        // (fmul:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3469
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
3470
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3471
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3472
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3473
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3474
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3475
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3476
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3477
56
        GIR_EraseFromParent, /*InsnID*/0,
3478
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3479
56
        // GIR_Coverage, 399,
3480
56
        GIR_Done,
3481
56
      // Label 252: @8069
3482
56
      GIM_Try, /*On fail goto*//*Label 253*/ 8117, // Rule ID 2003 //
3483
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3484
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3485
56
        // (fmul:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3486
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
3487
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3488
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3489
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3490
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3491
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3492
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3493
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3494
56
        GIR_EraseFromParent, /*InsnID*/0,
3495
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3496
56
        // GIR_Coverage, 2003,
3497
56
        GIR_Done,
3498
56
      // Label 253: @8117
3499
56
      GIM_Reject,
3500
56
    // Label 251: @8118
3501
56
    GIM_Reject,
3502
56
    // Label 246: @8119
3503
56
    GIM_Try, /*On fail goto*//*Label 254*/ 8230,
3504
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3505
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3506
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3507
56
      GIM_Try, /*On fail goto*//*Label 255*/ 8181, // Rule ID 457 //
3508
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3509
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3510
56
        // (fmul:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3511
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
3512
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3513
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3514
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3515
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3516
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3517
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3518
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3519
56
        GIR_EraseFromParent, /*InsnID*/0,
3520
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3521
56
        // GIR_Coverage, 457,
3522
56
        GIR_Done,
3523
56
      // Label 255: @8181
3524
56
      GIM_Try, /*On fail goto*//*Label 256*/ 8229, // Rule ID 2015 //
3525
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3526
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
3527
56
        // (fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3528
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
3529
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3530
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
3531
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
3532
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
3533
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
3534
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
3535
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
3536
56
        GIR_EraseFromParent, /*InsnID*/0,
3537
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3538
56
        // GIR_Coverage, 2015,
3539
56
        GIR_Done,
3540
56
      // Label 256: @8229
3541
56
      GIM_Reject,
3542
56
    // Label 254: @8230
3543
56
    GIM_Reject,
3544
56
    // Label 247: @8231
3545
56
    GIM_Reject,
3546
56
    // Label 16: @8232
3547
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 260*/ 8477,
3548
56
    /*GILLT_s16*//*Label 257*/ 8241,
3549
56
    /*GILLT_s32*//*Label 258*/ 8321,
3550
56
    /*GILLT_s64*//*Label 259*/ 8399,
3551
56
    // Label 257: @8241
3552
56
    GIM_Try, /*On fail goto*//*Label 261*/ 8320, // Rule ID 494 //
3553
56
      GIM_CheckFeatures, GIFBS_Has16BitInsts_isVIOnly,
3554
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3555
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3556
56
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
3557
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3558
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3559
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3560
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3561
56
      // (fma:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F16:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3562
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F16,
3563
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3564
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3565
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3566
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3567
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3568
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3569
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3570
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3571
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3572
56
      GIR_EraseFromParent, /*InsnID*/0,
3573
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3574
56
      // GIR_Coverage, 494,
3575
56
      GIR_Done,
3576
56
    // Label 261: @8320
3577
56
    GIM_Reject,
3578
56
    // Label 258: @8321
3579
56
    GIM_Try, /*On fail goto*//*Label 262*/ 8398, // Rule ID 453 //
3580
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3581
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3582
56
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
3583
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3584
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3585
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3586
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3587
56
      // (fma:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3588
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F32,
3589
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3590
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3591
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3592
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3593
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3594
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3595
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3596
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3597
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3598
56
      GIR_EraseFromParent, /*InsnID*/0,
3599
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3600
56
      // GIR_Coverage, 453,
3601
56
      GIR_Done,
3602
56
    // Label 262: @8398
3603
56
    GIM_Reject,
3604
56
    // Label 259: @8399
3605
56
    GIM_Try, /*On fail goto*//*Label 263*/ 8476, // Rule ID 455 //
3606
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3607
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3608
56
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
3609
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3610
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3611
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
3612
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
3613
56
      // (fma:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3614
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F64,
3615
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3616
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3617
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3618
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
3619
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
3620
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
3621
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
3622
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3623
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3624
56
      GIR_EraseFromParent, /*InsnID*/0,
3625
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3626
56
      // GIR_Coverage, 455,
3627
56
      GIR_Done,
3628
56
    // Label 263: @8476
3629
56
    GIM_Reject,
3630
56
    // Label 260: @8477
3631
56
    GIM_Reject,
3632
56
    // Label 17: @8478
3633
56
    GIM_Try, /*On fail goto*//*Label 264*/ 8550, // Rule ID 1729 //
3634
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3635
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
3636
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3637
56
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3638
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3639
56
      // (fpow:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)  =>  (V_EXP_F32_e32:{ *:[f32] } (V_MUL_LEGACY_F32_e32:{ *:[i16] } f32:{ *:[f32] }:$src1, (V_LOG_F32_e32:{ *:[i16] } f32:{ *:[f32] }:$src0)))
3640
56
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
3641
56
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
3642
56
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/AMDGPU::V_LOG_F32_e32,
3643
56
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3644
56
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src0
3645
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3646
56
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_MUL_LEGACY_F32_e32,
3647
56
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3648
56
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src1
3649
56
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3650
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3651
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e32,
3652
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3653
56
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3654
56
      GIR_EraseFromParent, /*InsnID*/0,
3655
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3656
56
      // GIR_Coverage, 1729,
3657
56
      GIR_Done,
3658
56
    // Label 264: @8550
3659
56
    GIM_Reject,
3660
56
    // Label 18: @8551
3661
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 267*/ 8647,
3662
56
    /*GILLT_s16*//*Label 265*/ 8559,
3663
56
    /*GILLT_s32*//*Label 266*/ 8603,
3664
56
    // Label 265: @8559
3665
56
    GIM_Try, /*On fail goto*//*Label 268*/ 8602, // Rule ID 386 //
3666
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3667
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3668
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3669
56
      // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3670
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F16_e64,
3671
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3672
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3673
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3674
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3675
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3676
56
      GIR_EraseFromParent, /*InsnID*/0,
3677
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3678
56
      // GIR_Coverage, 386,
3679
56
      GIR_Done,
3680
56
    // Label 268: @8602
3681
56
    GIM_Reject,
3682
56
    // Label 266: @8603
3683
56
    GIM_Try, /*On fail goto*//*Label 269*/ 8646, // Rule ID 353 //
3684
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3685
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3686
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3687
56
      // (fexp2:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3688
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e64,
3689
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3690
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3691
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3692
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3693
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3694
56
      GIR_EraseFromParent, /*InsnID*/0,
3695
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3696
56
      // GIR_Coverage, 353,
3697
56
      GIR_Done,
3698
56
    // Label 269: @8646
3699
56
    GIM_Reject,
3700
56
    // Label 267: @8647
3701
56
    GIM_Reject,
3702
56
    // Label 19: @8648
3703
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 272*/ 8744,
3704
56
    /*GILLT_s16*//*Label 270*/ 8656,
3705
56
    /*GILLT_s32*//*Label 271*/ 8700,
3706
56
    // Label 270: @8656
3707
56
    GIM_Try, /*On fail goto*//*Label 273*/ 8699, // Rule ID 385 //
3708
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3709
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3710
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3711
56
      // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3712
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F16_e64,
3713
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3714
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3715
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3716
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3717
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3718
56
      GIR_EraseFromParent, /*InsnID*/0,
3719
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3720
56
      // GIR_Coverage, 385,
3721
56
      GIR_Done,
3722
56
    // Label 273: @8699
3723
56
    GIM_Reject,
3724
56
    // Label 271: @8700
3725
56
    GIM_Try, /*On fail goto*//*Label 274*/ 8743, // Rule ID 354 //
3726
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3727
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3728
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3729
56
      // (flog2:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3730
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F32_e64,
3731
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3732
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3733
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3734
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3735
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3736
56
      GIR_EraseFromParent, /*InsnID*/0,
3737
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3738
56
      // GIR_Coverage, 354,
3739
56
      GIR_Done,
3740
56
    // Label 274: @8743
3741
56
    GIM_Reject,
3742
56
    // Label 272: @8744
3743
56
    GIM_Reject,
3744
56
    // Label 20: @8745
3745
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 277*/ 8841,
3746
56
    /*GILLT_s32*//*Label 275*/ 8753,
3747
56
    /*GILLT_s64*//*Label 276*/ 8797,
3748
56
    // Label 275: @8753
3749
56
    GIM_Try, /*On fail goto*//*Label 278*/ 8796, // Rule ID 337 //
3750
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3751
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3752
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3753
56
      // (fpextend:{ *:[f32] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3754
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F16_e64,
3755
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3756
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3757
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3758
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3759
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3760
56
      GIR_EraseFromParent, /*InsnID*/0,
3761
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3762
56
      // GIR_Coverage, 337,
3763
56
      GIR_Done,
3764
56
    // Label 278: @8796
3765
56
    GIM_Reject,
3766
56
    // Label 276: @8797
3767
56
    GIM_Try, /*On fail goto*//*Label 279*/ 8840, // Rule ID 341 //
3768
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3769
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
3770
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3771
56
      // (fpextend:{ *:[f64] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_F32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3772
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_F32_e64,
3773
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3774
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3775
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3776
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3777
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3778
56
      GIR_EraseFromParent, /*InsnID*/0,
3779
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3780
56
      // GIR_Coverage, 341,
3781
56
      GIR_Done,
3782
56
    // Label 279: @8840
3783
56
    GIM_Reject,
3784
56
    // Label 277: @8841
3785
56
    GIM_Reject,
3786
56
    // Label 21: @8842
3787
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 282*/ 8938,
3788
56
    /*GILLT_s16*//*Label 280*/ 8850,
3789
56
    /*GILLT_s32*//*Label 281*/ 8894,
3790
56
    // Label 280: @8850
3791
56
    GIM_Try, /*On fail goto*//*Label 283*/ 8893, // Rule ID 336 //
3792
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3793
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3794
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3795
56
      // (fpround:{ *:[f16] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_F32_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3796
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_F32_e64,
3797
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3798
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3799
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3800
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3801
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3802
56
      GIR_EraseFromParent, /*InsnID*/0,
3803
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3804
56
      // GIR_Coverage, 336,
3805
56
      GIR_Done,
3806
56
    // Label 283: @8893
3807
56
    GIM_Reject,
3808
56
    // Label 281: @8894
3809
56
    GIM_Try, /*On fail goto*//*Label 284*/ 8937, // Rule ID 340 //
3810
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3811
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3812
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3813
56
      // (fpround:{ *:[f32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F64_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3814
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F64_e64,
3815
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3816
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3817
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3818
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3819
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3820
56
      GIR_EraseFromParent, /*InsnID*/0,
3821
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3822
56
      // GIR_Coverage, 340,
3823
56
      GIR_Done,
3824
56
    // Label 284: @8937
3825
56
    GIM_Reject,
3826
56
    // Label 282: @8938
3827
56
    GIM_Reject,
3828
56
    // Label 22: @8939
3829
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 288*/ 9172,
3830
56
    /*GILLT_s1*//*Label 285*/ 8948,
3831
56
    /*GILLT_s16*//*Label 286*/ 9041,
3832
56
    /*GILLT_s32*//*Label 287*/ 9085,
3833
56
    // Label 285: @8948
3834
56
    GIM_Try, /*On fail goto*//*Label 289*/ 8994, // Rule ID 1771 //
3835
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3836
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3837
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3838
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3839
56
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 3212836864:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
3840
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
3841
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3842
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3843
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/3212836864,
3844
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3845
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3846
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3847
56
      GIR_EraseFromParent, /*InsnID*/0,
3848
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3849
56
      // GIR_Coverage, 1771,
3850
56
      GIR_Done,
3851
56
    // Label 289: @8994
3852
56
    GIM_Try, /*On fail goto*//*Label 290*/ 9040, // Rule ID 1773 //
3853
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3854
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3855
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3856
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3857
56
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, -4616189618054758400:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
3858
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
3859
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3860
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3861
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/-4616189618054758400,
3862
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3863
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3864
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3865
56
      GIR_EraseFromParent, /*InsnID*/0,
3866
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3867
56
      // GIR_Coverage, 1773,
3868
56
      GIR_Done,
3869
56
    // Label 290: @9040
3870
56
    GIM_Reject,
3871
56
    // Label 286: @9041
3872
56
    GIM_Try, /*On fail goto*//*Label 291*/ 9084, // Rule ID 381 //
3873
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3874
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3875
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3876
56
      // (fp_to_sint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3877
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I16_F16_e64,
3878
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3879
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3880
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3881
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3882
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3883
56
      GIR_EraseFromParent, /*InsnID*/0,
3884
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3885
56
      // GIR_Coverage, 381,
3886
56
      GIR_Done,
3887
56
    // Label 291: @9084
3888
56
    GIM_Reject,
3889
56
    // Label 287: @9085
3890
56
    GIM_Try, /*On fail goto*//*Label 292*/ 9128, // Rule ID 330 //
3891
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3892
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3893
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3894
56
      // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3895
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F64_e64,
3896
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3897
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3898
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3899
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3900
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3901
56
      GIR_EraseFromParent, /*InsnID*/0,
3902
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3903
56
      // GIR_Coverage, 330,
3904
56
      GIR_Done,
3905
56
    // Label 292: @9128
3906
56
    GIM_Try, /*On fail goto*//*Label 293*/ 9171, // Rule ID 335 //
3907
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3908
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3909
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3910
56
      // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3911
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F32_e64,
3912
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3913
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3914
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3915
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3916
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3917
56
      GIR_EraseFromParent, /*InsnID*/0,
3918
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3919
56
      // GIR_Coverage, 335,
3920
56
      GIR_Done,
3921
56
    // Label 293: @9171
3922
56
    GIM_Reject,
3923
56
    // Label 288: @9172
3924
56
    GIM_Reject,
3925
56
    // Label 23: @9173
3926
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 297*/ 9406,
3927
56
    /*GILLT_s1*//*Label 294*/ 9182,
3928
56
    /*GILLT_s16*//*Label 295*/ 9275,
3929
56
    /*GILLT_s32*//*Label 296*/ 9319,
3930
56
    // Label 294: @9182
3931
56
    GIM_Try, /*On fail goto*//*Label 298*/ 9228, // Rule ID 1770 //
3932
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3933
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3934
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3935
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3936
56
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 1065353216:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
3937
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
3938
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3939
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3940
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/1065353216,
3941
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3942
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3943
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3944
56
      GIR_EraseFromParent, /*InsnID*/0,
3945
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3946
56
      // GIR_Coverage, 1770,
3947
56
      GIR_Done,
3948
56
    // Label 298: @9228
3949
56
    GIM_Try, /*On fail goto*//*Label 299*/ 9274, // Rule ID 1772 //
3950
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
3951
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3952
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
3953
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
3954
56
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, 4607182418800017408:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
3955
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
3956
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
3957
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3958
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/4607182418800017408,
3959
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3960
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3961
56
      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3962
56
      GIR_EraseFromParent, /*InsnID*/0,
3963
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3964
56
      // GIR_Coverage, 1772,
3965
56
      GIR_Done,
3966
56
    // Label 299: @9274
3967
56
    GIM_Reject,
3968
56
    // Label 295: @9275
3969
56
    GIM_Try, /*On fail goto*//*Label 300*/ 9318, // Rule ID 380 //
3970
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3971
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3972
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3973
56
      // (fp_to_uint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3974
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U16_F16_e64,
3975
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3976
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3977
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3978
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3979
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3980
56
      GIR_EraseFromParent, /*InsnID*/0,
3981
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3982
56
      // GIR_Coverage, 380,
3983
56
      GIR_Done,
3984
56
    // Label 300: @9318
3985
56
    GIM_Reject,
3986
56
    // Label 296: @9319
3987
56
    GIM_Try, /*On fail goto*//*Label 301*/ 9362, // Rule ID 334 //
3988
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3989
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
3990
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
3991
56
      // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
3992
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F32_e64,
3993
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
3994
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
3995
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
3996
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
3997
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
3998
56
      GIR_EraseFromParent, /*InsnID*/0,
3999
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4000
56
      // GIR_Coverage, 334,
4001
56
      GIR_Done,
4002
56
    // Label 301: @9362
4003
56
    GIM_Try, /*On fail goto*//*Label 302*/ 9405, // Rule ID 346 //
4004
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4005
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4006
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4007
56
      // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4008
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F64_e64,
4009
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4010
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4011
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4012
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4013
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4014
56
      GIR_EraseFromParent, /*InsnID*/0,
4015
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4016
56
      // GIR_Coverage, 346,
4017
56
      GIR_Done,
4018
56
    // Label 302: @9405
4019
56
    GIM_Reject,
4020
56
    // Label 297: @9406
4021
56
    GIM_Reject,
4022
56
    // Label 24: @9407
4023
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 306*/ 9536,
4024
56
    /*GILLT_s16*//*Label 303*/ 9416,
4025
56
    /*GILLT_s32*//*Label 304*/ 9456,
4026
56
    /*GILLT_s64*//*Label 305*/ 9496,
4027
56
    // Label 303: @9416
4028
56
    GIM_Try, /*On fail goto*//*Label 307*/ 9455, // Rule ID 379 //
4029
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4030
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4031
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4032
56
      // (sint_to_fp:{ *:[f16] } (VOP3OMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_I16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4033
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_I16_e64,
4034
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4035
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4036
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4037
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4038
56
      GIR_EraseFromParent, /*InsnID*/0,
4039
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4040
56
      // GIR_Coverage, 379,
4041
56
      GIR_Done,
4042
56
    // Label 307: @9455
4043
56
    GIM_Reject,
4044
56
    // Label 304: @9456
4045
56
    GIM_Try, /*On fail goto*//*Label 308*/ 9495, // Rule ID 332 //
4046
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4047
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4048
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4049
56
      // (sint_to_fp:{ *:[f32] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_I32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4050
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_I32_e64,
4051
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4052
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4053
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4054
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4055
56
      GIR_EraseFromParent, /*InsnID*/0,
4056
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4057
56
      // GIR_Coverage, 332,
4058
56
      GIR_Done,
4059
56
    // Label 308: @9495
4060
56
    GIM_Reject,
4061
56
    // Label 305: @9496
4062
56
    GIM_Try, /*On fail goto*//*Label 309*/ 9535, // Rule ID 331 //
4063
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4064
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4065
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4066
56
      // (sint_to_fp:{ *:[f64] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_I32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4067
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_I32_e64,
4068
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4069
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4070
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4071
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4072
56
      GIR_EraseFromParent, /*InsnID*/0,
4073
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4074
56
      // GIR_Coverage, 331,
4075
56
      GIR_Done,
4076
56
    // Label 309: @9535
4077
56
    GIM_Reject,
4078
56
    // Label 306: @9536
4079
56
    GIM_Reject,
4080
56
    // Label 25: @9537
4081
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 313*/ 9666,
4082
56
    /*GILLT_s16*//*Label 310*/ 9546,
4083
56
    /*GILLT_s32*//*Label 311*/ 9586,
4084
56
    /*GILLT_s64*//*Label 312*/ 9626,
4085
56
    // Label 310: @9546
4086
56
    GIM_Try, /*On fail goto*//*Label 314*/ 9585, // Rule ID 378 //
4087
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4088
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4089
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4090
56
      // (uint_to_fp:{ *:[f16] } (VOP3OMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_U16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4091
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_U16_e64,
4092
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4093
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4094
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4095
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4096
56
      GIR_EraseFromParent, /*InsnID*/0,
4097
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4098
56
      // GIR_Coverage, 378,
4099
56
      GIR_Done,
4100
56
    // Label 314: @9585
4101
56
    GIM_Reject,
4102
56
    // Label 311: @9586
4103
56
    GIM_Try, /*On fail goto*//*Label 315*/ 9625, // Rule ID 333 //
4104
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4105
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4106
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4107
56
      // (uint_to_fp:{ *:[f32] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_U32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4108
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_U32_e64,
4109
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4110
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4111
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4112
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4113
56
      GIR_EraseFromParent, /*InsnID*/0,
4114
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4115
56
      // GIR_Coverage, 333,
4116
56
      GIR_Done,
4117
56
    // Label 315: @9625
4118
56
    GIM_Reject,
4119
56
    // Label 312: @9626
4120
56
    GIM_Try, /*On fail goto*//*Label 316*/ 9665, // Rule ID 347 //
4121
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4122
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4123
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
4124
56
      // (uint_to_fp:{ *:[f64] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_U32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4125
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_U32_e64,
4126
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4127
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4128
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
4129
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
4130
56
      GIR_EraseFromParent, /*InsnID*/0,
4131
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4132
56
      // GIR_Coverage, 347,
4133
56
      GIR_Done,
4134
56
    // Label 316: @9665
4135
56
    GIM_Reject,
4136
56
    // Label 313: @9666
4137
56
    GIM_Reject,
4138
56
    // Label 26: @9667
4139
56
    GIM_Try, /*On fail goto*//*Label 317*/ 9681, // Rule ID 60 //
4140
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
4141
56
      // MIs[0] simm16
4142
56
      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
4143
56
      // (br (bb:{ *:[Other] }):$simm16)  =>  (S_BRANCH (bb:{ *:[Other] }):$simm16)
4144
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_BRANCH,
4145
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4146
56
      // GIR_Coverage, 60,
4147
56
      GIR_Done,
4148
56
    // Label 317: @9681
4149
56
    GIM_Reject,
4150
56
    // Label 27: @9682
4151
56
    GIM_Try, /*On fail goto*//*Label 318*/ 9708, // Rule ID 4 //
4152
56
      GIM_CheckFeatures, GIFBS_TruePredicate_TruePredicate,
4153
56
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4154
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4155
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
4156
56
      // (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0)  =>  (S_BCNT1_I32_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
4157
56
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_BCNT1_I32_B32,
4158
56
      GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
4159
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4160
56
      // GIR_Coverage, 4,
4161
56
      GIR_Done,
4162
56
    // Label 318: @9708
4163
56
    GIM_Reject,
4164
56
    // Label 28: @9709
4165
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 322*/ 9850,
4166
56
    /*GILLT_s16*//*Label 319*/ 9718,
4167
56
    /*GILLT_s32*//*Label 320*/ 9762,
4168
56
    /*GILLT_s64*//*Label 321*/ 9806,
4169
56
    // Label 319: @9718
4170
56
    GIM_Try, /*On fail goto*//*Label 323*/ 9761, // Rule ID 392 //
4171
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4172
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4173
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4174
56
      // (fceil:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CEIL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4175
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CEIL_F16_e64,
4176
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4177
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4178
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4179
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4180
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4181
56
      GIR_EraseFromParent, /*InsnID*/0,
4182
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4183
56
      // GIR_Coverage, 392,
4184
56
      GIR_Done,
4185
56
    // Label 323: @9761
4186
56
    GIM_Reject,
4187
56
    // Label 320: @9762
4188
56
    GIM_Try, /*On fail goto*//*Label 324*/ 9805, // Rule ID 350 //
4189
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4190
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4191
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4192
56
      // (fceil:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CEIL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4193
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CEIL_F32_e64,
4194
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4195
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4196
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4197
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4198
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4199
56
      GIR_EraseFromParent, /*InsnID*/0,
4200
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4201
56
      // GIR_Coverage, 350,
4202
56
      GIR_Done,
4203
56
    // Label 324: @9805
4204
56
    GIM_Reject,
4205
56
    // Label 321: @9806
4206
56
    GIM_Try, /*On fail goto*//*Label 325*/ 9849, // Rule ID 375 //
4207
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4208
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4209
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4210
56
      // (fceil:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CEIL_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4211
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CEIL_F64_e64,
4212
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4213
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4214
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4215
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4216
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4217
56
      GIR_EraseFromParent, /*InsnID*/0,
4218
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4219
56
      // GIR_Coverage, 375,
4220
56
      GIR_Done,
4221
56
    // Label 325: @9849
4222
56
    GIM_Reject,
4223
56
    // Label 322: @9850
4224
56
    GIM_Reject,
4225
56
    // Label 29: @9851
4226
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 329*/ 9992,
4227
56
    /*GILLT_s16*//*Label 326*/ 9860,
4228
56
    /*GILLT_s32*//*Label 327*/ 9904,
4229
56
    /*GILLT_s64*//*Label 328*/ 9948,
4230
56
    // Label 326: @9860
4231
56
    GIM_Try, /*On fail goto*//*Label 330*/ 9903, // Rule ID 383 //
4232
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4233
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4234
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4235
56
      // (fsqrt:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4236
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SQRT_F16_e64,
4237
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4238
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4239
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4240
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4241
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4242
56
      GIR_EraseFromParent, /*InsnID*/0,
4243
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4244
56
      // GIR_Coverage, 383,
4245
56
      GIR_Done,
4246
56
    // Label 330: @9903
4247
56
    GIM_Reject,
4248
56
    // Label 327: @9904
4249
56
    GIM_Try, /*On fail goto*//*Label 331*/ 9947, // Rule ID 358 //
4250
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4251
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4252
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4253
56
      // (fsqrt:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4254
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SQRT_F32_e64,
4255
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4256
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4257
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4258
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4259
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4260
56
      GIR_EraseFromParent, /*InsnID*/0,
4261
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4262
56
      // GIR_Coverage, 358,
4263
56
      GIR_Done,
4264
56
    // Label 331: @9947
4265
56
    GIM_Reject,
4266
56
    // Label 328: @9948
4267
56
    GIM_Try, /*On fail goto*//*Label 332*/ 9991, // Rule ID 361 //
4268
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4269
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4270
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4271
56
      // (fsqrt:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4272
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SQRT_F64_e64,
4273
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4274
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4275
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4276
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4277
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4278
56
      GIR_EraseFromParent, /*InsnID*/0,
4279
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4280
56
      // GIR_Coverage, 361,
4281
56
      GIR_Done,
4282
56
    // Label 332: @9991
4283
56
    GIM_Reject,
4284
56
    // Label 329: @9992
4285
56
    GIM_Reject,
4286
56
    // Label 30: @9993
4287
56
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 336*/ 10298,
4288
56
    /*GILLT_s16*//*Label 333*/ 10002,
4289
56
    /*GILLT_s32*//*Label 334*/ 10046,
4290
56
    /*GILLT_s64*//*Label 335*/ 10090,
4291
56
    // Label 333: @10002
4292
56
    GIM_Try, /*On fail goto*//*Label 337*/ 10045, // Rule ID 391 //
4293
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4294
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4295
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4296
56
      // (ffloor:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FLOOR_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4297
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FLOOR_F16_e64,
4298
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4299
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4300
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4301
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4302
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4303
56
      GIR_EraseFromParent, /*InsnID*/0,
4304
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4305
56
      // GIR_Coverage, 391,
4306
56
      GIR_Done,
4307
56
    // Label 337: @10045
4308
56
    GIM_Reject,
4309
56
    // Label 334: @10046
4310
56
    GIM_Try, /*On fail goto*//*Label 338*/ 10089, // Rule ID 352 //
4311
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4312
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
4313
56
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4314
56
      // (ffloor:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FLOOR_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4315
56
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FLOOR_F32_e64,
4316
56
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4317
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4318
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4319
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4320
56
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4321
56
      GIR_EraseFromParent, /*InsnID*/0,
4322
56
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4323
56
      // GIR_Coverage, 352,
4324
56
      GIR_Done,
4325
56
    // Label 338: @10089
4326
56
    GIM_Reject,
4327
56
    // Label 335: @10090
4328
56
    GIM_Try, /*On fail goto*//*Label 339*/ 10297,
4329
56
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4330
56
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
4331
56
      GIM_Try, /*On fail goto*//*Label 340*/ 10261, // Rule ID 1819 //
4332
56
        GIM_CheckFeatures, GIFBS_TruePredicate_isSI,
4333
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
4334
56
        // (ffloor:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$x, i32:{ *:[i32] }:$mods))  =>  (V_ADD_F64:{ *:[f64] } ?:{ *:[i32] }:$mods, ?:{ *:[f64] }:$x, 1:{ *:[i32] }, (V_CNDMASK_B64_PSEUDO:{ *:[i64] } (V_MIN_F64:{ *:[i64] } 0:{ *:[i32] }, (V_FRACT_F64_e64:{ *:[i64] } ?:{ *:[i32] }:$mods, ?:{ *:[f64] }:$x, 0:{ *:[i1] }, 0:{ *:[i32] }), 0:{ *:[i32] }, (V_MOV_B64_PSEUDO:{ *:[i64] } 4607182418800017407:{ *:[i64] }), 0:{ *:[i1] }, 0:{ *:[i32] }), ?:{ *:[f64] }:$x, (V_CMP_CLASS_F64_e64:{ *:[i1] } 0:{ *:[i32] }, ?:{ *:[f64] }:$x, 3:{ *:[i32] })), 0:{ *:[i1] }, 0:{ *:[i32] })
4335
56
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
4336
56
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
4337
56
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
4338
56
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
4339
56
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s1,
4340
56
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/AMDGPU::V_CMP_CLASS_F64_e64,
4341
56
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
4342
56
        GIR_AddImm, /*InsnID*/5, /*Imm*/0,
4343
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // x
4344
56
        GIR_AddImm, /*InsnID*/5, /*Imm*/3,
4345
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
4346
56
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/AMDGPU::V_MOV_B64_PSEUDO,
4347
56
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4348
56
        GIR_AddImm, /*InsnID*/4, /*Imm*/4607182418800017407,
4349
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4350
56
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/AMDGPU::V_FRACT_F64_e64,
4351
56
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4352
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // mods
4353
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // x
4354
56
        GIR_AddImm, /*InsnID*/3, /*Imm*/0,
4355
56
        GIR_AddImm, /*InsnID*/3, /*Imm*/0,
4356
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4357
56
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/AMDGPU::V_MIN_F64,
4358
56
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4359
56
        GIR_AddImm, /*InsnID*/2, /*Imm*/0,
4360
56
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4361
56
        GIR_AddImm, /*InsnID*/2, /*Imm*/0,
4362
56
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/3, /*TempRegFlags*/0,
4363
56
        GIR_AddImm, /*InsnID*/2, /*Imm*/0,
4364
56
        GIR_AddImm, /*InsnID*/2, /*Imm*/0,
4365
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4366
56
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_CNDMASK_B64_PSEUDO,
4367
56
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4368
56
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4369
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // x
4370
56
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/4, /*TempRegFlags*/0,
4371
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4372
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
4373
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4374
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // mods
4375
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // x
4376
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
4377
56
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4378
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4379
56
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4380
56
        GIR_EraseFromParent, /*InsnID*/0,
4381
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4382
56
        // GIR_Coverage, 1819,
4383
56
        GIR_Done,
4384
56
      // Label 340: @10261
4385
56
      GIM_Try, /*On fail goto*//*Label 341*/ 10296, // Rule ID 376 //
4386
56
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
4387
56
        // (ffloor:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FLOOR_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
4388
56
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FLOOR_F64_e64,
4389
56
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
4390
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
4391
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
4392
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
4393
56
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
4394
56
        GIR_EraseFromParent, /*InsnID*/0,
4395
56
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4396
56
        // GIR_Coverage, 376,
4397
56
        GIR_Done,
4398
56
      // Label 341: @10296
4399
56
      GIM_Reject,
4400
56
    // Label 339: @10297
4401
56
    GIM_Reject,
4402
56
    // Label 336: @10298
4403
56
    GIM_Reject,
4404
56
    // Label 31: @10299
4405
56
    GIM_Reject,
4406
56
    };
4407
56
  return MatchTable0;
4408
56
}
4409
#endif // ifdef GET_GLOBALISEL_IMPL
4410
#ifdef GET_GLOBALISEL_PREDICATES_DECL
4411
PredicateBitset AvailableModuleFeatures;
4412
mutable PredicateBitset AvailableFunctionFeatures;
4413
56
PredicateBitset getAvailableFeatures() const {
4414
56
  return AvailableModuleFeatures | AvailableFunctionFeatures;
4415
56
}
4416
PredicateBitset
4417
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const;
4418
PredicateBitset
4419
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget,
4420
                                 const MachineFunction *MF) const;
4421
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
4422
#ifdef GET_GLOBALISEL_PREDICATES_INIT
4423
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
4424
AvailableFunctionFeatures()
4425
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT