Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
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9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace AMDGPU {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    CFI_INSTRUCTION = 2,
18
    EH_LABEL  = 3,
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    GC_LABEL  = 4,
20
    ANNOTATION_LABEL  = 5,
21
    KILL  = 6,
22
    EXTRACT_SUBREG  = 7,
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    INSERT_SUBREG = 8,
24
    IMPLICIT_DEF  = 9,
25
    SUBREG_TO_REG = 10,
26
    COPY_TO_REGCLASS  = 11,
27
    DBG_VALUE = 12,
28
    DBG_LABEL = 13,
29
    REG_SEQUENCE  = 14,
30
    COPY  = 15,
31
    BUNDLE  = 16,
32
    LIFETIME_START  = 17,
33
    LIFETIME_END  = 18,
34
    STACKMAP  = 19,
35
    FENTRY_CALL = 20,
36
    PATCHPOINT  = 21,
37
    LOAD_STACK_GUARD  = 22,
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    STATEPOINT  = 23,
39
    LOCAL_ESCAPE  = 24,
40
    FAULTING_OP = 25,
41
    PATCHABLE_OP  = 26,
42
    PATCHABLE_FUNCTION_ENTER  = 27,
43
    PATCHABLE_RET = 28,
44
    PATCHABLE_FUNCTION_EXIT = 29,
45
    PATCHABLE_TAIL_CALL = 30,
46
    PATCHABLE_EVENT_CALL  = 31,
47
    PATCHABLE_TYPED_EVENT_CALL  = 32,
48
    ICALL_BRANCH_FUNNEL = 33,
49
    G_ADD = 34,
50
    G_SUB = 35,
51
    G_MUL = 36,
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    G_SDIV  = 37,
53
    G_UDIV  = 38,
54
    G_SREM  = 39,
55
    G_UREM  = 40,
56
    G_AND = 41,
57
    G_OR  = 42,
58
    G_XOR = 43,
59
    G_IMPLICIT_DEF  = 44,
60
    G_PHI = 45,
61
    G_FRAME_INDEX = 46,
62
    G_GLOBAL_VALUE  = 47,
63
    G_EXTRACT = 48,
64
    G_UNMERGE_VALUES  = 49,
65
    G_INSERT  = 50,
66
    G_MERGE_VALUES  = 51,
67
    G_PTRTOINT  = 52,
68
    G_INTTOPTR  = 53,
69
    G_BITCAST = 54,
70
    G_LOAD  = 55,
71
    G_SEXTLOAD  = 56,
72
    G_ZEXTLOAD  = 57,
73
    G_STORE = 58,
74
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59,
75
    G_ATOMIC_CMPXCHG  = 60,
76
    G_ATOMICRMW_XCHG  = 61,
77
    G_ATOMICRMW_ADD = 62,
78
    G_ATOMICRMW_SUB = 63,
79
    G_ATOMICRMW_AND = 64,
80
    G_ATOMICRMW_NAND  = 65,
81
    G_ATOMICRMW_OR  = 66,
82
    G_ATOMICRMW_XOR = 67,
83
    G_ATOMICRMW_MAX = 68,
84
    G_ATOMICRMW_MIN = 69,
85
    G_ATOMICRMW_UMAX  = 70,
86
    G_ATOMICRMW_UMIN  = 71,
87
    G_BRCOND  = 72,
88
    G_BRINDIRECT  = 73,
89
    G_INTRINSIC = 74,
90
    G_INTRINSIC_W_SIDE_EFFECTS  = 75,
91
    G_ANYEXT  = 76,
92
    G_TRUNC = 77,
93
    G_CONSTANT  = 78,
94
    G_FCONSTANT = 79,
95
    G_VASTART = 80,
96
    G_VAARG = 81,
97
    G_SEXT  = 82,
98
    G_ZEXT  = 83,
99
    G_SHL = 84,
100
    G_LSHR  = 85,
101
    G_ASHR  = 86,
102
    G_ICMP  = 87,
103
    G_FCMP  = 88,
104
    G_SELECT  = 89,
105
    G_UADDE = 90,
106
    G_USUBE = 91,
107
    G_SADDO = 92,
108
    G_SSUBO = 93,
109
    G_UMULO = 94,
110
    G_SMULO = 95,
111
    G_UMULH = 96,
112
    G_SMULH = 97,
113
    G_FADD  = 98,
114
    G_FSUB  = 99,
115
    G_FMUL  = 100,
116
    G_FMA = 101,
117
    G_FDIV  = 102,
118
    G_FREM  = 103,
119
    G_FPOW  = 104,
120
    G_FEXP  = 105,
121
    G_FEXP2 = 106,
122
    G_FLOG  = 107,
123
    G_FLOG2 = 108,
124
    G_FNEG  = 109,
125
    G_FPEXT = 110,
126
    G_FPTRUNC = 111,
127
    G_FPTOSI  = 112,
128
    G_FPTOUI  = 113,
129
    G_SITOFP  = 114,
130
    G_UITOFP  = 115,
131
    G_FABS  = 116,
132
    G_GEP = 117,
133
    G_PTR_MASK  = 118,
134
    G_BR  = 119,
135
    G_INSERT_VECTOR_ELT = 120,
136
    G_EXTRACT_VECTOR_ELT  = 121,
137
    G_SHUFFLE_VECTOR  = 122,
138
    G_BSWAP = 123,
139
    G_ADDRSPACE_CAST  = 124,
140
    ADJCALLSTACKDOWN  = 125,
141
    ADJCALLSTACKUP  = 126,
142
    ATOMIC_FENCE  = 127,
143
    BUFFER_ATOMIC_ADD_ADDR64  = 128,
144
    BUFFER_ATOMIC_ADD_ADDR64_RTN  = 129,
145
    BUFFER_ATOMIC_ADD_BOTHEN  = 130,
146
    BUFFER_ATOMIC_ADD_BOTHEN_RTN  = 131,
147
    BUFFER_ATOMIC_ADD_IDXEN = 132,
148
    BUFFER_ATOMIC_ADD_IDXEN_RTN = 133,
149
    BUFFER_ATOMIC_ADD_OFFEN = 134,
150
    BUFFER_ATOMIC_ADD_OFFEN_RTN = 135,
151
    BUFFER_ATOMIC_ADD_OFFSET  = 136,
152
    BUFFER_ATOMIC_ADD_OFFSET_RTN  = 137,
153
    BUFFER_ATOMIC_ADD_X2_ADDR64 = 138,
154
    BUFFER_ATOMIC_ADD_X2_ADDR64_RTN = 139,
155
    BUFFER_ATOMIC_ADD_X2_BOTHEN = 140,
156
    BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN = 141,
157
    BUFFER_ATOMIC_ADD_X2_IDXEN  = 142,
158
    BUFFER_ATOMIC_ADD_X2_IDXEN_RTN  = 143,
159
    BUFFER_ATOMIC_ADD_X2_OFFEN  = 144,
160
    BUFFER_ATOMIC_ADD_X2_OFFEN_RTN  = 145,
161
    BUFFER_ATOMIC_ADD_X2_OFFSET = 146,
162
    BUFFER_ATOMIC_ADD_X2_OFFSET_RTN = 147,
163
    BUFFER_ATOMIC_AND_ADDR64  = 148,
164
    BUFFER_ATOMIC_AND_ADDR64_RTN  = 149,
165
    BUFFER_ATOMIC_AND_BOTHEN  = 150,
166
    BUFFER_ATOMIC_AND_BOTHEN_RTN  = 151,
167
    BUFFER_ATOMIC_AND_IDXEN = 152,
168
    BUFFER_ATOMIC_AND_IDXEN_RTN = 153,
169
    BUFFER_ATOMIC_AND_OFFEN = 154,
170
    BUFFER_ATOMIC_AND_OFFEN_RTN = 155,
171
    BUFFER_ATOMIC_AND_OFFSET  = 156,
172
    BUFFER_ATOMIC_AND_OFFSET_RTN  = 157,
173
    BUFFER_ATOMIC_AND_X2_ADDR64 = 158,
174
    BUFFER_ATOMIC_AND_X2_ADDR64_RTN = 159,
175
    BUFFER_ATOMIC_AND_X2_BOTHEN = 160,
176
    BUFFER_ATOMIC_AND_X2_BOTHEN_RTN = 161,
177
    BUFFER_ATOMIC_AND_X2_IDXEN  = 162,
178
    BUFFER_ATOMIC_AND_X2_IDXEN_RTN  = 163,
179
    BUFFER_ATOMIC_AND_X2_OFFEN  = 164,
180
    BUFFER_ATOMIC_AND_X2_OFFEN_RTN  = 165,
181
    BUFFER_ATOMIC_AND_X2_OFFSET = 166,
182
    BUFFER_ATOMIC_AND_X2_OFFSET_RTN = 167,
183
    BUFFER_ATOMIC_CMPSWAP_ADDR64  = 168,
184
    BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN  = 169,
185
    BUFFER_ATOMIC_CMPSWAP_BOTHEN  = 170,
186
    BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN  = 171,
187
    BUFFER_ATOMIC_CMPSWAP_IDXEN = 172,
188
    BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN = 173,
189
    BUFFER_ATOMIC_CMPSWAP_OFFEN = 174,
190
    BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN = 175,
191
    BUFFER_ATOMIC_CMPSWAP_OFFSET  = 176,
192
    BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN  = 177,
193
    BUFFER_ATOMIC_CMPSWAP_X2_ADDR64 = 178,
194
    BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN = 179,
195
    BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN = 180,
196
    BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN = 181,
197
    BUFFER_ATOMIC_CMPSWAP_X2_IDXEN  = 182,
198
    BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN  = 183,
199
    BUFFER_ATOMIC_CMPSWAP_X2_OFFEN  = 184,
200
    BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN  = 185,
201
    BUFFER_ATOMIC_CMPSWAP_X2_OFFSET = 186,
202
    BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN = 187,
203
    BUFFER_ATOMIC_DEC_ADDR64  = 188,
204
    BUFFER_ATOMIC_DEC_ADDR64_RTN  = 189,
205
    BUFFER_ATOMIC_DEC_BOTHEN  = 190,
206
    BUFFER_ATOMIC_DEC_BOTHEN_RTN  = 191,
207
    BUFFER_ATOMIC_DEC_IDXEN = 192,
208
    BUFFER_ATOMIC_DEC_IDXEN_RTN = 193,
209
    BUFFER_ATOMIC_DEC_OFFEN = 194,
210
    BUFFER_ATOMIC_DEC_OFFEN_RTN = 195,
211
    BUFFER_ATOMIC_DEC_OFFSET  = 196,
212
    BUFFER_ATOMIC_DEC_OFFSET_RTN  = 197,
213
    BUFFER_ATOMIC_DEC_X2_ADDR64 = 198,
214
    BUFFER_ATOMIC_DEC_X2_ADDR64_RTN = 199,
215
    BUFFER_ATOMIC_DEC_X2_BOTHEN = 200,
216
    BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN = 201,
217
    BUFFER_ATOMIC_DEC_X2_IDXEN  = 202,
218
    BUFFER_ATOMIC_DEC_X2_IDXEN_RTN  = 203,
219
    BUFFER_ATOMIC_DEC_X2_OFFEN  = 204,
220
    BUFFER_ATOMIC_DEC_X2_OFFEN_RTN  = 205,
221
    BUFFER_ATOMIC_DEC_X2_OFFSET = 206,
222
    BUFFER_ATOMIC_DEC_X2_OFFSET_RTN = 207,
223
    BUFFER_ATOMIC_INC_ADDR64  = 208,
224
    BUFFER_ATOMIC_INC_ADDR64_RTN  = 209,
225
    BUFFER_ATOMIC_INC_BOTHEN  = 210,
226
    BUFFER_ATOMIC_INC_BOTHEN_RTN  = 211,
227
    BUFFER_ATOMIC_INC_IDXEN = 212,
228
    BUFFER_ATOMIC_INC_IDXEN_RTN = 213,
229
    BUFFER_ATOMIC_INC_OFFEN = 214,
230
    BUFFER_ATOMIC_INC_OFFEN_RTN = 215,
231
    BUFFER_ATOMIC_INC_OFFSET  = 216,
232
    BUFFER_ATOMIC_INC_OFFSET_RTN  = 217,
233
    BUFFER_ATOMIC_INC_X2_ADDR64 = 218,
234
    BUFFER_ATOMIC_INC_X2_ADDR64_RTN = 219,
235
    BUFFER_ATOMIC_INC_X2_BOTHEN = 220,
236
    BUFFER_ATOMIC_INC_X2_BOTHEN_RTN = 221,
237
    BUFFER_ATOMIC_INC_X2_IDXEN  = 222,
238
    BUFFER_ATOMIC_INC_X2_IDXEN_RTN  = 223,
239
    BUFFER_ATOMIC_INC_X2_OFFEN  = 224,
240
    BUFFER_ATOMIC_INC_X2_OFFEN_RTN  = 225,
241
    BUFFER_ATOMIC_INC_X2_OFFSET = 226,
242
    BUFFER_ATOMIC_INC_X2_OFFSET_RTN = 227,
243
    BUFFER_ATOMIC_OR_ADDR64 = 228,
244
    BUFFER_ATOMIC_OR_ADDR64_RTN = 229,
245
    BUFFER_ATOMIC_OR_BOTHEN = 230,
246
    BUFFER_ATOMIC_OR_BOTHEN_RTN = 231,
247
    BUFFER_ATOMIC_OR_IDXEN  = 232,
248
    BUFFER_ATOMIC_OR_IDXEN_RTN  = 233,
249
    BUFFER_ATOMIC_OR_OFFEN  = 234,
250
    BUFFER_ATOMIC_OR_OFFEN_RTN  = 235,
251
    BUFFER_ATOMIC_OR_OFFSET = 236,
252
    BUFFER_ATOMIC_OR_OFFSET_RTN = 237,
253
    BUFFER_ATOMIC_OR_X2_ADDR64  = 238,
254
    BUFFER_ATOMIC_OR_X2_ADDR64_RTN  = 239,
255
    BUFFER_ATOMIC_OR_X2_BOTHEN  = 240,
256
    BUFFER_ATOMIC_OR_X2_BOTHEN_RTN  = 241,
257
    BUFFER_ATOMIC_OR_X2_IDXEN = 242,
258
    BUFFER_ATOMIC_OR_X2_IDXEN_RTN = 243,
259
    BUFFER_ATOMIC_OR_X2_OFFEN = 244,
260
    BUFFER_ATOMIC_OR_X2_OFFEN_RTN = 245,
261
    BUFFER_ATOMIC_OR_X2_OFFSET  = 246,
262
    BUFFER_ATOMIC_OR_X2_OFFSET_RTN  = 247,
263
    BUFFER_ATOMIC_SMAX_ADDR64 = 248,
264
    BUFFER_ATOMIC_SMAX_ADDR64_RTN = 249,
265
    BUFFER_ATOMIC_SMAX_BOTHEN = 250,
266
    BUFFER_ATOMIC_SMAX_BOTHEN_RTN = 251,
267
    BUFFER_ATOMIC_SMAX_IDXEN  = 252,
268
    BUFFER_ATOMIC_SMAX_IDXEN_RTN  = 253,
269
    BUFFER_ATOMIC_SMAX_OFFEN  = 254,
270
    BUFFER_ATOMIC_SMAX_OFFEN_RTN  = 255,
271
    BUFFER_ATOMIC_SMAX_OFFSET = 256,
272
    BUFFER_ATOMIC_SMAX_OFFSET_RTN = 257,
273
    BUFFER_ATOMIC_SMAX_X2_ADDR64  = 258,
274
    BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN  = 259,
275
    BUFFER_ATOMIC_SMAX_X2_BOTHEN  = 260,
276
    BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN  = 261,
277
    BUFFER_ATOMIC_SMAX_X2_IDXEN = 262,
278
    BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN = 263,
279
    BUFFER_ATOMIC_SMAX_X2_OFFEN = 264,
280
    BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN = 265,
281
    BUFFER_ATOMIC_SMAX_X2_OFFSET  = 266,
282
    BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN  = 267,
283
    BUFFER_ATOMIC_SMIN_ADDR64 = 268,
284
    BUFFER_ATOMIC_SMIN_ADDR64_RTN = 269,
285
    BUFFER_ATOMIC_SMIN_BOTHEN = 270,
286
    BUFFER_ATOMIC_SMIN_BOTHEN_RTN = 271,
287
    BUFFER_ATOMIC_SMIN_IDXEN  = 272,
288
    BUFFER_ATOMIC_SMIN_IDXEN_RTN  = 273,
289
    BUFFER_ATOMIC_SMIN_OFFEN  = 274,
290
    BUFFER_ATOMIC_SMIN_OFFEN_RTN  = 275,
291
    BUFFER_ATOMIC_SMIN_OFFSET = 276,
292
    BUFFER_ATOMIC_SMIN_OFFSET_RTN = 277,
293
    BUFFER_ATOMIC_SMIN_X2_ADDR64  = 278,
294
    BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN  = 279,
295
    BUFFER_ATOMIC_SMIN_X2_BOTHEN  = 280,
296
    BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN  = 281,
297
    BUFFER_ATOMIC_SMIN_X2_IDXEN = 282,
298
    BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN = 283,
299
    BUFFER_ATOMIC_SMIN_X2_OFFEN = 284,
300
    BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN = 285,
301
    BUFFER_ATOMIC_SMIN_X2_OFFSET  = 286,
302
    BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN  = 287,
303
    BUFFER_ATOMIC_SUB_ADDR64  = 288,
304
    BUFFER_ATOMIC_SUB_ADDR64_RTN  = 289,
305
    BUFFER_ATOMIC_SUB_BOTHEN  = 290,
306
    BUFFER_ATOMIC_SUB_BOTHEN_RTN  = 291,
307
    BUFFER_ATOMIC_SUB_IDXEN = 292,
308
    BUFFER_ATOMIC_SUB_IDXEN_RTN = 293,
309
    BUFFER_ATOMIC_SUB_OFFEN = 294,
310
    BUFFER_ATOMIC_SUB_OFFEN_RTN = 295,
311
    BUFFER_ATOMIC_SUB_OFFSET  = 296,
312
    BUFFER_ATOMIC_SUB_OFFSET_RTN  = 297,
313
    BUFFER_ATOMIC_SUB_X2_ADDR64 = 298,
314
    BUFFER_ATOMIC_SUB_X2_ADDR64_RTN = 299,
315
    BUFFER_ATOMIC_SUB_X2_BOTHEN = 300,
316
    BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN = 301,
317
    BUFFER_ATOMIC_SUB_X2_IDXEN  = 302,
318
    BUFFER_ATOMIC_SUB_X2_IDXEN_RTN  = 303,
319
    BUFFER_ATOMIC_SUB_X2_OFFEN  = 304,
320
    BUFFER_ATOMIC_SUB_X2_OFFEN_RTN  = 305,
321
    BUFFER_ATOMIC_SUB_X2_OFFSET = 306,
322
    BUFFER_ATOMIC_SUB_X2_OFFSET_RTN = 307,
323
    BUFFER_ATOMIC_SWAP_ADDR64 = 308,
324
    BUFFER_ATOMIC_SWAP_ADDR64_RTN = 309,
325
    BUFFER_ATOMIC_SWAP_BOTHEN = 310,
326
    BUFFER_ATOMIC_SWAP_BOTHEN_RTN = 311,
327
    BUFFER_ATOMIC_SWAP_IDXEN  = 312,
328
    BUFFER_ATOMIC_SWAP_IDXEN_RTN  = 313,
329
    BUFFER_ATOMIC_SWAP_OFFEN  = 314,
330
    BUFFER_ATOMIC_SWAP_OFFEN_RTN  = 315,
331
    BUFFER_ATOMIC_SWAP_OFFSET = 316,
332
    BUFFER_ATOMIC_SWAP_OFFSET_RTN = 317,
333
    BUFFER_ATOMIC_SWAP_X2_ADDR64  = 318,
334
    BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN  = 319,
335
    BUFFER_ATOMIC_SWAP_X2_BOTHEN  = 320,
336
    BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN  = 321,
337
    BUFFER_ATOMIC_SWAP_X2_IDXEN = 322,
338
    BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN = 323,
339
    BUFFER_ATOMIC_SWAP_X2_OFFEN = 324,
340
    BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN = 325,
341
    BUFFER_ATOMIC_SWAP_X2_OFFSET  = 326,
342
    BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN  = 327,
343
    BUFFER_ATOMIC_UMAX_ADDR64 = 328,
344
    BUFFER_ATOMIC_UMAX_ADDR64_RTN = 329,
345
    BUFFER_ATOMIC_UMAX_BOTHEN = 330,
346
    BUFFER_ATOMIC_UMAX_BOTHEN_RTN = 331,
347
    BUFFER_ATOMIC_UMAX_IDXEN  = 332,
348
    BUFFER_ATOMIC_UMAX_IDXEN_RTN  = 333,
349
    BUFFER_ATOMIC_UMAX_OFFEN  = 334,
350
    BUFFER_ATOMIC_UMAX_OFFEN_RTN  = 335,
351
    BUFFER_ATOMIC_UMAX_OFFSET = 336,
352
    BUFFER_ATOMIC_UMAX_OFFSET_RTN = 337,
353
    BUFFER_ATOMIC_UMAX_X2_ADDR64  = 338,
354
    BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN  = 339,
355
    BUFFER_ATOMIC_UMAX_X2_BOTHEN  = 340,
356
    BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN  = 341,
357
    BUFFER_ATOMIC_UMAX_X2_IDXEN = 342,
358
    BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN = 343,
359
    BUFFER_ATOMIC_UMAX_X2_OFFEN = 344,
360
    BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN = 345,
361
    BUFFER_ATOMIC_UMAX_X2_OFFSET  = 346,
362
    BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN  = 347,
363
    BUFFER_ATOMIC_UMIN_ADDR64 = 348,
364
    BUFFER_ATOMIC_UMIN_ADDR64_RTN = 349,
365
    BUFFER_ATOMIC_UMIN_BOTHEN = 350,
366
    BUFFER_ATOMIC_UMIN_BOTHEN_RTN = 351,
367
    BUFFER_ATOMIC_UMIN_IDXEN  = 352,
368
    BUFFER_ATOMIC_UMIN_IDXEN_RTN  = 353,
369
    BUFFER_ATOMIC_UMIN_OFFEN  = 354,
370
    BUFFER_ATOMIC_UMIN_OFFEN_RTN  = 355,
371
    BUFFER_ATOMIC_UMIN_OFFSET = 356,
372
    BUFFER_ATOMIC_UMIN_OFFSET_RTN = 357,
373
    BUFFER_ATOMIC_UMIN_X2_ADDR64  = 358,
374
    BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN  = 359,
375
    BUFFER_ATOMIC_UMIN_X2_BOTHEN  = 360,
376
    BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN  = 361,
377
    BUFFER_ATOMIC_UMIN_X2_IDXEN = 362,
378
    BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN = 363,
379
    BUFFER_ATOMIC_UMIN_X2_OFFEN = 364,
380
    BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN = 365,
381
    BUFFER_ATOMIC_UMIN_X2_OFFSET  = 366,
382
    BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN  = 367,
383
    BUFFER_ATOMIC_XOR_ADDR64  = 368,
384
    BUFFER_ATOMIC_XOR_ADDR64_RTN  = 369,
385
    BUFFER_ATOMIC_XOR_BOTHEN  = 370,
386
    BUFFER_ATOMIC_XOR_BOTHEN_RTN  = 371,
387
    BUFFER_ATOMIC_XOR_IDXEN = 372,
388
    BUFFER_ATOMIC_XOR_IDXEN_RTN = 373,
389
    BUFFER_ATOMIC_XOR_OFFEN = 374,
390
    BUFFER_ATOMIC_XOR_OFFEN_RTN = 375,
391
    BUFFER_ATOMIC_XOR_OFFSET  = 376,
392
    BUFFER_ATOMIC_XOR_OFFSET_RTN  = 377,
393
    BUFFER_ATOMIC_XOR_X2_ADDR64 = 378,
394
    BUFFER_ATOMIC_XOR_X2_ADDR64_RTN = 379,
395
    BUFFER_ATOMIC_XOR_X2_BOTHEN = 380,
396
    BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN = 381,
397
    BUFFER_ATOMIC_XOR_X2_IDXEN  = 382,
398
    BUFFER_ATOMIC_XOR_X2_IDXEN_RTN  = 383,
399
    BUFFER_ATOMIC_XOR_X2_OFFEN  = 384,
400
    BUFFER_ATOMIC_XOR_X2_OFFEN_RTN  = 385,
401
    BUFFER_ATOMIC_XOR_X2_OFFSET = 386,
402
    BUFFER_ATOMIC_XOR_X2_OFFSET_RTN = 387,
403
    BUFFER_LOAD_DWORDX2_ADDR64  = 388,
404
    BUFFER_LOAD_DWORDX2_BOTHEN  = 389,
405
    BUFFER_LOAD_DWORDX2_BOTHEN_exact  = 390,
406
    BUFFER_LOAD_DWORDX2_IDXEN = 391,
407
    BUFFER_LOAD_DWORDX2_IDXEN_exact = 392,
408
    BUFFER_LOAD_DWORDX2_LDS_ADDR64  = 393,
409
    BUFFER_LOAD_DWORDX2_LDS_BOTHEN  = 394,
410
    BUFFER_LOAD_DWORDX2_LDS_BOTHEN_exact  = 395,
411
    BUFFER_LOAD_DWORDX2_LDS_IDXEN = 396,
412
    BUFFER_LOAD_DWORDX2_LDS_IDXEN_exact = 397,
413
    BUFFER_LOAD_DWORDX2_LDS_OFFEN = 398,
414
    BUFFER_LOAD_DWORDX2_LDS_OFFEN_exact = 399,
415
    BUFFER_LOAD_DWORDX2_LDS_OFFSET  = 400,
416
    BUFFER_LOAD_DWORDX2_LDS_OFFSET_exact  = 401,
417
    BUFFER_LOAD_DWORDX2_OFFEN = 402,
418
    BUFFER_LOAD_DWORDX2_OFFEN_exact = 403,
419
    BUFFER_LOAD_DWORDX2_OFFSET  = 404,
420
    BUFFER_LOAD_DWORDX2_OFFSET_exact  = 405,
421
    BUFFER_LOAD_DWORDX3_ADDR64  = 406,
422
    BUFFER_LOAD_DWORDX3_BOTHEN  = 407,
423
    BUFFER_LOAD_DWORDX3_BOTHEN_exact  = 408,
424
    BUFFER_LOAD_DWORDX3_IDXEN = 409,
425
    BUFFER_LOAD_DWORDX3_IDXEN_exact = 410,
426
    BUFFER_LOAD_DWORDX3_LDS_ADDR64  = 411,
427
    BUFFER_LOAD_DWORDX3_LDS_BOTHEN  = 412,
428
    BUFFER_LOAD_DWORDX3_LDS_BOTHEN_exact  = 413,
429
    BUFFER_LOAD_DWORDX3_LDS_IDXEN = 414,
430
    BUFFER_LOAD_DWORDX3_LDS_IDXEN_exact = 415,
431
    BUFFER_LOAD_DWORDX3_LDS_OFFEN = 416,
432
    BUFFER_LOAD_DWORDX3_LDS_OFFEN_exact = 417,
433
    BUFFER_LOAD_DWORDX3_LDS_OFFSET  = 418,
434
    BUFFER_LOAD_DWORDX3_LDS_OFFSET_exact  = 419,
435
    BUFFER_LOAD_DWORDX3_OFFEN = 420,
436
    BUFFER_LOAD_DWORDX3_OFFEN_exact = 421,
437
    BUFFER_LOAD_DWORDX3_OFFSET  = 422,
438
    BUFFER_LOAD_DWORDX3_OFFSET_exact  = 423,
439
    BUFFER_LOAD_DWORDX4_ADDR64  = 424,
440
    BUFFER_LOAD_DWORDX4_BOTHEN  = 425,
441
    BUFFER_LOAD_DWORDX4_BOTHEN_exact  = 426,
442
    BUFFER_LOAD_DWORDX4_IDXEN = 427,
443
    BUFFER_LOAD_DWORDX4_IDXEN_exact = 428,
444
    BUFFER_LOAD_DWORDX4_LDS_ADDR64  = 429,
445
    BUFFER_LOAD_DWORDX4_LDS_BOTHEN  = 430,
446
    BUFFER_LOAD_DWORDX4_LDS_BOTHEN_exact  = 431,
447
    BUFFER_LOAD_DWORDX4_LDS_IDXEN = 432,
448
    BUFFER_LOAD_DWORDX4_LDS_IDXEN_exact = 433,
449
    BUFFER_LOAD_DWORDX4_LDS_OFFEN = 434,
450
    BUFFER_LOAD_DWORDX4_LDS_OFFEN_exact = 435,
451
    BUFFER_LOAD_DWORDX4_LDS_OFFSET  = 436,
452
    BUFFER_LOAD_DWORDX4_LDS_OFFSET_exact  = 437,
453
    BUFFER_LOAD_DWORDX4_OFFEN = 438,
454
    BUFFER_LOAD_DWORDX4_OFFEN_exact = 439,
455
    BUFFER_LOAD_DWORDX4_OFFSET  = 440,
456
    BUFFER_LOAD_DWORDX4_OFFSET_exact  = 441,
457
    BUFFER_LOAD_DWORD_ADDR64  = 442,
458
    BUFFER_LOAD_DWORD_BOTHEN  = 443,
459
    BUFFER_LOAD_DWORD_BOTHEN_exact  = 444,
460
    BUFFER_LOAD_DWORD_IDXEN = 445,
461
    BUFFER_LOAD_DWORD_IDXEN_exact = 446,
462
    BUFFER_LOAD_DWORD_LDS_ADDR64  = 447,
463
    BUFFER_LOAD_DWORD_LDS_BOTHEN  = 448,
464
    BUFFER_LOAD_DWORD_LDS_BOTHEN_exact  = 449,
465
    BUFFER_LOAD_DWORD_LDS_IDXEN = 450,
466
    BUFFER_LOAD_DWORD_LDS_IDXEN_exact = 451,
467
    BUFFER_LOAD_DWORD_LDS_OFFEN = 452,
468
    BUFFER_LOAD_DWORD_LDS_OFFEN_exact = 453,
469
    BUFFER_LOAD_DWORD_LDS_OFFSET  = 454,
470
    BUFFER_LOAD_DWORD_LDS_OFFSET_exact  = 455,
471
    BUFFER_LOAD_DWORD_OFFEN = 456,
472
    BUFFER_LOAD_DWORD_OFFEN_exact = 457,
473
    BUFFER_LOAD_DWORD_OFFSET  = 458,
474
    BUFFER_LOAD_DWORD_OFFSET_exact  = 459,
475
    BUFFER_LOAD_FORMAT_D16_HI_X_ADDR64  = 460,
476
    BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN  = 461,
477
    BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_exact  = 462,
478
    BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN = 463,
479
    BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_exact = 464,
480
    BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN = 465,
481
    BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_exact = 466,
482
    BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET  = 467,
483
    BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_exact  = 468,
484
    BUFFER_LOAD_FORMAT_D16_XYZW_ADDR64  = 469,
485
    BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN  = 470,
486
    BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_exact  = 471,
487
    BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN = 472,
488
    BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_exact = 473,
489
    BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN = 474,
490
    BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_exact = 475,
491
    BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET  = 476,
492
    BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_exact  = 477,
493
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_ADDR64  = 478,
494
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN  = 479,
495
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_exact  = 480,
496
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN = 481,
497
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_exact = 482,
498
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN = 483,
499
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_exact = 484,
500
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET  = 485,
501
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_exact  = 486,
502
    BUFFER_LOAD_FORMAT_D16_XYZ_ADDR64 = 487,
503
    BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN = 488,
504
    BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_exact = 489,
505
    BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN  = 490,
506
    BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_exact  = 491,
507
    BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN  = 492,
508
    BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_exact  = 493,
509
    BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET = 494,
510
    BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_exact = 495,
511
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_ADDR64 = 496,
512
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN = 497,
513
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_exact = 498,
514
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN  = 499,
515
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_exact  = 500,
516
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN  = 501,
517
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_exact  = 502,
518
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET = 503,
519
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_exact = 504,
520
    BUFFER_LOAD_FORMAT_D16_XY_ADDR64  = 505,
521
    BUFFER_LOAD_FORMAT_D16_XY_BOTHEN  = 506,
522
    BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_exact  = 507,
523
    BUFFER_LOAD_FORMAT_D16_XY_IDXEN = 508,
524
    BUFFER_LOAD_FORMAT_D16_XY_IDXEN_exact = 509,
525
    BUFFER_LOAD_FORMAT_D16_XY_OFFEN = 510,
526
    BUFFER_LOAD_FORMAT_D16_XY_OFFEN_exact = 511,
527
    BUFFER_LOAD_FORMAT_D16_XY_OFFSET  = 512,
528
    BUFFER_LOAD_FORMAT_D16_XY_OFFSET_exact  = 513,
529
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_ADDR64  = 514,
530
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN  = 515,
531
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_exact  = 516,
532
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN = 517,
533
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_exact = 518,
534
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN = 519,
535
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_exact = 520,
536
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET  = 521,
537
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_exact  = 522,
538
    BUFFER_LOAD_FORMAT_D16_X_ADDR64 = 523,
539
    BUFFER_LOAD_FORMAT_D16_X_BOTHEN = 524,
540
    BUFFER_LOAD_FORMAT_D16_X_BOTHEN_exact = 525,
541
    BUFFER_LOAD_FORMAT_D16_X_IDXEN  = 526,
542
    BUFFER_LOAD_FORMAT_D16_X_IDXEN_exact  = 527,
543
    BUFFER_LOAD_FORMAT_D16_X_OFFEN  = 528,
544
    BUFFER_LOAD_FORMAT_D16_X_OFFEN_exact  = 529,
545
    BUFFER_LOAD_FORMAT_D16_X_OFFSET = 530,
546
    BUFFER_LOAD_FORMAT_D16_X_OFFSET_exact = 531,
547
    BUFFER_LOAD_FORMAT_D16_X_gfx80_ADDR64 = 532,
548
    BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN = 533,
549
    BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_exact = 534,
550
    BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN  = 535,
551
    BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_exact  = 536,
552
    BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN  = 537,
553
    BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_exact  = 538,
554
    BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET = 539,
555
    BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_exact = 540,
556
    BUFFER_LOAD_FORMAT_XYZW_ADDR64  = 541,
557
    BUFFER_LOAD_FORMAT_XYZW_BOTHEN  = 542,
558
    BUFFER_LOAD_FORMAT_XYZW_BOTHEN_exact  = 543,
559
    BUFFER_LOAD_FORMAT_XYZW_IDXEN = 544,
560
    BUFFER_LOAD_FORMAT_XYZW_IDXEN_exact = 545,
561
    BUFFER_LOAD_FORMAT_XYZW_OFFEN = 546,
562
    BUFFER_LOAD_FORMAT_XYZW_OFFEN_exact = 547,
563
    BUFFER_LOAD_FORMAT_XYZW_OFFSET  = 548,
564
    BUFFER_LOAD_FORMAT_XYZW_OFFSET_exact  = 549,
565
    BUFFER_LOAD_FORMAT_XYZ_ADDR64 = 550,
566
    BUFFER_LOAD_FORMAT_XYZ_BOTHEN = 551,
567
    BUFFER_LOAD_FORMAT_XYZ_BOTHEN_exact = 552,
568
    BUFFER_LOAD_FORMAT_XYZ_IDXEN  = 553,
569
    BUFFER_LOAD_FORMAT_XYZ_IDXEN_exact  = 554,
570
    BUFFER_LOAD_FORMAT_XYZ_OFFEN  = 555,
571
    BUFFER_LOAD_FORMAT_XYZ_OFFEN_exact  = 556,
572
    BUFFER_LOAD_FORMAT_XYZ_OFFSET = 557,
573
    BUFFER_LOAD_FORMAT_XYZ_OFFSET_exact = 558,
574
    BUFFER_LOAD_FORMAT_XY_ADDR64  = 559,
575
    BUFFER_LOAD_FORMAT_XY_BOTHEN  = 560,
576
    BUFFER_LOAD_FORMAT_XY_BOTHEN_exact  = 561,
577
    BUFFER_LOAD_FORMAT_XY_IDXEN = 562,
578
    BUFFER_LOAD_FORMAT_XY_IDXEN_exact = 563,
579
    BUFFER_LOAD_FORMAT_XY_OFFEN = 564,
580
    BUFFER_LOAD_FORMAT_XY_OFFEN_exact = 565,
581
    BUFFER_LOAD_FORMAT_XY_OFFSET  = 566,
582
    BUFFER_LOAD_FORMAT_XY_OFFSET_exact  = 567,
583
    BUFFER_LOAD_FORMAT_X_ADDR64 = 568,
584
    BUFFER_LOAD_FORMAT_X_BOTHEN = 569,
585
    BUFFER_LOAD_FORMAT_X_BOTHEN_exact = 570,
586
    BUFFER_LOAD_FORMAT_X_IDXEN  = 571,
587
    BUFFER_LOAD_FORMAT_X_IDXEN_exact  = 572,
588
    BUFFER_LOAD_FORMAT_X_LDS_ADDR64 = 573,
589
    BUFFER_LOAD_FORMAT_X_LDS_BOTHEN = 574,
590
    BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_exact = 575,
591
    BUFFER_LOAD_FORMAT_X_LDS_IDXEN  = 576,
592
    BUFFER_LOAD_FORMAT_X_LDS_IDXEN_exact  = 577,
593
    BUFFER_LOAD_FORMAT_X_LDS_OFFEN  = 578,
594
    BUFFER_LOAD_FORMAT_X_LDS_OFFEN_exact  = 579,
595
    BUFFER_LOAD_FORMAT_X_LDS_OFFSET = 580,
596
    BUFFER_LOAD_FORMAT_X_LDS_OFFSET_exact = 581,
597
    BUFFER_LOAD_FORMAT_X_OFFEN  = 582,
598
    BUFFER_LOAD_FORMAT_X_OFFEN_exact  = 583,
599
    BUFFER_LOAD_FORMAT_X_OFFSET = 584,
600
    BUFFER_LOAD_FORMAT_X_OFFSET_exact = 585,
601
    BUFFER_LOAD_SBYTE_ADDR64  = 586,
602
    BUFFER_LOAD_SBYTE_BOTHEN  = 587,
603
    BUFFER_LOAD_SBYTE_BOTHEN_exact  = 588,
604
    BUFFER_LOAD_SBYTE_D16_ADDR64  = 589,
605
    BUFFER_LOAD_SBYTE_D16_BOTHEN  = 590,
606
    BUFFER_LOAD_SBYTE_D16_BOTHEN_exact  = 591,
607
    BUFFER_LOAD_SBYTE_D16_HI_ADDR64 = 592,
608
    BUFFER_LOAD_SBYTE_D16_HI_BOTHEN = 593,
609
    BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_exact = 594,
610
    BUFFER_LOAD_SBYTE_D16_HI_IDXEN  = 595,
611
    BUFFER_LOAD_SBYTE_D16_HI_IDXEN_exact  = 596,
612
    BUFFER_LOAD_SBYTE_D16_HI_OFFEN  = 597,
613
    BUFFER_LOAD_SBYTE_D16_HI_OFFEN_exact  = 598,
614
    BUFFER_LOAD_SBYTE_D16_HI_OFFSET = 599,
615
    BUFFER_LOAD_SBYTE_D16_HI_OFFSET_exact = 600,
616
    BUFFER_LOAD_SBYTE_D16_IDXEN = 601,
617
    BUFFER_LOAD_SBYTE_D16_IDXEN_exact = 602,
618
    BUFFER_LOAD_SBYTE_D16_OFFEN = 603,
619
    BUFFER_LOAD_SBYTE_D16_OFFEN_exact = 604,
620
    BUFFER_LOAD_SBYTE_D16_OFFSET  = 605,
621
    BUFFER_LOAD_SBYTE_D16_OFFSET_exact  = 606,
622
    BUFFER_LOAD_SBYTE_IDXEN = 607,
623
    BUFFER_LOAD_SBYTE_IDXEN_exact = 608,
624
    BUFFER_LOAD_SBYTE_LDS_ADDR64  = 609,
625
    BUFFER_LOAD_SBYTE_LDS_BOTHEN  = 610,
626
    BUFFER_LOAD_SBYTE_LDS_BOTHEN_exact  = 611,
627
    BUFFER_LOAD_SBYTE_LDS_IDXEN = 612,
628
    BUFFER_LOAD_SBYTE_LDS_IDXEN_exact = 613,
629
    BUFFER_LOAD_SBYTE_LDS_OFFEN = 614,
630
    BUFFER_LOAD_SBYTE_LDS_OFFEN_exact = 615,
631
    BUFFER_LOAD_SBYTE_LDS_OFFSET  = 616,
632
    BUFFER_LOAD_SBYTE_LDS_OFFSET_exact  = 617,
633
    BUFFER_LOAD_SBYTE_OFFEN = 618,
634
    BUFFER_LOAD_SBYTE_OFFEN_exact = 619,
635
    BUFFER_LOAD_SBYTE_OFFSET  = 620,
636
    BUFFER_LOAD_SBYTE_OFFSET_exact  = 621,
637
    BUFFER_LOAD_SHORT_D16_ADDR64  = 622,
638
    BUFFER_LOAD_SHORT_D16_BOTHEN  = 623,
639
    BUFFER_LOAD_SHORT_D16_BOTHEN_exact  = 624,
640
    BUFFER_LOAD_SHORT_D16_HI_ADDR64 = 625,
641
    BUFFER_LOAD_SHORT_D16_HI_BOTHEN = 626,
642
    BUFFER_LOAD_SHORT_D16_HI_BOTHEN_exact = 627,
643
    BUFFER_LOAD_SHORT_D16_HI_IDXEN  = 628,
644
    BUFFER_LOAD_SHORT_D16_HI_IDXEN_exact  = 629,
645
    BUFFER_LOAD_SHORT_D16_HI_OFFEN  = 630,
646
    BUFFER_LOAD_SHORT_D16_HI_OFFEN_exact  = 631,
647
    BUFFER_LOAD_SHORT_D16_HI_OFFSET = 632,
648
    BUFFER_LOAD_SHORT_D16_HI_OFFSET_exact = 633,
649
    BUFFER_LOAD_SHORT_D16_IDXEN = 634,
650
    BUFFER_LOAD_SHORT_D16_IDXEN_exact = 635,
651
    BUFFER_LOAD_SHORT_D16_OFFEN = 636,
652
    BUFFER_LOAD_SHORT_D16_OFFEN_exact = 637,
653
    BUFFER_LOAD_SHORT_D16_OFFSET  = 638,
654
    BUFFER_LOAD_SHORT_D16_OFFSET_exact  = 639,
655
    BUFFER_LOAD_SSHORT_ADDR64 = 640,
656
    BUFFER_LOAD_SSHORT_BOTHEN = 641,
657
    BUFFER_LOAD_SSHORT_BOTHEN_exact = 642,
658
    BUFFER_LOAD_SSHORT_IDXEN  = 643,
659
    BUFFER_LOAD_SSHORT_IDXEN_exact  = 644,
660
    BUFFER_LOAD_SSHORT_LDS_ADDR64 = 645,
661
    BUFFER_LOAD_SSHORT_LDS_BOTHEN = 646,
662
    BUFFER_LOAD_SSHORT_LDS_BOTHEN_exact = 647,
663
    BUFFER_LOAD_SSHORT_LDS_IDXEN  = 648,
664
    BUFFER_LOAD_SSHORT_LDS_IDXEN_exact  = 649,
665
    BUFFER_LOAD_SSHORT_LDS_OFFEN  = 650,
666
    BUFFER_LOAD_SSHORT_LDS_OFFEN_exact  = 651,
667
    BUFFER_LOAD_SSHORT_LDS_OFFSET = 652,
668
    BUFFER_LOAD_SSHORT_LDS_OFFSET_exact = 653,
669
    BUFFER_LOAD_SSHORT_OFFEN  = 654,
670
    BUFFER_LOAD_SSHORT_OFFEN_exact  = 655,
671
    BUFFER_LOAD_SSHORT_OFFSET = 656,
672
    BUFFER_LOAD_SSHORT_OFFSET_exact = 657,
673
    BUFFER_LOAD_UBYTE_ADDR64  = 658,
674
    BUFFER_LOAD_UBYTE_BOTHEN  = 659,
675
    BUFFER_LOAD_UBYTE_BOTHEN_exact  = 660,
676
    BUFFER_LOAD_UBYTE_D16_ADDR64  = 661,
677
    BUFFER_LOAD_UBYTE_D16_BOTHEN  = 662,
678
    BUFFER_LOAD_UBYTE_D16_BOTHEN_exact  = 663,
679
    BUFFER_LOAD_UBYTE_D16_HI_ADDR64 = 664,
680
    BUFFER_LOAD_UBYTE_D16_HI_BOTHEN = 665,
681
    BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_exact = 666,
682
    BUFFER_LOAD_UBYTE_D16_HI_IDXEN  = 667,
683
    BUFFER_LOAD_UBYTE_D16_HI_IDXEN_exact  = 668,
684
    BUFFER_LOAD_UBYTE_D16_HI_OFFEN  = 669,
685
    BUFFER_LOAD_UBYTE_D16_HI_OFFEN_exact  = 670,
686
    BUFFER_LOAD_UBYTE_D16_HI_OFFSET = 671,
687
    BUFFER_LOAD_UBYTE_D16_HI_OFFSET_exact = 672,
688
    BUFFER_LOAD_UBYTE_D16_IDXEN = 673,
689
    BUFFER_LOAD_UBYTE_D16_IDXEN_exact = 674,
690
    BUFFER_LOAD_UBYTE_D16_OFFEN = 675,
691
    BUFFER_LOAD_UBYTE_D16_OFFEN_exact = 676,
692
    BUFFER_LOAD_UBYTE_D16_OFFSET  = 677,
693
    BUFFER_LOAD_UBYTE_D16_OFFSET_exact  = 678,
694
    BUFFER_LOAD_UBYTE_IDXEN = 679,
695
    BUFFER_LOAD_UBYTE_IDXEN_exact = 680,
696
    BUFFER_LOAD_UBYTE_LDS_ADDR64  = 681,
697
    BUFFER_LOAD_UBYTE_LDS_BOTHEN  = 682,
698
    BUFFER_LOAD_UBYTE_LDS_BOTHEN_exact  = 683,
699
    BUFFER_LOAD_UBYTE_LDS_IDXEN = 684,
700
    BUFFER_LOAD_UBYTE_LDS_IDXEN_exact = 685,
701
    BUFFER_LOAD_UBYTE_LDS_OFFEN = 686,
702
    BUFFER_LOAD_UBYTE_LDS_OFFEN_exact = 687,
703
    BUFFER_LOAD_UBYTE_LDS_OFFSET  = 688,
704
    BUFFER_LOAD_UBYTE_LDS_OFFSET_exact  = 689,
705
    BUFFER_LOAD_UBYTE_OFFEN = 690,
706
    BUFFER_LOAD_UBYTE_OFFEN_exact = 691,
707
    BUFFER_LOAD_UBYTE_OFFSET  = 692,
708
    BUFFER_LOAD_UBYTE_OFFSET_exact  = 693,
709
    BUFFER_LOAD_USHORT_ADDR64 = 694,
710
    BUFFER_LOAD_USHORT_BOTHEN = 695,
711
    BUFFER_LOAD_USHORT_BOTHEN_exact = 696,
712
    BUFFER_LOAD_USHORT_IDXEN  = 697,
713
    BUFFER_LOAD_USHORT_IDXEN_exact  = 698,
714
    BUFFER_LOAD_USHORT_LDS_ADDR64 = 699,
715
    BUFFER_LOAD_USHORT_LDS_BOTHEN = 700,
716
    BUFFER_LOAD_USHORT_LDS_BOTHEN_exact = 701,
717
    BUFFER_LOAD_USHORT_LDS_IDXEN  = 702,
718
    BUFFER_LOAD_USHORT_LDS_IDXEN_exact  = 703,
719
    BUFFER_LOAD_USHORT_LDS_OFFEN  = 704,
720
    BUFFER_LOAD_USHORT_LDS_OFFEN_exact  = 705,
721
    BUFFER_LOAD_USHORT_LDS_OFFSET = 706,
722
    BUFFER_LOAD_USHORT_LDS_OFFSET_exact = 707,
723
    BUFFER_LOAD_USHORT_OFFEN  = 708,
724
    BUFFER_LOAD_USHORT_OFFEN_exact  = 709,
725
    BUFFER_LOAD_USHORT_OFFSET = 710,
726
    BUFFER_LOAD_USHORT_OFFSET_exact = 711,
727
    BUFFER_STORE_BYTE_ADDR64  = 712,
728
    BUFFER_STORE_BYTE_BOTHEN  = 713,
729
    BUFFER_STORE_BYTE_BOTHEN_exact  = 714,
730
    BUFFER_STORE_BYTE_D16_HI_ADDR64 = 715,
731
    BUFFER_STORE_BYTE_D16_HI_BOTHEN = 716,
732
    BUFFER_STORE_BYTE_D16_HI_BOTHEN_exact = 717,
733
    BUFFER_STORE_BYTE_D16_HI_IDXEN  = 718,
734
    BUFFER_STORE_BYTE_D16_HI_IDXEN_exact  = 719,
735
    BUFFER_STORE_BYTE_D16_HI_OFFEN  = 720,
736
    BUFFER_STORE_BYTE_D16_HI_OFFEN_exact  = 721,
737
    BUFFER_STORE_BYTE_D16_HI_OFFSET = 722,
738
    BUFFER_STORE_BYTE_D16_HI_OFFSET_exact = 723,
739
    BUFFER_STORE_BYTE_IDXEN = 724,
740
    BUFFER_STORE_BYTE_IDXEN_exact = 725,
741
    BUFFER_STORE_BYTE_OFFEN = 726,
742
    BUFFER_STORE_BYTE_OFFEN_exact = 727,
743
    BUFFER_STORE_BYTE_OFFSET  = 728,
744
    BUFFER_STORE_BYTE_OFFSET_exact  = 729,
745
    BUFFER_STORE_DWORDX2_ADDR64 = 730,
746
    BUFFER_STORE_DWORDX2_BOTHEN = 731,
747
    BUFFER_STORE_DWORDX2_BOTHEN_exact = 732,
748
    BUFFER_STORE_DWORDX2_IDXEN  = 733,
749
    BUFFER_STORE_DWORDX2_IDXEN_exact  = 734,
750
    BUFFER_STORE_DWORDX2_OFFEN  = 735,
751
    BUFFER_STORE_DWORDX2_OFFEN_exact  = 736,
752
    BUFFER_STORE_DWORDX2_OFFSET = 737,
753
    BUFFER_STORE_DWORDX2_OFFSET_exact = 738,
754
    BUFFER_STORE_DWORDX3_ADDR64 = 739,
755
    BUFFER_STORE_DWORDX3_BOTHEN = 740,
756
    BUFFER_STORE_DWORDX3_BOTHEN_exact = 741,
757
    BUFFER_STORE_DWORDX3_IDXEN  = 742,
758
    BUFFER_STORE_DWORDX3_IDXEN_exact  = 743,
759
    BUFFER_STORE_DWORDX3_OFFEN  = 744,
760
    BUFFER_STORE_DWORDX3_OFFEN_exact  = 745,
761
    BUFFER_STORE_DWORDX3_OFFSET = 746,
762
    BUFFER_STORE_DWORDX3_OFFSET_exact = 747,
763
    BUFFER_STORE_DWORDX4_ADDR64 = 748,
764
    BUFFER_STORE_DWORDX4_BOTHEN = 749,
765
    BUFFER_STORE_DWORDX4_BOTHEN_exact = 750,
766
    BUFFER_STORE_DWORDX4_IDXEN  = 751,
767
    BUFFER_STORE_DWORDX4_IDXEN_exact  = 752,
768
    BUFFER_STORE_DWORDX4_OFFEN  = 753,
769
    BUFFER_STORE_DWORDX4_OFFEN_exact  = 754,
770
    BUFFER_STORE_DWORDX4_OFFSET = 755,
771
    BUFFER_STORE_DWORDX4_OFFSET_exact = 756,
772
    BUFFER_STORE_DWORD_ADDR64 = 757,
773
    BUFFER_STORE_DWORD_BOTHEN = 758,
774
    BUFFER_STORE_DWORD_BOTHEN_exact = 759,
775
    BUFFER_STORE_DWORD_IDXEN  = 760,
776
    BUFFER_STORE_DWORD_IDXEN_exact  = 761,
777
    BUFFER_STORE_DWORD_OFFEN  = 762,
778
    BUFFER_STORE_DWORD_OFFEN_exact  = 763,
779
    BUFFER_STORE_DWORD_OFFSET = 764,
780
    BUFFER_STORE_DWORD_OFFSET_exact = 765,
781
    BUFFER_STORE_FORMAT_D16_HI_X_ADDR64 = 766,
782
    BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN = 767,
783
    BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_exact = 768,
784
    BUFFER_STORE_FORMAT_D16_HI_X_IDXEN  = 769,
785
    BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_exact  = 770,
786
    BUFFER_STORE_FORMAT_D16_HI_X_OFFEN  = 771,
787
    BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_exact  = 772,
788
    BUFFER_STORE_FORMAT_D16_HI_X_OFFSET = 773,
789
    BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_exact = 774,
790
    BUFFER_STORE_FORMAT_D16_XYZW_ADDR64 = 775,
791
    BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN = 776,
792
    BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact = 777,
793
    BUFFER_STORE_FORMAT_D16_XYZW_IDXEN  = 778,
794
    BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact  = 779,
795
    BUFFER_STORE_FORMAT_D16_XYZW_OFFEN  = 780,
796
    BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact  = 781,
797
    BUFFER_STORE_FORMAT_D16_XYZW_OFFSET = 782,
798
    BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact = 783,
799
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_ADDR64 = 784,
800
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN = 785,
801
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact = 786,
802
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN  = 787,
803
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact  = 788,
804
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN  = 789,
805
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact  = 790,
806
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET = 791,
807
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact = 792,
808
    BUFFER_STORE_FORMAT_D16_XYZ_ADDR64  = 793,
809
    BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN  = 794,
810
    BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_exact  = 795,
811
    BUFFER_STORE_FORMAT_D16_XYZ_IDXEN = 796,
812
    BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_exact = 797,
813
    BUFFER_STORE_FORMAT_D16_XYZ_OFFEN = 798,
814
    BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_exact = 799,
815
    BUFFER_STORE_FORMAT_D16_XYZ_OFFSET  = 800,
816
    BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_exact  = 801,
817
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_ADDR64  = 802,
818
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN  = 803,
819
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact  = 804,
820
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN = 805,
821
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact = 806,
822
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN = 807,
823
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact = 808,
824
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET  = 809,
825
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact  = 810,
826
    BUFFER_STORE_FORMAT_D16_XY_ADDR64 = 811,
827
    BUFFER_STORE_FORMAT_D16_XY_BOTHEN = 812,
828
    BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact = 813,
829
    BUFFER_STORE_FORMAT_D16_XY_IDXEN  = 814,
830
    BUFFER_STORE_FORMAT_D16_XY_IDXEN_exact  = 815,
831
    BUFFER_STORE_FORMAT_D16_XY_OFFEN  = 816,
832
    BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact  = 817,
833
    BUFFER_STORE_FORMAT_D16_XY_OFFSET = 818,
834
    BUFFER_STORE_FORMAT_D16_XY_OFFSET_exact = 819,
835
    BUFFER_STORE_FORMAT_D16_XY_gfx80_ADDR64 = 820,
836
    BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN = 821,
837
    BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact = 822,
838
    BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN  = 823,
839
    BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact  = 824,
840
    BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN  = 825,
841
    BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact  = 826,
842
    BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET = 827,
843
    BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact = 828,
844
    BUFFER_STORE_FORMAT_D16_X_ADDR64  = 829,
845
    BUFFER_STORE_FORMAT_D16_X_BOTHEN  = 830,
846
    BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact  = 831,
847
    BUFFER_STORE_FORMAT_D16_X_IDXEN = 832,
848
    BUFFER_STORE_FORMAT_D16_X_IDXEN_exact = 833,
849
    BUFFER_STORE_FORMAT_D16_X_OFFEN = 834,
850
    BUFFER_STORE_FORMAT_D16_X_OFFEN_exact = 835,
851
    BUFFER_STORE_FORMAT_D16_X_OFFSET  = 836,
852
    BUFFER_STORE_FORMAT_D16_X_OFFSET_exact  = 837,
853
    BUFFER_STORE_FORMAT_D16_X_gfx80_ADDR64  = 838,
854
    BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN  = 839,
855
    BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact  = 840,
856
    BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN = 841,
857
    BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact = 842,
858
    BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN = 843,
859
    BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact = 844,
860
    BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET  = 845,
861
    BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact  = 846,
862
    BUFFER_STORE_FORMAT_XYZW_ADDR64 = 847,
863
    BUFFER_STORE_FORMAT_XYZW_BOTHEN = 848,
864
    BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact = 849,
865
    BUFFER_STORE_FORMAT_XYZW_IDXEN  = 850,
866
    BUFFER_STORE_FORMAT_XYZW_IDXEN_exact  = 851,
867
    BUFFER_STORE_FORMAT_XYZW_OFFEN  = 852,
868
    BUFFER_STORE_FORMAT_XYZW_OFFEN_exact  = 853,
869
    BUFFER_STORE_FORMAT_XYZW_OFFSET = 854,
870
    BUFFER_STORE_FORMAT_XYZW_OFFSET_exact = 855,
871
    BUFFER_STORE_FORMAT_XYZ_ADDR64  = 856,
872
    BUFFER_STORE_FORMAT_XYZ_BOTHEN  = 857,
873
    BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact  = 858,
874
    BUFFER_STORE_FORMAT_XYZ_IDXEN = 859,
875
    BUFFER_STORE_FORMAT_XYZ_IDXEN_exact = 860,
876
    BUFFER_STORE_FORMAT_XYZ_OFFEN = 861,
877
    BUFFER_STORE_FORMAT_XYZ_OFFEN_exact = 862,
878
    BUFFER_STORE_FORMAT_XYZ_OFFSET  = 863,
879
    BUFFER_STORE_FORMAT_XYZ_OFFSET_exact  = 864,
880
    BUFFER_STORE_FORMAT_XY_ADDR64 = 865,
881
    BUFFER_STORE_FORMAT_XY_BOTHEN = 866,
882
    BUFFER_STORE_FORMAT_XY_BOTHEN_exact = 867,
883
    BUFFER_STORE_FORMAT_XY_IDXEN  = 868,
884
    BUFFER_STORE_FORMAT_XY_IDXEN_exact  = 869,
885
    BUFFER_STORE_FORMAT_XY_OFFEN  = 870,
886
    BUFFER_STORE_FORMAT_XY_OFFEN_exact  = 871,
887
    BUFFER_STORE_FORMAT_XY_OFFSET = 872,
888
    BUFFER_STORE_FORMAT_XY_OFFSET_exact = 873,
889
    BUFFER_STORE_FORMAT_X_ADDR64  = 874,
890
    BUFFER_STORE_FORMAT_X_BOTHEN  = 875,
891
    BUFFER_STORE_FORMAT_X_BOTHEN_exact  = 876,
892
    BUFFER_STORE_FORMAT_X_IDXEN = 877,
893
    BUFFER_STORE_FORMAT_X_IDXEN_exact = 878,
894
    BUFFER_STORE_FORMAT_X_OFFEN = 879,
895
    BUFFER_STORE_FORMAT_X_OFFEN_exact = 880,
896
    BUFFER_STORE_FORMAT_X_OFFSET  = 881,
897
    BUFFER_STORE_FORMAT_X_OFFSET_exact  = 882,
898
    BUFFER_STORE_LDS_DWORD  = 883,
899
    BUFFER_STORE_SHORT_ADDR64 = 884,
900
    BUFFER_STORE_SHORT_BOTHEN = 885,
901
    BUFFER_STORE_SHORT_BOTHEN_exact = 886,
902
    BUFFER_STORE_SHORT_D16_HI_ADDR64  = 887,
903
    BUFFER_STORE_SHORT_D16_HI_BOTHEN  = 888,
904
    BUFFER_STORE_SHORT_D16_HI_BOTHEN_exact  = 889,
905
    BUFFER_STORE_SHORT_D16_HI_IDXEN = 890,
906
    BUFFER_STORE_SHORT_D16_HI_IDXEN_exact = 891,
907
    BUFFER_STORE_SHORT_D16_HI_OFFEN = 892,
908
    BUFFER_STORE_SHORT_D16_HI_OFFEN_exact = 893,
909
    BUFFER_STORE_SHORT_D16_HI_OFFSET  = 894,
910
    BUFFER_STORE_SHORT_D16_HI_OFFSET_exact  = 895,
911
    BUFFER_STORE_SHORT_IDXEN  = 896,
912
    BUFFER_STORE_SHORT_IDXEN_exact  = 897,
913
    BUFFER_STORE_SHORT_OFFEN  = 898,
914
    BUFFER_STORE_SHORT_OFFEN_exact  = 899,
915
    BUFFER_STORE_SHORT_OFFSET = 900,
916
    BUFFER_STORE_SHORT_OFFSET_exact = 901,
917
    BUFFER_WBINVL1  = 902,
918
    BUFFER_WBINVL1_SC = 903,
919
    BUFFER_WBINVL1_VOL  = 904,
920
    DS_ADD_F32  = 905,
921
    DS_ADD_F32_gfx9 = 906,
922
    DS_ADD_RTN_F32  = 907,
923
    DS_ADD_RTN_F32_gfx9 = 908,
924
    DS_ADD_RTN_U32  = 909,
925
    DS_ADD_RTN_U32_gfx9 = 910,
926
    DS_ADD_RTN_U64  = 911,
927
    DS_ADD_RTN_U64_gfx9 = 912,
928
    DS_ADD_SRC2_F32 = 913,
929
    DS_ADD_SRC2_U32 = 914,
930
    DS_ADD_SRC2_U64 = 915,
931
    DS_ADD_U32  = 916,
932
    DS_ADD_U32_gfx9 = 917,
933
    DS_ADD_U64  = 918,
934
    DS_ADD_U64_gfx9 = 919,
935
    DS_AND_B32  = 920,
936
    DS_AND_B32_gfx9 = 921,
937
    DS_AND_B64  = 922,
938
    DS_AND_B64_gfx9 = 923,
939
    DS_AND_RTN_B32  = 924,
940
    DS_AND_RTN_B32_gfx9 = 925,
941
    DS_AND_RTN_B64  = 926,
942
    DS_AND_RTN_B64_gfx9 = 927,
943
    DS_AND_SRC2_B32 = 928,
944
    DS_AND_SRC2_B64 = 929,
945
    DS_APPEND = 930,
946
    DS_BPERMUTE_B32 = 931,
947
    DS_CMPST_B32  = 932,
948
    DS_CMPST_B32_gfx9 = 933,
949
    DS_CMPST_B64  = 934,
950
    DS_CMPST_B64_gfx9 = 935,
951
    DS_CMPST_F32  = 936,
952
    DS_CMPST_F32_gfx9 = 937,
953
    DS_CMPST_F64  = 938,
954
    DS_CMPST_F64_gfx9 = 939,
955
    DS_CMPST_RTN_B32  = 940,
956
    DS_CMPST_RTN_B32_gfx9 = 941,
957
    DS_CMPST_RTN_B64  = 942,
958
    DS_CMPST_RTN_B64_gfx9 = 943,
959
    DS_CMPST_RTN_F32  = 944,
960
    DS_CMPST_RTN_F32_gfx9 = 945,
961
    DS_CMPST_RTN_F64  = 946,
962
    DS_CMPST_RTN_F64_gfx9 = 947,
963
    DS_CONDXCHG32_RTN_B64 = 948,
964
    DS_CONDXCHG32_RTN_B64_gfx9  = 949,
965
    DS_CONSUME  = 950,
966
    DS_DEC_RTN_U32  = 951,
967
    DS_DEC_RTN_U32_gfx9 = 952,
968
    DS_DEC_RTN_U64  = 953,
969
    DS_DEC_RTN_U64_gfx9 = 954,
970
    DS_DEC_SRC2_U32 = 955,
971
    DS_DEC_SRC2_U64 = 956,
972
    DS_DEC_U32  = 957,
973
    DS_DEC_U32_gfx9 = 958,
974
    DS_DEC_U64  = 959,
975
    DS_DEC_U64_gfx9 = 960,
976
    DS_GWS_BARRIER  = 961,
977
    DS_GWS_INIT = 962,
978
    DS_GWS_SEMA_BR  = 963,
979
    DS_GWS_SEMA_P = 964,
980
    DS_GWS_SEMA_RELEASE_ALL = 965,
981
    DS_GWS_SEMA_V = 966,
982
    DS_INC_RTN_U32  = 967,
983
    DS_INC_RTN_U32_gfx9 = 968,
984
    DS_INC_RTN_U64  = 969,
985
    DS_INC_RTN_U64_gfx9 = 970,
986
    DS_INC_SRC2_U32 = 971,
987
    DS_INC_SRC2_U64 = 972,
988
    DS_INC_U32  = 973,
989
    DS_INC_U32_gfx9 = 974,
990
    DS_INC_U64  = 975,
991
    DS_INC_U64_gfx9 = 976,
992
    DS_MAX_F32  = 977,
993
    DS_MAX_F32_gfx9 = 978,
994
    DS_MAX_F64  = 979,
995
    DS_MAX_F64_gfx9 = 980,
996
    DS_MAX_I32  = 981,
997
    DS_MAX_I32_gfx9 = 982,
998
    DS_MAX_I64  = 983,
999
    DS_MAX_I64_gfx9 = 984,
1000
    DS_MAX_RTN_F32  = 985,
1001
    DS_MAX_RTN_F32_gfx9 = 986,
1002
    DS_MAX_RTN_F64  = 987,
1003
    DS_MAX_RTN_F64_gfx9 = 988,
1004
    DS_MAX_RTN_I32  = 989,
1005
    DS_MAX_RTN_I32_gfx9 = 990,
1006
    DS_MAX_RTN_I64  = 991,
1007
    DS_MAX_RTN_I64_gfx9 = 992,
1008
    DS_MAX_RTN_U32  = 993,
1009
    DS_MAX_RTN_U32_gfx9 = 994,
1010
    DS_MAX_RTN_U64  = 995,
1011
    DS_MAX_RTN_U64_gfx9 = 996,
1012
    DS_MAX_SRC2_F32 = 997,
1013
    DS_MAX_SRC2_F64 = 998,
1014
    DS_MAX_SRC2_I32 = 999,
1015
    DS_MAX_SRC2_I64 = 1000,
1016
    DS_MAX_SRC2_U32 = 1001,
1017
    DS_MAX_SRC2_U64 = 1002,
1018
    DS_MAX_U32  = 1003,
1019
    DS_MAX_U32_gfx9 = 1004,
1020
    DS_MAX_U64  = 1005,
1021
    DS_MAX_U64_gfx9 = 1006,
1022
    DS_MIN_F32  = 1007,
1023
    DS_MIN_F32_gfx9 = 1008,
1024
    DS_MIN_F64  = 1009,
1025
    DS_MIN_F64_gfx9 = 1010,
1026
    DS_MIN_I32  = 1011,
1027
    DS_MIN_I32_gfx9 = 1012,
1028
    DS_MIN_I64  = 1013,
1029
    DS_MIN_I64_gfx9 = 1014,
1030
    DS_MIN_RTN_F32  = 1015,
1031
    DS_MIN_RTN_F32_gfx9 = 1016,
1032
    DS_MIN_RTN_F64  = 1017,
1033
    DS_MIN_RTN_F64_gfx9 = 1018,
1034
    DS_MIN_RTN_I32  = 1019,
1035
    DS_MIN_RTN_I32_gfx9 = 1020,
1036
    DS_MIN_RTN_I64  = 1021,
1037
    DS_MIN_RTN_I64_gfx9 = 1022,
1038
    DS_MIN_RTN_U32  = 1023,
1039
    DS_MIN_RTN_U32_gfx9 = 1024,
1040
    DS_MIN_RTN_U64  = 1025,
1041
    DS_MIN_RTN_U64_gfx9 = 1026,
1042
    DS_MIN_SRC2_F32 = 1027,
1043
    DS_MIN_SRC2_F64 = 1028,
1044
    DS_MIN_SRC2_I32 = 1029,
1045
    DS_MIN_SRC2_I64 = 1030,
1046
    DS_MIN_SRC2_U32 = 1031,
1047
    DS_MIN_SRC2_U64 = 1032,
1048
    DS_MIN_U32  = 1033,
1049
    DS_MIN_U32_gfx9 = 1034,
1050
    DS_MIN_U64  = 1035,
1051
    DS_MIN_U64_gfx9 = 1036,
1052
    DS_MSKOR_B32  = 1037,
1053
    DS_MSKOR_B32_gfx9 = 1038,
1054
    DS_MSKOR_B64  = 1039,
1055
    DS_MSKOR_B64_gfx9 = 1040,
1056
    DS_MSKOR_RTN_B32  = 1041,
1057
    DS_MSKOR_RTN_B32_gfx9 = 1042,
1058
    DS_MSKOR_RTN_B64  = 1043,
1059
    DS_MSKOR_RTN_B64_gfx9 = 1044,
1060
    DS_NOP  = 1045,
1061
    DS_ORDERED_COUNT  = 1046,
1062
    DS_OR_B32 = 1047,
1063
    DS_OR_B32_gfx9  = 1048,
1064
    DS_OR_B64 = 1049,
1065
    DS_OR_B64_gfx9  = 1050,
1066
    DS_OR_RTN_B32 = 1051,
1067
    DS_OR_RTN_B32_gfx9  = 1052,
1068
    DS_OR_RTN_B64 = 1053,
1069
    DS_OR_RTN_B64_gfx9  = 1054,
1070
    DS_OR_SRC2_B32  = 1055,
1071
    DS_OR_SRC2_B64  = 1056,
1072
    DS_PERMUTE_B32  = 1057,
1073
    DS_READ2ST64_B32  = 1058,
1074
    DS_READ2ST64_B32_gfx9 = 1059,
1075
    DS_READ2ST64_B64  = 1060,
1076
    DS_READ2ST64_B64_gfx9 = 1061,
1077
    DS_READ2_B32  = 1062,
1078
    DS_READ2_B32_gfx9 = 1063,
1079
    DS_READ2_B64  = 1064,
1080
    DS_READ2_B64_gfx9 = 1065,
1081
    DS_READ_ADDTID_B32  = 1066,
1082
    DS_READ_B128  = 1067,
1083
    DS_READ_B128_gfx9 = 1068,
1084
    DS_READ_B32 = 1069,
1085
    DS_READ_B32_gfx9  = 1070,
1086
    DS_READ_B64 = 1071,
1087
    DS_READ_B64_gfx9  = 1072,
1088
    DS_READ_B96 = 1073,
1089
    DS_READ_B96_gfx9  = 1074,
1090
    DS_READ_I16 = 1075,
1091
    DS_READ_I16_gfx9  = 1076,
1092
    DS_READ_I8  = 1077,
1093
    DS_READ_I8_D16  = 1078,
1094
    DS_READ_I8_D16_HI = 1079,
1095
    DS_READ_I8_gfx9 = 1080,
1096
    DS_READ_U16 = 1081,
1097
    DS_READ_U16_D16 = 1082,
1098
    DS_READ_U16_D16_HI  = 1083,
1099
    DS_READ_U16_gfx9  = 1084,
1100
    DS_READ_U8  = 1085,
1101
    DS_READ_U8_D16  = 1086,
1102
    DS_READ_U8_D16_HI = 1087,
1103
    DS_READ_U8_gfx9 = 1088,
1104
    DS_RSUB_RTN_U32 = 1089,
1105
    DS_RSUB_RTN_U32_gfx9  = 1090,
1106
    DS_RSUB_RTN_U64 = 1091,
1107
    DS_RSUB_RTN_U64_gfx9  = 1092,
1108
    DS_RSUB_SRC2_U32  = 1093,
1109
    DS_RSUB_SRC2_U64  = 1094,
1110
    DS_RSUB_U32 = 1095,
1111
    DS_RSUB_U32_gfx9  = 1096,
1112
    DS_RSUB_U64 = 1097,
1113
    DS_RSUB_U64_gfx9  = 1098,
1114
    DS_SUB_RTN_U32  = 1099,
1115
    DS_SUB_RTN_U32_gfx9 = 1100,
1116
    DS_SUB_RTN_U64  = 1101,
1117
    DS_SUB_RTN_U64_gfx9 = 1102,
1118
    DS_SUB_SRC2_U32 = 1103,
1119
    DS_SUB_SRC2_U64 = 1104,
1120
    DS_SUB_U32  = 1105,
1121
    DS_SUB_U32_gfx9 = 1106,
1122
    DS_SUB_U64  = 1107,
1123
    DS_SUB_U64_gfx9 = 1108,
1124
    DS_SWIZZLE_B32  = 1109,
1125
    DS_WRAP_RTN_B32 = 1110,
1126
    DS_WRAP_RTN_B32_gfx9  = 1111,
1127
    DS_WRITE2ST64_B32 = 1112,
1128
    DS_WRITE2ST64_B32_gfx9  = 1113,
1129
    DS_WRITE2ST64_B64 = 1114,
1130
    DS_WRITE2ST64_B64_gfx9  = 1115,
1131
    DS_WRITE2_B32 = 1116,
1132
    DS_WRITE2_B32_gfx9  = 1117,
1133
    DS_WRITE2_B64 = 1118,
1134
    DS_WRITE2_B64_gfx9  = 1119,
1135
    DS_WRITE_ADDTID_B32 = 1120,
1136
    DS_WRITE_B128 = 1121,
1137
    DS_WRITE_B128_gfx9  = 1122,
1138
    DS_WRITE_B16  = 1123,
1139
    DS_WRITE_B16_D16_HI = 1124,
1140
    DS_WRITE_B16_gfx9 = 1125,
1141
    DS_WRITE_B32  = 1126,
1142
    DS_WRITE_B32_gfx9 = 1127,
1143
    DS_WRITE_B64  = 1128,
1144
    DS_WRITE_B64_gfx9 = 1129,
1145
    DS_WRITE_B8 = 1130,
1146
    DS_WRITE_B8_D16_HI  = 1131,
1147
    DS_WRITE_B8_gfx9  = 1132,
1148
    DS_WRITE_B96  = 1133,
1149
    DS_WRITE_B96_gfx9 = 1134,
1150
    DS_WRITE_SRC2_B32 = 1135,
1151
    DS_WRITE_SRC2_B64 = 1136,
1152
    DS_WRXCHG2ST64_RTN_B32  = 1137,
1153
    DS_WRXCHG2ST64_RTN_B32_gfx9 = 1138,
1154
    DS_WRXCHG2ST64_RTN_B64  = 1139,
1155
    DS_WRXCHG2ST64_RTN_B64_gfx9 = 1140,
1156
    DS_WRXCHG2_RTN_B32  = 1141,
1157
    DS_WRXCHG2_RTN_B32_gfx9 = 1142,
1158
    DS_WRXCHG2_RTN_B64  = 1143,
1159
    DS_WRXCHG2_RTN_B64_gfx9 = 1144,
1160
    DS_WRXCHG_RTN_B32 = 1145,
1161
    DS_WRXCHG_RTN_B32_gfx9  = 1146,
1162
    DS_WRXCHG_RTN_B64 = 1147,
1163
    DS_WRXCHG_RTN_B64_gfx9  = 1148,
1164
    DS_XOR_B32  = 1149,
1165
    DS_XOR_B32_gfx9 = 1150,
1166
    DS_XOR_B64  = 1151,
1167
    DS_XOR_B64_gfx9 = 1152,
1168
    DS_XOR_RTN_B32  = 1153,
1169
    DS_XOR_RTN_B32_gfx9 = 1154,
1170
    DS_XOR_RTN_B64  = 1155,
1171
    DS_XOR_RTN_B64_gfx9 = 1156,
1172
    DS_XOR_SRC2_B32 = 1157,
1173
    DS_XOR_SRC2_B64 = 1158,
1174
    EXIT_WWM  = 1159,
1175
    EXP = 1160,
1176
    EXP_DONE  = 1161,
1177
    FLAT_ATOMIC_ADD = 1162,
1178
    FLAT_ATOMIC_ADD_RTN = 1163,
1179
    FLAT_ATOMIC_ADD_X2  = 1164,
1180
    FLAT_ATOMIC_ADD_X2_RTN  = 1165,
1181
    FLAT_ATOMIC_AND = 1166,
1182
    FLAT_ATOMIC_AND_RTN = 1167,
1183
    FLAT_ATOMIC_AND_X2  = 1168,
1184
    FLAT_ATOMIC_AND_X2_RTN  = 1169,
1185
    FLAT_ATOMIC_CMPSWAP = 1170,
1186
    FLAT_ATOMIC_CMPSWAP_RTN = 1171,
1187
    FLAT_ATOMIC_CMPSWAP_X2  = 1172,
1188
    FLAT_ATOMIC_CMPSWAP_X2_RTN  = 1173,
1189
    FLAT_ATOMIC_DEC = 1174,
1190
    FLAT_ATOMIC_DEC_RTN = 1175,
1191
    FLAT_ATOMIC_DEC_X2  = 1176,
1192
    FLAT_ATOMIC_DEC_X2_RTN  = 1177,
1193
    FLAT_ATOMIC_FCMPSWAP  = 1178,
1194
    FLAT_ATOMIC_FCMPSWAP_RTN  = 1179,
1195
    FLAT_ATOMIC_FCMPSWAP_X2 = 1180,
1196
    FLAT_ATOMIC_FCMPSWAP_X2_RTN = 1181,
1197
    FLAT_ATOMIC_FMAX  = 1182,
1198
    FLAT_ATOMIC_FMAX_RTN  = 1183,
1199
    FLAT_ATOMIC_FMAX_X2 = 1184,
1200
    FLAT_ATOMIC_FMAX_X2_RTN = 1185,
1201
    FLAT_ATOMIC_FMIN  = 1186,
1202
    FLAT_ATOMIC_FMIN_RTN  = 1187,
1203
    FLAT_ATOMIC_FMIN_X2 = 1188,
1204
    FLAT_ATOMIC_FMIN_X2_RTN = 1189,
1205
    FLAT_ATOMIC_INC = 1190,
1206
    FLAT_ATOMIC_INC_RTN = 1191,
1207
    FLAT_ATOMIC_INC_X2  = 1192,
1208
    FLAT_ATOMIC_INC_X2_RTN  = 1193,
1209
    FLAT_ATOMIC_OR  = 1194,
1210
    FLAT_ATOMIC_OR_RTN  = 1195,
1211
    FLAT_ATOMIC_OR_X2 = 1196,
1212
    FLAT_ATOMIC_OR_X2_RTN = 1197,
1213
    FLAT_ATOMIC_SMAX  = 1198,
1214
    FLAT_ATOMIC_SMAX_RTN  = 1199,
1215
    FLAT_ATOMIC_SMAX_X2 = 1200,
1216
    FLAT_ATOMIC_SMAX_X2_RTN = 1201,
1217
    FLAT_ATOMIC_SMIN  = 1202,
1218
    FLAT_ATOMIC_SMIN_RTN  = 1203,
1219
    FLAT_ATOMIC_SMIN_X2 = 1204,
1220
    FLAT_ATOMIC_SMIN_X2_RTN = 1205,
1221
    FLAT_ATOMIC_SUB = 1206,
1222
    FLAT_ATOMIC_SUB_RTN = 1207,
1223
    FLAT_ATOMIC_SUB_X2  = 1208,
1224
    FLAT_ATOMIC_SUB_X2_RTN  = 1209,
1225
    FLAT_ATOMIC_SWAP  = 1210,
1226
    FLAT_ATOMIC_SWAP_RTN  = 1211,
1227
    FLAT_ATOMIC_SWAP_X2 = 1212,
1228
    FLAT_ATOMIC_SWAP_X2_RTN = 1213,
1229
    FLAT_ATOMIC_UMAX  = 1214,
1230
    FLAT_ATOMIC_UMAX_RTN  = 1215,
1231
    FLAT_ATOMIC_UMAX_X2 = 1216,
1232
    FLAT_ATOMIC_UMAX_X2_RTN = 1217,
1233
    FLAT_ATOMIC_UMIN  = 1218,
1234
    FLAT_ATOMIC_UMIN_RTN  = 1219,
1235
    FLAT_ATOMIC_UMIN_X2 = 1220,
1236
    FLAT_ATOMIC_UMIN_X2_RTN = 1221,
1237
    FLAT_ATOMIC_XOR = 1222,
1238
    FLAT_ATOMIC_XOR_RTN = 1223,
1239
    FLAT_ATOMIC_XOR_X2  = 1224,
1240
    FLAT_ATOMIC_XOR_X2_RTN  = 1225,
1241
    FLAT_LOAD_DWORD = 1226,
1242
    FLAT_LOAD_DWORDX2 = 1227,
1243
    FLAT_LOAD_DWORDX3 = 1228,
1244
    FLAT_LOAD_DWORDX4 = 1229,
1245
    FLAT_LOAD_SBYTE = 1230,
1246
    FLAT_LOAD_SBYTE_D16 = 1231,
1247
    FLAT_LOAD_SBYTE_D16_HI  = 1232,
1248
    FLAT_LOAD_SHORT_D16 = 1233,
1249
    FLAT_LOAD_SHORT_D16_HI  = 1234,
1250
    FLAT_LOAD_SSHORT  = 1235,
1251
    FLAT_LOAD_UBYTE = 1236,
1252
    FLAT_LOAD_UBYTE_D16 = 1237,
1253
    FLAT_LOAD_UBYTE_D16_HI  = 1238,
1254
    FLAT_LOAD_USHORT  = 1239,
1255
    FLAT_STORE_BYTE = 1240,
1256
    FLAT_STORE_BYTE_D16_HI  = 1241,
1257
    FLAT_STORE_DWORD  = 1242,
1258
    FLAT_STORE_DWORDX2  = 1243,
1259
    FLAT_STORE_DWORDX3  = 1244,
1260
    FLAT_STORE_DWORDX4  = 1245,
1261
    FLAT_STORE_SHORT  = 1246,
1262
    FLAT_STORE_SHORT_D16_HI = 1247,
1263
    GET_GROUPSTATICSIZE = 1248,
1264
    GLOBAL_ATOMIC_ADD = 1249,
1265
    GLOBAL_ATOMIC_ADD_RTN = 1250,
1266
    GLOBAL_ATOMIC_ADD_SADDR = 1251,
1267
    GLOBAL_ATOMIC_ADD_SADDR_RTN = 1252,
1268
    GLOBAL_ATOMIC_ADD_X2  = 1253,
1269
    GLOBAL_ATOMIC_ADD_X2_RTN  = 1254,
1270
    GLOBAL_ATOMIC_ADD_X2_SADDR  = 1255,
1271
    GLOBAL_ATOMIC_ADD_X2_SADDR_RTN  = 1256,
1272
    GLOBAL_ATOMIC_AND = 1257,
1273
    GLOBAL_ATOMIC_AND_RTN = 1258,
1274
    GLOBAL_ATOMIC_AND_SADDR = 1259,
1275
    GLOBAL_ATOMIC_AND_SADDR_RTN = 1260,
1276
    GLOBAL_ATOMIC_AND_X2  = 1261,
1277
    GLOBAL_ATOMIC_AND_X2_RTN  = 1262,
1278
    GLOBAL_ATOMIC_AND_X2_SADDR  = 1263,
1279
    GLOBAL_ATOMIC_AND_X2_SADDR_RTN  = 1264,
1280
    GLOBAL_ATOMIC_CMPSWAP = 1265,
1281
    GLOBAL_ATOMIC_CMPSWAP_RTN = 1266,
1282
    GLOBAL_ATOMIC_CMPSWAP_SADDR = 1267,
1283
    GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN = 1268,
1284
    GLOBAL_ATOMIC_CMPSWAP_X2  = 1269,
1285
    GLOBAL_ATOMIC_CMPSWAP_X2_RTN  = 1270,
1286
    GLOBAL_ATOMIC_CMPSWAP_X2_SADDR  = 1271,
1287
    GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN  = 1272,
1288
    GLOBAL_ATOMIC_DEC = 1273,
1289
    GLOBAL_ATOMIC_DEC_RTN = 1274,
1290
    GLOBAL_ATOMIC_DEC_SADDR = 1275,
1291
    GLOBAL_ATOMIC_DEC_SADDR_RTN = 1276,
1292
    GLOBAL_ATOMIC_DEC_X2  = 1277,
1293
    GLOBAL_ATOMIC_DEC_X2_RTN  = 1278,
1294
    GLOBAL_ATOMIC_DEC_X2_SADDR  = 1279,
1295
    GLOBAL_ATOMIC_DEC_X2_SADDR_RTN  = 1280,
1296
    GLOBAL_ATOMIC_INC = 1281,
1297
    GLOBAL_ATOMIC_INC_RTN = 1282,
1298
    GLOBAL_ATOMIC_INC_SADDR = 1283,
1299
    GLOBAL_ATOMIC_INC_SADDR_RTN = 1284,
1300
    GLOBAL_ATOMIC_INC_X2  = 1285,
1301
    GLOBAL_ATOMIC_INC_X2_RTN  = 1286,
1302
    GLOBAL_ATOMIC_INC_X2_SADDR  = 1287,
1303
    GLOBAL_ATOMIC_INC_X2_SADDR_RTN  = 1288,
1304
    GLOBAL_ATOMIC_OR  = 1289,
1305
    GLOBAL_ATOMIC_OR_RTN  = 1290,
1306
    GLOBAL_ATOMIC_OR_SADDR  = 1291,
1307
    GLOBAL_ATOMIC_OR_SADDR_RTN  = 1292,
1308
    GLOBAL_ATOMIC_OR_X2 = 1293,
1309
    GLOBAL_ATOMIC_OR_X2_RTN = 1294,
1310
    GLOBAL_ATOMIC_OR_X2_SADDR = 1295,
1311
    GLOBAL_ATOMIC_OR_X2_SADDR_RTN = 1296,
1312
    GLOBAL_ATOMIC_SMAX  = 1297,
1313
    GLOBAL_ATOMIC_SMAX_RTN  = 1298,
1314
    GLOBAL_ATOMIC_SMAX_SADDR  = 1299,
1315
    GLOBAL_ATOMIC_SMAX_SADDR_RTN  = 1300,
1316
    GLOBAL_ATOMIC_SMAX_X2 = 1301,
1317
    GLOBAL_ATOMIC_SMAX_X2_RTN = 1302,
1318
    GLOBAL_ATOMIC_SMAX_X2_SADDR = 1303,
1319
    GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN = 1304,
1320
    GLOBAL_ATOMIC_SMIN  = 1305,
1321
    GLOBAL_ATOMIC_SMIN_RTN  = 1306,
1322
    GLOBAL_ATOMIC_SMIN_SADDR  = 1307,
1323
    GLOBAL_ATOMIC_SMIN_SADDR_RTN  = 1308,
1324
    GLOBAL_ATOMIC_SMIN_X2 = 1309,
1325
    GLOBAL_ATOMIC_SMIN_X2_RTN = 1310,
1326
    GLOBAL_ATOMIC_SMIN_X2_SADDR = 1311,
1327
    GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN = 1312,
1328
    GLOBAL_ATOMIC_SUB = 1313,
1329
    GLOBAL_ATOMIC_SUB_RTN = 1314,
1330
    GLOBAL_ATOMIC_SUB_SADDR = 1315,
1331
    GLOBAL_ATOMIC_SUB_SADDR_RTN = 1316,
1332
    GLOBAL_ATOMIC_SUB_X2  = 1317,
1333
    GLOBAL_ATOMIC_SUB_X2_RTN  = 1318,
1334
    GLOBAL_ATOMIC_SUB_X2_SADDR  = 1319,
1335
    GLOBAL_ATOMIC_SUB_X2_SADDR_RTN  = 1320,
1336
    GLOBAL_ATOMIC_SWAP  = 1321,
1337
    GLOBAL_ATOMIC_SWAP_RTN  = 1322,
1338
    GLOBAL_ATOMIC_SWAP_SADDR  = 1323,
1339
    GLOBAL_ATOMIC_SWAP_SADDR_RTN  = 1324,
1340
    GLOBAL_ATOMIC_SWAP_X2 = 1325,
1341
    GLOBAL_ATOMIC_SWAP_X2_RTN = 1326,
1342
    GLOBAL_ATOMIC_SWAP_X2_SADDR = 1327,
1343
    GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN = 1328,
1344
    GLOBAL_ATOMIC_UMAX  = 1329,
1345
    GLOBAL_ATOMIC_UMAX_RTN  = 1330,
1346
    GLOBAL_ATOMIC_UMAX_SADDR  = 1331,
1347
    GLOBAL_ATOMIC_UMAX_SADDR_RTN  = 1332,
1348
    GLOBAL_ATOMIC_UMAX_X2 = 1333,
1349
    GLOBAL_ATOMIC_UMAX_X2_RTN = 1334,
1350
    GLOBAL_ATOMIC_UMAX_X2_SADDR = 1335,
1351
    GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN = 1336,
1352
    GLOBAL_ATOMIC_UMIN  = 1337,
1353
    GLOBAL_ATOMIC_UMIN_RTN  = 1338,
1354
    GLOBAL_ATOMIC_UMIN_SADDR  = 1339,
1355
    GLOBAL_ATOMIC_UMIN_SADDR_RTN  = 1340,
1356
    GLOBAL_ATOMIC_UMIN_X2 = 1341,
1357
    GLOBAL_ATOMIC_UMIN_X2_RTN = 1342,
1358
    GLOBAL_ATOMIC_UMIN_X2_SADDR = 1343,
1359
    GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN = 1344,
1360
    GLOBAL_ATOMIC_XOR = 1345,
1361
    GLOBAL_ATOMIC_XOR_RTN = 1346,
1362
    GLOBAL_ATOMIC_XOR_SADDR = 1347,
1363
    GLOBAL_ATOMIC_XOR_SADDR_RTN = 1348,
1364
    GLOBAL_ATOMIC_XOR_X2  = 1349,
1365
    GLOBAL_ATOMIC_XOR_X2_RTN  = 1350,
1366
    GLOBAL_ATOMIC_XOR_X2_SADDR  = 1351,
1367
    GLOBAL_ATOMIC_XOR_X2_SADDR_RTN  = 1352,
1368
    GLOBAL_LOAD_DWORD = 1353,
1369
    GLOBAL_LOAD_DWORDX2 = 1354,
1370
    GLOBAL_LOAD_DWORDX2_SADDR = 1355,
1371
    GLOBAL_LOAD_DWORDX3 = 1356,
1372
    GLOBAL_LOAD_DWORDX3_SADDR = 1357,
1373
    GLOBAL_LOAD_DWORDX4 = 1358,
1374
    GLOBAL_LOAD_DWORDX4_SADDR = 1359,
1375
    GLOBAL_LOAD_DWORD_SADDR = 1360,
1376
    GLOBAL_LOAD_SBYTE = 1361,
1377
    GLOBAL_LOAD_SBYTE_D16 = 1362,
1378
    GLOBAL_LOAD_SBYTE_D16_HI  = 1363,
1379
    GLOBAL_LOAD_SBYTE_D16_HI_SADDR  = 1364,
1380
    GLOBAL_LOAD_SBYTE_D16_SADDR = 1365,
1381
    GLOBAL_LOAD_SBYTE_SADDR = 1366,
1382
    GLOBAL_LOAD_SHORT_D16 = 1367,
1383
    GLOBAL_LOAD_SHORT_D16_HI  = 1368,
1384
    GLOBAL_LOAD_SHORT_D16_HI_SADDR  = 1369,
1385
    GLOBAL_LOAD_SHORT_D16_SADDR = 1370,
1386
    GLOBAL_LOAD_SSHORT  = 1371,
1387
    GLOBAL_LOAD_SSHORT_SADDR  = 1372,
1388
    GLOBAL_LOAD_UBYTE = 1373,
1389
    GLOBAL_LOAD_UBYTE_D16 = 1374,
1390
    GLOBAL_LOAD_UBYTE_D16_HI  = 1375,
1391
    GLOBAL_LOAD_UBYTE_D16_HI_SADDR  = 1376,
1392
    GLOBAL_LOAD_UBYTE_D16_SADDR = 1377,
1393
    GLOBAL_LOAD_UBYTE_SADDR = 1378,
1394
    GLOBAL_LOAD_USHORT  = 1379,
1395
    GLOBAL_LOAD_USHORT_SADDR  = 1380,
1396
    GLOBAL_STORE_BYTE = 1381,
1397
    GLOBAL_STORE_BYTE_D16_HI  = 1382,
1398
    GLOBAL_STORE_BYTE_D16_HI_SADDR  = 1383,
1399
    GLOBAL_STORE_BYTE_SADDR = 1384,
1400
    GLOBAL_STORE_DWORD  = 1385,
1401
    GLOBAL_STORE_DWORDX2  = 1386,
1402
    GLOBAL_STORE_DWORDX2_SADDR  = 1387,
1403
    GLOBAL_STORE_DWORDX3  = 1388,
1404
    GLOBAL_STORE_DWORDX3_SADDR  = 1389,
1405
    GLOBAL_STORE_DWORDX4  = 1390,
1406
    GLOBAL_STORE_DWORDX4_SADDR  = 1391,
1407
    GLOBAL_STORE_DWORD_SADDR  = 1392,
1408
    GLOBAL_STORE_SHORT  = 1393,
1409
    GLOBAL_STORE_SHORT_D16_HI = 1394,
1410
    GLOBAL_STORE_SHORT_D16_HI_SADDR = 1395,
1411
    GLOBAL_STORE_SHORT_SADDR  = 1396,
1412
    SCRATCH_LOAD_DWORD  = 1397,
1413
    SCRATCH_LOAD_DWORDX2  = 1398,
1414
    SCRATCH_LOAD_DWORDX2_SADDR  = 1399,
1415
    SCRATCH_LOAD_DWORDX3  = 1400,
1416
    SCRATCH_LOAD_DWORDX3_SADDR  = 1401,
1417
    SCRATCH_LOAD_DWORDX4  = 1402,
1418
    SCRATCH_LOAD_DWORDX4_SADDR  = 1403,
1419
    SCRATCH_LOAD_DWORD_SADDR  = 1404,
1420
    SCRATCH_LOAD_SBYTE  = 1405,
1421
    SCRATCH_LOAD_SBYTE_D16  = 1406,
1422
    SCRATCH_LOAD_SBYTE_D16_HI = 1407,
1423
    SCRATCH_LOAD_SBYTE_D16_HI_SADDR = 1408,
1424
    SCRATCH_LOAD_SBYTE_D16_SADDR  = 1409,
1425
    SCRATCH_LOAD_SBYTE_SADDR  = 1410,
1426
    SCRATCH_LOAD_SHORT_D16  = 1411,
1427
    SCRATCH_LOAD_SHORT_D16_HI = 1412,
1428
    SCRATCH_LOAD_SHORT_D16_HI_SADDR = 1413,
1429
    SCRATCH_LOAD_SHORT_D16_SADDR  = 1414,
1430
    SCRATCH_LOAD_SSHORT = 1415,
1431
    SCRATCH_LOAD_SSHORT_SADDR = 1416,
1432
    SCRATCH_LOAD_UBYTE  = 1417,
1433
    SCRATCH_LOAD_UBYTE_D16  = 1418,
1434
    SCRATCH_LOAD_UBYTE_D16_HI = 1419,
1435
    SCRATCH_LOAD_UBYTE_D16_HI_SADDR = 1420,
1436
    SCRATCH_LOAD_UBYTE_D16_SADDR  = 1421,
1437
    SCRATCH_LOAD_UBYTE_SADDR  = 1422,
1438
    SCRATCH_LOAD_USHORT = 1423,
1439
    SCRATCH_LOAD_USHORT_SADDR = 1424,
1440
    SCRATCH_STORE_BYTE  = 1425,
1441
    SCRATCH_STORE_BYTE_D16_HI = 1426,
1442
    SCRATCH_STORE_BYTE_D16_HI_SADDR = 1427,
1443
    SCRATCH_STORE_BYTE_SADDR  = 1428,
1444
    SCRATCH_STORE_DWORD = 1429,
1445
    SCRATCH_STORE_DWORDX2 = 1430,
1446
    SCRATCH_STORE_DWORDX2_SADDR = 1431,
1447
    SCRATCH_STORE_DWORDX3 = 1432,
1448
    SCRATCH_STORE_DWORDX3_SADDR = 1433,
1449
    SCRATCH_STORE_DWORDX4 = 1434,
1450
    SCRATCH_STORE_DWORDX4_SADDR = 1435,
1451
    SCRATCH_STORE_DWORD_SADDR = 1436,
1452
    SCRATCH_STORE_SHORT = 1437,
1453
    SCRATCH_STORE_SHORT_D16_HI  = 1438,
1454
    SCRATCH_STORE_SHORT_D16_HI_SADDR  = 1439,
1455
    SCRATCH_STORE_SHORT_SADDR = 1440,
1456
    SI_BREAK  = 1441,
1457
    SI_BR_UNDEF = 1442,
1458
    SI_CALL = 1443,
1459
    SI_CALL_ISEL  = 1444,
1460
    SI_ELSE = 1445,
1461
    SI_ELSE_BREAK = 1446,
1462
    SI_END_CF = 1447,
1463
    SI_IF = 1448,
1464
    SI_IF_BREAK = 1449,
1465
    SI_ILLEGAL_COPY = 1450,
1466
    SI_INDIRECT_DST_V1  = 1451,
1467
    SI_INDIRECT_DST_V16 = 1452,
1468
    SI_INDIRECT_DST_V2  = 1453,
1469
    SI_INDIRECT_DST_V4  = 1454,
1470
    SI_INDIRECT_DST_V8  = 1455,
1471
    SI_INDIRECT_SRC_V1  = 1456,
1472
    SI_INDIRECT_SRC_V16 = 1457,
1473
    SI_INDIRECT_SRC_V2  = 1458,
1474
    SI_INDIRECT_SRC_V4  = 1459,
1475
    SI_INDIRECT_SRC_V8  = 1460,
1476
    SI_INIT_EXEC  = 1461,
1477
    SI_INIT_EXEC_FROM_INPUT = 1462,
1478
    SI_INIT_M0  = 1463,
1479
    SI_KILL_F32_COND_IMM_PSEUDO = 1464,
1480
    SI_KILL_F32_COND_IMM_TERMINATOR = 1465,
1481
    SI_KILL_I1_PSEUDO = 1466,
1482
    SI_KILL_I1_TERMINATOR = 1467,
1483
    SI_LOOP = 1468,
1484
    SI_MASKED_UNREACHABLE = 1469,
1485
    SI_MASK_BRANCH  = 1470,
1486
    SI_NON_UNIFORM_BRCOND_PSEUDO  = 1471,
1487
    SI_PC_ADD_REL_OFFSET  = 1472,
1488
    SI_PS_LIVE  = 1473,
1489
    SI_RETURN = 1474,
1490
    SI_RETURN_TO_EPILOG = 1475,
1491
    SI_SPILL_S128_RESTORE = 1476,
1492
    SI_SPILL_S128_SAVE  = 1477,
1493
    SI_SPILL_S256_RESTORE = 1478,
1494
    SI_SPILL_S256_SAVE  = 1479,
1495
    SI_SPILL_S32_RESTORE  = 1480,
1496
    SI_SPILL_S32_SAVE = 1481,
1497
    SI_SPILL_S512_RESTORE = 1482,
1498
    SI_SPILL_S512_SAVE  = 1483,
1499
    SI_SPILL_S64_RESTORE  = 1484,
1500
    SI_SPILL_S64_SAVE = 1485,
1501
    SI_SPILL_V128_RESTORE = 1486,
1502
    SI_SPILL_V128_SAVE  = 1487,
1503
    SI_SPILL_V256_RESTORE = 1488,
1504
    SI_SPILL_V256_SAVE  = 1489,
1505
    SI_SPILL_V32_RESTORE  = 1490,
1506
    SI_SPILL_V32_SAVE = 1491,
1507
    SI_SPILL_V512_RESTORE = 1492,
1508
    SI_SPILL_V512_SAVE  = 1493,
1509
    SI_SPILL_V64_RESTORE  = 1494,
1510
    SI_SPILL_V64_SAVE = 1495,
1511
    SI_SPILL_V96_RESTORE  = 1496,
1512
    SI_SPILL_V96_SAVE = 1497,
1513
    SI_TCRETURN = 1498,
1514
    SI_TCRETURN_ISEL  = 1499,
1515
    S_ABSDIFF_I32 = 1500,
1516
    S_ABS_I32 = 1501,
1517
    S_ADDC_U32  = 1502,
1518
    S_ADDK_I32  = 1503,
1519
    S_ADD_I32 = 1504,
1520
    S_ADD_U32 = 1505,
1521
    S_ADD_U64_CO_PSEUDO = 1506,
1522
    S_ADD_U64_PSEUDO  = 1507,
1523
    S_ANDN1_SAVEEXEC_B64  = 1508,
1524
    S_ANDN1_WREXEC_B64  = 1509,
1525
    S_ANDN2_B32 = 1510,
1526
    S_ANDN2_B64 = 1511,
1527
    S_ANDN2_B64_term  = 1512,
1528
    S_ANDN2_SAVEEXEC_B64  = 1513,
1529
    S_ANDN2_WREXEC_B64  = 1514,
1530
    S_AND_B32 = 1515,
1531
    S_AND_B64 = 1516,
1532
    S_AND_SAVEEXEC_B64  = 1517,
1533
    S_ASHR_I32  = 1518,
1534
    S_ASHR_I64  = 1519,
1535
    S_ATC_PROBE_BUFFER_IMM  = 1520,
1536
    S_ATC_PROBE_BUFFER_SGPR = 1521,
1537
    S_ATC_PROBE_IMM = 1522,
1538
    S_ATC_PROBE_SGPR  = 1523,
1539
    S_ATOMIC_ADD_IMM  = 1524,
1540
    S_ATOMIC_ADD_IMM_RTN  = 1525,
1541
    S_ATOMIC_ADD_SGPR = 1526,
1542
    S_ATOMIC_ADD_SGPR_RTN = 1527,
1543
    S_ATOMIC_ADD_X2_IMM = 1528,
1544
    S_ATOMIC_ADD_X2_IMM_RTN = 1529,
1545
    S_ATOMIC_ADD_X2_SGPR  = 1530,
1546
    S_ATOMIC_ADD_X2_SGPR_RTN  = 1531,
1547
    S_ATOMIC_AND_IMM  = 1532,
1548
    S_ATOMIC_AND_IMM_RTN  = 1533,
1549
    S_ATOMIC_AND_SGPR = 1534,
1550
    S_ATOMIC_AND_SGPR_RTN = 1535,
1551
    S_ATOMIC_AND_X2_IMM = 1536,
1552
    S_ATOMIC_AND_X2_IMM_RTN = 1537,
1553
    S_ATOMIC_AND_X2_SGPR  = 1538,
1554
    S_ATOMIC_AND_X2_SGPR_RTN  = 1539,
1555
    S_ATOMIC_CMPSWAP_IMM  = 1540,
1556
    S_ATOMIC_CMPSWAP_IMM_RTN  = 1541,
1557
    S_ATOMIC_CMPSWAP_SGPR = 1542,
1558
    S_ATOMIC_CMPSWAP_SGPR_RTN = 1543,
1559
    S_ATOMIC_CMPSWAP_X2_IMM = 1544,
1560
    S_ATOMIC_CMPSWAP_X2_IMM_RTN = 1545,
1561
    S_ATOMIC_CMPSWAP_X2_SGPR  = 1546,
1562
    S_ATOMIC_CMPSWAP_X2_SGPR_RTN  = 1547,
1563
    S_ATOMIC_DEC_IMM  = 1548,
1564
    S_ATOMIC_DEC_IMM_RTN  = 1549,
1565
    S_ATOMIC_DEC_SGPR = 1550,
1566
    S_ATOMIC_DEC_SGPR_RTN = 1551,
1567
    S_ATOMIC_DEC_X2_IMM = 1552,
1568
    S_ATOMIC_DEC_X2_IMM_RTN = 1553,
1569
    S_ATOMIC_DEC_X2_SGPR  = 1554,
1570
    S_ATOMIC_DEC_X2_SGPR_RTN  = 1555,
1571
    S_ATOMIC_INC_IMM  = 1556,
1572
    S_ATOMIC_INC_IMM_RTN  = 1557,
1573
    S_ATOMIC_INC_SGPR = 1558,
1574
    S_ATOMIC_INC_SGPR_RTN = 1559,
1575
    S_ATOMIC_INC_X2_IMM = 1560,
1576
    S_ATOMIC_INC_X2_IMM_RTN = 1561,
1577
    S_ATOMIC_INC_X2_SGPR  = 1562,
1578
    S_ATOMIC_INC_X2_SGPR_RTN  = 1563,
1579
    S_ATOMIC_OR_IMM = 1564,
1580
    S_ATOMIC_OR_IMM_RTN = 1565,
1581
    S_ATOMIC_OR_SGPR  = 1566,
1582
    S_ATOMIC_OR_SGPR_RTN  = 1567,
1583
    S_ATOMIC_OR_X2_IMM  = 1568,
1584
    S_ATOMIC_OR_X2_IMM_RTN  = 1569,
1585
    S_ATOMIC_OR_X2_SGPR = 1570,
1586
    S_ATOMIC_OR_X2_SGPR_RTN = 1571,
1587
    S_ATOMIC_SMAX_IMM = 1572,
1588
    S_ATOMIC_SMAX_IMM_RTN = 1573,
1589
    S_ATOMIC_SMAX_SGPR  = 1574,
1590
    S_ATOMIC_SMAX_SGPR_RTN  = 1575,
1591
    S_ATOMIC_SMAX_X2_IMM  = 1576,
1592
    S_ATOMIC_SMAX_X2_IMM_RTN  = 1577,
1593
    S_ATOMIC_SMAX_X2_SGPR = 1578,
1594
    S_ATOMIC_SMAX_X2_SGPR_RTN = 1579,
1595
    S_ATOMIC_SMIN_IMM = 1580,
1596
    S_ATOMIC_SMIN_IMM_RTN = 1581,
1597
    S_ATOMIC_SMIN_SGPR  = 1582,
1598
    S_ATOMIC_SMIN_SGPR_RTN  = 1583,
1599
    S_ATOMIC_SMIN_X2_IMM  = 1584,
1600
    S_ATOMIC_SMIN_X2_IMM_RTN  = 1585,
1601
    S_ATOMIC_SMIN_X2_SGPR = 1586,
1602
    S_ATOMIC_SMIN_X2_SGPR_RTN = 1587,
1603
    S_ATOMIC_SUB_IMM  = 1588,
1604
    S_ATOMIC_SUB_IMM_RTN  = 1589,
1605
    S_ATOMIC_SUB_SGPR = 1590,
1606
    S_ATOMIC_SUB_SGPR_RTN = 1591,
1607
    S_ATOMIC_SUB_X2_IMM = 1592,
1608
    S_ATOMIC_SUB_X2_IMM_RTN = 1593,
1609
    S_ATOMIC_SUB_X2_SGPR  = 1594,
1610
    S_ATOMIC_SUB_X2_SGPR_RTN  = 1595,
1611
    S_ATOMIC_SWAP_IMM = 1596,
1612
    S_ATOMIC_SWAP_IMM_RTN = 1597,
1613
    S_ATOMIC_SWAP_SGPR  = 1598,
1614
    S_ATOMIC_SWAP_SGPR_RTN  = 1599,
1615
    S_ATOMIC_SWAP_X2_IMM  = 1600,
1616
    S_ATOMIC_SWAP_X2_IMM_RTN  = 1601,
1617
    S_ATOMIC_SWAP_X2_SGPR = 1602,
1618
    S_ATOMIC_SWAP_X2_SGPR_RTN = 1603,
1619
    S_ATOMIC_UMAX_IMM = 1604,
1620
    S_ATOMIC_UMAX_IMM_RTN = 1605,
1621
    S_ATOMIC_UMAX_SGPR  = 1606,
1622
    S_ATOMIC_UMAX_SGPR_RTN  = 1607,
1623
    S_ATOMIC_UMAX_X2_IMM  = 1608,
1624
    S_ATOMIC_UMAX_X2_IMM_RTN  = 1609,
1625
    S_ATOMIC_UMAX_X2_SGPR = 1610,
1626
    S_ATOMIC_UMAX_X2_SGPR_RTN = 1611,
1627
    S_ATOMIC_UMIN_IMM = 1612,
1628
    S_ATOMIC_UMIN_IMM_RTN = 1613,
1629
    S_ATOMIC_UMIN_SGPR  = 1614,
1630
    S_ATOMIC_UMIN_SGPR_RTN  = 1615,
1631
    S_ATOMIC_UMIN_X2_IMM  = 1616,
1632
    S_ATOMIC_UMIN_X2_IMM_RTN  = 1617,
1633
    S_ATOMIC_UMIN_X2_SGPR = 1618,
1634
    S_ATOMIC_UMIN_X2_SGPR_RTN = 1619,
1635
    S_ATOMIC_XOR_IMM  = 1620,
1636
    S_ATOMIC_XOR_IMM_RTN  = 1621,
1637
    S_ATOMIC_XOR_SGPR = 1622,
1638
    S_ATOMIC_XOR_SGPR_RTN = 1623,
1639
    S_ATOMIC_XOR_X2_IMM = 1624,
1640
    S_ATOMIC_XOR_X2_IMM_RTN = 1625,
1641
    S_ATOMIC_XOR_X2_SGPR  = 1626,
1642
    S_ATOMIC_XOR_X2_SGPR_RTN  = 1627,
1643
    S_BCNT0_I32_B32 = 1628,
1644
    S_BCNT0_I32_B64 = 1629,
1645
    S_BCNT1_I32_B32 = 1630,
1646
    S_BCNT1_I32_B64 = 1631,
1647
    S_BFE_I32 = 1632,
1648
    S_BFE_I64 = 1633,
1649
    S_BFE_U32 = 1634,
1650
    S_BFE_U64 = 1635,
1651
    S_BFM_B32 = 1636,
1652
    S_BFM_B64 = 1637,
1653
    S_BITREPLICATE_B64_B32  = 1638,
1654
    S_BITSET0_B32 = 1639,
1655
    S_BITSET0_B64 = 1640,
1656
    S_BITSET1_B32 = 1641,
1657
    S_BITSET1_B64 = 1642,
1658
    S_BREV_B32  = 1643,
1659
    S_BREV_B64  = 1644,
1660
    S_BUFFER_ATOMIC_ADD_IMM = 1645,
1661
    S_BUFFER_ATOMIC_ADD_IMM_RTN = 1646,
1662
    S_BUFFER_ATOMIC_ADD_SGPR  = 1647,
1663
    S_BUFFER_ATOMIC_ADD_SGPR_RTN  = 1648,
1664
    S_BUFFER_ATOMIC_ADD_X2_IMM  = 1649,
1665
    S_BUFFER_ATOMIC_ADD_X2_IMM_RTN  = 1650,
1666
    S_BUFFER_ATOMIC_ADD_X2_SGPR = 1651,
1667
    S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN = 1652,
1668
    S_BUFFER_ATOMIC_AND_IMM = 1653,
1669
    S_BUFFER_ATOMIC_AND_IMM_RTN = 1654,
1670
    S_BUFFER_ATOMIC_AND_SGPR  = 1655,
1671
    S_BUFFER_ATOMIC_AND_SGPR_RTN  = 1656,
1672
    S_BUFFER_ATOMIC_AND_X2_IMM  = 1657,
1673
    S_BUFFER_ATOMIC_AND_X2_IMM_RTN  = 1658,
1674
    S_BUFFER_ATOMIC_AND_X2_SGPR = 1659,
1675
    S_BUFFER_ATOMIC_AND_X2_SGPR_RTN = 1660,
1676
    S_BUFFER_ATOMIC_CMPSWAP_IMM = 1661,
1677
    S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN = 1662,
1678
    S_BUFFER_ATOMIC_CMPSWAP_SGPR  = 1663,
1679
    S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN  = 1664,
1680
    S_BUFFER_ATOMIC_CMPSWAP_X2_IMM  = 1665,
1681
    S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN  = 1666,
1682
    S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR = 1667,
1683
    S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN = 1668,
1684
    S_BUFFER_ATOMIC_DEC_IMM = 1669,
1685
    S_BUFFER_ATOMIC_DEC_IMM_RTN = 1670,
1686
    S_BUFFER_ATOMIC_DEC_SGPR  = 1671,
1687
    S_BUFFER_ATOMIC_DEC_SGPR_RTN  = 1672,
1688
    S_BUFFER_ATOMIC_DEC_X2_IMM  = 1673,
1689
    S_BUFFER_ATOMIC_DEC_X2_IMM_RTN  = 1674,
1690
    S_BUFFER_ATOMIC_DEC_X2_SGPR = 1675,
1691
    S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN = 1676,
1692
    S_BUFFER_ATOMIC_INC_IMM = 1677,
1693
    S_BUFFER_ATOMIC_INC_IMM_RTN = 1678,
1694
    S_BUFFER_ATOMIC_INC_SGPR  = 1679,
1695
    S_BUFFER_ATOMIC_INC_SGPR_RTN  = 1680,
1696
    S_BUFFER_ATOMIC_INC_X2_IMM  = 1681,
1697
    S_BUFFER_ATOMIC_INC_X2_IMM_RTN  = 1682,
1698
    S_BUFFER_ATOMIC_INC_X2_SGPR = 1683,
1699
    S_BUFFER_ATOMIC_INC_X2_SGPR_RTN = 1684,
1700
    S_BUFFER_ATOMIC_OR_IMM  = 1685,
1701
    S_BUFFER_ATOMIC_OR_IMM_RTN  = 1686,
1702
    S_BUFFER_ATOMIC_OR_SGPR = 1687,
1703
    S_BUFFER_ATOMIC_OR_SGPR_RTN = 1688,
1704
    S_BUFFER_ATOMIC_OR_X2_IMM = 1689,
1705
    S_BUFFER_ATOMIC_OR_X2_IMM_RTN = 1690,
1706
    S_BUFFER_ATOMIC_OR_X2_SGPR  = 1691,
1707
    S_BUFFER_ATOMIC_OR_X2_SGPR_RTN  = 1692,
1708
    S_BUFFER_ATOMIC_SMAX_IMM  = 1693,
1709
    S_BUFFER_ATOMIC_SMAX_IMM_RTN  = 1694,
1710
    S_BUFFER_ATOMIC_SMAX_SGPR = 1695,
1711
    S_BUFFER_ATOMIC_SMAX_SGPR_RTN = 1696,
1712
    S_BUFFER_ATOMIC_SMAX_X2_IMM = 1697,
1713
    S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN = 1698,
1714
    S_BUFFER_ATOMIC_SMAX_X2_SGPR  = 1699,
1715
    S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN  = 1700,
1716
    S_BUFFER_ATOMIC_SMIN_IMM  = 1701,
1717
    S_BUFFER_ATOMIC_SMIN_IMM_RTN  = 1702,
1718
    S_BUFFER_ATOMIC_SMIN_SGPR = 1703,
1719
    S_BUFFER_ATOMIC_SMIN_SGPR_RTN = 1704,
1720
    S_BUFFER_ATOMIC_SMIN_X2_IMM = 1705,
1721
    S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN = 1706,
1722
    S_BUFFER_ATOMIC_SMIN_X2_SGPR  = 1707,
1723
    S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN  = 1708,
1724
    S_BUFFER_ATOMIC_SUB_IMM = 1709,
1725
    S_BUFFER_ATOMIC_SUB_IMM_RTN = 1710,
1726
    S_BUFFER_ATOMIC_SUB_SGPR  = 1711,
1727
    S_BUFFER_ATOMIC_SUB_SGPR_RTN  = 1712,
1728
    S_BUFFER_ATOMIC_SUB_X2_IMM  = 1713,
1729
    S_BUFFER_ATOMIC_SUB_X2_IMM_RTN  = 1714,
1730
    S_BUFFER_ATOMIC_SUB_X2_SGPR = 1715,
1731
    S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN = 1716,
1732
    S_BUFFER_ATOMIC_SWAP_IMM  = 1717,
1733
    S_BUFFER_ATOMIC_SWAP_IMM_RTN  = 1718,
1734
    S_BUFFER_ATOMIC_SWAP_SGPR = 1719,
1735
    S_BUFFER_ATOMIC_SWAP_SGPR_RTN = 1720,
1736
    S_BUFFER_ATOMIC_SWAP_X2_IMM = 1721,
1737
    S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN = 1722,
1738
    S_BUFFER_ATOMIC_SWAP_X2_SGPR  = 1723,
1739
    S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN  = 1724,
1740
    S_BUFFER_ATOMIC_UMAX_IMM  = 1725,
1741
    S_BUFFER_ATOMIC_UMAX_IMM_RTN  = 1726,
1742
    S_BUFFER_ATOMIC_UMAX_SGPR = 1727,
1743
    S_BUFFER_ATOMIC_UMAX_SGPR_RTN = 1728,
1744
    S_BUFFER_ATOMIC_UMAX_X2_IMM = 1729,
1745
    S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN = 1730,
1746
    S_BUFFER_ATOMIC_UMAX_X2_SGPR  = 1731,
1747
    S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN  = 1732,
1748
    S_BUFFER_ATOMIC_UMIN_IMM  = 1733,
1749
    S_BUFFER_ATOMIC_UMIN_IMM_RTN  = 1734,
1750
    S_BUFFER_ATOMIC_UMIN_SGPR = 1735,
1751
    S_BUFFER_ATOMIC_UMIN_SGPR_RTN = 1736,
1752
    S_BUFFER_ATOMIC_UMIN_X2_IMM = 1737,
1753
    S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN = 1738,
1754
    S_BUFFER_ATOMIC_UMIN_X2_SGPR  = 1739,
1755
    S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN  = 1740,
1756
    S_BUFFER_ATOMIC_XOR_IMM = 1741,
1757
    S_BUFFER_ATOMIC_XOR_IMM_RTN = 1742,
1758
    S_BUFFER_ATOMIC_XOR_SGPR  = 1743,
1759
    S_BUFFER_ATOMIC_XOR_SGPR_RTN  = 1744,
1760
    S_BUFFER_ATOMIC_XOR_X2_IMM  = 1745,
1761
    S_BUFFER_ATOMIC_XOR_X2_IMM_RTN  = 1746,
1762
    S_BUFFER_ATOMIC_XOR_X2_SGPR = 1747,
1763
    S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN = 1748,
1764
    S_BUFFER_LOAD_DWORDX16_IMM  = 1749,
1765
    S_BUFFER_LOAD_DWORDX16_SGPR = 1750,
1766
    S_BUFFER_LOAD_DWORDX2_IMM = 1751,
1767
    S_BUFFER_LOAD_DWORDX2_SGPR  = 1752,
1768
    S_BUFFER_LOAD_DWORDX4_IMM = 1753,
1769
    S_BUFFER_LOAD_DWORDX4_SGPR  = 1754,
1770
    S_BUFFER_LOAD_DWORDX8_IMM = 1755,
1771
    S_BUFFER_LOAD_DWORDX8_SGPR  = 1756,
1772
    S_BUFFER_LOAD_DWORD_IMM = 1757,
1773
    S_BUFFER_LOAD_DWORD_SGPR  = 1758,
1774
    S_BUFFER_STORE_DWORDX2_IMM  = 1759,
1775
    S_BUFFER_STORE_DWORDX2_SGPR = 1760,
1776
    S_BUFFER_STORE_DWORDX4_IMM  = 1761,
1777
    S_BUFFER_STORE_DWORDX4_SGPR = 1762,
1778
    S_BUFFER_STORE_DWORD_IMM  = 1763,
1779
    S_BUFFER_STORE_DWORD_SGPR = 1764,
1780
    S_CALL_B64  = 1765,
1781
    S_CBRANCH_G_FORK  = 1766,
1782
    S_CBRANCH_I_FORK  = 1767,
1783
    S_CBRANCH_JOIN  = 1768,
1784
    S_CMOVK_I32 = 1769,
1785
    S_CMOV_B32  = 1770,
1786
    S_CMOV_B64  = 1771,
1787
    S_CMPK_EQ_I32 = 1772,
1788
    S_CMPK_EQ_U32 = 1773,
1789
    S_CMPK_GE_I32 = 1774,
1790
    S_CMPK_GE_U32 = 1775,
1791
    S_CMPK_GT_I32 = 1776,
1792
    S_CMPK_GT_U32 = 1777,
1793
    S_CMPK_LE_I32 = 1778,
1794
    S_CMPK_LE_U32 = 1779,
1795
    S_CMPK_LG_I32 = 1780,
1796
    S_CMPK_LG_U32 = 1781,
1797
    S_CMPK_LT_I32 = 1782,
1798
    S_CMPK_LT_U32 = 1783,
1799
    S_CSELECT_B32 = 1784,
1800
    S_CSELECT_B64 = 1785,
1801
    S_DCACHE_DISCARD_IMM  = 1786,
1802
    S_DCACHE_DISCARD_SGPR = 1787,
1803
    S_DCACHE_DISCARD_X2_IMM = 1788,
1804
    S_DCACHE_DISCARD_X2_SGPR  = 1789,
1805
    S_DCACHE_INV  = 1790,
1806
    S_DCACHE_INV_VOL  = 1791,
1807
    S_DCACHE_WB = 1792,
1808
    S_DCACHE_WB_VOL = 1793,
1809
    S_FF0_I32_B32 = 1794,
1810
    S_FF0_I32_B64 = 1795,
1811
    S_FF1_I32_B32 = 1796,
1812
    S_FF1_I32_B64 = 1797,
1813
    S_FLBIT_I32 = 1798,
1814
    S_FLBIT_I32_B32 = 1799,
1815
    S_FLBIT_I32_B64 = 1800,
1816
    S_FLBIT_I32_I64 = 1801,
1817
    S_GETPC_B64 = 1802,
1818
    S_GETREG_B32  = 1803,
1819
    S_LOAD_DWORDX16_IMM = 1804,
1820
    S_LOAD_DWORDX16_SGPR  = 1805,
1821
    S_LOAD_DWORDX2_IMM  = 1806,
1822
    S_LOAD_DWORDX2_SGPR = 1807,
1823
    S_LOAD_DWORDX4_IMM  = 1808,
1824
    S_LOAD_DWORDX4_SGPR = 1809,
1825
    S_LOAD_DWORDX8_IMM  = 1810,
1826
    S_LOAD_DWORDX8_SGPR = 1811,
1827
    S_LOAD_DWORD_IMM  = 1812,
1828
    S_LOAD_DWORD_SGPR = 1813,
1829
    S_LSHL1_ADD_U32 = 1814,
1830
    S_LSHL2_ADD_U32 = 1815,
1831
    S_LSHL3_ADD_U32 = 1816,
1832
    S_LSHL4_ADD_U32 = 1817,
1833
    S_LSHL_B32  = 1818,
1834
    S_LSHL_B64  = 1819,
1835
    S_LSHR_B32  = 1820,
1836
    S_LSHR_B64  = 1821,
1837
    S_MAX_I32 = 1822,
1838
    S_MAX_U32 = 1823,
1839
    S_MEMREALTIME = 1824,
1840
    S_MEMTIME = 1825,
1841
    S_MIN_I32 = 1826,
1842
    S_MIN_U32 = 1827,
1843
    S_MOVK_I32  = 1828,
1844
    S_MOVRELD_B32 = 1829,
1845
    S_MOVRELD_B64 = 1830,
1846
    S_MOVRELS_B32 = 1831,
1847
    S_MOVRELS_B64 = 1832,
1848
    S_MOV_B32 = 1833,
1849
    S_MOV_B64 = 1834,
1850
    S_MOV_B64_term  = 1835,
1851
    S_MOV_FED_B32 = 1836,
1852
    S_MOV_REGRD_B32 = 1837,
1853
    S_MULK_I32  = 1838,
1854
    S_MUL_HI_I32  = 1839,
1855
    S_MUL_HI_U32  = 1840,
1856
    S_MUL_I32 = 1841,
1857
    S_NAND_B32  = 1842,
1858
    S_NAND_B64  = 1843,
1859
    S_NAND_SAVEEXEC_B64 = 1844,
1860
    S_NOR_B32 = 1845,
1861
    S_NOR_B64 = 1846,
1862
    S_NOR_SAVEEXEC_B64  = 1847,
1863
    S_NOT_B32 = 1848,
1864
    S_NOT_B64 = 1849,
1865
    S_ORN1_SAVEEXEC_B64 = 1850,
1866
    S_ORN2_B32  = 1851,
1867
    S_ORN2_B64  = 1852,
1868
    S_ORN2_SAVEEXEC_B64 = 1853,
1869
    S_OR_B32  = 1854,
1870
    S_OR_B64  = 1855,
1871
    S_OR_SAVEEXEC_B64 = 1856,
1872
    S_PACK_HH_B32_B16 = 1857,
1873
    S_PACK_LH_B32_B16 = 1858,
1874
    S_PACK_LL_B32_B16 = 1859,
1875
    S_QUADMASK_B32  = 1860,
1876
    S_QUADMASK_B64  = 1861,
1877
    S_RFE_B64 = 1862,
1878
    S_RFE_RESTORE_B64 = 1863,
1879
    S_SCRATCH_LOAD_DWORDX2_IMM  = 1864,
1880
    S_SCRATCH_LOAD_DWORDX2_SGPR = 1865,
1881
    S_SCRATCH_LOAD_DWORDX4_IMM  = 1866,
1882
    S_SCRATCH_LOAD_DWORDX4_SGPR = 1867,
1883
    S_SCRATCH_LOAD_DWORD_IMM  = 1868,
1884
    S_SCRATCH_LOAD_DWORD_SGPR = 1869,
1885
    S_SCRATCH_STORE_DWORDX2_IMM = 1870,
1886
    S_SCRATCH_STORE_DWORDX2_SGPR  = 1871,
1887
    S_SCRATCH_STORE_DWORDX4_IMM = 1872,
1888
    S_SCRATCH_STORE_DWORDX4_SGPR  = 1873,
1889
    S_SCRATCH_STORE_DWORD_IMM = 1874,
1890
    S_SCRATCH_STORE_DWORD_SGPR  = 1875,
1891
    S_SETPC_B64 = 1876,
1892
    S_SETPC_B64_return  = 1877,
1893
    S_SETREG_B32  = 1878,
1894
    S_SETREG_IMM32_B32  = 1879,
1895
    S_SET_GPR_IDX_IDX = 1880,
1896
    S_SEXT_I32_I16  = 1881,
1897
    S_SEXT_I32_I8 = 1882,
1898
    S_STORE_DWORDX2_IMM = 1883,
1899
    S_STORE_DWORDX2_SGPR  = 1884,
1900
    S_STORE_DWORDX4_IMM = 1885,
1901
    S_STORE_DWORDX4_SGPR  = 1886,
1902
    S_STORE_DWORD_IMM = 1887,
1903
    S_STORE_DWORD_SGPR  = 1888,
1904
    S_SUBB_U32  = 1889,
1905
    S_SUB_I32 = 1890,
1906
    S_SUB_U32 = 1891,
1907
    S_SUB_U64_CO_PSEUDO = 1892,
1908
    S_SUB_U64_PSEUDO  = 1893,
1909
    S_SWAPPC_B64  = 1894,
1910
    S_WQM_B32 = 1895,
1911
    S_WQM_B64 = 1896,
1912
    S_XNOR_B32  = 1897,
1913
    S_XNOR_B64  = 1898,
1914
    S_XNOR_SAVEEXEC_B64 = 1899,
1915
    S_XOR_B32 = 1900,
1916
    S_XOR_B64 = 1901,
1917
    S_XOR_B64_term  = 1902,
1918
    S_XOR_SAVEEXEC_B64  = 1903,
1919
    TBUFFER_LOAD_FORMAT_D16_XYZW_ADDR64 = 1904,
1920
    TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN = 1905,
1921
    TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_exact = 1906,
1922
    TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN  = 1907,
1923
    TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_exact  = 1908,
1924
    TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN  = 1909,
1925
    TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_exact  = 1910,
1926
    TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET = 1911,
1927
    TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_exact = 1912,
1928
    TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_ADDR64 = 1913,
1929
    TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN = 1914,
1930
    TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_exact = 1915,
1931
    TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN  = 1916,
1932
    TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_exact  = 1917,
1933
    TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN  = 1918,
1934
    TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_exact  = 1919,
1935
    TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET = 1920,
1936
    TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_exact = 1921,
1937
    TBUFFER_LOAD_FORMAT_D16_XYZ_ADDR64  = 1922,
1938
    TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN  = 1923,
1939
    TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_exact  = 1924,
1940
    TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN = 1925,
1941
    TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_exact = 1926,
1942
    TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN = 1927,
1943
    TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_exact = 1928,
1944
    TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET  = 1929,
1945
    TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_exact  = 1930,
1946
    TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_ADDR64  = 1931,
1947
    TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN  = 1932,
1948
    TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_exact  = 1933,
1949
    TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN = 1934,
1950
    TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_exact = 1935,
1951
    TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN = 1936,
1952
    TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_exact = 1937,
1953
    TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET  = 1938,
1954
    TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_exact  = 1939,
1955
    TBUFFER_LOAD_FORMAT_D16_XY_ADDR64 = 1940,
1956
    TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN = 1941,
1957
    TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_exact = 1942,
1958
    TBUFFER_LOAD_FORMAT_D16_XY_IDXEN  = 1943,
1959
    TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_exact  = 1944,
1960
    TBUFFER_LOAD_FORMAT_D16_XY_OFFEN  = 1945,
1961
    TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_exact  = 1946,
1962
    TBUFFER_LOAD_FORMAT_D16_XY_OFFSET = 1947,
1963
    TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_exact = 1948,
1964
    TBUFFER_LOAD_FORMAT_D16_XY_gfx80_ADDR64 = 1949,
1965
    TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN = 1950,
1966
    TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_exact = 1951,
1967
    TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN  = 1952,
1968
    TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_exact  = 1953,
1969
    TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN  = 1954,
1970
    TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_exact  = 1955,
1971
    TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET = 1956,
1972
    TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_exact = 1957,
1973
    TBUFFER_LOAD_FORMAT_D16_X_ADDR64  = 1958,
1974
    TBUFFER_LOAD_FORMAT_D16_X_BOTHEN  = 1959,
1975
    TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_exact  = 1960,
1976
    TBUFFER_LOAD_FORMAT_D16_X_IDXEN = 1961,
1977
    TBUFFER_LOAD_FORMAT_D16_X_IDXEN_exact = 1962,
1978
    TBUFFER_LOAD_FORMAT_D16_X_OFFEN = 1963,
1979
    TBUFFER_LOAD_FORMAT_D16_X_OFFEN_exact = 1964,
1980
    TBUFFER_LOAD_FORMAT_D16_X_OFFSET  = 1965,
1981
    TBUFFER_LOAD_FORMAT_D16_X_OFFSET_exact  = 1966,
1982
    TBUFFER_LOAD_FORMAT_D16_X_gfx80_ADDR64  = 1967,
1983
    TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN  = 1968,
1984
    TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_exact  = 1969,
1985
    TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN = 1970,
1986
    TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_exact = 1971,
1987
    TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN = 1972,
1988
    TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_exact = 1973,
1989
    TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET  = 1974,
1990
    TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_exact  = 1975,
1991
    TBUFFER_LOAD_FORMAT_XYZW_ADDR64 = 1976,
1992
    TBUFFER_LOAD_FORMAT_XYZW_BOTHEN = 1977,
1993
    TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_exact = 1978,
1994
    TBUFFER_LOAD_FORMAT_XYZW_IDXEN  = 1979,
1995
    TBUFFER_LOAD_FORMAT_XYZW_IDXEN_exact  = 1980,
1996
    TBUFFER_LOAD_FORMAT_XYZW_OFFEN  = 1981,
1997
    TBUFFER_LOAD_FORMAT_XYZW_OFFEN_exact  = 1982,
1998
    TBUFFER_LOAD_FORMAT_XYZW_OFFSET = 1983,
1999
    TBUFFER_LOAD_FORMAT_XYZW_OFFSET_exact = 1984,
2000
    TBUFFER_LOAD_FORMAT_XYZ_ADDR64  = 1985,
2001
    TBUFFER_LOAD_FORMAT_XYZ_BOTHEN  = 1986,
2002
    TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_exact  = 1987,
2003
    TBUFFER_LOAD_FORMAT_XYZ_IDXEN = 1988,
2004
    TBUFFER_LOAD_FORMAT_XYZ_IDXEN_exact = 1989,
2005
    TBUFFER_LOAD_FORMAT_XYZ_OFFEN = 1990,
2006
    TBUFFER_LOAD_FORMAT_XYZ_OFFEN_exact = 1991,
2007
    TBUFFER_LOAD_FORMAT_XYZ_OFFSET  = 1992,
2008
    TBUFFER_LOAD_FORMAT_XYZ_OFFSET_exact  = 1993,
2009
    TBUFFER_LOAD_FORMAT_XY_ADDR64 = 1994,
2010
    TBUFFER_LOAD_FORMAT_XY_BOTHEN = 1995,
2011
    TBUFFER_LOAD_FORMAT_XY_BOTHEN_exact = 1996,
2012
    TBUFFER_LOAD_FORMAT_XY_IDXEN  = 1997,
2013
    TBUFFER_LOAD_FORMAT_XY_IDXEN_exact  = 1998,
2014
    TBUFFER_LOAD_FORMAT_XY_OFFEN  = 1999,
2015
    TBUFFER_LOAD_FORMAT_XY_OFFEN_exact  = 2000,
2016
    TBUFFER_LOAD_FORMAT_XY_OFFSET = 2001,
2017
    TBUFFER_LOAD_FORMAT_XY_OFFSET_exact = 2002,
2018
    TBUFFER_LOAD_FORMAT_X_ADDR64  = 2003,
2019
    TBUFFER_LOAD_FORMAT_X_BOTHEN  = 2004,
2020
    TBUFFER_LOAD_FORMAT_X_BOTHEN_exact  = 2005,
2021
    TBUFFER_LOAD_FORMAT_X_IDXEN = 2006,
2022
    TBUFFER_LOAD_FORMAT_X_IDXEN_exact = 2007,
2023
    TBUFFER_LOAD_FORMAT_X_OFFEN = 2008,
2024
    TBUFFER_LOAD_FORMAT_X_OFFEN_exact = 2009,
2025
    TBUFFER_LOAD_FORMAT_X_OFFSET  = 2010,
2026
    TBUFFER_LOAD_FORMAT_X_OFFSET_exact  = 2011,
2027
    TBUFFER_STORE_FORMAT_D16_XYZW_ADDR64  = 2012,
2028
    TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN  = 2013,
2029
    TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact  = 2014,
2030
    TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN = 2015,
2031
    TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact = 2016,
2032
    TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN = 2017,
2033
    TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact = 2018,
2034
    TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET  = 2019,
2035
    TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact  = 2020,
2036
    TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_ADDR64  = 2021,
2037
    TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN  = 2022,
2038
    TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact  = 2023,
2039
    TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN = 2024,
2040
    TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact = 2025,
2041
    TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN = 2026,
2042
    TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact = 2027,
2043
    TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET  = 2028,
2044
    TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact  = 2029,
2045
    TBUFFER_STORE_FORMAT_D16_XYZ_ADDR64 = 2030,
2046
    TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN = 2031,
2047
    TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_exact = 2032,
2048
    TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN  = 2033,
2049
    TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_exact  = 2034,
2050
    TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN  = 2035,
2051
    TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_exact  = 2036,
2052
    TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET = 2037,
2053
    TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_exact = 2038,
2054
    TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_ADDR64 = 2039,
2055
    TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN = 2040,
2056
    TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact = 2041,
2057
    TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN  = 2042,
2058
    TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact  = 2043,
2059
    TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN  = 2044,
2060
    TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact  = 2045,
2061
    TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET = 2046,
2062
    TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact = 2047,
2063
    TBUFFER_STORE_FORMAT_D16_XY_ADDR64  = 2048,
2064
    TBUFFER_STORE_FORMAT_D16_XY_BOTHEN  = 2049,
2065
    TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact  = 2050,
2066
    TBUFFER_STORE_FORMAT_D16_XY_IDXEN = 2051,
2067
    TBUFFER_STORE_FORMAT_D16_XY_IDXEN_exact = 2052,
2068
    TBUFFER_STORE_FORMAT_D16_XY_OFFEN = 2053,
2069
    TBUFFER_STORE_FORMAT_D16_XY_OFFEN_exact = 2054,
2070
    TBUFFER_STORE_FORMAT_D16_XY_OFFSET  = 2055,
2071
    TBUFFER_STORE_FORMAT_D16_XY_OFFSET_exact  = 2056,
2072
    TBUFFER_STORE_FORMAT_D16_XY_gfx80_ADDR64  = 2057,
2073
    TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN  = 2058,
2074
    TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact  = 2059,
2075
    TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN = 2060,
2076
    TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact = 2061,
2077
    TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN = 2062,
2078
    TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact = 2063,
2079
    TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET  = 2064,
2080
    TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact  = 2065,
2081
    TBUFFER_STORE_FORMAT_D16_X_ADDR64 = 2066,
2082
    TBUFFER_STORE_FORMAT_D16_X_BOTHEN = 2067,
2083
    TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact = 2068,
2084
    TBUFFER_STORE_FORMAT_D16_X_IDXEN  = 2069,
2085
    TBUFFER_STORE_FORMAT_D16_X_IDXEN_exact  = 2070,
2086
    TBUFFER_STORE_FORMAT_D16_X_OFFEN  = 2071,
2087
    TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact  = 2072,
2088
    TBUFFER_STORE_FORMAT_D16_X_OFFSET = 2073,
2089
    TBUFFER_STORE_FORMAT_D16_X_OFFSET_exact = 2074,
2090
    TBUFFER_STORE_FORMAT_D16_X_gfx80_ADDR64 = 2075,
2091
    TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN = 2076,
2092
    TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact = 2077,
2093
    TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN  = 2078,
2094
    TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact  = 2079,
2095
    TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN  = 2080,
2096
    TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact  = 2081,
2097
    TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET = 2082,
2098
    TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact = 2083,
2099
    TBUFFER_STORE_FORMAT_XYZW_ADDR64  = 2084,
2100
    TBUFFER_STORE_FORMAT_XYZW_BOTHEN  = 2085,
2101
    TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact  = 2086,
2102
    TBUFFER_STORE_FORMAT_XYZW_IDXEN = 2087,
2103
    TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact = 2088,
2104
    TBUFFER_STORE_FORMAT_XYZW_OFFEN = 2089,
2105
    TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact = 2090,
2106
    TBUFFER_STORE_FORMAT_XYZW_OFFSET  = 2091,
2107
    TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact  = 2092,
2108
    TBUFFER_STORE_FORMAT_XYZ_ADDR64 = 2093,
2109
    TBUFFER_STORE_FORMAT_XYZ_BOTHEN = 2094,
2110
    TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact = 2095,
2111
    TBUFFER_STORE_FORMAT_XYZ_IDXEN  = 2096,
2112
    TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact  = 2097,
2113
    TBUFFER_STORE_FORMAT_XYZ_OFFEN  = 2098,
2114
    TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact  = 2099,
2115
    TBUFFER_STORE_FORMAT_XYZ_OFFSET = 2100,
2116
    TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact = 2101,
2117
    TBUFFER_STORE_FORMAT_XY_ADDR64  = 2102,
2118
    TBUFFER_STORE_FORMAT_XY_BOTHEN  = 2103,
2119
    TBUFFER_STORE_FORMAT_XY_BOTHEN_exact  = 2104,
2120
    TBUFFER_STORE_FORMAT_XY_IDXEN = 2105,
2121
    TBUFFER_STORE_FORMAT_XY_IDXEN_exact = 2106,
2122
    TBUFFER_STORE_FORMAT_XY_OFFEN = 2107,
2123
    TBUFFER_STORE_FORMAT_XY_OFFEN_exact = 2108,
2124
    TBUFFER_STORE_FORMAT_XY_OFFSET  = 2109,
2125
    TBUFFER_STORE_FORMAT_XY_OFFSET_exact  = 2110,
2126
    TBUFFER_STORE_FORMAT_X_ADDR64 = 2111,
2127
    TBUFFER_STORE_FORMAT_X_BOTHEN = 2112,
2128
    TBUFFER_STORE_FORMAT_X_BOTHEN_exact = 2113,
2129
    TBUFFER_STORE_FORMAT_X_IDXEN  = 2114,
2130
    TBUFFER_STORE_FORMAT_X_IDXEN_exact  = 2115,
2131
    TBUFFER_STORE_FORMAT_X_OFFEN  = 2116,
2132
    TBUFFER_STORE_FORMAT_X_OFFEN_exact  = 2117,
2133
    TBUFFER_STORE_FORMAT_X_OFFSET = 2118,
2134
    TBUFFER_STORE_FORMAT_X_OFFSET_exact = 2119,
2135
    V_ADD3_U32  = 2120,
2136
    V_ADDC_U32_e32  = 2121,
2137
    V_ADDC_U32_e64  = 2122,
2138
    V_ADDC_U32_sdwa = 2123,
2139
    V_ADD_F16_e32 = 2124,
2140
    V_ADD_F16_e64 = 2125,
2141
    V_ADD_F16_sdwa  = 2126,
2142
    V_ADD_F32_e32 = 2127,
2143
    V_ADD_F32_e64 = 2128,
2144
    V_ADD_F32_sdwa  = 2129,
2145
    V_ADD_F64 = 2130,
2146
    V_ADD_I16 = 2131,
2147
    V_ADD_I32_e32 = 2132,
2148
    V_ADD_I32_e64 = 2133,
2149
    V_ADD_I32_gfx9  = 2134,
2150
    V_ADD_I32_sdwa  = 2135,
2151
    V_ADD_LSHL_U32  = 2136,
2152
    V_ADD_U16_e32 = 2137,
2153
    V_ADD_U16_e64 = 2138,
2154
    V_ADD_U16_sdwa  = 2139,
2155
    V_ADD_U32_e32 = 2140,
2156
    V_ADD_U32_e64 = 2141,
2157
    V_ADD_U32_sdwa  = 2142,
2158
    V_ALIGNBIT_B32  = 2143,
2159
    V_ALIGNBYTE_B32 = 2144,
2160
    V_AND_B32_e32 = 2145,
2161
    V_AND_B32_e64 = 2146,
2162
    V_AND_B32_sdwa  = 2147,
2163
    V_AND_OR_B32  = 2148,
2164
    V_ASHRREV_I16_e32 = 2149,
2165
    V_ASHRREV_I16_e64 = 2150,
2166
    V_ASHRREV_I16_sdwa  = 2151,
2167
    V_ASHRREV_I32_e32 = 2152,
2168
    V_ASHRREV_I32_e64 = 2153,
2169
    V_ASHRREV_I32_sdwa  = 2154,
2170
    V_ASHRREV_I64 = 2155,
2171
    V_ASHR_I32_e32  = 2156,
2172
    V_ASHR_I32_e64  = 2157,
2173
    V_ASHR_I32_sdwa = 2158,
2174
    V_ASHR_I64  = 2159,
2175
    V_BCNT_U32_B32_e32  = 2160,
2176
    V_BCNT_U32_B32_e64  = 2161,
2177
    V_BCNT_U32_B32_sdwa = 2162,
2178
    V_BFE_I32 = 2163,
2179
    V_BFE_U32 = 2164,
2180
    V_BFI_B32 = 2165,
2181
    V_BFM_B32_e32 = 2166,
2182
    V_BFM_B32_e64 = 2167,
2183
    V_BFM_B32_sdwa  = 2168,
2184
    V_BFREV_B32_e32 = 2169,
2185
    V_BFREV_B32_e64 = 2170,
2186
    V_BFREV_B32_sdwa  = 2171,
2187
    V_CEIL_F16_e32  = 2172,
2188
    V_CEIL_F16_e64  = 2173,
2189
    V_CEIL_F16_sdwa = 2174,
2190
    V_CEIL_F32_e32  = 2175,
2191
    V_CEIL_F32_e64  = 2176,
2192
    V_CEIL_F32_sdwa = 2177,
2193
    V_CEIL_F64_e32  = 2178,
2194
    V_CEIL_F64_e64  = 2179,
2195
    V_CEIL_F64_sdwa = 2180,
2196
    V_CLREXCP_e32 = 2181,
2197
    V_CLREXCP_e64 = 2182,
2198
    V_CLREXCP_sdwa  = 2183,
2199
    V_CMPSX_EQ_F32_e32  = 2184,
2200
    V_CMPSX_EQ_F32_e64  = 2185,
2201
    V_CMPSX_EQ_F32_sdwa = 2186,
2202
    V_CMPSX_EQ_F64_e32  = 2187,
2203
    V_CMPSX_EQ_F64_e64  = 2188,
2204
    V_CMPSX_EQ_F64_sdwa = 2189,
2205
    V_CMPSX_F_F32_e32 = 2190,
2206
    V_CMPSX_F_F32_e64 = 2191,
2207
    V_CMPSX_F_F32_sdwa  = 2192,
2208
    V_CMPSX_F_F64_e32 = 2193,
2209
    V_CMPSX_F_F64_e64 = 2194,
2210
    V_CMPSX_F_F64_sdwa  = 2195,
2211
    V_CMPSX_GE_F32_e32  = 2196,
2212
    V_CMPSX_GE_F32_e64  = 2197,
2213
    V_CMPSX_GE_F32_sdwa = 2198,
2214
    V_CMPSX_GE_F64_e32  = 2199,
2215
    V_CMPSX_GE_F64_e64  = 2200,
2216
    V_CMPSX_GE_F64_sdwa = 2201,
2217
    V_CMPSX_GT_F32_e32  = 2202,
2218
    V_CMPSX_GT_F32_e64  = 2203,
2219
    V_CMPSX_GT_F32_sdwa = 2204,
2220
    V_CMPSX_GT_F64_e32  = 2205,
2221
    V_CMPSX_GT_F64_e64  = 2206,
2222
    V_CMPSX_GT_F64_sdwa = 2207,
2223
    V_CMPSX_LE_F32_e32  = 2208,
2224
    V_CMPSX_LE_F32_e64  = 2209,
2225
    V_CMPSX_LE_F32_sdwa = 2210,
2226
    V_CMPSX_LE_F64_e32  = 2211,
2227
    V_CMPSX_LE_F64_e64  = 2212,
2228
    V_CMPSX_LE_F64_sdwa = 2213,
2229
    V_CMPSX_LG_F32_e32  = 2214,
2230
    V_CMPSX_LG_F32_e64  = 2215,
2231
    V_CMPSX_LG_F32_sdwa = 2216,
2232
    V_CMPSX_LG_F64_e32  = 2217,
2233
    V_CMPSX_LG_F64_e64  = 2218,
2234
    V_CMPSX_LG_F64_sdwa = 2219,
2235
    V_CMPSX_LT_F32_e32  = 2220,
2236
    V_CMPSX_LT_F32_e64  = 2221,
2237
    V_CMPSX_LT_F32_sdwa = 2222,
2238
    V_CMPSX_LT_F64_e32  = 2223,
2239
    V_CMPSX_LT_F64_e64  = 2224,
2240
    V_CMPSX_LT_F64_sdwa = 2225,
2241
    V_CMPSX_NEQ_F32_e32 = 2226,
2242
    V_CMPSX_NEQ_F32_e64 = 2227,
2243
    V_CMPSX_NEQ_F32_sdwa  = 2228,
2244
    V_CMPSX_NEQ_F64_e32 = 2229,
2245
    V_CMPSX_NEQ_F64_e64 = 2230,
2246
    V_CMPSX_NEQ_F64_sdwa  = 2231,
2247
    V_CMPSX_NGE_F32_e32 = 2232,
2248
    V_CMPSX_NGE_F32_e64 = 2233,
2249
    V_CMPSX_NGE_F32_sdwa  = 2234,
2250
    V_CMPSX_NGE_F64_e32 = 2235,
2251
    V_CMPSX_NGE_F64_e64 = 2236,
2252
    V_CMPSX_NGE_F64_sdwa  = 2237,
2253
    V_CMPSX_NGT_F32_e32 = 2238,
2254
    V_CMPSX_NGT_F32_e64 = 2239,
2255
    V_CMPSX_NGT_F32_sdwa  = 2240,
2256
    V_CMPSX_NGT_F64_e32 = 2241,
2257
    V_CMPSX_NGT_F64_e64 = 2242,
2258
    V_CMPSX_NGT_F64_sdwa  = 2243,
2259
    V_CMPSX_NLE_F32_e32 = 2244,
2260
    V_CMPSX_NLE_F32_e64 = 2245,
2261
    V_CMPSX_NLE_F32_sdwa  = 2246,
2262
    V_CMPSX_NLE_F64_e32 = 2247,
2263
    V_CMPSX_NLE_F64_e64 = 2248,
2264
    V_CMPSX_NLE_F64_sdwa  = 2249,
2265
    V_CMPSX_NLG_F32_e32 = 2250,
2266
    V_CMPSX_NLG_F32_e64 = 2251,
2267
    V_CMPSX_NLG_F32_sdwa  = 2252,
2268
    V_CMPSX_NLG_F64_e32 = 2253,
2269
    V_CMPSX_NLG_F64_e64 = 2254,
2270
    V_CMPSX_NLG_F64_sdwa  = 2255,
2271
    V_CMPSX_NLT_F32_e32 = 2256,
2272
    V_CMPSX_NLT_F32_e64 = 2257,
2273
    V_CMPSX_NLT_F32_sdwa  = 2258,
2274
    V_CMPSX_NLT_F64_e32 = 2259,
2275
    V_CMPSX_NLT_F64_e64 = 2260,
2276
    V_CMPSX_NLT_F64_sdwa  = 2261,
2277
    V_CMPSX_O_F32_e32 = 2262,
2278
    V_CMPSX_O_F32_e64 = 2263,
2279
    V_CMPSX_O_F32_sdwa  = 2264,
2280
    V_CMPSX_O_F64_e32 = 2265,
2281
    V_CMPSX_O_F64_e64 = 2266,
2282
    V_CMPSX_O_F64_sdwa  = 2267,
2283
    V_CMPSX_TRU_F32_e32 = 2268,
2284
    V_CMPSX_TRU_F32_e64 = 2269,
2285
    V_CMPSX_TRU_F32_sdwa  = 2270,
2286
    V_CMPSX_TRU_F64_e32 = 2271,
2287
    V_CMPSX_TRU_F64_e64 = 2272,
2288
    V_CMPSX_TRU_F64_sdwa  = 2273,
2289
    V_CMPSX_U_F32_e32 = 2274,
2290
    V_CMPSX_U_F32_e64 = 2275,
2291
    V_CMPSX_U_F32_sdwa  = 2276,
2292
    V_CMPSX_U_F64_e32 = 2277,
2293
    V_CMPSX_U_F64_e64 = 2278,
2294
    V_CMPSX_U_F64_sdwa  = 2279,
2295
    V_CMPS_EQ_F32_e32 = 2280,
2296
    V_CMPS_EQ_F32_e64 = 2281,
2297
    V_CMPS_EQ_F32_sdwa  = 2282,
2298
    V_CMPS_EQ_F64_e32 = 2283,
2299
    V_CMPS_EQ_F64_e64 = 2284,
2300
    V_CMPS_EQ_F64_sdwa  = 2285,
2301
    V_CMPS_F_F32_e32  = 2286,
2302
    V_CMPS_F_F32_e64  = 2287,
2303
    V_CMPS_F_F32_sdwa = 2288,
2304
    V_CMPS_F_F64_e32  = 2289,
2305
    V_CMPS_F_F64_e64  = 2290,
2306
    V_CMPS_F_F64_sdwa = 2291,
2307
    V_CMPS_GE_F32_e32 = 2292,
2308
    V_CMPS_GE_F32_e64 = 2293,
2309
    V_CMPS_GE_F32_sdwa  = 2294,
2310
    V_CMPS_GE_F64_e32 = 2295,
2311
    V_CMPS_GE_F64_e64 = 2296,
2312
    V_CMPS_GE_F64_sdwa  = 2297,
2313
    V_CMPS_GT_F32_e32 = 2298,
2314
    V_CMPS_GT_F32_e64 = 2299,
2315
    V_CMPS_GT_F32_sdwa  = 2300,
2316
    V_CMPS_GT_F64_e32 = 2301,
2317
    V_CMPS_GT_F64_e64 = 2302,
2318
    V_CMPS_GT_F64_sdwa  = 2303,
2319
    V_CMPS_LE_F32_e32 = 2304,
2320
    V_CMPS_LE_F32_e64 = 2305,
2321
    V_CMPS_LE_F32_sdwa  = 2306,
2322
    V_CMPS_LE_F64_e32 = 2307,
2323
    V_CMPS_LE_F64_e64 = 2308,
2324
    V_CMPS_LE_F64_sdwa  = 2309,
2325
    V_CMPS_LG_F32_e32 = 2310,
2326
    V_CMPS_LG_F32_e64 = 2311,
2327
    V_CMPS_LG_F32_sdwa  = 2312,
2328
    V_CMPS_LG_F64_e32 = 2313,
2329
    V_CMPS_LG_F64_e64 = 2314,
2330
    V_CMPS_LG_F64_sdwa  = 2315,
2331
    V_CMPS_LT_F32_e32 = 2316,
2332
    V_CMPS_LT_F32_e64 = 2317,
2333
    V_CMPS_LT_F32_sdwa  = 2318,
2334
    V_CMPS_LT_F64_e32 = 2319,
2335
    V_CMPS_LT_F64_e64 = 2320,
2336
    V_CMPS_LT_F64_sdwa  = 2321,
2337
    V_CMPS_NEQ_F32_e32  = 2322,
2338
    V_CMPS_NEQ_F32_e64  = 2323,
2339
    V_CMPS_NEQ_F32_sdwa = 2324,
2340
    V_CMPS_NEQ_F64_e32  = 2325,
2341
    V_CMPS_NEQ_F64_e64  = 2326,
2342
    V_CMPS_NEQ_F64_sdwa = 2327,
2343
    V_CMPS_NGE_F32_e32  = 2328,
2344
    V_CMPS_NGE_F32_e64  = 2329,
2345
    V_CMPS_NGE_F32_sdwa = 2330,
2346
    V_CMPS_NGE_F64_e32  = 2331,
2347
    V_CMPS_NGE_F64_e64  = 2332,
2348
    V_CMPS_NGE_F64_sdwa = 2333,
2349
    V_CMPS_NGT_F32_e32  = 2334,
2350
    V_CMPS_NGT_F32_e64  = 2335,
2351
    V_CMPS_NGT_F32_sdwa = 2336,
2352
    V_CMPS_NGT_F64_e32  = 2337,
2353
    V_CMPS_NGT_F64_e64  = 2338,
2354
    V_CMPS_NGT_F64_sdwa = 2339,
2355
    V_CMPS_NLE_F32_e32  = 2340,
2356
    V_CMPS_NLE_F32_e64  = 2341,
2357
    V_CMPS_NLE_F32_sdwa = 2342,
2358
    V_CMPS_NLE_F64_e32  = 2343,
2359
    V_CMPS_NLE_F64_e64  = 2344,
2360
    V_CMPS_NLE_F64_sdwa = 2345,
2361
    V_CMPS_NLG_F32_e32  = 2346,
2362
    V_CMPS_NLG_F32_e64  = 2347,
2363
    V_CMPS_NLG_F32_sdwa = 2348,
2364
    V_CMPS_NLG_F64_e32  = 2349,
2365
    V_CMPS_NLG_F64_e64  = 2350,
2366
    V_CMPS_NLG_F64_sdwa = 2351,
2367
    V_CMPS_NLT_F32_e32  = 2352,
2368
    V_CMPS_NLT_F32_e64  = 2353,
2369
    V_CMPS_NLT_F32_sdwa = 2354,
2370
    V_CMPS_NLT_F64_e32  = 2355,
2371
    V_CMPS_NLT_F64_e64  = 2356,
2372
    V_CMPS_NLT_F64_sdwa = 2357,
2373
    V_CMPS_O_F32_e32  = 2358,
2374
    V_CMPS_O_F32_e64  = 2359,
2375
    V_CMPS_O_F32_sdwa = 2360,
2376
    V_CMPS_O_F64_e32  = 2361,
2377
    V_CMPS_O_F64_e64  = 2362,
2378
    V_CMPS_O_F64_sdwa = 2363,
2379
    V_CMPS_TRU_F32_e32  = 2364,
2380
    V_CMPS_TRU_F32_e64  = 2365,
2381
    V_CMPS_TRU_F32_sdwa = 2366,
2382
    V_CMPS_TRU_F64_e32  = 2367,
2383
    V_CMPS_TRU_F64_e64  = 2368,
2384
    V_CMPS_TRU_F64_sdwa = 2369,
2385
    V_CMPS_U_F32_e32  = 2370,
2386
    V_CMPS_U_F32_e64  = 2371,
2387
    V_CMPS_U_F32_sdwa = 2372,
2388
    V_CMPS_U_F64_e32  = 2373,
2389
    V_CMPS_U_F64_e64  = 2374,
2390
    V_CMPS_U_F64_sdwa = 2375,
2391
    V_CMPX_CLASS_F16_e32  = 2376,
2392
    V_CMPX_CLASS_F16_e64  = 2377,
2393
    V_CMPX_CLASS_F16_sdwa = 2378,
2394
    V_CMPX_CLASS_F32_e32  = 2379,
2395
    V_CMPX_CLASS_F32_e64  = 2380,
2396
    V_CMPX_CLASS_F32_sdwa = 2381,
2397
    V_CMPX_CLASS_F64_e32  = 2382,
2398
    V_CMPX_CLASS_F64_e64  = 2383,
2399
    V_CMPX_CLASS_F64_sdwa = 2384,
2400
    V_CMPX_EQ_F16_e32 = 2385,
2401
    V_CMPX_EQ_F16_e64 = 2386,
2402
    V_CMPX_EQ_F16_sdwa  = 2387,
2403
    V_CMPX_EQ_F32_e32 = 2388,
2404
    V_CMPX_EQ_F32_e64 = 2389,
2405
    V_CMPX_EQ_F32_sdwa  = 2390,
2406
    V_CMPX_EQ_F64_e32 = 2391,
2407
    V_CMPX_EQ_F64_e64 = 2392,
2408
    V_CMPX_EQ_F64_sdwa  = 2393,
2409
    V_CMPX_EQ_I16_e32 = 2394,
2410
    V_CMPX_EQ_I16_e64 = 2395,
2411
    V_CMPX_EQ_I16_sdwa  = 2396,
2412
    V_CMPX_EQ_I32_e32 = 2397,
2413
    V_CMPX_EQ_I32_e64 = 2398,
2414
    V_CMPX_EQ_I32_sdwa  = 2399,
2415
    V_CMPX_EQ_I64_e32 = 2400,
2416
    V_CMPX_EQ_I64_e64 = 2401,
2417
    V_CMPX_EQ_I64_sdwa  = 2402,
2418
    V_CMPX_EQ_U16_e32 = 2403,
2419
    V_CMPX_EQ_U16_e64 = 2404,
2420
    V_CMPX_EQ_U16_sdwa  = 2405,
2421
    V_CMPX_EQ_U32_e32 = 2406,
2422
    V_CMPX_EQ_U32_e64 = 2407,
2423
    V_CMPX_EQ_U32_sdwa  = 2408,
2424
    V_CMPX_EQ_U64_e32 = 2409,
2425
    V_CMPX_EQ_U64_e64 = 2410,
2426
    V_CMPX_EQ_U64_sdwa  = 2411,
2427
    V_CMPX_F_F16_e32  = 2412,
2428
    V_CMPX_F_F16_e64  = 2413,
2429
    V_CMPX_F_F16_sdwa = 2414,
2430
    V_CMPX_F_F32_e32  = 2415,
2431
    V_CMPX_F_F32_e64  = 2416,
2432
    V_CMPX_F_F32_sdwa = 2417,
2433
    V_CMPX_F_F64_e32  = 2418,
2434
    V_CMPX_F_F64_e64  = 2419,
2435
    V_CMPX_F_F64_sdwa = 2420,
2436
    V_CMPX_F_I16_e32  = 2421,
2437
    V_CMPX_F_I16_e64  = 2422,
2438
    V_CMPX_F_I16_sdwa = 2423,
2439
    V_CMPX_F_I32_e32  = 2424,
2440
    V_CMPX_F_I32_e64  = 2425,
2441
    V_CMPX_F_I32_sdwa = 2426,
2442
    V_CMPX_F_I64_e32  = 2427,
2443
    V_CMPX_F_I64_e64  = 2428,
2444
    V_CMPX_F_I64_sdwa = 2429,
2445
    V_CMPX_F_U16_e32  = 2430,
2446
    V_CMPX_F_U16_e64  = 2431,
2447
    V_CMPX_F_U16_sdwa = 2432,
2448
    V_CMPX_F_U32_e32  = 2433,
2449
    V_CMPX_F_U32_e64  = 2434,
2450
    V_CMPX_F_U32_sdwa = 2435,
2451
    V_CMPX_F_U64_e32  = 2436,
2452
    V_CMPX_F_U64_e64  = 2437,
2453
    V_CMPX_F_U64_sdwa = 2438,
2454
    V_CMPX_GE_F16_e32 = 2439,
2455
    V_CMPX_GE_F16_e64 = 2440,
2456
    V_CMPX_GE_F16_sdwa  = 2441,
2457
    V_CMPX_GE_F32_e32 = 2442,
2458
    V_CMPX_GE_F32_e64 = 2443,
2459
    V_CMPX_GE_F32_sdwa  = 2444,
2460
    V_CMPX_GE_F64_e32 = 2445,
2461
    V_CMPX_GE_F64_e64 = 2446,
2462
    V_CMPX_GE_F64_sdwa  = 2447,
2463
    V_CMPX_GE_I16_e32 = 2448,
2464
    V_CMPX_GE_I16_e64 = 2449,
2465
    V_CMPX_GE_I16_sdwa  = 2450,
2466
    V_CMPX_GE_I32_e32 = 2451,
2467
    V_CMPX_GE_I32_e64 = 2452,
2468
    V_CMPX_GE_I32_sdwa  = 2453,
2469
    V_CMPX_GE_I64_e32 = 2454,
2470
    V_CMPX_GE_I64_e64 = 2455,
2471
    V_CMPX_GE_I64_sdwa  = 2456,
2472
    V_CMPX_GE_U16_e32 = 2457,
2473
    V_CMPX_GE_U16_e64 = 2458,
2474
    V_CMPX_GE_U16_sdwa  = 2459,
2475
    V_CMPX_GE_U32_e32 = 2460,
2476
    V_CMPX_GE_U32_e64 = 2461,
2477
    V_CMPX_GE_U32_sdwa  = 2462,
2478
    V_CMPX_GE_U64_e32 = 2463,
2479
    V_CMPX_GE_U64_e64 = 2464,
2480
    V_CMPX_GE_U64_sdwa  = 2465,
2481
    V_CMPX_GT_F16_e32 = 2466,
2482
    V_CMPX_GT_F16_e64 = 2467,
2483
    V_CMPX_GT_F16_sdwa  = 2468,
2484
    V_CMPX_GT_F32_e32 = 2469,
2485
    V_CMPX_GT_F32_e64 = 2470,
2486
    V_CMPX_GT_F32_sdwa  = 2471,
2487
    V_CMPX_GT_F64_e32 = 2472,
2488
    V_CMPX_GT_F64_e64 = 2473,
2489
    V_CMPX_GT_F64_sdwa  = 2474,
2490
    V_CMPX_GT_I16_e32 = 2475,
2491
    V_CMPX_GT_I16_e64 = 2476,
2492
    V_CMPX_GT_I16_sdwa  = 2477,
2493
    V_CMPX_GT_I32_e32 = 2478,
2494
    V_CMPX_GT_I32_e64 = 2479,
2495
    V_CMPX_GT_I32_sdwa  = 2480,
2496
    V_CMPX_GT_I64_e32 = 2481,
2497
    V_CMPX_GT_I64_e64 = 2482,
2498
    V_CMPX_GT_I64_sdwa  = 2483,
2499
    V_CMPX_GT_U16_e32 = 2484,
2500
    V_CMPX_GT_U16_e64 = 2485,
2501
    V_CMPX_GT_U16_sdwa  = 2486,
2502
    V_CMPX_GT_U32_e32 = 2487,
2503
    V_CMPX_GT_U32_e64 = 2488,
2504
    V_CMPX_GT_U32_sdwa  = 2489,
2505
    V_CMPX_GT_U64_e32 = 2490,
2506
    V_CMPX_GT_U64_e64 = 2491,
2507
    V_CMPX_GT_U64_sdwa  = 2492,
2508
    V_CMPX_LE_F16_e32 = 2493,
2509
    V_CMPX_LE_F16_e64 = 2494,
2510
    V_CMPX_LE_F16_sdwa  = 2495,
2511
    V_CMPX_LE_F32_e32 = 2496,
2512
    V_CMPX_LE_F32_e64 = 2497,
2513
    V_CMPX_LE_F32_sdwa  = 2498,
2514
    V_CMPX_LE_F64_e32 = 2499,
2515
    V_CMPX_LE_F64_e64 = 2500,
2516
    V_CMPX_LE_F64_sdwa  = 2501,
2517
    V_CMPX_LE_I16_e32 = 2502,
2518
    V_CMPX_LE_I16_e64 = 2503,
2519
    V_CMPX_LE_I16_sdwa  = 2504,
2520
    V_CMPX_LE_I32_e32 = 2505,
2521
    V_CMPX_LE_I32_e64 = 2506,
2522
    V_CMPX_LE_I32_sdwa  = 2507,
2523
    V_CMPX_LE_I64_e32 = 2508,
2524
    V_CMPX_LE_I64_e64 = 2509,
2525
    V_CMPX_LE_I64_sdwa  = 2510,
2526
    V_CMPX_LE_U16_e32 = 2511,
2527
    V_CMPX_LE_U16_e64 = 2512,
2528
    V_CMPX_LE_U16_sdwa  = 2513,
2529
    V_CMPX_LE_U32_e32 = 2514,
2530
    V_CMPX_LE_U32_e64 = 2515,
2531
    V_CMPX_LE_U32_sdwa  = 2516,
2532
    V_CMPX_LE_U64_e32 = 2517,
2533
    V_CMPX_LE_U64_e64 = 2518,
2534
    V_CMPX_LE_U64_sdwa  = 2519,
2535
    V_CMPX_LG_F16_e32 = 2520,
2536
    V_CMPX_LG_F16_e64 = 2521,
2537
    V_CMPX_LG_F16_sdwa  = 2522,
2538
    V_CMPX_LG_F32_e32 = 2523,
2539
    V_CMPX_LG_F32_e64 = 2524,
2540
    V_CMPX_LG_F32_sdwa  = 2525,
2541
    V_CMPX_LG_F64_e32 = 2526,
2542
    V_CMPX_LG_F64_e64 = 2527,
2543
    V_CMPX_LG_F64_sdwa  = 2528,
2544
    V_CMPX_LT_F16_e32 = 2529,
2545
    V_CMPX_LT_F16_e64 = 2530,
2546
    V_CMPX_LT_F16_sdwa  = 2531,
2547
    V_CMPX_LT_F32_e32 = 2532,
2548
    V_CMPX_LT_F32_e64 = 2533,
2549
    V_CMPX_LT_F32_sdwa  = 2534,
2550
    V_CMPX_LT_F64_e32 = 2535,
2551
    V_CMPX_LT_F64_e64 = 2536,
2552
    V_CMPX_LT_F64_sdwa  = 2537,
2553
    V_CMPX_LT_I16_e32 = 2538,
2554
    V_CMPX_LT_I16_e64 = 2539,
2555
    V_CMPX_LT_I16_sdwa  = 2540,
2556
    V_CMPX_LT_I32_e32 = 2541,
2557
    V_CMPX_LT_I32_e64 = 2542,
2558
    V_CMPX_LT_I32_sdwa  = 2543,
2559
    V_CMPX_LT_I64_e32 = 2544,
2560
    V_CMPX_LT_I64_e64 = 2545,
2561
    V_CMPX_LT_I64_sdwa  = 2546,
2562
    V_CMPX_LT_U16_e32 = 2547,
2563
    V_CMPX_LT_U16_e64 = 2548,
2564
    V_CMPX_LT_U16_sdwa  = 2549,
2565
    V_CMPX_LT_U32_e32 = 2550,
2566
    V_CMPX_LT_U32_e64 = 2551,
2567
    V_CMPX_LT_U32_sdwa  = 2552,
2568
    V_CMPX_LT_U64_e32 = 2553,
2569
    V_CMPX_LT_U64_e64 = 2554,
2570
    V_CMPX_LT_U64_sdwa  = 2555,
2571
    V_CMPX_NEQ_F16_e32  = 2556,
2572
    V_CMPX_NEQ_F16_e64  = 2557,
2573
    V_CMPX_NEQ_F16_sdwa = 2558,
2574
    V_CMPX_NEQ_F32_e32  = 2559,
2575
    V_CMPX_NEQ_F32_e64  = 2560,
2576
    V_CMPX_NEQ_F32_sdwa = 2561,
2577
    V_CMPX_NEQ_F64_e32  = 2562,
2578
    V_CMPX_NEQ_F64_e64  = 2563,
2579
    V_CMPX_NEQ_F64_sdwa = 2564,
2580
    V_CMPX_NE_I16_e32 = 2565,
2581
    V_CMPX_NE_I16_e64 = 2566,
2582
    V_CMPX_NE_I16_sdwa  = 2567,
2583
    V_CMPX_NE_I32_e32 = 2568,
2584
    V_CMPX_NE_I32_e64 = 2569,
2585
    V_CMPX_NE_I32_sdwa  = 2570,
2586
    V_CMPX_NE_I64_e32 = 2571,
2587
    V_CMPX_NE_I64_e64 = 2572,
2588
    V_CMPX_NE_I64_sdwa  = 2573,
2589
    V_CMPX_NE_U16_e32 = 2574,
2590
    V_CMPX_NE_U16_e64 = 2575,
2591
    V_CMPX_NE_U16_sdwa  = 2576,
2592
    V_CMPX_NE_U32_e32 = 2577,
2593
    V_CMPX_NE_U32_e64 = 2578,
2594
    V_CMPX_NE_U32_sdwa  = 2579,
2595
    V_CMPX_NE_U64_e32 = 2580,
2596
    V_CMPX_NE_U64_e64 = 2581,
2597
    V_CMPX_NE_U64_sdwa  = 2582,
2598
    V_CMPX_NGE_F16_e32  = 2583,
2599
    V_CMPX_NGE_F16_e64  = 2584,
2600
    V_CMPX_NGE_F16_sdwa = 2585,
2601
    V_CMPX_NGE_F32_e32  = 2586,
2602
    V_CMPX_NGE_F32_e64  = 2587,
2603
    V_CMPX_NGE_F32_sdwa = 2588,
2604
    V_CMPX_NGE_F64_e32  = 2589,
2605
    V_CMPX_NGE_F64_e64  = 2590,
2606
    V_CMPX_NGE_F64_sdwa = 2591,
2607
    V_CMPX_NGT_F16_e32  = 2592,
2608
    V_CMPX_NGT_F16_e64  = 2593,
2609
    V_CMPX_NGT_F16_sdwa = 2594,
2610
    V_CMPX_NGT_F32_e32  = 2595,
2611
    V_CMPX_NGT_F32_e64  = 2596,
2612
    V_CMPX_NGT_F32_sdwa = 2597,
2613
    V_CMPX_NGT_F64_e32  = 2598,
2614
    V_CMPX_NGT_F64_e64  = 2599,
2615
    V_CMPX_NGT_F64_sdwa = 2600,
2616
    V_CMPX_NLE_F16_e32  = 2601,
2617
    V_CMPX_NLE_F16_e64  = 2602,
2618
    V_CMPX_NLE_F16_sdwa = 2603,
2619
    V_CMPX_NLE_F32_e32  = 2604,
2620
    V_CMPX_NLE_F32_e64  = 2605,
2621
    V_CMPX_NLE_F32_sdwa = 2606,
2622
    V_CMPX_NLE_F64_e32  = 2607,
2623
    V_CMPX_NLE_F64_e64  = 2608,
2624
    V_CMPX_NLE_F64_sdwa = 2609,
2625
    V_CMPX_NLG_F16_e32  = 2610,
2626
    V_CMPX_NLG_F16_e64  = 2611,
2627
    V_CMPX_NLG_F16_sdwa = 2612,
2628
    V_CMPX_NLG_F32_e32  = 2613,
2629
    V_CMPX_NLG_F32_e64  = 2614,
2630
    V_CMPX_NLG_F32_sdwa = 2615,
2631
    V_CMPX_NLG_F64_e32  = 2616,
2632
    V_CMPX_NLG_F64_e64  = 2617,
2633
    V_CMPX_NLG_F64_sdwa = 2618,
2634
    V_CMPX_NLT_F16_e32  = 2619,
2635
    V_CMPX_NLT_F16_e64  = 2620,
2636
    V_CMPX_NLT_F16_sdwa = 2621,
2637
    V_CMPX_NLT_F32_e32  = 2622,
2638
    V_CMPX_NLT_F32_e64  = 2623,
2639
    V_CMPX_NLT_F32_sdwa = 2624,
2640
    V_CMPX_NLT_F64_e32  = 2625,
2641
    V_CMPX_NLT_F64_e64  = 2626,
2642
    V_CMPX_NLT_F64_sdwa = 2627,
2643
    V_CMPX_O_F16_e32  = 2628,
2644
    V_CMPX_O_F16_e64  = 2629,
2645
    V_CMPX_O_F16_sdwa = 2630,
2646
    V_CMPX_O_F32_e32  = 2631,
2647
    V_CMPX_O_F32_e64  = 2632,
2648
    V_CMPX_O_F32_sdwa = 2633,
2649
    V_CMPX_O_F64_e32  = 2634,
2650
    V_CMPX_O_F64_e64  = 2635,
2651
    V_CMPX_O_F64_sdwa = 2636,
2652
    V_CMPX_TRU_F16_e32  = 2637,
2653
    V_CMPX_TRU_F16_e64  = 2638,
2654
    V_CMPX_TRU_F16_sdwa = 2639,
2655
    V_CMPX_TRU_F32_e32  = 2640,
2656
    V_CMPX_TRU_F32_e64  = 2641,
2657
    V_CMPX_TRU_F32_sdwa = 2642,
2658
    V_CMPX_TRU_F64_e32  = 2643,
2659
    V_CMPX_TRU_F64_e64  = 2644,
2660
    V_CMPX_TRU_F64_sdwa = 2645,
2661
    V_CMPX_T_I16_e32  = 2646,
2662
    V_CMPX_T_I16_e64  = 2647,
2663
    V_CMPX_T_I16_sdwa = 2648,
2664
    V_CMPX_T_I32_e32  = 2649,
2665
    V_CMPX_T_I32_e64  = 2650,
2666
    V_CMPX_T_I32_sdwa = 2651,
2667
    V_CMPX_T_I64_e32  = 2652,
2668
    V_CMPX_T_I64_e64  = 2653,
2669
    V_CMPX_T_I64_sdwa = 2654,
2670
    V_CMPX_T_U16_e32  = 2655,
2671
    V_CMPX_T_U16_e64  = 2656,
2672
    V_CMPX_T_U16_sdwa = 2657,
2673
    V_CMPX_T_U32_e32  = 2658,
2674
    V_CMPX_T_U32_e64  = 2659,
2675
    V_CMPX_T_U32_sdwa = 2660,
2676
    V_CMPX_T_U64_e32  = 2661,
2677
    V_CMPX_T_U64_e64  = 2662,
2678
    V_CMPX_T_U64_sdwa = 2663,
2679
    V_CMPX_U_F16_e32  = 2664,
2680
    V_CMPX_U_F16_e64  = 2665,
2681
    V_CMPX_U_F16_sdwa = 2666,
2682
    V_CMPX_U_F32_e32  = 2667,
2683
    V_CMPX_U_F32_e64  = 2668,
2684
    V_CMPX_U_F32_sdwa = 2669,
2685
    V_CMPX_U_F64_e32  = 2670,
2686
    V_CMPX_U_F64_e64  = 2671,
2687
    V_CMPX_U_F64_sdwa = 2672,
2688
    V_CMP_CLASS_F16_e32 = 2673,
2689
    V_CMP_CLASS_F16_e64 = 2674,
2690
    V_CMP_CLASS_F16_sdwa  = 2675,
2691
    V_CMP_CLASS_F32_e32 = 2676,
2692
    V_CMP_CLASS_F32_e64 = 2677,
2693
    V_CMP_CLASS_F32_sdwa  = 2678,
2694
    V_CMP_CLASS_F64_e32 = 2679,
2695
    V_CMP_CLASS_F64_e64 = 2680,
2696
    V_CMP_CLASS_F64_sdwa  = 2681,
2697
    V_CMP_EQ_F16_e32  = 2682,
2698
    V_CMP_EQ_F16_e64  = 2683,
2699
    V_CMP_EQ_F16_sdwa = 2684,
2700
    V_CMP_EQ_F32_e32  = 2685,
2701
    V_CMP_EQ_F32_e64  = 2686,
2702
    V_CMP_EQ_F32_sdwa = 2687,
2703
    V_CMP_EQ_F64_e32  = 2688,
2704
    V_CMP_EQ_F64_e64  = 2689,
2705
    V_CMP_EQ_F64_sdwa = 2690,
2706
    V_CMP_EQ_I16_e32  = 2691,
2707
    V_CMP_EQ_I16_e64  = 2692,
2708
    V_CMP_EQ_I16_sdwa = 2693,
2709
    V_CMP_EQ_I32_e32  = 2694,
2710
    V_CMP_EQ_I32_e64  = 2695,
2711
    V_CMP_EQ_I32_sdwa = 2696,
2712
    V_CMP_EQ_I64_e32  = 2697,
2713
    V_CMP_EQ_I64_e64  = 2698,
2714
    V_CMP_EQ_I64_sdwa = 2699,
2715
    V_CMP_EQ_U16_e32  = 2700,
2716
    V_CMP_EQ_U16_e64  = 2701,
2717
    V_CMP_EQ_U16_sdwa = 2702,
2718
    V_CMP_EQ_U32_e32  = 2703,
2719
    V_CMP_EQ_U32_e64  = 2704,
2720
    V_CMP_EQ_U32_sdwa = 2705,
2721
    V_CMP_EQ_U64_e32  = 2706,
2722
    V_CMP_EQ_U64_e64  = 2707,
2723
    V_CMP_EQ_U64_sdwa = 2708,
2724
    V_CMP_F_F16_e32 = 2709,
2725
    V_CMP_F_F16_e64 = 2710,
2726
    V_CMP_F_F16_sdwa  = 2711,
2727
    V_CMP_F_F32_e32 = 2712,
2728
    V_CMP_F_F32_e64 = 2713,
2729
    V_CMP_F_F32_sdwa  = 2714,
2730
    V_CMP_F_F64_e32 = 2715,
2731
    V_CMP_F_F64_e64 = 2716,
2732
    V_CMP_F_F64_sdwa  = 2717,
2733
    V_CMP_F_I16_e32 = 2718,
2734
    V_CMP_F_I16_e64 = 2719,
2735
    V_CMP_F_I16_sdwa  = 2720,
2736
    V_CMP_F_I32_e32 = 2721,
2737
    V_CMP_F_I32_e64 = 2722,
2738
    V_CMP_F_I32_sdwa  = 2723,
2739
    V_CMP_F_I64_e32 = 2724,
2740
    V_CMP_F_I64_e64 = 2725,
2741
    V_CMP_F_I64_sdwa  = 2726,
2742
    V_CMP_F_U16_e32 = 2727,
2743
    V_CMP_F_U16_e64 = 2728,
2744
    V_CMP_F_U16_sdwa  = 2729,
2745
    V_CMP_F_U32_e32 = 2730,
2746
    V_CMP_F_U32_e64 = 2731,
2747
    V_CMP_F_U32_sdwa  = 2732,
2748
    V_CMP_F_U64_e32 = 2733,
2749
    V_CMP_F_U64_e64 = 2734,
2750
    V_CMP_F_U64_sdwa  = 2735,
2751
    V_CMP_GE_F16_e32  = 2736,
2752
    V_CMP_GE_F16_e64  = 2737,
2753
    V_CMP_GE_F16_sdwa = 2738,
2754
    V_CMP_GE_F32_e32  = 2739,
2755
    V_CMP_GE_F32_e64  = 2740,
2756
    V_CMP_GE_F32_sdwa = 2741,
2757
    V_CMP_GE_F64_e32  = 2742,
2758
    V_CMP_GE_F64_e64  = 2743,
2759
    V_CMP_GE_F64_sdwa = 2744,
2760
    V_CMP_GE_I16_e32  = 2745,
2761
    V_CMP_GE_I16_e64  = 2746,
2762
    V_CMP_GE_I16_sdwa = 2747,
2763
    V_CMP_GE_I32_e32  = 2748,
2764
    V_CMP_GE_I32_e64  = 2749,
2765
    V_CMP_GE_I32_sdwa = 2750,
2766
    V_CMP_GE_I64_e32  = 2751,
2767
    V_CMP_GE_I64_e64  = 2752,
2768
    V_CMP_GE_I64_sdwa = 2753,
2769
    V_CMP_GE_U16_e32  = 2754,
2770
    V_CMP_GE_U16_e64  = 2755,
2771
    V_CMP_GE_U16_sdwa = 2756,
2772
    V_CMP_GE_U32_e32  = 2757,
2773
    V_CMP_GE_U32_e64  = 2758,
2774
    V_CMP_GE_U32_sdwa = 2759,
2775
    V_CMP_GE_U64_e32  = 2760,
2776
    V_CMP_GE_U64_e64  = 2761,
2777
    V_CMP_GE_U64_sdwa = 2762,
2778
    V_CMP_GT_F16_e32  = 2763,
2779
    V_CMP_GT_F16_e64  = 2764,
2780
    V_CMP_GT_F16_sdwa = 2765,
2781
    V_CMP_GT_F32_e32  = 2766,
2782
    V_CMP_GT_F32_e64  = 2767,
2783
    V_CMP_GT_F32_sdwa = 2768,
2784
    V_CMP_GT_F64_e32  = 2769,
2785
    V_CMP_GT_F64_e64  = 2770,
2786
    V_CMP_GT_F64_sdwa = 2771,
2787
    V_CMP_GT_I16_e32  = 2772,
2788
    V_CMP_GT_I16_e64  = 2773,
2789
    V_CMP_GT_I16_sdwa = 2774,
2790
    V_CMP_GT_I32_e32  = 2775,
2791
    V_CMP_GT_I32_e64  = 2776,
2792
    V_CMP_GT_I32_sdwa = 2777,
2793
    V_CMP_GT_I64_e32  = 2778,
2794
    V_CMP_GT_I64_e64  = 2779,
2795
    V_CMP_GT_I64_sdwa = 2780,
2796
    V_CMP_GT_U16_e32  = 2781,
2797
    V_CMP_GT_U16_e64  = 2782,
2798
    V_CMP_GT_U16_sdwa = 2783,
2799
    V_CMP_GT_U32_e32  = 2784,
2800
    V_CMP_GT_U32_e64  = 2785,
2801
    V_CMP_GT_U32_sdwa = 2786,
2802
    V_CMP_GT_U64_e32  = 2787,
2803
    V_CMP_GT_U64_e64  = 2788,
2804
    V_CMP_GT_U64_sdwa = 2789,
2805
    V_CMP_LE_F16_e32  = 2790,
2806
    V_CMP_LE_F16_e64  = 2791,
2807
    V_CMP_LE_F16_sdwa = 2792,
2808
    V_CMP_LE_F32_e32  = 2793,
2809
    V_CMP_LE_F32_e64  = 2794,
2810
    V_CMP_LE_F32_sdwa = 2795,
2811
    V_CMP_LE_F64_e32  = 2796,
2812
    V_CMP_LE_F64_e64  = 2797,
2813
    V_CMP_LE_F64_sdwa = 2798,
2814
    V_CMP_LE_I16_e32  = 2799,
2815
    V_CMP_LE_I16_e64  = 2800,
2816
    V_CMP_LE_I16_sdwa = 2801,
2817
    V_CMP_LE_I32_e32  = 2802,
2818
    V_CMP_LE_I32_e64  = 2803,
2819
    V_CMP_LE_I32_sdwa = 2804,
2820
    V_CMP_LE_I64_e32  = 2805,
2821
    V_CMP_LE_I64_e64  = 2806,
2822
    V_CMP_LE_I64_sdwa = 2807,
2823
    V_CMP_LE_U16_e32  = 2808,
2824
    V_CMP_LE_U16_e64  = 2809,
2825
    V_CMP_LE_U16_sdwa = 2810,
2826
    V_CMP_LE_U32_e32  = 2811,
2827
    V_CMP_LE_U32_e64  = 2812,
2828
    V_CMP_LE_U32_sdwa = 2813,
2829
    V_CMP_LE_U64_e32  = 2814,
2830
    V_CMP_LE_U64_e64  = 2815,
2831
    V_CMP_LE_U64_sdwa = 2816,
2832
    V_CMP_LG_F16_e32  = 2817,
2833
    V_CMP_LG_F16_e64  = 2818,
2834
    V_CMP_LG_F16_sdwa = 2819,
2835
    V_CMP_LG_F32_e32  = 2820,
2836
    V_CMP_LG_F32_e64  = 2821,
2837
    V_CMP_LG_F32_sdwa = 2822,
2838
    V_CMP_LG_F64_e32  = 2823,
2839
    V_CMP_LG_F64_e64  = 2824,
2840
    V_CMP_LG_F64_sdwa = 2825,
2841
    V_CMP_LT_F16_e32  = 2826,
2842
    V_CMP_LT_F16_e64  = 2827,
2843
    V_CMP_LT_F16_sdwa = 2828,
2844
    V_CMP_LT_F32_e32  = 2829,
2845
    V_CMP_LT_F32_e64  = 2830,
2846
    V_CMP_LT_F32_sdwa = 2831,
2847
    V_CMP_LT_F64_e32  = 2832,
2848
    V_CMP_LT_F64_e64  = 2833,
2849
    V_CMP_LT_F64_sdwa = 2834,
2850
    V_CMP_LT_I16_e32  = 2835,
2851
    V_CMP_LT_I16_e64  = 2836,
2852
    V_CMP_LT_I16_sdwa = 2837,
2853
    V_CMP_LT_I32_e32  = 2838,
2854
    V_CMP_LT_I32_e64  = 2839,
2855
    V_CMP_LT_I32_sdwa = 2840,
2856
    V_CMP_LT_I64_e32  = 2841,
2857
    V_CMP_LT_I64_e64  = 2842,
2858
    V_CMP_LT_I64_sdwa = 2843,
2859
    V_CMP_LT_U16_e32  = 2844,
2860
    V_CMP_LT_U16_e64  = 2845,
2861
    V_CMP_LT_U16_sdwa = 2846,
2862
    V_CMP_LT_U32_e32  = 2847,
2863
    V_CMP_LT_U32_e64  = 2848,
2864
    V_CMP_LT_U32_sdwa = 2849,
2865
    V_CMP_LT_U64_e32  = 2850,
2866
    V_CMP_LT_U64_e64  = 2851,
2867
    V_CMP_LT_U64_sdwa = 2852,
2868
    V_CMP_NEQ_F16_e32 = 2853,
2869
    V_CMP_NEQ_F16_e64 = 2854,
2870
    V_CMP_NEQ_F16_sdwa  = 2855,
2871
    V_CMP_NEQ_F32_e32 = 2856,
2872
    V_CMP_NEQ_F32_e64 = 2857,
2873
    V_CMP_NEQ_F32_sdwa  = 2858,
2874
    V_CMP_NEQ_F64_e32 = 2859,
2875
    V_CMP_NEQ_F64_e64 = 2860,
2876
    V_CMP_NEQ_F64_sdwa  = 2861,
2877
    V_CMP_NE_I16_e32  = 2862,
2878
    V_CMP_NE_I16_e64  = 2863,
2879
    V_CMP_NE_I16_sdwa = 2864,
2880
    V_CMP_NE_I32_e32  = 2865,
2881
    V_CMP_NE_I32_e64  = 2866,
2882
    V_CMP_NE_I32_sdwa = 2867,
2883
    V_CMP_NE_I64_e32  = 2868,
2884
    V_CMP_NE_I64_e64  = 2869,
2885
    V_CMP_NE_I64_sdwa = 2870,
2886
    V_CMP_NE_U16_e32  = 2871,
2887
    V_CMP_NE_U16_e64  = 2872,
2888
    V_CMP_NE_U16_sdwa = 2873,
2889
    V_CMP_NE_U32_e32  = 2874,
2890
    V_CMP_NE_U32_e64  = 2875,
2891
    V_CMP_NE_U32_sdwa = 2876,
2892
    V_CMP_NE_U64_e32  = 2877,
2893
    V_CMP_NE_U64_e64  = 2878,
2894
    V_CMP_NE_U64_sdwa = 2879,
2895
    V_CMP_NGE_F16_e32 = 2880,
2896
    V_CMP_NGE_F16_e64 = 2881,
2897
    V_CMP_NGE_F16_sdwa  = 2882,
2898
    V_CMP_NGE_F32_e32 = 2883,
2899
    V_CMP_NGE_F32_e64 = 2884,
2900
    V_CMP_NGE_F32_sdwa  = 2885,
2901
    V_CMP_NGE_F64_e32 = 2886,
2902
    V_CMP_NGE_F64_e64 = 2887,
2903
    V_CMP_NGE_F64_sdwa  = 2888,
2904
    V_CMP_NGT_F16_e32 = 2889,
2905
    V_CMP_NGT_F16_e64 = 2890,
2906
    V_CMP_NGT_F16_sdwa  = 2891,
2907
    V_CMP_NGT_F32_e32 = 2892,
2908
    V_CMP_NGT_F32_e64 = 2893,
2909
    V_CMP_NGT_F32_sdwa  = 2894,
2910
    V_CMP_NGT_F64_e32 = 2895,
2911
    V_CMP_NGT_F64_e64 = 2896,
2912
    V_CMP_NGT_F64_sdwa  = 2897,
2913
    V_CMP_NLE_F16_e32 = 2898,
2914
    V_CMP_NLE_F16_e64 = 2899,
2915
    V_CMP_NLE_F16_sdwa  = 2900,
2916
    V_CMP_NLE_F32_e32 = 2901,
2917
    V_CMP_NLE_F32_e64 = 2902,
2918
    V_CMP_NLE_F32_sdwa  = 2903,
2919
    V_CMP_NLE_F64_e32 = 2904,
2920
    V_CMP_NLE_F64_e64 = 2905,
2921
    V_CMP_NLE_F64_sdwa  = 2906,
2922
    V_CMP_NLG_F16_e32 = 2907,
2923
    V_CMP_NLG_F16_e64 = 2908,
2924
    V_CMP_NLG_F16_sdwa  = 2909,
2925
    V_CMP_NLG_F32_e32 = 2910,
2926
    V_CMP_NLG_F32_e64 = 2911,
2927
    V_CMP_NLG_F32_sdwa  = 2912,
2928
    V_CMP_NLG_F64_e32 = 2913,
2929
    V_CMP_NLG_F64_e64 = 2914,
2930
    V_CMP_NLG_F64_sdwa  = 2915,
2931
    V_CMP_NLT_F16_e32 = 2916,
2932
    V_CMP_NLT_F16_e64 = 2917,
2933
    V_CMP_NLT_F16_sdwa  = 2918,
2934
    V_CMP_NLT_F32_e32 = 2919,
2935
    V_CMP_NLT_F32_e64 = 2920,
2936
    V_CMP_NLT_F32_sdwa  = 2921,
2937
    V_CMP_NLT_F64_e32 = 2922,
2938
    V_CMP_NLT_F64_e64 = 2923,
2939
    V_CMP_NLT_F64_sdwa  = 2924,
2940
    V_CMP_O_F16_e32 = 2925,
2941
    V_CMP_O_F16_e64 = 2926,
2942
    V_CMP_O_F16_sdwa  = 2927,
2943
    V_CMP_O_F32_e32 = 2928,
2944
    V_CMP_O_F32_e64 = 2929,
2945
    V_CMP_O_F32_sdwa  = 2930,
2946
    V_CMP_O_F64_e32 = 2931,
2947
    V_CMP_O_F64_e64 = 2932,
2948
    V_CMP_O_F64_sdwa  = 2933,
2949
    V_CMP_TRU_F16_e32 = 2934,
2950
    V_CMP_TRU_F16_e64 = 2935,
2951
    V_CMP_TRU_F16_sdwa  = 2936,
2952
    V_CMP_TRU_F32_e32 = 2937,
2953
    V_CMP_TRU_F32_e64 = 2938,
2954
    V_CMP_TRU_F32_sdwa  = 2939,
2955
    V_CMP_TRU_F64_e32 = 2940,
2956
    V_CMP_TRU_F64_e64 = 2941,
2957
    V_CMP_TRU_F64_sdwa  = 2942,
2958
    V_CMP_T_I16_e32 = 2943,
2959
    V_CMP_T_I16_e64 = 2944,
2960
    V_CMP_T_I16_sdwa  = 2945,
2961
    V_CMP_T_I32_e32 = 2946,
2962
    V_CMP_T_I32_e64 = 2947,
2963
    V_CMP_T_I32_sdwa  = 2948,
2964
    V_CMP_T_I64_e32 = 2949,
2965
    V_CMP_T_I64_e64 = 2950,
2966
    V_CMP_T_I64_sdwa  = 2951,
2967
    V_CMP_T_U16_e32 = 2952,
2968
    V_CMP_T_U16_e64 = 2953,
2969
    V_CMP_T_U16_sdwa  = 2954,
2970
    V_CMP_T_U32_e32 = 2955,
2971
    V_CMP_T_U32_e64 = 2956,
2972
    V_CMP_T_U32_sdwa  = 2957,
2973
    V_CMP_T_U64_e32 = 2958,
2974
    V_CMP_T_U64_e64 = 2959,
2975
    V_CMP_T_U64_sdwa  = 2960,
2976
    V_CMP_U_F16_e32 = 2961,
2977
    V_CMP_U_F16_e64 = 2962,
2978
    V_CMP_U_F16_sdwa  = 2963,
2979
    V_CMP_U_F32_e32 = 2964,
2980
    V_CMP_U_F32_e64 = 2965,
2981
    V_CMP_U_F32_sdwa  = 2966,
2982
    V_CMP_U_F64_e32 = 2967,
2983
    V_CMP_U_F64_e64 = 2968,
2984
    V_CMP_U_F64_sdwa  = 2969,
2985
    V_CNDMASK_B32_e32 = 2970,
2986
    V_CNDMASK_B32_e64 = 2971,
2987
    V_CNDMASK_B32_sdwa  = 2972,
2988
    V_CNDMASK_B64_PSEUDO  = 2973,
2989
    V_COS_F16_e32 = 2974,
2990
    V_COS_F16_e64 = 2975,
2991
    V_COS_F16_sdwa  = 2976,
2992
    V_COS_F32_e32 = 2977,
2993
    V_COS_F32_e64 = 2978,
2994
    V_COS_F32_sdwa  = 2979,
2995
    V_CUBEID_F32  = 2980,
2996
    V_CUBEMA_F32  = 2981,
2997
    V_CUBESC_F32  = 2982,
2998
    V_CUBETC_F32  = 2983,
2999
    V_CVT_F16_F32_e32 = 2984,
3000
    V_CVT_F16_F32_e64 = 2985,
3001
    V_CVT_F16_F32_sdwa  = 2986,
3002
    V_CVT_F16_I16_e32 = 2987,
3003
    V_CVT_F16_I16_e64 = 2988,
3004
    V_CVT_F16_I16_sdwa  = 2989,
3005
    V_CVT_F16_U16_e32 = 2990,
3006
    V_CVT_F16_U16_e64 = 2991,
3007
    V_CVT_F16_U16_sdwa  = 2992,
3008
    V_CVT_F32_F16_e32 = 2993,
3009
    V_CVT_F32_F16_e64 = 2994,
3010
    V_CVT_F32_F16_sdwa  = 2995,
3011
    V_CVT_F32_F64_e32 = 2996,
3012
    V_CVT_F32_F64_e64 = 2997,
3013
    V_CVT_F32_F64_sdwa  = 2998,
3014
    V_CVT_F32_I32_e32 = 2999,
3015
    V_CVT_F32_I32_e64 = 3000,
3016
    V_CVT_F32_I32_sdwa  = 3001,
3017
    V_CVT_F32_U32_e32 = 3002,
3018
    V_CVT_F32_U32_e64 = 3003,
3019
    V_CVT_F32_U32_sdwa  = 3004,
3020
    V_CVT_F32_UBYTE0_e32  = 3005,
3021
    V_CVT_F32_UBYTE0_e64  = 3006,
3022
    V_CVT_F32_UBYTE0_sdwa = 3007,
3023
    V_CVT_F32_UBYTE1_e32  = 3008,
3024
    V_CVT_F32_UBYTE1_e64  = 3009,
3025
    V_CVT_F32_UBYTE1_sdwa = 3010,
3026
    V_CVT_F32_UBYTE2_e32  = 3011,
3027
    V_CVT_F32_UBYTE2_e64  = 3012,
3028
    V_CVT_F32_UBYTE2_sdwa = 3013,
3029
    V_CVT_F32_UBYTE3_e32  = 3014,
3030
    V_CVT_F32_UBYTE3_e64  = 3015,
3031
    V_CVT_F32_UBYTE3_sdwa = 3016,
3032
    V_CVT_F64_F32_e32 = 3017,
3033
    V_CVT_F64_F32_e64 = 3018,
3034
    V_CVT_F64_F32_sdwa  = 3019,
3035
    V_CVT_F64_I32_e32 = 3020,
3036
    V_CVT_F64_I32_e64 = 3021,
3037
    V_CVT_F64_I32_sdwa  = 3022,
3038
    V_CVT_F64_U32_e32 = 3023,
3039
    V_CVT_F64_U32_e64 = 3024,
3040
    V_CVT_F64_U32_sdwa  = 3025,
3041
    V_CVT_FLR_I32_F32_e32 = 3026,
3042
    V_CVT_FLR_I32_F32_e64 = 3027,
3043
    V_CVT_FLR_I32_F32_sdwa  = 3028,
3044
    V_CVT_I16_F16_e32 = 3029,
3045
    V_CVT_I16_F16_e64 = 3030,
3046
    V_CVT_I16_F16_sdwa  = 3031,
3047
    V_CVT_I32_F32_e32 = 3032,
3048
    V_CVT_I32_F32_e64 = 3033,
3049
    V_CVT_I32_F32_sdwa  = 3034,
3050
    V_CVT_I32_F64_e32 = 3035,
3051
    V_CVT_I32_F64_e64 = 3036,
3052
    V_CVT_I32_F64_sdwa  = 3037,
3053
    V_CVT_NORM_I16_F16_e32  = 3038,
3054
    V_CVT_NORM_I16_F16_e64  = 3039,
3055
    V_CVT_NORM_I16_F16_sdwa = 3040,
3056
    V_CVT_NORM_U16_F16_e32  = 3041,
3057
    V_CVT_NORM_U16_F16_e64  = 3042,
3058
    V_CVT_NORM_U16_F16_sdwa = 3043,
3059
    V_CVT_OFF_F32_I4_e32  = 3044,
3060
    V_CVT_OFF_F32_I4_e64  = 3045,
3061
    V_CVT_OFF_F32_I4_sdwa = 3046,
3062
    V_CVT_PKACCUM_U8_F32_e32  = 3047,
3063
    V_CVT_PKACCUM_U8_F32_e64  = 3048,
3064
    V_CVT_PKACCUM_U8_F32_sdwa = 3049,
3065
    V_CVT_PKNORM_I16_F16  = 3050,
3066
    V_CVT_PKNORM_I16_F32_e32  = 3051,
3067
    V_CVT_PKNORM_I16_F32_e64  = 3052,
3068
    V_CVT_PKNORM_I16_F32_sdwa = 3053,
3069
    V_CVT_PKNORM_U16_F16  = 3054,
3070
    V_CVT_PKNORM_U16_F32_e32  = 3055,
3071
    V_CVT_PKNORM_U16_F32_e64  = 3056,
3072
    V_CVT_PKNORM_U16_F32_sdwa = 3057,
3073
    V_CVT_PKRTZ_F16_F32_e32 = 3058,
3074
    V_CVT_PKRTZ_F16_F32_e64 = 3059,
3075
    V_CVT_PKRTZ_F16_F32_sdwa  = 3060,
3076
    V_CVT_PK_I16_I32_e32  = 3061,
3077
    V_CVT_PK_I16_I32_e64  = 3062,
3078
    V_CVT_PK_I16_I32_sdwa = 3063,
3079
    V_CVT_PK_U16_U32_e32  = 3064,
3080
    V_CVT_PK_U16_U32_e64  = 3065,
3081
    V_CVT_PK_U16_U32_sdwa = 3066,
3082
    V_CVT_PK_U8_F32 = 3067,
3083
    V_CVT_RPI_I32_F32_e32 = 3068,
3084
    V_CVT_RPI_I32_F32_e64 = 3069,
3085
    V_CVT_RPI_I32_F32_sdwa  = 3070,
3086
    V_CVT_U16_F16_e32 = 3071,
3087
    V_CVT_U16_F16_e64 = 3072,
3088
    V_CVT_U16_F16_sdwa  = 3073,
3089
    V_CVT_U32_F32_e32 = 3074,
3090
    V_CVT_U32_F32_e64 = 3075,
3091
    V_CVT_U32_F32_sdwa  = 3076,
3092
    V_CVT_U32_F64_e32 = 3077,
3093
    V_CVT_U32_F64_e64 = 3078,
3094
    V_CVT_U32_F64_sdwa  = 3079,
3095
    V_DIV_FIXUP_F16 = 3080,
3096
    V_DIV_FIXUP_F16_gfx9  = 3081,
3097
    V_DIV_FIXUP_F32 = 3082,
3098
    V_DIV_FIXUP_F64 = 3083,
3099
    V_DIV_FMAS_F32  = 3084,
3100
    V_DIV_FMAS_F64  = 3085,
3101
    V_DIV_SCALE_F32 = 3086,
3102
    V_DIV_SCALE_F64 = 3087,
3103
    V_DOT2_F32_F16  = 3088,
3104
    V_DOT2_I32_I16  = 3089,
3105
    V_DOT2_U32_U16  = 3090,
3106
    V_DOT4_I32_I8 = 3091,
3107
    V_DOT4_U32_U8 = 3092,
3108
    V_DOT8_I32_I4 = 3093,
3109
    V_DOT8_U32_U4 = 3094,
3110
    V_EXP_F16_e32 = 3095,
3111
    V_EXP_F16_e64 = 3096,
3112
    V_EXP_F16_sdwa  = 3097,
3113
    V_EXP_F32_e32 = 3098,
3114
    V_EXP_F32_e64 = 3099,
3115
    V_EXP_F32_sdwa  = 3100,
3116
    V_EXP_LEGACY_F32_e32  = 3101,
3117
    V_EXP_LEGACY_F32_e64  = 3102,
3118
    V_EXP_LEGACY_F32_sdwa = 3103,
3119
    V_FFBH_I32_e32  = 3104,
3120
    V_FFBH_I32_e64  = 3105,
3121
    V_FFBH_I32_sdwa = 3106,
3122
    V_FFBH_U32_e32  = 3107,
3123
    V_FFBH_U32_e64  = 3108,
3124
    V_FFBH_U32_sdwa = 3109,
3125
    V_FFBL_B32_e32  = 3110,
3126
    V_FFBL_B32_e64  = 3111,
3127
    V_FFBL_B32_sdwa = 3112,
3128
    V_FLOOR_F16_e32 = 3113,
3129
    V_FLOOR_F16_e64 = 3114,
3130
    V_FLOOR_F16_sdwa  = 3115,
3131
    V_FLOOR_F32_e32 = 3116,
3132
    V_FLOOR_F32_e64 = 3117,
3133
    V_FLOOR_F32_sdwa  = 3118,
3134
    V_FLOOR_F64_e32 = 3119,
3135
    V_FLOOR_F64_e64 = 3120,
3136
    V_FLOOR_F64_sdwa  = 3121,
3137
    V_FMAC_F32_e32  = 3122,
3138
    V_FMAC_F32_e64  = 3123,
3139
    V_FMAC_F32_sdwa = 3124,
3140
    V_FMA_F16 = 3125,
3141
    V_FMA_F16_gfx9  = 3126,
3142
    V_FMA_F32 = 3127,
3143
    V_FMA_F64 = 3128,
3144
    V_FMA_MIXHI_F16 = 3129,
3145
    V_FMA_MIXLO_F16 = 3130,
3146
    V_FMA_MIX_F32 = 3131,
3147
    V_FRACT_F16_e32 = 3132,
3148
    V_FRACT_F16_e64 = 3133,
3149
    V_FRACT_F16_sdwa  = 3134,
3150
    V_FRACT_F32_e32 = 3135,
3151
    V_FRACT_F32_e64 = 3136,
3152
    V_FRACT_F32_sdwa  = 3137,
3153
    V_FRACT_F64_e32 = 3138,
3154
    V_FRACT_F64_e64 = 3139,
3155
    V_FRACT_F64_sdwa  = 3140,
3156
    V_FREXP_EXP_I16_F16_e32 = 3141,
3157
    V_FREXP_EXP_I16_F16_e64 = 3142,
3158
    V_FREXP_EXP_I16_F16_sdwa  = 3143,
3159
    V_FREXP_EXP_I32_F32_e32 = 3144,
3160
    V_FREXP_EXP_I32_F32_e64 = 3145,
3161
    V_FREXP_EXP_I32_F32_sdwa  = 3146,
3162
    V_FREXP_EXP_I32_F64_e32 = 3147,
3163
    V_FREXP_EXP_I32_F64_e64 = 3148,
3164
    V_FREXP_EXP_I32_F64_sdwa  = 3149,
3165
    V_FREXP_MANT_F16_e32  = 3150,
3166
    V_FREXP_MANT_F16_e64  = 3151,
3167
    V_FREXP_MANT_F16_sdwa = 3152,
3168
    V_FREXP_MANT_F32_e32  = 3153,
3169
    V_FREXP_MANT_F32_e64  = 3154,
3170
    V_FREXP_MANT_F32_sdwa = 3155,
3171
    V_FREXP_MANT_F64_e32  = 3156,
3172
    V_FREXP_MANT_F64_e64  = 3157,
3173
    V_FREXP_MANT_F64_sdwa = 3158,
3174
    V_INTERP_MOV_F32  = 3159,
3175
    V_INTERP_MOV_F32_e64  = 3160,
3176
    V_INTERP_P1LL_F16 = 3161,
3177
    V_INTERP_P1LV_F16 = 3162,
3178
    V_INTERP_P1_F32 = 3163,
3179
    V_INTERP_P1_F32_16bank  = 3164,
3180
    V_INTERP_P1_F32_e64 = 3165,
3181
    V_INTERP_P2_F16 = 3166,
3182
    V_INTERP_P2_F16_gfx9  = 3167,
3183
    V_INTERP_P2_F32 = 3168,
3184
    V_INTERP_P2_F32_e64 = 3169,
3185
    V_LDEXP_F16_e32 = 3170,
3186
    V_LDEXP_F16_e64 = 3171,
3187
    V_LDEXP_F16_sdwa  = 3172,
3188
    V_LDEXP_F32_e32 = 3173,
3189
    V_LDEXP_F32_e64 = 3174,
3190
    V_LDEXP_F32_sdwa  = 3175,
3191
    V_LDEXP_F64 = 3176,
3192
    V_LERP_U8 = 3177,
3193
    V_LOG_CLAMP_F32_e32 = 3178,
3194
    V_LOG_CLAMP_F32_e64 = 3179,
3195
    V_LOG_CLAMP_F32_sdwa  = 3180,
3196
    V_LOG_F16_e32 = 3181,
3197
    V_LOG_F16_e64 = 3182,
3198
    V_LOG_F16_sdwa  = 3183,
3199
    V_LOG_F32_e32 = 3184,
3200
    V_LOG_F32_e64 = 3185,
3201
    V_LOG_F32_sdwa  = 3186,
3202
    V_LOG_LEGACY_F32_e32  = 3187,
3203
    V_LOG_LEGACY_F32_e64  = 3188,
3204
    V_LOG_LEGACY_F32_sdwa = 3189,
3205
    V_LSHLREV_B16_e32 = 3190,
3206
    V_LSHLREV_B16_e64 = 3191,
3207
    V_LSHLREV_B16_sdwa  = 3192,
3208
    V_LSHLREV_B32_e32 = 3193,
3209
    V_LSHLREV_B32_e64 = 3194,
3210
    V_LSHLREV_B32_sdwa  = 3195,
3211
    V_LSHLREV_B64 = 3196,
3212
    V_LSHL_ADD_U32  = 3197,
3213
    V_LSHL_B32_e32  = 3198,
3214
    V_LSHL_B32_e64  = 3199,
3215
    V_LSHL_B32_sdwa = 3200,
3216
    V_LSHL_B64  = 3201,
3217
    V_LSHL_OR_B32 = 3202,
3218
    V_LSHRREV_B16_e32 = 3203,
3219
    V_LSHRREV_B16_e64 = 3204,
3220
    V_LSHRREV_B16_sdwa  = 3205,
3221
    V_LSHRREV_B32_e32 = 3206,
3222
    V_LSHRREV_B32_e64 = 3207,
3223
    V_LSHRREV_B32_sdwa  = 3208,
3224
    V_LSHRREV_B64 = 3209,
3225
    V_LSHR_B32_e32  = 3210,
3226
    V_LSHR_B32_e64  = 3211,
3227
    V_LSHR_B32_sdwa = 3212,
3228
    V_LSHR_B64  = 3213,
3229
    V_MAC_F16_e32 = 3214,
3230
    V_MAC_F16_e64 = 3215,
3231
    V_MAC_F16_sdwa  = 3216,
3232
    V_MAC_F32_e32 = 3217,
3233
    V_MAC_F32_e64 = 3218,
3234
    V_MAC_F32_sdwa  = 3219,
3235
    V_MAC_LEGACY_F32_e32  = 3220,
3236
    V_MAC_LEGACY_F32_e64  = 3221,
3237
    V_MAC_LEGACY_F32_sdwa = 3222,
3238
    V_MADAK_F16 = 3223,
3239
    V_MADAK_F32 = 3224,
3240
    V_MADMK_F16 = 3225,
3241
    V_MADMK_F32 = 3226,
3242
    V_MAD_F16 = 3227,
3243
    V_MAD_F16_gfx9  = 3228,
3244
    V_MAD_F32 = 3229,
3245
    V_MAD_I16 = 3230,
3246
    V_MAD_I16_gfx9  = 3231,
3247
    V_MAD_I32_I16 = 3232,
3248
    V_MAD_I32_I24 = 3233,
3249
    V_MAD_I64_I32 = 3234,
3250
    V_MAD_LEGACY_F32  = 3235,
3251
    V_MAD_MIXHI_F16 = 3236,
3252
    V_MAD_MIXLO_F16 = 3237,
3253
    V_MAD_MIX_F32 = 3238,
3254
    V_MAD_U16 = 3239,
3255
    V_MAD_U16_gfx9  = 3240,
3256
    V_MAD_U32_U16 = 3241,
3257
    V_MAD_U32_U24 = 3242,
3258
    V_MAD_U64_U32 = 3243,
3259
    V_MAX3_F16  = 3244,
3260
    V_MAX3_F32  = 3245,
3261
    V_MAX3_I16  = 3246,
3262
    V_MAX3_I32  = 3247,
3263
    V_MAX3_U16  = 3248,
3264
    V_MAX3_U32  = 3249,
3265
    V_MAX_F16_e32 = 3250,
3266
    V_MAX_F16_e64 = 3251,
3267
    V_MAX_F16_sdwa  = 3252,
3268
    V_MAX_F32_e32 = 3253,
3269
    V_MAX_F32_e64 = 3254,
3270
    V_MAX_F32_sdwa  = 3255,
3271
    V_MAX_F64 = 3256,
3272
    V_MAX_I16_e32 = 3257,
3273
    V_MAX_I16_e64 = 3258,
3274
    V_MAX_I16_sdwa  = 3259,
3275
    V_MAX_I32_e32 = 3260,
3276
    V_MAX_I32_e64 = 3261,
3277
    V_MAX_I32_sdwa  = 3262,
3278
    V_MAX_LEGACY_F32_e32  = 3263,
3279
    V_MAX_LEGACY_F32_e64  = 3264,
3280
    V_MAX_LEGACY_F32_sdwa = 3265,
3281
    V_MAX_U16_e32 = 3266,
3282
    V_MAX_U16_e64 = 3267,
3283
    V_MAX_U16_sdwa  = 3268,
3284
    V_MAX_U32_e32 = 3269,
3285
    V_MAX_U32_e64 = 3270,
3286
    V_MAX_U32_sdwa  = 3271,
3287
    V_MBCNT_HI_U32_B32_e32  = 3272,
3288
    V_MBCNT_HI_U32_B32_e64  = 3273,
3289
    V_MBCNT_HI_U32_B32_sdwa = 3274,
3290
    V_MBCNT_LO_U32_B32_e32  = 3275,
3291
    V_MBCNT_LO_U32_B32_e64  = 3276,
3292
    V_MBCNT_LO_U32_B32_sdwa = 3277,
3293
    V_MED3_F16  = 3278,
3294
    V_MED3_F32  = 3279,
3295
    V_MED3_I16  = 3280,
3296
    V_MED3_I32  = 3281,
3297
    V_MED3_U16  = 3282,
3298
    V_MED3_U32  = 3283,
3299
    V_MIN3_F16  = 3284,
3300
    V_MIN3_F32  = 3285,
3301
    V_MIN3_I16  = 3286,
3302
    V_MIN3_I32  = 3287,
3303
    V_MIN3_U16  = 3288,
3304
    V_MIN3_U32  = 3289,
3305
    V_MIN_F16_e32 = 3290,
3306
    V_MIN_F16_e64 = 3291,
3307
    V_MIN_F16_sdwa  = 3292,
3308
    V_MIN_F32_e32 = 3293,
3309
    V_MIN_F32_e64 = 3294,
3310
    V_MIN_F32_sdwa  = 3295,
3311
    V_MIN_F64 = 3296,
3312
    V_MIN_I16_e32 = 3297,
3313
    V_MIN_I16_e64 = 3298,
3314
    V_MIN_I16_sdwa  = 3299,
3315
    V_MIN_I32_e32 = 3300,
3316
    V_MIN_I32_e64 = 3301,
3317
    V_MIN_I32_sdwa  = 3302,
3318
    V_MIN_LEGACY_F32_e32  = 3303,
3319
    V_MIN_LEGACY_F32_e64  = 3304,
3320
    V_MIN_LEGACY_F32_sdwa = 3305,
3321
    V_MIN_U16_e32 = 3306,
3322
    V_MIN_U16_e64 = 3307,
3323
    V_MIN_U16_sdwa  = 3308,
3324
    V_MIN_U32_e32 = 3309,
3325
    V_MIN_U32_e64 = 3310,
3326
    V_MIN_U32_sdwa  = 3311,
3327
    V_MOVRELD_B32_V1  = 3312,
3328
    V_MOVRELD_B32_V16 = 3313,
3329
    V_MOVRELD_B32_V2  = 3314,
3330
    V_MOVRELD_B32_V4  = 3315,
3331
    V_MOVRELD_B32_V8  = 3316,
3332
    V_MOVRELD_B32_e32 = 3317,
3333
    V_MOVRELD_B32_e64 = 3318,
3334
    V_MOVRELD_B32_sdwa  = 3319,
3335
    V_MOVRELSD_B32_e32  = 3320,
3336
    V_MOVRELSD_B32_e64  = 3321,
3337
    V_MOVRELSD_B32_sdwa = 3322,
3338
    V_MOVRELS_B32_e32 = 3323,
3339
    V_MOVRELS_B32_e64 = 3324,
3340
    V_MOVRELS_B32_sdwa  = 3325,
3341
    V_MOV_B32_e32 = 3326,
3342
    V_MOV_B32_e64 = 3327,
3343
    V_MOV_B32_indirect  = 3328,
3344
    V_MOV_B32_sdwa  = 3329,
3345
    V_MOV_B64_PSEUDO  = 3330,
3346
    V_MOV_FED_B32_e32 = 3331,
3347
    V_MOV_FED_B32_e64 = 3332,
3348
    V_MOV_FED_B32_sdwa  = 3333,
3349
    V_MQSAD_PK_U16_U8 = 3334,
3350
    V_MQSAD_U32_U8  = 3335,
3351
    V_MSAD_U8 = 3336,
3352
    V_MULLIT_F32  = 3337,
3353
    V_MUL_F16_e32 = 3338,
3354
    V_MUL_F16_e64 = 3339,
3355
    V_MUL_F16_sdwa  = 3340,
3356
    V_MUL_F32_e32 = 3341,
3357
    V_MUL_F32_e64 = 3342,
3358
    V_MUL_F32_sdwa  = 3343,
3359
    V_MUL_F64 = 3344,
3360
    V_MUL_HI_I32  = 3345,
3361
    V_MUL_HI_I32_I24_e32  = 3346,
3362
    V_MUL_HI_I32_I24_e64  = 3347,
3363
    V_MUL_HI_I32_I24_sdwa = 3348,
3364
    V_MUL_HI_U32  = 3349,
3365
    V_MUL_HI_U32_U24_e32  = 3350,
3366
    V_MUL_HI_U32_U24_e64  = 3351,
3367
    V_MUL_HI_U32_U24_sdwa = 3352,
3368
    V_MUL_I32_I24_e32 = 3353,
3369
    V_MUL_I32_I24_e64 = 3354,
3370
    V_MUL_I32_I24_sdwa  = 3355,
3371
    V_MUL_LEGACY_F32_e32  = 3356,
3372
    V_MUL_LEGACY_F32_e64  = 3357,
3373
    V_MUL_LEGACY_F32_sdwa = 3358,
3374
    V_MUL_LO_I32  = 3359,
3375
    V_MUL_LO_U16_e32  = 3360,
3376
    V_MUL_LO_U16_e64  = 3361,
3377
    V_MUL_LO_U16_sdwa = 3362,
3378
    V_MUL_LO_U32  = 3363,
3379
    V_MUL_U32_U24_e32 = 3364,
3380
    V_MUL_U32_U24_e64 = 3365,
3381
    V_MUL_U32_U24_sdwa  = 3366,
3382
    V_NOP_e32 = 3367,
3383
    V_NOP_e64 = 3368,
3384
    V_NOP_sdwa  = 3369,
3385
    V_NOT_B32_e32 = 3370,
3386
    V_NOT_B32_e64 = 3371,
3387
    V_NOT_B32_sdwa  = 3372,
3388
    V_OR3_B32 = 3373,
3389
    V_OR_B32_e32  = 3374,
3390
    V_OR_B32_e64  = 3375,
3391
    V_OR_B32_sdwa = 3376,
3392
    V_PACK_B32_F16  = 3377,
3393
    V_PERM_B32  = 3378,
3394
    V_PK_ADD_F16  = 3379,
3395
    V_PK_ADD_I16  = 3380,
3396
    V_PK_ADD_U16  = 3381,
3397
    V_PK_ASHRREV_I16  = 3382,
3398
    V_PK_FMA_F16  = 3383,
3399
    V_PK_LSHLREV_B16  = 3384,
3400
    V_PK_LSHRREV_B16  = 3385,
3401
    V_PK_MAD_I16  = 3386,
3402
    V_PK_MAD_U16  = 3387,
3403
    V_PK_MAX_F16  = 3388,
3404
    V_PK_MAX_I16  = 3389,
3405
    V_PK_MAX_U16  = 3390,
3406
    V_PK_MIN_F16  = 3391,
3407
    V_PK_MIN_I16  = 3392,
3408
    V_PK_MIN_U16  = 3393,
3409
    V_PK_MUL_F16  = 3394,
3410
    V_PK_MUL_LO_U16 = 3395,
3411
    V_PK_SUB_I16  = 3396,
3412
    V_PK_SUB_U16  = 3397,
3413
    V_QSAD_PK_U16_U8  = 3398,
3414
    V_RCP_CLAMP_F32_e32 = 3399,
3415
    V_RCP_CLAMP_F32_e64 = 3400,
3416
    V_RCP_CLAMP_F32_sdwa  = 3401,
3417
    V_RCP_CLAMP_F64_e32 = 3402,
3418
    V_RCP_CLAMP_F64_e64 = 3403,
3419
    V_RCP_CLAMP_F64_sdwa  = 3404,
3420
    V_RCP_F16_e32 = 3405,
3421
    V_RCP_F16_e64 = 3406,
3422
    V_RCP_F16_sdwa  = 3407,
3423
    V_RCP_F32_e32 = 3408,
3424
    V_RCP_F32_e64 = 3409,
3425
    V_RCP_F32_sdwa  = 3410,
3426
    V_RCP_F64_e32 = 3411,
3427
    V_RCP_F64_e64 = 3412,
3428
    V_RCP_F64_sdwa  = 3413,
3429
    V_RCP_IFLAG_F32_e32 = 3414,
3430
    V_RCP_IFLAG_F32_e64 = 3415,
3431
    V_RCP_IFLAG_F32_sdwa  = 3416,
3432
    V_RCP_LEGACY_F32_e32  = 3417,
3433
    V_RCP_LEGACY_F32_e64  = 3418,
3434
    V_RCP_LEGACY_F32_sdwa = 3419,
3435
    V_READLANE_B32  = 3420,
3436
    V_RNDNE_F16_e32 = 3421,
3437
    V_RNDNE_F16_e64 = 3422,
3438
    V_RNDNE_F16_sdwa  = 3423,
3439
    V_RNDNE_F32_e32 = 3424,
3440
    V_RNDNE_F32_e64 = 3425,
3441
    V_RNDNE_F32_sdwa  = 3426,
3442
    V_RNDNE_F64_e32 = 3427,
3443
    V_RNDNE_F64_e64 = 3428,
3444
    V_RNDNE_F64_sdwa  = 3429,
3445
    V_RSQ_CLAMP_F32_e32 = 3430,
3446
    V_RSQ_CLAMP_F32_e64 = 3431,
3447
    V_RSQ_CLAMP_F32_sdwa  = 3432,
3448
    V_RSQ_CLAMP_F64_e32 = 3433,
3449
    V_RSQ_CLAMP_F64_e64 = 3434,
3450
    V_RSQ_CLAMP_F64_sdwa  = 3435,
3451
    V_RSQ_F16_e32 = 3436,
3452
    V_RSQ_F16_e64 = 3437,
3453
    V_RSQ_F16_sdwa  = 3438,
3454
    V_RSQ_F32_e32 = 3439,
3455
    V_RSQ_F32_e64 = 3440,
3456
    V_RSQ_F32_sdwa  = 3441,
3457
    V_RSQ_F64_e32 = 3442,
3458
    V_RSQ_F64_e64 = 3443,
3459
    V_RSQ_F64_sdwa  = 3444,
3460
    V_RSQ_LEGACY_F32_e32  = 3445,
3461
    V_RSQ_LEGACY_F32_e64  = 3446,
3462
    V_RSQ_LEGACY_F32_sdwa = 3447,
3463
    V_SAD_HI_U8 = 3448,
3464
    V_SAD_U16 = 3449,
3465
    V_SAD_U32 = 3450,
3466
    V_SAD_U8  = 3451,
3467
    V_SAT_PK_U8_I16_e32 = 3452,
3468
    V_SAT_PK_U8_I16_e64 = 3453,
3469
    V_SAT_PK_U8_I16_sdwa  = 3454,
3470
    V_SCREEN_PARTITION_4SE_B32_e32  = 3455,
3471
    V_SCREEN_PARTITION_4SE_B32_e64  = 3456,
3472
    V_SCREEN_PARTITION_4SE_B32_sdwa = 3457,
3473
    V_SET_INACTIVE_B32  = 3458,
3474
    V_SET_INACTIVE_B64  = 3459,
3475
    V_SIN_F16_e32 = 3460,
3476
    V_SIN_F16_e64 = 3461,
3477
    V_SIN_F16_sdwa  = 3462,
3478
    V_SIN_F32_e32 = 3463,
3479
    V_SIN_F32_e64 = 3464,
3480
    V_SIN_F32_sdwa  = 3465,
3481
    V_SQRT_F16_e32  = 3466,
3482
    V_SQRT_F16_e64  = 3467,
3483
    V_SQRT_F16_sdwa = 3468,
3484
    V_SQRT_F32_e32  = 3469,
3485
    V_SQRT_F32_e64  = 3470,
3486
    V_SQRT_F32_sdwa = 3471,
3487
    V_SQRT_F64_e32  = 3472,
3488
    V_SQRT_F64_e64  = 3473,
3489
    V_SQRT_F64_sdwa = 3474,
3490
    V_SUBBREV_U32_e32 = 3475,
3491
    V_SUBBREV_U32_e64 = 3476,
3492
    V_SUBBREV_U32_sdwa  = 3477,
3493
    V_SUBB_U32_e32  = 3478,
3494
    V_SUBB_U32_e64  = 3479,
3495
    V_SUBB_U32_sdwa = 3480,
3496
    V_SUBREV_F16_e32  = 3481,
3497
    V_SUBREV_F16_e64  = 3482,
3498
    V_SUBREV_F16_sdwa = 3483,
3499
    V_SUBREV_F32_e32  = 3484,
3500
    V_SUBREV_F32_e64  = 3485,
3501
    V_SUBREV_F32_sdwa = 3486,
3502
    V_SUBREV_I32_e32  = 3487,
3503
    V_SUBREV_I32_e64  = 3488,
3504
    V_SUBREV_I32_sdwa = 3489,
3505
    V_SUBREV_U16_e32  = 3490,
3506
    V_SUBREV_U16_e64  = 3491,
3507
    V_SUBREV_U16_sdwa = 3492,
3508
    V_SUBREV_U32_e32  = 3493,
3509
    V_SUBREV_U32_e64  = 3494,
3510
    V_SUBREV_U32_sdwa = 3495,
3511
    V_SUB_F16_e32 = 3496,
3512
    V_SUB_F16_e64 = 3497,
3513
    V_SUB_F16_sdwa  = 3498,
3514
    V_SUB_F32_e32 = 3499,
3515
    V_SUB_F32_e64 = 3500,
3516
    V_SUB_F32_sdwa  = 3501,
3517
    V_SUB_I16 = 3502,
3518
    V_SUB_I32_e32 = 3503,
3519
    V_SUB_I32_e64 = 3504,
3520
    V_SUB_I32_gfx9  = 3505,
3521
    V_SUB_I32_sdwa  = 3506,
3522
    V_SUB_U16_e32 = 3507,
3523
    V_SUB_U16_e64 = 3508,
3524
    V_SUB_U16_sdwa  = 3509,
3525
    V_SUB_U32_e32 = 3510,
3526
    V_SUB_U32_e64 = 3511,
3527
    V_SUB_U32_sdwa  = 3512,
3528
    V_SWAP_B32  = 3513,
3529
    V_TRIG_PREOP_F64  = 3514,
3530
    V_TRUNC_F16_e32 = 3515,
3531
    V_TRUNC_F16_e64 = 3516,
3532
    V_TRUNC_F16_sdwa  = 3517,
3533
    V_TRUNC_F32_e32 = 3518,
3534
    V_TRUNC_F32_e64 = 3519,
3535
    V_TRUNC_F32_sdwa  = 3520,
3536
    V_TRUNC_F64_e32 = 3521,
3537
    V_TRUNC_F64_e64 = 3522,
3538
    V_TRUNC_F64_sdwa  = 3523,
3539
    V_WRITELANE_B32 = 3524,
3540
    V_XAD_U32 = 3525,
3541
    V_XNOR_B32_e32  = 3526,
3542
    V_XNOR_B32_e64  = 3527,
3543
    V_XNOR_B32_sdwa = 3528,
3544
    V_XOR_B32_e32 = 3529,
3545
    V_XOR_B32_e64 = 3530,
3546
    V_XOR_B32_sdwa  = 3531,
3547
    WAVE_BARRIER  = 3532,
3548
    WQM = 3533,
3549
    WWM = 3534,
3550
    BUFFER_ATOMIC_ADD_ADDR64_RTN_si = 3535,
3551
    BUFFER_ATOMIC_ADD_ADDR64_si = 3536,
3552
    BUFFER_ATOMIC_ADD_BOTHEN_RTN_si = 3537,
3553
    BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi = 3538,
3554
    BUFFER_ATOMIC_ADD_BOTHEN_si = 3539,
3555
    BUFFER_ATOMIC_ADD_BOTHEN_vi = 3540,
3556
    BUFFER_ATOMIC_ADD_IDXEN_RTN_si  = 3541,
3557
    BUFFER_ATOMIC_ADD_IDXEN_RTN_vi  = 3542,
3558
    BUFFER_ATOMIC_ADD_IDXEN_si  = 3543,
3559
    BUFFER_ATOMIC_ADD_IDXEN_vi  = 3544,
3560
    BUFFER_ATOMIC_ADD_OFFEN_RTN_si  = 3545,
3561
    BUFFER_ATOMIC_ADD_OFFEN_RTN_vi  = 3546,
3562
    BUFFER_ATOMIC_ADD_OFFEN_si  = 3547,
3563
    BUFFER_ATOMIC_ADD_OFFEN_vi  = 3548,
3564
    BUFFER_ATOMIC_ADD_OFFSET_RTN_si = 3549,
3565
    BUFFER_ATOMIC_ADD_OFFSET_RTN_vi = 3550,
3566
    BUFFER_ATOMIC_ADD_OFFSET_si = 3551,
3567
    BUFFER_ATOMIC_ADD_OFFSET_vi = 3552,
3568
    BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_si  = 3553,
3569
    BUFFER_ATOMIC_ADD_X2_ADDR64_si  = 3554,
3570
    BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_si  = 3555,
3571
    BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi  = 3556,
3572
    BUFFER_ATOMIC_ADD_X2_BOTHEN_si  = 3557,
3573
    BUFFER_ATOMIC_ADD_X2_BOTHEN_vi  = 3558,
3574
    BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_si = 3559,
3575
    BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi = 3560,
3576
    BUFFER_ATOMIC_ADD_X2_IDXEN_si = 3561,
3577
    BUFFER_ATOMIC_ADD_X2_IDXEN_vi = 3562,
3578
    BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_si = 3563,
3579
    BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi = 3564,
3580
    BUFFER_ATOMIC_ADD_X2_OFFEN_si = 3565,
3581
    BUFFER_ATOMIC_ADD_X2_OFFEN_vi = 3566,
3582
    BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_si  = 3567,
3583
    BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi  = 3568,
3584
    BUFFER_ATOMIC_ADD_X2_OFFSET_si  = 3569,
3585
    BUFFER_ATOMIC_ADD_X2_OFFSET_vi  = 3570,
3586
    BUFFER_ATOMIC_AND_ADDR64_RTN_si = 3571,
3587
    BUFFER_ATOMIC_AND_ADDR64_si = 3572,
3588
    BUFFER_ATOMIC_AND_BOTHEN_RTN_si = 3573,
3589
    BUFFER_ATOMIC_AND_BOTHEN_RTN_vi = 3574,
3590
    BUFFER_ATOMIC_AND_BOTHEN_si = 3575,
3591
    BUFFER_ATOMIC_AND_BOTHEN_vi = 3576,
3592
    BUFFER_ATOMIC_AND_IDXEN_RTN_si  = 3577,
3593
    BUFFER_ATOMIC_AND_IDXEN_RTN_vi  = 3578,
3594
    BUFFER_ATOMIC_AND_IDXEN_si  = 3579,
3595
    BUFFER_ATOMIC_AND_IDXEN_vi  = 3580,
3596
    BUFFER_ATOMIC_AND_OFFEN_RTN_si  = 3581,
3597
    BUFFER_ATOMIC_AND_OFFEN_RTN_vi  = 3582,
3598
    BUFFER_ATOMIC_AND_OFFEN_si  = 3583,
3599
    BUFFER_ATOMIC_AND_OFFEN_vi  = 3584,
3600
    BUFFER_ATOMIC_AND_OFFSET_RTN_si = 3585,
3601
    BUFFER_ATOMIC_AND_OFFSET_RTN_vi = 3586,
3602
    BUFFER_ATOMIC_AND_OFFSET_si = 3587,
3603
    BUFFER_ATOMIC_AND_OFFSET_vi = 3588,
3604
    BUFFER_ATOMIC_AND_X2_ADDR64_RTN_si  = 3589,
3605
    BUFFER_ATOMIC_AND_X2_ADDR64_si  = 3590,
3606
    BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_si  = 3591,
3607
    BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi  = 3592,
3608
    BUFFER_ATOMIC_AND_X2_BOTHEN_si  = 3593,
3609
    BUFFER_ATOMIC_AND_X2_BOTHEN_vi  = 3594,
3610
    BUFFER_ATOMIC_AND_X2_IDXEN_RTN_si = 3595,
3611
    BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi = 3596,
3612
    BUFFER_ATOMIC_AND_X2_IDXEN_si = 3597,
3613
    BUFFER_ATOMIC_AND_X2_IDXEN_vi = 3598,
3614
    BUFFER_ATOMIC_AND_X2_OFFEN_RTN_si = 3599,
3615
    BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi = 3600,
3616
    BUFFER_ATOMIC_AND_X2_OFFEN_si = 3601,
3617
    BUFFER_ATOMIC_AND_X2_OFFEN_vi = 3602,
3618
    BUFFER_ATOMIC_AND_X2_OFFSET_RTN_si  = 3603,
3619
    BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi  = 3604,
3620
    BUFFER_ATOMIC_AND_X2_OFFSET_si  = 3605,
3621
    BUFFER_ATOMIC_AND_X2_OFFSET_vi  = 3606,
3622
    BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_si = 3607,
3623
    BUFFER_ATOMIC_CMPSWAP_ADDR64_si = 3608,
3624
    BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_si = 3609,
3625
    BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi = 3610,
3626
    BUFFER_ATOMIC_CMPSWAP_BOTHEN_si = 3611,
3627
    BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi = 3612,
3628
    BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_si  = 3613,
3629
    BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi  = 3614,
3630
    BUFFER_ATOMIC_CMPSWAP_IDXEN_si  = 3615,
3631
    BUFFER_ATOMIC_CMPSWAP_IDXEN_vi  = 3616,
3632
    BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_si  = 3617,
3633
    BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi  = 3618,
3634
    BUFFER_ATOMIC_CMPSWAP_OFFEN_si  = 3619,
3635
    BUFFER_ATOMIC_CMPSWAP_OFFEN_vi  = 3620,
3636
    BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_si = 3621,
3637
    BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi = 3622,
3638
    BUFFER_ATOMIC_CMPSWAP_OFFSET_si = 3623,
3639
    BUFFER_ATOMIC_CMPSWAP_OFFSET_vi = 3624,
3640
    BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_si  = 3625,
3641
    BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_si  = 3626,
3642
    BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_si  = 3627,
3643
    BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi  = 3628,
3644
    BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_si  = 3629,
3645
    BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_vi  = 3630,
3646
    BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_si = 3631,
3647
    BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi = 3632,
3648
    BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_si = 3633,
3649
    BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_vi = 3634,
3650
    BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_si = 3635,
3651
    BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi = 3636,
3652
    BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_si = 3637,
3653
    BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_vi = 3638,
3654
    BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_si  = 3639,
3655
    BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi  = 3640,
3656
    BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_si  = 3641,
3657
    BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_vi  = 3642,
3658
    BUFFER_ATOMIC_DEC_ADDR64_RTN_si = 3643,
3659
    BUFFER_ATOMIC_DEC_ADDR64_si = 3644,
3660
    BUFFER_ATOMIC_DEC_BOTHEN_RTN_si = 3645,
3661
    BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi = 3646,
3662
    BUFFER_ATOMIC_DEC_BOTHEN_si = 3647,
3663
    BUFFER_ATOMIC_DEC_BOTHEN_vi = 3648,
3664
    BUFFER_ATOMIC_DEC_IDXEN_RTN_si  = 3649,
3665
    BUFFER_ATOMIC_DEC_IDXEN_RTN_vi  = 3650,
3666
    BUFFER_ATOMIC_DEC_IDXEN_si  = 3651,
3667
    BUFFER_ATOMIC_DEC_IDXEN_vi  = 3652,
3668
    BUFFER_ATOMIC_DEC_OFFEN_RTN_si  = 3653,
3669
    BUFFER_ATOMIC_DEC_OFFEN_RTN_vi  = 3654,
3670
    BUFFER_ATOMIC_DEC_OFFEN_si  = 3655,
3671
    BUFFER_ATOMIC_DEC_OFFEN_vi  = 3656,
3672
    BUFFER_ATOMIC_DEC_OFFSET_RTN_si = 3657,
3673
    BUFFER_ATOMIC_DEC_OFFSET_RTN_vi = 3658,
3674
    BUFFER_ATOMIC_DEC_OFFSET_si = 3659,
3675
    BUFFER_ATOMIC_DEC_OFFSET_vi = 3660,
3676
    BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_si  = 3661,
3677
    BUFFER_ATOMIC_DEC_X2_ADDR64_si  = 3662,
3678
    BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_si  = 3663,
3679
    BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi  = 3664,
3680
    BUFFER_ATOMIC_DEC_X2_BOTHEN_si  = 3665,
3681
    BUFFER_ATOMIC_DEC_X2_BOTHEN_vi  = 3666,
3682
    BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_si = 3667,
3683
    BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi = 3668,
3684
    BUFFER_ATOMIC_DEC_X2_IDXEN_si = 3669,
3685
    BUFFER_ATOMIC_DEC_X2_IDXEN_vi = 3670,
3686
    BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_si = 3671,
3687
    BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi = 3672,
3688
    BUFFER_ATOMIC_DEC_X2_OFFEN_si = 3673,
3689
    BUFFER_ATOMIC_DEC_X2_OFFEN_vi = 3674,
3690
    BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_si  = 3675,
3691
    BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi  = 3676,
3692
    BUFFER_ATOMIC_DEC_X2_OFFSET_si  = 3677,
3693
    BUFFER_ATOMIC_DEC_X2_OFFSET_vi  = 3678,
3694
    BUFFER_ATOMIC_INC_ADDR64_RTN_si = 3679,
3695
    BUFFER_ATOMIC_INC_ADDR64_si = 3680,
3696
    BUFFER_ATOMIC_INC_BOTHEN_RTN_si = 3681,
3697
    BUFFER_ATOMIC_INC_BOTHEN_RTN_vi = 3682,
3698
    BUFFER_ATOMIC_INC_BOTHEN_si = 3683,
3699
    BUFFER_ATOMIC_INC_BOTHEN_vi = 3684,
3700
    BUFFER_ATOMIC_INC_IDXEN_RTN_si  = 3685,
3701
    BUFFER_ATOMIC_INC_IDXEN_RTN_vi  = 3686,
3702
    BUFFER_ATOMIC_INC_IDXEN_si  = 3687,
3703
    BUFFER_ATOMIC_INC_IDXEN_vi  = 3688,
3704
    BUFFER_ATOMIC_INC_OFFEN_RTN_si  = 3689,
3705
    BUFFER_ATOMIC_INC_OFFEN_RTN_vi  = 3690,
3706
    BUFFER_ATOMIC_INC_OFFEN_si  = 3691,
3707
    BUFFER_ATOMIC_INC_OFFEN_vi  = 3692,
3708
    BUFFER_ATOMIC_INC_OFFSET_RTN_si = 3693,
3709
    BUFFER_ATOMIC_INC_OFFSET_RTN_vi = 3694,
3710
    BUFFER_ATOMIC_INC_OFFSET_si = 3695,
3711
    BUFFER_ATOMIC_INC_OFFSET_vi = 3696,
3712
    BUFFER_ATOMIC_INC_X2_ADDR64_RTN_si  = 3697,
3713
    BUFFER_ATOMIC_INC_X2_ADDR64_si  = 3698,
3714
    BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_si  = 3699,
3715
    BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi  = 3700,
3716
    BUFFER_ATOMIC_INC_X2_BOTHEN_si  = 3701,
3717
    BUFFER_ATOMIC_INC_X2_BOTHEN_vi  = 3702,
3718
    BUFFER_ATOMIC_INC_X2_IDXEN_RTN_si = 3703,
3719
    BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi = 3704,
3720
    BUFFER_ATOMIC_INC_X2_IDXEN_si = 3705,
3721
    BUFFER_ATOMIC_INC_X2_IDXEN_vi = 3706,
3722
    BUFFER_ATOMIC_INC_X2_OFFEN_RTN_si = 3707,
3723
    BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi = 3708,
3724
    BUFFER_ATOMIC_INC_X2_OFFEN_si = 3709,
3725
    BUFFER_ATOMIC_INC_X2_OFFEN_vi = 3710,
3726
    BUFFER_ATOMIC_INC_X2_OFFSET_RTN_si  = 3711,
3727
    BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi  = 3712,
3728
    BUFFER_ATOMIC_INC_X2_OFFSET_si  = 3713,
3729
    BUFFER_ATOMIC_INC_X2_OFFSET_vi  = 3714,
3730
    BUFFER_ATOMIC_OR_ADDR64_RTN_si  = 3715,
3731
    BUFFER_ATOMIC_OR_ADDR64_si  = 3716,
3732
    BUFFER_ATOMIC_OR_BOTHEN_RTN_si  = 3717,
3733
    BUFFER_ATOMIC_OR_BOTHEN_RTN_vi  = 3718,
3734
    BUFFER_ATOMIC_OR_BOTHEN_si  = 3719,
3735
    BUFFER_ATOMIC_OR_BOTHEN_vi  = 3720,
3736
    BUFFER_ATOMIC_OR_IDXEN_RTN_si = 3721,
3737
    BUFFER_ATOMIC_OR_IDXEN_RTN_vi = 3722,
3738
    BUFFER_ATOMIC_OR_IDXEN_si = 3723,
3739
    BUFFER_ATOMIC_OR_IDXEN_vi = 3724,
3740
    BUFFER_ATOMIC_OR_OFFEN_RTN_si = 3725,
3741
    BUFFER_ATOMIC_OR_OFFEN_RTN_vi = 3726,
3742
    BUFFER_ATOMIC_OR_OFFEN_si = 3727,
3743
    BUFFER_ATOMIC_OR_OFFEN_vi = 3728,
3744
    BUFFER_ATOMIC_OR_OFFSET_RTN_si  = 3729,
3745
    BUFFER_ATOMIC_OR_OFFSET_RTN_vi  = 3730,
3746
    BUFFER_ATOMIC_OR_OFFSET_si  = 3731,
3747
    BUFFER_ATOMIC_OR_OFFSET_vi  = 3732,
3748
    BUFFER_ATOMIC_OR_X2_ADDR64_RTN_si = 3733,
3749
    BUFFER_ATOMIC_OR_X2_ADDR64_si = 3734,
3750
    BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_si = 3735,
3751
    BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi = 3736,
3752
    BUFFER_ATOMIC_OR_X2_BOTHEN_si = 3737,
3753
    BUFFER_ATOMIC_OR_X2_BOTHEN_vi = 3738,
3754
    BUFFER_ATOMIC_OR_X2_IDXEN_RTN_si  = 3739,
3755
    BUFFER_ATOMIC_OR_X2_IDXEN_RTN_vi  = 3740,
3756
    BUFFER_ATOMIC_OR_X2_IDXEN_si  = 3741,
3757
    BUFFER_ATOMIC_OR_X2_IDXEN_vi  = 3742,
3758
    BUFFER_ATOMIC_OR_X2_OFFEN_RTN_si  = 3743,
3759
    BUFFER_ATOMIC_OR_X2_OFFEN_RTN_vi  = 3744,
3760
    BUFFER_ATOMIC_OR_X2_OFFEN_si  = 3745,
3761
    BUFFER_ATOMIC_OR_X2_OFFEN_vi  = 3746,
3762
    BUFFER_ATOMIC_OR_X2_OFFSET_RTN_si = 3747,
3763
    BUFFER_ATOMIC_OR_X2_OFFSET_RTN_vi = 3748,
3764
    BUFFER_ATOMIC_OR_X2_OFFSET_si = 3749,
3765
    BUFFER_ATOMIC_OR_X2_OFFSET_vi = 3750,
3766
    BUFFER_ATOMIC_SMAX_ADDR64_RTN_si  = 3751,
3767
    BUFFER_ATOMIC_SMAX_ADDR64_si  = 3752,
3768
    BUFFER_ATOMIC_SMAX_BOTHEN_RTN_si  = 3753,
3769
    BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi  = 3754,
3770
    BUFFER_ATOMIC_SMAX_BOTHEN_si  = 3755,
3771
    BUFFER_ATOMIC_SMAX_BOTHEN_vi  = 3756,
3772
    BUFFER_ATOMIC_SMAX_IDXEN_RTN_si = 3757,
3773
    BUFFER_ATOMIC_SMAX_IDXEN_RTN_vi = 3758,
3774
    BUFFER_ATOMIC_SMAX_IDXEN_si = 3759,
3775
    BUFFER_ATOMIC_SMAX_IDXEN_vi = 3760,
3776
    BUFFER_ATOMIC_SMAX_OFFEN_RTN_si = 3761,
3777
    BUFFER_ATOMIC_SMAX_OFFEN_RTN_vi = 3762,
3778
    BUFFER_ATOMIC_SMAX_OFFEN_si = 3763,
3779
    BUFFER_ATOMIC_SMAX_OFFEN_vi = 3764,
3780
    BUFFER_ATOMIC_SMAX_OFFSET_RTN_si  = 3765,
3781
    BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi  = 3766,
3782
    BUFFER_ATOMIC_SMAX_OFFSET_si  = 3767,
3783
    BUFFER_ATOMIC_SMAX_OFFSET_vi  = 3768,
3784
    BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_si = 3769,
3785
    BUFFER_ATOMIC_SMAX_X2_ADDR64_si = 3770,
3786
    BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_si = 3771,
3787
    BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi = 3772,
3788
    BUFFER_ATOMIC_SMAX_X2_BOTHEN_si = 3773,
3789
    BUFFER_ATOMIC_SMAX_X2_BOTHEN_vi = 3774,
3790
    BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_si  = 3775,
3791
    BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_vi  = 3776,
3792
    BUFFER_ATOMIC_SMAX_X2_IDXEN_si  = 3777,
3793
    BUFFER_ATOMIC_SMAX_X2_IDXEN_vi  = 3778,
3794
    BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_si  = 3779,
3795
    BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_vi  = 3780,
3796
    BUFFER_ATOMIC_SMAX_X2_OFFEN_si  = 3781,
3797
    BUFFER_ATOMIC_SMAX_X2_OFFEN_vi  = 3782,
3798
    BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_si = 3783,
3799
    BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_vi = 3784,
3800
    BUFFER_ATOMIC_SMAX_X2_OFFSET_si = 3785,
3801
    BUFFER_ATOMIC_SMAX_X2_OFFSET_vi = 3786,
3802
    BUFFER_ATOMIC_SMIN_ADDR64_RTN_si  = 3787,
3803
    BUFFER_ATOMIC_SMIN_ADDR64_si  = 3788,
3804
    BUFFER_ATOMIC_SMIN_BOTHEN_RTN_si  = 3789,
3805
    BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi  = 3790,
3806
    BUFFER_ATOMIC_SMIN_BOTHEN_si  = 3791,
3807
    BUFFER_ATOMIC_SMIN_BOTHEN_vi  = 3792,
3808
    BUFFER_ATOMIC_SMIN_IDXEN_RTN_si = 3793,
3809
    BUFFER_ATOMIC_SMIN_IDXEN_RTN_vi = 3794,
3810
    BUFFER_ATOMIC_SMIN_IDXEN_si = 3795,
3811
    BUFFER_ATOMIC_SMIN_IDXEN_vi = 3796,
3812
    BUFFER_ATOMIC_SMIN_OFFEN_RTN_si = 3797,
3813
    BUFFER_ATOMIC_SMIN_OFFEN_RTN_vi = 3798,
3814
    BUFFER_ATOMIC_SMIN_OFFEN_si = 3799,
3815
    BUFFER_ATOMIC_SMIN_OFFEN_vi = 3800,
3816
    BUFFER_ATOMIC_SMIN_OFFSET_RTN_si  = 3801,
3817
    BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi  = 3802,
3818
    BUFFER_ATOMIC_SMIN_OFFSET_si  = 3803,
3819
    BUFFER_ATOMIC_SMIN_OFFSET_vi  = 3804,
3820
    BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_si = 3805,
3821
    BUFFER_ATOMIC_SMIN_X2_ADDR64_si = 3806,
3822
    BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_si = 3807,
3823
    BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi = 3808,
3824
    BUFFER_ATOMIC_SMIN_X2_BOTHEN_si = 3809,
3825
    BUFFER_ATOMIC_SMIN_X2_BOTHEN_vi = 3810,
3826
    BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_si  = 3811,
3827
    BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_vi  = 3812,
3828
    BUFFER_ATOMIC_SMIN_X2_IDXEN_si  = 3813,
3829
    BUFFER_ATOMIC_SMIN_X2_IDXEN_vi  = 3814,
3830
    BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_si  = 3815,
3831
    BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_vi  = 3816,
3832
    BUFFER_ATOMIC_SMIN_X2_OFFEN_si  = 3817,
3833
    BUFFER_ATOMIC_SMIN_X2_OFFEN_vi  = 3818,
3834
    BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_si = 3819,
3835
    BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_vi = 3820,
3836
    BUFFER_ATOMIC_SMIN_X2_OFFSET_si = 3821,
3837
    BUFFER_ATOMIC_SMIN_X2_OFFSET_vi = 3822,
3838
    BUFFER_ATOMIC_SUB_ADDR64_RTN_si = 3823,
3839
    BUFFER_ATOMIC_SUB_ADDR64_si = 3824,
3840
    BUFFER_ATOMIC_SUB_BOTHEN_RTN_si = 3825,
3841
    BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi = 3826,
3842
    BUFFER_ATOMIC_SUB_BOTHEN_si = 3827,
3843
    BUFFER_ATOMIC_SUB_BOTHEN_vi = 3828,
3844
    BUFFER_ATOMIC_SUB_IDXEN_RTN_si  = 3829,
3845
    BUFFER_ATOMIC_SUB_IDXEN_RTN_vi  = 3830,
3846
    BUFFER_ATOMIC_SUB_IDXEN_si  = 3831,
3847
    BUFFER_ATOMIC_SUB_IDXEN_vi  = 3832,
3848
    BUFFER_ATOMIC_SUB_OFFEN_RTN_si  = 3833,
3849
    BUFFER_ATOMIC_SUB_OFFEN_RTN_vi  = 3834,
3850
    BUFFER_ATOMIC_SUB_OFFEN_si  = 3835,
3851
    BUFFER_ATOMIC_SUB_OFFEN_vi  = 3836,
3852
    BUFFER_ATOMIC_SUB_OFFSET_RTN_si = 3837,
3853
    BUFFER_ATOMIC_SUB_OFFSET_RTN_vi = 3838,
3854
    BUFFER_ATOMIC_SUB_OFFSET_si = 3839,
3855
    BUFFER_ATOMIC_SUB_OFFSET_vi = 3840,
3856
    BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_si  = 3841,
3857
    BUFFER_ATOMIC_SUB_X2_ADDR64_si  = 3842,
3858
    BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_si  = 3843,
3859
    BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi  = 3844,
3860
    BUFFER_ATOMIC_SUB_X2_BOTHEN_si  = 3845,
3861
    BUFFER_ATOMIC_SUB_X2_BOTHEN_vi  = 3846,
3862
    BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_si = 3847,
3863
    BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_vi = 3848,
3864
    BUFFER_ATOMIC_SUB_X2_IDXEN_si = 3849,
3865
    BUFFER_ATOMIC_SUB_X2_IDXEN_vi = 3850,
3866
    BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_si = 3851,
3867
    BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_vi = 3852,
3868
    BUFFER_ATOMIC_SUB_X2_OFFEN_si = 3853,
3869
    BUFFER_ATOMIC_SUB_X2_OFFEN_vi = 3854,
3870
    BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_si  = 3855,
3871
    BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_vi  = 3856,
3872
    BUFFER_ATOMIC_SUB_X2_OFFSET_si  = 3857,
3873
    BUFFER_ATOMIC_SUB_X2_OFFSET_vi  = 3858,
3874
    BUFFER_ATOMIC_SWAP_ADDR64_RTN_si  = 3859,
3875
    BUFFER_ATOMIC_SWAP_ADDR64_si  = 3860,
3876
    BUFFER_ATOMIC_SWAP_BOTHEN_RTN_si  = 3861,
3877
    BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi  = 3862,
3878
    BUFFER_ATOMIC_SWAP_BOTHEN_si  = 3863,
3879
    BUFFER_ATOMIC_SWAP_BOTHEN_vi  = 3864,
3880
    BUFFER_ATOMIC_SWAP_IDXEN_RTN_si = 3865,
3881
    BUFFER_ATOMIC_SWAP_IDXEN_RTN_vi = 3866,
3882
    BUFFER_ATOMIC_SWAP_IDXEN_si = 3867,
3883
    BUFFER_ATOMIC_SWAP_IDXEN_vi = 3868,
3884
    BUFFER_ATOMIC_SWAP_OFFEN_RTN_si = 3869,
3885
    BUFFER_ATOMIC_SWAP_OFFEN_RTN_vi = 3870,
3886
    BUFFER_ATOMIC_SWAP_OFFEN_si = 3871,
3887
    BUFFER_ATOMIC_SWAP_OFFEN_vi = 3872,
3888
    BUFFER_ATOMIC_SWAP_OFFSET_RTN_si  = 3873,
3889
    BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi  = 3874,
3890
    BUFFER_ATOMIC_SWAP_OFFSET_si  = 3875,
3891
    BUFFER_ATOMIC_SWAP_OFFSET_vi  = 3876,
3892
    BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_si = 3877,
3893
    BUFFER_ATOMIC_SWAP_X2_ADDR64_si = 3878,
3894
    BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_si = 3879,
3895
    BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi = 3880,
3896
    BUFFER_ATOMIC_SWAP_X2_BOTHEN_si = 3881,
3897
    BUFFER_ATOMIC_SWAP_X2_BOTHEN_vi = 3882,
3898
    BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_si  = 3883,
3899
    BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_vi  = 3884,
3900
    BUFFER_ATOMIC_SWAP_X2_IDXEN_si  = 3885,
3901
    BUFFER_ATOMIC_SWAP_X2_IDXEN_vi  = 3886,
3902
    BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_si  = 3887,
3903
    BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_vi  = 3888,
3904
    BUFFER_ATOMIC_SWAP_X2_OFFEN_si  = 3889,
3905
    BUFFER_ATOMIC_SWAP_X2_OFFEN_vi  = 3890,
3906
    BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_si = 3891,
3907
    BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_vi = 3892,
3908
    BUFFER_ATOMIC_SWAP_X2_OFFSET_si = 3893,
3909
    BUFFER_ATOMIC_SWAP_X2_OFFSET_vi = 3894,
3910
    BUFFER_ATOMIC_UMAX_ADDR64_RTN_si  = 3895,
3911
    BUFFER_ATOMIC_UMAX_ADDR64_si  = 3896,
3912
    BUFFER_ATOMIC_UMAX_BOTHEN_RTN_si  = 3897,
3913
    BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi  = 3898,
3914
    BUFFER_ATOMIC_UMAX_BOTHEN_si  = 3899,
3915
    BUFFER_ATOMIC_UMAX_BOTHEN_vi  = 3900,
3916
    BUFFER_ATOMIC_UMAX_IDXEN_RTN_si = 3901,
3917
    BUFFER_ATOMIC_UMAX_IDXEN_RTN_vi = 3902,
3918
    BUFFER_ATOMIC_UMAX_IDXEN_si = 3903,
3919
    BUFFER_ATOMIC_UMAX_IDXEN_vi = 3904,
3920
    BUFFER_ATOMIC_UMAX_OFFEN_RTN_si = 3905,
3921
    BUFFER_ATOMIC_UMAX_OFFEN_RTN_vi = 3906,
3922
    BUFFER_ATOMIC_UMAX_OFFEN_si = 3907,
3923
    BUFFER_ATOMIC_UMAX_OFFEN_vi = 3908,
3924
    BUFFER_ATOMIC_UMAX_OFFSET_RTN_si  = 3909,
3925
    BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi  = 3910,
3926
    BUFFER_ATOMIC_UMAX_OFFSET_si  = 3911,
3927
    BUFFER_ATOMIC_UMAX_OFFSET_vi  = 3912,
3928
    BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_si = 3913,
3929
    BUFFER_ATOMIC_UMAX_X2_ADDR64_si = 3914,
3930
    BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_si = 3915,
3931
    BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi = 3916,
3932
    BUFFER_ATOMIC_UMAX_X2_BOTHEN_si = 3917,
3933
    BUFFER_ATOMIC_UMAX_X2_BOTHEN_vi = 3918,
3934
    BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_si  = 3919,
3935
    BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_vi  = 3920,
3936
    BUFFER_ATOMIC_UMAX_X2_IDXEN_si  = 3921,
3937
    BUFFER_ATOMIC_UMAX_X2_IDXEN_vi  = 3922,
3938
    BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_si  = 3923,
3939
    BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_vi  = 3924,
3940
    BUFFER_ATOMIC_UMAX_X2_OFFEN_si  = 3925,
3941
    BUFFER_ATOMIC_UMAX_X2_OFFEN_vi  = 3926,
3942
    BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_si = 3927,
3943
    BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_vi = 3928,
3944
    BUFFER_ATOMIC_UMAX_X2_OFFSET_si = 3929,
3945
    BUFFER_ATOMIC_UMAX_X2_OFFSET_vi = 3930,
3946
    BUFFER_ATOMIC_UMIN_ADDR64_RTN_si  = 3931,
3947
    BUFFER_ATOMIC_UMIN_ADDR64_si  = 3932,
3948
    BUFFER_ATOMIC_UMIN_BOTHEN_RTN_si  = 3933,
3949
    BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi  = 3934,
3950
    BUFFER_ATOMIC_UMIN_BOTHEN_si  = 3935,
3951
    BUFFER_ATOMIC_UMIN_BOTHEN_vi  = 3936,
3952
    BUFFER_ATOMIC_UMIN_IDXEN_RTN_si = 3937,
3953
    BUFFER_ATOMIC_UMIN_IDXEN_RTN_vi = 3938,
3954
    BUFFER_ATOMIC_UMIN_IDXEN_si = 3939,
3955
    BUFFER_ATOMIC_UMIN_IDXEN_vi = 3940,
3956
    BUFFER_ATOMIC_UMIN_OFFEN_RTN_si = 3941,
3957
    BUFFER_ATOMIC_UMIN_OFFEN_RTN_vi = 3942,
3958
    BUFFER_ATOMIC_UMIN_OFFEN_si = 3943,
3959
    BUFFER_ATOMIC_UMIN_OFFEN_vi = 3944,
3960
    BUFFER_ATOMIC_UMIN_OFFSET_RTN_si  = 3945,
3961
    BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi  = 3946,
3962
    BUFFER_ATOMIC_UMIN_OFFSET_si  = 3947,
3963
    BUFFER_ATOMIC_UMIN_OFFSET_vi  = 3948,
3964
    BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_si = 3949,
3965
    BUFFER_ATOMIC_UMIN_X2_ADDR64_si = 3950,
3966
    BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_si = 3951,
3967
    BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi = 3952,
3968
    BUFFER_ATOMIC_UMIN_X2_BOTHEN_si = 3953,
3969
    BUFFER_ATOMIC_UMIN_X2_BOTHEN_vi = 3954,
3970
    BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_si  = 3955,
3971
    BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_vi  = 3956,
3972
    BUFFER_ATOMIC_UMIN_X2_IDXEN_si  = 3957,
3973
    BUFFER_ATOMIC_UMIN_X2_IDXEN_vi  = 3958,
3974
    BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_si  = 3959,
3975
    BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_vi  = 3960,
3976
    BUFFER_ATOMIC_UMIN_X2_OFFEN_si  = 3961,
3977
    BUFFER_ATOMIC_UMIN_X2_OFFEN_vi  = 3962,
3978
    BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_si = 3963,
3979
    BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_vi = 3964,
3980
    BUFFER_ATOMIC_UMIN_X2_OFFSET_si = 3965,
3981
    BUFFER_ATOMIC_UMIN_X2_OFFSET_vi = 3966,
3982
    BUFFER_ATOMIC_XOR_ADDR64_RTN_si = 3967,
3983
    BUFFER_ATOMIC_XOR_ADDR64_si = 3968,
3984
    BUFFER_ATOMIC_XOR_BOTHEN_RTN_si = 3969,
3985
    BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi = 3970,
3986
    BUFFER_ATOMIC_XOR_BOTHEN_si = 3971,
3987
    BUFFER_ATOMIC_XOR_BOTHEN_vi = 3972,
3988
    BUFFER_ATOMIC_XOR_IDXEN_RTN_si  = 3973,
3989
    BUFFER_ATOMIC_XOR_IDXEN_RTN_vi  = 3974,
3990
    BUFFER_ATOMIC_XOR_IDXEN_si  = 3975,
3991
    BUFFER_ATOMIC_XOR_IDXEN_vi  = 3976,
3992
    BUFFER_ATOMIC_XOR_OFFEN_RTN_si  = 3977,
3993
    BUFFER_ATOMIC_XOR_OFFEN_RTN_vi  = 3978,
3994
    BUFFER_ATOMIC_XOR_OFFEN_si  = 3979,
3995
    BUFFER_ATOMIC_XOR_OFFEN_vi  = 3980,
3996
    BUFFER_ATOMIC_XOR_OFFSET_RTN_si = 3981,
3997
    BUFFER_ATOMIC_XOR_OFFSET_RTN_vi = 3982,
3998
    BUFFER_ATOMIC_XOR_OFFSET_si = 3983,
3999
    BUFFER_ATOMIC_XOR_OFFSET_vi = 3984,
4000
    BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_si  = 3985,
4001
    BUFFER_ATOMIC_XOR_X2_ADDR64_si  = 3986,
4002
    BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_si  = 3987,
4003
    BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi  = 3988,
4004
    BUFFER_ATOMIC_XOR_X2_BOTHEN_si  = 3989,
4005
    BUFFER_ATOMIC_XOR_X2_BOTHEN_vi  = 3990,
4006
    BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_si = 3991,
4007
    BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_vi = 3992,
4008
    BUFFER_ATOMIC_XOR_X2_IDXEN_si = 3993,
4009
    BUFFER_ATOMIC_XOR_X2_IDXEN_vi = 3994,
4010
    BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_si = 3995,
4011
    BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_vi = 3996,
4012
    BUFFER_ATOMIC_XOR_X2_OFFEN_si = 3997,
4013
    BUFFER_ATOMIC_XOR_X2_OFFEN_vi = 3998,
4014
    BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_si  = 3999,
4015
    BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_vi  = 4000,
4016
    BUFFER_ATOMIC_XOR_X2_OFFSET_si  = 4001,
4017
    BUFFER_ATOMIC_XOR_X2_OFFSET_vi  = 4002,
4018
    BUFFER_LOAD_DWORDX2_ADDR64_si = 4003,
4019
    BUFFER_LOAD_DWORDX2_BOTHEN_si = 4004,
4020
    BUFFER_LOAD_DWORDX2_BOTHEN_vi = 4005,
4021
    BUFFER_LOAD_DWORDX2_IDXEN_si  = 4006,
4022
    BUFFER_LOAD_DWORDX2_IDXEN_vi  = 4007,
4023
    BUFFER_LOAD_DWORDX2_LDS_BOTHEN_vi = 4008,
4024
    BUFFER_LOAD_DWORDX2_LDS_IDXEN_vi  = 4009,
4025
    BUFFER_LOAD_DWORDX2_LDS_OFFEN_vi  = 4010,
4026
    BUFFER_LOAD_DWORDX2_LDS_OFFSET_vi = 4011,
4027
    BUFFER_LOAD_DWORDX2_OFFEN_si  = 4012,
4028
    BUFFER_LOAD_DWORDX2_OFFEN_vi  = 4013,
4029
    BUFFER_LOAD_DWORDX2_OFFSET_si = 4014,
4030
    BUFFER_LOAD_DWORDX2_OFFSET_vi = 4015,
4031
    BUFFER_LOAD_DWORDX3_ADDR64_si = 4016,
4032
    BUFFER_LOAD_DWORDX3_BOTHEN_si = 4017,
4033
    BUFFER_LOAD_DWORDX3_BOTHEN_vi = 4018,
4034
    BUFFER_LOAD_DWORDX3_IDXEN_si  = 4019,
4035
    BUFFER_LOAD_DWORDX3_IDXEN_vi  = 4020,
4036
    BUFFER_LOAD_DWORDX3_LDS_BOTHEN_vi = 4021,
4037
    BUFFER_LOAD_DWORDX3_LDS_IDXEN_vi  = 4022,
4038
    BUFFER_LOAD_DWORDX3_LDS_OFFEN_vi  = 4023,
4039
    BUFFER_LOAD_DWORDX3_LDS_OFFSET_vi = 4024,
4040
    BUFFER_LOAD_DWORDX3_OFFEN_si  = 4025,
4041
    BUFFER_LOAD_DWORDX3_OFFEN_vi  = 4026,
4042
    BUFFER_LOAD_DWORDX3_OFFSET_si = 4027,
4043
    BUFFER_LOAD_DWORDX3_OFFSET_vi = 4028,
4044
    BUFFER_LOAD_DWORDX4_ADDR64_si = 4029,
4045
    BUFFER_LOAD_DWORDX4_BOTHEN_si = 4030,
4046
    BUFFER_LOAD_DWORDX4_BOTHEN_vi = 4031,
4047
    BUFFER_LOAD_DWORDX4_IDXEN_si  = 4032,
4048
    BUFFER_LOAD_DWORDX4_IDXEN_vi  = 4033,
4049
    BUFFER_LOAD_DWORDX4_LDS_BOTHEN_vi = 4034,
4050
    BUFFER_LOAD_DWORDX4_LDS_IDXEN_vi  = 4035,
4051
    BUFFER_LOAD_DWORDX4_LDS_OFFEN_vi  = 4036,
4052
    BUFFER_LOAD_DWORDX4_LDS_OFFSET_vi = 4037,
4053
    BUFFER_LOAD_DWORDX4_OFFEN_si  = 4038,
4054
    BUFFER_LOAD_DWORDX4_OFFEN_vi  = 4039,
4055
    BUFFER_LOAD_DWORDX4_OFFSET_si = 4040,
4056
    BUFFER_LOAD_DWORDX4_OFFSET_vi = 4041,
4057
    BUFFER_LOAD_DWORD_ADDR64_si = 4042,
4058
    BUFFER_LOAD_DWORD_BOTHEN_si = 4043,
4059
    BUFFER_LOAD_DWORD_BOTHEN_vi = 4044,
4060
    BUFFER_LOAD_DWORD_IDXEN_si  = 4045,
4061
    BUFFER_LOAD_DWORD_IDXEN_vi  = 4046,
4062
    BUFFER_LOAD_DWORD_LDS_ADDR64_si = 4047,
4063
    BUFFER_LOAD_DWORD_LDS_BOTHEN_si = 4048,
4064
    BUFFER_LOAD_DWORD_LDS_BOTHEN_vi = 4049,
4065
    BUFFER_LOAD_DWORD_LDS_IDXEN_si  = 4050,
4066
    BUFFER_LOAD_DWORD_LDS_IDXEN_vi  = 4051,
4067
    BUFFER_LOAD_DWORD_LDS_OFFEN_si  = 4052,
4068
    BUFFER_LOAD_DWORD_LDS_OFFEN_vi  = 4053,
4069
    BUFFER_LOAD_DWORD_LDS_OFFSET_si = 4054,
4070
    BUFFER_LOAD_DWORD_LDS_OFFSET_vi = 4055,
4071
    BUFFER_LOAD_DWORD_OFFEN_si  = 4056,
4072
    BUFFER_LOAD_DWORD_OFFEN_vi  = 4057,
4073
    BUFFER_LOAD_DWORD_OFFSET_si = 4058,
4074
    BUFFER_LOAD_DWORD_OFFSET_vi = 4059,
4075
    BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_vi = 4060,
4076
    BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_vi  = 4061,
4077
    BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_vi  = 4062,
4078
    BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_vi = 4063,
4079
    BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi = 4064,
4080
    BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi  = 4065,
4081
    BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi  = 4066,
4082
    BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi = 4067,
4083
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80  = 4068,
4084
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80 = 4069,
4085
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80 = 4070,
4086
    BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80  = 4071,
4087
    BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi  = 4072,
4088
    BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi = 4073,
4089
    BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi = 4074,
4090
    BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi  = 4075,
4091
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80 = 4076,
4092
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80  = 4077,
4093
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80  = 4078,
4094
    BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80 = 4079,
4095
    BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi = 4080,
4096
    BUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi  = 4081,
4097
    BUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi  = 4082,
4098
    BUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi = 4083,
4099
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80  = 4084,
4100
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80 = 4085,
4101
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80 = 4086,
4102
    BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80  = 4087,
4103
    BUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi  = 4088,
4104
    BUFFER_LOAD_FORMAT_D16_X_IDXEN_vi = 4089,
4105
    BUFFER_LOAD_FORMAT_D16_X_OFFEN_vi = 4090,
4106
    BUFFER_LOAD_FORMAT_D16_X_OFFSET_vi  = 4091,
4107
    BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80 = 4092,
4108
    BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80  = 4093,
4109
    BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80  = 4094,
4110
    BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80 = 4095,
4111
    BUFFER_LOAD_FORMAT_XYZW_ADDR64_si = 4096,
4112
    BUFFER_LOAD_FORMAT_XYZW_BOTHEN_si = 4097,
4113
    BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi = 4098,
4114
    BUFFER_LOAD_FORMAT_XYZW_IDXEN_si  = 4099,
4115
    BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi  = 4100,
4116
    BUFFER_LOAD_FORMAT_XYZW_OFFEN_si  = 4101,
4117
    BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi  = 4102,
4118
    BUFFER_LOAD_FORMAT_XYZW_OFFSET_si = 4103,
4119
    BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi = 4104,
4120
    BUFFER_LOAD_FORMAT_XYZ_ADDR64_si  = 4105,
4121
    BUFFER_LOAD_FORMAT_XYZ_BOTHEN_si  = 4106,
4122
    BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi  = 4107,
4123
    BUFFER_LOAD_FORMAT_XYZ_IDXEN_si = 4108,
4124
    BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi = 4109,
4125
    BUFFER_LOAD_FORMAT_XYZ_OFFEN_si = 4110,
4126
    BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi = 4111,
4127
    BUFFER_LOAD_FORMAT_XYZ_OFFSET_si  = 4112,
4128
    BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi  = 4113,
4129
    BUFFER_LOAD_FORMAT_XY_ADDR64_si = 4114,
4130
    BUFFER_LOAD_FORMAT_XY_BOTHEN_si = 4115,
4131
    BUFFER_LOAD_FORMAT_XY_BOTHEN_vi = 4116,
4132
    BUFFER_LOAD_FORMAT_XY_IDXEN_si  = 4117,
4133
    BUFFER_LOAD_FORMAT_XY_IDXEN_vi  = 4118,
4134
    BUFFER_LOAD_FORMAT_XY_OFFEN_si  = 4119,
4135
    BUFFER_LOAD_FORMAT_XY_OFFEN_vi  = 4120,
4136
    BUFFER_LOAD_FORMAT_XY_OFFSET_si = 4121,
4137
    BUFFER_LOAD_FORMAT_XY_OFFSET_vi = 4122,
4138
    BUFFER_LOAD_FORMAT_X_ADDR64_si  = 4123,
4139
    BUFFER_LOAD_FORMAT_X_BOTHEN_si  = 4124,
4140
    BUFFER_LOAD_FORMAT_X_BOTHEN_vi  = 4125,
4141
    BUFFER_LOAD_FORMAT_X_IDXEN_si = 4126,
4142
    BUFFER_LOAD_FORMAT_X_IDXEN_vi = 4127,
4143
    BUFFER_LOAD_FORMAT_X_LDS_ADDR64_si  = 4128,
4144
    BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_si  = 4129,
4145
    BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_vi  = 4130,
4146
    BUFFER_LOAD_FORMAT_X_LDS_IDXEN_si = 4131,
4147
    BUFFER_LOAD_FORMAT_X_LDS_IDXEN_vi = 4132,
4148
    BUFFER_LOAD_FORMAT_X_LDS_OFFEN_si = 4133,
4149
    BUFFER_LOAD_FORMAT_X_LDS_OFFEN_vi = 4134,
4150
    BUFFER_LOAD_FORMAT_X_LDS_OFFSET_si  = 4135,
4151
    BUFFER_LOAD_FORMAT_X_LDS_OFFSET_vi  = 4136,
4152
    BUFFER_LOAD_FORMAT_X_OFFEN_si = 4137,
4153
    BUFFER_LOAD_FORMAT_X_OFFEN_vi = 4138,
4154
    BUFFER_LOAD_FORMAT_X_OFFSET_si  = 4139,
4155
    BUFFER_LOAD_FORMAT_X_OFFSET_vi  = 4140,
4156
    BUFFER_LOAD_SBYTE_ADDR64_si = 4141,
4157
    BUFFER_LOAD_SBYTE_BOTHEN_si = 4142,
4158
    BUFFER_LOAD_SBYTE_BOTHEN_vi = 4143,
4159
    BUFFER_LOAD_SBYTE_D16_BOTHEN_vi = 4144,
4160
    BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi  = 4145,
4161
    BUFFER_LOAD_SBYTE_D16_HI_IDXEN_vi = 4146,
4162
    BUFFER_LOAD_SBYTE_D16_HI_OFFEN_vi = 4147,
4163
    BUFFER_LOAD_SBYTE_D16_HI_OFFSET_vi  = 4148,
4164
    BUFFER_LOAD_SBYTE_D16_IDXEN_vi  = 4149,
4165
    BUFFER_LOAD_SBYTE_D16_OFFEN_vi  = 4150,
4166
    BUFFER_LOAD_SBYTE_D16_OFFSET_vi = 4151,
4167
    BUFFER_LOAD_SBYTE_IDXEN_si  = 4152,
4168
    BUFFER_LOAD_SBYTE_IDXEN_vi  = 4153,
4169
    BUFFER_LOAD_SBYTE_LDS_ADDR64_si = 4154,
4170
    BUFFER_LOAD_SBYTE_LDS_BOTHEN_si = 4155,
4171
    BUFFER_LOAD_SBYTE_LDS_BOTHEN_vi = 4156,
4172
    BUFFER_LOAD_SBYTE_LDS_IDXEN_si  = 4157,
4173
    BUFFER_LOAD_SBYTE_LDS_IDXEN_vi  = 4158,
4174
    BUFFER_LOAD_SBYTE_LDS_OFFEN_si  = 4159,
4175
    BUFFER_LOAD_SBYTE_LDS_OFFEN_vi  = 4160,
4176
    BUFFER_LOAD_SBYTE_LDS_OFFSET_si = 4161,
4177
    BUFFER_LOAD_SBYTE_LDS_OFFSET_vi = 4162,
4178
    BUFFER_LOAD_SBYTE_OFFEN_si  = 4163,
4179
    BUFFER_LOAD_SBYTE_OFFEN_vi  = 4164,
4180
    BUFFER_LOAD_SBYTE_OFFSET_si = 4165,
4181
    BUFFER_LOAD_SBYTE_OFFSET_vi = 4166,
4182
    BUFFER_LOAD_SHORT_D16_BOTHEN_vi = 4167,
4183
    BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi  = 4168,
4184
    BUFFER_LOAD_SHORT_D16_HI_IDXEN_vi = 4169,
4185
    BUFFER_LOAD_SHORT_D16_HI_OFFEN_vi = 4170,
4186
    BUFFER_LOAD_SHORT_D16_HI_OFFSET_vi  = 4171,
4187
    BUFFER_LOAD_SHORT_D16_IDXEN_vi  = 4172,
4188
    BUFFER_LOAD_SHORT_D16_OFFEN_vi  = 4173,
4189
    BUFFER_LOAD_SHORT_D16_OFFSET_vi = 4174,
4190
    BUFFER_LOAD_SSHORT_ADDR64_si  = 4175,
4191
    BUFFER_LOAD_SSHORT_BOTHEN_si  = 4176,
4192
    BUFFER_LOAD_SSHORT_BOTHEN_vi  = 4177,
4193
    BUFFER_LOAD_SSHORT_IDXEN_si = 4178,
4194
    BUFFER_LOAD_SSHORT_IDXEN_vi = 4179,
4195
    BUFFER_LOAD_SSHORT_LDS_ADDR64_si  = 4180,
4196
    BUFFER_LOAD_SSHORT_LDS_BOTHEN_si  = 4181,
4197
    BUFFER_LOAD_SSHORT_LDS_BOTHEN_vi  = 4182,
4198
    BUFFER_LOAD_SSHORT_LDS_IDXEN_si = 4183,
4199
    BUFFER_LOAD_SSHORT_LDS_IDXEN_vi = 4184,
4200
    BUFFER_LOAD_SSHORT_LDS_OFFEN_si = 4185,
4201
    BUFFER_LOAD_SSHORT_LDS_OFFEN_vi = 4186,
4202
    BUFFER_LOAD_SSHORT_LDS_OFFSET_si  = 4187,
4203
    BUFFER_LOAD_SSHORT_LDS_OFFSET_vi  = 4188,
4204
    BUFFER_LOAD_SSHORT_OFFEN_si = 4189,
4205
    BUFFER_LOAD_SSHORT_OFFEN_vi = 4190,
4206
    BUFFER_LOAD_SSHORT_OFFSET_si  = 4191,
4207
    BUFFER_LOAD_SSHORT_OFFSET_vi  = 4192,
4208
    BUFFER_LOAD_UBYTE_ADDR64_si = 4193,
4209
    BUFFER_LOAD_UBYTE_BOTHEN_si = 4194,
4210
    BUFFER_LOAD_UBYTE_BOTHEN_vi = 4195,
4211
    BUFFER_LOAD_UBYTE_D16_BOTHEN_vi = 4196,
4212
    BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi  = 4197,
4213
    BUFFER_LOAD_UBYTE_D16_HI_IDXEN_vi = 4198,
4214
    BUFFER_LOAD_UBYTE_D16_HI_OFFEN_vi = 4199,
4215
    BUFFER_LOAD_UBYTE_D16_HI_OFFSET_vi  = 4200,
4216
    BUFFER_LOAD_UBYTE_D16_IDXEN_vi  = 4201,
4217
    BUFFER_LOAD_UBYTE_D16_OFFEN_vi  = 4202,
4218
    BUFFER_LOAD_UBYTE_D16_OFFSET_vi = 4203,
4219
    BUFFER_LOAD_UBYTE_IDXEN_si  = 4204,
4220
    BUFFER_LOAD_UBYTE_IDXEN_vi  = 4205,
4221
    BUFFER_LOAD_UBYTE_LDS_ADDR64_si = 4206,
4222
    BUFFER_LOAD_UBYTE_LDS_BOTHEN_si = 4207,
4223
    BUFFER_LOAD_UBYTE_LDS_BOTHEN_vi = 4208,
4224
    BUFFER_LOAD_UBYTE_LDS_IDXEN_si  = 4209,
4225
    BUFFER_LOAD_UBYTE_LDS_IDXEN_vi  = 4210,
4226
    BUFFER_LOAD_UBYTE_LDS_OFFEN_si  = 4211,
4227
    BUFFER_LOAD_UBYTE_LDS_OFFEN_vi  = 4212,
4228
    BUFFER_LOAD_UBYTE_LDS_OFFSET_si = 4213,
4229
    BUFFER_LOAD_UBYTE_LDS_OFFSET_vi = 4214,
4230
    BUFFER_LOAD_UBYTE_OFFEN_si  = 4215,
4231
    BUFFER_LOAD_UBYTE_OFFEN_vi  = 4216,
4232
    BUFFER_LOAD_UBYTE_OFFSET_si = 4217,
4233
    BUFFER_LOAD_UBYTE_OFFSET_vi = 4218,
4234
    BUFFER_LOAD_USHORT_ADDR64_si  = 4219,
4235
    BUFFER_LOAD_USHORT_BOTHEN_si  = 4220,
4236
    BUFFER_LOAD_USHORT_BOTHEN_vi  = 4221,
4237
    BUFFER_LOAD_USHORT_IDXEN_si = 4222,
4238
    BUFFER_LOAD_USHORT_IDXEN_vi = 4223,
4239
    BUFFER_LOAD_USHORT_LDS_ADDR64_si  = 4224,
4240
    BUFFER_LOAD_USHORT_LDS_BOTHEN_si  = 4225,
4241
    BUFFER_LOAD_USHORT_LDS_BOTHEN_vi  = 4226,
4242
    BUFFER_LOAD_USHORT_LDS_IDXEN_si = 4227,
4243
    BUFFER_LOAD_USHORT_LDS_IDXEN_vi = 4228,
4244
    BUFFER_LOAD_USHORT_LDS_OFFEN_si = 4229,
4245
    BUFFER_LOAD_USHORT_LDS_OFFEN_vi = 4230,
4246
    BUFFER_LOAD_USHORT_LDS_OFFSET_si  = 4231,
4247
    BUFFER_LOAD_USHORT_LDS_OFFSET_vi  = 4232,
4248
    BUFFER_LOAD_USHORT_OFFEN_si = 4233,
4249
    BUFFER_LOAD_USHORT_OFFEN_vi = 4234,
4250
    BUFFER_LOAD_USHORT_OFFSET_si  = 4235,
4251
    BUFFER_LOAD_USHORT_OFFSET_vi  = 4236,
4252
    BUFFER_STORE_BYTE_ADDR64_si = 4237,
4253
    BUFFER_STORE_BYTE_BOTHEN_si = 4238,
4254
    BUFFER_STORE_BYTE_BOTHEN_vi = 4239,
4255
    BUFFER_STORE_BYTE_D16_HI_BOTHEN_vi  = 4240,
4256
    BUFFER_STORE_BYTE_D16_HI_IDXEN_vi = 4241,
4257
    BUFFER_STORE_BYTE_D16_HI_OFFEN_vi = 4242,
4258
    BUFFER_STORE_BYTE_D16_HI_OFFSET_vi  = 4243,
4259
    BUFFER_STORE_BYTE_IDXEN_si  = 4244,
4260
    BUFFER_STORE_BYTE_IDXEN_vi  = 4245,
4261
    BUFFER_STORE_BYTE_OFFEN_si  = 4246,
4262
    BUFFER_STORE_BYTE_OFFEN_vi  = 4247,
4263
    BUFFER_STORE_BYTE_OFFSET_si = 4248,
4264
    BUFFER_STORE_BYTE_OFFSET_vi = 4249,
4265
    BUFFER_STORE_DWORDX2_ADDR64_si  = 4250,
4266
    BUFFER_STORE_DWORDX2_BOTHEN_si  = 4251,
4267
    BUFFER_STORE_DWORDX2_BOTHEN_vi  = 4252,
4268
    BUFFER_STORE_DWORDX2_IDXEN_si = 4253,
4269
    BUFFER_STORE_DWORDX2_IDXEN_vi = 4254,
4270
    BUFFER_STORE_DWORDX2_OFFEN_si = 4255,
4271
    BUFFER_STORE_DWORDX2_OFFEN_vi = 4256,
4272
    BUFFER_STORE_DWORDX2_OFFSET_si  = 4257,
4273
    BUFFER_STORE_DWORDX2_OFFSET_vi  = 4258,
4274
    BUFFER_STORE_DWORDX3_ADDR64_si  = 4259,
4275
    BUFFER_STORE_DWORDX3_BOTHEN_si  = 4260,
4276
    BUFFER_STORE_DWORDX3_BOTHEN_vi  = 4261,
4277
    BUFFER_STORE_DWORDX3_IDXEN_si = 4262,
4278
    BUFFER_STORE_DWORDX3_IDXEN_vi = 4263,
4279
    BUFFER_STORE_DWORDX3_OFFEN_si = 4264,
4280
    BUFFER_STORE_DWORDX3_OFFEN_vi = 4265,
4281
    BUFFER_STORE_DWORDX3_OFFSET_si  = 4266,
4282
    BUFFER_STORE_DWORDX3_OFFSET_vi  = 4267,
4283
    BUFFER_STORE_DWORDX4_ADDR64_si  = 4268,
4284
    BUFFER_STORE_DWORDX4_BOTHEN_si  = 4269,
4285
    BUFFER_STORE_DWORDX4_BOTHEN_vi  = 4270,
4286
    BUFFER_STORE_DWORDX4_IDXEN_si = 4271,
4287
    BUFFER_STORE_DWORDX4_IDXEN_vi = 4272,
4288
    BUFFER_STORE_DWORDX4_OFFEN_si = 4273,
4289
    BUFFER_STORE_DWORDX4_OFFEN_vi = 4274,
4290
    BUFFER_STORE_DWORDX4_OFFSET_si  = 4275,
4291
    BUFFER_STORE_DWORDX4_OFFSET_vi  = 4276,
4292
    BUFFER_STORE_DWORD_ADDR64_si  = 4277,
4293
    BUFFER_STORE_DWORD_BOTHEN_si  = 4278,
4294
    BUFFER_STORE_DWORD_BOTHEN_vi  = 4279,
4295
    BUFFER_STORE_DWORD_IDXEN_si = 4280,
4296
    BUFFER_STORE_DWORD_IDXEN_vi = 4281,
4297
    BUFFER_STORE_DWORD_OFFEN_si = 4282,
4298
    BUFFER_STORE_DWORD_OFFEN_vi = 4283,
4299
    BUFFER_STORE_DWORD_OFFSET_si  = 4284,
4300
    BUFFER_STORE_DWORD_OFFSET_vi  = 4285,
4301
    BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_vi  = 4286,
4302
    BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_vi = 4287,
4303
    BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_vi = 4288,
4304
    BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_vi  = 4289,
4305
    BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi  = 4290,
4306
    BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi = 4291,
4307
    BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi = 4292,
4308
    BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi  = 4293,
4309
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80 = 4294,
4310
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80  = 4295,
4311
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80  = 4296,
4312
    BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80 = 4297,
4313
    BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi = 4298,
4314
    BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi  = 4299,
4315
    BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi  = 4300,
4316
    BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi = 4301,
4317
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80  = 4302,
4318
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80 = 4303,
4319
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80 = 4304,
4320
    BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80  = 4305,
4321
    BUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi  = 4306,
4322
    BUFFER_STORE_FORMAT_D16_XY_IDXEN_vi = 4307,
4323
    BUFFER_STORE_FORMAT_D16_XY_OFFEN_vi = 4308,
4324
    BUFFER_STORE_FORMAT_D16_XY_OFFSET_vi  = 4309,
4325
    BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80 = 4310,
4326
    BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80  = 4311,
4327
    BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80  = 4312,
4328
    BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80 = 4313,
4329
    BUFFER_STORE_FORMAT_D16_X_BOTHEN_vi = 4314,
4330
    BUFFER_STORE_FORMAT_D16_X_IDXEN_vi  = 4315,
4331
    BUFFER_STORE_FORMAT_D16_X_OFFEN_vi  = 4316,
4332
    BUFFER_STORE_FORMAT_D16_X_OFFSET_vi = 4317,
4333
    BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80  = 4318,
4334
    BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80 = 4319,
4335
    BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80 = 4320,
4336
    BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80  = 4321,
4337
    BUFFER_STORE_FORMAT_XYZW_ADDR64_si  = 4322,
4338
    BUFFER_STORE_FORMAT_XYZW_BOTHEN_si  = 4323,
4339
    BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi  = 4324,
4340
    BUFFER_STORE_FORMAT_XYZW_IDXEN_si = 4325,
4341
    BUFFER_STORE_FORMAT_XYZW_IDXEN_vi = 4326,
4342
    BUFFER_STORE_FORMAT_XYZW_OFFEN_si = 4327,
4343
    BUFFER_STORE_FORMAT_XYZW_OFFEN_vi = 4328,
4344
    BUFFER_STORE_FORMAT_XYZW_OFFSET_si  = 4329,
4345
    BUFFER_STORE_FORMAT_XYZW_OFFSET_vi  = 4330,
4346
    BUFFER_STORE_FORMAT_XYZ_ADDR64_si = 4331,
4347
    BUFFER_STORE_FORMAT_XYZ_BOTHEN_si = 4332,
4348
    BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi = 4333,
4349
    BUFFER_STORE_FORMAT_XYZ_IDXEN_si  = 4334,
4350
    BUFFER_STORE_FORMAT_XYZ_IDXEN_vi  = 4335,
4351
    BUFFER_STORE_FORMAT_XYZ_OFFEN_si  = 4336,
4352
    BUFFER_STORE_FORMAT_XYZ_OFFEN_vi  = 4337,
4353
    BUFFER_STORE_FORMAT_XYZ_OFFSET_si = 4338,
4354
    BUFFER_STORE_FORMAT_XYZ_OFFSET_vi = 4339,
4355
    BUFFER_STORE_FORMAT_XY_ADDR64_si  = 4340,
4356
    BUFFER_STORE_FORMAT_XY_BOTHEN_si  = 4341,
4357
    BUFFER_STORE_FORMAT_XY_BOTHEN_vi  = 4342,
4358
    BUFFER_STORE_FORMAT_XY_IDXEN_si = 4343,
4359
    BUFFER_STORE_FORMAT_XY_IDXEN_vi = 4344,
4360
    BUFFER_STORE_FORMAT_XY_OFFEN_si = 4345,
4361
    BUFFER_STORE_FORMAT_XY_OFFEN_vi = 4346,
4362
    BUFFER_STORE_FORMAT_XY_OFFSET_si  = 4347,
4363
    BUFFER_STORE_FORMAT_XY_OFFSET_vi  = 4348,
4364
    BUFFER_STORE_FORMAT_X_ADDR64_si = 4349,
4365
    BUFFER_STORE_FORMAT_X_BOTHEN_si = 4350,
4366
    BUFFER_STORE_FORMAT_X_BOTHEN_vi = 4351,
4367
    BUFFER_STORE_FORMAT_X_IDXEN_si  = 4352,
4368
    BUFFER_STORE_FORMAT_X_IDXEN_vi  = 4353,
4369
    BUFFER_STORE_FORMAT_X_OFFEN_si  = 4354,
4370
    BUFFER_STORE_FORMAT_X_OFFEN_vi  = 4355,
4371
    BUFFER_STORE_FORMAT_X_OFFSET_si = 4356,
4372
    BUFFER_STORE_FORMAT_X_OFFSET_vi = 4357,
4373
    BUFFER_STORE_LDS_DWORD_vi = 4358,
4374
    BUFFER_STORE_SHORT_ADDR64_si  = 4359,
4375
    BUFFER_STORE_SHORT_BOTHEN_si  = 4360,
4376
    BUFFER_STORE_SHORT_BOTHEN_vi  = 4361,
4377
    BUFFER_STORE_SHORT_D16_HI_BOTHEN_vi = 4362,
4378
    BUFFER_STORE_SHORT_D16_HI_IDXEN_vi  = 4363,
4379
    BUFFER_STORE_SHORT_D16_HI_OFFEN_vi  = 4364,
4380
    BUFFER_STORE_SHORT_D16_HI_OFFSET_vi = 4365,
4381
    BUFFER_STORE_SHORT_IDXEN_si = 4366,
4382
    BUFFER_STORE_SHORT_IDXEN_vi = 4367,
4383
    BUFFER_STORE_SHORT_OFFEN_si = 4368,
4384
    BUFFER_STORE_SHORT_OFFEN_vi = 4369,
4385
    BUFFER_STORE_SHORT_OFFSET_si  = 4370,
4386
    BUFFER_STORE_SHORT_OFFSET_vi  = 4371,
4387
    BUFFER_WBINVL1_SC_si  = 4372,
4388
    BUFFER_WBINVL1_VOL_ci = 4373,
4389
    BUFFER_WBINVL1_VOL_vi = 4374,
4390
    BUFFER_WBINVL1_si = 4375,
4391
    BUFFER_WBINVL1_vi = 4376,
4392
    DS_ADD_F32_vi = 4377,
4393
    DS_ADD_RTN_F32_vi = 4378,
4394
    DS_ADD_RTN_U32_si = 4379,
4395
    DS_ADD_RTN_U32_vi = 4380,
4396
    DS_ADD_RTN_U64_si = 4381,
4397
    DS_ADD_RTN_U64_vi = 4382,
4398
    DS_ADD_SRC2_F32_vi  = 4383,
4399
    DS_ADD_SRC2_U32_si  = 4384,
4400
    DS_ADD_SRC2_U32_vi  = 4385,
4401
    DS_ADD_SRC2_U64_si  = 4386,
4402
    DS_ADD_SRC2_U64_vi  = 4387,
4403
    DS_ADD_U32_si = 4388,
4404
    DS_ADD_U32_vi = 4389,
4405
    DS_ADD_U64_si = 4390,
4406
    DS_ADD_U64_vi = 4391,
4407
    DS_AND_B32_si = 4392,
4408
    DS_AND_B32_vi = 4393,
4409
    DS_AND_B64_si = 4394,
4410
    DS_AND_B64_vi = 4395,
4411
    DS_AND_RTN_B32_si = 4396,
4412
    DS_AND_RTN_B32_vi = 4397,
4413
    DS_AND_RTN_B64_si = 4398,
4414
    DS_AND_RTN_B64_vi = 4399,
4415
    DS_AND_SRC2_B32_si  = 4400,
4416
    DS_AND_SRC2_B32_vi  = 4401,
4417
    DS_AND_SRC2_B64_si  = 4402,
4418
    DS_AND_SRC2_B64_vi  = 4403,
4419
    DS_APPEND_si  = 4404,
4420
    DS_APPEND_vi  = 4405,
4421
    DS_BPERMUTE_B32_vi  = 4406,
4422
    DS_CMPST_B32_si = 4407,
4423
    DS_CMPST_B32_vi = 4408,
4424
    DS_CMPST_B64_si = 4409,
4425
    DS_CMPST_B64_vi = 4410,
4426
    DS_CMPST_F32_si = 4411,
4427
    DS_CMPST_F32_vi = 4412,
4428
    DS_CMPST_F64_si = 4413,
4429
    DS_CMPST_F64_vi = 4414,
4430
    DS_CMPST_RTN_B32_si = 4415,
4431
    DS_CMPST_RTN_B32_vi = 4416,
4432
    DS_CMPST_RTN_B64_si = 4417,
4433
    DS_CMPST_RTN_B64_vi = 4418,
4434
    DS_CMPST_RTN_F32_si = 4419,
4435
    DS_CMPST_RTN_F32_vi = 4420,
4436
    DS_CMPST_RTN_F64_si = 4421,
4437
    DS_CMPST_RTN_F64_vi = 4422,
4438
    DS_CONDXCHG32_RTN_B64_si  = 4423,
4439
    DS_CONDXCHG32_RTN_B64_vi  = 4424,
4440
    DS_CONSUME_si = 4425,
4441
    DS_CONSUME_vi = 4426,
4442
    DS_DEC_RTN_U32_si = 4427,
4443
    DS_DEC_RTN_U32_vi = 4428,
4444
    DS_DEC_RTN_U64_si = 4429,
4445
    DS_DEC_RTN_U64_vi = 4430,
4446
    DS_DEC_SRC2_U32_si  = 4431,
4447
    DS_DEC_SRC2_U32_vi  = 4432,
4448
    DS_DEC_SRC2_U64_si  = 4433,
4449
    DS_DEC_SRC2_U64_vi  = 4434,
4450
    DS_DEC_U32_si = 4435,
4451
    DS_DEC_U32_vi = 4436,
4452
    DS_DEC_U64_si = 4437,
4453
    DS_DEC_U64_vi = 4438,
4454
    DS_GWS_BARRIER_si = 4439,
4455
    DS_GWS_BARRIER_vi = 4440,
4456
    DS_GWS_INIT_si  = 4441,
4457
    DS_GWS_INIT_vi  = 4442,
4458
    DS_GWS_SEMA_BR_si = 4443,
4459
    DS_GWS_SEMA_BR_vi = 4444,
4460
    DS_GWS_SEMA_P_si  = 4445,
4461
    DS_GWS_SEMA_P_vi  = 4446,
4462
    DS_GWS_SEMA_RELEASE_ALL_si  = 4447,
4463
    DS_GWS_SEMA_RELEASE_ALL_vi  = 4448,
4464
    DS_GWS_SEMA_V_si  = 4449,
4465
    DS_GWS_SEMA_V_vi  = 4450,
4466
    DS_INC_RTN_U32_si = 4451,
4467
    DS_INC_RTN_U32_vi = 4452,
4468
    DS_INC_RTN_U64_si = 4453,
4469
    DS_INC_RTN_U64_vi = 4454,
4470
    DS_INC_SRC2_U32_si  = 4455,
4471
    DS_INC_SRC2_U32_vi  = 4456,
4472
    DS_INC_SRC2_U64_si  = 4457,
4473
    DS_INC_SRC2_U64_vi  = 4458,
4474
    DS_INC_U32_si = 4459,
4475
    DS_INC_U32_vi = 4460,
4476
    DS_INC_U64_si = 4461,
4477
    DS_INC_U64_vi = 4462,
4478
    DS_MAX_F32_si = 4463,
4479
    DS_MAX_F32_vi = 4464,
4480
    DS_MAX_F64_si = 4465,
4481
    DS_MAX_F64_vi = 4466,
4482
    DS_MAX_I32_si = 4467,
4483
    DS_MAX_I32_vi = 4468,
4484
    DS_MAX_I64_si = 4469,
4485
    DS_MAX_I64_vi = 4470,
4486
    DS_MAX_RTN_F32_si = 4471,
4487
    DS_MAX_RTN_F32_vi = 4472,
4488
    DS_MAX_RTN_F64_si = 4473,
4489
    DS_MAX_RTN_F64_vi = 4474,
4490
    DS_MAX_RTN_I32_si = 4475,
4491
    DS_MAX_RTN_I32_vi = 4476,
4492
    DS_MAX_RTN_I64_si = 4477,
4493
    DS_MAX_RTN_I64_vi = 4478,
4494
    DS_MAX_RTN_U32_si = 4479,
4495
    DS_MAX_RTN_U32_vi = 4480,
4496
    DS_MAX_RTN_U64_si = 4481,
4497
    DS_MAX_RTN_U64_vi = 4482,
4498
    DS_MAX_SRC2_F32_si  = 4483,
4499
    DS_MAX_SRC2_F32_vi  = 4484,
4500
    DS_MAX_SRC2_F64_si  = 4485,
4501
    DS_MAX_SRC2_F64_vi  = 4486,
4502
    DS_MAX_SRC2_I32_si  = 4487,
4503
    DS_MAX_SRC2_I32_vi  = 4488,
4504
    DS_MAX_SRC2_I64_si  = 4489,
4505
    DS_MAX_SRC2_I64_vi  = 4490,
4506
    DS_MAX_SRC2_U32_si  = 4491,
4507
    DS_MAX_SRC2_U32_vi  = 4492,
4508
    DS_MAX_SRC2_U64_si  = 4493,
4509
    DS_MAX_SRC2_U64_vi  = 4494,
4510
    DS_MAX_U32_si = 4495,
4511
    DS_MAX_U32_vi = 4496,
4512
    DS_MAX_U64_si = 4497,
4513
    DS_MAX_U64_vi = 4498,
4514
    DS_MIN_F32_si = 4499,
4515
    DS_MIN_F32_vi = 4500,
4516
    DS_MIN_F64_si = 4501,
4517
    DS_MIN_F64_vi = 4502,
4518
    DS_MIN_I32_si = 4503,
4519
    DS_MIN_I32_vi = 4504,
4520
    DS_MIN_I64_si = 4505,
4521
    DS_MIN_I64_vi = 4506,
4522
    DS_MIN_RTN_F32_si = 4507,
4523
    DS_MIN_RTN_F32_vi = 4508,
4524
    DS_MIN_RTN_F64_si = 4509,
4525
    DS_MIN_RTN_F64_vi = 4510,
4526
    DS_MIN_RTN_I32_si = 4511,
4527
    DS_MIN_RTN_I32_vi = 4512,
4528
    DS_MIN_RTN_I64_si = 4513,
4529
    DS_MIN_RTN_I64_vi = 4514,
4530
    DS_MIN_RTN_U32_si = 4515,
4531
    DS_MIN_RTN_U32_vi = 4516,
4532
    DS_MIN_RTN_U64_si = 4517,
4533
    DS_MIN_RTN_U64_vi = 4518,
4534
    DS_MIN_SRC2_F32_si  = 4519,
4535
    DS_MIN_SRC2_F32_vi  = 4520,
4536
    DS_MIN_SRC2_F64_si  = 4521,
4537
    DS_MIN_SRC2_F64_vi  = 4522,
4538
    DS_MIN_SRC2_I32_si  = 4523,
4539
    DS_MIN_SRC2_I32_vi  = 4524,
4540
    DS_MIN_SRC2_I64_si  = 4525,
4541
    DS_MIN_SRC2_I64_vi  = 4526,
4542
    DS_MIN_SRC2_U32_si  = 4527,
4543
    DS_MIN_SRC2_U32_vi  = 4528,
4544
    DS_MIN_SRC2_U64_si  = 4529,
4545
    DS_MIN_SRC2_U64_vi  = 4530,
4546
    DS_MIN_U32_si = 4531,
4547
    DS_MIN_U32_vi = 4532,
4548
    DS_MIN_U64_si = 4533,
4549
    DS_MIN_U64_vi = 4534,
4550
    DS_MSKOR_B32_si = 4535,
4551
    DS_MSKOR_B32_vi = 4536,
4552
    DS_MSKOR_B64_si = 4537,
4553
    DS_MSKOR_B64_vi = 4538,
4554
    DS_MSKOR_RTN_B32_si = 4539,
4555
    DS_MSKOR_RTN_B32_vi = 4540,
4556
    DS_MSKOR_RTN_B64_si = 4541,
4557
    DS_MSKOR_RTN_B64_vi = 4542,
4558
    DS_NOP_si = 4543,
4559
    DS_NOP_vi = 4544,
4560
    DS_ORDERED_COUNT_si = 4545,
4561
    DS_ORDERED_COUNT_vi = 4546,
4562
    DS_OR_B32_si  = 4547,
4563
    DS_OR_B32_vi  = 4548,
4564
    DS_OR_B64_si  = 4549,
4565
    DS_OR_B64_vi  = 4550,
4566
    DS_OR_RTN_B32_si  = 4551,
4567
    DS_OR_RTN_B32_vi  = 4552,
4568
    DS_OR_RTN_B64_si  = 4553,
4569
    DS_OR_RTN_B64_vi  = 4554,
4570
    DS_OR_SRC2_B32_si = 4555,
4571
    DS_OR_SRC2_B32_vi = 4556,
4572
    DS_OR_SRC2_B64_si = 4557,
4573
    DS_OR_SRC2_B64_vi = 4558,
4574
    DS_PERMUTE_B32_vi = 4559,
4575
    DS_READ2ST64_B32_si = 4560,
4576
    DS_READ2ST64_B32_vi = 4561,
4577
    DS_READ2ST64_B64_si = 4562,
4578
    DS_READ2ST64_B64_vi = 4563,
4579
    DS_READ2_B32_si = 4564,
4580
    DS_READ2_B32_vi = 4565,
4581
    DS_READ2_B64_si = 4566,
4582
    DS_READ2_B64_vi = 4567,
4583
    DS_READ_ADDTID_B32_vi = 4568,
4584
    DS_READ_B128_si = 4569,
4585
    DS_READ_B128_vi = 4570,
4586
    DS_READ_B32_si  = 4571,
4587
    DS_READ_B32_vi  = 4572,
4588
    DS_READ_B64_si  = 4573,
4589
    DS_READ_B64_vi  = 4574,
4590
    DS_READ_B96_si  = 4575,
4591
    DS_READ_B96_vi  = 4576,
4592
    DS_READ_I16_si  = 4577,
4593
    DS_READ_I16_vi  = 4578,
4594
    DS_READ_I8_D16_HI_vi  = 4579,
4595
    DS_READ_I8_D16_vi = 4580,
4596
    DS_READ_I8_si = 4581,
4597
    DS_READ_I8_vi = 4582,
4598
    DS_READ_U16_D16_HI_vi = 4583,
4599
    DS_READ_U16_D16_vi  = 4584,
4600
    DS_READ_U16_si  = 4585,
4601
    DS_READ_U16_vi  = 4586,
4602
    DS_READ_U8_D16_HI_vi  = 4587,
4603
    DS_READ_U8_D16_vi = 4588,
4604
    DS_READ_U8_si = 4589,
4605
    DS_READ_U8_vi = 4590,
4606
    DS_RSUB_RTN_U32_si  = 4591,
4607
    DS_RSUB_RTN_U32_vi  = 4592,
4608
    DS_RSUB_RTN_U64_si  = 4593,
4609
    DS_RSUB_RTN_U64_vi  = 4594,
4610
    DS_RSUB_SRC2_U32_si = 4595,
4611
    DS_RSUB_SRC2_U32_vi = 4596,
4612
    DS_RSUB_SRC2_U64_si = 4597,
4613
    DS_RSUB_SRC2_U64_vi = 4598,
4614
    DS_RSUB_U32_si  = 4599,
4615
    DS_RSUB_U32_vi  = 4600,
4616
    DS_RSUB_U64_si  = 4601,
4617
    DS_RSUB_U64_vi  = 4602,
4618
    DS_SUB_RTN_U32_si = 4603,
4619
    DS_SUB_RTN_U32_vi = 4604,
4620
    DS_SUB_RTN_U64_si = 4605,
4621
    DS_SUB_RTN_U64_vi = 4606,
4622
    DS_SUB_SRC2_U32_si  = 4607,
4623
    DS_SUB_SRC2_U32_vi  = 4608,
4624
    DS_SUB_SRC2_U64_si  = 4609,
4625
    DS_SUB_SRC2_U64_vi  = 4610,
4626
    DS_SUB_U32_si = 4611,
4627
    DS_SUB_U32_vi = 4612,
4628
    DS_SUB_U64_si = 4613,
4629
    DS_SUB_U64_vi = 4614,
4630
    DS_SWIZZLE_B32_si = 4615,
4631
    DS_SWIZZLE_B32_vi = 4616,
4632
    DS_WRAP_RTN_B32_si  = 4617,
4633
    DS_WRAP_RTN_B32_vi  = 4618,
4634
    DS_WRITE2ST64_B32_si  = 4619,
4635
    DS_WRITE2ST64_B32_vi  = 4620,
4636
    DS_WRITE2ST64_B64_si  = 4621,
4637
    DS_WRITE2ST64_B64_vi  = 4622,
4638
    DS_WRITE2_B32_si  = 4623,
4639
    DS_WRITE2_B32_vi  = 4624,
4640
    DS_WRITE2_B64_si  = 4625,
4641
    DS_WRITE2_B64_vi  = 4626,
4642
    DS_WRITE_ADDTID_B32_vi  = 4627,
4643
    DS_WRITE_B128_si  = 4628,
4644
    DS_WRITE_B128_vi  = 4629,
4645
    DS_WRITE_B16_D16_HI_vi  = 4630,
4646
    DS_WRITE_B16_si = 4631,
4647
    DS_WRITE_B16_vi = 4632,
4648
    DS_WRITE_B32_si = 4633,
4649
    DS_WRITE_B32_vi = 4634,
4650
    DS_WRITE_B64_si = 4635,
4651
    DS_WRITE_B64_vi = 4636,
4652
    DS_WRITE_B8_D16_HI_vi = 4637,
4653
    DS_WRITE_B8_si  = 4638,
4654
    DS_WRITE_B8_vi  = 4639,
4655
    DS_WRITE_B96_si = 4640,
4656
    DS_WRITE_B96_vi = 4641,
4657
    DS_WRITE_SRC2_B32_si  = 4642,
4658
    DS_WRITE_SRC2_B32_vi  = 4643,
4659
    DS_WRITE_SRC2_B64_si  = 4644,
4660
    DS_WRITE_SRC2_B64_vi  = 4645,
4661
    DS_WRXCHG2ST64_RTN_B32_si = 4646,
4662
    DS_WRXCHG2ST64_RTN_B32_vi = 4647,
4663
    DS_WRXCHG2ST64_RTN_B64_si = 4648,
4664
    DS_WRXCHG2ST64_RTN_B64_vi = 4649,
4665
    DS_WRXCHG2_RTN_B32_si = 4650,
4666
    DS_WRXCHG2_RTN_B32_vi = 4651,
4667
    DS_WRXCHG2_RTN_B64_si = 4652,
4668
    DS_WRXCHG2_RTN_B64_vi = 4653,
4669
    DS_WRXCHG_RTN_B32_si  = 4654,
4670
    DS_WRXCHG_RTN_B32_vi  = 4655,
4671
    DS_WRXCHG_RTN_B64_si  = 4656,
4672
    DS_WRXCHG_RTN_B64_vi  = 4657,
4673
    DS_XOR_B32_si = 4658,
4674
    DS_XOR_B32_vi = 4659,
4675
    DS_XOR_B64_si = 4660,
4676
    DS_XOR_B64_vi = 4661,
4677
    DS_XOR_RTN_B32_si = 4662,
4678
    DS_XOR_RTN_B32_vi = 4663,
4679
    DS_XOR_RTN_B64_si = 4664,
4680
    DS_XOR_RTN_B64_vi = 4665,
4681
    DS_XOR_SRC2_B32_si  = 4666,
4682
    DS_XOR_SRC2_B32_vi  = 4667,
4683
    DS_XOR_SRC2_B64_si  = 4668,
4684
    DS_XOR_SRC2_B64_vi  = 4669,
4685
    EXP_DONE_si = 4670,
4686
    EXP_DONE_vi = 4671,
4687
    EXP_si  = 4672,
4688
    EXP_vi  = 4673,
4689
    FLAT_ATOMIC_ADD_RTN_ci  = 4674,
4690
    FLAT_ATOMIC_ADD_RTN_vi  = 4675,
4691
    FLAT_ATOMIC_ADD_X2_RTN_ci = 4676,
4692
    FLAT_ATOMIC_ADD_X2_RTN_vi = 4677,
4693
    FLAT_ATOMIC_ADD_X2_ci = 4678,
4694
    FLAT_ATOMIC_ADD_X2_vi = 4679,
4695
    FLAT_ATOMIC_ADD_ci  = 4680,
4696
    FLAT_ATOMIC_ADD_vi  = 4681,
4697
    FLAT_ATOMIC_AND_RTN_ci  = 4682,
4698
    FLAT_ATOMIC_AND_RTN_vi  = 4683,
4699
    FLAT_ATOMIC_AND_X2_RTN_ci = 4684,
4700
    FLAT_ATOMIC_AND_X2_RTN_vi = 4685,
4701
    FLAT_ATOMIC_AND_X2_ci = 4686,
4702
    FLAT_ATOMIC_AND_X2_vi = 4687,
4703
    FLAT_ATOMIC_AND_ci  = 4688,
4704
    FLAT_ATOMIC_AND_vi  = 4689,
4705
    FLAT_ATOMIC_CMPSWAP_RTN_ci  = 4690,
4706
    FLAT_ATOMIC_CMPSWAP_RTN_vi  = 4691,
4707
    FLAT_ATOMIC_CMPSWAP_X2_RTN_ci = 4692,
4708
    FLAT_ATOMIC_CMPSWAP_X2_RTN_vi = 4693,
4709
    FLAT_ATOMIC_CMPSWAP_X2_ci = 4694,
4710
    FLAT_ATOMIC_CMPSWAP_X2_vi = 4695,
4711
    FLAT_ATOMIC_CMPSWAP_ci  = 4696,
4712
    FLAT_ATOMIC_CMPSWAP_vi  = 4697,
4713
    FLAT_ATOMIC_DEC_RTN_ci  = 4698,
4714
    FLAT_ATOMIC_DEC_RTN_vi  = 4699,
4715
    FLAT_ATOMIC_DEC_X2_RTN_ci = 4700,
4716
    FLAT_ATOMIC_DEC_X2_RTN_vi = 4701,
4717
    FLAT_ATOMIC_DEC_X2_ci = 4702,
4718
    FLAT_ATOMIC_DEC_X2_vi = 4703,
4719
    FLAT_ATOMIC_DEC_ci  = 4704,
4720
    FLAT_ATOMIC_DEC_vi  = 4705,
4721
    FLAT_ATOMIC_FCMPSWAP_RTN_ci = 4706,
4722
    FLAT_ATOMIC_FCMPSWAP_X2_RTN_ci  = 4707,
4723
    FLAT_ATOMIC_FCMPSWAP_X2_ci  = 4708,
4724
    FLAT_ATOMIC_FCMPSWAP_ci = 4709,
4725
    FLAT_ATOMIC_FMAX_RTN_ci = 4710,
4726
    FLAT_ATOMIC_FMAX_X2_RTN_ci  = 4711,
4727
    FLAT_ATOMIC_FMAX_X2_ci  = 4712,
4728
    FLAT_ATOMIC_FMAX_ci = 4713,
4729
    FLAT_ATOMIC_FMIN_RTN_ci = 4714,
4730
    FLAT_ATOMIC_FMIN_X2_RTN_ci  = 4715,
4731
    FLAT_ATOMIC_FMIN_X2_ci  = 4716,
4732
    FLAT_ATOMIC_FMIN_ci = 4717,
4733
    FLAT_ATOMIC_INC_RTN_ci  = 4718,
4734
    FLAT_ATOMIC_INC_RTN_vi  = 4719,
4735
    FLAT_ATOMIC_INC_X2_RTN_ci = 4720,
4736
    FLAT_ATOMIC_INC_X2_RTN_vi = 4721,
4737
    FLAT_ATOMIC_INC_X2_ci = 4722,
4738
    FLAT_ATOMIC_INC_X2_vi = 4723,
4739
    FLAT_ATOMIC_INC_ci  = 4724,
4740
    FLAT_ATOMIC_INC_vi  = 4725,
4741
    FLAT_ATOMIC_OR_RTN_ci = 4726,
4742
    FLAT_ATOMIC_OR_RTN_vi = 4727,
4743
    FLAT_ATOMIC_OR_X2_RTN_ci  = 4728,
4744
    FLAT_ATOMIC_OR_X2_RTN_vi  = 4729,
4745
    FLAT_ATOMIC_OR_X2_ci  = 4730,
4746
    FLAT_ATOMIC_OR_X2_vi  = 4731,
4747
    FLAT_ATOMIC_OR_ci = 4732,
4748
    FLAT_ATOMIC_OR_vi = 4733,
4749
    FLAT_ATOMIC_SMAX_RTN_ci = 4734,
4750
    FLAT_ATOMIC_SMAX_RTN_vi = 4735,
4751
    FLAT_ATOMIC_SMAX_X2_RTN_ci  = 4736,
4752
    FLAT_ATOMIC_SMAX_X2_RTN_vi  = 4737,
4753
    FLAT_ATOMIC_SMAX_X2_ci  = 4738,
4754
    FLAT_ATOMIC_SMAX_X2_vi  = 4739,
4755
    FLAT_ATOMIC_SMAX_ci = 4740,
4756
    FLAT_ATOMIC_SMAX_vi = 4741,
4757
    FLAT_ATOMIC_SMIN_RTN_ci = 4742,
4758
    FLAT_ATOMIC_SMIN_RTN_vi = 4743,
4759
    FLAT_ATOMIC_SMIN_X2_RTN_ci  = 4744,
4760
    FLAT_ATOMIC_SMIN_X2_RTN_vi  = 4745,
4761
    FLAT_ATOMIC_SMIN_X2_ci  = 4746,
4762
    FLAT_ATOMIC_SMIN_X2_vi  = 4747,
4763
    FLAT_ATOMIC_SMIN_ci = 4748,
4764
    FLAT_ATOMIC_SMIN_vi = 4749,
4765
    FLAT_ATOMIC_SUB_RTN_ci  = 4750,
4766
    FLAT_ATOMIC_SUB_RTN_vi  = 4751,
4767
    FLAT_ATOMIC_SUB_X2_RTN_ci = 4752,
4768
    FLAT_ATOMIC_SUB_X2_RTN_vi = 4753,
4769
    FLAT_ATOMIC_SUB_X2_ci = 4754,
4770
    FLAT_ATOMIC_SUB_X2_vi = 4755,
4771
    FLAT_ATOMIC_SUB_ci  = 4756,
4772
    FLAT_ATOMIC_SUB_vi  = 4757,
4773
    FLAT_ATOMIC_SWAP_RTN_ci = 4758,
4774
    FLAT_ATOMIC_SWAP_RTN_vi = 4759,
4775
    FLAT_ATOMIC_SWAP_X2_RTN_ci  = 4760,
4776
    FLAT_ATOMIC_SWAP_X2_RTN_vi  = 4761,
4777
    FLAT_ATOMIC_SWAP_X2_ci  = 4762,
4778
    FLAT_ATOMIC_SWAP_X2_vi  = 4763,
4779
    FLAT_ATOMIC_SWAP_ci = 4764,
4780
    FLAT_ATOMIC_SWAP_vi = 4765,
4781
    FLAT_ATOMIC_UMAX_RTN_ci = 4766,
4782
    FLAT_ATOMIC_UMAX_RTN_vi = 4767,
4783
    FLAT_ATOMIC_UMAX_X2_RTN_ci  = 4768,
4784
    FLAT_ATOMIC_UMAX_X2_RTN_vi  = 4769,
4785
    FLAT_ATOMIC_UMAX_X2_ci  = 4770,
4786
    FLAT_ATOMIC_UMAX_X2_vi  = 4771,
4787
    FLAT_ATOMIC_UMAX_ci = 4772,
4788
    FLAT_ATOMIC_UMAX_vi = 4773,
4789
    FLAT_ATOMIC_UMIN_RTN_ci = 4774,
4790
    FLAT_ATOMIC_UMIN_RTN_vi = 4775,
4791
    FLAT_ATOMIC_UMIN_X2_RTN_ci  = 4776,
4792
    FLAT_ATOMIC_UMIN_X2_RTN_vi  = 4777,
4793
    FLAT_ATOMIC_UMIN_X2_ci  = 4778,
4794
    FLAT_ATOMIC_UMIN_X2_vi  = 4779,
4795
    FLAT_ATOMIC_UMIN_ci = 4780,
4796
    FLAT_ATOMIC_UMIN_vi = 4781,
4797
    FLAT_ATOMIC_XOR_RTN_ci  = 4782,
4798
    FLAT_ATOMIC_XOR_RTN_vi  = 4783,
4799
    FLAT_ATOMIC_XOR_X2_RTN_ci = 4784,
4800
    FLAT_ATOMIC_XOR_X2_RTN_vi = 4785,
4801
    FLAT_ATOMIC_XOR_X2_ci = 4786,
4802
    FLAT_ATOMIC_XOR_X2_vi = 4787,
4803
    FLAT_ATOMIC_XOR_ci  = 4788,
4804
    FLAT_ATOMIC_XOR_vi  = 4789,
4805
    FLAT_LOAD_DWORDX2_ci  = 4790,
4806
    FLAT_LOAD_DWORDX2_vi  = 4791,
4807
    FLAT_LOAD_DWORDX3_ci  = 4792,
4808
    FLAT_LOAD_DWORDX3_vi  = 4793,
4809
    FLAT_LOAD_DWORDX4_ci  = 4794,
4810
    FLAT_LOAD_DWORDX4_vi  = 4795,
4811
    FLAT_LOAD_DWORD_ci  = 4796,
4812
    FLAT_LOAD_DWORD_vi  = 4797,
4813
    FLAT_LOAD_SBYTE_D16_HI_vi = 4798,
4814
    FLAT_LOAD_SBYTE_D16_vi  = 4799,
4815
    FLAT_LOAD_SBYTE_ci  = 4800,
4816
    FLAT_LOAD_SBYTE_vi  = 4801,
4817
    FLAT_LOAD_SHORT_D16_HI_vi = 4802,
4818
    FLAT_LOAD_SHORT_D16_vi  = 4803,
4819
    FLAT_LOAD_SSHORT_ci = 4804,
4820
    FLAT_LOAD_SSHORT_vi = 4805,
4821
    FLAT_LOAD_UBYTE_D16_HI_vi = 4806,
4822
    FLAT_LOAD_UBYTE_D16_vi  = 4807,
4823
    FLAT_LOAD_UBYTE_ci  = 4808,
4824
    FLAT_LOAD_UBYTE_vi  = 4809,
4825
    FLAT_LOAD_USHORT_ci = 4810,
4826
    FLAT_LOAD_USHORT_vi = 4811,
4827
    FLAT_STORE_BYTE_D16_HI_vi = 4812,
4828
    FLAT_STORE_BYTE_ci  = 4813,
4829
    FLAT_STORE_BYTE_vi  = 4814,
4830
    FLAT_STORE_DWORDX2_ci = 4815,
4831
    FLAT_STORE_DWORDX2_vi = 4816,
4832
    FLAT_STORE_DWORDX3_ci = 4817,
4833
    FLAT_STORE_DWORDX3_vi = 4818,
4834
    FLAT_STORE_DWORDX4_ci = 4819,
4835
    FLAT_STORE_DWORDX4_vi = 4820,
4836
    FLAT_STORE_DWORD_ci = 4821,
4837
    FLAT_STORE_DWORD_vi = 4822,
4838
    FLAT_STORE_SHORT_D16_HI_vi  = 4823,
4839
    FLAT_STORE_SHORT_ci = 4824,
4840
    FLAT_STORE_SHORT_vi = 4825,
4841
    GLOBAL_ATOMIC_ADD_RTN_vi  = 4826,
4842
    GLOBAL_ATOMIC_ADD_SADDR_RTN_vi  = 4827,
4843
    GLOBAL_ATOMIC_ADD_SADDR_vi  = 4828,
4844
    GLOBAL_ATOMIC_ADD_X2_RTN_vi = 4829,
4845
    GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_vi = 4830,
4846
    GLOBAL_ATOMIC_ADD_X2_SADDR_vi = 4831,
4847
    GLOBAL_ATOMIC_ADD_X2_vi = 4832,
4848
    GLOBAL_ATOMIC_ADD_vi  = 4833,
4849
    GLOBAL_ATOMIC_AND_RTN_vi  = 4834,
4850
    GLOBAL_ATOMIC_AND_SADDR_RTN_vi  = 4835,
4851
    GLOBAL_ATOMIC_AND_SADDR_vi  = 4836,
4852
    GLOBAL_ATOMIC_AND_X2_RTN_vi = 4837,
4853
    GLOBAL_ATOMIC_AND_X2_SADDR_RTN_vi = 4838,
4854
    GLOBAL_ATOMIC_AND_X2_SADDR_vi = 4839,
4855
    GLOBAL_ATOMIC_AND_X2_vi = 4840,
4856
    GLOBAL_ATOMIC_AND_vi  = 4841,
4857
    GLOBAL_ATOMIC_CMPSWAP_RTN_vi  = 4842,
4858
    GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_vi  = 4843,
4859
    GLOBAL_ATOMIC_CMPSWAP_SADDR_vi  = 4844,
4860
    GLOBAL_ATOMIC_CMPSWAP_X2_RTN_vi = 4845,
4861
    GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_vi = 4846,
4862
    GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_vi = 4847,
4863
    GLOBAL_ATOMIC_CMPSWAP_X2_vi = 4848,
4864
    GLOBAL_ATOMIC_CMPSWAP_vi  = 4849,
4865
    GLOBAL_ATOMIC_DEC_RTN_vi  = 4850,
4866
    GLOBAL_ATOMIC_DEC_SADDR_RTN_vi  = 4851,
4867
    GLOBAL_ATOMIC_DEC_SADDR_vi  = 4852,
4868
    GLOBAL_ATOMIC_DEC_X2_RTN_vi = 4853,
4869
    GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_vi = 4854,
4870
    GLOBAL_ATOMIC_DEC_X2_SADDR_vi = 4855,
4871
    GLOBAL_ATOMIC_DEC_X2_vi = 4856,
4872
    GLOBAL_ATOMIC_DEC_vi  = 4857,
4873
    GLOBAL_ATOMIC_INC_RTN_vi  = 4858,
4874
    GLOBAL_ATOMIC_INC_SADDR_RTN_vi  = 4859,
4875
    GLOBAL_ATOMIC_INC_SADDR_vi  = 4860,
4876
    GLOBAL_ATOMIC_INC_X2_RTN_vi = 4861,
4877
    GLOBAL_ATOMIC_INC_X2_SADDR_RTN_vi = 4862,
4878
    GLOBAL_ATOMIC_INC_X2_SADDR_vi = 4863,
4879
    GLOBAL_ATOMIC_INC_X2_vi = 4864,
4880
    GLOBAL_ATOMIC_INC_vi  = 4865,
4881
    GLOBAL_ATOMIC_OR_RTN_vi = 4866,
4882
    GLOBAL_ATOMIC_OR_SADDR_RTN_vi = 4867,
4883
    GLOBAL_ATOMIC_OR_SADDR_vi = 4868,
4884
    GLOBAL_ATOMIC_OR_X2_RTN_vi  = 4869,
4885
    GLOBAL_ATOMIC_OR_X2_SADDR_RTN_vi  = 4870,
4886
    GLOBAL_ATOMIC_OR_X2_SADDR_vi  = 4871,
4887
    GLOBAL_ATOMIC_OR_X2_vi  = 4872,
4888
    GLOBAL_ATOMIC_OR_vi = 4873,
4889
    GLOBAL_ATOMIC_SMAX_RTN_vi = 4874,
4890
    GLOBAL_ATOMIC_SMAX_SADDR_RTN_vi = 4875,
4891
    GLOBAL_ATOMIC_SMAX_SADDR_vi = 4876,
4892
    GLOBAL_ATOMIC_SMAX_X2_RTN_vi  = 4877,
4893
    GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_vi  = 4878,
4894
    GLOBAL_ATOMIC_SMAX_X2_SADDR_vi  = 4879,
4895
    GLOBAL_ATOMIC_SMAX_X2_vi  = 4880,
4896
    GLOBAL_ATOMIC_SMAX_vi = 4881,
4897
    GLOBAL_ATOMIC_SMIN_RTN_vi = 4882,
4898
    GLOBAL_ATOMIC_SMIN_SADDR_RTN_vi = 4883,
4899
    GLOBAL_ATOMIC_SMIN_SADDR_vi = 4884,
4900
    GLOBAL_ATOMIC_SMIN_X2_RTN_vi  = 4885,
4901
    GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_vi  = 4886,
4902
    GLOBAL_ATOMIC_SMIN_X2_SADDR_vi  = 4887,
4903
    GLOBAL_ATOMIC_SMIN_X2_vi  = 4888,
4904
    GLOBAL_ATOMIC_SMIN_vi = 4889,
4905
    GLOBAL_ATOMIC_SUB_RTN_vi  = 4890,
4906
    GLOBAL_ATOMIC_SUB_SADDR_RTN_vi  = 4891,
4907
    GLOBAL_ATOMIC_SUB_SADDR_vi  = 4892,
4908
    GLOBAL_ATOMIC_SUB_X2_RTN_vi = 4893,
4909
    GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_vi = 4894,
4910
    GLOBAL_ATOMIC_SUB_X2_SADDR_vi = 4895,
4911
    GLOBAL_ATOMIC_SUB_X2_vi = 4896,
4912
    GLOBAL_ATOMIC_SUB_vi  = 4897,
4913
    GLOBAL_ATOMIC_SWAP_RTN_vi = 4898,
4914
    GLOBAL_ATOMIC_SWAP_SADDR_RTN_vi = 4899,
4915
    GLOBAL_ATOMIC_SWAP_SADDR_vi = 4900,
4916
    GLOBAL_ATOMIC_SWAP_X2_RTN_vi  = 4901,
4917
    GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_vi  = 4902,
4918
    GLOBAL_ATOMIC_SWAP_X2_SADDR_vi  = 4903,
4919
    GLOBAL_ATOMIC_SWAP_X2_vi  = 4904,
4920
    GLOBAL_ATOMIC_SWAP_vi = 4905,
4921
    GLOBAL_ATOMIC_UMAX_RTN_vi = 4906,
4922
    GLOBAL_ATOMIC_UMAX_SADDR_RTN_vi = 4907,
4923
    GLOBAL_ATOMIC_UMAX_SADDR_vi = 4908,
4924
    GLOBAL_ATOMIC_UMAX_X2_RTN_vi  = 4909,
4925
    GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_vi  = 4910,
4926
    GLOBAL_ATOMIC_UMAX_X2_SADDR_vi  = 4911,
4927
    GLOBAL_ATOMIC_UMAX_X2_vi  = 4912,
4928
    GLOBAL_ATOMIC_UMAX_vi = 4913,
4929
    GLOBAL_ATOMIC_UMIN_RTN_vi = 4914,
4930
    GLOBAL_ATOMIC_UMIN_SADDR_RTN_vi = 4915,
4931
    GLOBAL_ATOMIC_UMIN_SADDR_vi = 4916,
4932
    GLOBAL_ATOMIC_UMIN_X2_RTN_vi  = 4917,
4933
    GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_vi  = 4918,
4934
    GLOBAL_ATOMIC_UMIN_X2_SADDR_vi  = 4919,
4935
    GLOBAL_ATOMIC_UMIN_X2_vi  = 4920,
4936
    GLOBAL_ATOMIC_UMIN_vi = 4921,
4937
    GLOBAL_ATOMIC_XOR_RTN_vi  = 4922,
4938
    GLOBAL_ATOMIC_XOR_SADDR_RTN_vi  = 4923,
4939
    GLOBAL_ATOMIC_XOR_SADDR_vi  = 4924,
4940
    GLOBAL_ATOMIC_XOR_X2_RTN_vi = 4925,
4941
    GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_vi = 4926,
4942
    GLOBAL_ATOMIC_XOR_X2_SADDR_vi = 4927,
4943
    GLOBAL_ATOMIC_XOR_X2_vi = 4928,
4944
    GLOBAL_ATOMIC_XOR_vi  = 4929,
4945
    GLOBAL_LOAD_DWORDX2_SADDR_vi  = 4930,
4946
    GLOBAL_LOAD_DWORDX2_vi  = 4931,
4947
    GLOBAL_LOAD_DWORDX3_SADDR_vi  = 4932,
4948
    GLOBAL_LOAD_DWORDX3_vi  = 4933,
4949
    GLOBAL_LOAD_DWORDX4_SADDR_vi  = 4934,
4950
    GLOBAL_LOAD_DWORDX4_vi  = 4935,
4951
    GLOBAL_LOAD_DWORD_SADDR_vi  = 4936,
4952
    GLOBAL_LOAD_DWORD_vi  = 4937,
4953
    GLOBAL_LOAD_SBYTE_D16_HI_SADDR_vi = 4938,
4954
    GLOBAL_LOAD_SBYTE_D16_HI_vi = 4939,
4955
    GLOBAL_LOAD_SBYTE_D16_SADDR_vi  = 4940,
4956
    GLOBAL_LOAD_SBYTE_D16_vi  = 4941,
4957
    GLOBAL_LOAD_SBYTE_SADDR_vi  = 4942,
4958
    GLOBAL_LOAD_SBYTE_vi  = 4943,
4959
    GLOBAL_LOAD_SHORT_D16_HI_SADDR_vi = 4944,
4960
    GLOBAL_LOAD_SHORT_D16_HI_vi = 4945,
4961
    GLOBAL_LOAD_SHORT_D16_SADDR_vi  = 4946,
4962
    GLOBAL_LOAD_SHORT_D16_vi  = 4947,
4963
    GLOBAL_LOAD_SSHORT_SADDR_vi = 4948,
4964
    GLOBAL_LOAD_SSHORT_vi = 4949,
4965
    GLOBAL_LOAD_UBYTE_D16_HI_SADDR_vi = 4950,
4966
    GLOBAL_LOAD_UBYTE_D16_HI_vi = 4951,
4967
    GLOBAL_LOAD_UBYTE_D16_SADDR_vi  = 4952,
4968
    GLOBAL_LOAD_UBYTE_D16_vi  = 4953,
4969
    GLOBAL_LOAD_UBYTE_SADDR_vi  = 4954,
4970
    GLOBAL_LOAD_UBYTE_vi  = 4955,
4971
    GLOBAL_LOAD_USHORT_SADDR_vi = 4956,
4972
    GLOBAL_LOAD_USHORT_vi = 4957,
4973
    GLOBAL_STORE_BYTE_D16_HI_SADDR_vi = 4958,
4974
    GLOBAL_STORE_BYTE_D16_HI_vi = 4959,
4975
    GLOBAL_STORE_BYTE_SADDR_vi  = 4960,
4976
    GLOBAL_STORE_BYTE_vi  = 4961,
4977
    GLOBAL_STORE_DWORDX2_SADDR_vi = 4962,
4978
    GLOBAL_STORE_DWORDX2_vi = 4963,
4979
    GLOBAL_STORE_DWORDX3_SADDR_vi = 4964,
4980
    GLOBAL_STORE_DWORDX3_vi = 4965,
4981
    GLOBAL_STORE_DWORDX4_SADDR_vi = 4966,
4982
    GLOBAL_STORE_DWORDX4_vi = 4967,
4983
    GLOBAL_STORE_DWORD_SADDR_vi = 4968,
4984
    GLOBAL_STORE_DWORD_vi = 4969,
4985
    GLOBAL_STORE_SHORT_D16_HI_SADDR_vi  = 4970,
4986
    GLOBAL_STORE_SHORT_D16_HI_vi  = 4971,
4987
    GLOBAL_STORE_SHORT_SADDR_vi = 4972,
4988
    GLOBAL_STORE_SHORT_vi = 4973,
4989
    IMAGE_ATOMIC_ADD_V1_V1_si = 4974,
4990
    IMAGE_ATOMIC_ADD_V1_V1_vi = 4975,
4991
    IMAGE_ATOMIC_ADD_V1_V2_si = 4976,
4992
    IMAGE_ATOMIC_ADD_V1_V2_vi = 4977,
4993
    IMAGE_ATOMIC_ADD_V1_V3_si = 4978,
4994
    IMAGE_ATOMIC_ADD_V1_V3_vi = 4979,
4995
    IMAGE_ATOMIC_ADD_V1_V4_si = 4980,
4996
    IMAGE_ATOMIC_ADD_V1_V4_vi = 4981,
4997
    IMAGE_ATOMIC_ADD_V2_V1_si = 4982,
4998
    IMAGE_ATOMIC_ADD_V2_V1_vi = 4983,
4999
    IMAGE_ATOMIC_ADD_V2_V2_si = 4984,
5000
    IMAGE_ATOMIC_ADD_V2_V2_vi = 4985,
5001
    IMAGE_ATOMIC_ADD_V2_V3_si = 4986,
5002
    IMAGE_ATOMIC_ADD_V2_V3_vi = 4987,
5003
    IMAGE_ATOMIC_ADD_V2_V4_si = 4988,
5004
    IMAGE_ATOMIC_ADD_V2_V4_vi = 4989,
5005
    IMAGE_ATOMIC_AND_V1_V1_si = 4990,
5006
    IMAGE_ATOMIC_AND_V1_V1_vi = 4991,
5007
    IMAGE_ATOMIC_AND_V1_V2_si = 4992,
5008
    IMAGE_ATOMIC_AND_V1_V2_vi = 4993,
5009
    IMAGE_ATOMIC_AND_V1_V3_si = 4994,
5010
    IMAGE_ATOMIC_AND_V1_V3_vi = 4995,
5011
    IMAGE_ATOMIC_AND_V1_V4_si = 4996,
5012
    IMAGE_ATOMIC_AND_V1_V4_vi = 4997,
5013
    IMAGE_ATOMIC_AND_V2_V1_si = 4998,
5014
    IMAGE_ATOMIC_AND_V2_V1_vi = 4999,
5015
    IMAGE_ATOMIC_AND_V2_V2_si = 5000,
5016
    IMAGE_ATOMIC_AND_V2_V2_vi = 5001,
5017
    IMAGE_ATOMIC_AND_V2_V3_si = 5002,
5018
    IMAGE_ATOMIC_AND_V2_V3_vi = 5003,
5019
    IMAGE_ATOMIC_AND_V2_V4_si = 5004,
5020
    IMAGE_ATOMIC_AND_V2_V4_vi = 5005,
5021
    IMAGE_ATOMIC_CMPSWAP_V1_V1_si = 5006,
5022
    IMAGE_ATOMIC_CMPSWAP_V1_V1_vi = 5007,
5023
    IMAGE_ATOMIC_CMPSWAP_V1_V2_si = 5008,
5024
    IMAGE_ATOMIC_CMPSWAP_V1_V2_vi = 5009,
5025
    IMAGE_ATOMIC_CMPSWAP_V1_V3_si = 5010,
5026
    IMAGE_ATOMIC_CMPSWAP_V1_V3_vi = 5011,
5027
    IMAGE_ATOMIC_CMPSWAP_V1_V4_si = 5012,
5028
    IMAGE_ATOMIC_CMPSWAP_V1_V4_vi = 5013,
5029
    IMAGE_ATOMIC_CMPSWAP_V2_V1_si = 5014,
5030
    IMAGE_ATOMIC_CMPSWAP_V2_V1_vi = 5015,
5031
    IMAGE_ATOMIC_CMPSWAP_V2_V2_si = 5016,
5032
    IMAGE_ATOMIC_CMPSWAP_V2_V2_vi = 5017,
5033
    IMAGE_ATOMIC_CMPSWAP_V2_V3_si = 5018,
5034
    IMAGE_ATOMIC_CMPSWAP_V2_V3_vi = 5019,
5035
    IMAGE_ATOMIC_CMPSWAP_V2_V4_si = 5020,
5036
    IMAGE_ATOMIC_CMPSWAP_V2_V4_vi = 5021,
5037
    IMAGE_ATOMIC_DEC_V1_V1_si = 5022,
5038
    IMAGE_ATOMIC_DEC_V1_V1_vi = 5023,
5039
    IMAGE_ATOMIC_DEC_V1_V2_si = 5024,
5040
    IMAGE_ATOMIC_DEC_V1_V2_vi = 5025,
5041
    IMAGE_ATOMIC_DEC_V1_V3_si = 5026,
5042
    IMAGE_ATOMIC_DEC_V1_V3_vi = 5027,
5043
    IMAGE_ATOMIC_DEC_V1_V4_si = 5028,
5044
    IMAGE_ATOMIC_DEC_V1_V4_vi = 5029,
5045
    IMAGE_ATOMIC_DEC_V2_V1_si = 5030,
5046
    IMAGE_ATOMIC_DEC_V2_V1_vi = 5031,
5047
    IMAGE_ATOMIC_DEC_V2_V2_si = 5032,
5048
    IMAGE_ATOMIC_DEC_V2_V2_vi = 5033,
5049
    IMAGE_ATOMIC_DEC_V2_V3_si = 5034,
5050
    IMAGE_ATOMIC_DEC_V2_V3_vi = 5035,
5051
    IMAGE_ATOMIC_DEC_V2_V4_si = 5036,
5052
    IMAGE_ATOMIC_DEC_V2_V4_vi = 5037,
5053
    IMAGE_ATOMIC_INC_V1_V1_si = 5038,
5054
    IMAGE_ATOMIC_INC_V1_V1_vi = 5039,
5055
    IMAGE_ATOMIC_INC_V1_V2_si = 5040,
5056
    IMAGE_ATOMIC_INC_V1_V2_vi = 5041,
5057
    IMAGE_ATOMIC_INC_V1_V3_si = 5042,
5058
    IMAGE_ATOMIC_INC_V1_V3_vi = 5043,
5059
    IMAGE_ATOMIC_INC_V1_V4_si = 5044,
5060
    IMAGE_ATOMIC_INC_V1_V4_vi = 5045,
5061
    IMAGE_ATOMIC_INC_V2_V1_si = 5046,
5062
    IMAGE_ATOMIC_INC_V2_V1_vi = 5047,
5063
    IMAGE_ATOMIC_INC_V2_V2_si = 5048,
5064
    IMAGE_ATOMIC_INC_V2_V2_vi = 5049,
5065
    IMAGE_ATOMIC_INC_V2_V3_si = 5050,
5066
    IMAGE_ATOMIC_INC_V2_V3_vi = 5051,
5067
    IMAGE_ATOMIC_INC_V2_V4_si = 5052,
5068
    IMAGE_ATOMIC_INC_V2_V4_vi = 5053,
5069
    IMAGE_ATOMIC_OR_V1_V1_si  = 5054,
5070
    IMAGE_ATOMIC_OR_V1_V1_vi  = 5055,
5071
    IMAGE_ATOMIC_OR_V1_V2_si  = 5056,
5072
    IMAGE_ATOMIC_OR_V1_V2_vi  = 5057,
5073
    IMAGE_ATOMIC_OR_V1_V3_si  = 5058,
5074
    IMAGE_ATOMIC_OR_V1_V3_vi  = 5059,
5075
    IMAGE_ATOMIC_OR_V1_V4_si  = 5060,
5076
    IMAGE_ATOMIC_OR_V1_V4_vi  = 5061,
5077
    IMAGE_ATOMIC_OR_V2_V1_si  = 5062,
5078
    IMAGE_ATOMIC_OR_V2_V1_vi  = 5063,
5079
    IMAGE_ATOMIC_OR_V2_V2_si  = 5064,
5080
    IMAGE_ATOMIC_OR_V2_V2_vi  = 5065,
5081
    IMAGE_ATOMIC_OR_V2_V3_si  = 5066,
5082
    IMAGE_ATOMIC_OR_V2_V3_vi  = 5067,
5083
    IMAGE_ATOMIC_OR_V2_V4_si  = 5068,
5084
    IMAGE_ATOMIC_OR_V2_V4_vi  = 5069,
5085
    IMAGE_ATOMIC_SMAX_V1_V1_si  = 5070,
5086
    IMAGE_ATOMIC_SMAX_V1_V1_vi  = 5071,
5087
    IMAGE_ATOMIC_SMAX_V1_V2_si  = 5072,
5088
    IMAGE_ATOMIC_SMAX_V1_V2_vi  = 5073,
5089
    IMAGE_ATOMIC_SMAX_V1_V3_si  = 5074,
5090
    IMAGE_ATOMIC_SMAX_V1_V3_vi  = 5075,
5091
    IMAGE_ATOMIC_SMAX_V1_V4_si  = 5076,
5092
    IMAGE_ATOMIC_SMAX_V1_V4_vi  = 5077,
5093
    IMAGE_ATOMIC_SMAX_V2_V1_si  = 5078,
5094
    IMAGE_ATOMIC_SMAX_V2_V1_vi  = 5079,
5095
    IMAGE_ATOMIC_SMAX_V2_V2_si  = 5080,
5096
    IMAGE_ATOMIC_SMAX_V2_V2_vi  = 5081,
5097
    IMAGE_ATOMIC_SMAX_V2_V3_si  = 5082,
5098
    IMAGE_ATOMIC_SMAX_V2_V3_vi  = 5083,
5099
    IMAGE_ATOMIC_SMAX_V2_V4_si  = 5084,
5100
    IMAGE_ATOMIC_SMAX_V2_V4_vi  = 5085,
5101
    IMAGE_ATOMIC_SMIN_V1_V1_si  = 5086,
5102
    IMAGE_ATOMIC_SMIN_V1_V1_vi  = 5087,
5103
    IMAGE_ATOMIC_SMIN_V1_V2_si  = 5088,
5104
    IMAGE_ATOMIC_SMIN_V1_V2_vi  = 5089,
5105
    IMAGE_ATOMIC_SMIN_V1_V3_si  = 5090,
5106
    IMAGE_ATOMIC_SMIN_V1_V3_vi  = 5091,
5107
    IMAGE_ATOMIC_SMIN_V1_V4_si  = 5092,
5108
    IMAGE_ATOMIC_SMIN_V1_V4_vi  = 5093,
5109
    IMAGE_ATOMIC_SMIN_V2_V1_si  = 5094,
5110
    IMAGE_ATOMIC_SMIN_V2_V1_vi  = 5095,
5111
    IMAGE_ATOMIC_SMIN_V2_V2_si  = 5096,
5112
    IMAGE_ATOMIC_SMIN_V2_V2_vi  = 5097,
5113
    IMAGE_ATOMIC_SMIN_V2_V3_si  = 5098,
5114
    IMAGE_ATOMIC_SMIN_V2_V3_vi  = 5099,
5115
    IMAGE_ATOMIC_SMIN_V2_V4_si  = 5100,
5116
    IMAGE_ATOMIC_SMIN_V2_V4_vi  = 5101,
5117
    IMAGE_ATOMIC_SUB_V1_V1_si = 5102,
5118
    IMAGE_ATOMIC_SUB_V1_V1_vi = 5103,
5119
    IMAGE_ATOMIC_SUB_V1_V2_si = 5104,
5120
    IMAGE_ATOMIC_SUB_V1_V2_vi = 5105,
5121
    IMAGE_ATOMIC_SUB_V1_V3_si = 5106,
5122
    IMAGE_ATOMIC_SUB_V1_V3_vi = 5107,
5123
    IMAGE_ATOMIC_SUB_V1_V4_si = 5108,
5124
    IMAGE_ATOMIC_SUB_V1_V4_vi = 5109,
5125
    IMAGE_ATOMIC_SUB_V2_V1_si = 5110,
5126
    IMAGE_ATOMIC_SUB_V2_V1_vi = 5111,
5127
    IMAGE_ATOMIC_SUB_V2_V2_si = 5112,
5128
    IMAGE_ATOMIC_SUB_V2_V2_vi = 5113,
5129
    IMAGE_ATOMIC_SUB_V2_V3_si = 5114,
5130
    IMAGE_ATOMIC_SUB_V2_V3_vi = 5115,
5131
    IMAGE_ATOMIC_SUB_V2_V4_si = 5116,
5132
    IMAGE_ATOMIC_SUB_V2_V4_vi = 5117,
5133
    IMAGE_ATOMIC_SWAP_V1_V1_si  = 5118,
5134
    IMAGE_ATOMIC_SWAP_V1_V1_vi  = 5119,
5135
    IMAGE_ATOMIC_SWAP_V1_V2_si  = 5120,
5136
    IMAGE_ATOMIC_SWAP_V1_V2_vi  = 5121,
5137
    IMAGE_ATOMIC_SWAP_V1_V3_si  = 5122,
5138
    IMAGE_ATOMIC_SWAP_V1_V3_vi  = 5123,
5139
    IMAGE_ATOMIC_SWAP_V1_V4_si  = 5124,
5140
    IMAGE_ATOMIC_SWAP_V1_V4_vi  = 5125,
5141
    IMAGE_ATOMIC_SWAP_V2_V1_si  = 5126,
5142
    IMAGE_ATOMIC_SWAP_V2_V1_vi  = 5127,
5143
    IMAGE_ATOMIC_SWAP_V2_V2_si  = 5128,
5144
    IMAGE_ATOMIC_SWAP_V2_V2_vi  = 5129,
5145
    IMAGE_ATOMIC_SWAP_V2_V3_si  = 5130,
5146
    IMAGE_ATOMIC_SWAP_V2_V3_vi  = 5131,
5147
    IMAGE_ATOMIC_SWAP_V2_V4_si  = 5132,
5148
    IMAGE_ATOMIC_SWAP_V2_V4_vi  = 5133,
5149
    IMAGE_ATOMIC_UMAX_V1_V1_si  = 5134,
5150
    IMAGE_ATOMIC_UMAX_V1_V1_vi  = 5135,
5151
    IMAGE_ATOMIC_UMAX_V1_V2_si  = 5136,
5152
    IMAGE_ATOMIC_UMAX_V1_V2_vi  = 5137,
5153
    IMAGE_ATOMIC_UMAX_V1_V3_si  = 5138,
5154
    IMAGE_ATOMIC_UMAX_V1_V3_vi  = 5139,
5155
    IMAGE_ATOMIC_UMAX_V1_V4_si  = 5140,
5156
    IMAGE_ATOMIC_UMAX_V1_V4_vi  = 5141,
5157
    IMAGE_ATOMIC_UMAX_V2_V1_si  = 5142,
5158
    IMAGE_ATOMIC_UMAX_V2_V1_vi  = 5143,
5159
    IMAGE_ATOMIC_UMAX_V2_V2_si  = 5144,
5160
    IMAGE_ATOMIC_UMAX_V2_V2_vi  = 5145,
5161
    IMAGE_ATOMIC_UMAX_V2_V3_si  = 5146,
5162
    IMAGE_ATOMIC_UMAX_V2_V3_vi  = 5147,
5163
    IMAGE_ATOMIC_UMAX_V2_V4_si  = 5148,
5164
    IMAGE_ATOMIC_UMAX_V2_V4_vi  = 5149,
5165
    IMAGE_ATOMIC_UMIN_V1_V1_si  = 5150,
5166
    IMAGE_ATOMIC_UMIN_V1_V1_vi  = 5151,
5167
    IMAGE_ATOMIC_UMIN_V1_V2_si  = 5152,
5168
    IMAGE_ATOMIC_UMIN_V1_V2_vi  = 5153,
5169
    IMAGE_ATOMIC_UMIN_V1_V3_si  = 5154,
5170
    IMAGE_ATOMIC_UMIN_V1_V3_vi  = 5155,
5171
    IMAGE_ATOMIC_UMIN_V1_V4_si  = 5156,
5172
    IMAGE_ATOMIC_UMIN_V1_V4_vi  = 5157,
5173
    IMAGE_ATOMIC_UMIN_V2_V1_si  = 5158,
5174
    IMAGE_ATOMIC_UMIN_V2_V1_vi  = 5159,
5175
    IMAGE_ATOMIC_UMIN_V2_V2_si  = 5160,
5176
    IMAGE_ATOMIC_UMIN_V2_V2_vi  = 5161,
5177
    IMAGE_ATOMIC_UMIN_V2_V3_si  = 5162,
5178
    IMAGE_ATOMIC_UMIN_V2_V3_vi  = 5163,
5179
    IMAGE_ATOMIC_UMIN_V2_V4_si  = 5164,
5180
    IMAGE_ATOMIC_UMIN_V2_V4_vi  = 5165,
5181
    IMAGE_ATOMIC_XOR_V1_V1_si = 5166,
5182
    IMAGE_ATOMIC_XOR_V1_V1_vi = 5167,
5183
    IMAGE_ATOMIC_XOR_V1_V2_si = 5168,
5184
    IMAGE_ATOMIC_XOR_V1_V2_vi = 5169,
5185
    IMAGE_ATOMIC_XOR_V1_V3_si = 5170,
5186
    IMAGE_ATOMIC_XOR_V1_V3_vi = 5171,
5187
    IMAGE_ATOMIC_XOR_V1_V4_si = 5172,
5188
    IMAGE_ATOMIC_XOR_V1_V4_vi = 5173,
5189
    IMAGE_ATOMIC_XOR_V2_V1_si = 5174,
5190
    IMAGE_ATOMIC_XOR_V2_V1_vi = 5175,
5191
    IMAGE_ATOMIC_XOR_V2_V2_si = 5176,
5192
    IMAGE_ATOMIC_XOR_V2_V2_vi = 5177,
5193
    IMAGE_ATOMIC_XOR_V2_V3_si = 5178,
5194
    IMAGE_ATOMIC_XOR_V2_V3_vi = 5179,
5195
    IMAGE_ATOMIC_XOR_V2_V4_si = 5180,
5196
    IMAGE_ATOMIC_XOR_V2_V4_vi = 5181,
5197
    IMAGE_GATHER4_B_CL_O_V2_V3  = 5182,
5198
    IMAGE_GATHER4_B_CL_O_V2_V4  = 5183,
5199
    IMAGE_GATHER4_B_CL_O_V2_V8  = 5184,
5200
    IMAGE_GATHER4_B_CL_O_V4_V3  = 5185,
5201
    IMAGE_GATHER4_B_CL_O_V4_V4  = 5186,
5202
    IMAGE_GATHER4_B_CL_O_V4_V8  = 5187,
5203
    IMAGE_GATHER4_B_CL_V2_V2  = 5188,
5204
    IMAGE_GATHER4_B_CL_V2_V3  = 5189,
5205
    IMAGE_GATHER4_B_CL_V2_V4  = 5190,
5206
    IMAGE_GATHER4_B_CL_V2_V8  = 5191,
5207
    IMAGE_GATHER4_B_CL_V4_V2  = 5192,
5208
    IMAGE_GATHER4_B_CL_V4_V3  = 5193,
5209
    IMAGE_GATHER4_B_CL_V4_V4  = 5194,
5210
    IMAGE_GATHER4_B_CL_V4_V8  = 5195,
5211
    IMAGE_GATHER4_B_O_V2_V3 = 5196,
5212
    IMAGE_GATHER4_B_O_V2_V4 = 5197,
5213
    IMAGE_GATHER4_B_O_V2_V8 = 5198,
5214
    IMAGE_GATHER4_B_O_V4_V3 = 5199,
5215
    IMAGE_GATHER4_B_O_V4_V4 = 5200,
5216
    IMAGE_GATHER4_B_O_V4_V8 = 5201,
5217
    IMAGE_GATHER4_B_V2_V2 = 5202,
5218
    IMAGE_GATHER4_B_V2_V3 = 5203,
5219
    IMAGE_GATHER4_B_V2_V4 = 5204,
5220
    IMAGE_GATHER4_B_V4_V2 = 5205,
5221
    IMAGE_GATHER4_B_V4_V3 = 5206,
5222
    IMAGE_GATHER4_B_V4_V4 = 5207,
5223
    IMAGE_GATHER4_CL_O_V2_V2  = 5208,
5224
    IMAGE_GATHER4_CL_O_V2_V3  = 5209,
5225
    IMAGE_GATHER4_CL_O_V2_V4  = 5210,
5226
    IMAGE_GATHER4_CL_O_V2_V8  = 5211,
5227
    IMAGE_GATHER4_CL_O_V4_V2  = 5212,
5228
    IMAGE_GATHER4_CL_O_V4_V3  = 5213,
5229
    IMAGE_GATHER4_CL_O_V4_V4  = 5214,
5230
    IMAGE_GATHER4_CL_O_V4_V8  = 5215,
5231
    IMAGE_GATHER4_CL_V2_V1  = 5216,
5232
    IMAGE_GATHER4_CL_V2_V2  = 5217,
5233
    IMAGE_GATHER4_CL_V2_V3  = 5218,
5234
    IMAGE_GATHER4_CL_V2_V4  = 5219,
5235
    IMAGE_GATHER4_CL_V4_V1  = 5220,
5236
    IMAGE_GATHER4_CL_V4_V2  = 5221,
5237
    IMAGE_GATHER4_CL_V4_V3  = 5222,
5238
    IMAGE_GATHER4_CL_V4_V4  = 5223,
5239
    IMAGE_GATHER4_C_B_CL_O_V2_V4  = 5224,
5240
    IMAGE_GATHER4_C_B_CL_O_V2_V8  = 5225,
5241
    IMAGE_GATHER4_C_B_CL_O_V4_V4  = 5226,
5242
    IMAGE_GATHER4_C_B_CL_O_V4_V8  = 5227,
5243
    IMAGE_GATHER4_C_B_CL_V2_V3  = 5228,
5244
    IMAGE_GATHER4_C_B_CL_V2_V4  = 5229,
5245
    IMAGE_GATHER4_C_B_CL_V2_V8  = 5230,
5246
    IMAGE_GATHER4_C_B_CL_V4_V3  = 5231,
5247
    IMAGE_GATHER4_C_B_CL_V4_V4  = 5232,
5248
    IMAGE_GATHER4_C_B_CL_V4_V8  = 5233,
5249
    IMAGE_GATHER4_C_B_O_V2_V4 = 5234,
5250
    IMAGE_GATHER4_C_B_O_V2_V8 = 5235,
5251
    IMAGE_GATHER4_C_B_O_V4_V4 = 5236,
5252
    IMAGE_GATHER4_C_B_O_V4_V8 = 5237,
5253
    IMAGE_GATHER4_C_B_V2_V3 = 5238,
5254
    IMAGE_GATHER4_C_B_V2_V4 = 5239,
5255
    IMAGE_GATHER4_C_B_V2_V8 = 5240,
5256
    IMAGE_GATHER4_C_B_V4_V3 = 5241,
5257
    IMAGE_GATHER4_C_B_V4_V4 = 5242,
5258
    IMAGE_GATHER4_C_B_V4_V8 = 5243,
5259
    IMAGE_GATHER4_C_CL_O_V2_V3  = 5244,
5260
    IMAGE_GATHER4_C_CL_O_V2_V4  = 5245,
5261
    IMAGE_GATHER4_C_CL_O_V2_V8  = 5246,
5262
    IMAGE_GATHER4_C_CL_O_V4_V3  = 5247,
5263
    IMAGE_GATHER4_C_CL_O_V4_V4  = 5248,
5264
    IMAGE_GATHER4_C_CL_O_V4_V8  = 5249,
5265
    IMAGE_GATHER4_C_CL_V2_V2  = 5250,
5266
    IMAGE_GATHER4_C_CL_V2_V3  = 5251,
5267
    IMAGE_GATHER4_C_CL_V2_V4  = 5252,
5268
    IMAGE_GATHER4_C_CL_V2_V8  = 5253,
5269
    IMAGE_GATHER4_C_CL_V4_V2  = 5254,
5270
    IMAGE_GATHER4_C_CL_V4_V3  = 5255,
5271
    IMAGE_GATHER4_C_CL_V4_V4  = 5256,
5272
    IMAGE_GATHER4_C_CL_V4_V8  = 5257,
5273
    IMAGE_GATHER4_C_LZ_O_V2_V3  = 5258,
5274
    IMAGE_GATHER4_C_LZ_O_V2_V4  = 5259,
5275
    IMAGE_GATHER4_C_LZ_O_V2_V8  = 5260,
5276
    IMAGE_GATHER4_C_LZ_O_V4_V3  = 5261,
5277
    IMAGE_GATHER4_C_LZ_O_V4_V4  = 5262,
5278
    IMAGE_GATHER4_C_LZ_O_V4_V8  = 5263,
5279
    IMAGE_GATHER4_C_LZ_V2_V2  = 5264,
5280
    IMAGE_GATHER4_C_LZ_V2_V3  = 5265,
5281
    IMAGE_GATHER4_C_LZ_V2_V4  = 5266,
5282
    IMAGE_GATHER4_C_LZ_V4_V2  = 5267,
5283
    IMAGE_GATHER4_C_LZ_V4_V3  = 5268,
5284
    IMAGE_GATHER4_C_LZ_V4_V4  = 5269,
5285
    IMAGE_GATHER4_C_L_O_V2_V3 = 5270,
5286
    IMAGE_GATHER4_C_L_O_V2_V4 = 5271,
5287
    IMAGE_GATHER4_C_L_O_V2_V8 = 5272,
5288
    IMAGE_GATHER4_C_L_O_V4_V3 = 5273,
5289
    IMAGE_GATHER4_C_L_O_V4_V4 = 5274,
5290
    IMAGE_GATHER4_C_L_O_V4_V8 = 5275,
5291
    IMAGE_GATHER4_C_L_V2_V2 = 5276,
5292
    IMAGE_GATHER4_C_L_V2_V3 = 5277,
5293
    IMAGE_GATHER4_C_L_V2_V4 = 5278,
5294
    IMAGE_GATHER4_C_L_V2_V8 = 5279,
5295
    IMAGE_GATHER4_C_L_V4_V2 = 5280,
5296
    IMAGE_GATHER4_C_L_V4_V3 = 5281,
5297
    IMAGE_GATHER4_C_L_V4_V4 = 5282,
5298
    IMAGE_GATHER4_C_L_V4_V8 = 5283,
5299
    IMAGE_GATHER4_C_O_V2_V3 = 5284,
5300
    IMAGE_GATHER4_C_O_V2_V4 = 5285,
5301
    IMAGE_GATHER4_C_O_V2_V8 = 5286,
5302
    IMAGE_GATHER4_C_O_V4_V3 = 5287,
5303
    IMAGE_GATHER4_C_O_V4_V4 = 5288,
5304
    IMAGE_GATHER4_C_O_V4_V8 = 5289,
5305
    IMAGE_GATHER4_C_V2_V2 = 5290,
5306
    IMAGE_GATHER4_C_V2_V3 = 5291,
5307
    IMAGE_GATHER4_C_V2_V4 = 5292,
5308
    IMAGE_GATHER4_C_V4_V2 = 5293,
5309
    IMAGE_GATHER4_C_V4_V3 = 5294,
5310
    IMAGE_GATHER4_C_V4_V4 = 5295,
5311
    IMAGE_GATHER4_LZ_O_V2_V2  = 5296,
5312
    IMAGE_GATHER4_LZ_O_V2_V3  = 5297,
5313
    IMAGE_GATHER4_LZ_O_V2_V4  = 5298,
5314
    IMAGE_GATHER4_LZ_O_V4_V2  = 5299,
5315
    IMAGE_GATHER4_LZ_O_V4_V3  = 5300,
5316
    IMAGE_GATHER4_LZ_O_V4_V4  = 5301,
5317
    IMAGE_GATHER4_LZ_V2_V1  = 5302,
5318
    IMAGE_GATHER4_LZ_V2_V2  = 5303,
5319
    IMAGE_GATHER4_LZ_V2_V3  = 5304,
5320
    IMAGE_GATHER4_LZ_V2_V4  = 5305,
5321
    IMAGE_GATHER4_LZ_V4_V1  = 5306,
5322
    IMAGE_GATHER4_LZ_V4_V2  = 5307,
5323
    IMAGE_GATHER4_LZ_V4_V3  = 5308,
5324
    IMAGE_GATHER4_LZ_V4_V4  = 5309,
5325
    IMAGE_GATHER4_L_O_V2_V2 = 5310,
5326
    IMAGE_GATHER4_L_O_V2_V3 = 5311,
5327
    IMAGE_GATHER4_L_O_V2_V4 = 5312,
5328
    IMAGE_GATHER4_L_O_V2_V8 = 5313,
5329
    IMAGE_GATHER4_L_O_V4_V2 = 5314,
5330
    IMAGE_GATHER4_L_O_V4_V3 = 5315,
5331
    IMAGE_GATHER4_L_O_V4_V4 = 5316,
5332
    IMAGE_GATHER4_L_O_V4_V8 = 5317,
5333
    IMAGE_GATHER4_L_V2_V1 = 5318,
5334
    IMAGE_GATHER4_L_V2_V2 = 5319,
5335
    IMAGE_GATHER4_L_V2_V3 = 5320,
5336
    IMAGE_GATHER4_L_V2_V4 = 5321,
5337
    IMAGE_GATHER4_L_V4_V1 = 5322,
5338
    IMAGE_GATHER4_L_V4_V2 = 5323,
5339
    IMAGE_GATHER4_L_V4_V3 = 5324,
5340
    IMAGE_GATHER4_L_V4_V4 = 5325,
5341
    IMAGE_GATHER4_O_V2_V2 = 5326,
5342
    IMAGE_GATHER4_O_V2_V3 = 5327,
5343
    IMAGE_GATHER4_O_V2_V4 = 5328,
5344
    IMAGE_GATHER4_O_V4_V2 = 5329,
5345
    IMAGE_GATHER4_O_V4_V3 = 5330,
5346
    IMAGE_GATHER4_O_V4_V4 = 5331,
5347
    IMAGE_GATHER4_V2_V1 = 5332,
5348
    IMAGE_GATHER4_V2_V2 = 5333,
5349
    IMAGE_GATHER4_V2_V3 = 5334,
5350
    IMAGE_GATHER4_V2_V4 = 5335,
5351
    IMAGE_GATHER4_V4_V1 = 5336,
5352
    IMAGE_GATHER4_V4_V2 = 5337,
5353
    IMAGE_GATHER4_V4_V3 = 5338,
5354
    IMAGE_GATHER4_V4_V4 = 5339,
5355
    IMAGE_GET_LOD_V1_V1 = 5340,
5356
    IMAGE_GET_LOD_V1_V2 = 5341,
5357
    IMAGE_GET_LOD_V1_V3 = 5342,
5358
    IMAGE_GET_LOD_V1_V4 = 5343,
5359
    IMAGE_GET_LOD_V2_V1 = 5344,
5360
    IMAGE_GET_LOD_V2_V2 = 5345,
5361
    IMAGE_GET_LOD_V2_V3 = 5346,
5362
    IMAGE_GET_LOD_V2_V4 = 5347,
5363
    IMAGE_GET_LOD_V3_V1 = 5348,
5364
    IMAGE_GET_LOD_V3_V2 = 5349,
5365
    IMAGE_GET_LOD_V3_V3 = 5350,
5366
    IMAGE_GET_LOD_V3_V4 = 5351,
5367
    IMAGE_GET_LOD_V4_V1 = 5352,
5368
    IMAGE_GET_LOD_V4_V2 = 5353,
5369
    IMAGE_GET_LOD_V4_V3 = 5354,
5370
    IMAGE_GET_LOD_V4_V4 = 5355,
5371
    IMAGE_GET_RESINFO_V1_V1 = 5356,
5372
    IMAGE_GET_RESINFO_V1_V2 = 5357,
5373
    IMAGE_GET_RESINFO_V1_V3 = 5358,
5374
    IMAGE_GET_RESINFO_V1_V4 = 5359,
5375
    IMAGE_GET_RESINFO_V2_V1 = 5360,
5376
    IMAGE_GET_RESINFO_V2_V2 = 5361,
5377
    IMAGE_GET_RESINFO_V2_V3 = 5362,
5378
    IMAGE_GET_RESINFO_V2_V4 = 5363,
5379
    IMAGE_GET_RESINFO_V3_V1 = 5364,
5380
    IMAGE_GET_RESINFO_V3_V2 = 5365,
5381
    IMAGE_GET_RESINFO_V3_V3 = 5366,
5382
    IMAGE_GET_RESINFO_V3_V4 = 5367,
5383
    IMAGE_GET_RESINFO_V4_V1 = 5368,
5384
    IMAGE_GET_RESINFO_V4_V2 = 5369,
5385
    IMAGE_GET_RESINFO_V4_V3 = 5370,
5386
    IMAGE_GET_RESINFO_V4_V4 = 5371,
5387
    IMAGE_LOAD_MIP_PCK_SGN_V1_V1  = 5372,
5388
    IMAGE_LOAD_MIP_PCK_SGN_V1_V2  = 5373,
5389
    IMAGE_LOAD_MIP_PCK_SGN_V1_V3  = 5374,
5390
    IMAGE_LOAD_MIP_PCK_SGN_V1_V4  = 5375,
5391
    IMAGE_LOAD_MIP_PCK_SGN_V2_V1  = 5376,
5392
    IMAGE_LOAD_MIP_PCK_SGN_V2_V2  = 5377,
5393
    IMAGE_LOAD_MIP_PCK_SGN_V2_V3  = 5378,
5394
    IMAGE_LOAD_MIP_PCK_SGN_V2_V4  = 5379,
5395
    IMAGE_LOAD_MIP_PCK_SGN_V3_V1  = 5380,
5396
    IMAGE_LOAD_MIP_PCK_SGN_V3_V2  = 5381,
5397
    IMAGE_LOAD_MIP_PCK_SGN_V3_V3  = 5382,
5398
    IMAGE_LOAD_MIP_PCK_SGN_V3_V4  = 5383,
5399
    IMAGE_LOAD_MIP_PCK_SGN_V4_V1  = 5384,
5400
    IMAGE_LOAD_MIP_PCK_SGN_V4_V2  = 5385,
5401
    IMAGE_LOAD_MIP_PCK_SGN_V4_V3  = 5386,
5402
    IMAGE_LOAD_MIP_PCK_SGN_V4_V4  = 5387,
5403
    IMAGE_LOAD_MIP_PCK_V1_V1  = 5388,
5404
    IMAGE_LOAD_MIP_PCK_V1_V2  = 5389,
5405
    IMAGE_LOAD_MIP_PCK_V1_V3  = 5390,
5406
    IMAGE_LOAD_MIP_PCK_V1_V4  = 5391,
5407
    IMAGE_LOAD_MIP_PCK_V2_V1  = 5392,
5408
    IMAGE_LOAD_MIP_PCK_V2_V2  = 5393,
5409
    IMAGE_LOAD_MIP_PCK_V2_V3  = 5394,
5410
    IMAGE_LOAD_MIP_PCK_V2_V4  = 5395,
5411
    IMAGE_LOAD_MIP_PCK_V3_V1  = 5396,
5412
    IMAGE_LOAD_MIP_PCK_V3_V2  = 5397,
5413
    IMAGE_LOAD_MIP_PCK_V3_V3  = 5398,
5414
    IMAGE_LOAD_MIP_PCK_V3_V4  = 5399,
5415
    IMAGE_LOAD_MIP_PCK_V4_V1  = 5400,
5416
    IMAGE_LOAD_MIP_PCK_V4_V2  = 5401,
5417
    IMAGE_LOAD_MIP_PCK_V4_V3  = 5402,
5418
    IMAGE_LOAD_MIP_PCK_V4_V4  = 5403,
5419
    IMAGE_LOAD_MIP_V1_V1  = 5404,
5420
    IMAGE_LOAD_MIP_V1_V2  = 5405,
5421
    IMAGE_LOAD_MIP_V1_V3  = 5406,
5422
    IMAGE_LOAD_MIP_V1_V4  = 5407,
5423
    IMAGE_LOAD_MIP_V2_V1  = 5408,
5424
    IMAGE_LOAD_MIP_V2_V2  = 5409,
5425
    IMAGE_LOAD_MIP_V2_V3  = 5410,
5426
    IMAGE_LOAD_MIP_V2_V4  = 5411,
5427
    IMAGE_LOAD_MIP_V3_V1  = 5412,
5428
    IMAGE_LOAD_MIP_V3_V2  = 5413,
5429
    IMAGE_LOAD_MIP_V3_V3  = 5414,
5430
    IMAGE_LOAD_MIP_V3_V4  = 5415,
5431
    IMAGE_LOAD_MIP_V4_V1  = 5416,
5432
    IMAGE_LOAD_MIP_V4_V2  = 5417,
5433
    IMAGE_LOAD_MIP_V4_V3  = 5418,
5434
    IMAGE_LOAD_MIP_V4_V4  = 5419,
5435
    IMAGE_LOAD_PCK_SGN_V1_V1  = 5420,
5436
    IMAGE_LOAD_PCK_SGN_V1_V2  = 5421,
5437
    IMAGE_LOAD_PCK_SGN_V1_V3  = 5422,
5438
    IMAGE_LOAD_PCK_SGN_V1_V4  = 5423,
5439
    IMAGE_LOAD_PCK_SGN_V2_V1  = 5424,
5440
    IMAGE_LOAD_PCK_SGN_V2_V2  = 5425,
5441
    IMAGE_LOAD_PCK_SGN_V2_V3  = 5426,
5442
    IMAGE_LOAD_PCK_SGN_V2_V4  = 5427,
5443
    IMAGE_LOAD_PCK_SGN_V3_V1  = 5428,
5444
    IMAGE_LOAD_PCK_SGN_V3_V2  = 5429,
5445
    IMAGE_LOAD_PCK_SGN_V3_V3  = 5430,
5446
    IMAGE_LOAD_PCK_SGN_V3_V4  = 5431,
5447
    IMAGE_LOAD_PCK_SGN_V4_V1  = 5432,
5448
    IMAGE_LOAD_PCK_SGN_V4_V2  = 5433,
5449
    IMAGE_LOAD_PCK_SGN_V4_V3  = 5434,
5450
    IMAGE_LOAD_PCK_SGN_V4_V4  = 5435,
5451
    IMAGE_LOAD_PCK_V1_V1  = 5436,
5452
    IMAGE_LOAD_PCK_V1_V2  = 5437,
5453
    IMAGE_LOAD_PCK_V1_V3  = 5438,
5454
    IMAGE_LOAD_PCK_V1_V4  = 5439,
5455
    IMAGE_LOAD_PCK_V2_V1  = 5440,
5456
    IMAGE_LOAD_PCK_V2_V2  = 5441,
5457
    IMAGE_LOAD_PCK_V2_V3  = 5442,
5458
    IMAGE_LOAD_PCK_V2_V4  = 5443,
5459
    IMAGE_LOAD_PCK_V3_V1  = 5444,
5460
    IMAGE_LOAD_PCK_V3_V2  = 5445,
5461
    IMAGE_LOAD_PCK_V3_V3  = 5446,
5462
    IMAGE_LOAD_PCK_V3_V4  = 5447,
5463
    IMAGE_LOAD_PCK_V4_V1  = 5448,
5464
    IMAGE_LOAD_PCK_V4_V2  = 5449,
5465
    IMAGE_LOAD_PCK_V4_V3  = 5450,
5466
    IMAGE_LOAD_PCK_V4_V4  = 5451,
5467
    IMAGE_LOAD_V1_V1  = 5452,
5468
    IMAGE_LOAD_V1_V2  = 5453,
5469
    IMAGE_LOAD_V1_V3  = 5454,
5470
    IMAGE_LOAD_V1_V4  = 5455,
5471
    IMAGE_LOAD_V2_V1  = 5456,
5472
    IMAGE_LOAD_V2_V2  = 5457,
5473
    IMAGE_LOAD_V2_V3  = 5458,
5474
    IMAGE_LOAD_V2_V4  = 5459,
5475
    IMAGE_LOAD_V3_V1  = 5460,
5476
    IMAGE_LOAD_V3_V2  = 5461,
5477
    IMAGE_LOAD_V3_V3  = 5462,
5478
    IMAGE_LOAD_V3_V4  = 5463,
5479
    IMAGE_LOAD_V4_V1  = 5464,
5480
    IMAGE_LOAD_V4_V2  = 5465,
5481
    IMAGE_LOAD_V4_V3  = 5466,
5482
    IMAGE_LOAD_V4_V4  = 5467,
5483
    IMAGE_SAMPLE_B_CL_O_V1_V3 = 5468,
5484
    IMAGE_SAMPLE_B_CL_O_V1_V4 = 5469,
5485
    IMAGE_SAMPLE_B_CL_O_V1_V8 = 5470,
5486
    IMAGE_SAMPLE_B_CL_O_V2_V3 = 5471,
5487
    IMAGE_SAMPLE_B_CL_O_V2_V4 = 5472,
5488
    IMAGE_SAMPLE_B_CL_O_V2_V8 = 5473,
5489
    IMAGE_SAMPLE_B_CL_O_V3_V3 = 5474,
5490
    IMAGE_SAMPLE_B_CL_O_V3_V4 = 5475,
5491
    IMAGE_SAMPLE_B_CL_O_V3_V8 = 5476,
5492
    IMAGE_SAMPLE_B_CL_O_V4_V3 = 5477,
5493
    IMAGE_SAMPLE_B_CL_O_V4_V4 = 5478,
5494
    IMAGE_SAMPLE_B_CL_O_V4_V8 = 5479,
5495
    IMAGE_SAMPLE_B_CL_V1_V2 = 5480,
5496
    IMAGE_SAMPLE_B_CL_V1_V3 = 5481,
5497
    IMAGE_SAMPLE_B_CL_V1_V4 = 5482,
5498
    IMAGE_SAMPLE_B_CL_V1_V8 = 5483,
5499
    IMAGE_SAMPLE_B_CL_V2_V2 = 5484,
5500
    IMAGE_SAMPLE_B_CL_V2_V3 = 5485,
5501
    IMAGE_SAMPLE_B_CL_V2_V4 = 5486,
5502
    IMAGE_SAMPLE_B_CL_V2_V8 = 5487,
5503
    IMAGE_SAMPLE_B_CL_V3_V2 = 5488,
5504
    IMAGE_SAMPLE_B_CL_V3_V3 = 5489,
5505
    IMAGE_SAMPLE_B_CL_V3_V4 = 5490,
5506
    IMAGE_SAMPLE_B_CL_V3_V8 = 5491,
5507
    IMAGE_SAMPLE_B_CL_V4_V2 = 5492,
5508
    IMAGE_SAMPLE_B_CL_V4_V3 = 5493,
5509
    IMAGE_SAMPLE_B_CL_V4_V4 = 5494,
5510
    IMAGE_SAMPLE_B_CL_V4_V8 = 5495,
5511
    IMAGE_SAMPLE_B_O_V1_V3  = 5496,
5512
    IMAGE_SAMPLE_B_O_V1_V4  = 5497,
5513
    IMAGE_SAMPLE_B_O_V1_V8  = 5498,
5514
    IMAGE_SAMPLE_B_O_V2_V3  = 5499,
5515
    IMAGE_SAMPLE_B_O_V2_V4  = 5500,
5516
    IMAGE_SAMPLE_B_O_V2_V8  = 5501,
5517
    IMAGE_SAMPLE_B_O_V3_V3  = 5502,
5518
    IMAGE_SAMPLE_B_O_V3_V4  = 5503,
5519
    IMAGE_SAMPLE_B_O_V3_V8  = 5504,
5520
    IMAGE_SAMPLE_B_O_V4_V3  = 5505,
5521
    IMAGE_SAMPLE_B_O_V4_V4  = 5506,
5522
    IMAGE_SAMPLE_B_O_V4_V8  = 5507,
5523
    IMAGE_SAMPLE_B_V1_V2  = 5508,
5524
    IMAGE_SAMPLE_B_V1_V3  = 5509,
5525
    IMAGE_SAMPLE_B_V1_V4  = 5510,
5526
    IMAGE_SAMPLE_B_V2_V2  = 5511,
5527
    IMAGE_SAMPLE_B_V2_V3  = 5512,
5528
    IMAGE_SAMPLE_B_V2_V4  = 5513,
5529
    IMAGE_SAMPLE_B_V3_V2  = 5514,
5530
    IMAGE_SAMPLE_B_V3_V3  = 5515,
5531
    IMAGE_SAMPLE_B_V3_V4  = 5516,
5532
    IMAGE_SAMPLE_B_V4_V2  = 5517,
5533
    IMAGE_SAMPLE_B_V4_V3  = 5518,
5534
    IMAGE_SAMPLE_B_V4_V4  = 5519,
5535
    IMAGE_SAMPLE_CD_CL_O_V1_V16 = 5520,
5536
    IMAGE_SAMPLE_CD_CL_O_V1_V3  = 5521,
5537
    IMAGE_SAMPLE_CD_CL_O_V1_V4  = 5522,
5538
    IMAGE_SAMPLE_CD_CL_O_V1_V8  = 5523,
5539
    IMAGE_SAMPLE_CD_CL_O_V2_V16 = 5524,
5540
    IMAGE_SAMPLE_CD_CL_O_V2_V3  = 5525,
5541
    IMAGE_SAMPLE_CD_CL_O_V2_V4  = 5526,
5542
    IMAGE_SAMPLE_CD_CL_O_V2_V8  = 5527,
5543
    IMAGE_SAMPLE_CD_CL_O_V3_V16 = 5528,
5544
    IMAGE_SAMPLE_CD_CL_O_V3_V3  = 5529,
5545
    IMAGE_SAMPLE_CD_CL_O_V3_V4  = 5530,
5546
    IMAGE_SAMPLE_CD_CL_O_V3_V8  = 5531,
5547
    IMAGE_SAMPLE_CD_CL_O_V4_V16 = 5532,
5548
    IMAGE_SAMPLE_CD_CL_O_V4_V3  = 5533,
5549
    IMAGE_SAMPLE_CD_CL_O_V4_V4  = 5534,
5550
    IMAGE_SAMPLE_CD_CL_O_V4_V8  = 5535,
5551
    IMAGE_SAMPLE_CD_CL_V1_V16 = 5536,
5552
    IMAGE_SAMPLE_CD_CL_V1_V2  = 5537,
5553
    IMAGE_SAMPLE_CD_CL_V1_V3  = 5538,
5554
    IMAGE_SAMPLE_CD_CL_V1_V4  = 5539,
5555
    IMAGE_SAMPLE_CD_CL_V1_V8  = 5540,
5556
    IMAGE_SAMPLE_CD_CL_V2_V16 = 5541,
5557
    IMAGE_SAMPLE_CD_CL_V2_V2  = 5542,
5558
    IMAGE_SAMPLE_CD_CL_V2_V3  = 5543,
5559
    IMAGE_SAMPLE_CD_CL_V2_V4  = 5544,
5560
    IMAGE_SAMPLE_CD_CL_V2_V8  = 5545,
5561
    IMAGE_SAMPLE_CD_CL_V3_V16 = 5546,
5562
    IMAGE_SAMPLE_CD_CL_V3_V2  = 5547,
5563
    IMAGE_SAMPLE_CD_CL_V3_V3  = 5548,
5564
    IMAGE_SAMPLE_CD_CL_V3_V4  = 5549,
5565
    IMAGE_SAMPLE_CD_CL_V3_V8  = 5550,
5566
    IMAGE_SAMPLE_CD_CL_V4_V16 = 5551,
5567
    IMAGE_SAMPLE_CD_CL_V4_V2  = 5552,
5568
    IMAGE_SAMPLE_CD_CL_V4_V3  = 5553,
5569
    IMAGE_SAMPLE_CD_CL_V4_V4  = 5554,
5570
    IMAGE_SAMPLE_CD_CL_V4_V8  = 5555,
5571
    IMAGE_SAMPLE_CD_O_V1_V16  = 5556,
5572
    IMAGE_SAMPLE_CD_O_V1_V3 = 5557,
5573
    IMAGE_SAMPLE_CD_O_V1_V4 = 5558,
5574
    IMAGE_SAMPLE_CD_O_V1_V8 = 5559,
5575
    IMAGE_SAMPLE_CD_O_V2_V16  = 5560,
5576
    IMAGE_SAMPLE_CD_O_V2_V3 = 5561,
5577
    IMAGE_SAMPLE_CD_O_V2_V4 = 5562,
5578
    IMAGE_SAMPLE_CD_O_V2_V8 = 5563,
5579
    IMAGE_SAMPLE_CD_O_V3_V16  = 5564,
5580
    IMAGE_SAMPLE_CD_O_V3_V3 = 5565,
5581
    IMAGE_SAMPLE_CD_O_V3_V4 = 5566,
5582
    IMAGE_SAMPLE_CD_O_V3_V8 = 5567,
5583
    IMAGE_SAMPLE_CD_O_V4_V16  = 5568,
5584
    IMAGE_SAMPLE_CD_O_V4_V3 = 5569,
5585
    IMAGE_SAMPLE_CD_O_V4_V4 = 5570,
5586
    IMAGE_SAMPLE_CD_O_V4_V8 = 5571,
5587
    IMAGE_SAMPLE_CD_V1_V16  = 5572,
5588
    IMAGE_SAMPLE_CD_V1_V2 = 5573,
5589
    IMAGE_SAMPLE_CD_V1_V3 = 5574,
5590
    IMAGE_SAMPLE_CD_V1_V4 = 5575,
5591
    IMAGE_SAMPLE_CD_V1_V8 = 5576,
5592
    IMAGE_SAMPLE_CD_V2_V16  = 5577,
5593
    IMAGE_SAMPLE_CD_V2_V2 = 5578,
5594
    IMAGE_SAMPLE_CD_V2_V3 = 5579,
5595
    IMAGE_SAMPLE_CD_V2_V4 = 5580,
5596
    IMAGE_SAMPLE_CD_V2_V8 = 5581,
5597
    IMAGE_SAMPLE_CD_V3_V16  = 5582,
5598
    IMAGE_SAMPLE_CD_V3_V2 = 5583,
5599
    IMAGE_SAMPLE_CD_V3_V3 = 5584,
5600
    IMAGE_SAMPLE_CD_V3_V4 = 5585,
5601
    IMAGE_SAMPLE_CD_V3_V8 = 5586,
5602
    IMAGE_SAMPLE_CD_V4_V16  = 5587,
5603
    IMAGE_SAMPLE_CD_V4_V2 = 5588,
5604
    IMAGE_SAMPLE_CD_V4_V3 = 5589,
5605
    IMAGE_SAMPLE_CD_V4_V4 = 5590,
5606
    IMAGE_SAMPLE_CD_V4_V8 = 5591,
5607
    IMAGE_SAMPLE_CL_O_V1_V2 = 5592,
5608
    IMAGE_SAMPLE_CL_O_V1_V3 = 5593,
5609
    IMAGE_SAMPLE_CL_O_V1_V4 = 5594,
5610
    IMAGE_SAMPLE_CL_O_V1_V8 = 5595,
5611