Coverage Report

Created: 2019-02-15 18:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc
Line
Count
Source
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Register Bank Source Fragments                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_REGBANK_DECLARATIONS
10
#undef GET_REGBANK_DECLARATIONS
11
namespace llvm {
12
namespace AMDGPU {
13
enum {
14
  SCCRegBankID,
15
  SGPRRegBankID,
16
  VCCRegBankID,
17
  VGPRRegBankID,
18
  NumRegisterBanks,
19
};
20
} // end namespace AMDGPU
21
} // end namespace llvm
22
#endif // GET_REGBANK_DECLARATIONS
23
24
#ifdef GET_TARGET_REGBANK_CLASS
25
#undef GET_TARGET_REGBANK_CLASS
26
private:
27
  static RegisterBank *RegBanks[];
28
29
protected:
30
  AMDGPUGenRegisterBankInfo();
31
32
#endif // GET_TARGET_REGBANK_CLASS
33
34
#ifdef GET_TARGET_REGBANK_IMPL
35
#undef GET_TARGET_REGBANK_IMPL
36
namespace llvm {
37
namespace AMDGPU {
38
const uint32_t SCCRegBankCoverageData[] = {
39
    // 0-31
40
    (1u << (AMDGPU::SCC_CLASSRegClassID - 0)) |
41
    0,
42
    // 32-63
43
    0,
44
};
45
const uint32_t SGPRRegBankCoverageData[] = {
46
    // 0-31
47
    (1u << (AMDGPU::SReg_32RegClassID - 0)) |
48
    (1u << (AMDGPU::SReg_32_XEXEC_HIRegClassID - 0)) |
49
    (1u << (AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID - 0)) |
50
    (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 0)) |
51
    (1u << (AMDGPU::SGPR_32RegClassID - 0)) |
52
    (1u << (AMDGPU::TTMP_32RegClassID - 0)) |
53
    (1u << (AMDGPU::M0_CLASSRegClassID - 0)) |
54
    (1u << (AMDGPU::SReg_32_XM0RegClassID - 0)) |
55
    (1u << (AMDGPU::SReg_64RegClassID - 0)) |
56
    (1u << (AMDGPU::VS_32RegClassID - 0)) |
57
    (1u << (AMDGPU::SReg_64_XEXECRegClassID - 0)) |
58
    (1u << (AMDGPU::SGPR_64RegClassID - 0)) |
59
    (1u << (AMDGPU::TTMP_64RegClassID - 0)) |
60
    (1u << (AMDGPU::SReg_128RegClassID - 0)) |
61
    (1u << (AMDGPU::VS_64RegClassID - 0)) |
62
    (1u << (AMDGPU::SGPR_128RegClassID - 0)) |
63
    (1u << (AMDGPU::TTMP_128RegClassID - 0)) |
64
    (1u << (AMDGPU::SReg_256RegClassID - 0)) |
65
    (1u << (AMDGPU::SGPR_256RegClassID - 0)) |
66
    (1u << (AMDGPU::TTMP_256RegClassID - 0)) |
67
    (1u << (AMDGPU::SReg_512RegClassID - 0)) |
68
    0,
69
    // 32-63
70
    (1u << (AMDGPU::SGPR_512RegClassID - 32)) |
71
    (1u << (AMDGPU::TTMP_512RegClassID - 32)) |
72
    0,
73
};
74
const uint32_t VCCRegBankCoverageData[] = {
75
    // 0-31
76
    (1u << (AMDGPU::SReg_64RegClassID - 0)) |
77
    (1u << (AMDGPU::VS_32RegClassID - 0)) |
78
    (1u << (AMDGPU::SReg_32RegClassID - 0)) |
79
    (1u << (AMDGPU::SReg_32_XEXEC_HIRegClassID - 0)) |
80
    (1u << (AMDGPU::SReg_32_XM0RegClassID - 0)) |
81
    (1u << (AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID - 0)) |
82
    (1u << (AMDGPU::SReg_64_XEXECRegClassID - 0)) |
83
    (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 0)) |
84
    (1u << (AMDGPU::SGPR_64RegClassID - 0)) |
85
    (1u << (AMDGPU::SGPR_32RegClassID - 0)) |
86
    (1u << (AMDGPU::TTMP_64RegClassID - 0)) |
87
    (1u << (AMDGPU::TTMP_32RegClassID - 0)) |
88
    0,
89
    // 32-63
90
    0,
91
};
92
const uint32_t VGPRRegBankCoverageData[] = {
93
    // 0-31
94
    (1u << (AMDGPU::VGPR_32RegClassID - 0)) |
95
    (1u << (AMDGPU::VReg_1RegClassID - 0)) |
96
    (1u << (AMDGPU::VReg_64RegClassID - 0)) |
97
    (1u << (AMDGPU::VS_32RegClassID - 0)) |
98
    (1u << (AMDGPU::VReg_96RegClassID - 0)) |
99
    (1u << (AMDGPU::VS_64RegClassID - 0)) |
100
    (1u << (AMDGPU::VReg_128RegClassID - 0)) |
101
    (1u << (AMDGPU::VReg_256RegClassID - 0)) |
102
    (1u << (AMDGPU::VReg_512RegClassID - 0)) |
103
    0,
104
    // 32-63
105
    0,
106
};
107
108
RegisterBank SCCRegBank(/* ID */ AMDGPU::SCCRegBankID, /* Name */ "SCC", /* Size */ 1, /* CoveredRegClasses */ SCCRegBankCoverageData, /* NumRegClasses */ 34);
109
RegisterBank SGPRRegBank(/* ID */ AMDGPU::SGPRRegBankID, /* Name */ "SGPR", /* Size */ 512, /* CoveredRegClasses */ SGPRRegBankCoverageData, /* NumRegClasses */ 34);
110
RegisterBank VCCRegBank(/* ID */ AMDGPU::VCCRegBankID, /* Name */ "VCC", /* Size */ 64, /* CoveredRegClasses */ VCCRegBankCoverageData, /* NumRegClasses */ 34);
111
RegisterBank VGPRRegBank(/* ID */ AMDGPU::VGPRRegBankID, /* Name */ "VGPR", /* Size */ 512, /* CoveredRegClasses */ VGPRRegBankCoverageData, /* NumRegClasses */ 34);
112
} // end namespace AMDGPU
113
114
RegisterBank *AMDGPUGenRegisterBankInfo::RegBanks[] = {
115
    &AMDGPU::SCCRegBank,
116
    &AMDGPU::SGPRRegBank,
117
    &AMDGPU::VCCRegBank,
118
    &AMDGPU::VGPRRegBank,
119
};
120
121
AMDGPUGenRegisterBankInfo::AMDGPUGenRegisterBankInfo()
122
2.90k
    : RegisterBankInfo(RegBanks, AMDGPU::NumRegisterBanks) {
123
2.90k
  // Assert that RegBank indices match their ID's
124
#ifndef NDEBUG
125
  unsigned Index = 0;
126
  for (const auto &RB : RegBanks)
127
    assert(Index++ == RB->getID() && "Index != ID");
128
#endif // NDEBUG
129
}
130
} // end namespace llvm
131
#endif // GET_TARGET_REGBANK_IMPL