Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Register Bank Source Fragments                                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGBANK_DECLARATIONS
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#undef GET_REGBANK_DECLARATIONS
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namespace llvm {
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namespace AMDGPU {
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enum {
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  SCCRegBankID,
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  SGPRRegBankID,
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  VGPRRegBankID,
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  NumRegisterBanks,
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};
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} // end namespace AMDGPU
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} // end namespace llvm
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#endif // GET_REGBANK_DECLARATIONS
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#ifdef GET_TARGET_REGBANK_CLASS
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#undef GET_TARGET_REGBANK_CLASS
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private:
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  static RegisterBank *RegBanks[];
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protected:
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  AMDGPUGenRegisterBankInfo();
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#endif // GET_TARGET_REGBANK_CLASS
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#ifdef GET_TARGET_REGBANK_IMPL
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#undef GET_TARGET_REGBANK_IMPL
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namespace llvm {
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namespace AMDGPU {
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const uint32_t SCCRegBankCoverageData[] = {
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    // 0-31
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    (1u << (AMDGPU::SCC_CLASSRegClassID - 0)) |
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    0,
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    // 32-63
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    0,
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};
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const uint32_t SGPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (AMDGPU::SReg_32RegClassID - 0)) |
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    (1u << (AMDGPU::SReg_32_XEXEC_HIRegClassID - 0)) |
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    (1u << (AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID - 0)) |
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    (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 0)) |
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    (1u << (AMDGPU::SGPR_32RegClassID - 0)) |
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    (1u << (AMDGPU::TTMP_32RegClassID - 0)) |
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    (1u << (AMDGPU::M0_CLASSRegClassID - 0)) |
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    (1u << (AMDGPU::SReg_32_XM0RegClassID - 0)) |
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    (1u << (AMDGPU::SReg_64RegClassID - 0)) |
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    (1u << (AMDGPU::VS_32RegClassID - 0)) |
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    (1u << (AMDGPU::SReg_64_XEXECRegClassID - 0)) |
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    (1u << (AMDGPU::SGPR_64RegClassID - 0)) |
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    (1u << (AMDGPU::TTMP_64RegClassID - 0)) |
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    (1u << (AMDGPU::SReg_128RegClassID - 0)) |
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    (1u << (AMDGPU::VS_64RegClassID - 0)) |
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    (1u << (AMDGPU::SGPR_128RegClassID - 0)) |
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    (1u << (AMDGPU::TTMP_128RegClassID - 0)) |
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    (1u << (AMDGPU::SReg_256RegClassID - 0)) |
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    (1u << (AMDGPU::SGPR_256RegClassID - 0)) |
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    (1u << (AMDGPU::TTMP_256RegClassID - 0)) |
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    (1u << (AMDGPU::SReg_512RegClassID - 0)) |
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    (1u << (AMDGPU::SGPR_512RegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (AMDGPU::TTMP_512RegClassID - 32)) |
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    0,
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};
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const uint32_t VGPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (AMDGPU::VGPR_32RegClassID - 0)) |
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    (1u << (AMDGPU::VReg_1RegClassID - 0)) |
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    (1u << (AMDGPU::VReg_64RegClassID - 0)) |
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    (1u << (AMDGPU::VS_32RegClassID - 0)) |
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    (1u << (AMDGPU::VReg_96RegClassID - 0)) |
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    (1u << (AMDGPU::VS_64RegClassID - 0)) |
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    (1u << (AMDGPU::VReg_128RegClassID - 0)) |
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    (1u << (AMDGPU::VReg_256RegClassID - 0)) |
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    (1u << (AMDGPU::VReg_512RegClassID - 0)) |
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    0,
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    // 32-63
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    0,
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};
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RegisterBank SCCRegBank(/* ID */ AMDGPU::SCCRegBankID, /* Name */ "SCC", /* Size */ 1, /* CoveredRegClasses */ SCCRegBankCoverageData, /* NumRegClasses */ 33);
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RegisterBank SGPRRegBank(/* ID */ AMDGPU::SGPRRegBankID, /* Name */ "SGPR", /* Size */ 512, /* CoveredRegClasses */ SGPRRegBankCoverageData, /* NumRegClasses */ 33);
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RegisterBank VGPRRegBank(/* ID */ AMDGPU::VGPRRegBankID, /* Name */ "VGPR", /* Size */ 512, /* CoveredRegClasses */ VGPRRegBankCoverageData, /* NumRegClasses */ 33);
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} // end namespace AMDGPU
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RegisterBank *AMDGPUGenRegisterBankInfo::RegBanks[] = {
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    &AMDGPU::SCCRegBank,
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    &AMDGPU::SGPRRegBank,
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    &AMDGPU::VGPRRegBank,
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};
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AMDGPUGenRegisterBankInfo::AMDGPUGenRegisterBankInfo()
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2.28k
    : RegisterBankInfo(RegBanks, AMDGPU::NumRegisterBanks) {
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2.28k
  // Assert that RegBank indices match their ID's
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#ifndef NDEBUG
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  unsigned Index = 0;
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  for (const auto &RB : RegBanks)
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    assert(Index++ == RB->getID() && "Index != ID");
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#endif // NDEBUG
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}
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} // end namespace llvm
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#endif // GET_TARGET_REGBANK_IMPL