Coverage Report

Created: 2019-02-15 18:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenSubtargetInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Subtarget Enumeration Source Fragment                                      *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_SUBTARGETINFO_ENUM
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#undef GET_SUBTARGETINFO_ENUM
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namespace llvm {
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namespace AMDGPU {
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enum {
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  Feature16BitInsts = 0,
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  FeatureAddNoCarryInsts = 1,
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  FeatureApertureRegs = 2,
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  FeatureAutoWaitcntBeforeBarrier = 3,
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  FeatureCIInsts = 4,
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  FeatureCodeObjectV3 = 5,
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  FeatureDLInsts = 6,
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  FeatureDPP = 7,
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  FeatureDX10Clamp = 8,
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  FeatureDebuggerEmitPrologue = 9,
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  FeatureDebuggerInsertNops = 10,
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  FeatureDisable = 11,
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  FeatureDot1Insts = 12,
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  FeatureDot2Insts = 13,
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  FeatureDumpCode = 14,
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  FeatureDumpCodeLower = 15,
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  FeatureEnableDS128 = 16,
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  FeatureEnableHugePrivateBuffer = 17,
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  FeatureEnableLoadStoreOpt = 18,
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  FeatureEnablePRTStrictNull = 19,
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  FeatureEnableSIScheduler = 20,
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  FeatureEnableUnsafeDSOffsetFolding = 21,
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  FeatureFMA = 22,
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  FeatureFP16Denormals = 23,
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  FeatureFP32Denormals = 24,
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  FeatureFP64 = 25,
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  FeatureFP64Denormals = 26,
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  FeatureFP64FP16Denormals = 27,
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  FeatureFPExceptions = 28,
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  FeatureFastFMAF32 = 29,
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  FeatureFlatAddressSpace = 30,
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  FeatureFlatForGlobal = 31,
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  FeatureFlatGlobalInsts = 32,
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  FeatureFlatInstOffsets = 33,
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  FeatureFlatScratchInsts = 34,
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  FeatureFmaMixInsts = 35,
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  FeatureGCN3Encoding = 36,
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  FeatureGFX9 = 37,
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  FeatureGFX9Insts = 38,
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  FeatureIntClamp = 39,
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  FeatureInv2PiInlineImm = 40,
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  FeatureLDSBankCount16 = 41,
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  FeatureLDSBankCount32 = 42,
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  FeatureLocalMemorySize0 = 43,
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  FeatureLocalMemorySize32768 = 44,
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  FeatureLocalMemorySize65536 = 45,
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  FeatureMIMG_R128 = 46,
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  FeatureMadMixInsts = 47,
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  FeatureMaxPrivateElementSize4 = 48,
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  FeatureMaxPrivateElementSize8 = 49,
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  FeatureMaxPrivateElementSize16 = 50,
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  FeatureMovrel = 51,
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  FeaturePromoteAlloca = 52,
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  FeatureR128A16 = 53,
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  FeatureSDWA = 54,
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  FeatureSDWAMac = 55,
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  FeatureSDWAOmod = 56,
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  FeatureSDWAOutModsVOPC = 57,
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  FeatureSDWAScalar = 58,
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  FeatureSDWASdst = 59,
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  FeatureSGPRInitBug = 60,
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  FeatureSMemRealTime = 61,
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  FeatureSRAMECC = 62,
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  FeatureScalarAtomics = 63,
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  FeatureScalarStores = 64,
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  FeatureSeaIslands = 65,
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  FeatureSouthernIslands = 66,
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  FeatureTrapHandler = 67,
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  FeatureTrigReducedRange = 68,
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  FeatureUnalignedBufferAccess = 69,
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  FeatureUnalignedScratchAccess = 70,
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  FeatureUnpackedD16VMem = 71,
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  FeatureVGPRIndexMode = 72,
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  FeatureVIInsts = 73,
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  FeatureVOP3P = 74,
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  FeatureVolcanicIslands = 75,
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  FeatureWavefrontSize16 = 76,
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  FeatureWavefrontSize32 = 77,
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  FeatureWavefrontSize64 = 78,
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  FeatureXNACK = 79,
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  HalfRate64Ops = 80,
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};
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} // end namespace AMDGPU
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_ENUM
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#ifdef GET_SUBTARGETINFO_MC_DESC
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#undef GET_SUBTARGETINFO_MC_DESC
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namespace llvm {
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// Sorted (by key) array of values for CPU features.
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extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[] = {
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  { "16-bit-insts", "Has i16/f16 instructions", { AMDGPU::Feature16BitInsts }, { } },
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  { "DumpCode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCode }, { } },
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  { "GFX9", "GFX9 GPU generation", { AMDGPU::FeatureGFX9 }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN3Encoding, AMDGPU::FeatureCIInsts, AMDGPU::FeatureVIInsts, AMDGPU::Feature16BitInsts, AMDGPU::FeatureSMemRealTime, AMDGPU::FeatureScalarStores, AMDGPU::FeatureInv2PiInlineImm, AMDGPU::FeatureApertureRegs, AMDGPU::FeatureGFX9Insts, AMDGPU::FeatureVOP3P, AMDGPU::FeatureVGPRIndexMode, AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureDPP, AMDGPU::FeatureIntClamp, AMDGPU::FeatureSDWA, AMDGPU::FeatureSDWAOmod, AMDGPU::FeatureSDWAScalar, AMDGPU::FeatureSDWASdst, AMDGPU::FeatureFlatInstOffsets, AMDGPU::FeatureFlatGlobalInsts, AMDGPU::FeatureFlatScratchInsts, AMDGPU::FeatureAddNoCarryInsts, AMDGPU::FeatureScalarAtomics, AMDGPU::FeatureR128A16 } },
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  { "SEA_ISLANDS", "SEA_ISLANDS GPU generation", { AMDGPU::FeatureSeaIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureCIInsts, AMDGPU::FeatureMovrel, AMDGPU::FeatureTrigReducedRange } },
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  { "SOUTHERN_ISLANDS", "SOUTHERN_ISLANDS GPU generation", { AMDGPU::FeatureSouthernIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize32768, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureMovrel, AMDGPU::FeatureTrigReducedRange } },
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  { "VOLCANIC_ISLANDS", "VOLCANIC_ISLANDS GPU generation", { AMDGPU::FeatureVolcanicIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN3Encoding, AMDGPU::FeatureCIInsts, AMDGPU::FeatureVIInsts, AMDGPU::Feature16BitInsts, AMDGPU::FeatureSMemRealTime, AMDGPU::FeatureVGPRIndexMode, AMDGPU::FeatureMovrel, AMDGPU::FeatureScalarStores, AMDGPU::FeatureInv2PiInlineImm, AMDGPU::FeatureSDWA, AMDGPU::FeatureSDWAOutModsVOPC, AMDGPU::FeatureSDWAMac, AMDGPU::FeatureDPP, AMDGPU::FeatureIntClamp, AMDGPU::FeatureTrigReducedRange } },
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  { "add-no-carry-insts", "Have VALU add/sub instructions without carry out", { AMDGPU::FeatureAddNoCarryInsts }, { } },
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  { "amdgpu-debugger-emit-prologue", "Emit debugger prologue", { AMDGPU::FeatureDebuggerEmitPrologue }, { } },
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  { "amdgpu-debugger-insert-nops", "Insert one nop instruction for each high level source statement", { AMDGPU::FeatureDebuggerInsertNops }, { } },
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  { "aperture-regs", "Has Memory Aperture Base and Size Registers", { AMDGPU::FeatureApertureRegs }, { } },
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  { "auto-waitcnt-before-barrier", "Hardware automatically inserts waitcnt before barrier", { AMDGPU::FeatureAutoWaitcntBeforeBarrier }, { } },
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  { "ci-insts", "Additional instructions for CI+", { AMDGPU::FeatureCIInsts }, { } },
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  { "code-object-v3", "Generate code object version 3", { AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "dl-insts", "Has v_fmac_f32 and v_xnor_b32 instructions", { AMDGPU::FeatureDLInsts }, { } },
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  { "dot1-insts", "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions", { AMDGPU::FeatureDot1Insts }, { } },
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  { "dot2-insts", "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions", { AMDGPU::FeatureDot2Insts }, { } },
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  { "dpp", "Support DPP (Data Parallel Primitives) extension", { AMDGPU::FeatureDPP }, { } },
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  { "dumpcode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCodeLower }, { } },
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  { "dx10-clamp", "clamp modifier clamps NaNs to 0.0", { AMDGPU::FeatureDX10Clamp }, { } },
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  { "enable-ds128", "Use ds_{read|write}_b128", { AMDGPU::FeatureEnableDS128 }, { } },
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  { "enable-prt-strict-null", "Enable zeroing of result registers for sparse texture fetches", { AMDGPU::FeatureEnablePRTStrictNull }, { } },
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  { "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", { AMDGPU::FeatureFastFMAF32 }, { } },
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  { "flat-address-space", "Support flat address space", { AMDGPU::FeatureFlatAddressSpace }, { } },
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  { "flat-for-global", "Force to generate flat instruction for global", { AMDGPU::FeatureFlatForGlobal }, { } },
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  { "flat-global-insts", "Have global_* flat memory instructions", { AMDGPU::FeatureFlatGlobalInsts }, { } },
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  { "flat-inst-offsets", "Flat instructions have immediate offset addressing mode", { AMDGPU::FeatureFlatInstOffsets }, { } },
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  { "flat-scratch-insts", "Have scratch_* flat memory instructions", { AMDGPU::FeatureFlatScratchInsts }, { } },
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  { "fma-mix-insts", "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions", { AMDGPU::FeatureFmaMixInsts }, { } },
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  { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", { AMDGPU::FeatureFMA }, { } },
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  { "fp-exceptions", "Enable floating point exceptions", { AMDGPU::FeatureFPExceptions }, { } },
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  { "fp16-denormals", "Enable half precision denormal handling", { AMDGPU::FeatureFP16Denormals }, { AMDGPU::FeatureFP64FP16Denormals } },
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  { "fp32-denormals", "Enable single precision denormal handling", { AMDGPU::FeatureFP32Denormals }, { } },
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  { "fp64", "Enable double precision operations", { AMDGPU::FeatureFP64 }, { } },
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  { "fp64-denormals", "Enable double and half precision denormal handling", { AMDGPU::FeatureFP64Denormals }, { AMDGPU::FeatureFP64, AMDGPU::FeatureFP64FP16Denormals } },
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  { "fp64-fp16-denormals", "Enable double and half precision denormal handling", { AMDGPU::FeatureFP64FP16Denormals }, { AMDGPU::FeatureFP64 } },
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  { "gcn3-encoding", "Encoding format for VI", { AMDGPU::FeatureGCN3Encoding }, { } },
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  { "gfx9-insts", "Additional instructions for GFX9+", { AMDGPU::FeatureGFX9Insts }, { } },
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  { "half-rate-64-ops", "Most fp64 instructions are half rate instead of quarter", { AMDGPU::HalfRate64Ops }, { } },
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  { "huge-private-buffer", "Enable private/scratch buffer sizes greater than 128 GB", { AMDGPU::FeatureEnableHugePrivateBuffer }, { } },
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  { "int-clamp-insts", "Support clamp for integer destination", { AMDGPU::FeatureIntClamp }, { } },
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  { "inv-2pi-inline-imm", "Has 1 / (2 * pi) as inline immediate", { AMDGPU::FeatureInv2PiInlineImm }, { } },
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  { "ldsbankcount16", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount16 }, { } },
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  { "ldsbankcount32", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount32 }, { } },
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  { "load-store-opt", "Enable SI load/store optimizer pass", { AMDGPU::FeatureEnableLoadStoreOpt }, { } },
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  { "localmemorysize0", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize0 }, { } },
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  { "localmemorysize32768", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize32768 }, { } },
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  { "localmemorysize65536", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize65536 }, { } },
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  { "mad-mix-insts", "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", { AMDGPU::FeatureMadMixInsts }, { } },
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  { "max-private-element-size-16", "Maximum private access size may be 16", { AMDGPU::FeatureMaxPrivateElementSize16 }, { } },
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  { "max-private-element-size-4", "Maximum private access size may be 4", { AMDGPU::FeatureMaxPrivateElementSize4 }, { } },
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  { "max-private-element-size-8", "Maximum private access size may be 8", { AMDGPU::FeatureMaxPrivateElementSize8 }, { } },
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  { "mimg-r128", "Support 128-bit texture resources", { AMDGPU::FeatureMIMG_R128 }, { } },
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  { "movrel", "Has v_movrel*_b32 instructions", { AMDGPU::FeatureMovrel }, { } },
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  { "promote-alloca", "Enable promote alloca pass", { AMDGPU::FeaturePromoteAlloca }, { } },
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  { "r128-a16", "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9", { AMDGPU::FeatureR128A16 }, { } },
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  { "s-memrealtime", "Has s_memrealtime instruction", { AMDGPU::FeatureSMemRealTime }, { } },
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  { "scalar-atomics", "Has atomic scalar memory instructions", { AMDGPU::FeatureScalarAtomics }, { } },
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  { "scalar-stores", "Has store scalar memory instructions", { AMDGPU::FeatureScalarStores }, { } },
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  { "sdwa", "Support SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWA }, { } },
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  { "sdwa-mav", "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAMac }, { } },
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  { "sdwa-omod", "Support OMod with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAOmod }, { } },
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  { "sdwa-out-mods-vopc", "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAOutModsVOPC }, { } },
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  { "sdwa-scalar", "Support scalar register with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAScalar }, { } },
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  { "sdwa-sdst", "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWASdst }, { } },
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  { "sgpr-init-bug", "VI SGPR initialization bug requiring a fixed SGPR allocation size", { AMDGPU::FeatureSGPRInitBug }, { } },
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  { "si-scheduler", "Enable SI Machine Scheduler", { AMDGPU::FeatureEnableSIScheduler }, { } },
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  { "sram-ecc", "Enable SRAM ECC", { AMDGPU::FeatureSRAMECC }, { } },
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  { "trap-handler", "Trap handler support", { AMDGPU::FeatureTrapHandler }, { } },
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  { "trig-reduced-range", "Requires use of fract on arguments to trig instructions", { AMDGPU::FeatureTrigReducedRange }, { } },
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  { "unaligned-buffer-access", "Support unaligned global loads and stores", { AMDGPU::FeatureUnalignedBufferAccess }, { } },
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  { "unaligned-scratch-access", "Support unaligned scratch loads and stores", { AMDGPU::FeatureUnalignedScratchAccess }, { } },
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  { "unpacked-d16-vmem", "Has unpacked d16 vmem instructions", { AMDGPU::FeatureUnpackedD16VMem }, { } },
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  { "unsafe-ds-offset-folding", "Force using DS instruction immediate offsets on SI", { AMDGPU::FeatureEnableUnsafeDSOffsetFolding }, { } },
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  { "vgpr-index-mode", "Has VGPR mode register indexing", { AMDGPU::FeatureVGPRIndexMode }, { } },
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  { "vi-insts", "Additional instructions for VI+", { AMDGPU::FeatureVIInsts }, { } },
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  { "vop3p", "Has VOP3P packed instructions", { AMDGPU::FeatureVOP3P }, { } },
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  { "wavefrontsize16", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize16 }, { } },
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  { "wavefrontsize32", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize32 }, { } },
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  { "wavefrontsize64", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize64 }, { } },
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  { "xnack", "Enable XNACK support", { AMDGPU::FeatureXNACK }, { } },
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};
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// Sorted (by key) array of values for CPU subtype.
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extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[] = {
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  { "bonaire", "Select the bonaire processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "carrizo", "Select the carrizo processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "fiji", "Select the fiji processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "generic", "Select the generic processor", { AMDGPU::FeatureWavefrontSize64 }, { } },
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  { "gfx600", "Select the gfx600 processor", { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx601", "Select the gfx601 processor", { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx700", "Select the gfx700 processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx701", "Select the gfx701 processor", { AMDGPU::FeatureSeaIslands, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx702", "Select the gfx702 processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx703", "Select the gfx703 processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx704", "Select the gfx704 processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx801", "Select the gfx801 processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx802", "Select the gfx802 processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureSGPRInitBug, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx803", "Select the gfx803 processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx810", "Select the gfx810 processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureXNACK, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx900", "Select the gfx900 processor", { AMDGPU::FeatureGFX9, AMDGPU::FeatureMadMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx902", "Select the gfx902 processor", { AMDGPU::FeatureGFX9, AMDGPU::FeatureMadMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx904", "Select the gfx904 processor", { AMDGPU::FeatureGFX9, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureFmaMixInsts, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "gfx906", "Select the gfx906 processor", { AMDGPU::FeatureGFX9, AMDGPU::HalfRate64Ops, AMDGPU::FeatureFmaMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureDLInsts, AMDGPU::FeatureDot1Insts, AMDGPU::FeatureDot2Insts, AMDGPU::FeatureSRAMECC, AMDGPU::FeatureCodeObjectV3 }, { } },
213
  { "gfx909", "Select the gfx909 processor", { AMDGPU::FeatureGFX9, AMDGPU::FeatureMadMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "hainan", "Select the hainan processor", { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "hawaii", "Select the hawaii processor", { AMDGPU::FeatureSeaIslands, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "iceland", "Select the iceland processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureSGPRInitBug, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 }, { } },
217
  { "kabini", "Select the kabini processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "kaveri", "Select the kaveri processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "mullins", "Select the mullins processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureCodeObjectV3 }, { } },
220
  { "oland", "Select the oland processor", { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "pitcairn", "Select the pitcairn processor", { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "polaris10", "Select the polaris10 processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "polaris11", "Select the polaris11 processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "stoney", "Select the stoney processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureXNACK, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "tahiti", "Select the tahiti processor", { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "tonga", "Select the tonga processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureSGPRInitBug, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 }, { } },
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  { "verde", "Select the verde processor", { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 }, { } },
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};
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#ifdef DBGFIELD
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#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
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#endif
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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#define DBGFIELD(x) x,
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#else
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#define DBGFIELD(x)
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#endif
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// ===============================================================
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// Data tables for the new per-operand machine model.
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// {ProcResourceIdx, Cycles}
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extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[] = {
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  { 0,  0}, // Invalid
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  { 5,  1}, // #1
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  { 6,  1}, // #2
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  { 3,  1}, // #3
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  { 2,  1}, // #4
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  { 1,  1}, // #5
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  { 4,  1}, // #6
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  { 4,  1}, // #7
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  { 5,  1}, // #8
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  { 5,  2} // #9
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}; // AMDGPUWriteProcResTable
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// {Cycles, WriteResourceID}
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extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[] = {
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  { 0,  0}, // Invalid
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  { 1,  0}, // #1 Write32Bit_WriteSALU_WriteFloatFMA
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  {80,  0}, // #2 WriteVMEM
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  { 5,  0}, // #3 WriteLDS_WriteSMEM
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  { 4,  0}, // #4 WriteExport_WriteQuarterRate32_WriteDouble
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  { 8,  0}, // #5 WriteBranch_WriteDoubleAdd
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  { 1,  0}, // #6 Write32Bit_WriteFloatFMA
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  { 1,  0}, // #7 WriteSALU
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  { 2,  0}, // #8 Write64Bit_WriteDoubleAdd
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  {16,  0}, // #9 WriteFloatFMA_WriteDouble
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  {16,  0}, // #10 WriteFloatFMA_WriteDouble
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  { 1,  0}, // #11 WriteSALU
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  { 4,  0}, // #12 WriteQuarterRate32_WriteDouble
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  { 1,  0}, // #13 WriteSALU
272
  { 2,  0}, // #14 Write64Bit
273
  { 2,  0}, // #15 Write64Bit
274
  {500,  0} // #16 WriteBarrier
275
}; // AMDGPUWriteLatencyTable
276
277
// {UseIdx, WriteResourceID, Cycles}
278
extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[] = {
279
  {0,  0,  0}, // Invalid
280
}; // AMDGPUReadAdvanceTable
281
282
// {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
283
static const llvm::MCSchedClassDesc SIQuarterSpeedModelSchedClasses[] = {
284
  {DBGFIELD("InvalidSchedClass")  16383, false, false,  0, 0,  0, 0,  0, 0},
285
  {DBGFIELD("NullALU_Write32Bit") 1, false, false,  1, 1,  1, 1,  0, 0}, // #1
286
  {DBGFIELD("NullALU_WriteVMEM")  1, false, false,  2, 1,  2, 1,  0, 0}, // #2
287
  {DBGFIELD("NullALU_WriteLDS")   1, false, false,  3, 1,  3, 1,  0, 0}, // #3
288
  {DBGFIELD("NullALU_WriteExport") 1, false, false,  4, 1,  4, 1,  0, 0}, // #4
289
  {DBGFIELD("NullALU_WriteBranch") 1, false, false,  5, 1,  5, 1,  0, 0}, // #5
290
  {DBGFIELD("NullALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #6
291
  {DBGFIELD("NullALU_WriteSALU")  1, false, false,  6, 1,  1, 1,  0, 0}, // #7
292
  {DBGFIELD("NullALU_WriteSMEM")  1, false, false,  3, 1,  3, 1,  0, 0}, // #8
293
  {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false,  7, 2,  6, 2,  0, 0}, // #9
294
  {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false,  1, 1,  5, 1,  0, 0}, // #10
295
  {DBGFIELD("NullALU_Write64Bit") 1, false, false,  1, 1,  8, 1,  0, 0}, // #11
296
  {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false,  1, 1,  4, 1,  0, 0}, // #12
297
  {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false,  1, 1,  9, 1,  0, 0}, // #13
298
  {DBGFIELD("NullALU_WriteDouble") 1, false, false,  1, 1,  9, 1,  0, 0}, // #14
299
  {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false,  7, 2, 10, 2,  0, 0}, // #15
300
  {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false,  7, 2, 10, 2,  0, 0}, // #16
301
  {DBGFIELD("NullALU_WriteQuarterRate32_WriteSALU") 2, false, false,  7, 2, 12, 2,  0, 0}, // #17
302
  {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false,  9, 1, 14, 2,  0, 0}, // #18
303
  {DBGFIELD("NullALU_WriteBarrier") 1, false, false,  5, 1, 16, 1,  0, 0}, // #19
304
  {DBGFIELD("COPY")               16382, false, false,  0, 0,  0, 0,  0, 0}, // #20
305
  {DBGFIELD("Write32Bit")         1, false, false,  1, 1,  1, 1,  0, 0}, // #21
306
  {DBGFIELD("Write64Bit")         1, false, false,  1, 1,  8, 1,  0, 0}, // #22
307
  {DBGFIELD("WriteSALU")          1, false, false,  6, 1,  1, 1,  0, 0}, // #23
308
}; // SIQuarterSpeedModelSchedClasses
309
310
// {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
311
static const llvm::MCSchedClassDesc SIFullSpeedModelSchedClasses[] = {
312
  {DBGFIELD("InvalidSchedClass")  16383, false, false,  0, 0,  0, 0,  0, 0},
313
  {DBGFIELD("NullALU_Write32Bit") 1, false, false,  1, 1,  1, 1,  0, 0}, // #1
314
  {DBGFIELD("NullALU_WriteVMEM")  1, false, false,  2, 1,  2, 1,  0, 0}, // #2
315
  {DBGFIELD("NullALU_WriteLDS")   1, false, false,  3, 1,  3, 1,  0, 0}, // #3
316
  {DBGFIELD("NullALU_WriteExport") 1, false, false,  4, 1,  4, 1,  0, 0}, // #4
317
  {DBGFIELD("NullALU_WriteBranch") 1, false, false,  5, 1,  5, 1,  0, 0}, // #5
318
  {DBGFIELD("NullALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #6
319
  {DBGFIELD("NullALU_WriteSALU")  1, false, false,  6, 1,  1, 1,  0, 0}, // #7
320
  {DBGFIELD("NullALU_WriteSMEM")  1, false, false,  3, 1,  3, 1,  0, 0}, // #8
321
  {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false,  7, 2,  6, 2,  0, 0}, // #9
322
  {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false,  1, 1,  8, 1,  0, 0}, // #10
323
  {DBGFIELD("NullALU_Write64Bit") 1, false, false,  1, 1,  8, 1,  0, 0}, // #11
324
  {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false,  1, 1,  4, 1,  0, 0}, // #12
325
  {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false,  1, 1,  1, 1,  0, 0}, // #13
326
  {DBGFIELD("NullALU_WriteDouble") 1, false, false,  1, 1,  4, 1,  0, 0}, // #14
327
  {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false,  7, 2,  6, 2,  0, 0}, // #15
328
  {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false,  7, 2, 12, 2,  0, 0}, // #16
329
  {DBGFIELD("NullALU_WriteQuarterRate32_WriteSALU") 2, false, false,  7, 2, 12, 2,  0, 0}, // #17
330
  {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false,  9, 1, 14, 2,  0, 0}, // #18
331
  {DBGFIELD("NullALU_WriteBarrier") 1, false, false,  5, 1, 16, 1,  0, 0}, // #19
332
  {DBGFIELD("COPY")               16382, false, false,  0, 0,  0, 0,  0, 0}, // #20
333
  {DBGFIELD("Write32Bit")         1, false, false,  1, 1,  1, 1,  0, 0}, // #21
334
  {DBGFIELD("Write64Bit")         1, false, false,  1, 1,  8, 1,  0, 0}, // #22
335
  {DBGFIELD("WriteSALU")          1, false, false,  6, 1,  1, 1,  0, 0}, // #23
336
}; // SIFullSpeedModelSchedClasses
337
338
static const llvm::MCSchedModel NoSchedModel = {
339
  MCSchedModel::DefaultIssueWidth,
340
  MCSchedModel::DefaultMicroOpBufferSize,
341
  MCSchedModel::DefaultLoopMicroOpBufferSize,
342
  MCSchedModel::DefaultLoadLatency,
343
  MCSchedModel::DefaultHighLatency,
344
  MCSchedModel::DefaultMispredictPenalty,
345
  false, // PostRAScheduler
346
  false, // CompleteModel
347
  0, // Processor ID
348
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
349
  nullptr, // No Itinerary
350
  nullptr // No extra processor descriptor
351
};
352
353
static const unsigned SIQuarterSpeedModelProcResourceSubUnits[] = {
354
  0,  // Invalid
355
};
356
357
// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
358
static const llvm::MCProcResourceDesc SIQuarterSpeedModelProcResources[] = {
359
  {"InvalidUnit", 0, 0, 0, 0},
360
  {"HWBranch",        1, 0, 1, nullptr}, // #1
361
  {"HWExport",        1, 0, 7, nullptr}, // #2
362
  {"HWLGKM",          1, 0, 31, nullptr}, // #3
363
  {"HWSALU",          1, 0, 1, nullptr}, // #4
364
  {"HWVALU",          1, 0, 1, nullptr}, // #5
365
  {"HWVMEM",          1, 0, 15, nullptr}, // #6
366
};
367
368
static const llvm::MCSchedModel SIQuarterSpeedModel = {
369
  1, // IssueWidth
370
  1, // MicroOpBufferSize
371
  MCSchedModel::DefaultLoopMicroOpBufferSize,
372
  MCSchedModel::DefaultLoadLatency,
373
  MCSchedModel::DefaultHighLatency,
374
  20, // MispredictPenalty
375
  true, // PostRAScheduler
376
  false, // CompleteModel
377
  1, // Processor ID
378
  SIQuarterSpeedModelProcResources,
379
  SIQuarterSpeedModelSchedClasses,
380
  7,
381
  24,
382
  nullptr, // No Itinerary
383
  nullptr // No extra processor descriptor
384
};
385
386
static const unsigned SIFullSpeedModelProcResourceSubUnits[] = {
387
  0,  // Invalid
388
};
389
390
// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
391
static const llvm::MCProcResourceDesc SIFullSpeedModelProcResources[] = {
392
  {"InvalidUnit", 0, 0, 0, 0},
393
  {"HWBranch",        1, 0, 1, nullptr}, // #1
394
  {"HWExport",        1, 0, 7, nullptr}, // #2
395
  {"HWLGKM",          1, 0, 31, nullptr}, // #3
396
  {"HWSALU",          1, 0, 1, nullptr}, // #4
397
  {"HWVALU",          1, 0, 1, nullptr}, // #5
398
  {"HWVMEM",          1, 0, 15, nullptr}, // #6
399
};
400
401
static const llvm::MCSchedModel SIFullSpeedModel = {
402
  1, // IssueWidth
403
  1, // MicroOpBufferSize
404
  MCSchedModel::DefaultLoopMicroOpBufferSize,
405
  MCSchedModel::DefaultLoadLatency,
406
  MCSchedModel::DefaultHighLatency,
407
  20, // MispredictPenalty
408
  true, // PostRAScheduler
409
  false, // CompleteModel
410
  2, // Processor ID
411
  SIFullSpeedModelProcResources,
412
  SIFullSpeedModelSchedClasses,
413
  7,
414
  24,
415
  nullptr, // No Itinerary
416
  nullptr // No extra processor descriptor
417
};
418
419
// Sorted (by key) array of sched model for CPU subtype.
420
extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[] = {
421
  { "bonaire", (const void *)&SIQuarterSpeedModel },
422
  { "carrizo", (const void *)&SIQuarterSpeedModel },
423
  { "fiji", (const void *)&SIQuarterSpeedModel },
424
  { "generic", (const void *)&NoSchedModel },
425
  { "gfx600", (const void *)&SIFullSpeedModel },
426
  { "gfx601", (const void *)&SIQuarterSpeedModel },
427
  { "gfx700", (const void *)&SIQuarterSpeedModel },
428
  { "gfx701", (const void *)&SIFullSpeedModel },
429
  { "gfx702", (const void *)&SIQuarterSpeedModel },
430
  { "gfx703", (const void *)&SIQuarterSpeedModel },
431
  { "gfx704", (const void *)&SIQuarterSpeedModel },
432
  { "gfx801", (const void *)&SIQuarterSpeedModel },
433
  { "gfx802", (const void *)&SIQuarterSpeedModel },
434
  { "gfx803", (const void *)&SIQuarterSpeedModel },
435
  { "gfx810", (const void *)&SIQuarterSpeedModel },
436
  { "gfx900", (const void *)&SIQuarterSpeedModel },
437
  { "gfx902", (const void *)&SIQuarterSpeedModel },
438
  { "gfx904", (const void *)&SIQuarterSpeedModel },
439
  { "gfx906", (const void *)&SIQuarterSpeedModel },
440
  { "gfx909", (const void *)&SIQuarterSpeedModel },
441
  { "hainan", (const void *)&SIQuarterSpeedModel },
442
  { "hawaii", (const void *)&SIFullSpeedModel },
443
  { "iceland", (const void *)&SIQuarterSpeedModel },
444
  { "kabini", (const void *)&SIQuarterSpeedModel },
445
  { "kaveri", (const void *)&SIQuarterSpeedModel },
446
  { "mullins", (const void *)&SIQuarterSpeedModel },
447
  { "oland", (const void *)&SIQuarterSpeedModel },
448
  { "pitcairn", (const void *)&SIQuarterSpeedModel },
449
  { "polaris10", (const void *)&SIQuarterSpeedModel },
450
  { "polaris11", (const void *)&SIQuarterSpeedModel },
451
  { "stoney", (const void *)&SIQuarterSpeedModel },
452
  { "tahiti", (const void *)&SIFullSpeedModel },
453
  { "tonga", (const void *)&SIQuarterSpeedModel },
454
  { "verde", (const void *)&SIQuarterSpeedModel },
455
};
456
457
#undef DBGFIELD
458
namespace AMDGPU_MC {
459
unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
460
0
    const MCInst *MI, unsigned CPUID) {
461
0
  switch (SchedClass) {
462
0
  case 20: // COPY
463
0
    if (CPUID == 1) { // SIQuarterSpeedModel
464
0
      return 23; // WriteSALU
465
0
    }
466
0
    if (CPUID == 2) { // SIFullSpeedModel
467
0
      return 23; // WriteSALU
468
0
    }
469
0
    break;
470
0
  };
471
0
  // Don't know how to resolve this scheduling class.
472
0
  return 0;
473
0
}
474
} // end of namespace AMDGPU_MC
475
476
struct AMDGPUGenMCSubtargetInfo : public MCSubtargetInfo {
477
  AMDGPUGenMCSubtargetInfo(const Triple &TT, 
478
    StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
479
    ArrayRef<SubtargetFeatureKV> PD,
480
    const SubtargetInfoKV *ProcSched,
481
    const MCWriteProcResEntry *WPR,
482
    const MCWriteLatencyEntry *WL,
483
    const MCReadAdvanceEntry *RA, const InstrStage *IS,
484
    const unsigned *OC, const unsigned *FP) :
485
      MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
486
3.36k
                      WPR, WL, RA, IS, OC, FP) { }
487
488
  unsigned resolveVariantSchedClass(unsigned SchedClass,
489
0
      const MCInst *MI, unsigned CPUID) const override {
490
0
    return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 
491
0
  }
492
};
493
494
3.36k
static inline MCSubtargetInfo *createAMDGPUMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
495
3.36k
  return new AMDGPUGenMCSubtargetInfo(TT, CPU, FS, AMDGPUFeatureKV, AMDGPUSubTypeKV, 
496
3.36k
                      AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, 
497
3.36k
                      nullptr, nullptr, nullptr);
498
3.36k
}
499
500
} // end namespace llvm
501
502
#endif // GET_SUBTARGETINFO_MC_DESC
503
504
505
#ifdef GET_SUBTARGETINFO_TARGET_DESC
506
#undef GET_SUBTARGETINFO_TARGET_DESC
507
508
#include "llvm/Support/Debug.h"
509
#include "llvm/Support/raw_ostream.h"
510
511
// ParseSubtargetFeatures - Parses features string setting specified
512
// subtarget options.
513
2.90k
void llvm::AMDGPUSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
514
2.90k
  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
515
2.90k
  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
516
2.90k
  InitMCProcessorInfo(CPU, FS);
517
2.90k
  const FeatureBitset& Bits = getFeatureBits();
518
2.90k
  if (Bits[AMDGPU::Feature16BitInsts]) 
Has16BitInsts = true1.52k
;
519
2.90k
  if (Bits[AMDGPU::FeatureAddNoCarryInsts]) 
AddNoCarryInsts = true420
;
520
2.90k
  if (Bits[AMDGPU::FeatureApertureRegs]) 
HasApertureRegs = true420
;
521
2.90k
  if (Bits[AMDGPU::FeatureAutoWaitcntBeforeBarrier]) 
AutoWaitcntBeforeBarrier = true2
;
522
2.90k
  if (Bits[AMDGPU::FeatureCIInsts]) 
CIInsts = true1.78k
;
523
2.90k
  if (Bits[AMDGPU::FeatureCodeObjectV3]) 
CodeObjectV3 = true2.05k
;
524
2.90k
  if (Bits[AMDGPU::FeatureDLInsts]) 
HasDLInsts = true34
;
525
2.90k
  if (Bits[AMDGPU::FeatureDPP]) 
HasDPP = true1.52k
;
526
2.90k
  if (Bits[AMDGPU::FeatureDX10Clamp]) 
DX10Clamp = true2.90k
;
527
2.90k
  if (Bits[AMDGPU::FeatureDebuggerEmitPrologue]) 
DebuggerEmitPrologue = true4
;
528
2.90k
  if (Bits[AMDGPU::FeatureDebuggerInsertNops]) 
DebuggerInsertNops = true5
;
529
2.90k
  if (Bits[AMDGPU::FeatureDisable]) 
FeatureDisable = true0
;
530
2.90k
  if (Bits[AMDGPU::FeatureDot1Insts]) 
HasDot1Insts = true34
;
531
2.90k
  if (Bits[AMDGPU::FeatureDot2Insts]) 
HasDot2Insts = true34
;
532
2.90k
  if (Bits[AMDGPU::FeatureDumpCode]) 
DumpCode = true0
;
533
2.90k
  if (Bits[AMDGPU::FeatureDumpCodeLower]) 
DumpCode = true2
;
534
2.90k
  if (Bits[AMDGPU::FeatureEnableDS128]) 
EnableDS128 = true14
;
535
2.90k
  if (Bits[AMDGPU::FeatureEnableHugePrivateBuffer]) 
EnableHugePrivateBuffer = true1
;
536
2.90k
  if (Bits[AMDGPU::FeatureEnableLoadStoreOpt]) 
EnableLoadStoreOpt = true2.90k
;
537
2.90k
  if (Bits[AMDGPU::FeatureEnablePRTStrictNull]) 
EnablePRTStrictNull = true2.90k
;
538
2.90k
  if (Bits[AMDGPU::FeatureEnableSIScheduler]) 
EnableSIScheduler = true1
;
539
2.90k
  if (Bits[AMDGPU::FeatureEnableUnsafeDSOffsetFolding]) 
EnableUnsafeDSOffsetFolding = true1
;
540
2.90k
  if (Bits[AMDGPU::FeatureFMA]) 
FMA = true0
;
541
2.90k
  if (Bits[AMDGPU::FeatureFP16Denormals]) 
FP64FP16Denormals = true1
;
542
2.90k
  if (Bits[AMDGPU::FeatureFP32Denormals]) 
FP32Denormals = true62
;
543
2.90k
  if (Bits[AMDGPU::FeatureFP64]) FP64 = true;
544
2.90k
  if (Bits[AMDGPU::FeatureFP64Denormals]) 
FP64FP16Denormals = true2
;
545
2.90k
  if (Bits[AMDGPU::FeatureFP64FP16Denormals]) 
FP64FP16Denormals = true2.86k
;
546
2.90k
  if (Bits[AMDGPU::FeatureFPExceptions]) 
FPExceptions = true7
;
547
2.90k
  if (Bits[AMDGPU::FeatureFastFMAF32]) 
FastFMAF32 = true761
;
548
2.90k
  if (Bits[AMDGPU::FeatureFlatAddressSpace]) 
FlatAddressSpace = true1.97k
;
549
2.90k
  if (Bits[AMDGPU::FeatureFlatForGlobal]) 
FlatForGlobal = true524
;
550
2.90k
  if (Bits[AMDGPU::FeatureFlatGlobalInsts]) 
FlatGlobalInsts = true420
;
551
2.90k
  if (Bits[AMDGPU::FeatureFlatInstOffsets]) 
FlatInstOffsets = true420
;
552
2.90k
  if (Bits[AMDGPU::FeatureFlatScratchInsts]) 
FlatScratchInsts = true420
;
553
2.90k
  if (Bits[AMDGPU::FeatureFmaMixInsts]) 
HasFmaMixInsts = true39
;
554
2.90k
  if (Bits[AMDGPU::FeatureGCN3Encoding]) 
GCN3Encoding = true1.52k
;
555
2.90k
  if (Bits[AMDGPU::FeatureGFX9] && 
Gen < GCNSubtarget::GFX9420
)
Gen = GCNSubtarget::GFX9420
;
556
2.90k
  if (Bits[AMDGPU::FeatureGFX9Insts]) 
GFX9Insts = true420
;
557
2.90k
  if (Bits[AMDGPU::FeatureIntClamp]) 
HasIntClamp = true1.52k
;
558
2.90k
  if (Bits[AMDGPU::FeatureInv2PiInlineImm]) 
HasInv2PiInlineImm = true1.52k
;
559
2.90k
  if (Bits[AMDGPU::FeatureLDSBankCount16] && 
LDSBankCount < 1634
)
LDSBankCount = 1634
;
560
2.90k
  if (Bits[AMDGPU::FeatureLDSBankCount32] && 
LDSBankCount < 322.09k
)
LDSBankCount = 322.09k
;
561
2.90k
  if (Bits[AMDGPU::FeatureLocalMemorySize0] && 
LocalMemorySize < 00
)
LocalMemorySize = 00
;
562
2.90k
  if (Bits[AMDGPU::FeatureLocalMemorySize32768] && 
LocalMemorySize < 32768348
)
LocalMemorySize = 32768348
;
563
2.90k
  if (Bits[AMDGPU::FeatureLocalMemorySize65536] && 
LocalMemorySize < 655361.78k
)
LocalMemorySize = 655361.78k
;
564
2.90k
  if (Bits[AMDGPU::FeatureMIMG_R128]) 
MIMG_R128 = true1.71k
;
565
2.90k
  if (Bits[AMDGPU::FeatureMadMixInsts]) 
HasMadMixInsts = true381
;
566
2.90k
  if (Bits[AMDGPU::FeatureMaxPrivateElementSize4] && 
MaxPrivateElementSize < 46
)
MaxPrivateElementSize = 46
;
567
2.90k
  if (Bits[AMDGPU::FeatureMaxPrivateElementSize8] && 
MaxPrivateElementSize < 83
)
MaxPrivateElementSize = 83
;
568
2.90k
  if (Bits[AMDGPU::FeatureMaxPrivateElementSize16] && 
MaxPrivateElementSize < 1614
)
MaxPrivateElementSize = 1614
;
569
2.90k
  if (Bits[AMDGPU::FeatureMovrel]) 
HasMovrel = true1.71k
;
570
2.90k
  if (Bits[AMDGPU::FeaturePromoteAlloca]) 
EnablePromoteAlloca = true2.85k
;
571
2.90k
  if (Bits[AMDGPU::FeatureR128A16]) 
HasR128A16 = true420
;
572
2.90k
  if (Bits[AMDGPU::FeatureSDWA]) 
HasSDWA = true1.52k
;
573
2.90k
  if (Bits[AMDGPU::FeatureSDWAMac]) 
HasSDWAMac = true1.10k
;
574
2.90k
  if (Bits[AMDGPU::FeatureSDWAOmod]) 
HasSDWAOmod = true420
;
575
2.90k
  if (Bits[AMDGPU::FeatureSDWAOutModsVOPC]) 
HasSDWAOutModsVOPC = true1.10k
;
576
2.90k
  if (Bits[AMDGPU::FeatureSDWAScalar]) 
HasSDWAScalar = true420
;
577
2.90k
  if (Bits[AMDGPU::FeatureSDWASdst]) 
HasSDWASdst = true420
;
578
2.90k
  if (Bits[AMDGPU::FeatureSGPRInitBug]) 
SGPRInitBug = true487
;
579
2.90k
  if (Bits[AMDGPU::FeatureSMemRealTime]) 
HasSMemRealTime = true1.52k
;
580
2.90k
  if (Bits[AMDGPU::FeatureSRAMECC]) 
EnableSRAMECC = true35
;
581
2.90k
  if (Bits[AMDGPU::FeatureScalarAtomics]) 
HasScalarAtomics = true420
;
582
2.90k
  if (Bits[AMDGPU::FeatureScalarStores]) 
HasScalarStores = true1.52k
;
583
2.90k
  if (Bits[AMDGPU::FeatureSeaIslands] && 
Gen < GCNSubtarget::SEA_ISLANDS265
)
Gen = GCNSubtarget::SEA_ISLANDS265
;
584
2.90k
  if (Bits[AMDGPU::FeatureSouthernIslands] && 
Gen < GCNSubtarget::SOUTHERN_ISLANDS348
)
Gen = GCNSubtarget::SOUTHERN_ISLANDS0
;
585
2.90k
  if (Bits[AMDGPU::FeatureTrapHandler]) 
TrapHandler = true560
;
586
2.90k
  if (Bits[AMDGPU::FeatureTrigReducedRange]) 
HasTrigReducedRange = true1.71k
;
587
2.90k
  if (Bits[AMDGPU::FeatureUnalignedBufferAccess]) 
UnalignedBufferAccess = true559
;
588
2.90k
  if (Bits[AMDGPU::FeatureUnalignedScratchAccess]) 
UnalignedScratchAccess = true5
;
589
2.90k
  if (Bits[AMDGPU::FeatureUnpackedD16VMem]) 
HasUnpackedD16VMem = true1.07k
;
590
2.90k
  if (Bits[AMDGPU::FeatureVGPRIndexMode]) 
HasVGPRIndexMode = true1.52k
;
591
2.90k
  if (Bits[AMDGPU::FeatureVIInsts]) 
VIInsts = true1.52k
;
592
2.90k
  if (Bits[AMDGPU::FeatureVOP3P]) 
HasVOP3PInsts = true420
;
593
2.90k
  if (Bits[AMDGPU::FeatureVolcanicIslands] && 
Gen < GCNSubtarget::VOLCANIC_ISLANDS1.10k
)
Gen = GCNSubtarget::VOLCANIC_ISLANDS1.10k
;
594
2.90k
  if (Bits[AMDGPU::FeatureWavefrontSize16] && 
WavefrontSize < 160
)
WavefrontSize = 160
;
595
2.90k
  if (Bits[AMDGPU::FeatureWavefrontSize32] && 
WavefrontSize < 320
)
WavefrontSize = 320
;
596
2.90k
  if (Bits[AMDGPU::FeatureWavefrontSize64] && 
WavefrontSize < 642.88k
)
WavefrontSize = 642.88k
;
597
2.90k
  if (Bits[AMDGPU::FeatureXNACK]) 
EnableXNACK = true78
;
598
2.90k
  if (Bits[AMDGPU::HalfRate64Ops]) 
HalfRate64Ops = true378
;
599
2.90k
}
600
#endif // GET_SUBTARGETINFO_TARGET_DESC
601
602
603
#ifdef GET_SUBTARGETINFO_HEADER
604
#undef GET_SUBTARGETINFO_HEADER
605
606
namespace llvm {
607
class DFAPacketizer;
608
namespace AMDGPU_MC {
609
unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
610
}
611
612
struct AMDGPUGenSubtargetInfo : public TargetSubtargetInfo {
613
  explicit AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
614
public:
615
  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
616
  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
617
  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
618
};
619
} // end namespace llvm
620
621
#endif // GET_SUBTARGETINFO_HEADER
622
623
624
#ifdef GET_SUBTARGETINFO_CTOR
625
#undef GET_SUBTARGETINFO_CTOR
626
627
#include "llvm/CodeGen/TargetSchedule.h"
628
629
namespace llvm {
630
extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[];
631
extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[];
632
extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[];
633
extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[];
634
extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[];
635
extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[];
636
AMDGPUGenSubtargetInfo::AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
637
  : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(AMDGPUFeatureKV, 80), makeArrayRef(AMDGPUSubTypeKV, 34), 
638
                        AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, 
639
2.90k
                        nullptr, nullptr, nullptr) {}
640
641
unsigned AMDGPUGenSubtargetInfo
642
722k
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
643
722k
644
722k
  const SIInstrInfo *TII =
645
722k
    static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
646
722k
  (void)TII;
647
722k
648
722k
  switch (SchedClass) {
649
722k
  case 20: // COPY
650
722k
    if (SchedModel->getProcessorID() == 1) { // SIQuarterSpeedModel
651
631k
      if (TII->isVGPRCopy(*MI) && 
TII->getOpSize(*MI, 0) <= 32377k
)
652
377k
        return 21; // Write32Bit
653
254k
      if (TII->isVGPRCopy(*MI) && 
TII->getOpSize(*MI, 0) > 32197
)
654
197
        return 22; // Write64Bit
655
254k
      return 23; // WriteSALU
656
254k
    }
657
90.8k
    if (SchedModel->getProcessorID() == 2) { // SIFullSpeedModel
658
90.8k
      if (TII->isVGPRCopy(*MI) && 
TII->getOpSize(*MI, 0) <= 3252.5k
)
659
52.4k
        return 21; // Write32Bit
660
38.3k
      if (TII->isVGPRCopy(*MI) && 
TII->getOpSize(*MI, 0) > 3247
)
661
47
        return 22; // Write64Bit
662
38.3k
      return 23; // WriteSALU
663
38.3k
    }
664
0
    break;
665
0
  };
666
0
  report_fatal_error("Expected a variant SchedClass");
667
0
} // AMDGPUGenSubtargetInfo::resolveSchedClass
668
669
unsigned AMDGPUGenSubtargetInfo
670
0
::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
671
0
  return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
672
0
} // AMDGPUGenSubtargetInfo::resolveVariantSchedClass
673
674
} // end namespace llvm
675
676
#endif // GET_SUBTARGETINFO_CTOR
677
678
679
#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
680
#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
681
682
#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
683
684
685
#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
686
#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
687
688
#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
689