Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/AMDGPUGenSubtargetInfo.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Subtarget Enumeration Source Fragment                                      *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_SUBTARGETINFO_ENUM
11
#undef GET_SUBTARGETINFO_ENUM
12
13
namespace llvm {
14
namespace AMDGPU {
15
enum {
16
  Feature16BitInsts = 0,
17
  FeatureAddNoCarryInsts = 1,
18
  FeatureApertureRegs = 2,
19
  FeatureAutoWaitcntBeforeBarrier = 3,
20
  FeatureCIInsts = 4,
21
  FeatureCodeObjectV3 = 5,
22
  FeatureDLInsts = 6,
23
  FeatureDPP = 7,
24
  FeatureDX10Clamp = 8,
25
  FeatureDebuggerEmitPrologue = 9,
26
  FeatureDebuggerInsertNops = 10,
27
  FeatureDisable = 11,
28
  FeatureDumpCode = 12,
29
  FeatureDumpCodeLower = 13,
30
  FeatureEnableDS128 = 14,
31
  FeatureEnableHugePrivateBuffer = 15,
32
  FeatureEnableLoadStoreOpt = 16,
33
  FeatureEnableSIScheduler = 17,
34
  FeatureEnableUnsafeDSOffsetFolding = 18,
35
  FeatureFMA = 19,
36
  FeatureFP16Denormals = 20,
37
  FeatureFP32Denormals = 21,
38
  FeatureFP64 = 22,
39
  FeatureFP64Denormals = 23,
40
  FeatureFP64FP16Denormals = 24,
41
  FeatureFPExceptions = 25,
42
  FeatureFastFMAF32 = 26,
43
  FeatureFlatAddressSpace = 27,
44
  FeatureFlatForGlobal = 28,
45
  FeatureFlatGlobalInsts = 29,
46
  FeatureFlatInstOffsets = 30,
47
  FeatureFlatScratchInsts = 31,
48
  FeatureFmaMixInsts = 32,
49
  FeatureGCN = 33,
50
  FeatureGCN3Encoding = 34,
51
  FeatureGFX9 = 35,
52
  FeatureGFX9Insts = 36,
53
  FeatureISAVersion6_0_0 = 37,
54
  FeatureISAVersion6_0_1 = 38,
55
  FeatureISAVersion7_0_0 = 39,
56
  FeatureISAVersion7_0_1 = 40,
57
  FeatureISAVersion7_0_2 = 41,
58
  FeatureISAVersion7_0_3 = 42,
59
  FeatureISAVersion7_0_4 = 43,
60
  FeatureISAVersion8_0_1 = 44,
61
  FeatureISAVersion8_0_2 = 45,
62
  FeatureISAVersion8_0_3 = 46,
63
  FeatureISAVersion8_1_0 = 47,
64
  FeatureISAVersion9_0_0 = 48,
65
  FeatureISAVersion9_0_2 = 49,
66
  FeatureISAVersion9_0_4 = 50,
67
  FeatureISAVersion9_0_6 = 51,
68
  FeatureISAVersion9_0_9 = 52,
69
  FeatureIntClamp = 53,
70
  FeatureInv2PiInlineImm = 54,
71
  FeatureLDSBankCount16 = 55,
72
  FeatureLDSBankCount32 = 56,
73
  FeatureLocalMemorySize0 = 57,
74
  FeatureLocalMemorySize32768 = 58,
75
  FeatureLocalMemorySize65536 = 59,
76
  FeatureMIMG_R128 = 60,
77
  FeatureMadMixInsts = 61,
78
  FeatureMaxPrivateElementSize4 = 62,
79
  FeatureMaxPrivateElementSize8 = 63,
80
  FeatureMaxPrivateElementSize16 = 64,
81
  FeatureMovrel = 65,
82
  FeaturePromoteAlloca = 66,
83
  FeatureR128A16 = 67,
84
  FeatureSDWA = 68,
85
  FeatureSDWAMac = 69,
86
  FeatureSDWAOmod = 70,
87
  FeatureSDWAOutModsVOPC = 71,
88
  FeatureSDWAScalar = 72,
89
  FeatureSDWASdst = 73,
90
  FeatureSGPRInitBug = 74,
91
  FeatureSMemRealTime = 75,
92
  FeatureSRAMECC = 76,
93
  FeatureScalarAtomics = 77,
94
  FeatureScalarStores = 78,
95
  FeatureSeaIslands = 79,
96
  FeatureSouthernIslands = 80,
97
  FeatureTrapHandler = 81,
98
  FeatureTrigReducedRange = 82,
99
  FeatureUnalignedBufferAccess = 83,
100
  FeatureUnalignedScratchAccess = 84,
101
  FeatureUnpackedD16VMem = 85,
102
  FeatureVGPRIndexMode = 86,
103
  FeatureVIInsts = 87,
104
  FeatureVOP3P = 88,
105
  FeatureVolcanicIslands = 89,
106
  FeatureWavefrontSize16 = 90,
107
  FeatureWavefrontSize32 = 91,
108
  FeatureWavefrontSize64 = 92,
109
  FeatureXNACK = 93,
110
  HalfRate64Ops = 94,
111
};
112
} // end namespace AMDGPU
113
} // end namespace llvm
114
115
#endif // GET_SUBTARGETINFO_ENUM
116
117
118
#ifdef GET_SUBTARGETINFO_MC_DESC
119
#undef GET_SUBTARGETINFO_MC_DESC
120
121
namespace llvm {
122
// Sorted (by key) array of values for CPU features.
123
extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[] = {
124
  { "16-bit-insts", "Has i16/f16 instructions", { AMDGPU::Feature16BitInsts }, { } },
125
  { "DumpCode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCode }, { } },
126
  { "GFX9", "GFX9 GPU generation", { AMDGPU::FeatureGFX9 }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN, AMDGPU::FeatureGCN3Encoding, AMDGPU::FeatureCIInsts, AMDGPU::FeatureVIInsts, AMDGPU::Feature16BitInsts, AMDGPU::FeatureSMemRealTime, AMDGPU::FeatureScalarStores, AMDGPU::FeatureInv2PiInlineImm, AMDGPU::FeatureApertureRegs, AMDGPU::FeatureGFX9Insts, AMDGPU::FeatureVOP3P, AMDGPU::FeatureVGPRIndexMode, AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureDPP, AMDGPU::FeatureIntClamp, AMDGPU::FeatureSDWA, AMDGPU::FeatureSDWAOmod, AMDGPU::FeatureSDWAScalar, AMDGPU::FeatureSDWASdst, AMDGPU::FeatureFlatInstOffsets, AMDGPU::FeatureFlatGlobalInsts, AMDGPU::FeatureFlatScratchInsts, AMDGPU::FeatureAddNoCarryInsts, AMDGPU::FeatureScalarAtomics, AMDGPU::FeatureR128A16 } },
127
  { "SEA_ISLANDS", "SEA_ISLANDS GPU generation", { AMDGPU::FeatureSeaIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureGCN, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureCIInsts, AMDGPU::FeatureMovrel, AMDGPU::FeatureTrigReducedRange } },
128
  { "SOUTHERN_ISLANDS", "SOUTHERN_ISLANDS GPU generation", { AMDGPU::FeatureSouthernIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize32768, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureGCN, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureMovrel, AMDGPU::FeatureTrigReducedRange } },
129
  { "VOLCANIC_ISLANDS", "VOLCANIC_ISLANDS GPU generation", { AMDGPU::FeatureVolcanicIslands }, { AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureMIMG_R128, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN, AMDGPU::FeatureGCN3Encoding, AMDGPU::FeatureCIInsts, AMDGPU::FeatureVIInsts, AMDGPU::Feature16BitInsts, AMDGPU::FeatureSMemRealTime, AMDGPU::FeatureVGPRIndexMode, AMDGPU::FeatureMovrel, AMDGPU::FeatureScalarStores, AMDGPU::FeatureInv2PiInlineImm, AMDGPU::FeatureSDWA, AMDGPU::FeatureSDWAOutModsVOPC, AMDGPU::FeatureSDWAMac, AMDGPU::FeatureDPP, AMDGPU::FeatureIntClamp, AMDGPU::FeatureTrigReducedRange } },
130
  { "add-no-carry-insts", "Have VALU add/sub instructions without carry out", { AMDGPU::FeatureAddNoCarryInsts }, { } },
131
  { "amdgpu-debugger-emit-prologue", "Emit debugger prologue", { AMDGPU::FeatureDebuggerEmitPrologue }, { } },
132
  { "amdgpu-debugger-insert-nops", "Insert one nop instruction for each high level source statement", { AMDGPU::FeatureDebuggerInsertNops }, { } },
133
  { "aperture-regs", "Has Memory Aperture Base and Size Registers", { AMDGPU::FeatureApertureRegs }, { } },
134
  { "auto-waitcnt-before-barrier", "Hardware automatically inserts waitcnt before barrier", { AMDGPU::FeatureAutoWaitcntBeforeBarrier }, { } },
135
  { "ci-insts", "Additional instructions for CI+", { AMDGPU::FeatureCIInsts }, { } },
136
  { "code-object-v3", "Generate code object version 3", { AMDGPU::FeatureCodeObjectV3 }, { } },
137
  { "dl-insts", "Has deep learning instructions", { AMDGPU::FeatureDLInsts }, { } },
138
  { "dpp", "Support DPP (Data Parallel Primitives) extension", { AMDGPU::FeatureDPP }, { } },
139
  { "dumpcode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCodeLower }, { } },
140
  { "dx10-clamp", "clamp modifier clamps NaNs to 0.0", { AMDGPU::FeatureDX10Clamp }, { } },
141
  { "enable-ds128", "Use ds_{read|write}_b128", { AMDGPU::FeatureEnableDS128 }, { } },
142
  { "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", { AMDGPU::FeatureFastFMAF32 }, { } },
143
  { "flat-address-space", "Support flat address space", { AMDGPU::FeatureFlatAddressSpace }, { } },
144
  { "flat-for-global", "Force to generate flat instruction for global", { AMDGPU::FeatureFlatForGlobal }, { } },
145
  { "flat-global-insts", "Have global_* flat memory instructions", { AMDGPU::FeatureFlatGlobalInsts }, { } },
146
  { "flat-inst-offsets", "Flat instructions have immediate offset addressing mode", { AMDGPU::FeatureFlatInstOffsets }, { } },
147
  { "flat-scratch-insts", "Have scratch_* flat memory instructions", { AMDGPU::FeatureFlatScratchInsts }, { } },
148
  { "fma-mix-insts", "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions", { AMDGPU::FeatureFmaMixInsts }, { } },
149
  { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", { AMDGPU::FeatureFMA }, { } },
150
  { "fp-exceptions", "Enable floating point exceptions", { AMDGPU::FeatureFPExceptions }, { } },
151
  { "fp16-denormals", "Enable half precision denormal handling", { AMDGPU::FeatureFP16Denormals }, { AMDGPU::FeatureFP64FP16Denormals } },
152
  { "fp32-denormals", "Enable single precision denormal handling", { AMDGPU::FeatureFP32Denormals }, { } },
153
  { "fp64", "Enable double precision operations", { AMDGPU::FeatureFP64 }, { } },
154
  { "fp64-denormals", "Enable double and half precision denormal handling", { AMDGPU::FeatureFP64Denormals }, { AMDGPU::FeatureFP64, AMDGPU::FeatureFP64FP16Denormals } },
155
  { "fp64-fp16-denormals", "Enable double and half precision denormal handling", { AMDGPU::FeatureFP64FP16Denormals }, { AMDGPU::FeatureFP64 } },
156
  { "gcn", "GCN or newer GPU", { AMDGPU::FeatureGCN }, { } },
157
  { "gcn3-encoding", "Encoding format for VI", { AMDGPU::FeatureGCN3Encoding }, { } },
158
  { "gfx9-insts", "Additional instructions for GFX9+", { AMDGPU::FeatureGFX9Insts }, { } },
159
  { "half-rate-64-ops", "Most fp64 instructions are half rate instead of quarter", { AMDGPU::HalfRate64Ops }, { } },
160
  { "huge-private-buffer", "Enable private/scratch buffer sizes greater than 128 GB", { AMDGPU::FeatureEnableHugePrivateBuffer }, { } },
161
  { "int-clamp-insts", "Support clamp for integer destination", { AMDGPU::FeatureIntClamp }, { } },
162
  { "inv-2pi-inline-imm", "Has 1 / (2 * pi) as inline immediate", { AMDGPU::FeatureInv2PiInlineImm }, { } },
163
  { "isaver6.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion6_0_0 }, { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 } },
164
  { "isaver6.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion6_0_1 }, { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 } },
165
  { "isaver7.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_0 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 } },
166
  { "isaver7.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_1 }, { AMDGPU::FeatureSeaIslands, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureCodeObjectV3 } },
167
  { "isaver7.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_2 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureCodeObjectV3 } },
168
  { "isaver7.0.3", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_3 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureCodeObjectV3 } },
169
  { "isaver7.0.4", "Instruction set version number", { AMDGPU::FeatureISAVersion7_0_4 }, { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 } },
170
  { "isaver8.0.1", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_1 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 } },
171
  { "isaver8.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_2 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureSGPRInitBug, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 } },
172
  { "isaver8.0.3", "Instruction set version number", { AMDGPU::FeatureISAVersion8_0_3 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureUnpackedD16VMem, AMDGPU::FeatureCodeObjectV3 } },
173
  { "isaver8.1.0", "Instruction set version number", { AMDGPU::FeatureISAVersion8_1_0 }, { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureLDSBankCount16, AMDGPU::FeatureXNACK, AMDGPU::FeatureCodeObjectV3 } },
174
  { "isaver9.0.0", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_0 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureMadMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureCodeObjectV3 } },
175
  { "isaver9.0.2", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_2 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureMadMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK, AMDGPU::FeatureCodeObjectV3 } },
176
  { "isaver9.0.4", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_4 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureFmaMixInsts, AMDGPU::FeatureCodeObjectV3 } },
177
  { "isaver9.0.6", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_6 }, { AMDGPU::FeatureGFX9, AMDGPU::HalfRate64Ops, AMDGPU::FeatureFmaMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureDLInsts, AMDGPU::FeatureSRAMECC, AMDGPU::FeatureCodeObjectV3 } },
178
  { "isaver9.0.9", "Instruction set version number", { AMDGPU::FeatureISAVersion9_0_9 }, { AMDGPU::FeatureGFX9, AMDGPU::FeatureMadMixInsts, AMDGPU::FeatureLDSBankCount32, AMDGPU::FeatureXNACK, AMDGPU::FeatureCodeObjectV3 } },
179
  { "ldsbankcount16", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount16 }, { } },
180
  { "ldsbankcount32", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount32 }, { } },
181
  { "load-store-opt", "Enable SI load/store optimizer pass", { AMDGPU::FeatureEnableLoadStoreOpt }, { } },
182
  { "localmemorysize0", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize0 }, { } },
183
  { "localmemorysize32768", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize32768 }, { } },
184
  { "localmemorysize65536", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize65536 }, { } },
185
  { "mad-mix-insts", "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", { AMDGPU::FeatureMadMixInsts }, { } },
186
  { "max-private-element-size-16", "Maximum private access size may be 16", { AMDGPU::FeatureMaxPrivateElementSize16 }, { } },
187
  { "max-private-element-size-4", "Maximum private access size may be 4", { AMDGPU::FeatureMaxPrivateElementSize4 }, { } },
188
  { "max-private-element-size-8", "Maximum private access size may be 8", { AMDGPU::FeatureMaxPrivateElementSize8 }, { } },
189
  { "mimg-r128", "Support 128-bit texture resources", { AMDGPU::FeatureMIMG_R128 }, { } },
190
  { "movrel", "Has v_movrel*_b32 instructions", { AMDGPU::FeatureMovrel }, { } },
191
  { "promote-alloca", "Enable promote alloca pass", { AMDGPU::FeaturePromoteAlloca }, { } },
192
  { "r128-a16", "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9", { AMDGPU::FeatureR128A16 }, { } },
193
  { "s-memrealtime", "Has s_memrealtime instruction", { AMDGPU::FeatureSMemRealTime }, { } },
194
  { "scalar-atomics", "Has atomic scalar memory instructions", { AMDGPU::FeatureScalarAtomics }, { } },
195
  { "scalar-stores", "Has store scalar memory instructions", { AMDGPU::FeatureScalarStores }, { } },
196
  { "sdwa", "Support SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWA }, { } },
197
  { "sdwa-mav", "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAMac }, { } },
198
  { "sdwa-omod", "Support OMod with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAOmod }, { } },
199
  { "sdwa-out-mods-vopc", "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAOutModsVOPC }, { } },
200
  { "sdwa-scalar", "Support scalar register with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWAScalar }, { } },
201
  { "sdwa-sdst", "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", { AMDGPU::FeatureSDWASdst }, { } },
202
  { "sgpr-init-bug", "VI SGPR initialization bug requiring a fixed SGPR allocation size", { AMDGPU::FeatureSGPRInitBug }, { } },
203
  { "si-scheduler", "Enable SI Machine Scheduler", { AMDGPU::FeatureEnableSIScheduler }, { } },
204
  { "sram-ecc", "Enable SRAM ECC", { AMDGPU::FeatureSRAMECC }, { } },
205
  { "trap-handler", "Trap handler support", { AMDGPU::FeatureTrapHandler }, { } },
206
  { "trig-reduced-range", "Requires use of fract on arguments to trig instructions", { AMDGPU::FeatureTrigReducedRange }, { } },
207
  { "unaligned-buffer-access", "Support unaligned global loads and stores", { AMDGPU::FeatureUnalignedBufferAccess }, { } },
208
  { "unaligned-scratch-access", "Support unaligned scratch loads and stores", { AMDGPU::FeatureUnalignedScratchAccess }, { } },
209
  { "unpacked-d16-vmem", "Has unpacked d16 vmem instructions", { AMDGPU::FeatureUnpackedD16VMem }, { } },
210
  { "unsafe-ds-offset-folding", "Force using DS instruction immediate offsets on SI", { AMDGPU::FeatureEnableUnsafeDSOffsetFolding }, { } },
211
  { "vgpr-index-mode", "Has VGPR mode register indexing", { AMDGPU::FeatureVGPRIndexMode }, { } },
212
  { "vi-insts", "Additional instructions for VI+", { AMDGPU::FeatureVIInsts }, { } },
213
  { "vop3p", "Has VOP3P packed instructions", { AMDGPU::FeatureVOP3P }, { } },
214
  { "wavefrontsize16", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize16 }, { } },
215
  { "wavefrontsize32", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize32 }, { } },
216
  { "wavefrontsize64", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize64 }, { } },
217
  { "xnack", "Enable XNACK support", { AMDGPU::FeatureXNACK }, { } },
218
};
219
220
// Sorted (by key) array of values for CPU subtype.
221
extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[] = {
222
  { "bonaire", "Select the bonaire processor", { AMDGPU::FeatureISAVersion7_0_4 }, { } },
223
  { "carrizo", "Select the carrizo processor", { AMDGPU::FeatureISAVersion8_0_1 }, { } },
224
  { "fiji", "Select the fiji processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
225
  { "generic", "Select the generic processor", { AMDGPU::FeatureGCN, AMDGPU::FeatureWavefrontSize64 }, { } },
226
  { "gfx600", "Select the gfx600 processor", { AMDGPU::FeatureISAVersion6_0_0 }, { } },
227
  { "gfx601", "Select the gfx601 processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
228
  { "gfx700", "Select the gfx700 processor", { AMDGPU::FeatureISAVersion7_0_0 }, { } },
229
  { "gfx701", "Select the gfx701 processor", { AMDGPU::FeatureISAVersion7_0_1 }, { } },
230
  { "gfx702", "Select the gfx702 processor", { AMDGPU::FeatureISAVersion7_0_2 }, { } },
231
  { "gfx703", "Select the gfx703 processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
232
  { "gfx704", "Select the gfx704 processor", { AMDGPU::FeatureISAVersion7_0_4 }, { } },
233
  { "gfx801", "Select the gfx801 processor", { AMDGPU::FeatureISAVersion8_0_1 }, { } },
234
  { "gfx802", "Select the gfx802 processor", { AMDGPU::FeatureISAVersion8_0_2 }, { } },
235
  { "gfx803", "Select the gfx803 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
236
  { "gfx810", "Select the gfx810 processor", { AMDGPU::FeatureISAVersion8_1_0 }, { } },
237
  { "gfx900", "Select the gfx900 processor", { AMDGPU::FeatureISAVersion9_0_0 }, { } },
238
  { "gfx902", "Select the gfx902 processor", { AMDGPU::FeatureISAVersion9_0_2 }, { } },
239
  { "gfx904", "Select the gfx904 processor", { AMDGPU::FeatureISAVersion9_0_4 }, { } },
240
  { "gfx906", "Select the gfx906 processor", { AMDGPU::FeatureISAVersion9_0_6 }, { } },
241
  { "gfx909", "Select the gfx909 processor", { AMDGPU::FeatureISAVersion9_0_9 }, { } },
242
  { "hainan", "Select the hainan processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
243
  { "hawaii", "Select the hawaii processor", { AMDGPU::FeatureISAVersion7_0_1 }, { } },
244
  { "iceland", "Select the iceland processor", { AMDGPU::FeatureISAVersion8_0_2 }, { } },
245
  { "kabini", "Select the kabini processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
246
  { "kaveri", "Select the kaveri processor", { AMDGPU::FeatureISAVersion7_0_0 }, { } },
247
  { "mullins", "Select the mullins processor", { AMDGPU::FeatureISAVersion7_0_3 }, { } },
248
  { "oland", "Select the oland processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
249
  { "pitcairn", "Select the pitcairn processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
250
  { "polaris10", "Select the polaris10 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
251
  { "polaris11", "Select the polaris11 processor", { AMDGPU::FeatureISAVersion8_0_3 }, { } },
252
  { "stoney", "Select the stoney processor", { AMDGPU::FeatureISAVersion8_1_0 }, { } },
253
  { "tahiti", "Select the tahiti processor", { AMDGPU::FeatureISAVersion6_0_0 }, { } },
254
  { "tonga", "Select the tonga processor", { AMDGPU::FeatureISAVersion8_0_2 }, { } },
255
  { "verde", "Select the verde processor", { AMDGPU::FeatureISAVersion6_0_1 }, { } },
256
};
257
258
#ifdef DBGFIELD
259
#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
260
#endif
261
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
262
#define DBGFIELD(x) x,
263
#else
264
#define DBGFIELD(x)
265
#endif
266
267
// ===============================================================
268
// Data tables for the new per-operand machine model.
269
270
// {ProcResourceIdx, Cycles}
271
extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[] = {
272
  { 0,  0}, // Invalid
273
  { 5,  1}, // #1
274
  { 6,  1}, // #2
275
  { 3,  1}, // #3
276
  { 2,  1}, // #4
277
  { 1,  1}, // #5
278
  { 4,  1}, // #6
279
  { 4,  1}, // #7
280
  { 5,  1}, // #8
281
  { 5,  2} // #9
282
}; // AMDGPUWriteProcResTable
283
284
// {Cycles, WriteResourceID}
285
extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[] = {
286
  { 0,  0}, // Invalid
287
  { 1,  0}, // #1 Write32Bit_WriteSALU_WriteFloatFMA
288
  {80,  0}, // #2 WriteVMEM
289
  { 5,  0}, // #3 WriteLDS_WriteSMEM
290
  { 4,  0}, // #4 WriteExport_WriteQuarterRate32_WriteDouble
291
  { 8,  0}, // #5 WriteBranch_WriteDoubleAdd
292
  { 1,  0}, // #6 Write32Bit_WriteFloatFMA
293
  { 1,  0}, // #7 WriteSALU
294
  { 2,  0}, // #8 Write64Bit_WriteDoubleAdd
295
  {16,  0}, // #9 WriteFloatFMA_WriteDouble
296
  {16,  0}, // #10 WriteFloatFMA_WriteDouble
297
  { 1,  0}, // #11 WriteSALU
298
  { 4,  0}, // #12 WriteQuarterRate32_WriteDouble
299
  { 1,  0}, // #13 WriteSALU
300
  { 2,  0}, // #14 Write64Bit
301
  { 2,  0}, // #15 Write64Bit
302
  {500,  0} // #16 WriteBarrier
303
}; // AMDGPUWriteLatencyTable
304
305
// {UseIdx, WriteResourceID, Cycles}
306
extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[] = {
307
  {0,  0,  0}, // Invalid
308
}; // AMDGPUReadAdvanceTable
309
310
// {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
311
static const llvm::MCSchedClassDesc SIQuarterSpeedModelSchedClasses[] = {
312
  {DBGFIELD("InvalidSchedClass")  16383, false, false,  0, 0,  0, 0,  0, 0},
313
  {DBGFIELD("NullALU_Write32Bit") 1, false, false,  1, 1,  1, 1,  0, 0}, // #1
314
  {DBGFIELD("NullALU_WriteVMEM")  1, false, false,  2, 1,  2, 1,  0, 0}, // #2
315
  {DBGFIELD("NullALU_WriteLDS")   1, false, false,  3, 1,  3, 1,  0, 0}, // #3
316
  {DBGFIELD("NullALU_WriteExport") 1, false, false,  4, 1,  4, 1,  0, 0}, // #4
317
  {DBGFIELD("NullALU_WriteBranch") 1, false, false,  5, 1,  5, 1,  0, 0}, // #5
318
  {DBGFIELD("NullALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #6
319
  {DBGFIELD("NullALU_WriteSALU")  1, false, false,  6, 1,  1, 1,  0, 0}, // #7
320
  {DBGFIELD("NullALU_WriteSMEM")  1, false, false,  3, 1,  3, 1,  0, 0}, // #8
321
  {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false,  7, 2,  6, 2,  0, 0}, // #9
322
  {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false,  1, 1,  5, 1,  0, 0}, // #10
323
  {DBGFIELD("NullALU_Write64Bit") 1, false, false,  1, 1,  8, 1,  0, 0}, // #11
324
  {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false,  1, 1,  4, 1,  0, 0}, // #12
325
  {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false,  1, 1,  9, 1,  0, 0}, // #13
326
  {DBGFIELD("NullALU_WriteDouble") 1, false, false,  1, 1,  9, 1,  0, 0}, // #14
327
  {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false,  7, 2, 10, 2,  0, 0}, // #15
328
  {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false,  7, 2, 10, 2,  0, 0}, // #16
329
  {DBGFIELD("NullALU_WriteQuarterRate32_WriteSALU") 2, false, false,  7, 2, 12, 2,  0, 0}, // #17
330
  {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false,  9, 1, 14, 2,  0, 0}, // #18
331
  {DBGFIELD("NullALU_WriteBarrier") 1, false, false,  5, 1, 16, 1,  0, 0}, // #19
332
  {DBGFIELD("COPY")               16382, false, false,  0, 0,  0, 0,  0, 0}, // #20
333
  {DBGFIELD("Write32Bit")         1, false, false,  1, 1,  1, 1,  0, 0}, // #21
334
  {DBGFIELD("Write64Bit")         1, false, false,  1, 1,  8, 1,  0, 0}, // #22
335
  {DBGFIELD("WriteSALU")          1, false, false,  6, 1,  1, 1,  0, 0}, // #23
336
}; // SIQuarterSpeedModelSchedClasses
337
338
// {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
339
static const llvm::MCSchedClassDesc SIFullSpeedModelSchedClasses[] = {
340
  {DBGFIELD("InvalidSchedClass")  16383, false, false,  0, 0,  0, 0,  0, 0},
341
  {DBGFIELD("NullALU_Write32Bit") 1, false, false,  1, 1,  1, 1,  0, 0}, // #1
342
  {DBGFIELD("NullALU_WriteVMEM")  1, false, false,  2, 1,  2, 1,  0, 0}, // #2
343
  {DBGFIELD("NullALU_WriteLDS")   1, false, false,  3, 1,  3, 1,  0, 0}, // #3
344
  {DBGFIELD("NullALU_WriteExport") 1, false, false,  4, 1,  4, 1,  0, 0}, // #4
345
  {DBGFIELD("NullALU_WriteBranch") 1, false, false,  5, 1,  5, 1,  0, 0}, // #5
346
  {DBGFIELD("NullALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #6
347
  {DBGFIELD("NullALU_WriteSALU")  1, false, false,  6, 1,  1, 1,  0, 0}, // #7
348
  {DBGFIELD("NullALU_WriteSMEM")  1, false, false,  3, 1,  3, 1,  0, 0}, // #8
349
  {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false,  7, 2,  6, 2,  0, 0}, // #9
350
  {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false,  1, 1,  8, 1,  0, 0}, // #10
351
  {DBGFIELD("NullALU_Write64Bit") 1, false, false,  1, 1,  8, 1,  0, 0}, // #11
352
  {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false,  1, 1,  4, 1,  0, 0}, // #12
353
  {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false,  1, 1,  1, 1,  0, 0}, // #13
354
  {DBGFIELD("NullALU_WriteDouble") 1, false, false,  1, 1,  4, 1,  0, 0}, // #14
355
  {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false,  7, 2,  6, 2,  0, 0}, // #15
356
  {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false,  7, 2, 12, 2,  0, 0}, // #16
357
  {DBGFIELD("NullALU_WriteQuarterRate32_WriteSALU") 2, false, false,  7, 2, 12, 2,  0, 0}, // #17
358
  {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false,  9, 1, 14, 2,  0, 0}, // #18
359
  {DBGFIELD("NullALU_WriteBarrier") 1, false, false,  5, 1, 16, 1,  0, 0}, // #19
360
  {DBGFIELD("COPY")               16382, false, false,  0, 0,  0, 0,  0, 0}, // #20
361
  {DBGFIELD("Write32Bit")         1, false, false,  1, 1,  1, 1,  0, 0}, // #21
362
  {DBGFIELD("Write64Bit")         1, false, false,  1, 1,  8, 1,  0, 0}, // #22
363
  {DBGFIELD("WriteSALU")          1, false, false,  6, 1,  1, 1,  0, 0}, // #23
364
}; // SIFullSpeedModelSchedClasses
365
366
static const llvm::MCSchedModel NoSchedModel = {
367
  MCSchedModel::DefaultIssueWidth,
368
  MCSchedModel::DefaultMicroOpBufferSize,
369
  MCSchedModel::DefaultLoopMicroOpBufferSize,
370
  MCSchedModel::DefaultLoadLatency,
371
  MCSchedModel::DefaultHighLatency,
372
  MCSchedModel::DefaultMispredictPenalty,
373
  false, // PostRAScheduler
374
  false, // CompleteModel
375
  0, // Processor ID
376
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
377
  nullptr, // No Itinerary
378
  nullptr // No extra processor descriptor
379
};
380
381
static const unsigned SIQuarterSpeedModelProcResourceSubUnits[] = {
382
  0,  // Invalid
383
};
384
385
// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
386
static const llvm::MCProcResourceDesc SIQuarterSpeedModelProcResources[] = {
387
  {"InvalidUnit", 0, 0, 0, 0},
388
  {"HWBranch",        1, 0, 1, nullptr}, // #1
389
  {"HWExport",        1, 0, 7, nullptr}, // #2
390
  {"HWLGKM",          1, 0, 31, nullptr}, // #3
391
  {"HWSALU",          1, 0, 1, nullptr}, // #4
392
  {"HWVALU",          1, 0, 1, nullptr}, // #5
393
  {"HWVMEM",          1, 0, 15, nullptr}, // #6
394
};
395
396
static const llvm::MCSchedModel SIQuarterSpeedModel = {
397
  1, // IssueWidth
398
  1, // MicroOpBufferSize
399
  MCSchedModel::DefaultLoopMicroOpBufferSize,
400
  MCSchedModel::DefaultLoadLatency,
401
  MCSchedModel::DefaultHighLatency,
402
  20, // MispredictPenalty
403
  true, // PostRAScheduler
404
  false, // CompleteModel
405
  1, // Processor ID
406
  SIQuarterSpeedModelProcResources,
407
  SIQuarterSpeedModelSchedClasses,
408
  7,
409
  24,
410
  nullptr, // No Itinerary
411
  nullptr // No extra processor descriptor
412
};
413
414
static const unsigned SIFullSpeedModelProcResourceSubUnits[] = {
415
  0,  // Invalid
416
};
417
418
// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
419
static const llvm::MCProcResourceDesc SIFullSpeedModelProcResources[] = {
420
  {"InvalidUnit", 0, 0, 0, 0},
421
  {"HWBranch",        1, 0, 1, nullptr}, // #1
422
  {"HWExport",        1, 0, 7, nullptr}, // #2
423
  {"HWLGKM",          1, 0, 31, nullptr}, // #3
424
  {"HWSALU",          1, 0, 1, nullptr}, // #4
425
  {"HWVALU",          1, 0, 1, nullptr}, // #5
426
  {"HWVMEM",          1, 0, 15, nullptr}, // #6
427
};
428
429
static const llvm::MCSchedModel SIFullSpeedModel = {
430
  1, // IssueWidth
431
  1, // MicroOpBufferSize
432
  MCSchedModel::DefaultLoopMicroOpBufferSize,
433
  MCSchedModel::DefaultLoadLatency,
434
  MCSchedModel::DefaultHighLatency,
435
  20, // MispredictPenalty
436
  true, // PostRAScheduler
437
  false, // CompleteModel
438
  2, // Processor ID
439
  SIFullSpeedModelProcResources,
440
  SIFullSpeedModelSchedClasses,
441
  7,
442
  24,
443
  nullptr, // No Itinerary
444
  nullptr // No extra processor descriptor
445
};
446
447
// Sorted (by key) array of sched model for CPU subtype.
448
extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[] = {
449
  { "bonaire", (const void *)&SIQuarterSpeedModel },
450
  { "carrizo", (const void *)&SIQuarterSpeedModel },
451
  { "fiji", (const void *)&SIQuarterSpeedModel },
452
  { "generic", (const void *)&NoSchedModel },
453
  { "gfx600", (const void *)&SIFullSpeedModel },
454
  { "gfx601", (const void *)&SIQuarterSpeedModel },
455
  { "gfx700", (const void *)&SIQuarterSpeedModel },
456
  { "gfx701", (const void *)&SIFullSpeedModel },
457
  { "gfx702", (const void *)&SIQuarterSpeedModel },
458
  { "gfx703", (const void *)&SIQuarterSpeedModel },
459
  { "gfx704", (const void *)&SIQuarterSpeedModel },
460
  { "gfx801", (const void *)&SIQuarterSpeedModel },
461
  { "gfx802", (const void *)&SIQuarterSpeedModel },
462
  { "gfx803", (const void *)&SIQuarterSpeedModel },
463
  { "gfx810", (const void *)&SIQuarterSpeedModel },
464
  { "gfx900", (const void *)&SIQuarterSpeedModel },
465
  { "gfx902", (const void *)&SIQuarterSpeedModel },
466
  { "gfx904", (const void *)&SIQuarterSpeedModel },
467
  { "gfx906", (const void *)&SIQuarterSpeedModel },
468
  { "gfx909", (const void *)&SIQuarterSpeedModel },
469
  { "hainan", (const void *)&SIQuarterSpeedModel },
470
  { "hawaii", (const void *)&SIFullSpeedModel },
471
  { "iceland", (const void *)&SIQuarterSpeedModel },
472
  { "kabini", (const void *)&SIQuarterSpeedModel },
473
  { "kaveri", (const void *)&SIQuarterSpeedModel },
474
  { "mullins", (const void *)&SIQuarterSpeedModel },
475
  { "oland", (const void *)&SIQuarterSpeedModel },
476
  { "pitcairn", (const void *)&SIQuarterSpeedModel },
477
  { "polaris10", (const void *)&SIQuarterSpeedModel },
478
  { "polaris11", (const void *)&SIQuarterSpeedModel },
479
  { "stoney", (const void *)&SIQuarterSpeedModel },
480
  { "tahiti", (const void *)&SIFullSpeedModel },
481
  { "tonga", (const void *)&SIQuarterSpeedModel },
482
  { "verde", (const void *)&SIQuarterSpeedModel },
483
};
484
485
#undef DBGFIELD
486
namespace AMDGPU_MC {
487
unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
488
0
    const MCInst *MI, unsigned CPUID) {
489
0
  // Don't know how to resolve this scheduling class.
490
0
  return 0;
491
0
}
492
} // end of namespace AMDGPU_MC
493
494
struct AMDGPUGenMCSubtargetInfo : public MCSubtargetInfo {
495
  AMDGPUGenMCSubtargetInfo(const Triple &TT, 
496
    StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
497
    ArrayRef<SubtargetFeatureKV> PD,
498
    const SubtargetInfoKV *ProcSched,
499
    const MCWriteProcResEntry *WPR,
500
    const MCWriteLatencyEntry *WL,
501
    const MCReadAdvanceEntry *RA, const InstrStage *IS,
502
    const unsigned *OC, const unsigned *FP) :
503
      MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
504
2.98k
                      WPR, WL, RA, IS, OC, FP) { }
505
506
  unsigned resolveVariantSchedClass(unsigned SchedClass,
507
0
      const MCInst *MI, unsigned CPUID) const override {
508
0
    return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 
509
0
  }
510
};
511
512
2.98k
static inline MCSubtargetInfo *createAMDGPUMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
513
2.98k
  return new AMDGPUGenMCSubtargetInfo(TT, CPU, FS, AMDGPUFeatureKV, AMDGPUSubTypeKV, 
514
2.98k
                      AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, 
515
2.98k
                      nullptr, nullptr, nullptr);
516
2.98k
}
517
518
} // end namespace llvm
519
520
#endif // GET_SUBTARGETINFO_MC_DESC
521
522
523
#ifdef GET_SUBTARGETINFO_TARGET_DESC
524
#undef GET_SUBTARGETINFO_TARGET_DESC
525
526
#include "llvm/Support/Debug.h"
527
#include "llvm/Support/raw_ostream.h"
528
529
// ParseSubtargetFeatures - Parses features string setting specified
530
// subtarget options.
531
2.54k
void llvm::AMDGPUSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
532
2.54k
  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
533
2.54k
  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
534
2.54k
  InitMCProcessorInfo(CPU, FS);
535
2.54k
  const FeatureBitset& Bits = getFeatureBits();
536
2.54k
  if (Bits[AMDGPU::Feature16BitInsts]) 
Has16BitInsts = true1.28k
;
537
2.54k
  if (Bits[AMDGPU::FeatureAddNoCarryInsts]) 
AddNoCarryInsts = true359
;
538
2.54k
  if (Bits[AMDGPU::FeatureApertureRegs]) 
HasApertureRegs = true359
;
539
2.54k
  if (Bits[AMDGPU::FeatureAutoWaitcntBeforeBarrier]) 
AutoWaitcntBeforeBarrier = true2
;
540
2.54k
  if (Bits[AMDGPU::FeatureCIInsts]) 
CIInsts = true1.52k
;
541
2.54k
  if (Bits[AMDGPU::FeatureCodeObjectV3]) 
CodeObjectV3 = true1.73k
;
542
2.54k
  if (Bits[AMDGPU::FeatureDLInsts]) 
HasDLInsts = true32
;
543
2.54k
  if (Bits[AMDGPU::FeatureDPP]) 
HasDPP = true1.28k
;
544
2.54k
  if (Bits[AMDGPU::FeatureDX10Clamp]) 
DX10Clamp = true2.53k
;
545
2.54k
  if (Bits[AMDGPU::FeatureDebuggerEmitPrologue]) 
DebuggerEmitPrologue = true4
;
546
2.54k
  if (Bits[AMDGPU::FeatureDebuggerInsertNops]) 
DebuggerInsertNops = true5
;
547
2.54k
  if (Bits[AMDGPU::FeatureDisable]) 
FeatureDisable = true0
;
548
2.54k
  if (Bits[AMDGPU::FeatureDumpCode]) 
DumpCode = true0
;
549
2.54k
  if (Bits[AMDGPU::FeatureDumpCodeLower]) 
DumpCode = true2
;
550
2.54k
  if (Bits[AMDGPU::FeatureEnableDS128]) 
EnableDS128 = true14
;
551
2.54k
  if (Bits[AMDGPU::FeatureEnableHugePrivateBuffer]) 
EnableHugePrivateBuffer = true1
;
552
2.54k
  if (Bits[AMDGPU::FeatureEnableLoadStoreOpt]) 
EnableLoadStoreOpt = true2.53k
;
553
2.54k
  if (Bits[AMDGPU::FeatureEnableSIScheduler]) 
EnableSIScheduler = true1
;
554
2.54k
  if (Bits[AMDGPU::FeatureEnableUnsafeDSOffsetFolding]) 
EnableUnsafeDSOffsetFolding = true1
;
555
2.54k
  if (Bits[AMDGPU::FeatureFMA]) 
FMA = true0
;
556
2.54k
  if (Bits[AMDGPU::FeatureFP16Denormals]) 
FP64FP16Denormals = true1
;
557
2.54k
  if (Bits[AMDGPU::FeatureFP32Denormals]) 
FP32Denormals = true61
;
558
2.54k
  if (Bits[AMDGPU::FeatureFP64]) FP64 = true;
559
2.54k
  if (Bits[AMDGPU::FeatureFP64Denormals]) 
FP64FP16Denormals = true2
;
560
2.54k
  if (Bits[AMDGPU::FeatureFP64FP16Denormals]) 
FP64FP16Denormals = true2.50k
;
561
2.54k
  if (Bits[AMDGPU::FeatureFPExceptions]) 
FPExceptions = true7
;
562
2.54k
  if (Bits[AMDGPU::FeatureFastFMAF32]) 
FastFMAF32 = true634
;
563
2.54k
  if (Bits[AMDGPU::FeatureFlatAddressSpace]) 
FlatAddressSpace = true1.69k
;
564
2.54k
  if (Bits[AMDGPU::FeatureFlatForGlobal]) 
FlatForGlobal = true478
;
565
2.54k
  if (Bits[AMDGPU::FeatureFlatGlobalInsts]) 
FlatGlobalInsts = true359
;
566
2.54k
  if (Bits[AMDGPU::FeatureFlatInstOffsets]) 
FlatInstOffsets = true359
;
567
2.54k
  if (Bits[AMDGPU::FeatureFlatScratchInsts]) 
FlatScratchInsts = true359
;
568
2.54k
  if (Bits[AMDGPU::FeatureFmaMixInsts]) 
HasFmaMixInsts = true37
;
569
2.54k
  if (Bits[AMDGPU::FeatureGCN]) 
IsGCN = true2.52k
;
570
2.54k
  if (Bits[AMDGPU::FeatureGCN3Encoding]) 
GCN3Encoding = true1.28k
;
571
2.54k
  if (Bits[AMDGPU::FeatureGFX9] && 
Gen < GCNSubtarget::GFX9359
)
Gen = GCNSubtarget::GFX9359
;
572
2.54k
  if (Bits[AMDGPU::FeatureGFX9Insts]) 
GFX9Insts = true359
;
573
2.54k
  if (Bits[AMDGPU::FeatureISAVersion6_0_0] && 
IsaVersion < ISAVersion6_0_0182
)
IsaVersion = ISAVersion6_0_0182
;
574
2.54k
  if (Bits[AMDGPU::FeatureISAVersion6_0_1] && 
IsaVersion < ISAVersion6_0_1107
)
IsaVersion = ISAVersion6_0_1107
;
575
2.54k
  if (Bits[AMDGPU::FeatureISAVersion7_0_0] && 
IsaVersion < ISAVersion7_0_077
)
IsaVersion = ISAVersion7_0_077
;
576
2.54k
  if (Bits[AMDGPU::FeatureISAVersion7_0_1] && 
IsaVersion < ISAVersion7_0_147
)
IsaVersion = ISAVersion7_0_147
;
577
2.54k
  if (Bits[AMDGPU::FeatureISAVersion7_0_2] && 
IsaVersion < ISAVersion7_0_22
)
IsaVersion = ISAVersion7_0_22
;
578
2.54k
  if (Bits[AMDGPU::FeatureISAVersion7_0_3] && 
IsaVersion < ISAVersion7_0_37
)
IsaVersion = ISAVersion7_0_37
;
579
2.54k
  if (Bits[AMDGPU::FeatureISAVersion7_0_4] && 
IsaVersion < ISAVersion7_0_479
)
IsaVersion = ISAVersion7_0_479
;
580
2.54k
  if (Bits[AMDGPU::FeatureISAVersion8_0_1] && 
IsaVersion < ISAVersion8_0_128
)
IsaVersion = ISAVersion8_0_128
;
581
2.54k
  if (Bits[AMDGPU::FeatureISAVersion8_0_2] && 
IsaVersion < ISAVersion8_0_2458
)
IsaVersion = ISAVersion8_0_2458
;
582
2.54k
  if (Bits[AMDGPU::FeatureISAVersion8_0_3] && 
IsaVersion < ISAVersion8_0_3372
)
IsaVersion = ISAVersion8_0_3372
;
583
2.54k
  if (Bits[AMDGPU::FeatureISAVersion8_1_0] && 
IsaVersion < ISAVersion8_1_023
)
IsaVersion = ISAVersion8_1_023
;
584
2.54k
  if (Bits[AMDGPU::FeatureISAVersion9_0_0] && 
IsaVersion < ISAVersion9_0_0300
)
IsaVersion = ISAVersion9_0_0300
;
585
2.54k
  if (Bits[AMDGPU::FeatureISAVersion9_0_2] && 
IsaVersion < ISAVersion9_0_28
)
IsaVersion = ISAVersion9_0_28
;
586
2.54k
  if (Bits[AMDGPU::FeatureISAVersion9_0_4] && 
IsaVersion < ISAVersion9_0_45
)
IsaVersion = ISAVersion9_0_45
;
587
2.54k
  if (Bits[AMDGPU::FeatureISAVersion9_0_6] && 
IsaVersion < ISAVersion9_0_630
)
IsaVersion = ISAVersion9_0_630
;
588
2.54k
  if (Bits[AMDGPU::FeatureISAVersion9_0_9] && 
IsaVersion < ISAVersion9_0_91
)
IsaVersion = ISAVersion9_0_91
;
589
2.54k
  if (Bits[AMDGPU::FeatureIntClamp]) 
HasIntClamp = true1.28k
;
590
2.54k
  if (Bits[AMDGPU::FeatureInv2PiInlineImm]) 
HasInv2PiInlineImm = true1.28k
;
591
2.54k
  if (Bits[AMDGPU::FeatureLDSBankCount16] && 
LDSBankCount < 1633
)
LDSBankCount = 1633
;
592
2.54k
  if (Bits[AMDGPU::FeatureLDSBankCount32] && 
LDSBankCount < 321.78k
)
LDSBankCount = 321.78k
;
593
2.54k
  if (Bits[AMDGPU::FeatureLocalMemorySize0] && 
LocalMemorySize < 00
)
LocalMemorySize = 00
;
594
2.54k
  if (Bits[AMDGPU::FeatureLocalMemorySize32768] && 
LocalMemorySize < 32768291
)
LocalMemorySize = 32768291
;
595
2.54k
  if (Bits[AMDGPU::FeatureLocalMemorySize65536] && 
LocalMemorySize < 655361.52k
)
LocalMemorySize = 655361.52k
;
596
2.54k
  if (Bits[AMDGPU::FeatureMIMG_R128]) 
MIMG_R128 = true1.45k
;
597
2.54k
  if (Bits[AMDGPU::FeatureMadMixInsts]) 
HasMadMixInsts = true322
;
598
2.54k
  if (Bits[AMDGPU::FeatureMaxPrivateElementSize4] && 
MaxPrivateElementSize < 46
)
MaxPrivateElementSize = 46
;
599
2.54k
  if (Bits[AMDGPU::FeatureMaxPrivateElementSize8] && 
MaxPrivateElementSize < 83
)
MaxPrivateElementSize = 83
;
600
2.54k
  if (Bits[AMDGPU::FeatureMaxPrivateElementSize16] && 
MaxPrivateElementSize < 1612
)
MaxPrivateElementSize = 1612
;
601
2.54k
  if (Bits[AMDGPU::FeatureMovrel]) 
HasMovrel = true1.45k
;
602
2.54k
  if (Bits[AMDGPU::FeaturePromoteAlloca]) 
EnablePromoteAlloca = true2.49k
;
603
2.54k
  if (Bits[AMDGPU::FeatureR128A16]) 
HasR128A16 = true359
;
604
2.54k
  if (Bits[AMDGPU::FeatureSDWA]) 
HasSDWA = true1.28k
;
605
2.54k
  if (Bits[AMDGPU::FeatureSDWAMac]) 
HasSDWAMac = true923
;
606
2.54k
  if (Bits[AMDGPU::FeatureSDWAOmod]) 
HasSDWAOmod = true359
;
607
2.54k
  if (Bits[AMDGPU::FeatureSDWAOutModsVOPC]) 
HasSDWAOutModsVOPC = true923
;
608
2.54k
  if (Bits[AMDGPU::FeatureSDWAScalar]) 
HasSDWAScalar = true359
;
609
2.54k
  if (Bits[AMDGPU::FeatureSDWASdst]) 
HasSDWASdst = true359
;
610
2.54k
  if (Bits[AMDGPU::FeatureSGPRInitBug]) 
SGPRInitBug = true477
;
611
2.54k
  if (Bits[AMDGPU::FeatureSMemRealTime]) 
HasSMemRealTime = true1.28k
;
612
2.54k
  if (Bits[AMDGPU::FeatureSRAMECC]) 
EnableSRAMECC = true33
;
613
2.54k
  if (Bits[AMDGPU::FeatureScalarAtomics]) 
HasScalarAtomics = true359
;
614
2.54k
  if (Bits[AMDGPU::FeatureScalarStores]) 
HasScalarStores = true1.28k
;
615
2.54k
  if (Bits[AMDGPU::FeatureSeaIslands] && 
Gen < GCNSubtarget::SEA_ISLANDS245
)
Gen = GCNSubtarget::SEA_ISLANDS245
;
616
2.54k
  if (Bits[AMDGPU::FeatureSouthernIslands] && 
Gen < GCNSubtarget::SOUTHERN_ISLANDS291
)
Gen = GCNSubtarget::SOUTHERN_ISLANDS0
;
617
2.54k
  if (Bits[AMDGPU::FeatureTrapHandler]) 
TrapHandler = true514
;
618
2.54k
  if (Bits[AMDGPU::FeatureTrigReducedRange]) 
HasTrigReducedRange = true1.45k
;
619
2.54k
  if (Bits[AMDGPU::FeatureUnalignedBufferAccess]) 
UnalignedBufferAccess = true512
;
620
2.54k
  if (Bits[AMDGPU::FeatureUnalignedScratchAccess]) 
UnalignedScratchAccess = true4
;
621
2.54k
  if (Bits[AMDGPU::FeatureUnpackedD16VMem]) 
HasUnpackedD16VMem = true899
;
622
2.54k
  if (Bits[AMDGPU::FeatureVGPRIndexMode]) 
HasVGPRIndexMode = true1.28k
;
623
2.54k
  if (Bits[AMDGPU::FeatureVIInsts]) 
VIInsts = true1.28k
;
624
2.54k
  if (Bits[AMDGPU::FeatureVOP3P]) 
HasVOP3PInsts = true359
;
625
2.54k
  if (Bits[AMDGPU::FeatureVolcanicIslands] && 
Gen < GCNSubtarget::VOLCANIC_ISLANDS923
)
Gen = GCNSubtarget::VOLCANIC_ISLANDS923
;
626
2.54k
  if (Bits[AMDGPU::FeatureWavefrontSize16] && 
WavefrontSize < 160
)
WavefrontSize = 160
;
627
2.54k
  if (Bits[AMDGPU::FeatureWavefrontSize32] && 
WavefrontSize < 320
)
WavefrontSize = 320
;
628
2.54k
  if (Bits[AMDGPU::FeatureWavefrontSize64] && 
WavefrontSize < 642.52k
)
WavefrontSize = 642.52k
;
629
2.54k
  if (Bits[AMDGPU::FeatureXNACK]) 
EnableXNACK = true73
;
630
2.54k
  if (Bits[AMDGPU::HalfRate64Ops]) 
HalfRate64Ops = true310
;
631
2.54k
}
632
#endif // GET_SUBTARGETINFO_TARGET_DESC
633
634
635
#ifdef GET_SUBTARGETINFO_HEADER
636
#undef GET_SUBTARGETINFO_HEADER
637
638
namespace llvm {
639
class DFAPacketizer;
640
namespace AMDGPU_MC {
641
unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
642
}
643
644
struct AMDGPUGenSubtargetInfo : public TargetSubtargetInfo {
645
  explicit AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
646
public:
647
  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
648
  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
649
  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
650
};
651
} // end namespace llvm
652
653
#endif // GET_SUBTARGETINFO_HEADER
654
655
656
#ifdef GET_SUBTARGETINFO_CTOR
657
#undef GET_SUBTARGETINFO_CTOR
658
659
#include "llvm/CodeGen/TargetSchedule.h"
660
661
namespace llvm {
662
extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[];
663
extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[];
664
extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[];
665
extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[];
666
extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[];
667
extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[];
668
AMDGPUGenSubtargetInfo::AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
669
  : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(AMDGPUFeatureKV, 94), makeArrayRef(AMDGPUSubTypeKV, 34), 
670
                        AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, 
671
2.54k
                        nullptr, nullptr, nullptr) {}
672
673
unsigned AMDGPUGenSubtargetInfo
674
669k
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
675
669k
676
669k
  const SIInstrInfo *TII =
677
669k
    static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
678
669k
  (void)TII;
679
669k
680
669k
  switch (SchedClass) {
681
669k
  case 20: // COPY
682
669k
    if (SchedModel->getProcessorID() == 1) { // SIQuarterSpeedModel
683
585k
      if (TII->isVGPRCopy(*MI) && 
TII->getOpSize(*MI, 0) <= 32346k
)
684
346k
        return 21; // Write32Bit
685
239k
      if (TII->isVGPRCopy(*MI) && 
TII->getOpSize(*MI, 0) > 32131
)
686
131
        return 22; // Write64Bit
687
239k
      return 23; // WriteSALU
688
239k
    }
689
83.3k
    if (SchedModel->getProcessorID() == 2) { // SIFullSpeedModel
690
83.3k
      if (TII->isVGPRCopy(*MI) && 
TII->getOpSize(*MI, 0) <= 3246.4k
)
691
46.3k
        return 21; // Write32Bit
692
36.9k
      if (TII->isVGPRCopy(*MI) && 
TII->getOpSize(*MI, 0) > 3227
)
693
27
        return 22; // Write64Bit
694
36.9k
      return 23; // WriteSALU
695
36.9k
    }
696
0
    break;
697
0
  };
698
0
  report_fatal_error("Expected a variant SchedClass");
699
0
} // AMDGPUGenSubtargetInfo::resolveSchedClass
700
701
unsigned AMDGPUGenSubtargetInfo
702
0
::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
703
0
  return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
704
0
} // AMDGPUGenSubtargetInfo::resolveVariantSchedClass
705
706
} // end namespace llvm
707
708
#endif // GET_SUBTARGETINFO_CTOR
709
710
711
#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
712
#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
713
714
#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
715
716
717
#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
718
#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
719
720
#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
721