Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/R600GenCallingConv.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Calling Convention Implementation Fragment                                 *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
static bool CC_R600(unsigned ValNo, MVT ValVT,
10
                    MVT LocVT, CCValAssign::LocInfo LocInfo,
11
                    ISD::ArgFlagsTy ArgFlags, CCState &State);
12
static bool CC_R600_Kernel(unsigned ValNo, MVT ValVT,
13
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
14
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
15
16
17
static bool CC_R600(unsigned ValNo, MVT ValVT,
18
                    MVT LocVT, CCValAssign::LocInfo LocInfo,
19
65
                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
20
65
21
65
  if (ArgFlags.isInReg()) {
22
65
    if (LocVT == MVT::v4f32 ||
23
65
        
LocVT == MVT::v4i320
) {
24
65
      static const MCPhysReg RegList1[] = {
25
65
        R600::T0_XYZW, R600::T1_XYZW, R600::T2_XYZW, R600::T3_XYZW, R600::T4_XYZW, R600::T5_XYZW, R600::T6_XYZW, R600::T7_XYZW, R600::T8_XYZW, R600::T9_XYZW, R600::T10_XYZW, R600::T11_XYZW, R600::T12_XYZW, R600::T13_XYZW, R600::T14_XYZW, R600::T15_XYZW, R600::T16_XYZW, R600::T17_XYZW, R600::T18_XYZW, R600::T19_XYZW, R600::T20_XYZW, R600::T21_XYZW, R600::T22_XYZW, R600::T23_XYZW, R600::T24_XYZW, R600::T25_XYZW, R600::T26_XYZW, R600::T27_XYZW, R600::T28_XYZW, R600::T29_XYZW, R600::T30_XYZW, R600::T31_XYZW, R600::T32_XYZW
26
65
      };
27
65
      if (unsigned Reg = State.AllocateReg(RegList1)) {
28
65
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
29
65
        return false;
30
65
      }
31
0
    }
32
65
  }
33
0
34
0
  return true;  // CC didn't match.
35
0
}
36
37
38
static bool CC_R600_Kernel(unsigned ValNo, MVT ValVT,
39
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
40
0
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
41
0
42
0
  if (allocateKernArg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
43
0
    return false;
44
0
45
0
  return true;  // CC didn't match.
46
0
}