Coverage Report

Created: 2018-09-19 20:53

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/R600GenCallingConv.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Calling Convention Implementation Fragment                                 *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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static bool CC_R600(unsigned ValNo, MVT ValVT,
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                    MVT LocVT, CCValAssign::LocInfo LocInfo,
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                    ISD::ArgFlagsTy ArgFlags, CCState &State);
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static bool CC_R600(unsigned ValNo, MVT ValVT,
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                    MVT LocVT, CCValAssign::LocInfo LocInfo,
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                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
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  if (ArgFlags.isInReg()) {
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    if (LocVT == MVT::v4f32 ||
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        LocVT == MVT::v4i32) {
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      static const MCPhysReg RegList1[] = {
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        R600::T0_XYZW, R600::T1_XYZW, R600::T2_XYZW, R600::T3_XYZW, R600::T4_XYZW, R600::T5_XYZW, R600::T6_XYZW, R600::T7_XYZW, R600::T8_XYZW, R600::T9_XYZW, R600::T10_XYZW, R600::T11_XYZW, R600::T12_XYZW, R600::T13_XYZW, R600::T14_XYZW, R600::T15_XYZW, R600::T16_XYZW, R600::T17_XYZW, R600::T18_XYZW, R600::T19_XYZW, R600::T20_XYZW, R600::T21_XYZW, R600::T22_XYZW, R600::T23_XYZW, R600::T24_XYZW, R600::T25_XYZW, R600::T26_XYZW, R600::T27_XYZW, R600::T28_XYZW, R600::T29_XYZW, R600::T30_XYZW, R600::T31_XYZW, R600::T32_XYZW
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      };
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      if (unsigned Reg = State.AllocateReg(RegList1)) {
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        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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        return false;
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      }
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    }
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  }
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  return true;  // CC didn't match.
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}