Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/R600GenInstrInfo.inc
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace R600 {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    CFI_INSTRUCTION = 2,
18
    EH_LABEL  = 3,
19
    GC_LABEL  = 4,
20
    ANNOTATION_LABEL  = 5,
21
    KILL  = 6,
22
    EXTRACT_SUBREG  = 7,
23
    INSERT_SUBREG = 8,
24
    IMPLICIT_DEF  = 9,
25
    SUBREG_TO_REG = 10,
26
    COPY_TO_REGCLASS  = 11,
27
    DBG_VALUE = 12,
28
    DBG_LABEL = 13,
29
    REG_SEQUENCE  = 14,
30
    COPY  = 15,
31
    BUNDLE  = 16,
32
    LIFETIME_START  = 17,
33
    LIFETIME_END  = 18,
34
    STACKMAP  = 19,
35
    FENTRY_CALL = 20,
36
    PATCHPOINT  = 21,
37
    LOAD_STACK_GUARD  = 22,
38
    STATEPOINT  = 23,
39
    LOCAL_ESCAPE  = 24,
40
    FAULTING_OP = 25,
41
    PATCHABLE_OP  = 26,
42
    PATCHABLE_FUNCTION_ENTER  = 27,
43
    PATCHABLE_RET = 28,
44
    PATCHABLE_FUNCTION_EXIT = 29,
45
    PATCHABLE_TAIL_CALL = 30,
46
    PATCHABLE_EVENT_CALL  = 31,
47
    PATCHABLE_TYPED_EVENT_CALL  = 32,
48
    ICALL_BRANCH_FUNNEL = 33,
49
    G_ADD = 34,
50
    G_SUB = 35,
51
    G_MUL = 36,
52
    G_SDIV  = 37,
53
    G_UDIV  = 38,
54
    G_SREM  = 39,
55
    G_UREM  = 40,
56
    G_AND = 41,
57
    G_OR  = 42,
58
    G_XOR = 43,
59
    G_IMPLICIT_DEF  = 44,
60
    G_PHI = 45,
61
    G_FRAME_INDEX = 46,
62
    G_GLOBAL_VALUE  = 47,
63
    G_EXTRACT = 48,
64
    G_UNMERGE_VALUES  = 49,
65
    G_INSERT  = 50,
66
    G_MERGE_VALUES  = 51,
67
    G_PTRTOINT  = 52,
68
    G_INTTOPTR  = 53,
69
    G_BITCAST = 54,
70
    G_LOAD  = 55,
71
    G_SEXTLOAD  = 56,
72
    G_ZEXTLOAD  = 57,
73
    G_STORE = 58,
74
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59,
75
    G_ATOMIC_CMPXCHG  = 60,
76
    G_ATOMICRMW_XCHG  = 61,
77
    G_ATOMICRMW_ADD = 62,
78
    G_ATOMICRMW_SUB = 63,
79
    G_ATOMICRMW_AND = 64,
80
    G_ATOMICRMW_NAND  = 65,
81
    G_ATOMICRMW_OR  = 66,
82
    G_ATOMICRMW_XOR = 67,
83
    G_ATOMICRMW_MAX = 68,
84
    G_ATOMICRMW_MIN = 69,
85
    G_ATOMICRMW_UMAX  = 70,
86
    G_ATOMICRMW_UMIN  = 71,
87
    G_BRCOND  = 72,
88
    G_BRINDIRECT  = 73,
89
    G_INTRINSIC = 74,
90
    G_INTRINSIC_W_SIDE_EFFECTS  = 75,
91
    G_ANYEXT  = 76,
92
    G_TRUNC = 77,
93
    G_CONSTANT  = 78,
94
    G_FCONSTANT = 79,
95
    G_VASTART = 80,
96
    G_VAARG = 81,
97
    G_SEXT  = 82,
98
    G_ZEXT  = 83,
99
    G_SHL = 84,
100
    G_LSHR  = 85,
101
    G_ASHR  = 86,
102
    G_ICMP  = 87,
103
    G_FCMP  = 88,
104
    G_SELECT  = 89,
105
    G_UADDE = 90,
106
    G_USUBE = 91,
107
    G_SADDO = 92,
108
    G_SSUBO = 93,
109
    G_UMULO = 94,
110
    G_SMULO = 95,
111
    G_UMULH = 96,
112
    G_SMULH = 97,
113
    G_FADD  = 98,
114
    G_FSUB  = 99,
115
    G_FMUL  = 100,
116
    G_FMA = 101,
117
    G_FDIV  = 102,
118
    G_FREM  = 103,
119
    G_FPOW  = 104,
120
    G_FEXP  = 105,
121
    G_FEXP2 = 106,
122
    G_FLOG  = 107,
123
    G_FLOG2 = 108,
124
    G_FNEG  = 109,
125
    G_FPEXT = 110,
126
    G_FPTRUNC = 111,
127
    G_FPTOSI  = 112,
128
    G_FPTOUI  = 113,
129
    G_SITOFP  = 114,
130
    G_UITOFP  = 115,
131
    G_FABS  = 116,
132
    G_GEP = 117,
133
    G_PTR_MASK  = 118,
134
    G_BR  = 119,
135
    G_INSERT_VECTOR_ELT = 120,
136
    G_EXTRACT_VECTOR_ELT  = 121,
137
    G_SHUFFLE_VECTOR  = 122,
138
    G_BSWAP = 123,
139
    G_ADDRSPACE_CAST  = 124,
140
    BRANCH  = 125,
141
    BRANCH_COND_f32 = 126,
142
    BRANCH_COND_i32 = 127,
143
    BREAK = 128,
144
    BREAKC_f32  = 129,
145
    BREAKC_i32  = 130,
146
    BREAK_LOGICALNZ_f32 = 131,
147
    BREAK_LOGICALNZ_i32 = 132,
148
    BREAK_LOGICALZ_f32  = 133,
149
    BREAK_LOGICALZ_i32  = 134,
150
    CONST_COPY  = 135,
151
    CONTINUE  = 136,
152
    CONTINUEC_f32 = 137,
153
    CONTINUEC_i32 = 138,
154
    CONTINUE_LOGICALNZ_f32  = 139,
155
    CONTINUE_LOGICALNZ_i32  = 140,
156
    CONTINUE_LOGICALZ_f32 = 141,
157
    CONTINUE_LOGICALZ_i32 = 142,
158
    CUBE_eg_pseudo  = 143,
159
    CUBE_r600_pseudo  = 144,
160
    DEFAULT = 145,
161
    DOT_4 = 146,
162
    DUMMY_CHAIN = 147,
163
    ELSE  = 148,
164
    END = 149,
165
    ENDFUNC = 150,
166
    ENDIF = 151,
167
    ENDLOOP = 152,
168
    ENDMAIN = 153,
169
    ENDSWITCH = 154,
170
    FABS_R600 = 155,
171
    FNEG_R600 = 156,
172
    FUNC  = 157,
173
    IFC_f32 = 158,
174
    IFC_i32 = 159,
175
    IF_LOGICALNZ_f32  = 160,
176
    IF_LOGICALNZ_i32  = 161,
177
    IF_LOGICALZ_f32 = 162,
178
    IF_LOGICALZ_i32 = 163,
179
    IF_PREDICATE_SET  = 164,
180
    JUMP  = 165,
181
    JUMP_COND = 166,
182
    MASK_WRITE  = 167,
183
    MOV_IMM_F32 = 168,
184
    MOV_IMM_GLOBAL_ADDR = 169,
185
    MOV_IMM_I32 = 170,
186
    PRED_X  = 171,
187
    R600_EXTRACT_ELT_V2 = 172,
188
    R600_EXTRACT_ELT_V4 = 173,
189
    R600_INSERT_ELT_V2  = 174,
190
    R600_INSERT_ELT_V4  = 175,
191
    R600_RegisterLoad = 176,
192
    R600_RegisterStore  = 177,
193
    RETDYN  = 178,
194
    RETURN  = 179,
195
    TXD = 180,
196
    TXD_SHADOW  = 181,
197
    WHILELOOP = 182,
198
    ADD = 183,
199
    ADDC_UINT = 184,
200
    ADD_INT = 185,
201
    ALU_CLAUSE  = 186,
202
    AND_INT = 187,
203
    ASHR_eg = 188,
204
    ASHR_r600 = 189,
205
    BCNT_INT  = 190,
206
    BFE_INT_eg  = 191,
207
    BFE_UINT_eg = 192,
208
    BFI_INT_eg  = 193,
209
    BFM_INT_eg  = 194,
210
    BIT_ALIGN_INT_eg  = 195,
211
    CEIL  = 196,
212
    CF_ALU  = 197,
213
    CF_ALU_BREAK  = 198,
214
    CF_ALU_CONTINUE = 199,
215
    CF_ALU_ELSE_AFTER = 200,
216
    CF_ALU_POP_AFTER  = 201,
217
    CF_ALU_PUSH_BEFORE  = 202,
218
    CF_CALL_FS_EG = 203,
219
    CF_CALL_FS_R600 = 204,
220
    CF_CONTINUE_EG  = 205,
221
    CF_CONTINUE_R600  = 206,
222
    CF_ELSE_EG  = 207,
223
    CF_ELSE_R600  = 208,
224
    CF_END_CM = 209,
225
    CF_END_EG = 210,
226
    CF_END_R600 = 211,
227
    CF_JUMP_EG  = 212,
228
    CF_JUMP_R600  = 213,
229
    CF_PUSH_EG  = 214,
230
    CF_PUSH_ELSE_R600 = 215,
231
    CF_TC_EG  = 216,
232
    CF_TC_R600  = 217,
233
    CF_VC_EG  = 218,
234
    CF_VC_R600  = 219,
235
    CNDE_INT  = 220,
236
    CNDE_eg = 221,
237
    CNDE_r600 = 222,
238
    CNDGE_INT = 223,
239
    CNDGE_eg  = 224,
240
    CNDGE_r600  = 225,
241
    CNDGT_INT = 226,
242
    CNDGT_eg  = 227,
243
    CNDGT_r600  = 228,
244
    COS_cm  = 229,
245
    COS_eg  = 230,
246
    COS_r600  = 231,
247
    COS_r700  = 232,
248
    CUBE_eg_real  = 233,
249
    CUBE_r600_real  = 234,
250
    DOT4_eg = 235,
251
    DOT4_r600 = 236,
252
    EG_ExportBuf  = 237,
253
    EG_ExportSwz  = 238,
254
    END_LOOP_EG = 239,
255
    END_LOOP_R600 = 240,
256
    EXP_IEEE_cm = 241,
257
    EXP_IEEE_eg = 242,
258
    EXP_IEEE_r600 = 243,
259
    FETCH_CLAUSE  = 244,
260
    FFBH_UINT = 245,
261
    FFBL_INT  = 246,
262
    FLOOR = 247,
263
    FLT16_TO_FLT32  = 248,
264
    FLT32_TO_FLT16  = 249,
265
    FLT_TO_INT_eg = 250,
266
    FLT_TO_INT_r600 = 251,
267
    FLT_TO_UINT_eg  = 252,
268
    FLT_TO_UINT_r600  = 253,
269
    FMA_eg  = 254,
270
    FRACT = 255,
271
    GROUP_BARRIER = 256,
272
    INTERP_LOAD_P0  = 257,
273
    INTERP_PAIR_XY  = 258,
274
    INTERP_PAIR_ZW  = 259,
275
    INTERP_VEC_LOAD = 260,
276
    INTERP_XY = 261,
277
    INTERP_ZW = 262,
278
    INT_TO_FLT_eg = 263,
279
    INT_TO_FLT_r600 = 264,
280
    KILLGT  = 265,
281
    LDS_ADD = 266,
282
    LDS_ADD_RET = 267,
283
    LDS_AND = 268,
284
    LDS_AND_RET = 269,
285
    LDS_BYTE_READ_RET = 270,
286
    LDS_BYTE_WRITE  = 271,
287
    LDS_CMPST = 272,
288
    LDS_CMPST_RET = 273,
289
    LDS_MAX_INT = 274,
290
    LDS_MAX_INT_RET = 275,
291
    LDS_MAX_UINT  = 276,
292
    LDS_MAX_UINT_RET  = 277,
293
    LDS_MIN_INT = 278,
294
    LDS_MIN_INT_RET = 279,
295
    LDS_MIN_UINT  = 280,
296
    LDS_MIN_UINT_RET  = 281,
297
    LDS_OR  = 282,
298
    LDS_OR_RET  = 283,
299
    LDS_READ_RET  = 284,
300
    LDS_SHORT_READ_RET  = 285,
301
    LDS_SHORT_WRITE = 286,
302
    LDS_SUB = 287,
303
    LDS_SUB_RET = 288,
304
    LDS_UBYTE_READ_RET  = 289,
305
    LDS_USHORT_READ_RET = 290,
306
    LDS_WRITE = 291,
307
    LDS_WRXCHG  = 292,
308
    LDS_WRXCHG_RET  = 293,
309
    LDS_XOR = 294,
310
    LDS_XOR_RET = 295,
311
    LITERALS  = 296,
312
    LOG_CLAMPED_eg  = 297,
313
    LOG_CLAMPED_r600  = 298,
314
    LOG_IEEE_cm = 299,
315
    LOG_IEEE_eg = 300,
316
    LOG_IEEE_r600 = 301,
317
    LOOP_BREAK_EG = 302,
318
    LOOP_BREAK_R600 = 303,
319
    LSHL_eg = 304,
320
    LSHL_r600 = 305,
321
    LSHR_eg = 306,
322
    LSHR_r600 = 307,
323
    MAX = 308,
324
    MAX_DX10  = 309,
325
    MAX_INT = 310,
326
    MAX_UINT  = 311,
327
    MIN = 312,
328
    MIN_DX10  = 313,
329
    MIN_INT = 314,
330
    MIN_UINT  = 315,
331
    MOV = 316,
332
    MOVA_INT_eg = 317,
333
    MUL = 318,
334
    MULADD_IEEE_eg  = 319,
335
    MULADD_IEEE_r600  = 320,
336
    MULADD_INT24_cm = 321,
337
    MULADD_UINT24_eg  = 322,
338
    MULADD_eg = 323,
339
    MULADD_r600 = 324,
340
    MULHI_INT_cm  = 325,
341
    MULHI_INT_cm24  = 326,
342
    MULHI_INT_eg  = 327,
343
    MULHI_INT_r600  = 328,
344
    MULHI_UINT24_eg = 329,
345
    MULHI_UINT_cm = 330,
346
    MULHI_UINT_cm24 = 331,
347
    MULHI_UINT_eg = 332,
348
    MULHI_UINT_r600 = 333,
349
    MULLO_INT_cm  = 334,
350
    MULLO_INT_eg  = 335,
351
    MULLO_INT_r600  = 336,
352
    MULLO_UINT_cm = 337,
353
    MULLO_UINT_eg = 338,
354
    MULLO_UINT_r600 = 339,
355
    MUL_IEEE  = 340,
356
    MUL_INT24_cm  = 341,
357
    MUL_LIT_eg  = 342,
358
    MUL_LIT_r600  = 343,
359
    MUL_UINT24_eg = 344,
360
    NOT_INT = 345,
361
    OR_INT  = 346,
362
    PAD = 347,
363
    POP_EG  = 348,
364
    POP_R600  = 349,
365
    PRED_SETE = 350,
366
    PRED_SETE_INT = 351,
367
    PRED_SETGE  = 352,
368
    PRED_SETGE_INT  = 353,
369
    PRED_SETGT  = 354,
370
    PRED_SETGT_INT  = 355,
371
    PRED_SETNE  = 356,
372
    PRED_SETNE_INT  = 357,
373
    R600_ExportBuf  = 358,
374
    R600_ExportSwz  = 359,
375
    RAT_ATOMIC_ADD_NORET  = 360,
376
    RAT_ATOMIC_ADD_RTN  = 361,
377
    RAT_ATOMIC_AND_NORET  = 362,
378
    RAT_ATOMIC_AND_RTN  = 363,
379
    RAT_ATOMIC_CMPXCHG_INT_NORET  = 364,
380
    RAT_ATOMIC_CMPXCHG_INT_RTN  = 365,
381
    RAT_ATOMIC_DEC_UINT_NORET = 366,
382
    RAT_ATOMIC_DEC_UINT_RTN = 367,
383
    RAT_ATOMIC_INC_UINT_NORET = 368,
384
    RAT_ATOMIC_INC_UINT_RTN = 369,
385
    RAT_ATOMIC_MAX_INT_NORET  = 370,
386
    RAT_ATOMIC_MAX_INT_RTN  = 371,
387
    RAT_ATOMIC_MAX_UINT_NORET = 372,
388
    RAT_ATOMIC_MAX_UINT_RTN = 373,
389
    RAT_ATOMIC_MIN_INT_NORET  = 374,
390
    RAT_ATOMIC_MIN_INT_RTN  = 375,
391
    RAT_ATOMIC_MIN_UINT_NORET = 376,
392
    RAT_ATOMIC_MIN_UINT_RTN = 377,
393
    RAT_ATOMIC_OR_NORET = 378,
394
    RAT_ATOMIC_OR_RTN = 379,
395
    RAT_ATOMIC_RSUB_NORET = 380,
396
    RAT_ATOMIC_RSUB_RTN = 381,
397
    RAT_ATOMIC_SUB_NORET  = 382,
398
    RAT_ATOMIC_SUB_RTN  = 383,
399
    RAT_ATOMIC_XCHG_INT_NORET = 384,
400
    RAT_ATOMIC_XCHG_INT_RTN = 385,
401
    RAT_ATOMIC_XOR_NORET  = 386,
402
    RAT_ATOMIC_XOR_RTN  = 387,
403
    RAT_MSKOR = 388,
404
    RAT_STORE_DWORD128  = 389,
405
    RAT_STORE_DWORD32 = 390,
406
    RAT_STORE_DWORD64 = 391,
407
    RAT_STORE_TYPED_cm  = 392,
408
    RAT_STORE_TYPED_eg  = 393,
409
    RAT_WRITE_CACHELESS_128_eg  = 394,
410
    RAT_WRITE_CACHELESS_32_eg = 395,
411
    RAT_WRITE_CACHELESS_64_eg = 396,
412
    RECIPSQRT_CLAMPED_cm  = 397,
413
    RECIPSQRT_CLAMPED_eg  = 398,
414
    RECIPSQRT_CLAMPED_r600  = 399,
415
    RECIPSQRT_IEEE_cm = 400,
416
    RECIPSQRT_IEEE_eg = 401,
417
    RECIPSQRT_IEEE_r600 = 402,
418
    RECIP_CLAMPED_cm  = 403,
419
    RECIP_CLAMPED_eg  = 404,
420
    RECIP_CLAMPED_r600  = 405,
421
    RECIP_IEEE_cm = 406,
422
    RECIP_IEEE_eg = 407,
423
    RECIP_IEEE_r600 = 408,
424
    RECIP_UINT_eg = 409,
425
    RECIP_UINT_r600 = 410,
426
    RNDNE = 411,
427
    SETE  = 412,
428
    SETE_DX10 = 413,
429
    SETE_INT  = 414,
430
    SETGE_DX10  = 415,
431
    SETGE_INT = 416,
432
    SETGE_UINT  = 417,
433
    SETGT_DX10  = 418,
434
    SETGT_INT = 419,
435
    SETGT_UINT  = 420,
436
    SETNE_DX10  = 421,
437
    SETNE_INT = 422,
438
    SGE = 423,
439
    SGT = 424,
440
    SIN_cm  = 425,
441
    SIN_eg  = 426,
442
    SIN_r600  = 427,
443
    SIN_r700  = 428,
444
    SNE = 429,
445
    SUBB_UINT = 430,
446
    SUB_INT = 431,
447
    TEX_GET_GRADIENTS_H = 432,
448
    TEX_GET_GRADIENTS_V = 433,
449
    TEX_GET_TEXTURE_RESINFO = 434,
450
    TEX_LD  = 435,
451
    TEX_LDPTR = 436,
452
    TEX_SAMPLE  = 437,
453
    TEX_SAMPLE_C  = 438,
454
    TEX_SAMPLE_C_G  = 439,
455
    TEX_SAMPLE_C_L  = 440,
456
    TEX_SAMPLE_C_LB = 441,
457
    TEX_SAMPLE_G  = 442,
458
    TEX_SAMPLE_L  = 443,
459
    TEX_SAMPLE_LB = 444,
460
    TEX_SET_GRADIENTS_H = 445,
461
    TEX_SET_GRADIENTS_V = 446,
462
    TEX_VTX_CONSTBUF  = 447,
463
    TEX_VTX_TEXBUF  = 448,
464
    TRUNC = 449,
465
    UINT_TO_FLT_eg  = 450,
466
    UINT_TO_FLT_r600  = 451,
467
    VTX_READ_128_cm = 452,
468
    VTX_READ_128_eg = 453,
469
    VTX_READ_16_cm  = 454,
470
    VTX_READ_16_eg  = 455,
471
    VTX_READ_32_cm  = 456,
472
    VTX_READ_32_eg  = 457,
473
    VTX_READ_64_cm  = 458,
474
    VTX_READ_64_eg  = 459,
475
    VTX_READ_8_cm = 460,
476
    VTX_READ_8_eg = 461,
477
    WHILE_LOOP_EG = 462,
478
    WHILE_LOOP_R600 = 463,
479
    XOR_INT = 464,
480
    INSTRUCTION_LIST_END = 465
481
  };
482
483
} // end R600 namespace
484
} // end llvm namespace
485
#endif // GET_INSTRINFO_ENUM
486
487
#ifdef GET_INSTRINFO_SCHED_ENUM
488
#undef GET_INSTRINFO_SCHED_ENUM
489
namespace llvm {
490
491
namespace R600 {
492
namespace Sched {
493
  enum {
494
    NoInstrModel  = 0,
495
    NullALU = 1,
496
    VecALU  = 2,
497
    AnyALU  = 3,
498
    TransALU  = 4,
499
    XALU  = 5,
500
    SCHED_LIST_END = 6
501
  };
502
} // end Sched namespace
503
} // end R600 namespace
504
} // end llvm namespace
505
#endif // GET_INSTRINFO_SCHED_ENUM
506
507
#ifdef GET_INSTRINFO_MC_DESC
508
#undef GET_INSTRINFO_MC_DESC
509
namespace llvm {
510
511
512
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
513
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
514
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
515
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
516
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
517
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
518
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
519
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
520
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
521
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
522
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
523
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
524
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
525
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
526
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
527
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
528
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
529
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
530
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
531
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
532
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
533
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
534
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
535
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
536
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
537
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
538
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
539
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
540
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
541
static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
542
static const MCOperandInfo OperandInfo32[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
543
static const MCOperandInfo OperandInfo33[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
544
static const MCOperandInfo OperandInfo34[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
545
static const MCOperandInfo OperandInfo35[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
546
static const MCOperandInfo OperandInfo36[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
547
static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
548
static const MCOperandInfo OperandInfo38[] = { { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
549
static const MCOperandInfo OperandInfo39[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
550
static const MCOperandInfo OperandInfo40[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
551
static const MCOperandInfo OperandInfo41[] = { { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
552
static const MCOperandInfo OperandInfo42[] = { { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
553
static const MCOperandInfo OperandInfo43[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
554
static const MCOperandInfo OperandInfo44[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
555
static const MCOperandInfo OperandInfo45[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
556
static const MCOperandInfo OperandInfo46[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
557
static const MCOperandInfo OperandInfo47[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
558
static const MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
559
static const MCOperandInfo OperandInfo49[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
560
static const MCOperandInfo OperandInfo50[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
561
static const MCOperandInfo OperandInfo51[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
562
static const MCOperandInfo OperandInfo52[] = { { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
563
static const MCOperandInfo OperandInfo53[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
564
static const MCOperandInfo OperandInfo54[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
565
static const MCOperandInfo OperandInfo55[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
566
static const MCOperandInfo OperandInfo56[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
567
static const MCOperandInfo OperandInfo57[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
568
static const MCOperandInfo OperandInfo58[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
569
static const MCOperandInfo OperandInfo59[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
570
static const MCOperandInfo OperandInfo60[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
571
static const MCOperandInfo OperandInfo61[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
572
static const MCOperandInfo OperandInfo62[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
573
static const MCOperandInfo OperandInfo63[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
574
static const MCOperandInfo OperandInfo64[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
575
static const MCOperandInfo OperandInfo65[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
576
static const MCOperandInfo OperandInfo66[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
577
static const MCOperandInfo OperandInfo67[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
578
static const MCOperandInfo OperandInfo68[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
579
static const MCOperandInfo OperandInfo69[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
580
static const MCOperandInfo OperandInfo70[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
581
static const MCOperandInfo OperandInfo71[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
582
583
extern const MCInstrDesc R600Insts[] = {
584
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
585
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
586
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
587
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
588
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
589
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
590
  { 6,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
591
  { 7,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
592
  { 8,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
593
  { 9,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
594
  { 10, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
595
  { 11, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
596
  { 12, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
597
  { 13, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
598
  { 14, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
599
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
600
  { 16, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
601
  { 17, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
602
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
603
  { 19, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
604
  { 20, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
605
  { 21, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
606
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
607
  { 23, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
608
  { 24, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
609
  { 25, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
610
  { 26, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
611
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
612
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
613
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
614
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
615
  { 31, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
616
  { 32, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
617
  { 33, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
618
  { 34, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
619
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
620
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
621
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
622
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
623
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
624
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
625
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
626
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
627
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
628
  { 44, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
629
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
630
  { 46, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
631
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
632
  { 48, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
633
  { 49, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
634
  { 50, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
635
  { 51, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
636
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
637
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
638
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
639
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_LOAD
640
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_SEXTLOAD
641
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_ZEXTLOAD
642
  { 58, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_STORE
643
  { 59, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
644
  { 60, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #60 = G_ATOMIC_CMPXCHG
645
  { 61, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #61 = G_ATOMICRMW_XCHG
646
  { 62, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMICRMW_ADD
647
  { 63, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_SUB
648
  { 64, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_AND
649
  { 65, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_NAND
650
  { 66, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_OR
651
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XOR
652
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_MAX
653
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_MIN
654
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_UMAX
655
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_UMIN
656
  { 72, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #72 = G_BRCOND
657
  { 73, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #73 = G_BRINDIRECT
658
  { 74, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #74 = G_INTRINSIC
659
  { 75, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #75 = G_INTRINSIC_W_SIDE_EFFECTS
660
  { 76, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #76 = G_ANYEXT
661
  { 77, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #77 = G_TRUNC
662
  { 78, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #78 = G_CONSTANT
663
  { 79, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #79 = G_FCONSTANT
664
  { 80, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #80 = G_VASTART
665
  { 81, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #81 = G_VAARG
666
  { 82, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_SEXT
667
  { 83, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_ZEXT
668
  { 84, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #84 = G_SHL
669
  { 85, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #85 = G_LSHR
670
  { 86, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_ASHR
671
  { 87, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = G_ICMP
672
  { 88, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = G_FCMP
673
  { 89, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #89 = G_SELECT
674
  { 90, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_UADDE
675
  { 91, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_USUBE
676
  { 92, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #92 = G_SADDO
677
  { 93, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #93 = G_SSUBO
678
  { 94, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #94 = G_UMULO
679
  { 95, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #95 = G_SMULO
680
  { 96, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #96 = G_UMULH
681
  { 97, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #97 = G_SMULH
682
  { 98, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #98 = G_FADD
683
  { 99, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #99 = G_FSUB
684
  { 100,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #100 = G_FMUL
685
  { 101,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #101 = G_FMA
686
  { 102,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_FDIV
687
  { 103,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_FREM
688
  { 104,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FPOW
689
  { 105,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #105 = G_FEXP
690
  { 106,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #106 = G_FEXP2
691
  { 107,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FLOG
692
  { 108,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #108 = G_FLOG2
693
  { 109,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #109 = G_FNEG
694
  { 110,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #110 = G_FPEXT
695
  { 111,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #111 = G_FPTRUNC
696
  { 112,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #112 = G_FPTOSI
697
  { 113,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #113 = G_FPTOUI
698
  { 114,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #114 = G_SITOFP
699
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #115 = G_UITOFP
700
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #116 = G_FABS
701
  { 117,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #117 = G_GEP
702
  { 118,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #118 = G_PTR_MASK
703
  { 119,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #119 = G_BR
704
  { 120,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #120 = G_INSERT_VECTOR_ELT
705
  { 121,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #121 = G_EXTRACT_VECTOR_ELT
706
  { 122,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #122 = G_SHUFFLE_VECTOR
707
  { 123,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #123 = G_BSWAP
708
  { 124,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #124 = G_ADDRSPACE_CAST
709
  { 125,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #125 = BRANCH
710
  { 126,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #126 = BRANCH_COND_f32
711
  { 127,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #127 = BRANCH_COND_i32
712
  { 128,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #128 = BREAK
713
  { 129,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #129 = BREAKC_f32
714
  { 130,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #130 = BREAKC_i32
715
  { 131,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #131 = BREAK_LOGICALNZ_f32
716
  { 132,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #132 = BREAK_LOGICALNZ_i32
717
  { 133,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #133 = BREAK_LOGICALZ_f32
718
  { 134,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #134 = BREAK_LOGICALZ_i32
719
  { 135,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #135 = CONST_COPY
720
  { 136,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #136 = CONTINUE
721
  { 137,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #137 = CONTINUEC_f32
722
  { 138,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #138 = CONTINUEC_i32
723
  { 139,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #139 = CONTINUE_LOGICALNZ_f32
724
  { 140,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #140 = CONTINUE_LOGICALNZ_i32
725
  { 141,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #141 = CONTINUE_LOGICALZ_f32
726
  { 142,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #142 = CONTINUE_LOGICALZ_i32
727
  { 143,  2,  1,  0,  2,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #143 = CUBE_eg_pseudo
728
  { 144,  2,  1,  0,  2,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #144 = CUBE_r600_pseudo
729
  { 145,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #145 = DEFAULT
730
  { 146,  71, 1,  0,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #146 = DOT_4
731
  { 147,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #147 = DUMMY_CHAIN
732
  { 148,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #148 = ELSE
733
  { 149,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #149 = END
734
  { 150,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #150 = ENDFUNC
735
  { 151,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #151 = ENDIF
736
  { 152,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #152 = ENDLOOP
737
  { 153,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #153 = ENDMAIN
738
  { 154,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #154 = ENDSWITCH
739
  { 155,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #155 = FABS_R600
740
  { 156,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #156 = FNEG_R600
741
  { 157,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #157 = FUNC
742
  { 158,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #158 = IFC_f32
743
  { 159,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #159 = IFC_i32
744
  { 160,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #160 = IF_LOGICALNZ_f32
745
  { 161,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #161 = IF_LOGICALNZ_i32
746
  { 162,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #162 = IF_LOGICALZ_f32
747
  { 163,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #163 = IF_LOGICALZ_i32
748
  { 164,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #164 = IF_PREDICATE_SET
749
  { 165,  1,  0,  0,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #165 = JUMP
750
  { 166,  2,  0,  0,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #166 = JUMP_COND
751
  { 167,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #167 = MASK_WRITE
752
  { 168,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #168 = MOV_IMM_F32
753
  { 169,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #169 = MOV_IMM_GLOBAL_ADDR
754
  { 170,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #170 = MOV_IMM_I32
755
  { 171,  4,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #171 = PRED_X
756
  { 172,  3,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #172 = R600_EXTRACT_ELT_V2
757
  { 173,  3,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #173 = R600_EXTRACT_ELT_V4
758
  { 174,  4,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #174 = R600_INSERT_ELT_V2
759
  { 175,  4,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #175 = R600_INSERT_ELT_V4
760
  { 176,  4,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #176 = R600_RegisterLoad
761
  { 177,  4,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #177 = R600_RegisterStore
762
  { 178,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #178 = RETDYN
763
  { 179,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #179 = RETURN
764
  { 180,  7,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #180 = TXD
765
  { 181,  7,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #181 = TXD_SHADOW
766
  { 182,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #182 = WHILELOOP
767
  { 183,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #183 = ADD
768
  { 184,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #184 = ADDC_UINT
769
  { 185,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #185 = ADD_INT
770
  { 186,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #186 = ALU_CLAUSE
771
  { 187,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #187 = AND_INT
772
  { 188,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #188 = ASHR_eg
773
  { 189,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #189 = ASHR_r600
774
  { 190,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #190 = BCNT_INT
775
  { 191,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #191 = BFE_INT_eg
776
  { 192,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #192 = BFE_UINT_eg
777
  { 193,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #193 = BFI_INT_eg
778
  { 194,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #194 = BFM_INT_eg
779
  { 195,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #195 = BIT_ALIGN_INT_eg
780
  { 196,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #196 = CEIL
781
  { 197,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #197 = CF_ALU
782
  { 198,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #198 = CF_ALU_BREAK
783
  { 199,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #199 = CF_ALU_CONTINUE
784
  { 200,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #200 = CF_ALU_ELSE_AFTER
785
  { 201,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #201 = CF_ALU_POP_AFTER
786
  { 202,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #202 = CF_ALU_PUSH_BEFORE
787
  { 203,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #203 = CF_CALL_FS_EG
788
  { 204,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #204 = CF_CALL_FS_R600
789
  { 205,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #205 = CF_CONTINUE_EG
790
  { 206,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #206 = CF_CONTINUE_R600
791
  { 207,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #207 = CF_ELSE_EG
792
  { 208,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #208 = CF_ELSE_R600
793
  { 209,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #209 = CF_END_CM
794
  { 210,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #210 = CF_END_EG
795
  { 211,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #211 = CF_END_R600
796
  { 212,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #212 = CF_JUMP_EG
797
  { 213,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #213 = CF_JUMP_R600
798
  { 214,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #214 = CF_PUSH_EG
799
  { 215,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #215 = CF_PUSH_ELSE_R600
800
  { 216,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #216 = CF_TC_EG
801
  { 217,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #217 = CF_TC_R600
802
  { 218,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #218 = CF_VC_EG
803
  { 219,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #219 = CF_VC_R600
804
  { 220,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #220 = CNDE_INT
805
  { 221,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #221 = CNDE_eg
806
  { 222,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #222 = CNDE_r600
807
  { 223,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #223 = CNDGE_INT
808
  { 224,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #224 = CNDGE_eg
809
  { 225,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #225 = CNDGE_r600
810
  { 226,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #226 = CNDGT_INT
811
  { 227,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #227 = CNDGT_eg
812
  { 228,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #228 = CNDGT_r600
813
  { 229,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4650ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #229 = COS_cm
814
  { 230,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #230 = COS_eg
815
  { 231,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #231 = COS_r600
816
  { 232,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #232 = COS_r700
817
  { 233,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #233 = CUBE_eg_real
818
  { 234,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #234 = CUBE_r600_real
819
  { 235,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #235 = DOT4_eg
820
  { 236,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #236 = DOT4_r600
821
  { 237,  7,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #237 = EG_ExportBuf
822
  { 238,  9,  0,  0,  1,  0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #238 = EG_ExportSwz
823
  { 239,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #239 = END_LOOP_EG
824
  { 240,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #240 = END_LOOP_R600
825
  { 241,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #241 = EXP_IEEE_cm
826
  { 242,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #242 = EXP_IEEE_eg
827
  { 243,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #243 = EXP_IEEE_r600
828
  { 244,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #244 = FETCH_CLAUSE
829
  { 245,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #245 = FFBH_UINT
830
  { 246,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #246 = FFBL_INT
831
  { 247,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #247 = FLOOR
832
  { 248,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #248 = FLT16_TO_FLT32
833
  { 249,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #249 = FLT32_TO_FLT16
834
  { 250,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #250 = FLT_TO_INT_eg
835
  { 251,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #251 = FLT_TO_INT_r600
836
  { 252,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #252 = FLT_TO_UINT_eg
837
  { 253,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #253 = FLT_TO_UINT_r600
838
  { 254,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #254 = FMA_eg
839
  { 255,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #255 = FRACT
840
  { 256,  0,  0,  0,  3,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #256 = GROUP_BARRIER
841
  { 257,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #257 = INTERP_LOAD_P0
842
  { 258,  5,  2,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #258 = INTERP_PAIR_XY
843
  { 259,  5,  2,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #259 = INTERP_PAIR_ZW
844
  { 260,  2,  1,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #260 = INTERP_VEC_LOAD
845
  { 261,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #261 = INTERP_XY
846
  { 262,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #262 = INTERP_ZW
847
  { 263,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #263 = INT_TO_FLT_eg
848
  { 264,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #264 = INT_TO_FLT_r600
849
  { 265,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #265 = KILLGT
850
  { 266,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #266 = LDS_ADD
851
  { 267,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #267 = LDS_ADD_RET
852
  { 268,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #268 = LDS_AND
853
  { 269,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #269 = LDS_AND_RET
854
  { 270,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #270 = LDS_BYTE_READ_RET
855
  { 271,  9,  0,  0,  5,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #271 = LDS_BYTE_WRITE
856
  { 272,  12, 0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #272 = LDS_CMPST
857
  { 273,  13, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #273 = LDS_CMPST_RET
858
  { 274,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #274 = LDS_MAX_INT
859
  { 275,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #275 = LDS_MAX_INT_RET
860
  { 276,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #276 = LDS_MAX_UINT
861
  { 277,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #277 = LDS_MAX_UINT_RET
862
  { 278,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #278 = LDS_MIN_INT
863
  { 279,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #279 = LDS_MIN_INT_RET
864
  { 280,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #280 = LDS_MIN_UINT
865
  { 281,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #281 = LDS_MIN_UINT_RET
866
  { 282,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #282 = LDS_OR
867
  { 283,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #283 = LDS_OR_RET
868
  { 284,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #284 = LDS_READ_RET
869
  { 285,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #285 = LDS_SHORT_READ_RET
870
  { 286,  9,  0,  0,  5,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #286 = LDS_SHORT_WRITE
871
  { 287,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #287 = LDS_SUB
872
  { 288,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #288 = LDS_SUB_RET
873
  { 289,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #289 = LDS_UBYTE_READ_RET
874
  { 290,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #290 = LDS_USHORT_READ_RET
875
  { 291,  9,  0,  0,  5,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #291 = LDS_WRITE
876
  { 292,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #292 = LDS_WRXCHG
877
  { 293,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #293 = LDS_WRXCHG_RET
878
  { 294,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #294 = LDS_XOR
879
  { 295,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #295 = LDS_XOR_RET
880
  { 296,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #296 = LITERALS
881
  { 297,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #297 = LOG_CLAMPED_eg
882
  { 298,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #298 = LOG_CLAMPED_r600
883
  { 299,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #299 = LOG_IEEE_cm
884
  { 300,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #300 = LOG_IEEE_eg
885
  { 301,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #301 = LOG_IEEE_r600
886
  { 302,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #302 = LOOP_BREAK_EG
887
  { 303,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #303 = LOOP_BREAK_R600
888
  { 304,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #304 = LSHL_eg
889
  { 305,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #305 = LSHL_r600
890
  { 306,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #306 = LSHR_eg
891
  { 307,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #307 = LSHR_r600
892
  { 308,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #308 = MAX
893
  { 309,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #309 = MAX_DX10
894
  { 310,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #310 = MAX_INT
895
  { 311,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #311 = MAX_UINT
896
  { 312,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #312 = MIN
897
  { 313,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #313 = MIN_DX10
898
  { 314,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #314 = MIN_INT
899
  { 315,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #315 = MIN_UINT
900
  { 316,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #316 = MOV
901
  { 317,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #317 = MOVA_INT_eg
902
  { 318,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #318 = MUL
903
  { 319,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #319 = MULADD_IEEE_eg
904
  { 320,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #320 = MULADD_IEEE_r600
905
  { 321,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #321 = MULADD_INT24_cm
906
  { 322,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #322 = MULADD_UINT24_eg
907
  { 323,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #323 = MULADD_eg
908
  { 324,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #324 = MULADD_r600
909
  { 325,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #325 = MULHI_INT_cm
910
  { 326,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #326 = MULHI_INT_cm24
911
  { 327,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #327 = MULHI_INT_eg
912
  { 328,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #328 = MULHI_INT_r600
913
  { 329,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #329 = MULHI_UINT24_eg
914
  { 330,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #330 = MULHI_UINT_cm
915
  { 331,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #331 = MULHI_UINT_cm24
916
  { 332,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #332 = MULHI_UINT_eg
917
  { 333,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #333 = MULHI_UINT_r600
918
  { 334,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #334 = MULLO_INT_cm
919
  { 335,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #335 = MULLO_INT_eg
920
  { 336,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #336 = MULLO_INT_r600
921
  { 337,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #337 = MULLO_UINT_cm
922
  { 338,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #338 = MULLO_UINT_eg
923
  { 339,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #339 = MULLO_UINT_r600
924
  { 340,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #340 = MUL_IEEE
925
  { 341,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #341 = MUL_INT24_cm
926
  { 342,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #342 = MUL_LIT_eg
927
  { 343,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #343 = MUL_LIT_r600
928
  { 344,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #344 = MUL_UINT24_eg
929
  { 345,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #345 = NOT_INT
930
  { 346,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #346 = OR_INT
931
  { 347,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #347 = PAD
932
  { 348,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #348 = POP_EG
933
  { 349,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #349 = POP_R600
934
  { 350,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #350 = PRED_SETE
935
  { 351,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #351 = PRED_SETE_INT
936
  { 352,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #352 = PRED_SETGE
937
  { 353,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #353 = PRED_SETGE_INT
938
  { 354,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #354 = PRED_SETGT
939
  { 355,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #355 = PRED_SETGT_INT
940
  { 356,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #356 = PRED_SETNE
941
  { 357,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #357 = PRED_SETNE_INT
942
  { 358,  7,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #358 = R600_ExportBuf
943
  { 359,  9,  0,  0,  1,  0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #359 = R600_ExportSwz
944
  { 360,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #360 = RAT_ATOMIC_ADD_NORET
945
  { 361,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #361 = RAT_ATOMIC_ADD_RTN
946
  { 362,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #362 = RAT_ATOMIC_AND_NORET
947
  { 363,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #363 = RAT_ATOMIC_AND_RTN
948
  { 364,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #364 = RAT_ATOMIC_CMPXCHG_INT_NORET
949
  { 365,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #365 = RAT_ATOMIC_CMPXCHG_INT_RTN
950
  { 366,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #366 = RAT_ATOMIC_DEC_UINT_NORET
951
  { 367,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #367 = RAT_ATOMIC_DEC_UINT_RTN
952
  { 368,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #368 = RAT_ATOMIC_INC_UINT_NORET
953
  { 369,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #369 = RAT_ATOMIC_INC_UINT_RTN
954
  { 370,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #370 = RAT_ATOMIC_MAX_INT_NORET
955
  { 371,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #371 = RAT_ATOMIC_MAX_INT_RTN
956
  { 372,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #372 = RAT_ATOMIC_MAX_UINT_NORET
957
  { 373,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #373 = RAT_ATOMIC_MAX_UINT_RTN
958
  { 374,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #374 = RAT_ATOMIC_MIN_INT_NORET
959
  { 375,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #375 = RAT_ATOMIC_MIN_INT_RTN
960
  { 376,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #376 = RAT_ATOMIC_MIN_UINT_NORET
961
  { 377,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #377 = RAT_ATOMIC_MIN_UINT_RTN
962
  { 378,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #378 = RAT_ATOMIC_OR_NORET
963
  { 379,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #379 = RAT_ATOMIC_OR_RTN
964
  { 380,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #380 = RAT_ATOMIC_RSUB_NORET
965
  { 381,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #381 = RAT_ATOMIC_RSUB_RTN
966
  { 382,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #382 = RAT_ATOMIC_SUB_NORET
967
  { 383,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #383 = RAT_ATOMIC_SUB_RTN
968
  { 384,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #384 = RAT_ATOMIC_XCHG_INT_NORET
969
  { 385,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #385 = RAT_ATOMIC_XCHG_INT_RTN
970
  { 386,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #386 = RAT_ATOMIC_XOR_NORET
971
  { 387,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #387 = RAT_ATOMIC_XOR_RTN
972
  { 388,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #388 = RAT_MSKOR
973
  { 389,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #389 = RAT_STORE_DWORD128
974
  { 390,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #390 = RAT_STORE_DWORD32
975
  { 391,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #391 = RAT_STORE_DWORD64
976
  { 392,  4,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #392 = RAT_STORE_TYPED_cm
977
  { 393,  4,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #393 = RAT_STORE_TYPED_eg
978
  { 394,  3,  0,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #394 = RAT_WRITE_CACHELESS_128_eg
979
  { 395,  3,  0,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #395 = RAT_WRITE_CACHELESS_32_eg
980
  { 396,  3,  0,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #396 = RAT_WRITE_CACHELESS_64_eg
981
  { 397,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #397 = RECIPSQRT_CLAMPED_cm
982
  { 398,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #398 = RECIPSQRT_CLAMPED_eg
983
  { 399,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #399 = RECIPSQRT_CLAMPED_r600
984
  { 400,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #400 = RECIPSQRT_IEEE_cm
985
  { 401,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #401 = RECIPSQRT_IEEE_eg
986
  { 402,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #402 = RECIPSQRT_IEEE_r600
987
  { 403,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #403 = RECIP_CLAMPED_cm
988
  { 404,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #404 = RECIP_CLAMPED_eg
989
  { 405,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #405 = RECIP_CLAMPED_r600
990
  { 406,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #406 = RECIP_IEEE_cm
991
  { 407,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #407 = RECIP_IEEE_eg
992
  { 408,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #408 = RECIP_IEEE_r600
993
  { 409,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #409 = RECIP_UINT_eg
994
  { 410,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #410 = RECIP_UINT_r600
995
  { 411,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #411 = RNDNE
996
  { 412,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #412 = SETE
997
  { 413,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #413 = SETE_DX10
998
  { 414,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #414 = SETE_INT
999
  { 415,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #415 = SETGE_DX10
1000
  { 416,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #416 = SETGE_INT
1001
  { 417,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #417 = SETGE_UINT
1002
  { 418,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #418 = SETGT_DX10
1003
  { 419,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #419 = SETGT_INT
1004
  { 420,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #420 = SETGT_UINT
1005
  { 421,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #421 = SETNE_DX10
1006
  { 422,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #422 = SETNE_INT
1007
  { 423,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #423 = SGE
1008
  { 424,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #424 = SGT
1009
  { 425,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4650ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #425 = SIN_cm
1010
  { 426,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #426 = SIN_eg
1011
  { 427,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #427 = SIN_r600
1012
  { 428,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #428 = SIN_r700
1013
  { 429,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #429 = SNE
1014
  { 430,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #430 = SUBB_UINT
1015
  { 431,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #431 = SUB_INT
1016
  { 432,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #432 = TEX_GET_GRADIENTS_H
1017
  { 433,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #433 = TEX_GET_GRADIENTS_V
1018
  { 434,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #434 = TEX_GET_TEXTURE_RESINFO
1019
  { 435,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #435 = TEX_LD
1020
  { 436,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #436 = TEX_LDPTR
1021
  { 437,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #437 = TEX_SAMPLE
1022
  { 438,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #438 = TEX_SAMPLE_C
1023
  { 439,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #439 = TEX_SAMPLE_C_G
1024
  { 440,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #440 = TEX_SAMPLE_C_L
1025
  { 441,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #441 = TEX_SAMPLE_C_LB
1026
  { 442,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #442 = TEX_SAMPLE_G
1027
  { 443,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #443 = TEX_SAMPLE_L
1028
  { 444,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #444 = TEX_SAMPLE_LB
1029
  { 445,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #445 = TEX_SET_GRADIENTS_H
1030
  { 446,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #446 = TEX_SET_GRADIENTS_V
1031
  { 447,  4,  1,  0,  1,  0, 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #447 = TEX_VTX_CONSTBUF
1032
  { 448,  4,  1,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #448 = TEX_VTX_TEXBUF
1033
  { 449,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #449 = TRUNC
1034
  { 450,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #450 = UINT_TO_FLT_eg
1035
  { 451,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #451 = UINT_TO_FLT_r600
1036
  { 452,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #452 = VTX_READ_128_cm
1037
  { 453,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #453 = VTX_READ_128_eg
1038
  { 454,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #454 = VTX_READ_16_cm
1039
  { 455,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #455 = VTX_READ_16_eg
1040
  { 456,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #456 = VTX_READ_32_cm
1041
  { 457,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #457 = VTX_READ_32_eg
1042
  { 458,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #458 = VTX_READ_64_cm
1043
  { 459,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #459 = VTX_READ_64_eg
1044
  { 460,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #460 = VTX_READ_8_cm
1045
  { 461,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #461 = VTX_READ_8_eg
1046
  { 462,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #462 = WHILE_LOOP_EG
1047
  { 463,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #463 = WHILE_LOOP_R600
1048
  { 464,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #464 = XOR_INT
1049
};
1050
1051
extern const char R600InstrNameData[] = {
1052
  /* 0 */ 'C', 'F', '_', 'T', 'C', '_', 'R', '6', '0', '0', 0,
1053
  /* 11 */ 'C', 'F', '_', 'V', 'C', '_', 'R', '6', '0', '0', 0,
1054
  /* 22 */ 'C', 'F', '_', 'E', 'N', 'D', '_', 'R', '6', '0', '0', 0,
1055
  /* 34 */ 'C', 'F', '_', 'E', 'L', 'S', 'E', '_', 'R', '6', '0', '0', 0,
1056
  /* 47 */ 'C', 'F', '_', 'P', 'U', 'S', 'H', '_', 'E', 'L', 'S', 'E', '_', 'R', '6', '0', '0', 0,
1057
  /* 65 */ 'C', 'F', '_', 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'R', '6', '0', '0', 0,
1058
  /* 82 */ 'F', 'N', 'E', 'G', '_', 'R', '6', '0', '0', 0,
1059
  /* 92 */ 'L', 'O', 'O', 'P', '_', 'B', 'R', 'E', 'A', 'K', '_', 'R', '6', '0', '0', 0,
1060
  /* 108 */ 'C', 'F', '_', 'J', 'U', 'M', 'P', '_', 'R', '6', '0', '0', 0,
1061
  /* 121 */ 'E', 'N', 'D', '_', 'L', 'O', 'O', 'P', '_', 'R', '6', '0', '0', 0,
1062
  /* 135 */ 'W', 'H', 'I', 'L', 'E', '_', 'L', 'O', 'O', 'P', '_', 'R', '6', '0', '0', 0,
1063
  /* 151 */ 'P', 'O', 'P', '_', 'R', '6', '0', '0', 0,
1064
  /* 160 */ 'F', 'A', 'B', 'S', '_', 'R', '6', '0', '0', 0,
1065
  /* 170 */ 'C', 'F', '_', 'C', 'A', 'L', 'L', '_', 'F', 'S', '_', 'R', '6', '0', '0', 0,
1066
  /* 186 */ 'D', 'O', 'T', '4', '_', 'r', '6', '0', '0', 0,
1067
  /* 196 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'r', '6', '0', '0', 0,
1068
  /* 208 */ 'L', 'O', 'G', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'r', '6', '0', '0', 0,
1069
  /* 225 */ 'R', 'E', 'C', 'I', 'P', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'r', '6', '0', '0', 0,
1070
  /* 244 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'r', '6', '0', '0', 0,
1071
  /* 267 */ 'C', 'N', 'D', 'E', '_', 'r', '6', '0', '0', 0,
1072
  /* 277 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1073
  /* 294 */ 'L', 'O', 'G', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1074
  /* 308 */ 'R', 'E', 'C', 'I', 'P', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1075
  /* 324 */ 'E', 'X', 'P', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1076
  /* 338 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1077
  /* 358 */ 'C', 'N', 'D', 'G', 'E', '_', 'r', '6', '0', '0', 0,
1078
  /* 369 */ 'L', 'S', 'H', 'L', '_', 'r', '6', '0', '0', 0,
1079
  /* 379 */ 'S', 'I', 'N', '_', 'r', '6', '0', '0', 0,
1080
  /* 388 */ 'A', 'S', 'H', 'R', '_', 'r', '6', '0', '0', 0,
1081
  /* 398 */ 'L', 'S', 'H', 'R', '_', 'r', '6', '0', '0', 0,
1082
  /* 408 */ 'C', 'O', 'S', '_', 'r', '6', '0', '0', 0,
1083
  /* 417 */ 'C', 'N', 'D', 'G', 'T', '_', 'r', '6', '0', '0', 0,
1084
  /* 428 */ 'M', 'U', 'L', '_', 'L', 'I', 'T', '_', 'r', '6', '0', '0', 0,
1085
  /* 441 */ 'U', 'I', 'N', 'T', '_', 'T', 'O', '_', 'F', 'L', 'T', '_', 'r', '6', '0', '0', 0,
1086
  /* 458 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1087
  /* 474 */ 'M', 'U', 'L', 'L', 'O', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1088
  /* 490 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1089
  /* 507 */ 'R', 'E', 'C', 'I', 'P', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1090
  /* 523 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1091
  /* 538 */ 'M', 'U', 'L', 'L', 'O', '_', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1092
  /* 553 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1093
  /* 569 */ 'S', 'I', 'N', '_', 'r', '7', '0', '0', 0,
1094
  /* 578 */ 'C', 'O', 'S', '_', 'r', '7', '0', '0', 0,
1095
  /* 587 */ 'S', 'E', 'T', 'G', 'E', '_', 'D', 'X', '1', '0', 0,
1096
  /* 598 */ 'S', 'E', 'T', 'N', 'E', '_', 'D', 'X', '1', '0', 0,
1097
  /* 609 */ 'S', 'E', 'T', 'E', '_', 'D', 'X', '1', '0', 0,
1098
  /* 619 */ 'M', 'I', 'N', '_', 'D', 'X', '1', '0', 0,
1099
  /* 628 */ 'S', 'E', 'T', 'G', 'T', '_', 'D', 'X', '1', '0', 0,
1100
  /* 639 */ 'M', 'A', 'X', '_', 'D', 'X', '1', '0', 0,
1101
  /* 648 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'L', 'O', 'A', 'D', '_', 'P', '0', 0,
1102
  /* 663 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'D', 'W', 'O', 'R', 'D', '3', '2', 0,
1103
  /* 681 */ 'M', 'O', 'V', '_', 'I', 'M', 'M', '_', 'F', '3', '2', 0,
1104
  /* 693 */ 'M', 'O', 'V', '_', 'I', 'M', 'M', '_', 'I', '3', '2', 0,
1105
  /* 705 */ 'F', 'L', 'T', '1', '6', '_', 'T', 'O', '_', 'F', 'L', 'T', '3', '2', 0,
1106
  /* 720 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', 'C', '_', 'f', '3', '2', 0,
1107
  /* 734 */ 'I', 'F', 'C', '_', 'f', '3', '2', 0,
1108
  /* 742 */ 'B', 'R', 'E', 'A', 'K', 'C', '_', 'f', '3', '2', 0,
1109
  /* 753 */ 'B', 'R', 'A', 'N', 'C', 'H', '_', 'C', 'O', 'N', 'D', '_', 'f', '3', '2', 0,
1110
  /* 769 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'f', '3', '2', 0,
1111
  /* 791 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'f', '3', '2', 0,
1112
  /* 807 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'f', '3', '2', 0,
1113
  /* 826 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'f', '3', '2', 0,
1114
  /* 849 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'f', '3', '2', 0,
1115
  /* 866 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'f', '3', '2', 0,
1116
  /* 886 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', 'C', '_', 'i', '3', '2', 0,
1117
  /* 900 */ 'I', 'F', 'C', '_', 'i', '3', '2', 0,
1118
  /* 908 */ 'B', 'R', 'E', 'A', 'K', 'C', '_', 'i', '3', '2', 0,
1119
  /* 919 */ 'B', 'R', 'A', 'N', 'C', 'H', '_', 'C', 'O', 'N', 'D', '_', 'i', '3', '2', 0,
1120
  /* 935 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'i', '3', '2', 0,
1121
  /* 957 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'i', '3', '2', 0,
1122
  /* 973 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'i', '3', '2', 0,
1123
  /* 992 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'i', '3', '2', 0,
1124
  /* 1015 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'i', '3', '2', 0,
1125
  /* 1032 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'i', '3', '2', 0,
1126
  /* 1052 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
1127
  /* 1060 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
1128
  /* 1068 */ 'R', '6', '0', '0', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'E', 'L', 'T', '_', 'V', '2', 0,
1129
  /* 1088 */ 'R', '6', '0', '0', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'E', 'L', 'T', '_', 'V', '2', 0,
1130
  /* 1107 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'c', 'm', '2', '4', 0,
1131
  /* 1123 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'c', 'm', '2', '4', 0,
1132
  /* 1138 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'D', 'W', 'O', 'R', 'D', '6', '4', 0,
1133
  /* 1156 */ 'R', '6', '0', '0', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'E', 'L', 'T', '_', 'V', '4', 0,
1134
  /* 1176 */ 'R', '6', '0', '0', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'E', 'L', 'T', '_', 'V', '4', 0,
1135
  /* 1195 */ 'D', 'O', 'T', '_', '4', 0,
1136
  /* 1201 */ 'F', 'L', 'T', '3', '2', '_', 'T', 'O', '_', 'F', 'L', 'T', '1', '6', 0,
1137
  /* 1216 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'D', 'W', 'O', 'R', 'D', '1', '2', '8', 0,
1138
  /* 1235 */ 'G', '_', 'F', 'M', 'A', 0,
1139
  /* 1241 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', '_', 'L', 'B', 0,
1140
  /* 1257 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'L', 'B', 0,
1141
  /* 1271 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
1142
  /* 1278 */ 'G', '_', 'S', 'U', 'B', 0,
1143
  /* 1284 */ 'L', 'D', 'S', '_', 'S', 'U', 'B', 0,
1144
  /* 1292 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
1145
  /* 1308 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
1146
  /* 1320 */ 'E', 'N', 'D', 'F', 'U', 'N', 'C', 0,
1147
  /* 1328 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
1148
  /* 1338 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
1149
  /* 1346 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', 0,
1150
  /* 1359 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
1151
  /* 1370 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
1152
  /* 1381 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'V', 'E', 'C', '_', 'L', 'O', 'A', 'D', 0,
1153
  /* 1397 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
1154
  /* 1404 */ 'P', 'A', 'D', 0,
1155
  /* 1408 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
1156
  /* 1415 */ 'G', '_', 'A', 'D', 'D', 0,
1157
  /* 1421 */ 'L', 'D', 'S', '_', 'A', 'D', 'D', 0,
1158
  /* 1429 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
1159
  /* 1445 */ 'T', 'E', 'X', '_', 'L', 'D', 0,
1160
  /* 1452 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
1161
  /* 1469 */ 'G', '_', 'A', 'N', 'D', 0,
1162
  /* 1475 */ 'L', 'D', 'S', '_', 'A', 'N', 'D', 0,
1163
  /* 1483 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
1164
  /* 1499 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
1165
  /* 1512 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
1166
  /* 1521 */ 'J', 'U', 'M', 'P', '_', 'C', 'O', 'N', 'D', 0,
1167
  /* 1531 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
1168
  /* 1548 */ 'T', 'X', 'D', 0,
1169
  /* 1552 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
1170
  /* 1560 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
1171
  /* 1573 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
1172
  /* 1581 */ 'M', 'U', 'L', '_', 'I', 'E', 'E', 'E', 0,
1173
  /* 1590 */ 'S', 'G', 'E', 0,
1174
  /* 1594 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'E', 0,
1175
  /* 1605 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
1176
  /* 1612 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', 0,
1177
  /* 1623 */ 'R', 'N', 'D', 'N', 'E', 0,
1178
  /* 1629 */ 'S', 'N', 'E', 0,
1179
  /* 1633 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'N', 'E', 0,
1180
  /* 1644 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
1181
  /* 1657 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'P', 'U', 'S', 'H', '_', 'B', 'E', 'F', 'O', 'R', 'E', 0,
1182
  /* 1676 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
1183
  /* 1684 */ 'E', 'L', 'S', 'E', 0,
1184
  /* 1689 */ 'F', 'E', 'T', 'C', 'H', '_', 'C', 'L', 'A', 'U', 'S', 'E', 0,
1185
  /* 1702 */ 'A', 'L', 'U', '_', 'C', 'L', 'A', 'U', 'S', 'E', 0,
1186
  /* 1713 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'E', 0,
1187
  /* 1723 */ 'L', 'D', 'S', '_', 'B', 'Y', 'T', 'E', '_', 'W', 'R', 'I', 'T', 'E', 0,
1188
  /* 1738 */ 'M', 'A', 'S', 'K', '_', 'W', 'R', 'I', 'T', 'E', 0,
1189
  /* 1749 */ 'L', 'D', 'S', '_', 'W', 'R', 'I', 'T', 'E', 0,
1190
  /* 1759 */ 'L', 'D', 'S', '_', 'S', 'H', 'O', 'R', 'T', '_', 'W', 'R', 'I', 'T', 'E', 0,
1191
  /* 1775 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
1192
  /* 1785 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
1193
  /* 1800 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', 0,
1194
  /* 1816 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
1195
  /* 1831 */ 'E', 'N', 'D', 'I', 'F', 0,
1196
  /* 1837 */ 'T', 'E', 'X', '_', 'V', 'T', 'X', '_', 'C', 'O', 'N', 'S', 'T', 'B', 'U', 'F', 0,
1197
  /* 1854 */ 'T', 'E', 'X', '_', 'V', 'T', 'X', '_', 'T', 'E', 'X', 'B', 'U', 'F', 0,
1198
  /* 1869 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
1199
  /* 1876 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
1200
  /* 1891 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
1201
  /* 1905 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
1202
  /* 1919 */ 'C', 'F', '_', 'T', 'C', '_', 'E', 'G', 0,
1203
  /* 1928 */ 'C', 'F', '_', 'V', 'C', '_', 'E', 'G', 0,
1204
  /* 1937 */ 'C', 'F', '_', 'E', 'N', 'D', '_', 'E', 'G', 0,
1205
  /* 1947 */ 'C', 'F', '_', 'E', 'L', 'S', 'E', '_', 'E', 'G', 0,
1206
  /* 1958 */ 'C', 'F', '_', 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'E', 'G', 0,
1207
  /* 1973 */ 'C', 'F', '_', 'P', 'U', 'S', 'H', '_', 'E', 'G', 0,
1208
  /* 1984 */ 'L', 'O', 'O', 'P', '_', 'B', 'R', 'E', 'A', 'K', '_', 'E', 'G', 0,
1209
  /* 1998 */ 'C', 'F', '_', 'J', 'U', 'M', 'P', '_', 'E', 'G', 0,
1210
  /* 2009 */ 'E', 'N', 'D', '_', 'L', 'O', 'O', 'P', '_', 'E', 'G', 0,
1211
  /* 2021 */ 'W', 'H', 'I', 'L', 'E', '_', 'L', 'O', 'O', 'P', '_', 'E', 'G', 0,
1212
  /* 2035 */ 'P', 'O', 'P', '_', 'E', 'G', 0,
1213
  /* 2042 */ 'C', 'F', '_', 'C', 'A', 'L', 'L', '_', 'F', 'S', '_', 'E', 'G', 0,
1214
  /* 2056 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
1215
  /* 2073 */ 'L', 'D', 'S', '_', 'W', 'R', 'X', 'C', 'H', 'G', 0,
1216
  /* 2084 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
1217
  /* 2101 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
1218
  /* 2108 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
1219
  /* 2116 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', '_', 'G', 0,
1220
  /* 2131 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'G', 0,
1221
  /* 2144 */ 'B', 'R', 'A', 'N', 'C', 'H', 0,
1222
  /* 2151 */ 'E', 'N', 'D', 'S', 'W', 'I', 'T', 'C', 'H', 0,
1223
  /* 2161 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
1224
  /* 2169 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
1225
  /* 2177 */ 'T', 'E', 'X', '_', 'G', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'H', 0,
1226
  /* 2197 */ 'T', 'E', 'X', '_', 'S', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'H', 0,
1227
  /* 2217 */ 'G', '_', 'P', 'H', 'I', 0,
1228
  /* 2223 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
1229
  /* 2232 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
1230
  /* 2241 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'B', 'R', 'E', 'A', 'K', 0,
1231
  /* 2254 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
1232
  /* 2265 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
1233
  /* 2274 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
1234
  /* 2284 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
1235
  /* 2293 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
1236
  /* 2310 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
1237
  /* 2330 */ 'G', '_', 'S', 'H', 'L', 0,
1238
  /* 2336 */ 'C', 'E', 'I', 'L', 0,
1239
  /* 2341 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
1240
  /* 2361 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
1241
  /* 2388 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
1242
  /* 2409 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
1243
  /* 2421 */ 'K', 'I', 'L', 'L', 0,
1244
  /* 2426 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
1245
  /* 2433 */ 'G', '_', 'M', 'U', 'L', 0,
1246
  /* 2439 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', '_', 'L', 0,
1247
  /* 2454 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'L', 0,
1248
  /* 2467 */ 'C', 'F', '_', 'E', 'N', 'D', '_', 'C', 'M', 0,
1249
  /* 2477 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
1250
  /* 2484 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
1251
  /* 2491 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
1252
  /* 2498 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
1253
  /* 2508 */ 'D', 'U', 'M', 'M', 'Y', '_', 'C', 'H', 'A', 'I', 'N', 0,
1254
  /* 2520 */ 'E', 'N', 'D', 'M', 'A', 'I', 'N', 0,
1255
  /* 2528 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
1256
  /* 2545 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
1257
  /* 2561 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
1258
  /* 2577 */ 'R', 'E', 'T', 'U', 'R', 'N', 0,
1259
  /* 2584 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'S', 'U', 'B', '_', 'R', 'T', 'N', 0,
1260
  /* 2604 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'U', 'B', '_', 'R', 'T', 'N', 0,
1261
  /* 2623 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'D', 'D', '_', 'R', 'T', 'N', 0,
1262
  /* 2642 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'N', 'D', '_', 'R', 'T', 'N', 0,
1263
  /* 2661 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'O', 'R', '_', 'R', 'T', 'N', 0,
1264
  /* 2680 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'O', 'R', '_', 'R', 'T', 'N', 0,
1265
  /* 2698 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'D', 'E', 'C', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1266
  /* 2722 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'I', 'N', 'C', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1267
  /* 2746 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1268
  /* 2770 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1269
  /* 2794 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1270
  /* 2821 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1271
  /* 2845 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1272
  /* 2868 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1273
  /* 2891 */ 'R', 'E', 'T', 'D', 'Y', 'N', 0,
1274
  /* 2898 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
1275
  /* 2906 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
1276
  /* 2914 */ 'T', 'E', 'X', '_', 'G', 'E', 'T', '_', 'T', 'E', 'X', 'T', 'U', 'R', 'E', '_', 'R', 'E', 'S', 'I', 'N', 'F', 'O', 0,
1277
  /* 2938 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
1278
  /* 2946 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
1279
  /* 2954 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
1280
  /* 2963 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
1281
  /* 2971 */ 'G', '_', 'G', 'E', 'P', 0,
1282
  /* 2977 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
1283
  /* 2986 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
1284
  /* 2995 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
1285
  /* 3002 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
1286
  /* 3009 */ 'J', 'U', 'M', 'P', 0,
1287
  /* 3014 */ 'E', 'N', 'D', 'L', 'O', 'O', 'P', 0,
1288
  /* 3022 */ 'W', 'H', 'I', 'L', 'E', 'L', 'O', 'O', 'P', 0,
1289
  /* 3032 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
1290
  /* 3045 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
1291
  /* 3057 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
1292
  /* 3064 */ 'G', '_', 'B', 'R', 0,
1293
  /* 3069 */ 'M', 'O', 'V', '_', 'I', 'M', 'M', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'A', 'D', 'D', 'R', 0,
1294
  /* 3089 */ 'G', 'R', 'O', 'U', 'P', '_', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0,
1295
  /* 3103 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'E', 'L', 'S', 'E', '_', 'A', 'F', 'T', 'E', 'R', 0,
1296
  /* 3121 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'P', 'O', 'P', '_', 'A', 'F', 'T', 'E', 'R', 0,
1297
  /* 3138 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
1298
  /* 3163 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
1299
  /* 3170 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
1300
  /* 3177 */ 'R', 'A', 'T', '_', 'M', 'S', 'K', 'O', 'R', 0,
1301
  /* 3187 */ 'F', 'L', 'O', 'O', 'R', 0,
1302
  /* 3193 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
1303
  /* 3210 */ 'G', '_', 'X', 'O', 'R', 0,
1304
  /* 3216 */ 'L', 'D', 'S', '_', 'X', 'O', 'R', 0,
1305
  /* 3224 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
1306
  /* 3240 */ 'G', '_', 'O', 'R', 0,
1307
  /* 3245 */ 'L', 'D', 'S', '_', 'O', 'R', 0,
1308
  /* 3252 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
1309
  /* 3267 */ 'T', 'E', 'X', '_', 'L', 'D', 'P', 'T', 'R', 0,
1310
  /* 3277 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
1311
  /* 3288 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
1312
  /* 3295 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1313
  /* 3312 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1314
  /* 3327 */ 'L', 'I', 'T', 'E', 'R', 'A', 'L', 'S', 0,
1315
  /* 3336 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
1316
  /* 3353 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
1317
  /* 3383 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
1318
  /* 3410 */ 'F', 'R', 'A', 'C', 'T', 0,
1319
  /* 3416 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
1320
  /* 3426 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
1321
  /* 3435 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
1322
  /* 3448 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'S', 'U', 'B', '_', 'N', 'O', 'R', 'E', 'T', 0,
1323
  /* 3470 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'U', 'B', '_', 'N', 'O', 'R', 'E', 'T', 0,
1324
  /* 3491 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'D', 'D', '_', 'N', 'O', 'R', 'E', 'T', 0,
1325
  /* 3512 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'N', 'D', '_', 'N', 'O', 'R', 'E', 'T', 0,
1326
  /* 3533 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'O', 'R', '_', 'N', 'O', 'R', 'E', 'T', 0,
1327
  /* 3554 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'O', 'R', '_', 'N', 'O', 'R', 'E', 'T', 0,
1328
  /* 3574 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'D', 'E', 'C', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1329
  /* 3600 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'I', 'N', 'C', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1330
  /* 3626 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1331
  /* 3652 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1332
  /* 3678 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1333
  /* 3707 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1334
  /* 3733 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1335
  /* 3758 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1336
  /* 3783 */ 'L', 'D', 'S', '_', 'S', 'U', 'B', '_', 'R', 'E', 'T', 0,
1337
  /* 3795 */ 'L', 'D', 'S', '_', 'U', 'B', 'Y', 'T', 'E', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1338
  /* 3814 */ 'L', 'D', 'S', '_', 'B', 'Y', 'T', 'E', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1339
  /* 3832 */ 'L', 'D', 'S', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1340
  /* 3845 */ 'L', 'D', 'S', '_', 'U', 'S', 'H', 'O', 'R', 'T', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1341
  /* 3865 */ 'L', 'D', 'S', '_', 'S', 'H', 'O', 'R', 'T', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1342
  /* 3884 */ 'L', 'D', 'S', '_', 'A', 'D', 'D', '_', 'R', 'E', 'T', 0,
1343
  /* 3896 */ 'L', 'D', 'S', '_', 'A', 'N', 'D', '_', 'R', 'E', 'T', 0,
1344
  /* 3908 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
1345
  /* 3922 */ 'L', 'D', 'S', '_', 'W', 'R', 'X', 'C', 'H', 'G', '_', 'R', 'E', 'T', 0,
1346
  /* 3937 */ 'L', 'D', 'S', '_', 'X', 'O', 'R', '_', 'R', 'E', 'T', 0,
1347
  /* 3949 */ 'L', 'D', 'S', '_', 'O', 'R', '_', 'R', 'E', 'T', 0,
1348
  /* 3960 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1349
  /* 3977 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1350
  /* 3994 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1351
  /* 4010 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1352
  /* 4026 */ 'L', 'D', 'S', '_', 'C', 'M', 'P', 'S', 'T', '_', 'R', 'E', 'T', 0,
1353
  /* 4040 */ 'I', 'F', '_', 'P', 'R', 'E', 'D', 'I', 'C', 'A', 'T', 'E', '_', 'S', 'E', 'T', 0,
1354
  /* 4057 */ 'K', 'I', 'L', 'L', 'G', 'T', 0,
1355
  /* 4064 */ 'S', 'G', 'T', 0,
1356
  /* 4068 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'T', 0,
1357
  /* 4079 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
1358
  /* 4103 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1359
  /* 4124 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1360
  /* 4144 */ 'D', 'E', 'F', 'A', 'U', 'L', 'T', 0,
1361
  /* 4152 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1362
  /* 4164 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1363
  /* 4175 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
1364
  /* 4186 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
1365
  /* 4197 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
1366
  /* 4208 */ 'S', 'U', 'B', 'B', '_', 'U', 'I', 'N', 'T', 0,
1367
  /* 4218 */ 'A', 'D', 'D', 'C', '_', 'U', 'I', 'N', 'T', 0,
1368
  /* 4228 */ 'S', 'E', 'T', 'G', 'E', '_', 'U', 'I', 'N', 'T', 0,
1369
  /* 4239 */ 'F', 'F', 'B', 'H', '_', 'U', 'I', 'N', 'T', 0,
1370
  /* 4249 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', 0,
1371
  /* 4262 */ 'S', 'E', 'T', 'G', 'T', '_', 'U', 'I', 'N', 'T', 0,
1372
  /* 4273 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', 0,
1373
  /* 4286 */ 'S', 'U', 'B', '_', 'I', 'N', 'T', 0,
1374
  /* 4294 */ 'A', 'D', 'D', '_', 'I', 'N', 'T', 0,
1375
  /* 4302 */ 'A', 'N', 'D', '_', 'I', 'N', 'T', 0,
1376
  /* 4310 */ 'C', 'N', 'D', 'E', '_', 'I', 'N', 'T', 0,
1377
  /* 4319 */ 'C', 'N', 'D', 'G', 'E', '_', 'I', 'N', 'T', 0,
1378
  /* 4329 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'E', '_', 'I', 'N', 'T', 0,
1379
  /* 4344 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'N', 'E', '_', 'I', 'N', 'T', 0,
1380
  /* 4359 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'E', '_', 'I', 'N', 'T', 0,
1381
  /* 4373 */ 'F', 'F', 'B', 'L', '_', 'I', 'N', 'T', 0,
1382
  /* 4382 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', 0,
1383
  /* 4394 */ 'X', 'O', 'R', '_', 'I', 'N', 'T', 0,
1384
  /* 4402 */ 'C', 'N', 'D', 'G', 'T', '_', 'I', 'N', 'T', 0,
1385
  /* 4412 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'T', '_', 'I', 'N', 'T', 0,
1386
  /* 4427 */ 'B', 'C', 'N', 'T', '_', 'I', 'N', 'T', 0,
1387
  /* 4436 */ 'N', 'O', 'T', '_', 'I', 'N', 'T', 0,
1388
  /* 4444 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', 0,
1389
  /* 4456 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
1390
  /* 4466 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
1391
  /* 4481 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
1392
  /* 4490 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
1393
  /* 4500 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
1394
  /* 4517 */ 'L', 'D', 'S', '_', 'C', 'M', 'P', 'S', 'T', 0,
1395
  /* 4527 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
1396
  /* 4535 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
1397
  /* 4542 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
1398
  /* 4551 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
1399
  /* 4558 */ 'C', 'F', '_', 'A', 'L', 'U', 0,
1400
  /* 4565 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
1401
  /* 4572 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
1402
  /* 4579 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
1403
  /* 4586 */ 'M', 'O', 'V', 0,
1404
  /* 4590 */ 'T', 'E', 'X', '_', 'G', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'V', 0,
1405
  /* 4610 */ 'T', 'E', 'X', '_', 'S', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'V', 0,
1406
  /* 4630 */ 'T', 'X', 'D', '_', 'S', 'H', 'A', 'D', 'O', 'W', 0,
1407
  /* 4641 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
1408
  /* 4648 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'Z', 'W', 0,
1409
  /* 4658 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'P', 'A', 'I', 'R', '_', 'Z', 'W', 0,
1410
  /* 4673 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
1411
  /* 4690 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
1412
  /* 4706 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
1413
  /* 4720 */ 'P', 'R', 'E', 'D', '_', 'X', 0,
1414
  /* 4727 */ 'C', 'O', 'N', 'S', 'T', '_', 'C', 'O', 'P', 'Y', 0,
1415
  /* 4738 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'X', 'Y', 0,
1416
  /* 4748 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'P', 'A', 'I', 'R', '_', 'X', 'Y', 0,
1417
  /* 4763 */ 'R', '6', '0', '0', '_', 'R', 'e', 'g', 'i', 's', 't', 'e', 'r', 'L', 'o', 'a', 'd', 0,
1418
  /* 4781 */ 'R', '6', '0', '0', '_', 'R', 'e', 'g', 'i', 's', 't', 'e', 'r', 'S', 't', 'o', 'r', 'e', 0,
1419
  /* 4800 */ 'R', '6', '0', '0', '_', 'E', 'x', 'p', 'o', 'r', 't', 'B', 'u', 'f', 0,
1420
  /* 4815 */ 'E', 'G', '_', 'E', 'x', 'p', 'o', 'r', 't', 'B', 'u', 'f', 0,
1421
  /* 4828 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '3', '2', '_', 'e', 'g', 0,
1422
  /* 4843 */ 'R', 'A', 'T', '_', 'W', 'R', 'I', 'T', 'E', '_', 'C', 'A', 'C', 'H', 'E', 'L', 'E', 'S', 'S', '_', '3', '2', '_', 'e', 'g', 0,
1423
  /* 4869 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'U', 'I', 'N', 'T', '2', '4', '_', 'e', 'g', 0,
1424
  /* 4886 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '2', '4', '_', 'e', 'g', 0,
1425
  /* 4902 */ 'M', 'U', 'L', '_', 'U', 'I', 'N', 'T', '2', '4', '_', 'e', 'g', 0,
1426
  /* 4916 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '6', '4', '_', 'e', 'g', 0,
1427
  /* 4931 */ 'R', 'A', 'T', '_', 'W', 'R', 'I', 'T', 'E', '_', 'C', 'A', 'C', 'H', 'E', 'L', 'E', 'S', 'S', '_', '6', '4', '_', 'e', 'g', 0,
1428
  /* 4957 */ 'D', 'O', 'T', '4', '_', 'e', 'g', 0,
1429
  /* 4965 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '6', '_', 'e', 'g', 0,
1430
  /* 4980 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '2', '8', '_', 'e', 'g', 0,
1431
  /* 4996 */ 'R', 'A', 'T', '_', 'W', 'R', 'I', 'T', 'E', '_', 'C', 'A', 'C', 'H', 'E', 'L', 'E', 'S', 'S', '_', '1', '2', '8', '_', 'e', 'g', 0,
1432
  /* 5023 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '8', '_', 'e', 'g', 0,
1433
  /* 5037 */ 'F', 'M', 'A', '_', 'e', 'g', 0,
1434
  /* 5044 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'e', 'g', 0,
1435
  /* 5054 */ 'L', 'O', 'G', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'e', 'g', 0,
1436
  /* 5069 */ 'R', 'E', 'C', 'I', 'P', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'e', 'g', 0,
1437
  /* 5086 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'e', 'g', 0,
1438
  /* 5107 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'e', 'g', 0,
1439
  /* 5126 */ 'C', 'N', 'D', 'E', '_', 'e', 'g', 0,
1440
  /* 5134 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1441
  /* 5149 */ 'L', 'O', 'G', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1442
  /* 5161 */ 'R', 'E', 'C', 'I', 'P', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1443
  /* 5175 */ 'E', 'X', 'P', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1444
  /* 5187 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1445
  /* 5205 */ 'C', 'N', 'D', 'G', 'E', '_', 'e', 'g', 0,
1446
  /* 5214 */ 'L', 'S', 'H', 'L', '_', 'e', 'g', 0,
1447
  /* 5222 */ 'S', 'I', 'N', '_', 'e', 'g', 0,
1448
  /* 5229 */ 'A', 'S', 'H', 'R', '_', 'e', 'g', 0,
1449
  /* 5237 */ 'L', 'S', 'H', 'R', '_', 'e', 'g', 0,
1450
  /* 5245 */ 'C', 'O', 'S', '_', 'e', 'g', 0,
1451
  /* 5252 */ 'C', 'N', 'D', 'G', 'T', '_', 'e', 'g', 0,
1452
  /* 5261 */ 'M', 'U', 'L', '_', 'L', 'I', 'T', '_', 'e', 'g', 0,
1453
  /* 5272 */ 'U', 'I', 'N', 'T', '_', 'T', 'O', '_', 'F', 'L', 'T', '_', 'e', 'g', 0,
1454
  /* 5287 */ 'B', 'F', 'E', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1455
  /* 5299 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1456
  /* 5313 */ 'M', 'U', 'L', 'L', 'O', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1457
  /* 5327 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1458
  /* 5342 */ 'R', 'E', 'C', 'I', 'P', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1459
  /* 5356 */ 'M', 'O', 'V', 'A', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1460
  /* 5368 */ 'B', 'F', 'E', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1461
  /* 5379 */ 'B', 'F', 'I', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1462
  /* 5390 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1463
  /* 5403 */ 'B', 'F', 'M', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1464
  /* 5414 */ 'B', 'I', 'T', '_', 'A', 'L', 'I', 'G', 'N', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1465
  /* 5431 */ 'M', 'U', 'L', 'L', 'O', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1466
  /* 5444 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1467
  /* 5458 */ 'C', 'U', 'B', 'E', '_', 'r', '6', '0', '0', '_', 'r', 'e', 'a', 'l', 0,
1468
  /* 5473 */ 'C', 'U', 'B', 'E', '_', 'e', 'g', '_', 'r', 'e', 'a', 'l', 0,
1469
  /* 5486 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '3', '2', '_', 'c', 'm', 0,
1470
  /* 5501 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'I', 'N', 'T', '2', '4', '_', 'c', 'm', 0,
1471
  /* 5517 */ 'M', 'U', 'L', '_', 'I', 'N', 'T', '2', '4', '_', 'c', 'm', 0,
1472
  /* 5530 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '6', '4', '_', 'c', 'm', 0,
1473
  /* 5545 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '6', '_', 'c', 'm', 0,
1474
  /* 5560 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '2', '8', '_', 'c', 'm', 0,
1475
  /* 5576 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '8', '_', 'c', 'm', 0,
1476
  /* 5590 */ 'R', 'E', 'C', 'I', 'P', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'c', 'm', 0,
1477
  /* 5607 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'c', 'm', 0,
1478
  /* 5628 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'c', 'm', 0,
1479
  /* 5647 */ 'L', 'O', 'G', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1480
  /* 5659 */ 'R', 'E', 'C', 'I', 'P', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1481
  /* 5673 */ 'E', 'X', 'P', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1482
  /* 5685 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1483
  /* 5703 */ 'S', 'I', 'N', '_', 'c', 'm', 0,
1484
  /* 5710 */ 'C', 'O', 'S', '_', 'c', 'm', 0,
1485
  /* 5717 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'c', 'm', 0,
1486
  /* 5731 */ 'M', 'U', 'L', 'L', 'O', '_', 'U', 'I', 'N', 'T', '_', 'c', 'm', 0,
1487
  /* 5745 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'c', 'm', 0,
1488
  /* 5758 */ 'M', 'U', 'L', 'L', 'O', '_', 'I', 'N', 'T', '_', 'c', 'm', 0,
1489
  /* 5771 */ 'C', 'U', 'B', 'E', '_', 'r', '6', '0', '0', '_', 'p', 's', 'e', 'u', 'd', 'o', 0,
1490
  /* 5788 */ 'C', 'U', 'B', 'E', '_', 'e', 'g', '_', 'p', 's', 'e', 'u', 'd', 'o', 0,
1491
  /* 5803 */ 'R', '6', '0', '0', '_', 'E', 'x', 'p', 'o', 'r', 't', 'S', 'w', 'z', 0,
1492
  /* 5818 */ 'E', 'G', '_', 'E', 'x', 'p', 'o', 'r', 't', 'S', 'w', 'z', 0,
1493
};
1494
1495
extern const unsigned R600InstrNameIndices[] = {
1496
    2219U, 2498U, 2561U, 2284U, 2265U, 2293U, 2421U, 1876U, 
1497
    1891U, 1818U, 1905U, 3336U, 1775U, 2274U, 1560U, 4733U, 
1498
    1605U, 4466U, 1499U, 2954U, 2409U, 4186U, 1531U, 4175U, 
1499
    1644U, 3045U, 3032U, 3138U, 3908U, 4079U, 2341U, 2388U, 
1500
    2361U, 2310U, 1415U, 1278U, 2433U, 4572U, 4579U, 2484U, 
1501
    2491U, 1469U, 3240U, 3210U, 1816U, 2217U, 4706U, 1785U, 
1502
    3416U, 3295U, 4481U, 3312U, 4197U, 3277U, 4490U, 1397U, 
1503
    1359U, 1370U, 1676U, 3353U, 2056U, 2084U, 1429U, 1292U, 
1504
    1483U, 1452U, 3252U, 3224U, 4690U, 2545U, 4673U, 2528U, 
1505
    1512U, 3435U, 1308U, 3383U, 4542U, 1338U, 4164U, 4152U, 
1506
    4456U, 2108U, 4535U, 4551U, 2330U, 3170U, 3163U, 3002U, 
1507
    2995U, 3426U, 1573U, 1552U, 2906U, 2898U, 2946U, 2938U, 
1508
    2169U, 2161U, 1408U, 1271U, 2426U, 1235U, 4565U, 2477U, 
1509
    4641U, 3057U, 1060U, 2101U, 1052U, 1869U, 4527U, 1328U, 
1510
    2223U, 2232U, 2977U, 2986U, 3288U, 2971U, 2254U, 3064U, 
1511
    4124U, 4103U, 3193U, 2963U, 4500U, 2144U, 753U, 919U, 
1512
    2248U, 742U, 908U, 866U, 1032U, 807U, 973U, 4727U, 
1513
    1807U, 720U, 886U, 826U, 992U, 769U, 935U, 5788U, 
1514
    5771U, 4144U, 1195U, 2508U, 1684U, 1508U, 1320U, 1831U, 
1515
    3014U, 2520U, 2151U, 160U, 82U, 1323U, 734U, 900U, 
1516
    849U, 1015U, 791U, 957U, 4040U, 3009U, 1521U, 1738U, 
1517
    681U, 3069U, 693U, 4720U, 1068U, 1156U, 1088U, 1176U, 
1518
    4763U, 4781U, 2891U, 2577U, 1548U, 4630U, 3022U, 1411U, 
1519
    4218U, 4294U, 1702U, 4302U, 5229U, 388U, 4427U, 5368U, 
1520
    5287U, 5379U, 5403U, 5414U, 2336U, 4558U, 2241U, 1800U, 
1521
    3103U, 3121U, 1657U, 2042U, 170U, 1958U, 65U, 1947U, 
1522
    34U, 2467U, 1937U, 22U, 1998U, 108U, 1973U, 47U, 
1523
    1919U, 0U, 1928U, 11U, 4310U, 5126U, 267U, 4319U, 
1524
    5205U, 358U, 4402U, 5252U, 417U, 5710U, 5245U, 408U, 
1525
    578U, 5473U, 5458U, 4957U, 186U, 4815U, 5818U, 2009U, 
1526
    121U, 5673U, 5175U, 324U, 1689U, 4239U, 4373U, 3187U, 
1527
    705U, 1201U, 5444U, 553U, 5327U, 490U, 5037U, 3410U, 
1528
    3089U, 648U, 4748U, 4658U, 1381U, 4738U, 4648U, 5273U, 
1529
    442U, 4057U, 1421U, 3884U, 1475U, 3896U, 3814U, 1723U, 
1530
    4517U, 4026U, 4444U, 4010U, 4273U, 3977U, 4382U, 3994U, 
1531
    4249U, 3960U, 3245U, 3949U, 3832U, 3865U, 1759U, 1284U, 
1532
    3783U, 3795U, 3845U, 1749U, 2073U, 3922U, 3216U, 3937U, 
1533
    3327U, 5054U, 208U, 5647U, 5149U, 294U, 1984U, 92U, 
1534
    5214U, 369U, 5237U, 398U, 4686U, 639U, 4448U, 4277U, 
1535
    2541U, 619U, 4386U, 4253U, 4586U, 5356U, 2429U, 5134U, 
1536
    277U, 5501U, 4869U, 5044U, 196U, 5745U, 1123U, 5390U, 
1537
    523U, 4886U, 5717U, 1107U, 5299U, 458U, 5758U, 5431U, 
1538
    538U, 5731U, 5313U, 474U, 1581U, 5517U, 5261U, 428U, 
1539
    4902U, 4436U, 4395U, 1404U, 2035U, 151U, 1713U, 4359U, 
1540
    1594U, 4329U, 4068U, 4412U, 1633U, 4344U, 4800U, 5803U, 
1541
    3491U, 2623U, 3512U, 2642U, 3678U, 2794U, 3574U, 2698U, 
1542
    3600U, 2722U, 3758U, 2868U, 3652U, 2770U, 3733U, 2845U, 
1543
    3626U, 2746U, 3554U, 2680U, 3448U, 2584U, 3470U, 2604U, 
1544
    3707U, 2821U, 3533U, 2661U, 3177U, 1216U, 663U, 1138U, 
1545
    5628U, 5107U, 4996U, 4843U, 4931U, 5607U, 5086U, 244U, 
1546
    5685U, 5187U, 338U, 5590U, 5069U, 225U, 5659U, 5161U, 
1547
    308U, 5342U, 507U, 1623U, 1718U, 609U, 4364U, 587U, 
1548
    4334U, 4228U, 628U, 4417U, 4262U, 598U, 4349U, 1590U, 
1549
    4064U, 5703U, 5222U, 379U, 569U, 1629U, 4208U, 4286U, 
1550
    2177U, 4590U, 2914U, 1445U, 3267U, 1612U, 1346U, 2116U, 
1551
    2439U, 1241U, 2131U, 2454U, 1257U, 2197U, 4610U, 1837U, 
1552
    1854U, 1332U, 5272U, 441U, 5560U, 4980U, 5545U, 4965U, 
1553
    5486U, 4828U, 5530U, 4916U, 5576U, 5023U, 2021U, 135U, 
1554
    4394U, 
1555
};
1556
1557
291
static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
1558
291
  II->InitMCInstrInfo(R600Insts, R600InstrNameIndices, R600InstrNameData, 465);
1559
291
}
1560
1561
} // end llvm namespace
1562
#endif // GET_INSTRINFO_MC_DESC
1563
1564
#ifdef GET_INSTRINFO_HEADER
1565
#undef GET_INSTRINFO_HEADER
1566
namespace llvm {
1567
struct R600GenInstrInfo : public TargetInstrInfo {
1568
  explicit R600GenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
1569
285
  ~R600GenInstrInfo() override = default;
1570
1571
};
1572
} // end llvm namespace
1573
#endif // GET_INSTRINFO_HEADER
1574
1575
#ifdef GET_INSTRINFO_CTOR_DTOR
1576
#undef GET_INSTRINFO_CTOR_DTOR
1577
namespace llvm {
1578
extern const MCInstrDesc R600Insts[];
1579
extern const unsigned R600InstrNameIndices[];
1580
extern const char R600InstrNameData[];
1581
R600GenInstrInfo::R600GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
1582
286
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1583
286
  InitMCInstrInfo(R600Insts, R600InstrNameIndices, R600InstrNameData, 465);
1584
286
}
1585
} // end llvm namespace
1586
#endif // GET_INSTRINFO_CTOR_DTOR
1587
1588
#ifdef GET_INSTRINFO_OPERAND_ENUM
1589
#undef GET_INSTRINFO_OPERAND_ENUM
1590
namespace llvm {
1591
namespace R600 {
1592
namespace OpName {
1593
enum {
1594
  ADDR = 98,
1595
  COUNT = 105,
1596
  Enabled = 106,
1597
  KCACHE_ADDR0 = 103,
1598
  KCACHE_ADDR1 = 104,
1599
  KCACHE_BANK0 = 99,
1600
  KCACHE_BANK1 = 100,
1601
  KCACHE_MODE0 = 101,
1602
  KCACHE_MODE1 = 102,
1603
  addr = 72,
1604
  bank_swizzle = 93,
1605
  chan = 73,
1606
  clamp = 80,
1607
  clamp_W = 58,
1608
  clamp_X = 7,
1609
  clamp_Y = 24,
1610
  clamp_Z = 41,
1611
  dst = 0,
1612
  dst_rel = 79,
1613
  dst_rel_W = 57,
1614
  dst_rel_X = 6,
1615
  dst_rel_Y = 23,
1616
  dst_rel_Z = 40,
1617
  last = 90,
1618
  literal = 92,
1619
  literal0 = 70,
1620
  literal1 = 71,
1621
  omod = 78,
1622
  omod_W = 56,
1623
  omod_X = 5,
1624
  omod_Y = 22,
1625
  omod_Z = 39,
1626
  pred_sel = 91,
1627
  pred_sel_W = 69,
1628
  pred_sel_X = 18,
1629
  pred_sel_Y = 35,
1630
  pred_sel_Z = 52,
1631
  src0 = 1,
1632
  src0_W = 59,
1633
  src0_X = 8,
1634
  src0_Y = 25,
1635
  src0_Z = 42,
1636
  src0_abs = 83,
1637
  src0_abs_W = 62,
1638
  src0_abs_X = 11,
1639
  src0_abs_Y = 28,
1640
  src0_abs_Z = 45,
1641
  src0_neg = 81,
1642
  src0_neg_W = 60,
1643
  src0_neg_X = 9,
1644
  src0_neg_Y = 26,
1645
  src0_neg_Z = 43,
1646
  src0_rel = 82,
1647
  src0_rel_W = 61,
1648
  src0_rel_X = 10,
1649
  src0_rel_Y = 27,
1650
  src0_rel_Z = 44,
1651
  src0_sel = 84,
1652
  src0_sel_W = 63,
1653
  src0_sel_X = 12,
1654
  src0_sel_Y = 29,
1655
  src0_sel_Z = 46,
1656
  src1 = 85,
1657
  src1_W = 64,
1658
  src1_X = 13,
1659
  src1_Y = 30,
1660
  src1_Z = 47,
1661
  src1_abs = 88,
1662
  src1_abs_W = 67,
1663
  src1_abs_X = 16,
1664
  src1_abs_Y = 33,
1665
  src1_abs_Z = 50,
1666
  src1_neg = 86,
1667
  src1_neg_W = 65,
1668
  src1_neg_X = 14,
1669
  src1_neg_Y = 31,
1670
  src1_neg_Z = 48,
1671
  src1_rel = 87,
1672
  src1_rel_W = 66,
1673
  src1_rel_X = 15,
1674
  src1_rel_Y = 32,
1675
  src1_rel_Z = 49,
1676
  src1_sel = 89,
1677
  src1_sel_W = 68,
1678
  src1_sel_X = 17,
1679
  src1_sel_Y = 34,
1680
  src1_sel_Z = 51,
1681
  src2 = 94,
1682
  src2_neg = 95,
1683
  src2_rel = 96,
1684
  src2_sel = 97,
1685
  update_exec_mask = 75,
1686
  update_exec_mask_W = 53,
1687
  update_exec_mask_X = 2,
1688
  update_exec_mask_Y = 19,
1689
  update_exec_mask_Z = 36,
1690
  update_pred = 76,
1691
  update_pred_W = 54,
1692
  update_pred_X = 3,
1693
  update_pred_Y = 20,
1694
  update_pred_Z = 37,
1695
  val = 74,
1696
  write = 77,
1697
  write_W = 55,
1698
  write_X = 4,
1699
  write_Y = 21,
1700
  write_Z = 38,
1701
OPERAND_LAST
1702
};
1703
} // end namespace OpName
1704
} // end namespace R600
1705
} // end namespace llvm
1706
#endif //GET_INSTRINFO_OPERAND_ENUM
1707
1708
#ifdef GET_INSTRINFO_NAMED_OPS
1709
#undef GET_INSTRINFO_NAMED_OPS
1710
namespace llvm {
1711
namespace R600 {
1712
LLVM_READONLY
1713
4.18M
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1714
4.18M
  static const int16_t OperandMap [][107] = {
1715
4.18M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1716
4.18M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1717
4.18M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1718
4.18M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1719
4.18M
{0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1720
4.18M
{0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1721
4.18M
{0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1722
4.18M
{0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1723
4.18M
{0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1724
4.18M
{-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1725
4.18M
{-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1726
4.18M
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1727
4.18M
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
1728
4.18M
};
1729
4.18M
  switch(Opcode) {
1730
4.18M
  case R600::CUBE_eg_pseudo:
1731
66
  case R600::CUBE_r600_pseudo:
1732
66
    return OperandMap[0][NamedIdx];
1733
570
  case R600::LDS_ADD_RET:
1734
570
  case R600::LDS_AND_RET:
1735
570
  case R600::LDS_MAX_INT_RET:
1736
570
  case R600::LDS_MAX_UINT_RET:
1737
570
  case R600::LDS_MIN_INT_RET:
1738
570
  case R600::LDS_MIN_UINT_RET:
1739
570
  case R600::LDS_OR_RET:
1740
570
  case R600::LDS_SUB_RET:
1741
570
  case R600::LDS_WRXCHG_RET:
1742
570
  case R600::LDS_XOR_RET:
1743
570
    return OperandMap[1][NamedIdx];
1744
570
  case R600::LDS_CMPST_RET:
1745
0
    return OperandMap[2][NamedIdx];
1746
12.9k
  case R600::LDS_BYTE_READ_RET:
1747
12.9k
  case R600::LDS_READ_RET:
1748
12.9k
  case R600::LDS_SHORT_READ_RET:
1749
12.9k
  case R600::LDS_UBYTE_READ_RET:
1750
12.9k
  case R600::LDS_USHORT_READ_RET:
1751
12.9k
    return OperandMap[3][NamedIdx];
1752
806k
  case R600::BFE_INT_eg:
1753
806k
  case R600::BFE_UINT_eg:
1754
806k
  case R600::BFI_INT_eg:
1755
806k
  case R600::BIT_ALIGN_INT_eg:
1756
806k
  case R600::CNDE_INT:
1757
806k
  case R600::CNDE_eg:
1758
806k
  case R600::CNDE_r600:
1759
806k
  case R600::CNDGE_INT:
1760
806k
  case R600::CNDGE_eg:
1761
806k
  case R600::CNDGE_r600:
1762
806k
  case R600::CNDGT_INT:
1763
806k
  case R600::CNDGT_eg:
1764
806k
  case R600::CNDGT_r600:
1765
806k
  case R600::FMA_eg:
1766
806k
  case R600::MULADD_IEEE_eg:
1767
806k
  case R600::MULADD_IEEE_r600:
1768
806k
  case R600::MULADD_INT24_cm:
1769
806k
  case R600::MULADD_UINT24_eg:
1770
806k
  case R600::MULADD_eg:
1771
806k
  case R600::MULADD_r600:
1772
806k
  case R600::MUL_LIT_eg:
1773
806k
  case R600::MUL_LIT_r600:
1774
806k
    return OperandMap[4][NamedIdx];
1775
806k
  case R600::BCNT_INT:
1776
251k
  case R600::CEIL:
1777
251k
  case R600::COS_cm:
1778
251k
  case R600::COS_eg:
1779
251k
  case R600::COS_r600:
1780
251k
  case R600::COS_r700:
1781
251k
  case R600::EXP_IEEE_cm:
1782
251k
  case R600::EXP_IEEE_eg:
1783
251k
  case R600::EXP_IEEE_r600:
1784
251k
  case R600::FFBH_UINT:
1785
251k
  case R600::FFBL_INT:
1786
251k
  case R600::FLOOR:
1787
251k
  case R600::FLT16_TO_FLT32:
1788
251k
  case R600::FLT32_TO_FLT16:
1789
251k
  case R600::FLT_TO_INT_eg:
1790
251k
  case R600::FLT_TO_INT_r600:
1791
251k
  case R600::FLT_TO_UINT_eg:
1792
251k
  case R600::FLT_TO_UINT_r600:
1793
251k
  case R600::FRACT:
1794
251k
  case R600::INTERP_LOAD_P0:
1795
251k
  case R600::INT_TO_FLT_eg:
1796
251k
  case R600::INT_TO_FLT_r600:
1797
251k
  case R600::LOG_CLAMPED_eg:
1798
251k
  case R600::LOG_CLAMPED_r600:
1799
251k
  case R600::LOG_IEEE_cm:
1800
251k
  case R600::LOG_IEEE_eg:
1801
251k
  case R600::LOG_IEEE_r600:
1802
251k
  case R600::MOV:
1803
251k
  case R600::MOVA_INT_eg:
1804
251k
  case R600::NOT_INT:
1805
251k
  case R600::RECIPSQRT_CLAMPED_cm:
1806
251k
  case R600::RECIPSQRT_CLAMPED_eg:
1807
251k
  case R600::RECIPSQRT_CLAMPED_r600:
1808
251k
  case R600::RECIPSQRT_IEEE_cm:
1809
251k
  case R600::RECIPSQRT_IEEE_eg:
1810
251k
  case R600::RECIPSQRT_IEEE_r600:
1811
251k
  case R600::RECIP_CLAMPED_cm:
1812
251k
  case R600::RECIP_CLAMPED_eg:
1813
251k
  case R600::RECIP_CLAMPED_r600:
1814
251k
  case R600::RECIP_IEEE_cm:
1815
251k
  case R600::RECIP_IEEE_eg:
1816
251k
  case R600::RECIP_IEEE_r600:
1817
251k
  case R600::RECIP_UINT_eg:
1818
251k
  case R600::RECIP_UINT_r600:
1819
251k
  case R600::RNDNE:
1820
251k
  case R600::SIN_cm:
1821
251k
  case R600::SIN_eg:
1822
251k
  case R600::SIN_r600:
1823
251k
  case R600::SIN_r700:
1824
251k
  case R600::TRUNC:
1825
251k
  case R600::UINT_TO_FLT_eg:
1826
251k
  case R600::UINT_TO_FLT_r600:
1827
251k
    return OperandMap[5][NamedIdx];
1828
3.04M
  case R600::ADD:
1829
3.04M
  case R600::ADDC_UINT:
1830
3.04M
  case R600::ADD_INT:
1831
3.04M
  case R600::AND_INT:
1832
3.04M
  case R600::ASHR_eg:
1833
3.04M
  case R600::ASHR_r600:
1834
3.04M
  case R600::BFM_INT_eg:
1835
3.04M
  case R600::CUBE_eg_real:
1836
3.04M
  case R600::CUBE_r600_real:
1837
3.04M
  case R600::DOT4_eg:
1838
3.04M
  case R600::DOT4_r600:
1839
3.04M
  case R600::INTERP_XY:
1840
3.04M
  case R600::INTERP_ZW:
1841
3.04M
  case R600::KILLGT:
1842
3.04M
  case R600::LSHL_eg:
1843
3.04M
  case R600::LSHL_r600:
1844
3.04M
  case R600::LSHR_eg:
1845
3.04M
  case R600::LSHR_r600:
1846
3.04M
  case R600::MAX:
1847
3.04M
  case R600::MAX_DX10:
1848
3.04M
  case R600::MAX_INT:
1849
3.04M
  case R600::MAX_UINT:
1850
3.04M
  case R600::MIN:
1851
3.04M
  case R600::MIN_DX10:
1852
3.04M
  case R600::MIN_INT:
1853
3.04M
  case R600::MIN_UINT:
1854
3.04M
  case R600::MUL:
1855
3.04M
  case R600::MULHI_INT_cm:
1856
3.04M
  case R600::MULHI_INT_cm24:
1857
3.04M
  case R600::MULHI_INT_eg:
1858
3.04M
  case R600::MULHI_INT_r600:
1859
3.04M
  case R600::MULHI_UINT24_eg:
1860
3.04M
  case R600::MULHI_UINT_cm:
1861
3.04M
  case R600::MULHI_UINT_cm24:
1862
3.04M
  case R600::MULHI_UINT_eg:
1863
3.04M
  case R600::MULHI_UINT_r600:
1864
3.04M
  case R600::MULLO_INT_cm:
1865
3.04M
  case R600::MULLO_INT_eg:
1866
3.04M
  case R600::MULLO_INT_r600:
1867
3.04M
  case R600::MULLO_UINT_cm:
1868
3.04M
  case R600::MULLO_UINT_eg:
1869
3.04M
  case R600::MULLO_UINT_r600:
1870
3.04M
  case R600::MUL_IEEE:
1871
3.04M
  case R600::MUL_INT24_cm:
1872
3.04M
  case R600::MUL_UINT24_eg:
1873
3.04M
  case R600::OR_INT:
1874
3.04M
  case R600::PRED_SETE:
1875
3.04M
  case R600::PRED_SETE_INT:
1876
3.04M
  case R600::PRED_SETGE:
1877
3.04M
  case R600::PRED_SETGE_INT:
1878
3.04M
  case R600::PRED_SETGT:
1879
3.04M
  case R600::PRED_SETGT_INT:
1880
3.04M
  case R600::PRED_SETNE:
1881
3.04M
  case R600::PRED_SETNE_INT:
1882
3.04M
  case R600::SETE:
1883
3.04M
  case R600::SETE_DX10:
1884
3.04M
  case R600::SETE_INT:
1885
3.04M
  case R600::SETGE_DX10:
1886
3.04M
  case R600::SETGE_INT:
1887
3.04M
  case R600::SETGE_UINT:
1888
3.04M
  case R600::SETGT_DX10:
1889
3.04M
  case R600::SETGT_INT:
1890
3.04M
  case R600::SETGT_UINT:
1891
3.04M
  case R600::SETNE_DX10:
1892
3.04M
  case R600::SETNE_INT:
1893
3.04M
  case R600::SGE:
1894
3.04M
  case R600::SGT:
1895
3.04M
  case R600::SNE:
1896
3.04M
  case R600::SUBB_UINT:
1897
3.04M
  case R600::SUB_INT:
1898
3.04M
  case R600::XOR_INT:
1899
3.04M
    return OperandMap[6][NamedIdx];
1900
3.04M
  case R600::DOT_4:
1901
17.0k
    return OperandMap[7][NamedIdx];
1902
3.04M
  case R600::R600_RegisterLoad:
1903
2.25k
    return OperandMap[8][NamedIdx];
1904
3.04M
  case R600::LDS_ADD:
1905
36.4k
  case R600::LDS_AND:
1906
36.4k
  case R600::LDS_BYTE_WRITE:
1907
36.4k
  case R600::LDS_MAX_INT:
1908
36.4k
  case R600::LDS_MAX_UINT:
1909
36.4k
  case R600::LDS_MIN_INT:
1910
36.4k
  case R600::LDS_MIN_UINT:
1911
36.4k
  case R600::LDS_OR:
1912
36.4k
  case R600::LDS_SHORT_WRITE:
1913
36.4k
  case R600::LDS_SUB:
1914
36.4k
  case R600::LDS_WRITE:
1915
36.4k
  case R600::LDS_WRXCHG:
1916
36.4k
  case R600::LDS_XOR:
1917
36.4k
    return OperandMap[9][NamedIdx];
1918
36.4k
  case R600::LDS_CMPST:
1919
0
    return OperandMap[10][NamedIdx];
1920
36.4k
  case R600::R600_RegisterStore:
1921
1.87k
    return OperandMap[11][NamedIdx];
1922
36.4k
  case R600::CF_ALU:
1923
6.89k
  case R600::CF_ALU_BREAK:
1924
6.89k
  case R600::CF_ALU_CONTINUE:
1925
6.89k
  case R600::CF_ALU_ELSE_AFTER:
1926
6.89k
  case R600::CF_ALU_POP_AFTER:
1927
6.89k
  case R600::CF_ALU_PUSH_BEFORE:
1928
6.89k
    return OperandMap[12][NamedIdx];
1929
6.89k
    
default: return -15.86k
;
1930
4.18M
  }
1931
4.18M
}
1932
} // end namespace R600
1933
} // end namespace llvm
1934
#endif //GET_INSTRINFO_NAMED_OPS
1935
1936
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1937
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1938
namespace llvm {
1939
namespace R600 {
1940
namespace OpTypes {
1941
enum OperandType {
1942
  ABS = 0,
1943
  BANK_SWIZZLE = 1,
1944
  CLAMP = 2,
1945
  CT = 3,
1946
  FRAMEri = 4,
1947
  InstFlag = 5,
1948
  KCACHE = 6,
1949
  LAST = 7,
1950
  LITERAL = 8,
1951
  MEMrr = 9,
1952
  MEMxi = 10,
1953
  NEG = 11,
1954
  OMOD = 12,
1955
  R600_Pred = 13,
1956
  REL = 14,
1957
  RSel = 15,
1958
  SEL = 16,
1959
  UEM = 17,
1960
  UP = 18,
1961
  WRITE = 19,
1962
  brtarget = 20,
1963
  f32imm = 21,
1964
  f64imm = 22,
1965
  i16imm = 23,
1966
  i1imm = 24,
1967
  i32imm = 25,
1968
  i64imm = 26,
1969
  i8imm = 27,
1970
  ptype0 = 28,
1971
  ptype1 = 29,
1972
  ptype2 = 30,
1973
  ptype3 = 31,
1974
  ptype4 = 32,
1975
  ptype5 = 33,
1976
  s16imm = 34,
1977
  type0 = 35,
1978
  type1 = 36,
1979
  type2 = 37,
1980
  type3 = 38,
1981
  type4 = 39,
1982
  type5 = 40,
1983
  u16imm = 41,
1984
  u32imm = 42,
1985
  u8imm = 43,
1986
  OPERAND_TYPE_LIST_END
1987
};
1988
} // end namespace OpTypes
1989
} // end namespace R600
1990
} // end namespace llvm
1991
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1992
1993
#ifdef GET_INSTRMAP_INFO
1994
#undef GET_INSTRMAP_INFO
1995
namespace llvm {
1996
1997
namespace R600 {
1998
1999
enum DisableEncoding {
2000
  DisableEncoding_
2001
};
2002
2003
// getLDSNoRetOp
2004
LLVM_READONLY
2005
30
int getLDSNoRetOp(uint16_t Opcode) {
2006
30
static const uint16_t getLDSNoRetOpTable[][2] = {
2007
30
  { R600::LDS_ADD_RET, R600::LDS_ADD },
2008
30
  { R600::LDS_AND_RET, R600::LDS_AND },
2009
30
  { R600::LDS_MAX_INT_RET, R600::LDS_MAX_INT },
2010
30
  { R600::LDS_MAX_UINT_RET, R600::LDS_MAX_UINT },
2011
30
  { R600::LDS_MIN_INT_RET, R600::LDS_MIN_INT },
2012
30
  { R600::LDS_MIN_UINT_RET, R600::LDS_MIN_UINT },
2013
30
  { R600::LDS_OR_RET, R600::LDS_OR },
2014
30
  { R600::LDS_SUB_RET, R600::LDS_SUB },
2015
30
  { R600::LDS_WRXCHG_RET, R600::LDS_WRXCHG },
2016
30
  { R600::LDS_XOR_RET, R600::LDS_XOR },
2017
30
}; // End of getLDSNoRetOpTable
2018
30
2019
30
  unsigned mid;
2020
30
  unsigned start = 0;
2021
30
  unsigned end = 10;
2022
94
  while (start < end) {
2023
94
    mid = start + (end - start)/2;
2024
94
    if (Opcode == getLDSNoRetOpTable[mid][0]) {
2025
30
      break;
2026
30
    }
2027
64
    if (Opcode < getLDSNoRetOpTable[mid][0])
2028
46
      end = mid;
2029
18
    else
2030
18
      start = mid + 1;
2031
64
  }
2032
30
  if (start == end)
2033
0
    return -1; // Instruction doesn't exist in this table.
2034
30
2035
30
  return getLDSNoRetOpTable[mid][1];
2036
30
}
2037
2038
} // End R600 namespace
2039
} // End llvm namespace
2040
#endif // GET_INSTRMAP_INFO
2041