Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/R600GenInstrInfo.inc
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace R600 {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    CFI_INSTRUCTION = 2,
18
    EH_LABEL  = 3,
19
    GC_LABEL  = 4,
20
    ANNOTATION_LABEL  = 5,
21
    KILL  = 6,
22
    EXTRACT_SUBREG  = 7,
23
    INSERT_SUBREG = 8,
24
    IMPLICIT_DEF  = 9,
25
    SUBREG_TO_REG = 10,
26
    COPY_TO_REGCLASS  = 11,
27
    DBG_VALUE = 12,
28
    DBG_LABEL = 13,
29
    REG_SEQUENCE  = 14,
30
    COPY  = 15,
31
    BUNDLE  = 16,
32
    LIFETIME_START  = 17,
33
    LIFETIME_END  = 18,
34
    STACKMAP  = 19,
35
    FENTRY_CALL = 20,
36
    PATCHPOINT  = 21,
37
    LOAD_STACK_GUARD  = 22,
38
    STATEPOINT  = 23,
39
    LOCAL_ESCAPE  = 24,
40
    FAULTING_OP = 25,
41
    PATCHABLE_OP  = 26,
42
    PATCHABLE_FUNCTION_ENTER  = 27,
43
    PATCHABLE_RET = 28,
44
    PATCHABLE_FUNCTION_EXIT = 29,
45
    PATCHABLE_TAIL_CALL = 30,
46
    PATCHABLE_EVENT_CALL  = 31,
47
    PATCHABLE_TYPED_EVENT_CALL  = 32,
48
    ICALL_BRANCH_FUNNEL = 33,
49
    G_ADD = 34,
50
    G_SUB = 35,
51
    G_MUL = 36,
52
    G_SDIV  = 37,
53
    G_UDIV  = 38,
54
    G_SREM  = 39,
55
    G_UREM  = 40,
56
    G_AND = 41,
57
    G_OR  = 42,
58
    G_XOR = 43,
59
    G_IMPLICIT_DEF  = 44,
60
    G_PHI = 45,
61
    G_FRAME_INDEX = 46,
62
    G_GLOBAL_VALUE  = 47,
63
    G_EXTRACT = 48,
64
    G_UNMERGE_VALUES  = 49,
65
    G_INSERT  = 50,
66
    G_MERGE_VALUES  = 51,
67
    G_PTRTOINT  = 52,
68
    G_INTTOPTR  = 53,
69
    G_BITCAST = 54,
70
    G_INTRINSIC_TRUNC = 55,
71
    G_INTRINSIC_ROUND = 56,
72
    G_LOAD  = 57,
73
    G_SEXTLOAD  = 58,
74
    G_ZEXTLOAD  = 59,
75
    G_STORE = 60,
76
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 61,
77
    G_ATOMIC_CMPXCHG  = 62,
78
    G_ATOMICRMW_XCHG  = 63,
79
    G_ATOMICRMW_ADD = 64,
80
    G_ATOMICRMW_SUB = 65,
81
    G_ATOMICRMW_AND = 66,
82
    G_ATOMICRMW_NAND  = 67,
83
    G_ATOMICRMW_OR  = 68,
84
    G_ATOMICRMW_XOR = 69,
85
    G_ATOMICRMW_MAX = 70,
86
    G_ATOMICRMW_MIN = 71,
87
    G_ATOMICRMW_UMAX  = 72,
88
    G_ATOMICRMW_UMIN  = 73,
89
    G_BRCOND  = 74,
90
    G_BRINDIRECT  = 75,
91
    G_INTRINSIC = 76,
92
    G_INTRINSIC_W_SIDE_EFFECTS  = 77,
93
    G_ANYEXT  = 78,
94
    G_TRUNC = 79,
95
    G_CONSTANT  = 80,
96
    G_FCONSTANT = 81,
97
    G_VASTART = 82,
98
    G_VAARG = 83,
99
    G_SEXT  = 84,
100
    G_ZEXT  = 85,
101
    G_SHL = 86,
102
    G_LSHR  = 87,
103
    G_ASHR  = 88,
104
    G_ICMP  = 89,
105
    G_FCMP  = 90,
106
    G_SELECT  = 91,
107
    G_UADDO = 92,
108
    G_UADDE = 93,
109
    G_USUBO = 94,
110
    G_USUBE = 95,
111
    G_SADDO = 96,
112
    G_SADDE = 97,
113
    G_SSUBO = 98,
114
    G_SSUBE = 99,
115
    G_UMULO = 100,
116
    G_SMULO = 101,
117
    G_UMULH = 102,
118
    G_SMULH = 103,
119
    G_FADD  = 104,
120
    G_FSUB  = 105,
121
    G_FMUL  = 106,
122
    G_FMA = 107,
123
    G_FDIV  = 108,
124
    G_FREM  = 109,
125
    G_FPOW  = 110,
126
    G_FEXP  = 111,
127
    G_FEXP2 = 112,
128
    G_FLOG  = 113,
129
    G_FLOG2 = 114,
130
    G_FNEG  = 115,
131
    G_FPEXT = 116,
132
    G_FPTRUNC = 117,
133
    G_FPTOSI  = 118,
134
    G_FPTOUI  = 119,
135
    G_SITOFP  = 120,
136
    G_UITOFP  = 121,
137
    G_FABS  = 122,
138
    G_GEP = 123,
139
    G_PTR_MASK  = 124,
140
    G_BR  = 125,
141
    G_INSERT_VECTOR_ELT = 126,
142
    G_EXTRACT_VECTOR_ELT  = 127,
143
    G_SHUFFLE_VECTOR  = 128,
144
    G_CTTZ  = 129,
145
    G_CTTZ_ZERO_UNDEF = 130,
146
    G_CTLZ  = 131,
147
    G_CTLZ_ZERO_UNDEF = 132,
148
    G_CTPOP = 133,
149
    G_BSWAP = 134,
150
    G_ADDRSPACE_CAST  = 135,
151
    G_BLOCK_ADDR  = 136,
152
    BRANCH  = 137,
153
    BRANCH_COND_f32 = 138,
154
    BRANCH_COND_i32 = 139,
155
    BREAK = 140,
156
    BREAKC_f32  = 141,
157
    BREAKC_i32  = 142,
158
    BREAK_LOGICALNZ_f32 = 143,
159
    BREAK_LOGICALNZ_i32 = 144,
160
    BREAK_LOGICALZ_f32  = 145,
161
    BREAK_LOGICALZ_i32  = 146,
162
    CONST_COPY  = 147,
163
    CONTINUE  = 148,
164
    CONTINUEC_f32 = 149,
165
    CONTINUEC_i32 = 150,
166
    CONTINUE_LOGICALNZ_f32  = 151,
167
    CONTINUE_LOGICALNZ_i32  = 152,
168
    CONTINUE_LOGICALZ_f32 = 153,
169
    CONTINUE_LOGICALZ_i32 = 154,
170
    CUBE_eg_pseudo  = 155,
171
    CUBE_r600_pseudo  = 156,
172
    DEFAULT = 157,
173
    DOT_4 = 158,
174
    DUMMY_CHAIN = 159,
175
    ELSE  = 160,
176
    END = 161,
177
    ENDFUNC = 162,
178
    ENDIF = 163,
179
    ENDLOOP = 164,
180
    ENDMAIN = 165,
181
    ENDSWITCH = 166,
182
    FABS_R600 = 167,
183
    FNEG_R600 = 168,
184
    FUNC  = 169,
185
    IFC_f32 = 170,
186
    IFC_i32 = 171,
187
    IF_LOGICALNZ_f32  = 172,
188
    IF_LOGICALNZ_i32  = 173,
189
    IF_LOGICALZ_f32 = 174,
190
    IF_LOGICALZ_i32 = 175,
191
    IF_PREDICATE_SET  = 176,
192
    JUMP  = 177,
193
    JUMP_COND = 178,
194
    MASK_WRITE  = 179,
195
    MOV_IMM_F32 = 180,
196
    MOV_IMM_GLOBAL_ADDR = 181,
197
    MOV_IMM_I32 = 182,
198
    PRED_X  = 183,
199
    R600_EXTRACT_ELT_V2 = 184,
200
    R600_EXTRACT_ELT_V4 = 185,
201
    R600_INSERT_ELT_V2  = 186,
202
    R600_INSERT_ELT_V4  = 187,
203
    R600_RegisterLoad = 188,
204
    R600_RegisterStore  = 189,
205
    RETDYN  = 190,
206
    RETURN  = 191,
207
    TXD = 192,
208
    TXD_SHADOW  = 193,
209
    WHILELOOP = 194,
210
    ADD = 195,
211
    ADDC_UINT = 196,
212
    ADD_INT = 197,
213
    ALU_CLAUSE  = 198,
214
    AND_INT = 199,
215
    ASHR_eg = 200,
216
    ASHR_r600 = 201,
217
    BCNT_INT  = 202,
218
    BFE_INT_eg  = 203,
219
    BFE_UINT_eg = 204,
220
    BFI_INT_eg  = 205,
221
    BFM_INT_eg  = 206,
222
    BIT_ALIGN_INT_eg  = 207,
223
    CEIL  = 208,
224
    CF_ALU  = 209,
225
    CF_ALU_BREAK  = 210,
226
    CF_ALU_CONTINUE = 211,
227
    CF_ALU_ELSE_AFTER = 212,
228
    CF_ALU_POP_AFTER  = 213,
229
    CF_ALU_PUSH_BEFORE  = 214,
230
    CF_CALL_FS_EG = 215,
231
    CF_CALL_FS_R600 = 216,
232
    CF_CONTINUE_EG  = 217,
233
    CF_CONTINUE_R600  = 218,
234
    CF_ELSE_EG  = 219,
235
    CF_ELSE_R600  = 220,
236
    CF_END_CM = 221,
237
    CF_END_EG = 222,
238
    CF_END_R600 = 223,
239
    CF_JUMP_EG  = 224,
240
    CF_JUMP_R600  = 225,
241
    CF_PUSH_EG  = 226,
242
    CF_PUSH_ELSE_R600 = 227,
243
    CF_TC_EG  = 228,
244
    CF_TC_R600  = 229,
245
    CF_VC_EG  = 230,
246
    CF_VC_R600  = 231,
247
    CNDE_INT  = 232,
248
    CNDE_eg = 233,
249
    CNDE_r600 = 234,
250
    CNDGE_INT = 235,
251
    CNDGE_eg  = 236,
252
    CNDGE_r600  = 237,
253
    CNDGT_INT = 238,
254
    CNDGT_eg  = 239,
255
    CNDGT_r600  = 240,
256
    COS_cm  = 241,
257
    COS_eg  = 242,
258
    COS_r600  = 243,
259
    COS_r700  = 244,
260
    CUBE_eg_real  = 245,
261
    CUBE_r600_real  = 246,
262
    DOT4_eg = 247,
263
    DOT4_r600 = 248,
264
    EG_ExportBuf  = 249,
265
    EG_ExportSwz  = 250,
266
    END_LOOP_EG = 251,
267
    END_LOOP_R600 = 252,
268
    EXP_IEEE_cm = 253,
269
    EXP_IEEE_eg = 254,
270
    EXP_IEEE_r600 = 255,
271
    FETCH_CLAUSE  = 256,
272
    FFBH_UINT = 257,
273
    FFBL_INT  = 258,
274
    FLOOR = 259,
275
    FLT16_TO_FLT32  = 260,
276
    FLT32_TO_FLT16  = 261,
277
    FLT_TO_INT_eg = 262,
278
    FLT_TO_INT_r600 = 263,
279
    FLT_TO_UINT_eg  = 264,
280
    FLT_TO_UINT_r600  = 265,
281
    FMA_eg  = 266,
282
    FRACT = 267,
283
    GROUP_BARRIER = 268,
284
    INTERP_LOAD_P0  = 269,
285
    INTERP_PAIR_XY  = 270,
286
    INTERP_PAIR_ZW  = 271,
287
    INTERP_VEC_LOAD = 272,
288
    INTERP_XY = 273,
289
    INTERP_ZW = 274,
290
    INT_TO_FLT_eg = 275,
291
    INT_TO_FLT_r600 = 276,
292
    KILLGT  = 277,
293
    LDS_ADD = 278,
294
    LDS_ADD_RET = 279,
295
    LDS_AND = 280,
296
    LDS_AND_RET = 281,
297
    LDS_BYTE_READ_RET = 282,
298
    LDS_BYTE_WRITE  = 283,
299
    LDS_CMPST = 284,
300
    LDS_CMPST_RET = 285,
301
    LDS_MAX_INT = 286,
302
    LDS_MAX_INT_RET = 287,
303
    LDS_MAX_UINT  = 288,
304
    LDS_MAX_UINT_RET  = 289,
305
    LDS_MIN_INT = 290,
306
    LDS_MIN_INT_RET = 291,
307
    LDS_MIN_UINT  = 292,
308
    LDS_MIN_UINT_RET  = 293,
309
    LDS_OR  = 294,
310
    LDS_OR_RET  = 295,
311
    LDS_READ_RET  = 296,
312
    LDS_SHORT_READ_RET  = 297,
313
    LDS_SHORT_WRITE = 298,
314
    LDS_SUB = 299,
315
    LDS_SUB_RET = 300,
316
    LDS_UBYTE_READ_RET  = 301,
317
    LDS_USHORT_READ_RET = 302,
318
    LDS_WRITE = 303,
319
    LDS_WRXCHG  = 304,
320
    LDS_WRXCHG_RET  = 305,
321
    LDS_XOR = 306,
322
    LDS_XOR_RET = 307,
323
    LITERALS  = 308,
324
    LOG_CLAMPED_eg  = 309,
325
    LOG_CLAMPED_r600  = 310,
326
    LOG_IEEE_cm = 311,
327
    LOG_IEEE_eg = 312,
328
    LOG_IEEE_r600 = 313,
329
    LOOP_BREAK_EG = 314,
330
    LOOP_BREAK_R600 = 315,
331
    LSHL_eg = 316,
332
    LSHL_r600 = 317,
333
    LSHR_eg = 318,
334
    LSHR_r600 = 319,
335
    MAX = 320,
336
    MAX_DX10  = 321,
337
    MAX_INT = 322,
338
    MAX_UINT  = 323,
339
    MIN = 324,
340
    MIN_DX10  = 325,
341
    MIN_INT = 326,
342
    MIN_UINT  = 327,
343
    MOV = 328,
344
    MOVA_INT_eg = 329,
345
    MUL = 330,
346
    MULADD_IEEE_eg  = 331,
347
    MULADD_IEEE_r600  = 332,
348
    MULADD_INT24_cm = 333,
349
    MULADD_UINT24_eg  = 334,
350
    MULADD_eg = 335,
351
    MULADD_r600 = 336,
352
    MULHI_INT_cm  = 337,
353
    MULHI_INT_cm24  = 338,
354
    MULHI_INT_eg  = 339,
355
    MULHI_INT_r600  = 340,
356
    MULHI_UINT24_eg = 341,
357
    MULHI_UINT_cm = 342,
358
    MULHI_UINT_cm24 = 343,
359
    MULHI_UINT_eg = 344,
360
    MULHI_UINT_r600 = 345,
361
    MULLO_INT_cm  = 346,
362
    MULLO_INT_eg  = 347,
363
    MULLO_INT_r600  = 348,
364
    MULLO_UINT_cm = 349,
365
    MULLO_UINT_eg = 350,
366
    MULLO_UINT_r600 = 351,
367
    MUL_IEEE  = 352,
368
    MUL_INT24_cm  = 353,
369
    MUL_LIT_eg  = 354,
370
    MUL_LIT_r600  = 355,
371
    MUL_UINT24_eg = 356,
372
    NOT_INT = 357,
373
    OR_INT  = 358,
374
    PAD = 359,
375
    POP_EG  = 360,
376
    POP_R600  = 361,
377
    PRED_SETE = 362,
378
    PRED_SETE_INT = 363,
379
    PRED_SETGE  = 364,
380
    PRED_SETGE_INT  = 365,
381
    PRED_SETGT  = 366,
382
    PRED_SETGT_INT  = 367,
383
    PRED_SETNE  = 368,
384
    PRED_SETNE_INT  = 369,
385
    R600_ExportBuf  = 370,
386
    R600_ExportSwz  = 371,
387
    RAT_ATOMIC_ADD_NORET  = 372,
388
    RAT_ATOMIC_ADD_RTN  = 373,
389
    RAT_ATOMIC_AND_NORET  = 374,
390
    RAT_ATOMIC_AND_RTN  = 375,
391
    RAT_ATOMIC_CMPXCHG_INT_NORET  = 376,
392
    RAT_ATOMIC_CMPXCHG_INT_RTN  = 377,
393
    RAT_ATOMIC_DEC_UINT_NORET = 378,
394
    RAT_ATOMIC_DEC_UINT_RTN = 379,
395
    RAT_ATOMIC_INC_UINT_NORET = 380,
396
    RAT_ATOMIC_INC_UINT_RTN = 381,
397
    RAT_ATOMIC_MAX_INT_NORET  = 382,
398
    RAT_ATOMIC_MAX_INT_RTN  = 383,
399
    RAT_ATOMIC_MAX_UINT_NORET = 384,
400
    RAT_ATOMIC_MAX_UINT_RTN = 385,
401
    RAT_ATOMIC_MIN_INT_NORET  = 386,
402
    RAT_ATOMIC_MIN_INT_RTN  = 387,
403
    RAT_ATOMIC_MIN_UINT_NORET = 388,
404
    RAT_ATOMIC_MIN_UINT_RTN = 389,
405
    RAT_ATOMIC_OR_NORET = 390,
406
    RAT_ATOMIC_OR_RTN = 391,
407
    RAT_ATOMIC_RSUB_NORET = 392,
408
    RAT_ATOMIC_RSUB_RTN = 393,
409
    RAT_ATOMIC_SUB_NORET  = 394,
410
    RAT_ATOMIC_SUB_RTN  = 395,
411
    RAT_ATOMIC_XCHG_INT_NORET = 396,
412
    RAT_ATOMIC_XCHG_INT_RTN = 397,
413
    RAT_ATOMIC_XOR_NORET  = 398,
414
    RAT_ATOMIC_XOR_RTN  = 399,
415
    RAT_MSKOR = 400,
416
    RAT_STORE_DWORD128  = 401,
417
    RAT_STORE_DWORD32 = 402,
418
    RAT_STORE_DWORD64 = 403,
419
    RAT_STORE_TYPED_cm  = 404,
420
    RAT_STORE_TYPED_eg  = 405,
421
    RAT_WRITE_CACHELESS_128_eg  = 406,
422
    RAT_WRITE_CACHELESS_32_eg = 407,
423
    RAT_WRITE_CACHELESS_64_eg = 408,
424
    RECIPSQRT_CLAMPED_cm  = 409,
425
    RECIPSQRT_CLAMPED_eg  = 410,
426
    RECIPSQRT_CLAMPED_r600  = 411,
427
    RECIPSQRT_IEEE_cm = 412,
428
    RECIPSQRT_IEEE_eg = 413,
429
    RECIPSQRT_IEEE_r600 = 414,
430
    RECIP_CLAMPED_cm  = 415,
431
    RECIP_CLAMPED_eg  = 416,
432
    RECIP_CLAMPED_r600  = 417,
433
    RECIP_IEEE_cm = 418,
434
    RECIP_IEEE_eg = 419,
435
    RECIP_IEEE_r600 = 420,
436
    RECIP_UINT_eg = 421,
437
    RECIP_UINT_r600 = 422,
438
    RNDNE = 423,
439
    SETE  = 424,
440
    SETE_DX10 = 425,
441
    SETE_INT  = 426,
442
    SETGE_DX10  = 427,
443
    SETGE_INT = 428,
444
    SETGE_UINT  = 429,
445
    SETGT_DX10  = 430,
446
    SETGT_INT = 431,
447
    SETGT_UINT  = 432,
448
    SETNE_DX10  = 433,
449
    SETNE_INT = 434,
450
    SGE = 435,
451
    SGT = 436,
452
    SIN_cm  = 437,
453
    SIN_eg  = 438,
454
    SIN_r600  = 439,
455
    SIN_r700  = 440,
456
    SNE = 441,
457
    SUBB_UINT = 442,
458
    SUB_INT = 443,
459
    TEX_GET_GRADIENTS_H = 444,
460
    TEX_GET_GRADIENTS_V = 445,
461
    TEX_GET_TEXTURE_RESINFO = 446,
462
    TEX_LD  = 447,
463
    TEX_LDPTR = 448,
464
    TEX_SAMPLE  = 449,
465
    TEX_SAMPLE_C  = 450,
466
    TEX_SAMPLE_C_G  = 451,
467
    TEX_SAMPLE_C_L  = 452,
468
    TEX_SAMPLE_C_LB = 453,
469
    TEX_SAMPLE_G  = 454,
470
    TEX_SAMPLE_L  = 455,
471
    TEX_SAMPLE_LB = 456,
472
    TEX_SET_GRADIENTS_H = 457,
473
    TEX_SET_GRADIENTS_V = 458,
474
    TEX_VTX_CONSTBUF  = 459,
475
    TEX_VTX_TEXBUF  = 460,
476
    TRUNC = 461,
477
    UINT_TO_FLT_eg  = 462,
478
    UINT_TO_FLT_r600  = 463,
479
    VTX_READ_128_cm = 464,
480
    VTX_READ_128_eg = 465,
481
    VTX_READ_16_cm  = 466,
482
    VTX_READ_16_eg  = 467,
483
    VTX_READ_32_cm  = 468,
484
    VTX_READ_32_eg  = 469,
485
    VTX_READ_64_cm  = 470,
486
    VTX_READ_64_eg  = 471,
487
    VTX_READ_8_cm = 472,
488
    VTX_READ_8_eg = 473,
489
    WHILE_LOOP_EG = 474,
490
    WHILE_LOOP_R600 = 475,
491
    XOR_INT = 476,
492
    INSTRUCTION_LIST_END = 477
493
  };
494
495
} // end R600 namespace
496
} // end llvm namespace
497
#endif // GET_INSTRINFO_ENUM
498
499
#ifdef GET_INSTRINFO_SCHED_ENUM
500
#undef GET_INSTRINFO_SCHED_ENUM
501
namespace llvm {
502
503
namespace R600 {
504
namespace Sched {
505
  enum {
506
    NoInstrModel  = 0,
507
    NullALU = 1,
508
    VecALU  = 2,
509
    AnyALU  = 3,
510
    TransALU  = 4,
511
    XALU  = 5,
512
    SCHED_LIST_END = 6
513
  };
514
} // end Sched namespace
515
} // end R600 namespace
516
} // end llvm namespace
517
#endif // GET_INSTRINFO_SCHED_ENUM
518
519
#ifdef GET_INSTRINFO_MC_DESC
520
#undef GET_INSTRINFO_MC_DESC
521
namespace llvm {
522
523
524
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
525
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
526
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
527
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
528
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
529
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
530
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
531
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
532
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
533
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
534
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
535
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
536
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
537
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
538
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
539
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
540
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
541
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
542
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
543
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
544
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
545
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
546
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
547
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
548
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
549
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
550
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
551
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
552
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
553
static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
554
static const MCOperandInfo OperandInfo32[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
555
static const MCOperandInfo OperandInfo33[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
556
static const MCOperandInfo OperandInfo34[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
557
static const MCOperandInfo OperandInfo35[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
558
static const MCOperandInfo OperandInfo36[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
559
static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
560
static const MCOperandInfo OperandInfo38[] = { { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
561
static const MCOperandInfo OperandInfo39[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
562
static const MCOperandInfo OperandInfo40[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
563
static const MCOperandInfo OperandInfo41[] = { { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
564
static const MCOperandInfo OperandInfo42[] = { { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
565
static const MCOperandInfo OperandInfo43[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
566
static const MCOperandInfo OperandInfo44[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
567
static const MCOperandInfo OperandInfo45[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
568
static const MCOperandInfo OperandInfo46[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
569
static const MCOperandInfo OperandInfo47[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
570
static const MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
571
static const MCOperandInfo OperandInfo49[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
572
static const MCOperandInfo OperandInfo50[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
573
static const MCOperandInfo OperandInfo51[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
574
static const MCOperandInfo OperandInfo52[] = { { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
575
static const MCOperandInfo OperandInfo53[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
576
static const MCOperandInfo OperandInfo54[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
577
static const MCOperandInfo OperandInfo55[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
578
static const MCOperandInfo OperandInfo56[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
579
static const MCOperandInfo OperandInfo57[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
580
static const MCOperandInfo OperandInfo58[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
581
static const MCOperandInfo OperandInfo59[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
582
static const MCOperandInfo OperandInfo60[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
583
static const MCOperandInfo OperandInfo61[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
584
static const MCOperandInfo OperandInfo62[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
585
static const MCOperandInfo OperandInfo63[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
586
static const MCOperandInfo OperandInfo64[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
587
static const MCOperandInfo OperandInfo65[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
588
static const MCOperandInfo OperandInfo66[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
589
static const MCOperandInfo OperandInfo67[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
590
static const MCOperandInfo OperandInfo68[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
591
static const MCOperandInfo OperandInfo69[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
592
static const MCOperandInfo OperandInfo70[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
593
static const MCOperandInfo OperandInfo71[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
594
595
extern const MCInstrDesc R600Insts[] = {
596
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
597
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
598
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
599
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
600
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
601
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
602
  { 6,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
603
  { 7,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
604
  { 8,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
605
  { 9,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
606
  { 10, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
607
  { 11, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
608
  { 12, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
609
  { 13, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
610
  { 14, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
611
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
612
  { 16, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
613
  { 17, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
614
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
615
  { 19, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
616
  { 20, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
617
  { 21, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
618
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
619
  { 23, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
620
  { 24, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
621
  { 25, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
622
  { 26, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
623
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
624
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
625
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
626
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
627
  { 31, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
628
  { 32, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
629
  { 33, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
630
  { 34, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
631
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
632
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
633
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
634
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
635
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
636
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
637
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
638
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
639
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
640
  { 44, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
641
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
642
  { 46, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
643
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
644
  { 48, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
645
  { 49, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
646
  { 50, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
647
  { 51, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
648
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
649
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
650
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
651
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #55 = G_INTRINSIC_TRUNC
652
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #56 = G_INTRINSIC_ROUND
653
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_LOAD
654
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_SEXTLOAD
655
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = G_ZEXTLOAD
656
  { 60, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #60 = G_STORE
657
  { 61, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #61 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
658
  { 62, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMIC_CMPXCHG
659
  { 63, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_XCHG
660
  { 64, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_ADD
661
  { 65, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_SUB
662
  { 66, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_AND
663
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_NAND
664
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_OR
665
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_XOR
666
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_MAX
667
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_MIN
668
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_UMAX
669
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_UMIN
670
  { 74, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #74 = G_BRCOND
671
  { 75, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #75 = G_BRINDIRECT
672
  { 76, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #76 = G_INTRINSIC
673
  { 77, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #77 = G_INTRINSIC_W_SIDE_EFFECTS
674
  { 78, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #78 = G_ANYEXT
675
  { 79, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #79 = G_TRUNC
676
  { 80, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #80 = G_CONSTANT
677
  { 81, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #81 = G_FCONSTANT
678
  { 82, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #82 = G_VASTART
679
  { 83, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #83 = G_VAARG
680
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #84 = G_SEXT
681
  { 85, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #85 = G_ZEXT
682
  { 86, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_SHL
683
  { 87, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #87 = G_LSHR
684
  { 88, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #88 = G_ASHR
685
  { 89, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #89 = G_ICMP
686
  { 90, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_FCMP
687
  { 91, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #91 = G_SELECT
688
  { 92, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #92 = G_UADDO
689
  { 93, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #93 = G_UADDE
690
  { 94, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #94 = G_USUBO
691
  { 95, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #95 = G_USUBE
692
  { 96, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_SADDO
693
  { 97, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #97 = G_SADDE
694
  { 98, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #98 = G_SSUBO
695
  { 99, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #99 = G_SSUBE
696
  { 100,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #100 = G_UMULO
697
  { 101,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #101 = G_SMULO
698
  { 102,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_UMULH
699
  { 103,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_SMULH
700
  { 104,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FADD
701
  { 105,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #105 = G_FSUB
702
  { 106,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_FMUL
703
  { 107,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FMA
704
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FDIV
705
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FREM
706
  { 110,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FPOW
707
  { 111,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #111 = G_FEXP
708
  { 112,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #112 = G_FEXP2
709
  { 113,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #113 = G_FLOG
710
  { 114,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #114 = G_FLOG2
711
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FNEG
712
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #116 = G_FPEXT
713
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #117 = G_FPTRUNC
714
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #118 = G_FPTOSI
715
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #119 = G_FPTOUI
716
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #120 = G_SITOFP
717
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_UITOFP
718
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #122 = G_FABS
719
  { 123,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #123 = G_GEP
720
  { 124,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #124 = G_PTR_MASK
721
  { 125,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #125 = G_BR
722
  { 126,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #126 = G_INSERT_VECTOR_ELT
723
  { 127,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #127 = G_EXTRACT_VECTOR_ELT
724
  { 128,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #128 = G_SHUFFLE_VECTOR
725
  { 129,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #129 = G_CTTZ
726
  { 130,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #130 = G_CTTZ_ZERO_UNDEF
727
  { 131,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #131 = G_CTLZ
728
  { 132,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #132 = G_CTLZ_ZERO_UNDEF
729
  { 133,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #133 = G_CTPOP
730
  { 134,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #134 = G_BSWAP
731
  { 135,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_ADDRSPACE_CAST
732
  { 136,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #136 = G_BLOCK_ADDR
733
  { 137,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #137 = BRANCH
734
  { 138,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #138 = BRANCH_COND_f32
735
  { 139,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #139 = BRANCH_COND_i32
736
  { 140,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #140 = BREAK
737
  { 141,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #141 = BREAKC_f32
738
  { 142,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #142 = BREAKC_i32
739
  { 143,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #143 = BREAK_LOGICALNZ_f32
740
  { 144,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #144 = BREAK_LOGICALNZ_i32
741
  { 145,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #145 = BREAK_LOGICALZ_f32
742
  { 146,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #146 = BREAK_LOGICALZ_i32
743
  { 147,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #147 = CONST_COPY
744
  { 148,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #148 = CONTINUE
745
  { 149,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #149 = CONTINUEC_f32
746
  { 150,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #150 = CONTINUEC_i32
747
  { 151,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #151 = CONTINUE_LOGICALNZ_f32
748
  { 152,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #152 = CONTINUE_LOGICALNZ_i32
749
  { 153,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #153 = CONTINUE_LOGICALZ_f32
750
  { 154,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #154 = CONTINUE_LOGICALZ_i32
751
  { 155,  2,  1,  0,  2,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #155 = CUBE_eg_pseudo
752
  { 156,  2,  1,  0,  2,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #156 = CUBE_r600_pseudo
753
  { 157,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #157 = DEFAULT
754
  { 158,  71, 1,  0,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #158 = DOT_4
755
  { 159,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #159 = DUMMY_CHAIN
756
  { 160,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #160 = ELSE
757
  { 161,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #161 = END
758
  { 162,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #162 = ENDFUNC
759
  { 163,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #163 = ENDIF
760
  { 164,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #164 = ENDLOOP
761
  { 165,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #165 = ENDMAIN
762
  { 166,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #166 = ENDSWITCH
763
  { 167,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #167 = FABS_R600
764
  { 168,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #168 = FNEG_R600
765
  { 169,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #169 = FUNC
766
  { 170,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #170 = IFC_f32
767
  { 171,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #171 = IFC_i32
768
  { 172,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #172 = IF_LOGICALNZ_f32
769
  { 173,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #173 = IF_LOGICALNZ_i32
770
  { 174,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #174 = IF_LOGICALZ_f32
771
  { 175,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #175 = IF_LOGICALZ_i32
772
  { 176,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #176 = IF_PREDICATE_SET
773
  { 177,  1,  0,  0,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #177 = JUMP
774
  { 178,  2,  0,  0,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #178 = JUMP_COND
775
  { 179,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #179 = MASK_WRITE
776
  { 180,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #180 = MOV_IMM_F32
777
  { 181,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #181 = MOV_IMM_GLOBAL_ADDR
778
  { 182,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #182 = MOV_IMM_I32
779
  { 183,  4,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #183 = PRED_X
780
  { 184,  3,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #184 = R600_EXTRACT_ELT_V2
781
  { 185,  3,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #185 = R600_EXTRACT_ELT_V4
782
  { 186,  4,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #186 = R600_INSERT_ELT_V2
783
  { 187,  4,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #187 = R600_INSERT_ELT_V4
784
  { 188,  4,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #188 = R600_RegisterLoad
785
  { 189,  4,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #189 = R600_RegisterStore
786
  { 190,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #190 = RETDYN
787
  { 191,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #191 = RETURN
788
  { 192,  7,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #192 = TXD
789
  { 193,  7,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #193 = TXD_SHADOW
790
  { 194,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #194 = WHILELOOP
791
  { 195,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #195 = ADD
792
  { 196,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #196 = ADDC_UINT
793
  { 197,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #197 = ADD_INT
794
  { 198,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #198 = ALU_CLAUSE
795
  { 199,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #199 = AND_INT
796
  { 200,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #200 = ASHR_eg
797
  { 201,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #201 = ASHR_r600
798
  { 202,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #202 = BCNT_INT
799
  { 203,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #203 = BFE_INT_eg
800
  { 204,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #204 = BFE_UINT_eg
801
  { 205,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #205 = BFI_INT_eg
802
  { 206,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #206 = BFM_INT_eg
803
  { 207,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #207 = BIT_ALIGN_INT_eg
804
  { 208,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #208 = CEIL
805
  { 209,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #209 = CF_ALU
806
  { 210,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #210 = CF_ALU_BREAK
807
  { 211,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #211 = CF_ALU_CONTINUE
808
  { 212,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #212 = CF_ALU_ELSE_AFTER
809
  { 213,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #213 = CF_ALU_POP_AFTER
810
  { 214,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #214 = CF_ALU_PUSH_BEFORE
811
  { 215,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #215 = CF_CALL_FS_EG
812
  { 216,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #216 = CF_CALL_FS_R600
813
  { 217,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #217 = CF_CONTINUE_EG
814
  { 218,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #218 = CF_CONTINUE_R600
815
  { 219,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #219 = CF_ELSE_EG
816
  { 220,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #220 = CF_ELSE_R600
817
  { 221,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #221 = CF_END_CM
818
  { 222,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #222 = CF_END_EG
819
  { 223,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #223 = CF_END_R600
820
  { 224,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #224 = CF_JUMP_EG
821
  { 225,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #225 = CF_JUMP_R600
822
  { 226,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #226 = CF_PUSH_EG
823
  { 227,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #227 = CF_PUSH_ELSE_R600
824
  { 228,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #228 = CF_TC_EG
825
  { 229,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #229 = CF_TC_R600
826
  { 230,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #230 = CF_VC_EG
827
  { 231,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #231 = CF_VC_R600
828
  { 232,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #232 = CNDE_INT
829
  { 233,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #233 = CNDE_eg
830
  { 234,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #234 = CNDE_r600
831
  { 235,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #235 = CNDGE_INT
832
  { 236,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #236 = CNDGE_eg
833
  { 237,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #237 = CNDGE_r600
834
  { 238,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #238 = CNDGT_INT
835
  { 239,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #239 = CNDGT_eg
836
  { 240,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #240 = CNDGT_r600
837
  { 241,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4650ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #241 = COS_cm
838
  { 242,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #242 = COS_eg
839
  { 243,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #243 = COS_r600
840
  { 244,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #244 = COS_r700
841
  { 245,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #245 = CUBE_eg_real
842
  { 246,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #246 = CUBE_r600_real
843
  { 247,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #247 = DOT4_eg
844
  { 248,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #248 = DOT4_r600
845
  { 249,  7,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #249 = EG_ExportBuf
846
  { 250,  9,  0,  0,  1,  0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #250 = EG_ExportSwz
847
  { 251,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #251 = END_LOOP_EG
848
  { 252,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #252 = END_LOOP_R600
849
  { 253,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #253 = EXP_IEEE_cm
850
  { 254,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #254 = EXP_IEEE_eg
851
  { 255,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #255 = EXP_IEEE_r600
852
  { 256,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #256 = FETCH_CLAUSE
853
  { 257,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #257 = FFBH_UINT
854
  { 258,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #258 = FFBL_INT
855
  { 259,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #259 = FLOOR
856
  { 260,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #260 = FLT16_TO_FLT32
857
  { 261,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #261 = FLT32_TO_FLT16
858
  { 262,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #262 = FLT_TO_INT_eg
859
  { 263,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #263 = FLT_TO_INT_r600
860
  { 264,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #264 = FLT_TO_UINT_eg
861
  { 265,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #265 = FLT_TO_UINT_r600
862
  { 266,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #266 = FMA_eg
863
  { 267,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #267 = FRACT
864
  { 268,  0,  0,  0,  3,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #268 = GROUP_BARRIER
865
  { 269,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #269 = INTERP_LOAD_P0
866
  { 270,  5,  2,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #270 = INTERP_PAIR_XY
867
  { 271,  5,  2,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #271 = INTERP_PAIR_ZW
868
  { 272,  2,  1,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #272 = INTERP_VEC_LOAD
869
  { 273,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #273 = INTERP_XY
870
  { 274,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #274 = INTERP_ZW
871
  { 275,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #275 = INT_TO_FLT_eg
872
  { 276,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #276 = INT_TO_FLT_r600
873
  { 277,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #277 = KILLGT
874
  { 278,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #278 = LDS_ADD
875
  { 279,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #279 = LDS_ADD_RET
876
  { 280,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #280 = LDS_AND
877
  { 281,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #281 = LDS_AND_RET
878
  { 282,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #282 = LDS_BYTE_READ_RET
879
  { 283,  9,  0,  0,  5,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #283 = LDS_BYTE_WRITE
880
  { 284,  12, 0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #284 = LDS_CMPST
881
  { 285,  13, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #285 = LDS_CMPST_RET
882
  { 286,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #286 = LDS_MAX_INT
883
  { 287,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #287 = LDS_MAX_INT_RET
884
  { 288,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #288 = LDS_MAX_UINT
885
  { 289,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #289 = LDS_MAX_UINT_RET
886
  { 290,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #290 = LDS_MIN_INT
887
  { 291,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #291 = LDS_MIN_INT_RET
888
  { 292,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #292 = LDS_MIN_UINT
889
  { 293,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #293 = LDS_MIN_UINT_RET
890
  { 294,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #294 = LDS_OR
891
  { 295,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #295 = LDS_OR_RET
892
  { 296,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #296 = LDS_READ_RET
893
  { 297,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #297 = LDS_SHORT_READ_RET
894
  { 298,  9,  0,  0,  5,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #298 = LDS_SHORT_WRITE
895
  { 299,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #299 = LDS_SUB
896
  { 300,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #300 = LDS_SUB_RET
897
  { 301,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #301 = LDS_UBYTE_READ_RET
898
  { 302,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #302 = LDS_USHORT_READ_RET
899
  { 303,  9,  0,  0,  5,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #303 = LDS_WRITE
900
  { 304,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #304 = LDS_WRXCHG
901
  { 305,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #305 = LDS_WRXCHG_RET
902
  { 306,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #306 = LDS_XOR
903
  { 307,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #307 = LDS_XOR_RET
904
  { 308,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #308 = LITERALS
905
  { 309,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #309 = LOG_CLAMPED_eg
906
  { 310,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #310 = LOG_CLAMPED_r600
907
  { 311,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #311 = LOG_IEEE_cm
908
  { 312,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #312 = LOG_IEEE_eg
909
  { 313,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #313 = LOG_IEEE_r600
910
  { 314,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #314 = LOOP_BREAK_EG
911
  { 315,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #315 = LOOP_BREAK_R600
912
  { 316,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #316 = LSHL_eg
913
  { 317,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #317 = LSHL_r600
914
  { 318,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #318 = LSHR_eg
915
  { 319,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #319 = LSHR_r600
916
  { 320,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #320 = MAX
917
  { 321,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #321 = MAX_DX10
918
  { 322,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #322 = MAX_INT
919
  { 323,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #323 = MAX_UINT
920
  { 324,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #324 = MIN
921
  { 325,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #325 = MIN_DX10
922
  { 326,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #326 = MIN_INT
923
  { 327,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #327 = MIN_UINT
924
  { 328,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #328 = MOV
925
  { 329,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #329 = MOVA_INT_eg
926
  { 330,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #330 = MUL
927
  { 331,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #331 = MULADD_IEEE_eg
928
  { 332,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #332 = MULADD_IEEE_r600
929
  { 333,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #333 = MULADD_INT24_cm
930
  { 334,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #334 = MULADD_UINT24_eg
931
  { 335,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #335 = MULADD_eg
932
  { 336,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #336 = MULADD_r600
933
  { 337,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #337 = MULHI_INT_cm
934
  { 338,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #338 = MULHI_INT_cm24
935
  { 339,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #339 = MULHI_INT_eg
936
  { 340,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #340 = MULHI_INT_r600
937
  { 341,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #341 = MULHI_UINT24_eg
938
  { 342,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #342 = MULHI_UINT_cm
939
  { 343,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #343 = MULHI_UINT_cm24
940
  { 344,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #344 = MULHI_UINT_eg
941
  { 345,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #345 = MULHI_UINT_r600
942
  { 346,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #346 = MULLO_INT_cm
943
  { 347,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #347 = MULLO_INT_eg
944
  { 348,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #348 = MULLO_INT_r600
945
  { 349,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #349 = MULLO_UINT_cm
946
  { 350,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #350 = MULLO_UINT_eg
947
  { 351,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #351 = MULLO_UINT_r600
948
  { 352,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #352 = MUL_IEEE
949
  { 353,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #353 = MUL_INT24_cm
950
  { 354,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #354 = MUL_LIT_eg
951
  { 355,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #355 = MUL_LIT_r600
952
  { 356,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #356 = MUL_UINT24_eg
953
  { 357,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #357 = NOT_INT
954
  { 358,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #358 = OR_INT
955
  { 359,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #359 = PAD
956
  { 360,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #360 = POP_EG
957
  { 361,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #361 = POP_R600
958
  { 362,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #362 = PRED_SETE
959
  { 363,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #363 = PRED_SETE_INT
960
  { 364,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #364 = PRED_SETGE
961
  { 365,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #365 = PRED_SETGE_INT
962
  { 366,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #366 = PRED_SETGT
963
  { 367,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #367 = PRED_SETGT_INT
964
  { 368,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #368 = PRED_SETNE
965
  { 369,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #369 = PRED_SETNE_INT
966
  { 370,  7,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #370 = R600_ExportBuf
967
  { 371,  9,  0,  0,  1,  0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #371 = R600_ExportSwz
968
  { 372,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #372 = RAT_ATOMIC_ADD_NORET
969
  { 373,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #373 = RAT_ATOMIC_ADD_RTN
970
  { 374,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #374 = RAT_ATOMIC_AND_NORET
971
  { 375,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #375 = RAT_ATOMIC_AND_RTN
972
  { 376,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #376 = RAT_ATOMIC_CMPXCHG_INT_NORET
973
  { 377,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #377 = RAT_ATOMIC_CMPXCHG_INT_RTN
974
  { 378,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #378 = RAT_ATOMIC_DEC_UINT_NORET
975
  { 379,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #379 = RAT_ATOMIC_DEC_UINT_RTN
976
  { 380,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #380 = RAT_ATOMIC_INC_UINT_NORET
977
  { 381,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #381 = RAT_ATOMIC_INC_UINT_RTN
978
  { 382,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #382 = RAT_ATOMIC_MAX_INT_NORET
979
  { 383,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #383 = RAT_ATOMIC_MAX_INT_RTN
980
  { 384,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #384 = RAT_ATOMIC_MAX_UINT_NORET
981
  { 385,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #385 = RAT_ATOMIC_MAX_UINT_RTN
982
  { 386,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #386 = RAT_ATOMIC_MIN_INT_NORET
983
  { 387,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #387 = RAT_ATOMIC_MIN_INT_RTN
984
  { 388,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #388 = RAT_ATOMIC_MIN_UINT_NORET
985
  { 389,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #389 = RAT_ATOMIC_MIN_UINT_RTN
986
  { 390,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #390 = RAT_ATOMIC_OR_NORET
987
  { 391,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #391 = RAT_ATOMIC_OR_RTN
988
  { 392,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #392 = RAT_ATOMIC_RSUB_NORET
989
  { 393,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #393 = RAT_ATOMIC_RSUB_RTN
990
  { 394,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #394 = RAT_ATOMIC_SUB_NORET
991
  { 395,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #395 = RAT_ATOMIC_SUB_RTN
992
  { 396,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #396 = RAT_ATOMIC_XCHG_INT_NORET
993
  { 397,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #397 = RAT_ATOMIC_XCHG_INT_RTN
994
  { 398,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #398 = RAT_ATOMIC_XOR_NORET
995
  { 399,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #399 = RAT_ATOMIC_XOR_RTN
996
  { 400,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #400 = RAT_MSKOR
997
  { 401,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #401 = RAT_STORE_DWORD128
998
  { 402,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #402 = RAT_STORE_DWORD32
999
  { 403,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #403 = RAT_STORE_DWORD64
1000
  { 404,  4,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #404 = RAT_STORE_TYPED_cm
1001
  { 405,  4,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #405 = RAT_STORE_TYPED_eg
1002
  { 406,  3,  0,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #406 = RAT_WRITE_CACHELESS_128_eg
1003
  { 407,  3,  0,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #407 = RAT_WRITE_CACHELESS_32_eg
1004
  { 408,  3,  0,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #408 = RAT_WRITE_CACHELESS_64_eg
1005
  { 409,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #409 = RECIPSQRT_CLAMPED_cm
1006
  { 410,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #410 = RECIPSQRT_CLAMPED_eg
1007
  { 411,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #411 = RECIPSQRT_CLAMPED_r600
1008
  { 412,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #412 = RECIPSQRT_IEEE_cm
1009
  { 413,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #413 = RECIPSQRT_IEEE_eg
1010
  { 414,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #414 = RECIPSQRT_IEEE_r600
1011
  { 415,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #415 = RECIP_CLAMPED_cm
1012
  { 416,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #416 = RECIP_CLAMPED_eg
1013
  { 417,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #417 = RECIP_CLAMPED_r600
1014
  { 418,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #418 = RECIP_IEEE_cm
1015
  { 419,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #419 = RECIP_IEEE_eg
1016
  { 420,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #420 = RECIP_IEEE_r600
1017
  { 421,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #421 = RECIP_UINT_eg
1018
  { 422,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #422 = RECIP_UINT_r600
1019
  { 423,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #423 = RNDNE
1020
  { 424,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #424 = SETE
1021
  { 425,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #425 = SETE_DX10
1022
  { 426,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #426 = SETE_INT
1023
  { 427,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #427 = SETGE_DX10
1024
  { 428,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #428 = SETGE_INT
1025
  { 429,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #429 = SETGE_UINT
1026
  { 430,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #430 = SETGT_DX10
1027
  { 431,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #431 = SETGT_INT
1028
  { 432,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #432 = SETGT_UINT
1029
  { 433,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #433 = SETNE_DX10
1030
  { 434,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #434 = SETNE_INT
1031
  { 435,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #435 = SGE
1032
  { 436,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #436 = SGT
1033
  { 437,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4650ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #437 = SIN_cm
1034
  { 438,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #438 = SIN_eg
1035
  { 439,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #439 = SIN_r600
1036
  { 440,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #440 = SIN_r700
1037
  { 441,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #441 = SNE
1038
  { 442,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #442 = SUBB_UINT
1039
  { 443,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #443 = SUB_INT
1040
  { 444,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #444 = TEX_GET_GRADIENTS_H
1041
  { 445,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #445 = TEX_GET_GRADIENTS_V
1042
  { 446,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #446 = TEX_GET_TEXTURE_RESINFO
1043
  { 447,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #447 = TEX_LD
1044
  { 448,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #448 = TEX_LDPTR
1045
  { 449,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #449 = TEX_SAMPLE
1046
  { 450,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #450 = TEX_SAMPLE_C
1047
  { 451,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #451 = TEX_SAMPLE_C_G
1048
  { 452,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #452 = TEX_SAMPLE_C_L
1049
  { 453,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #453 = TEX_SAMPLE_C_LB
1050
  { 454,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #454 = TEX_SAMPLE_G
1051
  { 455,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #455 = TEX_SAMPLE_L
1052
  { 456,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #456 = TEX_SAMPLE_LB
1053
  { 457,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #457 = TEX_SET_GRADIENTS_H
1054
  { 458,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #458 = TEX_SET_GRADIENTS_V
1055
  { 459,  4,  1,  0,  1,  0, 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #459 = TEX_VTX_CONSTBUF
1056
  { 460,  4,  1,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #460 = TEX_VTX_TEXBUF
1057
  { 461,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #461 = TRUNC
1058
  { 462,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #462 = UINT_TO_FLT_eg
1059
  { 463,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #463 = UINT_TO_FLT_r600
1060
  { 464,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #464 = VTX_READ_128_cm
1061
  { 465,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #465 = VTX_READ_128_eg
1062
  { 466,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #466 = VTX_READ_16_cm
1063
  { 467,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #467 = VTX_READ_16_eg
1064
  { 468,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #468 = VTX_READ_32_cm
1065
  { 469,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #469 = VTX_READ_32_eg
1066
  { 470,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #470 = VTX_READ_64_cm
1067
  { 471,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #471 = VTX_READ_64_eg
1068
  { 472,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #472 = VTX_READ_8_cm
1069
  { 473,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #473 = VTX_READ_8_eg
1070
  { 474,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #474 = WHILE_LOOP_EG
1071
  { 475,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #475 = WHILE_LOOP_R600
1072
  { 476,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #476 = XOR_INT
1073
};
1074
1075
extern const char R600InstrNameData[] = {
1076
  /* 0 */ 'C', 'F', '_', 'T', 'C', '_', 'R', '6', '0', '0', 0,
1077
  /* 11 */ 'C', 'F', '_', 'V', 'C', '_', 'R', '6', '0', '0', 0,
1078
  /* 22 */ 'C', 'F', '_', 'E', 'N', 'D', '_', 'R', '6', '0', '0', 0,
1079
  /* 34 */ 'C', 'F', '_', 'E', 'L', 'S', 'E', '_', 'R', '6', '0', '0', 0,
1080
  /* 47 */ 'C', 'F', '_', 'P', 'U', 'S', 'H', '_', 'E', 'L', 'S', 'E', '_', 'R', '6', '0', '0', 0,
1081
  /* 65 */ 'C', 'F', '_', 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'R', '6', '0', '0', 0,
1082
  /* 82 */ 'F', 'N', 'E', 'G', '_', 'R', '6', '0', '0', 0,
1083
  /* 92 */ 'L', 'O', 'O', 'P', '_', 'B', 'R', 'E', 'A', 'K', '_', 'R', '6', '0', '0', 0,
1084
  /* 108 */ 'C', 'F', '_', 'J', 'U', 'M', 'P', '_', 'R', '6', '0', '0', 0,
1085
  /* 121 */ 'E', 'N', 'D', '_', 'L', 'O', 'O', 'P', '_', 'R', '6', '0', '0', 0,
1086
  /* 135 */ 'W', 'H', 'I', 'L', 'E', '_', 'L', 'O', 'O', 'P', '_', 'R', '6', '0', '0', 0,
1087
  /* 151 */ 'P', 'O', 'P', '_', 'R', '6', '0', '0', 0,
1088
  /* 160 */ 'F', 'A', 'B', 'S', '_', 'R', '6', '0', '0', 0,
1089
  /* 170 */ 'C', 'F', '_', 'C', 'A', 'L', 'L', '_', 'F', 'S', '_', 'R', '6', '0', '0', 0,
1090
  /* 186 */ 'D', 'O', 'T', '4', '_', 'r', '6', '0', '0', 0,
1091
  /* 196 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'r', '6', '0', '0', 0,
1092
  /* 208 */ 'L', 'O', 'G', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'r', '6', '0', '0', 0,
1093
  /* 225 */ 'R', 'E', 'C', 'I', 'P', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'r', '6', '0', '0', 0,
1094
  /* 244 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'r', '6', '0', '0', 0,
1095
  /* 267 */ 'C', 'N', 'D', 'E', '_', 'r', '6', '0', '0', 0,
1096
  /* 277 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1097
  /* 294 */ 'L', 'O', 'G', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1098
  /* 308 */ 'R', 'E', 'C', 'I', 'P', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1099
  /* 324 */ 'E', 'X', 'P', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1100
  /* 338 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1101
  /* 358 */ 'C', 'N', 'D', 'G', 'E', '_', 'r', '6', '0', '0', 0,
1102
  /* 369 */ 'L', 'S', 'H', 'L', '_', 'r', '6', '0', '0', 0,
1103
  /* 379 */ 'S', 'I', 'N', '_', 'r', '6', '0', '0', 0,
1104
  /* 388 */ 'A', 'S', 'H', 'R', '_', 'r', '6', '0', '0', 0,
1105
  /* 398 */ 'L', 'S', 'H', 'R', '_', 'r', '6', '0', '0', 0,
1106
  /* 408 */ 'C', 'O', 'S', '_', 'r', '6', '0', '0', 0,
1107
  /* 417 */ 'C', 'N', 'D', 'G', 'T', '_', 'r', '6', '0', '0', 0,
1108
  /* 428 */ 'M', 'U', 'L', '_', 'L', 'I', 'T', '_', 'r', '6', '0', '0', 0,
1109
  /* 441 */ 'U', 'I', 'N', 'T', '_', 'T', 'O', '_', 'F', 'L', 'T', '_', 'r', '6', '0', '0', 0,
1110
  /* 458 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1111
  /* 474 */ 'M', 'U', 'L', 'L', 'O', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1112
  /* 490 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1113
  /* 507 */ 'R', 'E', 'C', 'I', 'P', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1114
  /* 523 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1115
  /* 538 */ 'M', 'U', 'L', 'L', 'O', '_', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1116
  /* 553 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1117
  /* 569 */ 'S', 'I', 'N', '_', 'r', '7', '0', '0', 0,
1118
  /* 578 */ 'C', 'O', 'S', '_', 'r', '7', '0', '0', 0,
1119
  /* 587 */ 'S', 'E', 'T', 'G', 'E', '_', 'D', 'X', '1', '0', 0,
1120
  /* 598 */ 'S', 'E', 'T', 'N', 'E', '_', 'D', 'X', '1', '0', 0,
1121
  /* 609 */ 'S', 'E', 'T', 'E', '_', 'D', 'X', '1', '0', 0,
1122
  /* 619 */ 'M', 'I', 'N', '_', 'D', 'X', '1', '0', 0,
1123
  /* 628 */ 'S', 'E', 'T', 'G', 'T', '_', 'D', 'X', '1', '0', 0,
1124
  /* 639 */ 'M', 'A', 'X', '_', 'D', 'X', '1', '0', 0,
1125
  /* 648 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'L', 'O', 'A', 'D', '_', 'P', '0', 0,
1126
  /* 663 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'D', 'W', 'O', 'R', 'D', '3', '2', 0,
1127
  /* 681 */ 'M', 'O', 'V', '_', 'I', 'M', 'M', '_', 'F', '3', '2', 0,
1128
  /* 693 */ 'M', 'O', 'V', '_', 'I', 'M', 'M', '_', 'I', '3', '2', 0,
1129
  /* 705 */ 'F', 'L', 'T', '1', '6', '_', 'T', 'O', '_', 'F', 'L', 'T', '3', '2', 0,
1130
  /* 720 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', 'C', '_', 'f', '3', '2', 0,
1131
  /* 734 */ 'I', 'F', 'C', '_', 'f', '3', '2', 0,
1132
  /* 742 */ 'B', 'R', 'E', 'A', 'K', 'C', '_', 'f', '3', '2', 0,
1133
  /* 753 */ 'B', 'R', 'A', 'N', 'C', 'H', '_', 'C', 'O', 'N', 'D', '_', 'f', '3', '2', 0,
1134
  /* 769 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'f', '3', '2', 0,
1135
  /* 791 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'f', '3', '2', 0,
1136
  /* 807 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'f', '3', '2', 0,
1137
  /* 826 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'f', '3', '2', 0,
1138
  /* 849 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'f', '3', '2', 0,
1139
  /* 866 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'f', '3', '2', 0,
1140
  /* 886 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', 'C', '_', 'i', '3', '2', 0,
1141
  /* 900 */ 'I', 'F', 'C', '_', 'i', '3', '2', 0,
1142
  /* 908 */ 'B', 'R', 'E', 'A', 'K', 'C', '_', 'i', '3', '2', 0,
1143
  /* 919 */ 'B', 'R', 'A', 'N', 'C', 'H', '_', 'C', 'O', 'N', 'D', '_', 'i', '3', '2', 0,
1144
  /* 935 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'i', '3', '2', 0,
1145
  /* 957 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'i', '3', '2', 0,
1146
  /* 973 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'i', '3', '2', 0,
1147
  /* 992 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'i', '3', '2', 0,
1148
  /* 1015 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'i', '3', '2', 0,
1149
  /* 1032 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'i', '3', '2', 0,
1150
  /* 1052 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
1151
  /* 1060 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
1152
  /* 1068 */ 'R', '6', '0', '0', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'E', 'L', 'T', '_', 'V', '2', 0,
1153
  /* 1088 */ 'R', '6', '0', '0', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'E', 'L', 'T', '_', 'V', '2', 0,
1154
  /* 1107 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'c', 'm', '2', '4', 0,
1155
  /* 1123 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'c', 'm', '2', '4', 0,
1156
  /* 1138 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'D', 'W', 'O', 'R', 'D', '6', '4', 0,
1157
  /* 1156 */ 'R', '6', '0', '0', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'E', 'L', 'T', '_', 'V', '4', 0,
1158
  /* 1176 */ 'R', '6', '0', '0', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'E', 'L', 'T', '_', 'V', '4', 0,
1159
  /* 1195 */ 'D', 'O', 'T', '_', '4', 0,
1160
  /* 1201 */ 'F', 'L', 'T', '3', '2', '_', 'T', 'O', '_', 'F', 'L', 'T', '1', '6', 0,
1161
  /* 1216 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'D', 'W', 'O', 'R', 'D', '1', '2', '8', 0,
1162
  /* 1235 */ 'G', '_', 'F', 'M', 'A', 0,
1163
  /* 1241 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', '_', 'L', 'B', 0,
1164
  /* 1257 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'L', 'B', 0,
1165
  /* 1271 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
1166
  /* 1278 */ 'G', '_', 'S', 'U', 'B', 0,
1167
  /* 1284 */ 'L', 'D', 'S', '_', 'S', 'U', 'B', 0,
1168
  /* 1292 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
1169
  /* 1308 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
1170
  /* 1320 */ 'E', 'N', 'D', 'F', 'U', 'N', 'C', 0,
1171
  /* 1328 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
1172
  /* 1338 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
1173
  /* 1356 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
1174
  /* 1364 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', 0,
1175
  /* 1377 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
1176
  /* 1388 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
1177
  /* 1399 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'V', 'E', 'C', '_', 'L', 'O', 'A', 'D', 0,
1178
  /* 1415 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
1179
  /* 1422 */ 'P', 'A', 'D', 0,
1180
  /* 1426 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
1181
  /* 1433 */ 'G', '_', 'A', 'D', 'D', 0,
1182
  /* 1439 */ 'L', 'D', 'S', '_', 'A', 'D', 'D', 0,
1183
  /* 1447 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
1184
  /* 1463 */ 'T', 'E', 'X', '_', 'L', 'D', 0,
1185
  /* 1470 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
1186
  /* 1487 */ 'G', '_', 'A', 'N', 'D', 0,
1187
  /* 1493 */ 'L', 'D', 'S', '_', 'A', 'N', 'D', 0,
1188
  /* 1501 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
1189
  /* 1517 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
1190
  /* 1530 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
1191
  /* 1539 */ 'J', 'U', 'M', 'P', '_', 'C', 'O', 'N', 'D', 0,
1192
  /* 1549 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
1193
  /* 1567 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
1194
  /* 1584 */ 'T', 'X', 'D', 0,
1195
  /* 1588 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
1196
  /* 1596 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
1197
  /* 1604 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
1198
  /* 1617 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
1199
  /* 1625 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
1200
  /* 1633 */ 'M', 'U', 'L', '_', 'I', 'E', 'E', 'E', 0,
1201
  /* 1642 */ 'S', 'G', 'E', 0,
1202
  /* 1646 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'E', 0,
1203
  /* 1657 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
1204
  /* 1664 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', 0,
1205
  /* 1675 */ 'R', 'N', 'D', 'N', 'E', 0,
1206
  /* 1681 */ 'S', 'N', 'E', 0,
1207
  /* 1685 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'N', 'E', 0,
1208
  /* 1696 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
1209
  /* 1709 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'P', 'U', 'S', 'H', '_', 'B', 'E', 'F', 'O', 'R', 'E', 0,
1210
  /* 1728 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
1211
  /* 1736 */ 'E', 'L', 'S', 'E', 0,
1212
  /* 1741 */ 'F', 'E', 'T', 'C', 'H', '_', 'C', 'L', 'A', 'U', 'S', 'E', 0,
1213
  /* 1754 */ 'A', 'L', 'U', '_', 'C', 'L', 'A', 'U', 'S', 'E', 0,
1214
  /* 1765 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'E', 0,
1215
  /* 1775 */ 'L', 'D', 'S', '_', 'B', 'Y', 'T', 'E', '_', 'W', 'R', 'I', 'T', 'E', 0,
1216
  /* 1790 */ 'M', 'A', 'S', 'K', '_', 'W', 'R', 'I', 'T', 'E', 0,
1217
  /* 1801 */ 'L', 'D', 'S', '_', 'W', 'R', 'I', 'T', 'E', 0,
1218
  /* 1811 */ 'L', 'D', 'S', '_', 'S', 'H', 'O', 'R', 'T', '_', 'W', 'R', 'I', 'T', 'E', 0,
1219
  /* 1827 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
1220
  /* 1837 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
1221
  /* 1852 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', 0,
1222
  /* 1868 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
1223
  /* 1886 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
1224
  /* 1904 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
1225
  /* 1919 */ 'E', 'N', 'D', 'I', 'F', 0,
1226
  /* 1925 */ 'T', 'E', 'X', '_', 'V', 'T', 'X', '_', 'C', 'O', 'N', 'S', 'T', 'B', 'U', 'F', 0,
1227
  /* 1942 */ 'T', 'E', 'X', '_', 'V', 'T', 'X', '_', 'T', 'E', 'X', 'B', 'U', 'F', 0,
1228
  /* 1957 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
1229
  /* 1964 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
1230
  /* 1979 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
1231
  /* 1993 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
1232
  /* 2007 */ 'C', 'F', '_', 'T', 'C', '_', 'E', 'G', 0,
1233
  /* 2016 */ 'C', 'F', '_', 'V', 'C', '_', 'E', 'G', 0,
1234
  /* 2025 */ 'C', 'F', '_', 'E', 'N', 'D', '_', 'E', 'G', 0,
1235
  /* 2035 */ 'C', 'F', '_', 'E', 'L', 'S', 'E', '_', 'E', 'G', 0,
1236
  /* 2046 */ 'C', 'F', '_', 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'E', 'G', 0,
1237
  /* 2061 */ 'C', 'F', '_', 'P', 'U', 'S', 'H', '_', 'E', 'G', 0,
1238
  /* 2072 */ 'L', 'O', 'O', 'P', '_', 'B', 'R', 'E', 'A', 'K', '_', 'E', 'G', 0,
1239
  /* 2086 */ 'C', 'F', '_', 'J', 'U', 'M', 'P', '_', 'E', 'G', 0,
1240
  /* 2097 */ 'E', 'N', 'D', '_', 'L', 'O', 'O', 'P', '_', 'E', 'G', 0,
1241
  /* 2109 */ 'W', 'H', 'I', 'L', 'E', '_', 'L', 'O', 'O', 'P', '_', 'E', 'G', 0,
1242
  /* 2123 */ 'P', 'O', 'P', '_', 'E', 'G', 0,
1243
  /* 2130 */ 'C', 'F', '_', 'C', 'A', 'L', 'L', '_', 'F', 'S', '_', 'E', 'G', 0,
1244
  /* 2144 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
1245
  /* 2161 */ 'L', 'D', 'S', '_', 'W', 'R', 'X', 'C', 'H', 'G', 0,
1246
  /* 2172 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
1247
  /* 2189 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
1248
  /* 2196 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
1249
  /* 2204 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', '_', 'G', 0,
1250
  /* 2219 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'G', 0,
1251
  /* 2232 */ 'B', 'R', 'A', 'N', 'C', 'H', 0,
1252
  /* 2239 */ 'E', 'N', 'D', 'S', 'W', 'I', 'T', 'C', 'H', 0,
1253
  /* 2249 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
1254
  /* 2257 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
1255
  /* 2265 */ 'T', 'E', 'X', '_', 'G', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'H', 0,
1256
  /* 2285 */ 'T', 'E', 'X', '_', 'S', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'H', 0,
1257
  /* 2305 */ 'G', '_', 'P', 'H', 'I', 0,
1258
  /* 2311 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
1259
  /* 2320 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
1260
  /* 2329 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'B', 'R', 'E', 'A', 'K', 0,
1261
  /* 2342 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
1262
  /* 2353 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
1263
  /* 2362 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
1264
  /* 2372 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
1265
  /* 2381 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
1266
  /* 2398 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
1267
  /* 2418 */ 'G', '_', 'S', 'H', 'L', 0,
1268
  /* 2424 */ 'C', 'E', 'I', 'L', 0,
1269
  /* 2429 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
1270
  /* 2449 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
1271
  /* 2476 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
1272
  /* 2497 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
1273
  /* 2509 */ 'K', 'I', 'L', 'L', 0,
1274
  /* 2514 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
1275
  /* 2521 */ 'G', '_', 'M', 'U', 'L', 0,
1276
  /* 2527 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', '_', 'L', 0,
1277
  /* 2542 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'L', 0,
1278
  /* 2555 */ 'C', 'F', '_', 'E', 'N', 'D', '_', 'C', 'M', 0,
1279
  /* 2565 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
1280
  /* 2572 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
1281
  /* 2579 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
1282
  /* 2586 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
1283
  /* 2596 */ 'D', 'U', 'M', 'M', 'Y', '_', 'C', 'H', 'A', 'I', 'N', 0,
1284
  /* 2608 */ 'E', 'N', 'D', 'M', 'A', 'I', 'N', 0,
1285
  /* 2616 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
1286
  /* 2633 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
1287
  /* 2649 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
1288
  /* 2665 */ 'R', 'E', 'T', 'U', 'R', 'N', 0,
1289
  /* 2672 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'S', 'U', 'B', '_', 'R', 'T', 'N', 0,
1290
  /* 2692 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'U', 'B', '_', 'R', 'T', 'N', 0,
1291
  /* 2711 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'D', 'D', '_', 'R', 'T', 'N', 0,
1292
  /* 2730 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'N', 'D', '_', 'R', 'T', 'N', 0,
1293
  /* 2749 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'O', 'R', '_', 'R', 'T', 'N', 0,
1294
  /* 2768 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'O', 'R', '_', 'R', 'T', 'N', 0,
1295
  /* 2786 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'D', 'E', 'C', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1296
  /* 2810 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'I', 'N', 'C', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1297
  /* 2834 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1298
  /* 2858 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1299
  /* 2882 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1300
  /* 2909 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1301
  /* 2933 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1302
  /* 2956 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1303
  /* 2979 */ 'R', 'E', 'T', 'D', 'Y', 'N', 0,
1304
  /* 2986 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
1305
  /* 2994 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
1306
  /* 3002 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
1307
  /* 3010 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
1308
  /* 3018 */ 'T', 'E', 'X', '_', 'G', 'E', 'T', '_', 'T', 'E', 'X', 'T', 'U', 'R', 'E', '_', 'R', 'E', 'S', 'I', 'N', 'F', 'O', 0,
1309
  /* 3042 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
1310
  /* 3050 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
1311
  /* 3058 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
1312
  /* 3067 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
1313
  /* 3075 */ 'G', '_', 'G', 'E', 'P', 0,
1314
  /* 3081 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
1315
  /* 3090 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
1316
  /* 3099 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
1317
  /* 3106 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
1318
  /* 3113 */ 'J', 'U', 'M', 'P', 0,
1319
  /* 3118 */ 'E', 'N', 'D', 'L', 'O', 'O', 'P', 0,
1320
  /* 3126 */ 'W', 'H', 'I', 'L', 'E', 'L', 'O', 'O', 'P', 0,
1321
  /* 3136 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
1322
  /* 3144 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
1323
  /* 3157 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
1324
  /* 3169 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
1325
  /* 3176 */ 'G', '_', 'B', 'R', 0,
1326
  /* 3181 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
1327
  /* 3194 */ 'M', 'O', 'V', '_', 'I', 'M', 'M', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'A', 'D', 'D', 'R', 0,
1328
  /* 3214 */ 'G', 'R', 'O', 'U', 'P', '_', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0,
1329
  /* 3228 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'E', 'L', 'S', 'E', '_', 'A', 'F', 'T', 'E', 'R', 0,
1330
  /* 3246 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'P', 'O', 'P', '_', 'A', 'F', 'T', 'E', 'R', 0,
1331
  /* 3263 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
1332
  /* 3288 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
1333
  /* 3295 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
1334
  /* 3302 */ 'R', 'A', 'T', '_', 'M', 'S', 'K', 'O', 'R', 0,
1335
  /* 3312 */ 'F', 'L', 'O', 'O', 'R', 0,
1336
  /* 3318 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
1337
  /* 3335 */ 'G', '_', 'X', 'O', 'R', 0,
1338
  /* 3341 */ 'L', 'D', 'S', '_', 'X', 'O', 'R', 0,
1339
  /* 3349 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
1340
  /* 3365 */ 'G', '_', 'O', 'R', 0,
1341
  /* 3370 */ 'L', 'D', 'S', '_', 'O', 'R', 0,
1342
  /* 3377 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
1343
  /* 3392 */ 'T', 'E', 'X', '_', 'L', 'D', 'P', 'T', 'R', 0,
1344
  /* 3402 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
1345
  /* 3413 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
1346
  /* 3420 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1347
  /* 3437 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1348
  /* 3452 */ 'L', 'I', 'T', 'E', 'R', 'A', 'L', 'S', 0,
1349
  /* 3461 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
1350
  /* 3478 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
1351
  /* 3508 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
1352
  /* 3535 */ 'F', 'R', 'A', 'C', 'T', 0,
1353
  /* 3541 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
1354
  /* 3551 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
1355
  /* 3560 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
1356
  /* 3573 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'S', 'U', 'B', '_', 'N', 'O', 'R', 'E', 'T', 0,
1357
  /* 3595 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'U', 'B', '_', 'N', 'O', 'R', 'E', 'T', 0,
1358
  /* 3616 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'D', 'D', '_', 'N', 'O', 'R', 'E', 'T', 0,
1359
  /* 3637 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'N', 'D', '_', 'N', 'O', 'R', 'E', 'T', 0,
1360
  /* 3658 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'O', 'R', '_', 'N', 'O', 'R', 'E', 'T', 0,
1361
  /* 3679 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'O', 'R', '_', 'N', 'O', 'R', 'E', 'T', 0,
1362
  /* 3699 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'D', 'E', 'C', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1363
  /* 3725 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'I', 'N', 'C', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1364
  /* 3751 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1365
  /* 3777 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1366
  /* 3803 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1367
  /* 3832 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1368
  /* 3858 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1369
  /* 3883 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1370
  /* 3908 */ 'L', 'D', 'S', '_', 'S', 'U', 'B', '_', 'R', 'E', 'T', 0,
1371
  /* 3920 */ 'L', 'D', 'S', '_', 'U', 'B', 'Y', 'T', 'E', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1372
  /* 3939 */ 'L', 'D', 'S', '_', 'B', 'Y', 'T', 'E', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1373
  /* 3957 */ 'L', 'D', 'S', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1374
  /* 3970 */ 'L', 'D', 'S', '_', 'U', 'S', 'H', 'O', 'R', 'T', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1375
  /* 3990 */ 'L', 'D', 'S', '_', 'S', 'H', 'O', 'R', 'T', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1376
  /* 4009 */ 'L', 'D', 'S', '_', 'A', 'D', 'D', '_', 'R', 'E', 'T', 0,
1377
  /* 4021 */ 'L', 'D', 'S', '_', 'A', 'N', 'D', '_', 'R', 'E', 'T', 0,
1378
  /* 4033 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
1379
  /* 4047 */ 'L', 'D', 'S', '_', 'W', 'R', 'X', 'C', 'H', 'G', '_', 'R', 'E', 'T', 0,
1380
  /* 4062 */ 'L', 'D', 'S', '_', 'X', 'O', 'R', '_', 'R', 'E', 'T', 0,
1381
  /* 4074 */ 'L', 'D', 'S', '_', 'O', 'R', '_', 'R', 'E', 'T', 0,
1382
  /* 4085 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1383
  /* 4102 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1384
  /* 4119 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1385
  /* 4135 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1386
  /* 4151 */ 'L', 'D', 'S', '_', 'C', 'M', 'P', 'S', 'T', '_', 'R', 'E', 'T', 0,
1387
  /* 4165 */ 'I', 'F', '_', 'P', 'R', 'E', 'D', 'I', 'C', 'A', 'T', 'E', '_', 'S', 'E', 'T', 0,
1388
  /* 4182 */ 'K', 'I', 'L', 'L', 'G', 'T', 0,
1389
  /* 4189 */ 'S', 'G', 'T', 0,
1390
  /* 4193 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'T', 0,
1391
  /* 4204 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
1392
  /* 4228 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1393
  /* 4249 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1394
  /* 4269 */ 'D', 'E', 'F', 'A', 'U', 'L', 'T', 0,
1395
  /* 4277 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1396
  /* 4289 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1397
  /* 4300 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
1398
  /* 4311 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
1399
  /* 4322 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
1400
  /* 4333 */ 'S', 'U', 'B', 'B', '_', 'U', 'I', 'N', 'T', 0,
1401
  /* 4343 */ 'A', 'D', 'D', 'C', '_', 'U', 'I', 'N', 'T', 0,
1402
  /* 4353 */ 'S', 'E', 'T', 'G', 'E', '_', 'U', 'I', 'N', 'T', 0,
1403
  /* 4364 */ 'F', 'F', 'B', 'H', '_', 'U', 'I', 'N', 'T', 0,
1404
  /* 4374 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', 0,
1405
  /* 4387 */ 'S', 'E', 'T', 'G', 'T', '_', 'U', 'I', 'N', 'T', 0,
1406
  /* 4398 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', 0,
1407
  /* 4411 */ 'S', 'U', 'B', '_', 'I', 'N', 'T', 0,
1408
  /* 4419 */ 'A', 'D', 'D', '_', 'I', 'N', 'T', 0,
1409
  /* 4427 */ 'A', 'N', 'D', '_', 'I', 'N', 'T', 0,
1410
  /* 4435 */ 'C', 'N', 'D', 'E', '_', 'I', 'N', 'T', 0,
1411
  /* 4444 */ 'C', 'N', 'D', 'G', 'E', '_', 'I', 'N', 'T', 0,
1412
  /* 4454 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'E', '_', 'I', 'N', 'T', 0,
1413
  /* 4469 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'N', 'E', '_', 'I', 'N', 'T', 0,
1414
  /* 4484 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'E', '_', 'I', 'N', 'T', 0,
1415
  /* 4498 */ 'F', 'F', 'B', 'L', '_', 'I', 'N', 'T', 0,
1416
  /* 4507 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', 0,
1417
  /* 4519 */ 'X', 'O', 'R', '_', 'I', 'N', 'T', 0,
1418
  /* 4527 */ 'C', 'N', 'D', 'G', 'T', '_', 'I', 'N', 'T', 0,
1419
  /* 4537 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'T', '_', 'I', 'N', 'T', 0,
1420
  /* 4552 */ 'B', 'C', 'N', 'T', '_', 'I', 'N', 'T', 0,
1421
  /* 4561 */ 'N', 'O', 'T', '_', 'I', 'N', 'T', 0,
1422
  /* 4569 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', 0,
1423
  /* 4581 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
1424
  /* 4591 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
1425
  /* 4606 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
1426
  /* 4615 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
1427
  /* 4625 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
1428
  /* 4642 */ 'L', 'D', 'S', '_', 'C', 'M', 'P', 'S', 'T', 0,
1429
  /* 4652 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
1430
  /* 4660 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
1431
  /* 4667 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
1432
  /* 4676 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
1433
  /* 4683 */ 'C', 'F', '_', 'A', 'L', 'U', 0,
1434
  /* 4690 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
1435
  /* 4697 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
1436
  /* 4704 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
1437
  /* 4711 */ 'M', 'O', 'V', 0,
1438
  /* 4715 */ 'T', 'E', 'X', '_', 'G', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'V', 0,
1439
  /* 4735 */ 'T', 'E', 'X', '_', 'S', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'V', 0,
1440
  /* 4755 */ 'T', 'X', 'D', '_', 'S', 'H', 'A', 'D', 'O', 'W', 0,
1441
  /* 4766 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
1442
  /* 4773 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'Z', 'W', 0,
1443
  /* 4783 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'P', 'A', 'I', 'R', '_', 'Z', 'W', 0,
1444
  /* 4798 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
1445
  /* 4815 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
1446
  /* 4831 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
1447
  /* 4845 */ 'P', 'R', 'E', 'D', '_', 'X', 0,
1448
  /* 4852 */ 'C', 'O', 'N', 'S', 'T', '_', 'C', 'O', 'P', 'Y', 0,
1449
  /* 4863 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'X', 'Y', 0,
1450
  /* 4873 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'P', 'A', 'I', 'R', '_', 'X', 'Y', 0,
1451
  /* 4888 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
1452
  /* 4895 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
1453
  /* 4902 */ 'R', '6', '0', '0', '_', 'R', 'e', 'g', 'i', 's', 't', 'e', 'r', 'L', 'o', 'a', 'd', 0,
1454
  /* 4920 */ 'R', '6', '0', '0', '_', 'R', 'e', 'g', 'i', 's', 't', 'e', 'r', 'S', 't', 'o', 'r', 'e', 0,
1455
  /* 4939 */ 'R', '6', '0', '0', '_', 'E', 'x', 'p', 'o', 'r', 't', 'B', 'u', 'f', 0,
1456
  /* 4954 */ 'E', 'G', '_', 'E', 'x', 'p', 'o', 'r', 't', 'B', 'u', 'f', 0,
1457
  /* 4967 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '3', '2', '_', 'e', 'g', 0,
1458
  /* 4982 */ 'R', 'A', 'T', '_', 'W', 'R', 'I', 'T', 'E', '_', 'C', 'A', 'C', 'H', 'E', 'L', 'E', 'S', 'S', '_', '3', '2', '_', 'e', 'g', 0,
1459
  /* 5008 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'U', 'I', 'N', 'T', '2', '4', '_', 'e', 'g', 0,
1460
  /* 5025 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '2', '4', '_', 'e', 'g', 0,
1461
  /* 5041 */ 'M', 'U', 'L', '_', 'U', 'I', 'N', 'T', '2', '4', '_', 'e', 'g', 0,
1462
  /* 5055 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '6', '4', '_', 'e', 'g', 0,
1463
  /* 5070 */ 'R', 'A', 'T', '_', 'W', 'R', 'I', 'T', 'E', '_', 'C', 'A', 'C', 'H', 'E', 'L', 'E', 'S', 'S', '_', '6', '4', '_', 'e', 'g', 0,
1464
  /* 5096 */ 'D', 'O', 'T', '4', '_', 'e', 'g', 0,
1465
  /* 5104 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '6', '_', 'e', 'g', 0,
1466
  /* 5119 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '2', '8', '_', 'e', 'g', 0,
1467
  /* 5135 */ 'R', 'A', 'T', '_', 'W', 'R', 'I', 'T', 'E', '_', 'C', 'A', 'C', 'H', 'E', 'L', 'E', 'S', 'S', '_', '1', '2', '8', '_', 'e', 'g', 0,
1468
  /* 5162 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '8', '_', 'e', 'g', 0,
1469
  /* 5176 */ 'F', 'M', 'A', '_', 'e', 'g', 0,
1470
  /* 5183 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'e', 'g', 0,
1471
  /* 5193 */ 'L', 'O', 'G', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'e', 'g', 0,
1472
  /* 5208 */ 'R', 'E', 'C', 'I', 'P', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'e', 'g', 0,
1473
  /* 5225 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'e', 'g', 0,
1474
  /* 5246 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'e', 'g', 0,
1475
  /* 5265 */ 'C', 'N', 'D', 'E', '_', 'e', 'g', 0,
1476
  /* 5273 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1477
  /* 5288 */ 'L', 'O', 'G', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1478
  /* 5300 */ 'R', 'E', 'C', 'I', 'P', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1479
  /* 5314 */ 'E', 'X', 'P', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1480
  /* 5326 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1481
  /* 5344 */ 'C', 'N', 'D', 'G', 'E', '_', 'e', 'g', 0,
1482
  /* 5353 */ 'L', 'S', 'H', 'L', '_', 'e', 'g', 0,
1483
  /* 5361 */ 'S', 'I', 'N', '_', 'e', 'g', 0,
1484
  /* 5368 */ 'A', 'S', 'H', 'R', '_', 'e', 'g', 0,
1485
  /* 5376 */ 'L', 'S', 'H', 'R', '_', 'e', 'g', 0,
1486
  /* 5384 */ 'C', 'O', 'S', '_', 'e', 'g', 0,
1487
  /* 5391 */ 'C', 'N', 'D', 'G', 'T', '_', 'e', 'g', 0,
1488
  /* 5400 */ 'M', 'U', 'L', '_', 'L', 'I', 'T', '_', 'e', 'g', 0,
1489
  /* 5411 */ 'U', 'I', 'N', 'T', '_', 'T', 'O', '_', 'F', 'L', 'T', '_', 'e', 'g', 0,
1490
  /* 5426 */ 'B', 'F', 'E', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1491
  /* 5438 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1492
  /* 5452 */ 'M', 'U', 'L', 'L', 'O', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1493
  /* 5466 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1494
  /* 5481 */ 'R', 'E', 'C', 'I', 'P', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1495
  /* 5495 */ 'M', 'O', 'V', 'A', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1496
  /* 5507 */ 'B', 'F', 'E', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1497
  /* 5518 */ 'B', 'F', 'I', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1498
  /* 5529 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1499
  /* 5542 */ 'B', 'F', 'M', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1500
  /* 5553 */ 'B', 'I', 'T', '_', 'A', 'L', 'I', 'G', 'N', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1501
  /* 5570 */ 'M', 'U', 'L', 'L', 'O', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1502
  /* 5583 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1503
  /* 5597 */ 'C', 'U', 'B', 'E', '_', 'r', '6', '0', '0', '_', 'r', 'e', 'a', 'l', 0,
1504
  /* 5612 */ 'C', 'U', 'B', 'E', '_', 'e', 'g', '_', 'r', 'e', 'a', 'l', 0,
1505
  /* 5625 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '3', '2', '_', 'c', 'm', 0,
1506
  /* 5640 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'I', 'N', 'T', '2', '4', '_', 'c', 'm', 0,
1507
  /* 5656 */ 'M', 'U', 'L', '_', 'I', 'N', 'T', '2', '4', '_', 'c', 'm', 0,
1508
  /* 5669 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '6', '4', '_', 'c', 'm', 0,
1509
  /* 5684 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '6', '_', 'c', 'm', 0,
1510
  /* 5699 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '2', '8', '_', 'c', 'm', 0,
1511
  /* 5715 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '8', '_', 'c', 'm', 0,
1512
  /* 5729 */ 'R', 'E', 'C', 'I', 'P', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'c', 'm', 0,
1513
  /* 5746 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'c', 'm', 0,
1514
  /* 5767 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'c', 'm', 0,
1515
  /* 5786 */ 'L', 'O', 'G', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1516
  /* 5798 */ 'R', 'E', 'C', 'I', 'P', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1517
  /* 5812 */ 'E', 'X', 'P', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1518
  /* 5824 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1519
  /* 5842 */ 'S', 'I', 'N', '_', 'c', 'm', 0,
1520
  /* 5849 */ 'C', 'O', 'S', '_', 'c', 'm', 0,
1521
  /* 5856 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'c', 'm', 0,
1522
  /* 5870 */ 'M', 'U', 'L', 'L', 'O', '_', 'U', 'I', 'N', 'T', '_', 'c', 'm', 0,
1523
  /* 5884 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'c', 'm', 0,
1524
  /* 5897 */ 'M', 'U', 'L', 'L', 'O', '_', 'I', 'N', 'T', '_', 'c', 'm', 0,
1525
  /* 5910 */ 'C', 'U', 'B', 'E', '_', 'r', '6', '0', '0', '_', 'p', 's', 'e', 'u', 'd', 'o', 0,
1526
  /* 5927 */ 'C', 'U', 'B', 'E', '_', 'e', 'g', '_', 'p', 's', 'e', 'u', 'd', 'o', 0,
1527
  /* 5942 */ 'R', '6', '0', '0', '_', 'E', 'x', 'p', 'o', 'r', 't', 'S', 'w', 'z', 0,
1528
  /* 5957 */ 'E', 'G', '_', 'E', 'x', 'p', 'o', 'r', 't', 'S', 'w', 'z', 0,
1529
};
1530
1531
extern const unsigned R600InstrNameIndices[] = {
1532
    2307U, 2586U, 2649U, 2372U, 2353U, 2381U, 2509U, 1964U, 
1533
    1979U, 1906U, 1993U, 3461U, 1827U, 2362U, 1604U, 4858U, 
1534
    1657U, 4591U, 1517U, 3058U, 2497U, 4311U, 1567U, 4300U, 
1535
    1696U, 3157U, 3144U, 3263U, 4033U, 4204U, 2429U, 2476U, 
1536
    2449U, 2398U, 1433U, 1278U, 2521U, 4697U, 4704U, 2572U, 
1537
    2579U, 1487U, 3365U, 3335U, 1904U, 2305U, 4831U, 1837U, 
1538
    3541U, 3420U, 4606U, 3437U, 4322U, 3402U, 4615U, 1338U, 
1539
    1549U, 1415U, 1377U, 1388U, 1728U, 3478U, 2144U, 2172U, 
1540
    1447U, 1292U, 1501U, 1470U, 3377U, 3349U, 4815U, 2633U, 
1541
    4798U, 2616U, 1530U, 3560U, 1308U, 3508U, 4667U, 1356U, 
1542
    4289U, 4277U, 4581U, 2196U, 4660U, 4676U, 2418U, 3295U, 
1543
    3288U, 3106U, 3099U, 3551U, 3010U, 1625U, 2994U, 1596U, 
1544
    3002U, 1617U, 2986U, 1588U, 3050U, 3042U, 2257U, 2249U, 
1545
    1426U, 1271U, 2514U, 1235U, 4690U, 2565U, 4766U, 3169U, 
1546
    1060U, 2189U, 1052U, 1957U, 4652U, 1328U, 2311U, 2320U, 
1547
    3081U, 3090U, 3413U, 3075U, 2342U, 3176U, 4249U, 4228U, 
1548
    3318U, 4895U, 1886U, 4888U, 1868U, 3136U, 3067U, 4625U, 
1549
    3181U, 2232U, 753U, 919U, 2336U, 742U, 908U, 866U, 
1550
    1032U, 807U, 973U, 4852U, 1859U, 720U, 886U, 826U, 
1551
    992U, 769U, 935U, 5927U, 5910U, 4269U, 1195U, 2596U, 
1552
    1736U, 1526U, 1320U, 1919U, 3118U, 2608U, 2239U, 160U, 
1553
    82U, 1323U, 734U, 900U, 849U, 1015U, 791U, 957U, 
1554
    4165U, 3113U, 1539U, 1790U, 681U, 3194U, 693U, 4845U, 
1555
    1068U, 1156U, 1088U, 1176U, 4902U, 4920U, 2979U, 2665U, 
1556
    1584U, 4755U, 3126U, 1429U, 4343U, 4419U, 1754U, 4427U, 
1557
    5368U, 388U, 4552U, 5507U, 5426U, 5518U, 5542U, 5553U, 
1558
    2424U, 4683U, 2329U, 1852U, 3228U, 3246U, 1709U, 2130U, 
1559
    170U, 2046U, 65U, 2035U, 34U, 2555U, 2025U, 22U, 
1560
    2086U, 108U, 2061U, 47U, 2007U, 0U, 2016U, 11U, 
1561
    4435U, 5265U, 267U, 4444U, 5344U, 358U, 4527U, 5391U, 
1562
    417U, 5849U, 5384U, 408U, 578U, 5612U, 5597U, 5096U, 
1563
    186U, 4954U, 5957U, 2097U, 121U, 5812U, 5314U, 324U, 
1564
    1741U, 4364U, 4498U, 3312U, 705U, 1201U, 5583U, 553U, 
1565
    5466U, 490U, 5176U, 3535U, 3214U, 648U, 4873U, 4783U, 
1566
    1399U, 4863U, 4773U, 5412U, 442U, 4182U, 1439U, 4009U, 
1567
    1493U, 4021U, 3939U, 1775U, 4642U, 4151U, 4569U, 4135U, 
1568
    4398U, 4102U, 4507U, 4119U, 4374U, 4085U, 3370U, 4074U, 
1569
    3957U, 3990U, 1811U, 1284U, 3908U, 3920U, 3970U, 1801U, 
1570
    2161U, 4047U, 3341U, 4062U, 3452U, 5193U, 208U, 5786U, 
1571
    5288U, 294U, 2072U, 92U, 5353U, 369U, 5376U, 398U, 
1572
    4811U, 639U, 4573U, 4402U, 2629U, 619U, 4511U, 4378U, 
1573
    4711U, 5495U, 2517U, 5273U, 277U, 5640U, 5008U, 5183U, 
1574
    196U, 5884U, 1123U, 5529U, 523U, 5025U, 5856U, 1107U, 
1575
    5438U, 458U, 5897U, 5570U, 538U, 5870U, 5452U, 474U, 
1576
    1633U, 5656U, 5400U, 428U, 5041U, 4561U, 4520U, 1422U, 
1577
    2123U, 151U, 1765U, 4484U, 1646U, 4454U, 4193U, 4537U, 
1578
    1685U, 4469U, 4939U, 5942U, 3616U, 2711U, 3637U, 2730U, 
1579
    3803U, 2882U, 3699U, 2786U, 3725U, 2810U, 3883U, 2956U, 
1580
    3777U, 2858U, 3858U, 2933U, 3751U, 2834U, 3679U, 2768U, 
1581
    3573U, 2672U, 3595U, 2692U, 3832U, 2909U, 3658U, 2749U, 
1582
    3302U, 1216U, 663U, 1138U, 5767U, 5246U, 5135U, 4982U, 
1583
    5070U, 5746U, 5225U, 244U, 5824U, 5326U, 338U, 5729U, 
1584
    5208U, 225U, 5798U, 5300U, 308U, 5481U, 507U, 1675U, 
1585
    1770U, 609U, 4489U, 587U, 4459U, 4353U, 628U, 4542U, 
1586
    4387U, 598U, 4474U, 1642U, 4189U, 5842U, 5361U, 379U, 
1587
    569U, 1681U, 4333U, 4411U, 2265U, 4715U, 3018U, 1463U, 
1588
    3392U, 1664U, 1364U, 2204U, 2527U, 1241U, 2219U, 2542U, 
1589
    1257U, 2285U, 4735U, 1925U, 1942U, 1332U, 5411U, 441U, 
1590
    5699U, 5119U, 5684U, 5104U, 5625U, 4967U, 5669U, 5055U, 
1591
    5715U, 5162U, 2109U, 135U, 4519U, 
1592
};
1593
1594
296
static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
1595
296
  II->InitMCInstrInfo(R600Insts, R600InstrNameIndices, R600InstrNameData, 477);
1596
296
}
1597
1598
} // end llvm namespace
1599
#endif // GET_INSTRINFO_MC_DESC
1600
1601
#ifdef GET_INSTRINFO_HEADER
1602
#undef GET_INSTRINFO_HEADER
1603
namespace llvm {
1604
struct R600GenInstrInfo : public TargetInstrInfo {
1605
  explicit R600GenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
1606
289
  ~R600GenInstrInfo() override = default;
1607
1608
};
1609
} // end llvm namespace
1610
#endif // GET_INSTRINFO_HEADER
1611
1612
#ifdef GET_TII_HELPER_DECLS
1613
#undef GET_TII_HELPER_DECLS
1614
#endif // GET_TII_HELPER_DECLS
1615
1616
#ifdef GET_TII_HELPERS
1617
#undef GET_TII_HELPERS
1618
#endif // GET_TTI_HELPERS
1619
1620
#ifdef GET_INSTRINFO_CTOR_DTOR
1621
#undef GET_INSTRINFO_CTOR_DTOR
1622
namespace llvm {
1623
extern const MCInstrDesc R600Insts[];
1624
extern const unsigned R600InstrNameIndices[];
1625
extern const char R600InstrNameData[];
1626
R600GenInstrInfo::R600GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
1627
290
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1628
290
  InitMCInstrInfo(R600Insts, R600InstrNameIndices, R600InstrNameData, 477);
1629
290
}
1630
} // end llvm namespace
1631
#endif // GET_INSTRINFO_CTOR_DTOR
1632
1633
#ifdef GET_INSTRINFO_OPERAND_ENUM
1634
#undef GET_INSTRINFO_OPERAND_ENUM
1635
namespace llvm {
1636
namespace R600 {
1637
namespace OpName {
1638
enum {
1639
  ADDR = 98,
1640
  COUNT = 105,
1641
  Enabled = 106,
1642
  KCACHE_ADDR0 = 103,
1643
  KCACHE_ADDR1 = 104,
1644
  KCACHE_BANK0 = 99,
1645
  KCACHE_BANK1 = 100,
1646
  KCACHE_MODE0 = 101,
1647
  KCACHE_MODE1 = 102,
1648
  addr = 72,
1649
  bank_swizzle = 93,
1650
  chan = 73,
1651
  clamp = 80,
1652
  clamp_W = 58,
1653
  clamp_X = 7,
1654
  clamp_Y = 24,
1655
  clamp_Z = 41,
1656
  dst = 0,
1657
  dst_rel = 79,
1658
  dst_rel_W = 57,
1659
  dst_rel_X = 6,
1660
  dst_rel_Y = 23,
1661
  dst_rel_Z = 40,
1662
  last = 90,
1663
  literal = 92,
1664
  literal0 = 70,
1665
  literal1 = 71,
1666
  omod = 78,
1667
  omod_W = 56,
1668
  omod_X = 5,
1669
  omod_Y = 22,
1670
  omod_Z = 39,
1671
  pred_sel = 91,
1672
  pred_sel_W = 69,
1673
  pred_sel_X = 18,
1674
  pred_sel_Y = 35,
1675
  pred_sel_Z = 52,
1676
  src0 = 1,
1677
  src0_W = 59,
1678
  src0_X = 8,
1679
  src0_Y = 25,
1680
  src0_Z = 42,
1681
  src0_abs = 83,
1682
  src0_abs_W = 62,
1683
  src0_abs_X = 11,
1684
  src0_abs_Y = 28,
1685
  src0_abs_Z = 45,
1686
  src0_neg = 81,
1687
  src0_neg_W = 60,
1688
  src0_neg_X = 9,
1689
  src0_neg_Y = 26,
1690
  src0_neg_Z = 43,
1691
  src0_rel = 82,
1692
  src0_rel_W = 61,
1693
  src0_rel_X = 10,
1694
  src0_rel_Y = 27,
1695
  src0_rel_Z = 44,
1696
  src0_sel = 84,
1697
  src0_sel_W = 63,
1698
  src0_sel_X = 12,
1699
  src0_sel_Y = 29,
1700
  src0_sel_Z = 46,
1701
  src1 = 85,
1702
  src1_W = 64,
1703
  src1_X = 13,
1704
  src1_Y = 30,
1705
  src1_Z = 47,
1706
  src1_abs = 88,
1707
  src1_abs_W = 67,
1708
  src1_abs_X = 16,
1709
  src1_abs_Y = 33,
1710
  src1_abs_Z = 50,
1711
  src1_neg = 86,
1712
  src1_neg_W = 65,
1713
  src1_neg_X = 14,
1714
  src1_neg_Y = 31,
1715
  src1_neg_Z = 48,
1716
  src1_rel = 87,
1717
  src1_rel_W = 66,
1718
  src1_rel_X = 15,
1719
  src1_rel_Y = 32,
1720
  src1_rel_Z = 49,
1721
  src1_sel = 89,
1722
  src1_sel_W = 68,
1723
  src1_sel_X = 17,
1724
  src1_sel_Y = 34,
1725
  src1_sel_Z = 51,
1726
  src2 = 94,
1727
  src2_neg = 95,
1728
  src2_rel = 96,
1729
  src2_sel = 97,
1730
  update_exec_mask = 75,
1731
  update_exec_mask_W = 53,
1732
  update_exec_mask_X = 2,
1733
  update_exec_mask_Y = 19,
1734
  update_exec_mask_Z = 36,
1735
  update_pred = 76,
1736
  update_pred_W = 54,
1737
  update_pred_X = 3,
1738
  update_pred_Y = 20,
1739
  update_pred_Z = 37,
1740
  val = 74,
1741
  write = 77,
1742
  write_W = 55,
1743
  write_X = 4,
1744
  write_Y = 21,
1745
  write_Z = 38,
1746
OPERAND_LAST
1747
};
1748
} // end namespace OpName
1749
} // end namespace R600
1750
} // end namespace llvm
1751
#endif //GET_INSTRINFO_OPERAND_ENUM
1752
1753
#ifdef GET_INSTRINFO_NAMED_OPS
1754
#undef GET_INSTRINFO_NAMED_OPS
1755
namespace llvm {
1756
namespace R600 {
1757
LLVM_READONLY
1758
4.23M
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1759
4.23M
  static const int16_t OperandMap [][107] = {
1760
4.23M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1761
4.23M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1762
4.23M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1763
4.23M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1764
4.23M
{0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1765
4.23M
{0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1766
4.23M
{0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1767
4.23M
{0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1768
4.23M
{0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1769
4.23M
{-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1770
4.23M
{-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1771
4.23M
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1772
4.23M
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
1773
4.23M
};
1774
4.23M
  switch(Opcode) {
1775
4.23M
  case R600::CUBE_eg_pseudo:
1776
66
  case R600::CUBE_r600_pseudo:
1777
66
    return OperandMap[0][NamedIdx];
1778
570
  case R600::LDS_ADD_RET:
1779
570
  case R600::LDS_AND_RET:
1780
570
  case R600::LDS_MAX_INT_RET:
1781
570
  case R600::LDS_MAX_UINT_RET:
1782
570
  case R600::LDS_MIN_INT_RET:
1783
570
  case R600::LDS_MIN_UINT_RET:
1784
570
  case R600::LDS_OR_RET:
1785
570
  case R600::LDS_SUB_RET:
1786
570
  case R600::LDS_WRXCHG_RET:
1787
570
  case R600::LDS_XOR_RET:
1788
570
    return OperandMap[1][NamedIdx];
1789
570
  case R600::LDS_CMPST_RET:
1790
0
    return OperandMap[2][NamedIdx];
1791
13.4k
  case R600::LDS_BYTE_READ_RET:
1792
13.4k
  case R600::LDS_READ_RET:
1793
13.4k
  case R600::LDS_SHORT_READ_RET:
1794
13.4k
  case R600::LDS_UBYTE_READ_RET:
1795
13.4k
  case R600::LDS_USHORT_READ_RET:
1796
13.4k
    return OperandMap[3][NamedIdx];
1797
815k
  case R600::BFE_INT_eg:
1798
815k
  case R600::BFE_UINT_eg:
1799
815k
  case R600::BFI_INT_eg:
1800
815k
  case R600::BIT_ALIGN_INT_eg:
1801
815k
  case R600::CNDE_INT:
1802
815k
  case R600::CNDE_eg:
1803
815k
  case R600::CNDE_r600:
1804
815k
  case R600::CNDGE_INT:
1805
815k
  case R600::CNDGE_eg:
1806
815k
  case R600::CNDGE_r600:
1807
815k
  case R600::CNDGT_INT:
1808
815k
  case R600::CNDGT_eg:
1809
815k
  case R600::CNDGT_r600:
1810
815k
  case R600::FMA_eg:
1811
815k
  case R600::MULADD_IEEE_eg:
1812
815k
  case R600::MULADD_IEEE_r600:
1813
815k
  case R600::MULADD_INT24_cm:
1814
815k
  case R600::MULADD_UINT24_eg:
1815
815k
  case R600::MULADD_eg:
1816
815k
  case R600::MULADD_r600:
1817
815k
  case R600::MUL_LIT_eg:
1818
815k
  case R600::MUL_LIT_r600:
1819
815k
    return OperandMap[4][NamedIdx];
1820
815k
  case R600::BCNT_INT:
1821
255k
  case R600::CEIL:
1822
255k
  case R600::COS_cm:
1823
255k
  case R600::COS_eg:
1824
255k
  case R600::COS_r600:
1825
255k
  case R600::COS_r700:
1826
255k
  case R600::EXP_IEEE_cm:
1827
255k
  case R600::EXP_IEEE_eg:
1828
255k
  case R600::EXP_IEEE_r600:
1829
255k
  case R600::FFBH_UINT:
1830
255k
  case R600::FFBL_INT:
1831
255k
  case R600::FLOOR:
1832
255k
  case R600::FLT16_TO_FLT32:
1833
255k
  case R600::FLT32_TO_FLT16:
1834
255k
  case R600::FLT_TO_INT_eg:
1835
255k
  case R600::FLT_TO_INT_r600:
1836
255k
  case R600::FLT_TO_UINT_eg:
1837
255k
  case R600::FLT_TO_UINT_r600:
1838
255k
  case R600::FRACT:
1839
255k
  case R600::INTERP_LOAD_P0:
1840
255k
  case R600::INT_TO_FLT_eg:
1841
255k
  case R600::INT_TO_FLT_r600:
1842
255k
  case R600::LOG_CLAMPED_eg:
1843
255k
  case R600::LOG_CLAMPED_r600:
1844
255k
  case R600::LOG_IEEE_cm:
1845
255k
  case R600::LOG_IEEE_eg:
1846
255k
  case R600::LOG_IEEE_r600:
1847
255k
  case R600::MOV:
1848
255k
  case R600::MOVA_INT_eg:
1849
255k
  case R600::NOT_INT:
1850
255k
  case R600::RECIPSQRT_CLAMPED_cm:
1851
255k
  case R600::RECIPSQRT_CLAMPED_eg:
1852
255k
  case R600::RECIPSQRT_CLAMPED_r600:
1853
255k
  case R600::RECIPSQRT_IEEE_cm:
1854
255k
  case R600::RECIPSQRT_IEEE_eg:
1855
255k
  case R600::RECIPSQRT_IEEE_r600:
1856
255k
  case R600::RECIP_CLAMPED_cm:
1857
255k
  case R600::RECIP_CLAMPED_eg:
1858
255k
  case R600::RECIP_CLAMPED_r600:
1859
255k
  case R600::RECIP_IEEE_cm:
1860
255k
  case R600::RECIP_IEEE_eg:
1861
255k
  case R600::RECIP_IEEE_r600:
1862
255k
  case R600::RECIP_UINT_eg:
1863
255k
  case R600::RECIP_UINT_r600:
1864
255k
  case R600::RNDNE:
1865
255k
  case R600::SIN_cm:
1866
255k
  case R600::SIN_eg:
1867
255k
  case R600::SIN_r600:
1868
255k
  case R600::SIN_r700:
1869
255k
  case R600::TRUNC:
1870
255k
  case R600::UINT_TO_FLT_eg:
1871
255k
  case R600::UINT_TO_FLT_r600:
1872
255k
    return OperandMap[5][NamedIdx];
1873
3.08M
  case R600::ADD:
1874
3.08M
  case R600::ADDC_UINT:
1875
3.08M
  case R600::ADD_INT:
1876
3.08M
  case R600::AND_INT:
1877
3.08M
  case R600::ASHR_eg:
1878
3.08M
  case R600::ASHR_r600:
1879
3.08M
  case R600::BFM_INT_eg:
1880
3.08M
  case R600::CUBE_eg_real:
1881
3.08M
  case R600::CUBE_r600_real:
1882
3.08M
  case R600::DOT4_eg:
1883
3.08M
  case R600::DOT4_r600:
1884
3.08M
  case R600::INTERP_XY:
1885
3.08M
  case R600::INTERP_ZW:
1886
3.08M
  case R600::KILLGT:
1887
3.08M
  case R600::LSHL_eg:
1888
3.08M
  case R600::LSHL_r600:
1889
3.08M
  case R600::LSHR_eg:
1890
3.08M
  case R600::LSHR_r600:
1891
3.08M
  case R600::MAX:
1892
3.08M
  case R600::MAX_DX10:
1893
3.08M
  case R600::MAX_INT:
1894
3.08M
  case R600::MAX_UINT:
1895
3.08M
  case R600::MIN:
1896
3.08M
  case R600::MIN_DX10:
1897
3.08M
  case R600::MIN_INT:
1898
3.08M
  case R600::MIN_UINT:
1899
3.08M
  case R600::MUL:
1900
3.08M
  case R600::MULHI_INT_cm:
1901
3.08M
  case R600::MULHI_INT_cm24:
1902
3.08M
  case R600::MULHI_INT_eg:
1903
3.08M
  case R600::MULHI_INT_r600:
1904
3.08M
  case R600::MULHI_UINT24_eg:
1905
3.08M
  case R600::MULHI_UINT_cm:
1906
3.08M
  case R600::MULHI_UINT_cm24:
1907
3.08M
  case R600::MULHI_UINT_eg:
1908
3.08M
  case R600::MULHI_UINT_r600:
1909
3.08M
  case R600::MULLO_INT_cm:
1910
3.08M
  case R600::MULLO_INT_eg:
1911
3.08M
  case R600::MULLO_INT_r600:
1912
3.08M
  case R600::MULLO_UINT_cm:
1913
3.08M
  case R600::MULLO_UINT_eg:
1914
3.08M
  case R600::MULLO_UINT_r600:
1915
3.08M
  case R600::MUL_IEEE:
1916
3.08M
  case R600::MUL_INT24_cm:
1917
3.08M
  case R600::MUL_UINT24_eg:
1918
3.08M
  case R600::OR_INT:
1919
3.08M
  case R600::PRED_SETE:
1920
3.08M
  case R600::PRED_SETE_INT:
1921
3.08M
  case R600::PRED_SETGE:
1922
3.08M
  case R600::PRED_SETGE_INT:
1923
3.08M
  case R600::PRED_SETGT:
1924
3.08M
  case R600::PRED_SETGT_INT:
1925
3.08M
  case R600::PRED_SETNE:
1926
3.08M
  case R600::PRED_SETNE_INT:
1927
3.08M
  case R600::SETE:
1928
3.08M
  case R600::SETE_DX10:
1929
3.08M
  case R600::SETE_INT:
1930
3.08M
  case R600::SETGE_DX10:
1931
3.08M
  case R600::SETGE_INT:
1932
3.08M
  case R600::SETGE_UINT:
1933
3.08M
  case R600::SETGT_DX10:
1934
3.08M
  case R600::SETGT_INT:
1935
3.08M
  case R600::SETGT_UINT:
1936
3.08M
  case R600::SETNE_DX10:
1937
3.08M
  case R600::SETNE_INT:
1938
3.08M
  case R600::SGE:
1939
3.08M
  case R600::SGT:
1940
3.08M
  case R600::SNE:
1941
3.08M
  case R600::SUBB_UINT:
1942
3.08M
  case R600::SUB_INT:
1943
3.08M
  case R600::XOR_INT:
1944
3.08M
    return OperandMap[6][NamedIdx];
1945
3.08M
  case R600::DOT_4:
1946
17.0k
    return OperandMap[7][NamedIdx];
1947
3.08M
  case R600::R600_RegisterLoad:
1948
2.29k
    return OperandMap[8][NamedIdx];
1949
3.08M
  case R600::LDS_ADD:
1950
36.8k
  case R600::LDS_AND:
1951
36.8k
  case R600::LDS_BYTE_WRITE:
1952
36.8k
  case R600::LDS_MAX_INT:
1953
36.8k
  case R600::LDS_MAX_UINT:
1954
36.8k
  case R600::LDS_MIN_INT:
1955
36.8k
  case R600::LDS_MIN_UINT:
1956
36.8k
  case R600::LDS_OR:
1957
36.8k
  case R600::LDS_SHORT_WRITE:
1958
36.8k
  case R600::LDS_SUB:
1959
36.8k
  case R600::LDS_WRITE:
1960
36.8k
  case R600::LDS_WRXCHG:
1961
36.8k
  case R600::LDS_XOR:
1962
36.8k
    return OperandMap[9][NamedIdx];
1963
36.8k
  case R600::LDS_CMPST:
1964
0
    return OperandMap[10][NamedIdx];
1965
36.8k
  case R600::R600_RegisterStore:
1966
1.90k
    return OperandMap[11][NamedIdx];
1967
36.8k
  case R600::CF_ALU:
1968
7.16k
  case R600::CF_ALU_BREAK:
1969
7.16k
  case R600::CF_ALU_CONTINUE:
1970
7.16k
  case R600::CF_ALU_ELSE_AFTER:
1971
7.16k
  case R600::CF_ALU_POP_AFTER:
1972
7.16k
  case R600::CF_ALU_PUSH_BEFORE:
1973
7.16k
    return OperandMap[12][NamedIdx];
1974
7.16k
    
default: return -16.03k
;
1975
4.23M
  }
1976
4.23M
}
1977
} // end namespace R600
1978
} // end namespace llvm
1979
#endif //GET_INSTRINFO_NAMED_OPS
1980
1981
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1982
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1983
namespace llvm {
1984
namespace R600 {
1985
namespace OpTypes {
1986
enum OperandType {
1987
  ABS = 0,
1988
  BANK_SWIZZLE = 1,
1989
  CLAMP = 2,
1990
  CT = 3,
1991
  FRAMEri = 4,
1992
  InstFlag = 5,
1993
  KCACHE = 6,
1994
  LAST = 7,
1995
  LITERAL = 8,
1996
  MEMrr = 9,
1997
  MEMxi = 10,
1998
  NEG = 11,
1999
  OMOD = 12,
2000
  R600_Pred = 13,
2001
  REL = 14,
2002
  RSel = 15,
2003
  SEL = 16,
2004
  UEM = 17,
2005
  UP = 18,
2006
  WRITE = 19,
2007
  brtarget = 20,
2008
  f32imm = 21,
2009
  f64imm = 22,
2010
  i16imm = 23,
2011
  i1imm = 24,
2012
  i32imm = 25,
2013
  i64imm = 26,
2014
  i8imm = 27,
2015
  ptype0 = 28,
2016
  ptype1 = 29,
2017
  ptype2 = 30,
2018
  ptype3 = 31,
2019
  ptype4 = 32,
2020
  ptype5 = 33,
2021
  s16imm = 34,
2022
  type0 = 35,
2023
  type1 = 36,
2024
  type2 = 37,
2025
  type3 = 38,
2026
  type4 = 39,
2027
  type5 = 40,
2028
  u16imm = 41,
2029
  u32imm = 42,
2030
  u8imm = 43,
2031
  OPERAND_TYPE_LIST_END
2032
};
2033
} // end namespace OpTypes
2034
} // end namespace R600
2035
} // end namespace llvm
2036
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
2037
2038
#ifdef GET_INSTRMAP_INFO
2039
#undef GET_INSTRMAP_INFO
2040
namespace llvm {
2041
2042
namespace R600 {
2043
2044
enum DisableEncoding {
2045
  DisableEncoding_
2046
};
2047
2048
// getLDSNoRetOp
2049
LLVM_READONLY
2050
30
int getLDSNoRetOp(uint16_t Opcode) {
2051
30
static const uint16_t getLDSNoRetOpTable[][2] = {
2052
30
  { R600::LDS_ADD_RET, R600::LDS_ADD },
2053
30
  { R600::LDS_AND_RET, R600::LDS_AND },
2054
30
  { R600::LDS_MAX_INT_RET, R600::LDS_MAX_INT },
2055
30
  { R600::LDS_MAX_UINT_RET, R600::LDS_MAX_UINT },
2056
30
  { R600::LDS_MIN_INT_RET, R600::LDS_MIN_INT },
2057
30
  { R600::LDS_MIN_UINT_RET, R600::LDS_MIN_UINT },
2058
30
  { R600::LDS_OR_RET, R600::LDS_OR },
2059
30
  { R600::LDS_SUB_RET, R600::LDS_SUB },
2060
30
  { R600::LDS_WRXCHG_RET, R600::LDS_WRXCHG },
2061
30
  { R600::LDS_XOR_RET, R600::LDS_XOR },
2062
30
}; // End of getLDSNoRetOpTable
2063
30
2064
30
  unsigned mid;
2065
30
  unsigned start = 0;
2066
30
  unsigned end = 10;
2067
94
  while (start < end) {
2068
94
    mid = start + (end - start)/2;
2069
94
    if (Opcode == getLDSNoRetOpTable[mid][0]) {
2070
30
      break;
2071
30
    }
2072
64
    if (Opcode < getLDSNoRetOpTable[mid][0])
2073
46
      end = mid;
2074
18
    else
2075
18
      start = mid + 1;
2076
64
  }
2077
30
  if (start == end)
2078
0
    return -1; // Instruction doesn't exist in this table.
2079
30
2080
30
  return getLDSNoRetOpTable[mid][1];
2081
30
}
2082
2083
} // End R600 namespace
2084
} // End llvm namespace
2085
#endif // GET_INSTRMAP_INFO
2086