Coverage Report

Created: 2019-02-15 18:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/R600GenInstrInfo.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace R600 {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
18
    CFI_INSTRUCTION = 3,
19
    EH_LABEL  = 4,
20
    GC_LABEL  = 5,
21
    ANNOTATION_LABEL  = 6,
22
    KILL  = 7,
23
    EXTRACT_SUBREG  = 8,
24
    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
26
    SUBREG_TO_REG = 11,
27
    COPY_TO_REGCLASS  = 12,
28
    DBG_VALUE = 13,
29
    DBG_LABEL = 14,
30
    REG_SEQUENCE  = 15,
31
    COPY  = 16,
32
    BUNDLE  = 17,
33
    LIFETIME_START  = 18,
34
    LIFETIME_END  = 19,
35
    STACKMAP  = 20,
36
    FENTRY_CALL = 21,
37
    PATCHPOINT  = 22,
38
    LOAD_STACK_GUARD  = 23,
39
    STATEPOINT  = 24,
40
    LOCAL_ESCAPE  = 25,
41
    FAULTING_OP = 26,
42
    PATCHABLE_OP  = 27,
43
    PATCHABLE_FUNCTION_ENTER  = 28,
44
    PATCHABLE_RET = 29,
45
    PATCHABLE_FUNCTION_EXIT = 30,
46
    PATCHABLE_TAIL_CALL = 31,
47
    PATCHABLE_EVENT_CALL  = 32,
48
    PATCHABLE_TYPED_EVENT_CALL  = 33,
49
    ICALL_BRANCH_FUNNEL = 34,
50
    G_ADD = 35,
51
    G_SUB = 36,
52
    G_MUL = 37,
53
    G_SDIV  = 38,
54
    G_UDIV  = 39,
55
    G_SREM  = 40,
56
    G_UREM  = 41,
57
    G_AND = 42,
58
    G_OR  = 43,
59
    G_XOR = 44,
60
    G_IMPLICIT_DEF  = 45,
61
    G_PHI = 46,
62
    G_FRAME_INDEX = 47,
63
    G_GLOBAL_VALUE  = 48,
64
    G_EXTRACT = 49,
65
    G_UNMERGE_VALUES  = 50,
66
    G_INSERT  = 51,
67
    G_MERGE_VALUES  = 52,
68
    G_BUILD_VECTOR  = 53,
69
    G_BUILD_VECTOR_TRUNC  = 54,
70
    G_CONCAT_VECTORS  = 55,
71
    G_PTRTOINT  = 56,
72
    G_INTTOPTR  = 57,
73
    G_BITCAST = 58,
74
    G_INTRINSIC_TRUNC = 59,
75
    G_INTRINSIC_ROUND = 60,
76
    G_LOAD  = 61,
77
    G_SEXTLOAD  = 62,
78
    G_ZEXTLOAD  = 63,
79
    G_STORE = 64,
80
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65,
81
    G_ATOMIC_CMPXCHG  = 66,
82
    G_ATOMICRMW_XCHG  = 67,
83
    G_ATOMICRMW_ADD = 68,
84
    G_ATOMICRMW_SUB = 69,
85
    G_ATOMICRMW_AND = 70,
86
    G_ATOMICRMW_NAND  = 71,
87
    G_ATOMICRMW_OR  = 72,
88
    G_ATOMICRMW_XOR = 73,
89
    G_ATOMICRMW_MAX = 74,
90
    G_ATOMICRMW_MIN = 75,
91
    G_ATOMICRMW_UMAX  = 76,
92
    G_ATOMICRMW_UMIN  = 77,
93
    G_BRCOND  = 78,
94
    G_BRINDIRECT  = 79,
95
    G_INTRINSIC = 80,
96
    G_INTRINSIC_W_SIDE_EFFECTS  = 81,
97
    G_ANYEXT  = 82,
98
    G_TRUNC = 83,
99
    G_CONSTANT  = 84,
100
    G_FCONSTANT = 85,
101
    G_VASTART = 86,
102
    G_VAARG = 87,
103
    G_SEXT  = 88,
104
    G_ZEXT  = 89,
105
    G_SHL = 90,
106
    G_LSHR  = 91,
107
    G_ASHR  = 92,
108
    G_ICMP  = 93,
109
    G_FCMP  = 94,
110
    G_SELECT  = 95,
111
    G_UADDO = 96,
112
    G_UADDE = 97,
113
    G_USUBO = 98,
114
    G_USUBE = 99,
115
    G_SADDO = 100,
116
    G_SADDE = 101,
117
    G_SSUBO = 102,
118
    G_SSUBE = 103,
119
    G_UMULO = 104,
120
    G_SMULO = 105,
121
    G_UMULH = 106,
122
    G_SMULH = 107,
123
    G_FADD  = 108,
124
    G_FSUB  = 109,
125
    G_FMUL  = 110,
126
    G_FMA = 111,
127
    G_FDIV  = 112,
128
    G_FREM  = 113,
129
    G_FPOW  = 114,
130
    G_FEXP  = 115,
131
    G_FEXP2 = 116,
132
    G_FLOG  = 117,
133
    G_FLOG2 = 118,
134
    G_FLOG10  = 119,
135
    G_FNEG  = 120,
136
    G_FPEXT = 121,
137
    G_FPTRUNC = 122,
138
    G_FPTOSI  = 123,
139
    G_FPTOUI  = 124,
140
    G_SITOFP  = 125,
141
    G_UITOFP  = 126,
142
    G_FABS  = 127,
143
    G_FCANONICALIZE = 128,
144
    G_GEP = 129,
145
    G_PTR_MASK  = 130,
146
    G_BR  = 131,
147
    G_INSERT_VECTOR_ELT = 132,
148
    G_EXTRACT_VECTOR_ELT  = 133,
149
    G_SHUFFLE_VECTOR  = 134,
150
    G_CTTZ  = 135,
151
    G_CTTZ_ZERO_UNDEF = 136,
152
    G_CTLZ  = 137,
153
    G_CTLZ_ZERO_UNDEF = 138,
154
    G_CTPOP = 139,
155
    G_BSWAP = 140,
156
    G_FCEIL = 141,
157
    G_FCOS  = 142,
158
    G_FSIN  = 143,
159
    G_FSQRT = 144,
160
    G_FFLOOR  = 145,
161
    G_ADDRSPACE_CAST  = 146,
162
    G_BLOCK_ADDR  = 147,
163
    BRANCH  = 148,
164
    BRANCH_COND_f32 = 149,
165
    BRANCH_COND_i32 = 150,
166
    BREAK = 151,
167
    BREAKC_f32  = 152,
168
    BREAKC_i32  = 153,
169
    BREAK_LOGICALNZ_f32 = 154,
170
    BREAK_LOGICALNZ_i32 = 155,
171
    BREAK_LOGICALZ_f32  = 156,
172
    BREAK_LOGICALZ_i32  = 157,
173
    CONST_COPY  = 158,
174
    CONTINUE  = 159,
175
    CONTINUEC_f32 = 160,
176
    CONTINUEC_i32 = 161,
177
    CONTINUE_LOGICALNZ_f32  = 162,
178
    CONTINUE_LOGICALNZ_i32  = 163,
179
    CONTINUE_LOGICALZ_f32 = 164,
180
    CONTINUE_LOGICALZ_i32 = 165,
181
    CUBE_eg_pseudo  = 166,
182
    CUBE_r600_pseudo  = 167,
183
    DEFAULT = 168,
184
    DOT_4 = 169,
185
    DUMMY_CHAIN = 170,
186
    ELSE  = 171,
187
    END = 172,
188
    ENDFUNC = 173,
189
    ENDIF = 174,
190
    ENDLOOP = 175,
191
    ENDMAIN = 176,
192
    ENDSWITCH = 177,
193
    FABS_R600 = 178,
194
    FNEG_R600 = 179,
195
    FUNC  = 180,
196
    IFC_f32 = 181,
197
    IFC_i32 = 182,
198
    IF_LOGICALNZ_f32  = 183,
199
    IF_LOGICALNZ_i32  = 184,
200
    IF_LOGICALZ_f32 = 185,
201
    IF_LOGICALZ_i32 = 186,
202
    IF_PREDICATE_SET  = 187,
203
    JUMP  = 188,
204
    JUMP_COND = 189,
205
    MASK_WRITE  = 190,
206
    MOV_IMM_F32 = 191,
207
    MOV_IMM_GLOBAL_ADDR = 192,
208
    MOV_IMM_I32 = 193,
209
    PRED_X  = 194,
210
    R600_EXTRACT_ELT_V2 = 195,
211
    R600_EXTRACT_ELT_V4 = 196,
212
    R600_INSERT_ELT_V2  = 197,
213
    R600_INSERT_ELT_V4  = 198,
214
    R600_RegisterLoad = 199,
215
    R600_RegisterStore  = 200,
216
    RETDYN  = 201,
217
    RETURN  = 202,
218
    TXD = 203,
219
    TXD_SHADOW  = 204,
220
    WHILELOOP = 205,
221
    ADD = 206,
222
    ADDC_UINT = 207,
223
    ADD_INT = 208,
224
    ALU_CLAUSE  = 209,
225
    AND_INT = 210,
226
    ASHR_eg = 211,
227
    ASHR_r600 = 212,
228
    BCNT_INT  = 213,
229
    BFE_INT_eg  = 214,
230
    BFE_UINT_eg = 215,
231
    BFI_INT_eg  = 216,
232
    BFM_INT_eg  = 217,
233
    BIT_ALIGN_INT_eg  = 218,
234
    CEIL  = 219,
235
    CF_ALU  = 220,
236
    CF_ALU_BREAK  = 221,
237
    CF_ALU_CONTINUE = 222,
238
    CF_ALU_ELSE_AFTER = 223,
239
    CF_ALU_POP_AFTER  = 224,
240
    CF_ALU_PUSH_BEFORE  = 225,
241
    CF_CALL_FS_EG = 226,
242
    CF_CALL_FS_R600 = 227,
243
    CF_CONTINUE_EG  = 228,
244
    CF_CONTINUE_R600  = 229,
245
    CF_ELSE_EG  = 230,
246
    CF_ELSE_R600  = 231,
247
    CF_END_CM = 232,
248
    CF_END_EG = 233,
249
    CF_END_R600 = 234,
250
    CF_JUMP_EG  = 235,
251
    CF_JUMP_R600  = 236,
252
    CF_PUSH_EG  = 237,
253
    CF_PUSH_ELSE_R600 = 238,
254
    CF_TC_EG  = 239,
255
    CF_TC_R600  = 240,
256
    CF_VC_EG  = 241,
257
    CF_VC_R600  = 242,
258
    CNDE_INT  = 243,
259
    CNDE_eg = 244,
260
    CNDE_r600 = 245,
261
    CNDGE_INT = 246,
262
    CNDGE_eg  = 247,
263
    CNDGE_r600  = 248,
264
    CNDGT_INT = 249,
265
    CNDGT_eg  = 250,
266
    CNDGT_r600  = 251,
267
    COS_cm  = 252,
268
    COS_eg  = 253,
269
    COS_r600  = 254,
270
    COS_r700  = 255,
271
    CUBE_eg_real  = 256,
272
    CUBE_r600_real  = 257,
273
    DOT4_eg = 258,
274
    DOT4_r600 = 259,
275
    EG_ExportBuf  = 260,
276
    EG_ExportSwz  = 261,
277
    END_LOOP_EG = 262,
278
    END_LOOP_R600 = 263,
279
    EXP_IEEE_cm = 264,
280
    EXP_IEEE_eg = 265,
281
    EXP_IEEE_r600 = 266,
282
    FETCH_CLAUSE  = 267,
283
    FFBH_UINT = 268,
284
    FFBL_INT  = 269,
285
    FLOOR = 270,
286
    FLT16_TO_FLT32  = 271,
287
    FLT32_TO_FLT16  = 272,
288
    FLT_TO_INT_eg = 273,
289
    FLT_TO_INT_r600 = 274,
290
    FLT_TO_UINT_eg  = 275,
291
    FLT_TO_UINT_r600  = 276,
292
    FMA_eg  = 277,
293
    FRACT = 278,
294
    GROUP_BARRIER = 279,
295
    INTERP_LOAD_P0  = 280,
296
    INTERP_PAIR_XY  = 281,
297
    INTERP_PAIR_ZW  = 282,
298
    INTERP_VEC_LOAD = 283,
299
    INTERP_XY = 284,
300
    INTERP_ZW = 285,
301
    INT_TO_FLT_eg = 286,
302
    INT_TO_FLT_r600 = 287,
303
    KILLGT  = 288,
304
    LDS_ADD = 289,
305
    LDS_ADD_RET = 290,
306
    LDS_AND = 291,
307
    LDS_AND_RET = 292,
308
    LDS_BYTE_READ_RET = 293,
309
    LDS_BYTE_WRITE  = 294,
310
    LDS_CMPST = 295,
311
    LDS_CMPST_RET = 296,
312
    LDS_MAX_INT = 297,
313
    LDS_MAX_INT_RET = 298,
314
    LDS_MAX_UINT  = 299,
315
    LDS_MAX_UINT_RET  = 300,
316
    LDS_MIN_INT = 301,
317
    LDS_MIN_INT_RET = 302,
318
    LDS_MIN_UINT  = 303,
319
    LDS_MIN_UINT_RET  = 304,
320
    LDS_OR  = 305,
321
    LDS_OR_RET  = 306,
322
    LDS_READ_RET  = 307,
323
    LDS_SHORT_READ_RET  = 308,
324
    LDS_SHORT_WRITE = 309,
325
    LDS_SUB = 310,
326
    LDS_SUB_RET = 311,
327
    LDS_UBYTE_READ_RET  = 312,
328
    LDS_USHORT_READ_RET = 313,
329
    LDS_WRITE = 314,
330
    LDS_WRXCHG  = 315,
331
    LDS_WRXCHG_RET  = 316,
332
    LDS_XOR = 317,
333
    LDS_XOR_RET = 318,
334
    LITERALS  = 319,
335
    LOG_CLAMPED_eg  = 320,
336
    LOG_CLAMPED_r600  = 321,
337
    LOG_IEEE_cm = 322,
338
    LOG_IEEE_eg = 323,
339
    LOG_IEEE_r600 = 324,
340
    LOOP_BREAK_EG = 325,
341
    LOOP_BREAK_R600 = 326,
342
    LSHL_eg = 327,
343
    LSHL_r600 = 328,
344
    LSHR_eg = 329,
345
    LSHR_r600 = 330,
346
    MAX = 331,
347
    MAX_DX10  = 332,
348
    MAX_INT = 333,
349
    MAX_UINT  = 334,
350
    MIN = 335,
351
    MIN_DX10  = 336,
352
    MIN_INT = 337,
353
    MIN_UINT  = 338,
354
    MOV = 339,
355
    MOVA_INT_eg = 340,
356
    MUL = 341,
357
    MULADD_IEEE_eg  = 342,
358
    MULADD_IEEE_r600  = 343,
359
    MULADD_INT24_cm = 344,
360
    MULADD_UINT24_eg  = 345,
361
    MULADD_eg = 346,
362
    MULADD_r600 = 347,
363
    MULHI_INT_cm  = 348,
364
    MULHI_INT_cm24  = 349,
365
    MULHI_INT_eg  = 350,
366
    MULHI_INT_r600  = 351,
367
    MULHI_UINT24_eg = 352,
368
    MULHI_UINT_cm = 353,
369
    MULHI_UINT_cm24 = 354,
370
    MULHI_UINT_eg = 355,
371
    MULHI_UINT_r600 = 356,
372
    MULLO_INT_cm  = 357,
373
    MULLO_INT_eg  = 358,
374
    MULLO_INT_r600  = 359,
375
    MULLO_UINT_cm = 360,
376
    MULLO_UINT_eg = 361,
377
    MULLO_UINT_r600 = 362,
378
    MUL_IEEE  = 363,
379
    MUL_INT24_cm  = 364,
380
    MUL_LIT_eg  = 365,
381
    MUL_LIT_r600  = 366,
382
    MUL_UINT24_eg = 367,
383
    NOT_INT = 368,
384
    OR_INT  = 369,
385
    PAD = 370,
386
    POP_EG  = 371,
387
    POP_R600  = 372,
388
    PRED_SETE = 373,
389
    PRED_SETE_INT = 374,
390
    PRED_SETGE  = 375,
391
    PRED_SETGE_INT  = 376,
392
    PRED_SETGT  = 377,
393
    PRED_SETGT_INT  = 378,
394
    PRED_SETNE  = 379,
395
    PRED_SETNE_INT  = 380,
396
    R600_ExportBuf  = 381,
397
    R600_ExportSwz  = 382,
398
    RAT_ATOMIC_ADD_NORET  = 383,
399
    RAT_ATOMIC_ADD_RTN  = 384,
400
    RAT_ATOMIC_AND_NORET  = 385,
401
    RAT_ATOMIC_AND_RTN  = 386,
402
    RAT_ATOMIC_CMPXCHG_INT_NORET  = 387,
403
    RAT_ATOMIC_CMPXCHG_INT_RTN  = 388,
404
    RAT_ATOMIC_DEC_UINT_NORET = 389,
405
    RAT_ATOMIC_DEC_UINT_RTN = 390,
406
    RAT_ATOMIC_INC_UINT_NORET = 391,
407
    RAT_ATOMIC_INC_UINT_RTN = 392,
408
    RAT_ATOMIC_MAX_INT_NORET  = 393,
409
    RAT_ATOMIC_MAX_INT_RTN  = 394,
410
    RAT_ATOMIC_MAX_UINT_NORET = 395,
411
    RAT_ATOMIC_MAX_UINT_RTN = 396,
412
    RAT_ATOMIC_MIN_INT_NORET  = 397,
413
    RAT_ATOMIC_MIN_INT_RTN  = 398,
414
    RAT_ATOMIC_MIN_UINT_NORET = 399,
415
    RAT_ATOMIC_MIN_UINT_RTN = 400,
416
    RAT_ATOMIC_OR_NORET = 401,
417
    RAT_ATOMIC_OR_RTN = 402,
418
    RAT_ATOMIC_RSUB_NORET = 403,
419
    RAT_ATOMIC_RSUB_RTN = 404,
420
    RAT_ATOMIC_SUB_NORET  = 405,
421
    RAT_ATOMIC_SUB_RTN  = 406,
422
    RAT_ATOMIC_XCHG_INT_NORET = 407,
423
    RAT_ATOMIC_XCHG_INT_RTN = 408,
424
    RAT_ATOMIC_XOR_NORET  = 409,
425
    RAT_ATOMIC_XOR_RTN  = 410,
426
    RAT_MSKOR = 411,
427
    RAT_STORE_DWORD128  = 412,
428
    RAT_STORE_DWORD32 = 413,
429
    RAT_STORE_DWORD64 = 414,
430
    RAT_STORE_TYPED_cm  = 415,
431
    RAT_STORE_TYPED_eg  = 416,
432
    RAT_WRITE_CACHELESS_128_eg  = 417,
433
    RAT_WRITE_CACHELESS_32_eg = 418,
434
    RAT_WRITE_CACHELESS_64_eg = 419,
435
    RECIPSQRT_CLAMPED_cm  = 420,
436
    RECIPSQRT_CLAMPED_eg  = 421,
437
    RECIPSQRT_CLAMPED_r600  = 422,
438
    RECIPSQRT_IEEE_cm = 423,
439
    RECIPSQRT_IEEE_eg = 424,
440
    RECIPSQRT_IEEE_r600 = 425,
441
    RECIP_CLAMPED_cm  = 426,
442
    RECIP_CLAMPED_eg  = 427,
443
    RECIP_CLAMPED_r600  = 428,
444
    RECIP_IEEE_cm = 429,
445
    RECIP_IEEE_eg = 430,
446
    RECIP_IEEE_r600 = 431,
447
    RECIP_UINT_eg = 432,
448
    RECIP_UINT_r600 = 433,
449
    RNDNE = 434,
450
    SETE  = 435,
451
    SETE_DX10 = 436,
452
    SETE_INT  = 437,
453
    SETGE_DX10  = 438,
454
    SETGE_INT = 439,
455
    SETGE_UINT  = 440,
456
    SETGT_DX10  = 441,
457
    SETGT_INT = 442,
458
    SETGT_UINT  = 443,
459
    SETNE_DX10  = 444,
460
    SETNE_INT = 445,
461
    SGE = 446,
462
    SGT = 447,
463
    SIN_cm  = 448,
464
    SIN_eg  = 449,
465
    SIN_r600  = 450,
466
    SIN_r700  = 451,
467
    SNE = 452,
468
    SUBB_UINT = 453,
469
    SUB_INT = 454,
470
    TEX_GET_GRADIENTS_H = 455,
471
    TEX_GET_GRADIENTS_V = 456,
472
    TEX_GET_TEXTURE_RESINFO = 457,
473
    TEX_LD  = 458,
474
    TEX_LDPTR = 459,
475
    TEX_SAMPLE  = 460,
476
    TEX_SAMPLE_C  = 461,
477
    TEX_SAMPLE_C_G  = 462,
478
    TEX_SAMPLE_C_L  = 463,
479
    TEX_SAMPLE_C_LB = 464,
480
    TEX_SAMPLE_G  = 465,
481
    TEX_SAMPLE_L  = 466,
482
    TEX_SAMPLE_LB = 467,
483
    TEX_SET_GRADIENTS_H = 468,
484
    TEX_SET_GRADIENTS_V = 469,
485
    TEX_VTX_CONSTBUF  = 470,
486
    TEX_VTX_TEXBUF  = 471,
487
    TRUNC = 472,
488
    UINT_TO_FLT_eg  = 473,
489
    UINT_TO_FLT_r600  = 474,
490
    VTX_READ_128_cm = 475,
491
    VTX_READ_128_eg = 476,
492
    VTX_READ_16_cm  = 477,
493
    VTX_READ_16_eg  = 478,
494
    VTX_READ_32_cm  = 479,
495
    VTX_READ_32_eg  = 480,
496
    VTX_READ_64_cm  = 481,
497
    VTX_READ_64_eg  = 482,
498
    VTX_READ_8_cm = 483,
499
    VTX_READ_8_eg = 484,
500
    WHILE_LOOP_EG = 485,
501
    WHILE_LOOP_R600 = 486,
502
    XOR_INT = 487,
503
    INSTRUCTION_LIST_END = 488
504
  };
505
506
} // end R600 namespace
507
} // end llvm namespace
508
#endif // GET_INSTRINFO_ENUM
509
510
#ifdef GET_INSTRINFO_SCHED_ENUM
511
#undef GET_INSTRINFO_SCHED_ENUM
512
namespace llvm {
513
514
namespace R600 {
515
namespace Sched {
516
  enum {
517
    NoInstrModel  = 0,
518
    NullALU = 1,
519
    VecALU  = 2,
520
    AnyALU  = 3,
521
    TransALU  = 4,
522
    XALU  = 5,
523
    SCHED_LIST_END = 6
524
  };
525
} // end Sched namespace
526
} // end R600 namespace
527
} // end llvm namespace
528
#endif // GET_INSTRINFO_SCHED_ENUM
529
530
#ifdef GET_INSTRINFO_MC_DESC
531
#undef GET_INSTRINFO_MC_DESC
532
namespace llvm {
533
534
535
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
536
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
537
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
538
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
539
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
540
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
541
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
542
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
543
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
544
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
545
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
546
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
547
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
548
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
549
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
550
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
551
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
552
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
553
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
554
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
555
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
556
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
557
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
558
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
559
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
560
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
561
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
562
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
563
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
564
static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
565
static const MCOperandInfo OperandInfo32[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
566
static const MCOperandInfo OperandInfo33[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
567
static const MCOperandInfo OperandInfo34[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
568
static const MCOperandInfo OperandInfo35[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
569
static const MCOperandInfo OperandInfo36[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
570
static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
571
static const MCOperandInfo OperandInfo38[] = { { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
572
static const MCOperandInfo OperandInfo39[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
573
static const MCOperandInfo OperandInfo40[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
574
static const MCOperandInfo OperandInfo41[] = { { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
575
static const MCOperandInfo OperandInfo42[] = { { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
576
static const MCOperandInfo OperandInfo43[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
577
static const MCOperandInfo OperandInfo44[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
578
static const MCOperandInfo OperandInfo45[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
579
static const MCOperandInfo OperandInfo46[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
580
static const MCOperandInfo OperandInfo47[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
581
static const MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
582
static const MCOperandInfo OperandInfo49[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
583
static const MCOperandInfo OperandInfo50[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
584
static const MCOperandInfo OperandInfo51[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
585
static const MCOperandInfo OperandInfo52[] = { { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
586
static const MCOperandInfo OperandInfo53[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
587
static const MCOperandInfo OperandInfo54[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
588
static const MCOperandInfo OperandInfo55[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
589
static const MCOperandInfo OperandInfo56[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
590
static const MCOperandInfo OperandInfo57[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
591
static const MCOperandInfo OperandInfo58[] = { { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
592
static const MCOperandInfo OperandInfo59[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
593
static const MCOperandInfo OperandInfo60[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
594
static const MCOperandInfo OperandInfo61[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
595
static const MCOperandInfo OperandInfo62[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
596
static const MCOperandInfo OperandInfo63[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
597
static const MCOperandInfo OperandInfo64[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
598
static const MCOperandInfo OperandInfo65[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
599
static const MCOperandInfo OperandInfo66[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
600
static const MCOperandInfo OperandInfo67[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
601
static const MCOperandInfo OperandInfo68[] = { { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
602
static const MCOperandInfo OperandInfo69[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
603
static const MCOperandInfo OperandInfo70[] = { { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
604
static const MCOperandInfo OperandInfo71[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
605
606
extern const MCInstrDesc R600Insts[] = {
607
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
608
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
609
  { 2,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
610
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = CFI_INSTRUCTION
611
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = EH_LABEL
612
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = GC_LABEL
613
  { 6,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #6 = ANNOTATION_LABEL
614
  { 7,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #7 = KILL
615
  { 8,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #8 = EXTRACT_SUBREG
616
  { 9,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #9 = INSERT_SUBREG
617
  { 10, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #10 = IMPLICIT_DEF
618
  { 11, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #11 = SUBREG_TO_REG
619
  { 12, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #12 = COPY_TO_REGCLASS
620
  { 13, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #13 = DBG_VALUE
621
  { 14, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #14 = DBG_LABEL
622
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = REG_SEQUENCE
623
  { 16, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #16 = COPY
624
  { 17, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #17 = BUNDLE
625
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_START
626
  { 19, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #19 = LIFETIME_END
627
  { 20, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #20 = STACKMAP
628
  { 21, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #21 = FENTRY_CALL
629
  { 22, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #22 = PATCHPOINT
630
  { 23, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #23 = LOAD_STACK_GUARD
631
  { 24, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #24 = STATEPOINT
632
  { 25, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #25 = LOCAL_ESCAPE
633
  { 26, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = FAULTING_OP
634
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_OP
635
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_ENTER
636
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_RET
637
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_FUNCTION_EXIT
638
  { 31, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #31 = PATCHABLE_TAIL_CALL
639
  { 32, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #32 = PATCHABLE_EVENT_CALL
640
  { 33, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
641
  { 34, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #34 = ICALL_BRANCH_FUNNEL
642
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_ADD
643
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_SUB
644
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_MUL
645
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_SDIV
646
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_UDIV
647
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_SREM
648
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_UREM
649
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_AND
650
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_OR
651
  { 44, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #44 = G_XOR
652
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_IMPLICIT_DEF
653
  { 46, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #46 = G_PHI
654
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_FRAME_INDEX
655
  { 48, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #48 = G_GLOBAL_VALUE
656
  { 49, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #49 = G_EXTRACT
657
  { 50, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_UNMERGE_VALUES
658
  { 51, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #51 = G_INSERT
659
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_MERGE_VALUES
660
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_BUILD_VECTOR
661
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BUILD_VECTOR_TRUNC
662
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_CONCAT_VECTORS
663
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_PTRTOINT
664
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_INTTOPTR
665
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_BITCAST
666
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_INTRINSIC_TRUNC
667
  { 60, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #60 = G_INTRINSIC_ROUND
668
  { 61, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #61 = G_LOAD
669
  { 62, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #62 = G_SEXTLOAD
670
  { 63, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #63 = G_ZEXTLOAD
671
  { 64, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #64 = G_STORE
672
  { 65, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #65 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
673
  { 66, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMIC_CMPXCHG
674
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XCHG
675
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_ADD
676
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_SUB
677
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_AND
678
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_NAND
679
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_OR
680
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_XOR
681
  { 74, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #74 = G_ATOMICRMW_MAX
682
  { 75, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #75 = G_ATOMICRMW_MIN
683
  { 76, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #76 = G_ATOMICRMW_UMAX
684
  { 77, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #77 = G_ATOMICRMW_UMIN
685
  { 78, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #78 = G_BRCOND
686
  { 79, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #79 = G_BRINDIRECT
687
  { 80, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #80 = G_INTRINSIC
688
  { 81, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #81 = G_INTRINSIC_W_SIDE_EFFECTS
689
  { 82, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_ANYEXT
690
  { 83, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_TRUNC
691
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #84 = G_CONSTANT
692
  { 85, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #85 = G_FCONSTANT
693
  { 86, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #86 = G_VASTART
694
  { 87, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #87 = G_VAARG
695
  { 88, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #88 = G_SEXT
696
  { 89, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #89 = G_ZEXT
697
  { 90, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_SHL
698
  { 91, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_LSHR
699
  { 92, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #92 = G_ASHR
700
  { 93, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #93 = G_ICMP
701
  { 94, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #94 = G_FCMP
702
  { 95, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #95 = G_SELECT
703
  { 96, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_UADDO
704
  { 97, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #97 = G_UADDE
705
  { 98, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #98 = G_USUBO
706
  { 99, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #99 = G_USUBE
707
  { 100,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #100 = G_SADDO
708
  { 101,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #101 = G_SADDE
709
  { 102,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #102 = G_SSUBO
710
  { 103,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #103 = G_SSUBE
711
  { 104,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #104 = G_UMULO
712
  { 105,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #105 = G_SMULO
713
  { 106,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_UMULH
714
  { 107,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #107 = G_SMULH
715
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FADD
716
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FSUB
717
  { 110,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FMUL
718
  { 111,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #111 = G_FMA
719
  { 112,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #112 = G_FDIV
720
  { 113,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #113 = G_FREM
721
  { 114,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #114 = G_FPOW
722
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FEXP
723
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #116 = G_FEXP2
724
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #117 = G_FLOG
725
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #118 = G_FLOG2
726
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #119 = G_FLOG10
727
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #120 = G_FNEG
728
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_FPEXT
729
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #122 = G_FPTRUNC
730
  { 123,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #123 = G_FPTOSI
731
  { 124,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #124 = G_FPTOUI
732
  { 125,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #125 = G_SITOFP
733
  { 126,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #126 = G_UITOFP
734
  { 127,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #127 = G_FABS
735
  { 128,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #128 = G_FCANONICALIZE
736
  { 129,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #129 = G_GEP
737
  { 130,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #130 = G_PTR_MASK
738
  { 131,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #131 = G_BR
739
  { 132,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #132 = G_INSERT_VECTOR_ELT
740
  { 133,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #133 = G_EXTRACT_VECTOR_ELT
741
  { 134,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #134 = G_SHUFFLE_VECTOR
742
  { 135,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_CTTZ
743
  { 136,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #136 = G_CTTZ_ZERO_UNDEF
744
  { 137,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #137 = G_CTLZ
745
  { 138,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #138 = G_CTLZ_ZERO_UNDEF
746
  { 139,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #139 = G_CTPOP
747
  { 140,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #140 = G_BSWAP
748
  { 141,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #141 = G_FCEIL
749
  { 142,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #142 = G_FCOS
750
  { 143,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #143 = G_FSIN
751
  { 144,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #144 = G_FSQRT
752
  { 145,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #145 = G_FFLOOR
753
  { 146,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #146 = G_ADDRSPACE_CAST
754
  { 147,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #147 = G_BLOCK_ADDR
755
  { 148,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #148 = BRANCH
756
  { 149,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #149 = BRANCH_COND_f32
757
  { 150,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #150 = BRANCH_COND_i32
758
  { 151,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #151 = BREAK
759
  { 152,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #152 = BREAKC_f32
760
  { 153,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #153 = BREAKC_i32
761
  { 154,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #154 = BREAK_LOGICALNZ_f32
762
  { 155,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #155 = BREAK_LOGICALNZ_i32
763
  { 156,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #156 = BREAK_LOGICALZ_f32
764
  { 157,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #157 = BREAK_LOGICALZ_i32
765
  { 158,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #158 = CONST_COPY
766
  { 159,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #159 = CONTINUE
767
  { 160,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #160 = CONTINUEC_f32
768
  { 161,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #161 = CONTINUEC_i32
769
  { 162,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #162 = CONTINUE_LOGICALNZ_f32
770
  { 163,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #163 = CONTINUE_LOGICALNZ_i32
771
  { 164,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #164 = CONTINUE_LOGICALZ_f32
772
  { 165,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #165 = CONTINUE_LOGICALZ_i32
773
  { 166,  2,  1,  0,  2,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #166 = CUBE_eg_pseudo
774
  { 167,  2,  1,  0,  2,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #167 = CUBE_r600_pseudo
775
  { 168,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #168 = DEFAULT
776
  { 169,  71, 1,  0,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #169 = DOT_4
777
  { 170,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #170 = DUMMY_CHAIN
778
  { 171,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #171 = ELSE
779
  { 172,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #172 = END
780
  { 173,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #173 = ENDFUNC
781
  { 174,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #174 = ENDIF
782
  { 175,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #175 = ENDLOOP
783
  { 176,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #176 = ENDMAIN
784
  { 177,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #177 = ENDSWITCH
785
  { 178,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #178 = FABS_R600
786
  { 179,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #179 = FNEG_R600
787
  { 180,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #180 = FUNC
788
  { 181,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #181 = IFC_f32
789
  { 182,  2,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #182 = IFC_i32
790
  { 183,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #183 = IF_LOGICALNZ_f32
791
  { 184,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #184 = IF_LOGICALNZ_i32
792
  { 185,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #185 = IF_LOGICALZ_f32
793
  { 186,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #186 = IF_LOGICALZ_i32
794
  { 187,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #187 = IF_PREDICATE_SET
795
  { 188,  1,  0,  0,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #188 = JUMP
796
  { 189,  2,  0,  0,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #189 = JUMP_COND
797
  { 190,  1,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #190 = MASK_WRITE
798
  { 191,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #191 = MOV_IMM_F32
799
  { 192,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #192 = MOV_IMM_GLOBAL_ADDR
800
  { 193,  2,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #193 = MOV_IMM_I32
801
  { 194,  4,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #194 = PRED_X
802
  { 195,  3,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #195 = R600_EXTRACT_ELT_V2
803
  { 196,  3,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #196 = R600_EXTRACT_ELT_V4
804
  { 197,  4,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #197 = R600_INSERT_ELT_V2
805
  { 198,  4,  1,  0,  3,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #198 = R600_INSERT_ELT_V4
806
  { 199,  4,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #199 = R600_RegisterLoad
807
  { 200,  4,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #200 = R600_RegisterStore
808
  { 201,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #201 = RETDYN
809
  { 202,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #202 = RETURN
810
  { 203,  7,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #203 = TXD
811
  { 204,  7,  1,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #204 = TXD_SHADOW
812
  { 205,  0,  0,  0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #205 = WHILELOOP
813
  { 206,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #206 = ADD
814
  { 207,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #207 = ADDC_UINT
815
  { 208,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #208 = ADD_INT
816
  { 209,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #209 = ALU_CLAUSE
817
  { 210,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #210 = AND_INT
818
  { 211,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #211 = ASHR_eg
819
  { 212,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #212 = ASHR_r600
820
  { 213,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #213 = BCNT_INT
821
  { 214,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #214 = BFE_INT_eg
822
  { 215,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #215 = BFE_UINT_eg
823
  { 216,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #216 = BFI_INT_eg
824
  { 217,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #217 = BFM_INT_eg
825
  { 218,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #218 = BIT_ALIGN_INT_eg
826
  { 219,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #219 = CEIL
827
  { 220,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #220 = CF_ALU
828
  { 221,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #221 = CF_ALU_BREAK
829
  { 222,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #222 = CF_ALU_CONTINUE
830
  { 223,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #223 = CF_ALU_ELSE_AFTER
831
  { 224,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #224 = CF_ALU_POP_AFTER
832
  { 225,  9,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #225 = CF_ALU_PUSH_BEFORE
833
  { 226,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #226 = CF_CALL_FS_EG
834
  { 227,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #227 = CF_CALL_FS_R600
835
  { 228,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #228 = CF_CONTINUE_EG
836
  { 229,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #229 = CF_CONTINUE_R600
837
  { 230,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #230 = CF_ELSE_EG
838
  { 231,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #231 = CF_ELSE_R600
839
  { 232,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #232 = CF_END_CM
840
  { 233,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #233 = CF_END_EG
841
  { 234,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #234 = CF_END_R600
842
  { 235,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #235 = CF_JUMP_EG
843
  { 236,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #236 = CF_JUMP_R600
844
  { 237,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #237 = CF_PUSH_EG
845
  { 238,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #238 = CF_PUSH_ELSE_R600
846
  { 239,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #239 = CF_TC_EG
847
  { 240,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #240 = CF_TC_R600
848
  { 241,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #241 = CF_VC_EG
849
  { 242,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #242 = CF_VC_R600
850
  { 243,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #243 = CNDE_INT
851
  { 244,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #244 = CNDE_eg
852
  { 245,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #245 = CNDE_r600
853
  { 246,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #246 = CNDGE_INT
854
  { 247,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #247 = CNDGE_eg
855
  { 248,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #248 = CNDGE_r600
856
  { 249,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #249 = CNDGT_INT
857
  { 250,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #250 = CNDGT_eg
858
  { 251,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #251 = CNDGT_r600
859
  { 252,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4650ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #252 = COS_cm
860
  { 253,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #253 = COS_eg
861
  { 254,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #254 = COS_r600
862
  { 255,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #255 = COS_r700
863
  { 256,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #256 = CUBE_eg_real
864
  { 257,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #257 = CUBE_r600_real
865
  { 258,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #258 = DOT4_eg
866
  { 259,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #259 = DOT4_r600
867
  { 260,  7,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #260 = EG_ExportBuf
868
  { 261,  9,  0,  0,  1,  0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #261 = EG_ExportSwz
869
  { 262,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #262 = END_LOOP_EG
870
  { 263,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #263 = END_LOOP_R600
871
  { 264,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #264 = EXP_IEEE_cm
872
  { 265,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #265 = EXP_IEEE_eg
873
  { 266,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #266 = EXP_IEEE_r600
874
  { 267,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #267 = FETCH_CLAUSE
875
  { 268,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #268 = FFBH_UINT
876
  { 269,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #269 = FFBL_INT
877
  { 270,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #270 = FLOOR
878
  { 271,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #271 = FLT16_TO_FLT32
879
  { 272,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #272 = FLT32_TO_FLT16
880
  { 273,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #273 = FLT_TO_INT_eg
881
  { 274,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #274 = FLT_TO_INT_r600
882
  { 275,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #275 = FLT_TO_UINT_eg
883
  { 276,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #276 = FLT_TO_UINT_r600
884
  { 277,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #277 = FMA_eg
885
  { 278,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #278 = FRACT
886
  { 279,  0,  0,  0,  3,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #279 = GROUP_BARRIER
887
  { 280,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #280 = INTERP_LOAD_P0
888
  { 281,  5,  2,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #281 = INTERP_PAIR_XY
889
  { 282,  5,  2,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #282 = INTERP_PAIR_ZW
890
  { 283,  2,  1,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #283 = INTERP_VEC_LOAD
891
  { 284,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #284 = INTERP_XY
892
  { 285,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #285 = INTERP_ZW
893
  { 286,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #286 = INT_TO_FLT_eg
894
  { 287,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #287 = INT_TO_FLT_r600
895
  { 288,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #288 = KILLGT
896
  { 289,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #289 = LDS_ADD
897
  { 290,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #290 = LDS_ADD_RET
898
  { 291,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #291 = LDS_AND
899
  { 292,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #292 = LDS_AND_RET
900
  { 293,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #293 = LDS_BYTE_READ_RET
901
  { 294,  9,  0,  0,  5,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #294 = LDS_BYTE_WRITE
902
  { 295,  12, 0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #295 = LDS_CMPST
903
  { 296,  13, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #296 = LDS_CMPST_RET
904
  { 297,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #297 = LDS_MAX_INT
905
  { 298,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #298 = LDS_MAX_INT_RET
906
  { 299,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #299 = LDS_MAX_UINT
907
  { 300,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #300 = LDS_MAX_UINT_RET
908
  { 301,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #301 = LDS_MIN_INT
909
  { 302,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #302 = LDS_MIN_INT_RET
910
  { 303,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #303 = LDS_MIN_UINT
911
  { 304,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #304 = LDS_MIN_UINT_RET
912
  { 305,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #305 = LDS_OR
913
  { 306,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #306 = LDS_OR_RET
914
  { 307,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #307 = LDS_READ_RET
915
  { 308,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #308 = LDS_SHORT_READ_RET
916
  { 309,  9,  0,  0,  5,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #309 = LDS_SHORT_WRITE
917
  { 310,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #310 = LDS_SUB
918
  { 311,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #311 = LDS_SUB_RET
919
  { 312,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #312 = LDS_UBYTE_READ_RET
920
  { 313,  7,  1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #313 = LDS_USHORT_READ_RET
921
  { 314,  9,  0,  0,  5,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #314 = LDS_WRITE
922
  { 315,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #315 = LDS_WRXCHG
923
  { 316,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #316 = LDS_WRXCHG_RET
924
  { 317,  9,  0,  0,  5,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #317 = LDS_XOR
925
  { 318,  10, 1,  0,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #318 = LDS_XOR_RET
926
  { 319,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #319 = LITERALS
927
  { 320,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #320 = LOG_CLAMPED_eg
928
  { 321,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #321 = LOG_CLAMPED_r600
929
  { 322,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #322 = LOG_IEEE_cm
930
  { 323,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #323 = LOG_IEEE_eg
931
  { 324,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #324 = LOG_IEEE_r600
932
  { 325,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #325 = LOOP_BREAK_EG
933
  { 326,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #326 = LOOP_BREAK_R600
934
  { 327,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #327 = LSHL_eg
935
  { 328,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #328 = LSHL_r600
936
  { 329,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #329 = LSHR_eg
937
  { 330,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #330 = LSHR_r600
938
  { 331,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #331 = MAX
939
  { 332,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #332 = MAX_DX10
940
  { 333,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #333 = MAX_INT
941
  { 334,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #334 = MAX_UINT
942
  { 335,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #335 = MIN
943
  { 336,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #336 = MIN_DX10
944
  { 337,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #337 = MIN_INT
945
  { 338,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #338 = MIN_UINT
946
  { 339,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #339 = MOV
947
  { 340,  14, 1,  0,  2,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #340 = MOVA_INT_eg
948
  { 341,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #341 = MUL
949
  { 342,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #342 = MULADD_IEEE_eg
950
  { 343,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #343 = MULADD_IEEE_r600
951
  { 344,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #344 = MULADD_INT24_cm
952
  { 345,  19, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #345 = MULADD_UINT24_eg
953
  { 346,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #346 = MULADD_eg
954
  { 347,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #347 = MULADD_r600
955
  { 348,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #348 = MULHI_INT_cm
956
  { 349,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #349 = MULHI_INT_cm24
957
  { 350,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #350 = MULHI_INT_eg
958
  { 351,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #351 = MULHI_INT_r600
959
  { 352,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #352 = MULHI_UINT24_eg
960
  { 353,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #353 = MULHI_UINT_cm
961
  { 354,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #354 = MULHI_UINT_cm24
962
  { 355,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #355 = MULHI_UINT_eg
963
  { 356,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #356 = MULHI_UINT_r600
964
  { 357,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #357 = MULLO_INT_cm
965
  { 358,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #358 = MULLO_INT_eg
966
  { 359,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #359 = MULLO_INT_r600
967
  { 360,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a40ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #360 = MULLO_UINT_cm
968
  { 361,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #361 = MULLO_UINT_eg
969
  { 362,  21, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #362 = MULLO_UINT_r600
970
  { 363,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #363 = MUL_IEEE
971
  { 364,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #364 = MUL_INT24_cm
972
  { 365,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #365 = MUL_LIT_eg
973
  { 366,  19, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4220ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #366 = MUL_LIT_r600
974
  { 367,  21, 1,  0,  2,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #367 = MUL_UINT24_eg
975
  { 368,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #368 = NOT_INT
976
  { 369,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #369 = OR_INT
977
  { 370,  0,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #370 = PAD
978
  { 371,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #371 = POP_EG
979
  { 372,  2,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #372 = POP_R600
980
  { 373,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #373 = PRED_SETE
981
  { 374,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #374 = PRED_SETE_INT
982
  { 375,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #375 = PRED_SETGE
983
  { 376,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #376 = PRED_SETGE_INT
984
  { 377,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #377 = PRED_SETGT
985
  { 378,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #378 = PRED_SETGT_INT
986
  { 379,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #379 = PRED_SETNE
987
  { 380,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #380 = PRED_SETNE_INT
988
  { 381,  7,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #381 = R600_ExportBuf
989
  { 382,  9,  0,  0,  1,  0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #382 = R600_ExportSwz
990
  { 383,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #383 = RAT_ATOMIC_ADD_NORET
991
  { 384,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #384 = RAT_ATOMIC_ADD_RTN
992
  { 385,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #385 = RAT_ATOMIC_AND_NORET
993
  { 386,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #386 = RAT_ATOMIC_AND_RTN
994
  { 387,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #387 = RAT_ATOMIC_CMPXCHG_INT_NORET
995
  { 388,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #388 = RAT_ATOMIC_CMPXCHG_INT_RTN
996
  { 389,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #389 = RAT_ATOMIC_DEC_UINT_NORET
997
  { 390,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #390 = RAT_ATOMIC_DEC_UINT_RTN
998
  { 391,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #391 = RAT_ATOMIC_INC_UINT_NORET
999
  { 392,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #392 = RAT_ATOMIC_INC_UINT_RTN
1000
  { 393,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #393 = RAT_ATOMIC_MAX_INT_NORET
1001
  { 394,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #394 = RAT_ATOMIC_MAX_INT_RTN
1002
  { 395,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #395 = RAT_ATOMIC_MAX_UINT_NORET
1003
  { 396,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #396 = RAT_ATOMIC_MAX_UINT_RTN
1004
  { 397,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #397 = RAT_ATOMIC_MIN_INT_NORET
1005
  { 398,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #398 = RAT_ATOMIC_MIN_INT_RTN
1006
  { 399,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #399 = RAT_ATOMIC_MIN_UINT_NORET
1007
  { 400,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #400 = RAT_ATOMIC_MIN_UINT_RTN
1008
  { 401,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #401 = RAT_ATOMIC_OR_NORET
1009
  { 402,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #402 = RAT_ATOMIC_OR_RTN
1010
  { 403,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #403 = RAT_ATOMIC_RSUB_NORET
1011
  { 404,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #404 = RAT_ATOMIC_RSUB_RTN
1012
  { 405,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #405 = RAT_ATOMIC_SUB_NORET
1013
  { 406,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #406 = RAT_ATOMIC_SUB_RTN
1014
  { 407,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #407 = RAT_ATOMIC_XCHG_INT_NORET
1015
  { 408,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #408 = RAT_ATOMIC_XCHG_INT_RTN
1016
  { 409,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #409 = RAT_ATOMIC_XOR_NORET
1017
  { 410,  3,  1,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #410 = RAT_ATOMIC_XOR_RTN
1018
  { 411,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #411 = RAT_MSKOR
1019
  { 412,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #412 = RAT_STORE_DWORD128
1020
  { 413,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #413 = RAT_STORE_DWORD32
1021
  { 414,  2,  0,  0,  1,  0|(1ULL<<MCID::MayStore), 0x20000ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #414 = RAT_STORE_DWORD64
1022
  { 415,  4,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #415 = RAT_STORE_TYPED_cm
1023
  { 416,  4,  0,  0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #416 = RAT_STORE_TYPED_eg
1024
  { 417,  3,  0,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #417 = RAT_WRITE_CACHELESS_128_eg
1025
  { 418,  3,  0,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #418 = RAT_WRITE_CACHELESS_32_eg
1026
  { 419,  3,  0,  0,  1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #419 = RAT_WRITE_CACHELESS_64_eg
1027
  { 420,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #420 = RECIPSQRT_CLAMPED_cm
1028
  { 421,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #421 = RECIPSQRT_CLAMPED_eg
1029
  { 422,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #422 = RECIPSQRT_CLAMPED_r600
1030
  { 423,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #423 = RECIPSQRT_IEEE_cm
1031
  { 424,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #424 = RECIPSQRT_IEEE_eg
1032
  { 425,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #425 = RECIPSQRT_IEEE_r600
1033
  { 426,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #426 = RECIP_CLAMPED_cm
1034
  { 427,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #427 = RECIP_CLAMPED_eg
1035
  { 428,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #428 = RECIP_CLAMPED_r600
1036
  { 429,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #429 = RECIP_IEEE_cm
1037
  { 430,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #430 = RECIP_IEEE_eg
1038
  { 431,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #431 = RECIP_IEEE_r600
1039
  { 432,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #432 = RECIP_UINT_eg
1040
  { 433,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #433 = RECIP_UINT_r600
1041
  { 434,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #434 = RNDNE
1042
  { 435,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #435 = SETE
1043
  { 436,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #436 = SETE_DX10
1044
  { 437,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #437 = SETE_INT
1045
  { 438,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #438 = SETGE_DX10
1046
  { 439,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #439 = SETGE_INT
1047
  { 440,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #440 = SETGE_UINT
1048
  { 441,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #441 = SETGT_DX10
1049
  { 442,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #442 = SETGT_INT
1050
  { 443,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #443 = SETGT_UINT
1051
  { 444,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #444 = SETNE_DX10
1052
  { 445,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #445 = SETNE_INT
1053
  { 446,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #446 = SGE
1054
  { 447,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #447 = SGT
1055
  { 448,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4650ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #448 = SIN_cm
1056
  { 449,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #449 = SIN_eg
1057
  { 450,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #450 = SIN_r600
1058
  { 451,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #451 = SIN_r700
1059
  { 452,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #452 = SNE
1060
  { 453,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #453 = SUBB_UINT
1061
  { 454,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #454 = SUB_INT
1062
  { 455,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #455 = TEX_GET_GRADIENTS_H
1063
  { 456,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #456 = TEX_GET_GRADIENTS_V
1064
  { 457,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #457 = TEX_GET_TEXTURE_RESINFO
1065
  { 458,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #458 = TEX_LD
1066
  { 459,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #459 = TEX_LDPTR
1067
  { 460,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #460 = TEX_SAMPLE
1068
  { 461,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #461 = TEX_SAMPLE_C
1069
  { 462,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #462 = TEX_SAMPLE_C_G
1070
  { 463,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #463 = TEX_SAMPLE_C_L
1071
  { 464,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #464 = TEX_SAMPLE_C_LB
1072
  { 465,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #465 = TEX_SAMPLE_G
1073
  { 466,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #466 = TEX_SAMPLE_L
1074
  { 467,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #467 = TEX_SAMPLE_LB
1075
  { 468,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #468 = TEX_SET_GRADIENTS_H
1076
  { 469,  19, 1,  0,  1,  0, 0x2000ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #469 = TEX_SET_GRADIENTS_V
1077
  { 470,  4,  1,  0,  1,  0, 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #470 = TEX_VTX_CONSTBUF
1078
  { 471,  4,  1,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #471 = TEX_VTX_TEXBUF
1079
  { 472,  14, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #472 = TRUNC
1080
  { 473,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #473 = UINT_TO_FLT_eg
1081
  { 474,  14, 1,  0,  4,  0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #474 = UINT_TO_FLT_r600
1082
  { 475,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #475 = VTX_READ_128_cm
1083
  { 476,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #476 = VTX_READ_128_eg
1084
  { 477,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #477 = VTX_READ_16_cm
1085
  { 478,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #478 = VTX_READ_16_eg
1086
  { 479,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #479 = VTX_READ_32_cm
1087
  { 480,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #480 = VTX_READ_32_eg
1088
  { 481,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #481 = VTX_READ_64_cm
1089
  { 482,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #482 = VTX_READ_64_eg
1090
  { 483,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #483 = VTX_READ_8_cm
1091
  { 484,  4,  1,  0,  1,  0|(1ULL<<MCID::MayLoad), 0x1000ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #484 = VTX_READ_8_eg
1092
  { 485,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #485 = WHILE_LOOP_EG
1093
  { 486,  1,  0,  0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #486 = WHILE_LOOP_R600
1094
  { 487,  21, 1,  0,  3,  0|(1ULL<<MCID::Predicable), 0x4a00ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #487 = XOR_INT
1095
};
1096
1097
extern const char R600InstrNameData[] = {
1098
  /* 0 */ 'C', 'F', '_', 'T', 'C', '_', 'R', '6', '0', '0', 0,
1099
  /* 11 */ 'C', 'F', '_', 'V', 'C', '_', 'R', '6', '0', '0', 0,
1100
  /* 22 */ 'C', 'F', '_', 'E', 'N', 'D', '_', 'R', '6', '0', '0', 0,
1101
  /* 34 */ 'C', 'F', '_', 'E', 'L', 'S', 'E', '_', 'R', '6', '0', '0', 0,
1102
  /* 47 */ 'C', 'F', '_', 'P', 'U', 'S', 'H', '_', 'E', 'L', 'S', 'E', '_', 'R', '6', '0', '0', 0,
1103
  /* 65 */ 'C', 'F', '_', 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'R', '6', '0', '0', 0,
1104
  /* 82 */ 'F', 'N', 'E', 'G', '_', 'R', '6', '0', '0', 0,
1105
  /* 92 */ 'L', 'O', 'O', 'P', '_', 'B', 'R', 'E', 'A', 'K', '_', 'R', '6', '0', '0', 0,
1106
  /* 108 */ 'C', 'F', '_', 'J', 'U', 'M', 'P', '_', 'R', '6', '0', '0', 0,
1107
  /* 121 */ 'E', 'N', 'D', '_', 'L', 'O', 'O', 'P', '_', 'R', '6', '0', '0', 0,
1108
  /* 135 */ 'W', 'H', 'I', 'L', 'E', '_', 'L', 'O', 'O', 'P', '_', 'R', '6', '0', '0', 0,
1109
  /* 151 */ 'P', 'O', 'P', '_', 'R', '6', '0', '0', 0,
1110
  /* 160 */ 'F', 'A', 'B', 'S', '_', 'R', '6', '0', '0', 0,
1111
  /* 170 */ 'C', 'F', '_', 'C', 'A', 'L', 'L', '_', 'F', 'S', '_', 'R', '6', '0', '0', 0,
1112
  /* 186 */ 'D', 'O', 'T', '4', '_', 'r', '6', '0', '0', 0,
1113
  /* 196 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'r', '6', '0', '0', 0,
1114
  /* 208 */ 'L', 'O', 'G', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'r', '6', '0', '0', 0,
1115
  /* 225 */ 'R', 'E', 'C', 'I', 'P', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'r', '6', '0', '0', 0,
1116
  /* 244 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'r', '6', '0', '0', 0,
1117
  /* 267 */ 'C', 'N', 'D', 'E', '_', 'r', '6', '0', '0', 0,
1118
  /* 277 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1119
  /* 294 */ 'L', 'O', 'G', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1120
  /* 308 */ 'R', 'E', 'C', 'I', 'P', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1121
  /* 324 */ 'E', 'X', 'P', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1122
  /* 338 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'I', 'E', 'E', 'E', '_', 'r', '6', '0', '0', 0,
1123
  /* 358 */ 'C', 'N', 'D', 'G', 'E', '_', 'r', '6', '0', '0', 0,
1124
  /* 369 */ 'L', 'S', 'H', 'L', '_', 'r', '6', '0', '0', 0,
1125
  /* 379 */ 'S', 'I', 'N', '_', 'r', '6', '0', '0', 0,
1126
  /* 388 */ 'A', 'S', 'H', 'R', '_', 'r', '6', '0', '0', 0,
1127
  /* 398 */ 'L', 'S', 'H', 'R', '_', 'r', '6', '0', '0', 0,
1128
  /* 408 */ 'C', 'O', 'S', '_', 'r', '6', '0', '0', 0,
1129
  /* 417 */ 'C', 'N', 'D', 'G', 'T', '_', 'r', '6', '0', '0', 0,
1130
  /* 428 */ 'M', 'U', 'L', '_', 'L', 'I', 'T', '_', 'r', '6', '0', '0', 0,
1131
  /* 441 */ 'U', 'I', 'N', 'T', '_', 'T', 'O', '_', 'F', 'L', 'T', '_', 'r', '6', '0', '0', 0,
1132
  /* 458 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1133
  /* 474 */ 'M', 'U', 'L', 'L', 'O', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1134
  /* 490 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1135
  /* 507 */ 'R', 'E', 'C', 'I', 'P', '_', 'U', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1136
  /* 523 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1137
  /* 538 */ 'M', 'U', 'L', 'L', 'O', '_', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1138
  /* 553 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'I', 'N', 'T', '_', 'r', '6', '0', '0', 0,
1139
  /* 569 */ 'S', 'I', 'N', '_', 'r', '7', '0', '0', 0,
1140
  /* 578 */ 'C', 'O', 'S', '_', 'r', '7', '0', '0', 0,
1141
  /* 587 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
1142
  /* 596 */ 'S', 'E', 'T', 'G', 'E', '_', 'D', 'X', '1', '0', 0,
1143
  /* 607 */ 'S', 'E', 'T', 'N', 'E', '_', 'D', 'X', '1', '0', 0,
1144
  /* 618 */ 'S', 'E', 'T', 'E', '_', 'D', 'X', '1', '0', 0,
1145
  /* 628 */ 'M', 'I', 'N', '_', 'D', 'X', '1', '0', 0,
1146
  /* 637 */ 'S', 'E', 'T', 'G', 'T', '_', 'D', 'X', '1', '0', 0,
1147
  /* 648 */ 'M', 'A', 'X', '_', 'D', 'X', '1', '0', 0,
1148
  /* 657 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'L', 'O', 'A', 'D', '_', 'P', '0', 0,
1149
  /* 672 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'D', 'W', 'O', 'R', 'D', '3', '2', 0,
1150
  /* 690 */ 'M', 'O', 'V', '_', 'I', 'M', 'M', '_', 'F', '3', '2', 0,
1151
  /* 702 */ 'M', 'O', 'V', '_', 'I', 'M', 'M', '_', 'I', '3', '2', 0,
1152
  /* 714 */ 'F', 'L', 'T', '1', '6', '_', 'T', 'O', '_', 'F', 'L', 'T', '3', '2', 0,
1153
  /* 729 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', 'C', '_', 'f', '3', '2', 0,
1154
  /* 743 */ 'I', 'F', 'C', '_', 'f', '3', '2', 0,
1155
  /* 751 */ 'B', 'R', 'E', 'A', 'K', 'C', '_', 'f', '3', '2', 0,
1156
  /* 762 */ 'B', 'R', 'A', 'N', 'C', 'H', '_', 'C', 'O', 'N', 'D', '_', 'f', '3', '2', 0,
1157
  /* 778 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'f', '3', '2', 0,
1158
  /* 800 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'f', '3', '2', 0,
1159
  /* 816 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'f', '3', '2', 0,
1160
  /* 835 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'f', '3', '2', 0,
1161
  /* 858 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'f', '3', '2', 0,
1162
  /* 875 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'f', '3', '2', 0,
1163
  /* 895 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', 'C', '_', 'i', '3', '2', 0,
1164
  /* 909 */ 'I', 'F', 'C', '_', 'i', '3', '2', 0,
1165
  /* 917 */ 'B', 'R', 'E', 'A', 'K', 'C', '_', 'i', '3', '2', 0,
1166
  /* 928 */ 'B', 'R', 'A', 'N', 'C', 'H', '_', 'C', 'O', 'N', 'D', '_', 'i', '3', '2', 0,
1167
  /* 944 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'i', '3', '2', 0,
1168
  /* 966 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'i', '3', '2', 0,
1169
  /* 982 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'Z', '_', 'i', '3', '2', 0,
1170
  /* 1001 */ 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'i', '3', '2', 0,
1171
  /* 1024 */ 'I', 'F', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'i', '3', '2', 0,
1172
  /* 1041 */ 'B', 'R', 'E', 'A', 'K', '_', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'N', 'Z', '_', 'i', '3', '2', 0,
1173
  /* 1061 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
1174
  /* 1069 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
1175
  /* 1077 */ 'R', '6', '0', '0', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'E', 'L', 'T', '_', 'V', '2', 0,
1176
  /* 1097 */ 'R', '6', '0', '0', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'E', 'L', 'T', '_', 'V', '2', 0,
1177
  /* 1116 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'c', 'm', '2', '4', 0,
1178
  /* 1132 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'c', 'm', '2', '4', 0,
1179
  /* 1147 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'D', 'W', 'O', 'R', 'D', '6', '4', 0,
1180
  /* 1165 */ 'R', '6', '0', '0', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'E', 'L', 'T', '_', 'V', '4', 0,
1181
  /* 1185 */ 'R', '6', '0', '0', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'E', 'L', 'T', '_', 'V', '4', 0,
1182
  /* 1204 */ 'D', 'O', 'T', '_', '4', 0,
1183
  /* 1210 */ 'F', 'L', 'T', '3', '2', '_', 'T', 'O', '_', 'F', 'L', 'T', '1', '6', 0,
1184
  /* 1225 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'D', 'W', 'O', 'R', 'D', '1', '2', '8', 0,
1185
  /* 1244 */ 'G', '_', 'F', 'M', 'A', 0,
1186
  /* 1250 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', '_', 'L', 'B', 0,
1187
  /* 1266 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'L', 'B', 0,
1188
  /* 1280 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
1189
  /* 1287 */ 'G', '_', 'S', 'U', 'B', 0,
1190
  /* 1293 */ 'L', 'D', 'S', '_', 'S', 'U', 'B', 0,
1191
  /* 1301 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
1192
  /* 1317 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
1193
  /* 1329 */ 'E', 'N', 'D', 'F', 'U', 'N', 'C', 0,
1194
  /* 1337 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
1195
  /* 1347 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
1196
  /* 1365 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
1197
  /* 1373 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'T', 'R', 'U', 'N', 'C', 0,
1198
  /* 1394 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', 0,
1199
  /* 1407 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
1200
  /* 1418 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
1201
  /* 1429 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'V', 'E', 'C', '_', 'L', 'O', 'A', 'D', 0,
1202
  /* 1445 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
1203
  /* 1452 */ 'P', 'A', 'D', 0,
1204
  /* 1456 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
1205
  /* 1463 */ 'G', '_', 'A', 'D', 'D', 0,
1206
  /* 1469 */ 'L', 'D', 'S', '_', 'A', 'D', 'D', 0,
1207
  /* 1477 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
1208
  /* 1493 */ 'T', 'E', 'X', '_', 'L', 'D', 0,
1209
  /* 1500 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
1210
  /* 1517 */ 'G', '_', 'A', 'N', 'D', 0,
1211
  /* 1523 */ 'L', 'D', 'S', '_', 'A', 'N', 'D', 0,
1212
  /* 1531 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
1213
  /* 1547 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
1214
  /* 1560 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
1215
  /* 1569 */ 'J', 'U', 'M', 'P', '_', 'C', 'O', 'N', 'D', 0,
1216
  /* 1579 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
1217
  /* 1597 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
1218
  /* 1614 */ 'T', 'X', 'D', 0,
1219
  /* 1618 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
1220
  /* 1626 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
1221
  /* 1634 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
1222
  /* 1647 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
1223
  /* 1655 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
1224
  /* 1663 */ 'M', 'U', 'L', '_', 'I', 'E', 'E', 'E', 0,
1225
  /* 1672 */ 'S', 'G', 'E', 0,
1226
  /* 1676 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'E', 0,
1227
  /* 1687 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
1228
  /* 1694 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', 0,
1229
  /* 1705 */ 'R', 'N', 'D', 'N', 'E', 0,
1230
  /* 1711 */ 'S', 'N', 'E', 0,
1231
  /* 1715 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'N', 'E', 0,
1232
  /* 1726 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
1233
  /* 1739 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'P', 'U', 'S', 'H', '_', 'B', 'E', 'F', 'O', 'R', 'E', 0,
1234
  /* 1758 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
1235
  /* 1766 */ 'E', 'L', 'S', 'E', 0,
1236
  /* 1771 */ 'F', 'E', 'T', 'C', 'H', '_', 'C', 'L', 'A', 'U', 'S', 'E', 0,
1237
  /* 1784 */ 'A', 'L', 'U', '_', 'C', 'L', 'A', 'U', 'S', 'E', 0,
1238
  /* 1795 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'E', 0,
1239
  /* 1805 */ 'L', 'D', 'S', '_', 'B', 'Y', 'T', 'E', '_', 'W', 'R', 'I', 'T', 'E', 0,
1240
  /* 1820 */ 'M', 'A', 'S', 'K', '_', 'W', 'R', 'I', 'T', 'E', 0,
1241
  /* 1831 */ 'L', 'D', 'S', '_', 'W', 'R', 'I', 'T', 'E', 0,
1242
  /* 1841 */ 'L', 'D', 'S', '_', 'S', 'H', 'O', 'R', 'T', '_', 'W', 'R', 'I', 'T', 'E', 0,
1243
  /* 1857 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
1244
  /* 1867 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
1245
  /* 1882 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', 0,
1246
  /* 1898 */ 'G', '_', 'F', 'C', 'A', 'N', 'O', 'N', 'I', 'C', 'A', 'L', 'I', 'Z', 'E', 0,
1247
  /* 1914 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
1248
  /* 1932 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
1249
  /* 1950 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
1250
  /* 1965 */ 'E', 'N', 'D', 'I', 'F', 0,
1251
  /* 1971 */ 'T', 'E', 'X', '_', 'V', 'T', 'X', '_', 'C', 'O', 'N', 'S', 'T', 'B', 'U', 'F', 0,
1252
  /* 1988 */ 'T', 'E', 'X', '_', 'V', 'T', 'X', '_', 'T', 'E', 'X', 'B', 'U', 'F', 0,
1253
  /* 2003 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
1254
  /* 2010 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
1255
  /* 2025 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
1256
  /* 2039 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
1257
  /* 2053 */ 'C', 'F', '_', 'T', 'C', '_', 'E', 'G', 0,
1258
  /* 2062 */ 'C', 'F', '_', 'V', 'C', '_', 'E', 'G', 0,
1259
  /* 2071 */ 'C', 'F', '_', 'E', 'N', 'D', '_', 'E', 'G', 0,
1260
  /* 2081 */ 'C', 'F', '_', 'E', 'L', 'S', 'E', '_', 'E', 'G', 0,
1261
  /* 2092 */ 'C', 'F', '_', 'C', 'O', 'N', 'T', 'I', 'N', 'U', 'E', '_', 'E', 'G', 0,
1262
  /* 2107 */ 'C', 'F', '_', 'P', 'U', 'S', 'H', '_', 'E', 'G', 0,
1263
  /* 2118 */ 'L', 'O', 'O', 'P', '_', 'B', 'R', 'E', 'A', 'K', '_', 'E', 'G', 0,
1264
  /* 2132 */ 'C', 'F', '_', 'J', 'U', 'M', 'P', '_', 'E', 'G', 0,
1265
  /* 2143 */ 'E', 'N', 'D', '_', 'L', 'O', 'O', 'P', '_', 'E', 'G', 0,
1266
  /* 2155 */ 'W', 'H', 'I', 'L', 'E', '_', 'L', 'O', 'O', 'P', '_', 'E', 'G', 0,
1267
  /* 2169 */ 'P', 'O', 'P', '_', 'E', 'G', 0,
1268
  /* 2176 */ 'C', 'F', '_', 'C', 'A', 'L', 'L', '_', 'F', 'S', '_', 'E', 'G', 0,
1269
  /* 2190 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
1270
  /* 2207 */ 'L', 'D', 'S', '_', 'W', 'R', 'X', 'C', 'H', 'G', 0,
1271
  /* 2218 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
1272
  /* 2235 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
1273
  /* 2242 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
1274
  /* 2250 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', '_', 'G', 0,
1275
  /* 2265 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'G', 0,
1276
  /* 2278 */ 'B', 'R', 'A', 'N', 'C', 'H', 0,
1277
  /* 2285 */ 'E', 'N', 'D', 'S', 'W', 'I', 'T', 'C', 'H', 0,
1278
  /* 2295 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
1279
  /* 2303 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
1280
  /* 2311 */ 'T', 'E', 'X', '_', 'G', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'H', 0,
1281
  /* 2331 */ 'T', 'E', 'X', '_', 'S', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'H', 0,
1282
  /* 2351 */ 'G', '_', 'P', 'H', 'I', 0,
1283
  /* 2357 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
1284
  /* 2366 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
1285
  /* 2375 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'B', 'R', 'E', 'A', 'K', 0,
1286
  /* 2388 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
1287
  /* 2399 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
1288
  /* 2408 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
1289
  /* 2418 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
1290
  /* 2427 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
1291
  /* 2444 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
1292
  /* 2464 */ 'G', '_', 'S', 'H', 'L', 0,
1293
  /* 2470 */ 'G', '_', 'F', 'C', 'E', 'I', 'L', 0,
1294
  /* 2478 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
1295
  /* 2498 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
1296
  /* 2525 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
1297
  /* 2546 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
1298
  /* 2558 */ 'K', 'I', 'L', 'L', 0,
1299
  /* 2563 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
1300
  /* 2570 */ 'G', '_', 'M', 'U', 'L', 0,
1301
  /* 2576 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'C', '_', 'L', 0,
1302
  /* 2591 */ 'T', 'E', 'X', '_', 'S', 'A', 'M', 'P', 'L', 'E', '_', 'L', 0,
1303
  /* 2604 */ 'C', 'F', '_', 'E', 'N', 'D', '_', 'C', 'M', 0,
1304
  /* 2614 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
1305
  /* 2621 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
1306
  /* 2628 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
1307
  /* 2635 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
1308
  /* 2645 */ 'D', 'U', 'M', 'M', 'Y', '_', 'C', 'H', 'A', 'I', 'N', 0,
1309
  /* 2657 */ 'E', 'N', 'D', 'M', 'A', 'I', 'N', 0,
1310
  /* 2665 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
1311
  /* 2682 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
1312
  /* 2698 */ 'G', '_', 'F', 'S', 'I', 'N', 0,
1313
  /* 2705 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
1314
  /* 2721 */ 'R', 'E', 'T', 'U', 'R', 'N', 0,
1315
  /* 2728 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'S', 'U', 'B', '_', 'R', 'T', 'N', 0,
1316
  /* 2748 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'U', 'B', '_', 'R', 'T', 'N', 0,
1317
  /* 2767 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'D', 'D', '_', 'R', 'T', 'N', 0,
1318
  /* 2786 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'N', 'D', '_', 'R', 'T', 'N', 0,
1319
  /* 2805 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'O', 'R', '_', 'R', 'T', 'N', 0,
1320
  /* 2824 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'O', 'R', '_', 'R', 'T', 'N', 0,
1321
  /* 2842 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'D', 'E', 'C', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1322
  /* 2866 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'I', 'N', 'C', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1323
  /* 2890 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1324
  /* 2914 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1325
  /* 2938 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1326
  /* 2965 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1327
  /* 2989 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1328
  /* 3012 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', '_', 'R', 'T', 'N', 0,
1329
  /* 3035 */ 'R', 'E', 'T', 'D', 'Y', 'N', 0,
1330
  /* 3042 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
1331
  /* 3050 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
1332
  /* 3058 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
1333
  /* 3066 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
1334
  /* 3074 */ 'T', 'E', 'X', '_', 'G', 'E', 'T', '_', 'T', 'E', 'X', 'T', 'U', 'R', 'E', '_', 'R', 'E', 'S', 'I', 'N', 'F', 'O', 0,
1335
  /* 3098 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
1336
  /* 3106 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
1337
  /* 3114 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
1338
  /* 3123 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
1339
  /* 3131 */ 'G', '_', 'G', 'E', 'P', 0,
1340
  /* 3137 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
1341
  /* 3146 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
1342
  /* 3155 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
1343
  /* 3162 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
1344
  /* 3169 */ 'J', 'U', 'M', 'P', 0,
1345
  /* 3174 */ 'E', 'N', 'D', 'L', 'O', 'O', 'P', 0,
1346
  /* 3182 */ 'W', 'H', 'I', 'L', 'E', 'L', 'O', 'O', 'P', 0,
1347
  /* 3192 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
1348
  /* 3200 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
1349
  /* 3213 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
1350
  /* 3225 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
1351
  /* 3232 */ 'G', '_', 'B', 'R', 0,
1352
  /* 3237 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', '_', 'B', 'R', 0,
1353
  /* 3250 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
1354
  /* 3263 */ 'M', 'O', 'V', '_', 'I', 'M', 'M', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'A', 'D', 'D', 'R', 0,
1355
  /* 3283 */ 'G', 'R', 'O', 'U', 'P', '_', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0,
1356
  /* 3297 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'E', 'L', 'S', 'E', '_', 'A', 'F', 'T', 'E', 'R', 0,
1357
  /* 3315 */ 'C', 'F', '_', 'A', 'L', 'U', '_', 'P', 'O', 'P', '_', 'A', 'F', 'T', 'E', 'R', 0,
1358
  /* 3332 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
1359
  /* 3357 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
1360
  /* 3364 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
1361
  /* 3371 */ 'R', 'A', 'T', '_', 'M', 'S', 'K', 'O', 'R', 0,
1362
  /* 3381 */ 'G', '_', 'F', 'F', 'L', 'O', 'O', 'R', 0,
1363
  /* 3390 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
1364
  /* 3405 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
1365
  /* 3422 */ 'G', '_', 'X', 'O', 'R', 0,
1366
  /* 3428 */ 'L', 'D', 'S', '_', 'X', 'O', 'R', 0,
1367
  /* 3436 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
1368
  /* 3452 */ 'G', '_', 'O', 'R', 0,
1369
  /* 3457 */ 'L', 'D', 'S', '_', 'O', 'R', 0,
1370
  /* 3464 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
1371
  /* 3479 */ 'T', 'E', 'X', '_', 'L', 'D', 'P', 'T', 'R', 0,
1372
  /* 3489 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
1373
  /* 3500 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
1374
  /* 3507 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1375
  /* 3524 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1376
  /* 3539 */ 'L', 'I', 'T', 'E', 'R', 'A', 'L', 'S', 0,
1377
  /* 3548 */ 'G', '_', 'F', 'C', 'O', 'S', 0,
1378
  /* 3555 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0,
1379
  /* 3572 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
1380
  /* 3589 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
1381
  /* 3619 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
1382
  /* 3646 */ 'F', 'R', 'A', 'C', 'T', 0,
1383
  /* 3652 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
1384
  /* 3662 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
1385
  /* 3671 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
1386
  /* 3684 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'S', 'U', 'B', '_', 'N', 'O', 'R', 'E', 'T', 0,
1387
  /* 3706 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'U', 'B', '_', 'N', 'O', 'R', 'E', 'T', 0,
1388
  /* 3727 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'D', 'D', '_', 'N', 'O', 'R', 'E', 'T', 0,
1389
  /* 3748 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'A', 'N', 'D', '_', 'N', 'O', 'R', 'E', 'T', 0,
1390
  /* 3769 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'O', 'R', '_', 'N', 'O', 'R', 'E', 'T', 0,
1391
  /* 3790 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'O', 'R', '_', 'N', 'O', 'R', 'E', 'T', 0,
1392
  /* 3810 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'D', 'E', 'C', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1393
  /* 3836 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'I', 'N', 'C', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1394
  /* 3862 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1395
  /* 3888 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1396
  /* 3914 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1397
  /* 3943 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'X', 'C', 'H', 'G', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1398
  /* 3969 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1399
  /* 3994 */ 'R', 'A', 'T', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', '_', 'N', 'O', 'R', 'E', 'T', 0,
1400
  /* 4019 */ 'L', 'D', 'S', '_', 'S', 'U', 'B', '_', 'R', 'E', 'T', 0,
1401
  /* 4031 */ 'L', 'D', 'S', '_', 'U', 'B', 'Y', 'T', 'E', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1402
  /* 4050 */ 'L', 'D', 'S', '_', 'B', 'Y', 'T', 'E', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1403
  /* 4068 */ 'L', 'D', 'S', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1404
  /* 4081 */ 'L', 'D', 'S', '_', 'U', 'S', 'H', 'O', 'R', 'T', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1405
  /* 4101 */ 'L', 'D', 'S', '_', 'S', 'H', 'O', 'R', 'T', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'T', 0,
1406
  /* 4120 */ 'L', 'D', 'S', '_', 'A', 'D', 'D', '_', 'R', 'E', 'T', 0,
1407
  /* 4132 */ 'L', 'D', 'S', '_', 'A', 'N', 'D', '_', 'R', 'E', 'T', 0,
1408
  /* 4144 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
1409
  /* 4158 */ 'L', 'D', 'S', '_', 'W', 'R', 'X', 'C', 'H', 'G', '_', 'R', 'E', 'T', 0,
1410
  /* 4173 */ 'L', 'D', 'S', '_', 'X', 'O', 'R', '_', 'R', 'E', 'T', 0,
1411
  /* 4185 */ 'L', 'D', 'S', '_', 'O', 'R', '_', 'R', 'E', 'T', 0,
1412
  /* 4196 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1413
  /* 4213 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1414
  /* 4230 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1415
  /* 4246 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', '_', 'R', 'E', 'T', 0,
1416
  /* 4262 */ 'L', 'D', 'S', '_', 'C', 'M', 'P', 'S', 'T', '_', 'R', 'E', 'T', 0,
1417
  /* 4276 */ 'I', 'F', '_', 'P', 'R', 'E', 'D', 'I', 'C', 'A', 'T', 'E', '_', 'S', 'E', 'T', 0,
1418
  /* 4293 */ 'K', 'I', 'L', 'L', 'G', 'T', 0,
1419
  /* 4300 */ 'S', 'G', 'T', 0,
1420
  /* 4304 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'T', 0,
1421
  /* 4315 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
1422
  /* 4339 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1423
  /* 4360 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1424
  /* 4380 */ 'D', 'E', 'F', 'A', 'U', 'L', 'T', 0,
1425
  /* 4388 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1426
  /* 4400 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1427
  /* 4411 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
1428
  /* 4422 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
1429
  /* 4433 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
1430
  /* 4444 */ 'S', 'U', 'B', 'B', '_', 'U', 'I', 'N', 'T', 0,
1431
  /* 4454 */ 'A', 'D', 'D', 'C', '_', 'U', 'I', 'N', 'T', 0,
1432
  /* 4464 */ 'S', 'E', 'T', 'G', 'E', '_', 'U', 'I', 'N', 'T', 0,
1433
  /* 4475 */ 'F', 'F', 'B', 'H', '_', 'U', 'I', 'N', 'T', 0,
1434
  /* 4485 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'U', 'I', 'N', 'T', 0,
1435
  /* 4498 */ 'S', 'E', 'T', 'G', 'T', '_', 'U', 'I', 'N', 'T', 0,
1436
  /* 4509 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'U', 'I', 'N', 'T', 0,
1437
  /* 4522 */ 'S', 'U', 'B', '_', 'I', 'N', 'T', 0,
1438
  /* 4530 */ 'A', 'D', 'D', '_', 'I', 'N', 'T', 0,
1439
  /* 4538 */ 'A', 'N', 'D', '_', 'I', 'N', 'T', 0,
1440
  /* 4546 */ 'C', 'N', 'D', 'E', '_', 'I', 'N', 'T', 0,
1441
  /* 4555 */ 'C', 'N', 'D', 'G', 'E', '_', 'I', 'N', 'T', 0,
1442
  /* 4565 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'E', '_', 'I', 'N', 'T', 0,
1443
  /* 4580 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'N', 'E', '_', 'I', 'N', 'T', 0,
1444
  /* 4595 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'E', '_', 'I', 'N', 'T', 0,
1445
  /* 4609 */ 'F', 'F', 'B', 'L', '_', 'I', 'N', 'T', 0,
1446
  /* 4618 */ 'L', 'D', 'S', '_', 'M', 'I', 'N', '_', 'I', 'N', 'T', 0,
1447
  /* 4630 */ 'X', 'O', 'R', '_', 'I', 'N', 'T', 0,
1448
  /* 4638 */ 'C', 'N', 'D', 'G', 'T', '_', 'I', 'N', 'T', 0,
1449
  /* 4648 */ 'P', 'R', 'E', 'D', '_', 'S', 'E', 'T', 'G', 'T', '_', 'I', 'N', 'T', 0,
1450
  /* 4663 */ 'B', 'C', 'N', 'T', '_', 'I', 'N', 'T', 0,
1451
  /* 4672 */ 'N', 'O', 'T', '_', 'I', 'N', 'T', 0,
1452
  /* 4680 */ 'L', 'D', 'S', '_', 'M', 'A', 'X', '_', 'I', 'N', 'T', 0,
1453
  /* 4692 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
1454
  /* 4702 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
1455
  /* 4717 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
1456
  /* 4726 */ 'G', '_', 'F', 'S', 'Q', 'R', 'T', 0,
1457
  /* 4734 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
1458
  /* 4744 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
1459
  /* 4761 */ 'L', 'D', 'S', '_', 'C', 'M', 'P', 'S', 'T', 0,
1460
  /* 4771 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
1461
  /* 4779 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
1462
  /* 4786 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
1463
  /* 4795 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
1464
  /* 4802 */ 'C', 'F', '_', 'A', 'L', 'U', 0,
1465
  /* 4809 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
1466
  /* 4816 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
1467
  /* 4823 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
1468
  /* 4830 */ 'M', 'O', 'V', 0,
1469
  /* 4834 */ 'T', 'E', 'X', '_', 'G', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'V', 0,
1470
  /* 4854 */ 'T', 'E', 'X', '_', 'S', 'E', 'T', '_', 'G', 'R', 'A', 'D', 'I', 'E', 'N', 'T', 'S', '_', 'V', 0,
1471
  /* 4874 */ 'T', 'X', 'D', '_', 'S', 'H', 'A', 'D', 'O', 'W', 0,
1472
  /* 4885 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
1473
  /* 4892 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'Z', 'W', 0,
1474
  /* 4902 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'P', 'A', 'I', 'R', '_', 'Z', 'W', 0,
1475
  /* 4917 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
1476
  /* 4934 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
1477
  /* 4950 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
1478
  /* 4964 */ 'P', 'R', 'E', 'D', '_', 'X', 0,
1479
  /* 4971 */ 'C', 'O', 'N', 'S', 'T', '_', 'C', 'O', 'P', 'Y', 0,
1480
  /* 4982 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'X', 'Y', 0,
1481
  /* 4992 */ 'I', 'N', 'T', 'E', 'R', 'P', '_', 'P', 'A', 'I', 'R', '_', 'X', 'Y', 0,
1482
  /* 5007 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
1483
  /* 5014 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
1484
  /* 5021 */ 'R', '6', '0', '0', '_', 'R', 'e', 'g', 'i', 's', 't', 'e', 'r', 'L', 'o', 'a', 'd', 0,
1485
  /* 5039 */ 'R', '6', '0', '0', '_', 'R', 'e', 'g', 'i', 's', 't', 'e', 'r', 'S', 't', 'o', 'r', 'e', 0,
1486
  /* 5058 */ 'R', '6', '0', '0', '_', 'E', 'x', 'p', 'o', 'r', 't', 'B', 'u', 'f', 0,
1487
  /* 5073 */ 'E', 'G', '_', 'E', 'x', 'p', 'o', 'r', 't', 'B', 'u', 'f', 0,
1488
  /* 5086 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '3', '2', '_', 'e', 'g', 0,
1489
  /* 5101 */ 'R', 'A', 'T', '_', 'W', 'R', 'I', 'T', 'E', '_', 'C', 'A', 'C', 'H', 'E', 'L', 'E', 'S', 'S', '_', '3', '2', '_', 'e', 'g', 0,
1490
  /* 5127 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'U', 'I', 'N', 'T', '2', '4', '_', 'e', 'g', 0,
1491
  /* 5144 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '2', '4', '_', 'e', 'g', 0,
1492
  /* 5160 */ 'M', 'U', 'L', '_', 'U', 'I', 'N', 'T', '2', '4', '_', 'e', 'g', 0,
1493
  /* 5174 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '6', '4', '_', 'e', 'g', 0,
1494
  /* 5189 */ 'R', 'A', 'T', '_', 'W', 'R', 'I', 'T', 'E', '_', 'C', 'A', 'C', 'H', 'E', 'L', 'E', 'S', 'S', '_', '6', '4', '_', 'e', 'g', 0,
1495
  /* 5215 */ 'D', 'O', 'T', '4', '_', 'e', 'g', 0,
1496
  /* 5223 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '6', '_', 'e', 'g', 0,
1497
  /* 5238 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '2', '8', '_', 'e', 'g', 0,
1498
  /* 5254 */ 'R', 'A', 'T', '_', 'W', 'R', 'I', 'T', 'E', '_', 'C', 'A', 'C', 'H', 'E', 'L', 'E', 'S', 'S', '_', '1', '2', '8', '_', 'e', 'g', 0,
1499
  /* 5281 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '8', '_', 'e', 'g', 0,
1500
  /* 5295 */ 'F', 'M', 'A', '_', 'e', 'g', 0,
1501
  /* 5302 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'e', 'g', 0,
1502
  /* 5312 */ 'L', 'O', 'G', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'e', 'g', 0,
1503
  /* 5327 */ 'R', 'E', 'C', 'I', 'P', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'e', 'g', 0,
1504
  /* 5344 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'e', 'g', 0,
1505
  /* 5365 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'e', 'g', 0,
1506
  /* 5384 */ 'C', 'N', 'D', 'E', '_', 'e', 'g', 0,
1507
  /* 5392 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1508
  /* 5407 */ 'L', 'O', 'G', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1509
  /* 5419 */ 'R', 'E', 'C', 'I', 'P', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1510
  /* 5433 */ 'E', 'X', 'P', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1511
  /* 5445 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'I', 'E', 'E', 'E', '_', 'e', 'g', 0,
1512
  /* 5463 */ 'C', 'N', 'D', 'G', 'E', '_', 'e', 'g', 0,
1513
  /* 5472 */ 'L', 'S', 'H', 'L', '_', 'e', 'g', 0,
1514
  /* 5480 */ 'S', 'I', 'N', '_', 'e', 'g', 0,
1515
  /* 5487 */ 'A', 'S', 'H', 'R', '_', 'e', 'g', 0,
1516
  /* 5495 */ 'L', 'S', 'H', 'R', '_', 'e', 'g', 0,
1517
  /* 5503 */ 'C', 'O', 'S', '_', 'e', 'g', 0,
1518
  /* 5510 */ 'C', 'N', 'D', 'G', 'T', '_', 'e', 'g', 0,
1519
  /* 5519 */ 'M', 'U', 'L', '_', 'L', 'I', 'T', '_', 'e', 'g', 0,
1520
  /* 5530 */ 'U', 'I', 'N', 'T', '_', 'T', 'O', '_', 'F', 'L', 'T', '_', 'e', 'g', 0,
1521
  /* 5545 */ 'B', 'F', 'E', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1522
  /* 5557 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1523
  /* 5571 */ 'M', 'U', 'L', 'L', 'O', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1524
  /* 5585 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1525
  /* 5600 */ 'R', 'E', 'C', 'I', 'P', '_', 'U', 'I', 'N', 'T', '_', 'e', 'g', 0,
1526
  /* 5614 */ 'M', 'O', 'V', 'A', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1527
  /* 5626 */ 'B', 'F', 'E', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1528
  /* 5637 */ 'B', 'F', 'I', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1529
  /* 5648 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1530
  /* 5661 */ 'B', 'F', 'M', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1531
  /* 5672 */ 'B', 'I', 'T', '_', 'A', 'L', 'I', 'G', 'N', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1532
  /* 5689 */ 'M', 'U', 'L', 'L', 'O', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1533
  /* 5702 */ 'F', 'L', 'T', '_', 'T', 'O', '_', 'I', 'N', 'T', '_', 'e', 'g', 0,
1534
  /* 5716 */ 'C', 'U', 'B', 'E', '_', 'r', '6', '0', '0', '_', 'r', 'e', 'a', 'l', 0,
1535
  /* 5731 */ 'C', 'U', 'B', 'E', '_', 'e', 'g', '_', 'r', 'e', 'a', 'l', 0,
1536
  /* 5744 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '3', '2', '_', 'c', 'm', 0,
1537
  /* 5759 */ 'M', 'U', 'L', 'A', 'D', 'D', '_', 'I', 'N', 'T', '2', '4', '_', 'c', 'm', 0,
1538
  /* 5775 */ 'M', 'U', 'L', '_', 'I', 'N', 'T', '2', '4', '_', 'c', 'm', 0,
1539
  /* 5788 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '6', '4', '_', 'c', 'm', 0,
1540
  /* 5803 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '6', '_', 'c', 'm', 0,
1541
  /* 5818 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '1', '2', '8', '_', 'c', 'm', 0,
1542
  /* 5834 */ 'V', 'T', 'X', '_', 'R', 'E', 'A', 'D', '_', '8', '_', 'c', 'm', 0,
1543
  /* 5848 */ 'R', 'E', 'C', 'I', 'P', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'c', 'm', 0,
1544
  /* 5865 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'C', 'L', 'A', 'M', 'P', 'E', 'D', '_', 'c', 'm', 0,
1545
  /* 5886 */ 'R', 'A', 'T', '_', 'S', 'T', 'O', 'R', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'c', 'm', 0,
1546
  /* 5905 */ 'L', 'O', 'G', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1547
  /* 5917 */ 'R', 'E', 'C', 'I', 'P', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1548
  /* 5931 */ 'E', 'X', 'P', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1549
  /* 5943 */ 'R', 'E', 'C', 'I', 'P', 'S', 'Q', 'R', 'T', '_', 'I', 'E', 'E', 'E', '_', 'c', 'm', 0,
1550
  /* 5961 */ 'S', 'I', 'N', '_', 'c', 'm', 0,
1551
  /* 5968 */ 'C', 'O', 'S', '_', 'c', 'm', 0,
1552
  /* 5975 */ 'M', 'U', 'L', 'H', 'I', '_', 'U', 'I', 'N', 'T', '_', 'c', 'm', 0,
1553
  /* 5989 */ 'M', 'U', 'L', 'L', 'O', '_', 'U', 'I', 'N', 'T', '_', 'c', 'm', 0,
1554
  /* 6003 */ 'M', 'U', 'L', 'H', 'I', '_', 'I', 'N', 'T', '_', 'c', 'm', 0,
1555
  /* 6016 */ 'M', 'U', 'L', 'L', 'O', '_', 'I', 'N', 'T', '_', 'c', 'm', 0,
1556
  /* 6029 */ 'C', 'U', 'B', 'E', '_', 'r', '6', '0', '0', '_', 'p', 's', 'e', 'u', 'd', 'o', 0,
1557
  /* 6046 */ 'C', 'U', 'B', 'E', '_', 'e', 'g', '_', 'p', 's', 'e', 'u', 'd', 'o', 0,
1558
  /* 6061 */ 'R', '6', '0', '0', '_', 'E', 'x', 'p', 'o', 'r', 't', 'S', 'w', 'z', 0,
1559
  /* 6076 */ 'E', 'G', '_', 'E', 'x', 'p', 'o', 'r', 't', 'S', 'w', 'z', 0,
1560
};
1561
1562
extern const unsigned R600InstrNameIndices[] = {
1563
    2353U, 2635U, 3237U, 2705U, 2418U, 2399U, 2427U, 2558U, 
1564
    2010U, 2025U, 1952U, 2039U, 3572U, 1857U, 2408U, 1634U, 
1565
    4977U, 1687U, 4702U, 1547U, 3114U, 2546U, 4422U, 1597U, 
1566
    4411U, 1726U, 3213U, 3200U, 3332U, 4144U, 4315U, 2478U, 
1567
    2525U, 2498U, 2444U, 1463U, 1287U, 2570U, 4816U, 4823U, 
1568
    2621U, 2628U, 1517U, 3452U, 3422U, 1950U, 2351U, 4950U, 
1569
    1867U, 3652U, 3507U, 4717U, 3524U, 3390U, 1373U, 3555U, 
1570
    4433U, 3489U, 4734U, 1347U, 1579U, 1445U, 1407U, 1418U, 
1571
    1758U, 3589U, 2190U, 2218U, 1477U, 1301U, 1531U, 1500U, 
1572
    3464U, 3436U, 4934U, 2682U, 4917U, 2665U, 1560U, 3671U, 
1573
    1317U, 3619U, 4786U, 1365U, 4400U, 4388U, 4692U, 2242U, 
1574
    4779U, 4795U, 2464U, 3364U, 3357U, 3162U, 3155U, 3662U, 
1575
    3066U, 1655U, 3050U, 1626U, 3058U, 1647U, 3042U, 1618U, 
1576
    3106U, 3098U, 2303U, 2295U, 1456U, 1280U, 2563U, 1244U, 
1577
    4809U, 2614U, 4885U, 3225U, 1069U, 2235U, 1061U, 587U, 
1578
    2003U, 4771U, 1337U, 2357U, 2366U, 3137U, 3146U, 3500U, 
1579
    1898U, 3131U, 2388U, 3232U, 4360U, 4339U, 3405U, 5014U, 
1580
    1932U, 5007U, 1914U, 3192U, 3123U, 2470U, 3548U, 2698U, 
1581
    4726U, 3381U, 4744U, 3250U, 2278U, 762U, 928U, 2382U, 
1582
    751U, 917U, 875U, 1041U, 816U, 982U, 4971U, 1889U, 
1583
    729U, 895U, 835U, 1001U, 778U, 944U, 6046U, 6029U, 
1584
    4380U, 1204U, 2645U, 1766U, 1556U, 1329U, 1965U, 3174U, 
1585
    2657U, 2285U, 160U, 82U, 1332U, 743U, 909U, 858U, 
1586
    1024U, 800U, 966U, 4276U, 3169U, 1569U, 1820U, 690U, 
1587
    3263U, 702U, 4964U, 1077U, 1165U, 1097U, 1185U, 5021U, 
1588
    5039U, 3035U, 2721U, 1614U, 4874U, 3182U, 1459U, 4454U, 
1589
    4530U, 1784U, 4538U, 5487U, 388U, 4663U, 5626U, 5545U, 
1590
    5637U, 5661U, 5672U, 2473U, 4802U, 2375U, 1882U, 3297U, 
1591
    3315U, 1739U, 2176U, 170U, 2092U, 65U, 2081U, 34U, 
1592
    2604U, 2071U, 22U, 2132U, 108U, 2107U, 47U, 2053U, 
1593
    0U, 2062U, 11U, 4546U, 5384U, 267U, 4555U, 5463U, 
1594
    358U, 4638U, 5510U, 417U, 5968U, 5503U, 408U, 578U, 
1595
    5731U, 5716U, 5215U, 186U, 5073U, 6076U, 2143U, 121U, 
1596
    5931U, 5433U, 324U, 1771U, 4475U, 4609U, 3384U, 714U, 
1597
    1210U, 5702U, 553U, 5585U, 490U, 5295U, 3646U, 3283U, 
1598
    657U, 4992U, 4902U, 1429U, 4982U, 4892U, 5531U, 442U, 
1599
    4293U, 1469U, 4120U, 1523U, 4132U, 4050U, 1805U, 4761U, 
1600
    4262U, 4680U, 4246U, 4509U, 4213U, 4618U, 4230U, 4485U, 
1601
    4196U, 3457U, 4185U, 4068U, 4101U, 1841U, 1293U, 4019U, 
1602
    4031U, 4081U, 1831U, 2207U, 4158U, 3428U, 4173U, 3539U, 
1603
    5312U, 208U, 5905U, 5407U, 294U, 2118U, 92U, 5472U, 
1604
    369U, 5495U, 398U, 4930U, 648U, 4684U, 4513U, 2678U, 
1605
    628U, 4622U, 4489U, 4830U, 5614U, 2566U, 5392U, 277U, 
1606
    5759U, 5127U, 5302U, 196U, 6003U, 1132U, 5648U, 523U, 
1607
    5144U, 5975U, 1116U, 5557U, 458U, 6016U, 5689U, 538U, 
1608
    5989U, 5571U, 474U, 1663U, 5775U, 5519U, 428U, 5160U, 
1609
    4672U, 4631U, 1452U, 2169U, 151U, 1795U, 4595U, 1676U, 
1610
    4565U, 4304U, 4648U, 1715U, 4580U, 5058U, 6061U, 3727U, 
1611
    2767U, 3748U, 2786U, 3914U, 2938U, 3810U, 2842U, 3836U, 
1612
    2866U, 3994U, 3012U, 3888U, 2914U, 3969U, 2989U, 3862U, 
1613
    2890U, 3790U, 2824U, 3684U, 2728U, 3706U, 2748U, 3943U, 
1614
    2965U, 3769U, 2805U, 3371U, 1225U, 672U, 1147U, 5886U, 
1615
    5365U, 5254U, 5101U, 5189U, 5865U, 5344U, 244U, 5943U, 
1616
    5445U, 338U, 5848U, 5327U, 225U, 5917U, 5419U, 308U, 
1617
    5600U, 507U, 1705U, 1800U, 618U, 4600U, 596U, 4570U, 
1618
    4464U, 637U, 4653U, 4498U, 607U, 4585U, 1672U, 4300U, 
1619
    5961U, 5480U, 379U, 569U, 1711U, 4444U, 4522U, 2311U, 
1620
    4834U, 3074U, 1493U, 3479U, 1694U, 1394U, 2250U, 2576U, 
1621
    1250U, 2265U, 2591U, 1266U, 2331U, 4854U, 1971U, 1988U, 
1622
    1341U, 5530U, 441U, 5818U, 5238U, 5803U, 5223U, 5744U, 
1623
    5086U, 5788U, 5174U, 5834U, 5281U, 2155U, 135U, 4630U, 
1624
};
1625
1626
292
static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
1627
292
  II->InitMCInstrInfo(R600Insts, R600InstrNameIndices, R600InstrNameData, 488);
1628
292
}
1629
1630
} // end llvm namespace
1631
#endif // GET_INSTRINFO_MC_DESC
1632
1633
#ifdef GET_INSTRINFO_HEADER
1634
#undef GET_INSTRINFO_HEADER
1635
namespace llvm {
1636
struct R600GenInstrInfo : public TargetInstrInfo {
1637
  explicit R600GenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
1638
285
  ~R600GenInstrInfo() override = default;
1639
1640
};
1641
} // end llvm namespace
1642
#endif // GET_INSTRINFO_HEADER
1643
1644
#ifdef GET_INSTRINFO_HELPER_DECLS
1645
#undef GET_INSTRINFO_HELPER_DECLS
1646
1647
1648
#endif // GET_INSTRINFO_HELPER_DECLS
1649
1650
#ifdef GET_INSTRINFO_HELPERS
1651
#undef GET_INSTRINFO_HELPERS
1652
1653
#endif // GET_INSTRINFO_HELPERS
1654
1655
#ifdef GET_INSTRINFO_CTOR_DTOR
1656
#undef GET_INSTRINFO_CTOR_DTOR
1657
namespace llvm {
1658
extern const MCInstrDesc R600Insts[];
1659
extern const unsigned R600InstrNameIndices[];
1660
extern const char R600InstrNameData[];
1661
R600GenInstrInfo::R600GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
1662
286
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1663
286
  InitMCInstrInfo(R600Insts, R600InstrNameIndices, R600InstrNameData, 488);
1664
286
}
1665
} // end llvm namespace
1666
#endif // GET_INSTRINFO_CTOR_DTOR
1667
1668
#ifdef GET_INSTRINFO_OPERAND_ENUM
1669
#undef GET_INSTRINFO_OPERAND_ENUM
1670
namespace llvm {
1671
namespace R600 {
1672
namespace OpName {
1673
enum {
1674
  ADDR = 98,
1675
  COUNT = 105,
1676
  Enabled = 106,
1677
  KCACHE_ADDR0 = 103,
1678
  KCACHE_ADDR1 = 104,
1679
  KCACHE_BANK0 = 99,
1680
  KCACHE_BANK1 = 100,
1681
  KCACHE_MODE0 = 101,
1682
  KCACHE_MODE1 = 102,
1683
  addr = 72,
1684
  bank_swizzle = 93,
1685
  chan = 73,
1686
  clamp = 80,
1687
  clamp_W = 58,
1688
  clamp_X = 7,
1689
  clamp_Y = 24,
1690
  clamp_Z = 41,
1691
  dst = 0,
1692
  dst_rel = 79,
1693
  dst_rel_W = 57,
1694
  dst_rel_X = 6,
1695
  dst_rel_Y = 23,
1696
  dst_rel_Z = 40,
1697
  last = 90,
1698
  literal = 92,
1699
  literal0 = 70,
1700
  literal1 = 71,
1701
  omod = 78,
1702
  omod_W = 56,
1703
  omod_X = 5,
1704
  omod_Y = 22,
1705
  omod_Z = 39,
1706
  pred_sel = 91,
1707
  pred_sel_W = 69,
1708
  pred_sel_X = 18,
1709
  pred_sel_Y = 35,
1710
  pred_sel_Z = 52,
1711
  src0 = 1,
1712
  src0_W = 59,
1713
  src0_X = 8,
1714
  src0_Y = 25,
1715
  src0_Z = 42,
1716
  src0_abs = 83,
1717
  src0_abs_W = 62,
1718
  src0_abs_X = 11,
1719
  src0_abs_Y = 28,
1720
  src0_abs_Z = 45,
1721
  src0_neg = 81,
1722
  src0_neg_W = 60,
1723
  src0_neg_X = 9,
1724
  src0_neg_Y = 26,
1725
  src0_neg_Z = 43,
1726
  src0_rel = 82,
1727
  src0_rel_W = 61,
1728
  src0_rel_X = 10,
1729
  src0_rel_Y = 27,
1730
  src0_rel_Z = 44,
1731
  src0_sel = 84,
1732
  src0_sel_W = 63,
1733
  src0_sel_X = 12,
1734
  src0_sel_Y = 29,
1735
  src0_sel_Z = 46,
1736
  src1 = 85,
1737
  src1_W = 64,
1738
  src1_X = 13,
1739
  src1_Y = 30,
1740
  src1_Z = 47,
1741
  src1_abs = 88,
1742
  src1_abs_W = 67,
1743
  src1_abs_X = 16,
1744
  src1_abs_Y = 33,
1745
  src1_abs_Z = 50,
1746
  src1_neg = 86,
1747
  src1_neg_W = 65,
1748
  src1_neg_X = 14,
1749
  src1_neg_Y = 31,
1750
  src1_neg_Z = 48,
1751
  src1_rel = 87,
1752
  src1_rel_W = 66,
1753
  src1_rel_X = 15,
1754
  src1_rel_Y = 32,
1755
  src1_rel_Z = 49,
1756
  src1_sel = 89,
1757
  src1_sel_W = 68,
1758
  src1_sel_X = 17,
1759
  src1_sel_Y = 34,
1760
  src1_sel_Z = 51,
1761
  src2 = 94,
1762
  src2_neg = 95,
1763
  src2_rel = 96,
1764
  src2_sel = 97,
1765
  update_exec_mask = 75,
1766
  update_exec_mask_W = 53,
1767
  update_exec_mask_X = 2,
1768
  update_exec_mask_Y = 19,
1769
  update_exec_mask_Z = 36,
1770
  update_pred = 76,
1771
  update_pred_W = 54,
1772
  update_pred_X = 3,
1773
  update_pred_Y = 20,
1774
  update_pred_Z = 37,
1775
  val = 74,
1776
  write = 77,
1777
  write_W = 55,
1778
  write_X = 4,
1779
  write_Y = 21,
1780
  write_Z = 38,
1781
OPERAND_LAST
1782
};
1783
} // end namespace OpName
1784
} // end namespace R600
1785
} // end namespace llvm
1786
#endif //GET_INSTRINFO_OPERAND_ENUM
1787
1788
#ifdef GET_INSTRINFO_NAMED_OPS
1789
#undef GET_INSTRINFO_NAMED_OPS
1790
namespace llvm {
1791
namespace R600 {
1792
LLVM_READONLY
1793
4.19M
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1794
4.19M
  static const int16_t OperandMap [][107] = {
1795
4.19M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1796
4.19M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1797
4.19M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1798
4.19M
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1799
4.19M
{0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1800
4.19M
{0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1801
4.19M
{0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1802
4.19M
{0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1803
4.19M
{0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1804
4.19M
{-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1805
4.19M
{-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1806
4.19M
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
1807
4.19M
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
1808
4.19M
};
1809
4.19M
  switch(Opcode) {
1810
4.19M
  case R600::CUBE_eg_pseudo:
1811
66
  case R600::CUBE_r600_pseudo:
1812
66
    return OperandMap[0][NamedIdx];
1813
587
  case R600::LDS_ADD_RET:
1814
587
  case R600::LDS_AND_RET:
1815
587
  case R600::LDS_MAX_INT_RET:
1816
587
  case R600::LDS_MAX_UINT_RET:
1817
587
  case R600::LDS_MIN_INT_RET:
1818
587
  case R600::LDS_MIN_UINT_RET:
1819
587
  case R600::LDS_OR_RET:
1820
587
  case R600::LDS_SUB_RET:
1821
587
  case R600::LDS_WRXCHG_RET:
1822
587
  case R600::LDS_XOR_RET:
1823
587
    return OperandMap[1][NamedIdx];
1824
587
  case R600::LDS_CMPST_RET:
1825
0
    return OperandMap[2][NamedIdx];
1826
13.4k
  case R600::LDS_BYTE_READ_RET:
1827
13.4k
  case R600::LDS_READ_RET:
1828
13.4k
  case R600::LDS_SHORT_READ_RET:
1829
13.4k
  case R600::LDS_UBYTE_READ_RET:
1830
13.4k
  case R600::LDS_USHORT_READ_RET:
1831
13.4k
    return OperandMap[3][NamedIdx];
1832
812k
  case R600::BFE_INT_eg:
1833
812k
  case R600::BFE_UINT_eg:
1834
812k
  case R600::BFI_INT_eg:
1835
812k
  case R600::BIT_ALIGN_INT_eg:
1836
812k
  case R600::CNDE_INT:
1837
812k
  case R600::CNDE_eg:
1838
812k
  case R600::CNDE_r600:
1839
812k
  case R600::CNDGE_INT:
1840
812k
  case R600::CNDGE_eg:
1841
812k
  case R600::CNDGE_r600:
1842
812k
  case R600::CNDGT_INT:
1843
812k
  case R600::CNDGT_eg:
1844
812k
  case R600::CNDGT_r600:
1845
812k
  case R600::FMA_eg:
1846
812k
  case R600::MULADD_IEEE_eg:
1847
812k
  case R600::MULADD_IEEE_r600:
1848
812k
  case R600::MULADD_INT24_cm:
1849
812k
  case R600::MULADD_UINT24_eg:
1850
812k
  case R600::MULADD_eg:
1851
812k
  case R600::MULADD_r600:
1852
812k
  case R600::MUL_LIT_eg:
1853
812k
  case R600::MUL_LIT_r600:
1854
812k
    return OperandMap[4][NamedIdx];
1855
812k
  case R600::BCNT_INT:
1856
253k
  case R600::CEIL:
1857
253k
  case R600::COS_cm:
1858
253k
  case R600::COS_eg:
1859
253k
  case R600::COS_r600:
1860
253k
  case R600::COS_r700:
1861
253k
  case R600::EXP_IEEE_cm:
1862
253k
  case R600::EXP_IEEE_eg:
1863
253k
  case R600::EXP_IEEE_r600:
1864
253k
  case R600::FFBH_UINT:
1865
253k
  case R600::FFBL_INT:
1866
253k
  case R600::FLOOR:
1867
253k
  case R600::FLT16_TO_FLT32:
1868
253k
  case R600::FLT32_TO_FLT16:
1869
253k
  case R600::FLT_TO_INT_eg:
1870
253k
  case R600::FLT_TO_INT_r600:
1871
253k
  case R600::FLT_TO_UINT_eg:
1872
253k
  case R600::FLT_TO_UINT_r600:
1873
253k
  case R600::FRACT:
1874
253k
  case R600::INTERP_LOAD_P0:
1875
253k
  case R600::INT_TO_FLT_eg:
1876
253k
  case R600::INT_TO_FLT_r600:
1877
253k
  case R600::LOG_CLAMPED_eg:
1878
253k
  case R600::LOG_CLAMPED_r600:
1879
253k
  case R600::LOG_IEEE_cm:
1880
253k
  case R600::LOG_IEEE_eg:
1881
253k
  case R600::LOG_IEEE_r600:
1882
253k
  case R600::MOV:
1883
253k
  case R600::MOVA_INT_eg:
1884
253k
  case R600::NOT_INT:
1885
253k
  case R600::RECIPSQRT_CLAMPED_cm:
1886
253k
  case R600::RECIPSQRT_CLAMPED_eg:
1887
253k
  case R600::RECIPSQRT_CLAMPED_r600:
1888
253k
  case R600::RECIPSQRT_IEEE_cm:
1889
253k
  case R600::RECIPSQRT_IEEE_eg:
1890
253k
  case R600::RECIPSQRT_IEEE_r600:
1891
253k
  case R600::RECIP_CLAMPED_cm:
1892
253k
  case R600::RECIP_CLAMPED_eg:
1893
253k
  case R600::RECIP_CLAMPED_r600:
1894
253k
  case R600::RECIP_IEEE_cm:
1895
253k
  case R600::RECIP_IEEE_eg:
1896
253k
  case R600::RECIP_IEEE_r600:
1897
253k
  case R600::RECIP_UINT_eg:
1898
253k
  case R600::RECIP_UINT_r600:
1899
253k
  case R600::RNDNE:
1900
253k
  case R600::SIN_cm:
1901
253k
  case R600::SIN_eg:
1902
253k
  case R600::SIN_r600:
1903
253k
  case R600::SIN_r700:
1904
253k
  case R600::TRUNC:
1905
253k
  case R600::UINT_TO_FLT_eg:
1906
253k
  case R600::UINT_TO_FLT_r600:
1907
253k
    return OperandMap[5][NamedIdx];
1908
3.04M
  case R600::ADD:
1909
3.04M
  case R600::ADDC_UINT:
1910
3.04M
  case R600::ADD_INT:
1911
3.04M
  case R600::AND_INT:
1912
3.04M
  case R600::ASHR_eg:
1913
3.04M
  case R600::ASHR_r600:
1914
3.04M
  case R600::BFM_INT_eg:
1915
3.04M
  case R600::CUBE_eg_real:
1916
3.04M
  case R600::CUBE_r600_real:
1917
3.04M
  case R600::DOT4_eg:
1918
3.04M
  case R600::DOT4_r600:
1919
3.04M
  case R600::INTERP_XY:
1920
3.04M
  case R600::INTERP_ZW:
1921
3.04M
  case R600::KILLGT:
1922
3.04M
  case R600::LSHL_eg:
1923
3.04M
  case R600::LSHL_r600:
1924
3.04M
  case R600::LSHR_eg:
1925
3.04M
  case R600::LSHR_r600:
1926
3.04M
  case R600::MAX:
1927
3.04M
  case R600::MAX_DX10:
1928
3.04M
  case R600::MAX_INT:
1929
3.04M
  case R600::MAX_UINT:
1930
3.04M
  case R600::MIN:
1931
3.04M
  case R600::MIN_DX10:
1932
3.04M
  case R600::MIN_INT:
1933
3.04M
  case R600::MIN_UINT:
1934
3.04M
  case R600::MUL:
1935
3.04M
  case R600::MULHI_INT_cm:
1936
3.04M
  case R600::MULHI_INT_cm24:
1937
3.04M
  case R600::MULHI_INT_eg:
1938
3.04M
  case R600::MULHI_INT_r600:
1939
3.04M
  case R600::MULHI_UINT24_eg:
1940
3.04M
  case R600::MULHI_UINT_cm:
1941
3.04M
  case R600::MULHI_UINT_cm24:
1942
3.04M
  case R600::MULHI_UINT_eg:
1943
3.04M
  case R600::MULHI_UINT_r600:
1944
3.04M
  case R600::MULLO_INT_cm:
1945
3.04M
  case R600::MULLO_INT_eg:
1946
3.04M
  case R600::MULLO_INT_r600:
1947
3.04M
  case R600::MULLO_UINT_cm:
1948
3.04M
  case R600::MULLO_UINT_eg:
1949
3.04M
  case R600::MULLO_UINT_r600:
1950
3.04M
  case R600::MUL_IEEE:
1951
3.04M
  case R600::MUL_INT24_cm:
1952
3.04M
  case R600::MUL_UINT24_eg:
1953
3.04M
  case R600::OR_INT:
1954
3.04M
  case R600::PRED_SETE:
1955
3.04M
  case R600::PRED_SETE_INT:
1956
3.04M
  case R600::PRED_SETGE:
1957
3.04M
  case R600::PRED_SETGE_INT:
1958
3.04M
  case R600::PRED_SETGT:
1959
3.04M
  case R600::PRED_SETGT_INT:
1960
3.04M
  case R600::PRED_SETNE:
1961
3.04M
  case R600::PRED_SETNE_INT:
1962
3.04M
  case R600::SETE:
1963
3.04M
  case R600::SETE_DX10:
1964
3.04M
  case R600::SETE_INT:
1965
3.04M
  case R600::SETGE_DX10:
1966
3.04M
  case R600::SETGE_INT:
1967
3.04M
  case R600::SETGE_UINT:
1968
3.04M
  case R600::SETGT_DX10:
1969
3.04M
  case R600::SETGT_INT:
1970
3.04M
  case R600::SETGT_UINT:
1971
3.04M
  case R600::SETNE_DX10:
1972
3.04M
  case R600::SETNE_INT:
1973
3.04M
  case R600::SGE:
1974
3.04M
  case R600::SGT:
1975
3.04M
  case R600::SNE:
1976
3.04M
  case R600::SUBB_UINT:
1977
3.04M
  case R600::SUB_INT:
1978
3.04M
  case R600::XOR_INT:
1979
3.04M
    return OperandMap[6][NamedIdx];
1980
3.04M
  case R600::DOT_4:
1981
17.0k
    return OperandMap[7][NamedIdx];
1982
3.04M
  case R600::R600_RegisterLoad:
1983
2.29k
    return OperandMap[8][NamedIdx];
1984
3.04M
  case R600::LDS_ADD:
1985
36.8k
  case R600::LDS_AND:
1986
36.8k
  case R600::LDS_BYTE_WRITE:
1987
36.8k
  case R600::LDS_MAX_INT:
1988
36.8k
  case R600::LDS_MAX_UINT:
1989
36.8k
  case R600::LDS_MIN_INT:
1990
36.8k
  case R600::LDS_MIN_UINT:
1991
36.8k
  case R600::LDS_OR:
1992
36.8k
  case R600::LDS_SHORT_WRITE:
1993
36.8k
  case R600::LDS_SUB:
1994
36.8k
  case R600::LDS_WRITE:
1995
36.8k
  case R600::LDS_WRXCHG:
1996
36.8k
  case R600::LDS_XOR:
1997
36.8k
    return OperandMap[9][NamedIdx];
1998
36.8k
  case R600::LDS_CMPST:
1999
0
    return OperandMap[10][NamedIdx];
2000
36.8k
  case R600::R600_RegisterStore:
2001
1.90k
    return OperandMap[11][NamedIdx];
2002
36.8k
  case R600::CF_ALU:
2003
7.12k
  case R600::CF_ALU_BREAK:
2004
7.12k
  case R600::CF_ALU_CONTINUE:
2005
7.12k
  case R600::CF_ALU_ELSE_AFTER:
2006
7.12k
  case R600::CF_ALU_POP_AFTER:
2007
7.12k
  case R600::CF_ALU_PUSH_BEFORE:
2008
7.12k
    return OperandMap[12][NamedIdx];
2009
7.12k
    
default: return -15.97k
;
2010
4.19M
  }
2011
4.19M
}
2012
} // end namespace R600
2013
} // end namespace llvm
2014
#endif //GET_INSTRINFO_NAMED_OPS
2015
2016
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
2017
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
2018
namespace llvm {
2019
namespace R600 {
2020
namespace OpTypes {
2021
enum OperandType {
2022
  ABS = 0,
2023
  BANK_SWIZZLE = 1,
2024
  CLAMP = 2,
2025
  CT = 3,
2026
  FRAMEri = 4,
2027
  InstFlag = 5,
2028
  KCACHE = 6,
2029
  LAST = 7,
2030
  LITERAL = 8,
2031
  MEMrr = 9,
2032
  MEMxi = 10,
2033
  NEG = 11,
2034
  OMOD = 12,
2035
  R600_Pred = 13,
2036
  REL = 14,
2037
  RSel = 15,
2038
  SEL = 16,
2039
  UEM = 17,
2040
  UP = 18,
2041
  WRITE = 19,
2042
  brtarget = 20,
2043
  f32imm = 21,
2044
  f64imm = 22,
2045
  i16imm = 23,
2046
  i1imm = 24,
2047
  i32imm = 25,
2048
  i64imm = 26,
2049
  i8imm = 27,
2050
  ptype0 = 28,
2051
  ptype1 = 29,
2052
  ptype2 = 30,
2053
  ptype3 = 31,
2054
  ptype4 = 32,
2055
  ptype5 = 33,
2056
  s16imm = 34,
2057
  type0 = 35,
2058
  type1 = 36,
2059
  type2 = 37,
2060
  type3 = 38,
2061
  type4 = 39,
2062
  type5 = 40,
2063
  u16imm = 41,
2064
  u32imm = 42,
2065
  u8imm = 43,
2066
  OPERAND_TYPE_LIST_END
2067
};
2068
} // end namespace OpTypes
2069
} // end namespace R600
2070
} // end namespace llvm
2071
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
2072
2073
#ifdef GET_INSTRMAP_INFO
2074
#undef GET_INSTRMAP_INFO
2075
namespace llvm {
2076
2077
namespace R600 {
2078
2079
enum DisableEncoding {
2080
  DisableEncoding_
2081
};
2082
2083
// getLDSNoRetOp
2084
LLVM_READONLY
2085
30
int getLDSNoRetOp(uint16_t Opcode) {
2086
30
static const uint16_t getLDSNoRetOpTable[][2] = {
2087
30
  { R600::LDS_ADD_RET, R600::LDS_ADD },
2088
30
  { R600::LDS_AND_RET, R600::LDS_AND },
2089
30
  { R600::LDS_MAX_INT_RET, R600::LDS_MAX_INT },
2090
30
  { R600::LDS_MAX_UINT_RET, R600::LDS_MAX_UINT },
2091
30
  { R600::LDS_MIN_INT_RET, R600::LDS_MIN_INT },
2092
30
  { R600::LDS_MIN_UINT_RET, R600::LDS_MIN_UINT },
2093
30
  { R600::LDS_OR_RET, R600::LDS_OR },
2094
30
  { R600::LDS_SUB_RET, R600::LDS_SUB },
2095
30
  { R600::LDS_WRXCHG_RET, R600::LDS_WRXCHG },
2096
30
  { R600::LDS_XOR_RET, R600::LDS_XOR },
2097
30
}; // End of getLDSNoRetOpTable
2098
30
2099
30
  unsigned mid;
2100
30
  unsigned start = 0;
2101
30
  unsigned end = 10;
2102
94
  while (start < end) {
2103
94
    mid = start + (end - start)/2;
2104
94
    if (Opcode == getLDSNoRetOpTable[mid][0]) {
2105
30
      break;
2106
30
    }
2107
64
    if (Opcode < getLDSNoRetOpTable[mid][0])
2108
46
      end = mid;
2109
18
    else
2110
18
      start = mid + 1;
2111
64
  }
2112
30
  if (start == end)
2113
0
    return -1; // Instruction doesn't exist in this table.
2114
30
2115
30
  return getLDSNoRetOpTable[mid][1];
2116
30
}
2117
2118
} // End R600 namespace
2119
} // End llvm namespace
2120
#endif // GET_INSTRMAP_INFO
2121