Coverage Report

Created: 2019-03-22 08:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/R600GenMCCodeEmitter.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Machine Code Emitter                                                       *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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uint64_t R600MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10
    SmallVectorImpl<MCFixup> &Fixups,
11
268
    const MCSubtargetInfo &STI) const {
12
268
  static const uint64_t InstBits[] = {
13
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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268
    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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268
    UINT64_C(0),
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    UINT64_C(0),
49
268
    UINT64_C(0),
50
268
    UINT64_C(0),
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268
    UINT64_C(0),
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268
    UINT64_C(0),
53
268
    UINT64_C(0),
54
268
    UINT64_C(0),
55
268
    UINT64_C(0),
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268
    UINT64_C(0),
57
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
64
268
    UINT64_C(0),
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268
    UINT64_C(0),
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268
    UINT64_C(0),
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268
    UINT64_C(0),
68
268
    UINT64_C(0),
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268
    UINT64_C(0),
70
268
    UINT64_C(0),
71
268
    UINT64_C(0),
72
268
    UINT64_C(0),
73
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    UINT64_C(0),
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268
    UINT64_C(0),
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268
    UINT64_C(0),
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268
    UINT64_C(0),
77
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
80
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
88
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    UINT64_C(0),
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    UINT64_C(0),
90
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
95
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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268
    UINT64_C(0),
99
268
    UINT64_C(0),
100
268
    UINT64_C(0),
101
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    UINT64_C(0),
102
268
    UINT64_C(0),
103
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    UINT64_C(0),
104
268
    UINT64_C(0),
105
268
    UINT64_C(0),
106
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    UINT64_C(0),
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    UINT64_C(0),
108
268
    UINT64_C(0),
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268
    UINT64_C(0),
110
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    UINT64_C(0),
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    UINT64_C(0),
112
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    UINT64_C(0),
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268
    UINT64_C(0),
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    UINT64_C(0),
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268
    UINT64_C(0),
116
268
    UINT64_C(0),
117
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    UINT64_C(0),
118
268
    UINT64_C(0),
119
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    UINT64_C(0),
120
268
    UINT64_C(0),
121
268
    UINT64_C(0),
122
268
    UINT64_C(0),
123
268
    UINT64_C(0),
124
268
    UINT64_C(0),
125
268
    UINT64_C(0),
126
268
    UINT64_C(0),
127
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    UINT64_C(0),
128
268
    UINT64_C(0),
129
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    UINT64_C(0),
130
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    UINT64_C(0),
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    UINT64_C(0),
132
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    UINT64_C(0),
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    UINT64_C(0),
134
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
137
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    UINT64_C(0),
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    UINT64_C(0),
139
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    UINT64_C(0),
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    UINT64_C(0),
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142
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
165
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    UINT64_C(0),
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    UINT64_C(0),
167
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
170
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    UINT64_C(0),
171
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    UINT64_C(0),
172
268
    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
175
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
188
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    UINT64_C(0),
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    UINT64_C(0),
190
268
    UINT64_C(0),
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    UINT64_C(0),
192
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
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    UINT64_C(0),
199
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    UINT64_C(0),
200
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    UINT64_C(0),
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    UINT64_C(0),
202
268
    UINT64_C(0),
203
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    UINT64_C(0),
204
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    UINT64_C(0),
205
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    UINT64_C(0),
206
268
    UINT64_C(0),
207
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    UINT64_C(0),
208
268
    UINT64_C(0),
209
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    UINT64_C(0),
210
268
    UINT64_C(0),
211
268
    UINT64_C(0),
212
268
    UINT64_C(0),
213
268
    UINT64_C(0),
214
268
    UINT64_C(0),
215
268
    UINT64_C(0),
216
268
    UINT64_C(0),
217
268
    UINT64_C(0),
218
268
    UINT64_C(0),
219
268
    UINT64_C(0),  // ADD
220
268
    UINT64_C(45079976738816), // ADDC_UINT
221
268
    UINT64_C(28587302322176), // ADD_INT
222
268
    UINT64_C(0),  // ALU_CLAUSE
223
268
    UINT64_C(26388279066624), // AND_INT
224
268
    UINT64_C(11544872091648), // ASHR_eg
225
268
    UINT64_C(61572651155456), // ASHR_r600
226
268
    UINT64_C(93458488360960), // BCNT_INT
227
268
    UINT64_C(175921860444160),  // BFE_INT_eg
228
268
    UINT64_C(140737488355328),  // BFE_UINT_eg
229
268
    UINT64_C(211106232532992),  // BFI_INT_eg
230
268
    UINT64_C(87960930222080), // BFM_INT_eg
231
268
    UINT64_C(422212465065984),  // BIT_ALIGN_INT_eg
232
268
    UINT64_C(9895604649984),  // CEIL
233
268
    UINT64_C(11529215046068469760), // CF_ALU
234
268
    UINT64_C(13258597302978740224), // CF_ALU_BREAK
235
268
    UINT64_C(12970366926827028480), // CF_ALU_CONTINUE
236
268
    UINT64_C(13546827679130451968), // CF_ALU_ELSE_AFTER
237
268
    UINT64_C(12105675798371893248), // CF_ALU_POP_AFTER
238
268
    UINT64_C(11817445422220181504), // CF_ALU_PUSH_BEFORE
239
268
    UINT64_C(9565645608534933504),  // CF_CALL_FS_EG
240
268
    UINT64_C(9907919180215091200),  // CF_CALL_FS_R600
241
268
    UINT64_C(9367487224930631680),  // CF_CONTINUE_EG
242
268
    UINT64_C(9511602413006487552),  // CF_CONTINUE_R600
243
268
    UINT64_C(9457559217478041600),  // CF_ELSE_EG
244
268
    UINT64_C(9691746398101307392),  // CF_ELSE_R600
245
268
    UINT64_C(9799832789158199296),  // CF_END_CM
246
268
    UINT64_C(9232379236109516800),  // CF_END_EG
247
268
    UINT64_C(9232379236109516800),  // CF_END_R600
248
268
    UINT64_C(9403516021949595648),  // CF_JUMP_EG
249
268
    UINT64_C(9583660007044415488),  // CF_JUMP_R600
250
268
    UINT64_C(9421530420459077632),  // CF_PUSH_EG
251
268
    UINT64_C(9655717601082343424),  // CF_PUSH_ELSE_R600
252
268
    UINT64_C(9241386435364257792),  // CF_TC_EG
253
268
    UINT64_C(9259400833873739776),  // CF_TC_R600
254
268
    UINT64_C(9259400833873739776),  // CF_VC_EG
255
268
    UINT64_C(9295429630892703744),  // CF_VC_R600
256
268
    UINT64_C(985162418487296),  // CNDE_INT
257
268
    UINT64_C(879609302220800),  // CNDE_eg
258
268
    UINT64_C(844424930131968),  // CNDE_r600
259
268
    UINT64_C(1055531162664960), // CNDGE_INT
260
268
    UINT64_C(949978046398464),  // CNDGE_eg
261
268
    UINT64_C(914793674309632),  // CNDGE_r600
262
268
    UINT64_C(1020346790576128), // CNDGT_INT
263
268
    UINT64_C(914793674309632),  // CNDGT_eg
264
268
    UINT64_C(879609302220800),  // CNDGT_r600
265
268
    UINT64_C(78065325572096), // COS_cm
266
268
    UINT64_C(78065325572096), // COS_eg
267
268
    UINT64_C(61022895341568), // COS_r600
268
268
    UINT64_C(61022895341568), // COS_r700
269
268
    UINT64_C(105553116266496),  // CUBE_eg_real
270
268
    UINT64_C(45079976738816), // CUBE_r600_real
271
268
    UINT64_C(104453604638720),  // DOT4_eg
272
268
    UINT64_C(43980465111040), // DOT4_r600
273
268
    UINT64_C(9223372036854775808),  // EG_ExportBuf
274
268
    UINT64_C(9223372040076001280),  // EG_ExportSwz
275
268
    UINT64_C(9313444029402185728),  // END_LOOP_EG
276
268
    UINT64_C(9403516021949595648),  // END_LOOP_R600
277
268
    UINT64_C(70918499991552), // EXP_IEEE_cm
278
268
    UINT64_C(70918499991552), // EXP_IEEE_eg
279
268
    UINT64_C(53326313947136), // EXP_IEEE_r600
280
268
    UINT64_C(0),  // FETCH_CLAUSE
281
268
    UINT64_C(94008244174848), // FFBH_UINT
282
268
    UINT64_C(94557999988736), // FFBL_INT
283
268
    UINT64_C(10995116277760), // FLOOR
284
268
    UINT64_C(89610197663744), // FLT16_TO_FLT32
285
268
    UINT64_C(89060441849856), // FLT32_TO_FLT16
286
268
    UINT64_C(43980465111040), // FLT_TO_INT_eg
287
268
    UINT64_C(58823872086016), // FLT_TO_INT_r600
288
268
    UINT64_C(84662395338752), // FLT_TO_UINT_eg
289
268
    UINT64_C(66520453480448), // FLT_TO_UINT_r600
290
268
    UINT64_C(246290604621824),  // FMA_eg
291
268
    UINT64_C(8796093022208),  // FRACT
292
268
    UINT64_C(46181635850240), // GROUP_BARRIER
293
268
    UINT64_C(123145302310912),  // INTERP_LOAD_P0
294
268
    UINT64_C(4294967295), // INTERP_PAIR_XY
295
268
    UINT64_C(4294967295), // INTERP_PAIR_ZW
296
268
    UINT64_C(4294967295), // INTERP_VEC_LOAD
297
268
    UINT64_C(5747147278385152), // INTERP_XY
298
268
    UINT64_C(5747697034199040), // INTERP_ZW
299
268
    UINT64_C(85212151152640), // INT_TO_FLT_eg
300
268
    UINT64_C(59373627899904), // INT_TO_FLT_r600
301
268
    UINT64_C(24739011624960), // KILLGT
302
268
    UINT64_C(598134325510144),  // LDS_ADD
303
268
    UINT64_C(288828510477221888), // LDS_ADD_RET
304
268
    UINT64_C(81662927618179072),  // LDS_AND
305
268
    UINT64_C(369893303769890816), // LDS_AND_RET
306
268
    UINT64_C(486986894081523712), // LDS_BYTE_READ_RET
307
268
    UINT64_C(162727720910848000), // LDS_BYTE_WRITE
308
268
    UINT64_C(144713322401366016), // LDS_CMPST
309
268
    UINT64_C(432943698553077760), // LDS_CMPST_RET
310
268
    UINT64_C(54641329853956096),  // LDS_MAX_INT
311
268
    UINT64_C(342871706005667840), // LDS_MAX_INT_RET
312
268
    UINT64_C(72655728363438080),  // LDS_MAX_UINT
313
268
    UINT64_C(360886104515149824), // LDS_MAX_UINT_RET
314
268
    UINT64_C(45634130599215104),  // LDS_MIN_INT
315
268
    UINT64_C(333864506750926848), // LDS_MIN_INT_RET
316
268
    UINT64_C(63648529108697088),  // LDS_MIN_UINT
317
268
    UINT64_C(351878905260408832), // LDS_MIN_UINT_RET
318
268
    UINT64_C(90670126872920064),  // LDS_OR
319
268
    UINT64_C(378900503024631808), // LDS_OR_RET
320
268
    UINT64_C(450958097062559744), // LDS_READ_RET
321
268
    UINT64_C(505001292591005696), // LDS_SHORT_READ_RET
322
268
    UINT64_C(171734920165588992), // LDS_SHORT_WRITE
323
268
    UINT64_C(9605333580251136), // LDS_SUB
324
268
    UINT64_C(297835709731962880), // LDS_SUB_RET
325
268
    UINT64_C(495994093336264704), // LDS_UBYTE_READ_RET
326
268
    UINT64_C(514008491845746688), // LDS_USHORT_READ_RET
327
268
    UINT64_C(117691724637143040), // LDS_WRITE
328
268
    UINT64_C(117691724637143040), // LDS_WRXCHG
329
268
    UINT64_C(405922100788854784), // LDS_WRXCHG_RET
330
268
    UINT64_C(99677326127661056),  // LDS_XOR
331
268
    UINT64_C(387907702279372800), // LDS_XOR_RET
332
268
    UINT64_C(0),  // LITERALS
333
268
    UINT64_C(71468255805440), // LOG_CLAMPED_eg
334
268
    UINT64_C(53876069761024), // LOG_CLAMPED_r600
335
268
    UINT64_C(72018011619328), // LOG_IEEE_cm
336
268
    UINT64_C(72018011619328), // LOG_IEEE_eg
337
268
    UINT64_C(54425825574912), // LOG_IEEE_r600
338
268
    UINT64_C(9385501623440113664),  // LOOP_BREAK_EG
339
268
    UINT64_C(9547631210025451520),  // LOOP_BREAK_R600
340
268
    UINT64_C(12644383719424), // LSHL_eg
341
268
    UINT64_C(62672162783232), // LSHL_r600
342
268
    UINT64_C(12094627905536), // LSHR_eg
343
268
    UINT64_C(62122406969344), // LSHR_r600
344
268
    UINT64_C(1649267441664),  // MAX
345
268
    UINT64_C(2748779069440),  // MAX_DX10
346
268
    UINT64_C(29686813949952), // MAX_INT
347
268
    UINT64_C(30786325577728), // MAX_UINT
348
268
    UINT64_C(2199023255552),  // MIN
349
268
    UINT64_C(3298534883328),  // MIN_DX10
350
268
    UINT64_C(30236569763840), // MIN_INT
351
268
    UINT64_C(31336081391616), // MIN_UINT
352
268
    UINT64_C(13743895347200), // MOV
353
268
    UINT64_C(112150186033152),  // MOVA_INT_eg
354
268
    UINT64_C(549755813888), // MUL
355
268
    UINT64_C(844424930131968),  // MULADD_IEEE_eg
356
268
    UINT64_C(703687441776640),  // MULADD_IEEE_r600
357
268
    UINT64_C(281474976710656),  // MULADD_INT24_cm
358
268
    UINT64_C(562949953421312),  // MULADD_UINT24_eg
359
268
    UINT64_C(703687441776640),  // MULADD_eg
360
268
    UINT64_C(562949953421312),  // MULADD_r600
361
268
    UINT64_C(79164837199872), // MULHI_INT_cm
362
268
    UINT64_C(50577534877696), // MULHI_INT_cm24
363
268
    UINT64_C(79164837199872), // MULHI_INT_eg
364
268
    UINT64_C(63771674411008), // MULHI_INT_r600
365
268
    UINT64_C(97856534872064), // MULHI_UINT24_eg
366
268
    UINT64_C(80264348827648), // MULHI_UINT_cm
367
268
    UINT64_C(97856534872064), // MULHI_UINT_cm24
368
268
    UINT64_C(80264348827648), // MULHI_UINT_eg
369
268
    UINT64_C(64871186038784), // MULHI_UINT_r600
370
268
    UINT64_C(78615081385984), // MULLO_INT_cm
371
268
    UINT64_C(78615081385984), // MULLO_INT_eg
372
268
    UINT64_C(63221918597120), // MULLO_INT_r600
373
268
    UINT64_C(79714593013760), // MULLO_UINT_cm
374
268
    UINT64_C(79714593013760), // MULLO_UINT_eg
375
268
    UINT64_C(64321430224896), // MULLO_UINT_r600
376
268
    UINT64_C(1099511627776),  // MUL_IEEE
377
268
    UINT64_C(50027779063808), // MUL_INT24_cm
378
268
    UINT64_C(1090715534753792), // MUL_LIT_eg
379
268
    UINT64_C(422212465065984),  // MUL_LIT_r600
380
268
    UINT64_C(99505802313728), // MUL_UINT24_eg
381
268
    UINT64_C(28037546508288), // NOT_INT
382
268
    UINT64_C(26938034880512), // OR_INT
383
268
    UINT64_C(0),  // PAD
384
268
    UINT64_C(9475573615987523584),  // POP_EG
385
268
    UINT64_C(9727775195120271360),  // POP_R600
386
268
    UINT64_C(17592186044416), // PRED_SETE
387
268
    UINT64_C(36283883716608), // PRED_SETE_INT
388
268
    UINT64_C(18691697672192), // PRED_SETGE
389
268
    UINT64_C(37383395344384), // PRED_SETGE_INT
390
268
    UINT64_C(18141941858304), // PRED_SETGT
391
268
    UINT64_C(36833639530496), // PRED_SETGT_INT
392
268
    UINT64_C(19241453486080), // PRED_SETNE
393
268
    UINT64_C(37933151158272), // PRED_SETNE_INT
394
268
    UINT64_C(9223372036854775808),  // R600_ExportBuf
395
268
    UINT64_C(9223372040076001280),  // R600_ExportSwz
396
268
    UINT64_C(10772874191460901488), // RAT_ATOMIC_ADD_NORET
397
268
    UINT64_C(10772874191460900976), // RAT_ATOMIC_ADD_RTN
398
268
    UINT64_C(10772874191460901600), // RAT_ATOMIC_AND_NORET
399
268
    UINT64_C(10772874191460901088), // RAT_ATOMIC_AND_RTN
400
268
    UINT64_C(10772874191460901440), // RAT_ATOMIC_CMPXCHG_INT_NORET
401
268
    UINT64_C(10772874191460900928), // RAT_ATOMIC_CMPXCHG_INT_RTN
402
268
    UINT64_C(10772874191460901680), // RAT_ATOMIC_DEC_UINT_NORET
403
268
    UINT64_C(10772874191460901168), // RAT_ATOMIC_DEC_UINT_RTN
404
268
    UINT64_C(10772874191460901664), // RAT_ATOMIC_INC_UINT_NORET
405
268
    UINT64_C(10772874191460901152), // RAT_ATOMIC_INC_UINT_RTN
406
268
    UINT64_C(10772874191460901568), // RAT_ATOMIC_MAX_INT_NORET
407
268
    UINT64_C(10772874191460901056), // RAT_ATOMIC_MAX_INT_RTN
408
268
    UINT64_C(10772874191460901584), // RAT_ATOMIC_MAX_UINT_NORET
409
268
    UINT64_C(10772874191460901072), // RAT_ATOMIC_MAX_UINT_RTN
410
268
    UINT64_C(10772874191460901536), // RAT_ATOMIC_MIN_INT_NORET
411
268
    UINT64_C(10772874191460901024), // RAT_ATOMIC_MIN_INT_RTN
412
268
    UINT64_C(10772874191460901552), // RAT_ATOMIC_MIN_UINT_NORET
413
268
    UINT64_C(10772874191460901040), // RAT_ATOMIC_MIN_UINT_RTN
414
268
    UINT64_C(10772874191460901616), // RAT_ATOMIC_OR_NORET
415
268
    UINT64_C(10772874191460901104), // RAT_ATOMIC_OR_RTN
416
268
    UINT64_C(10772874191460901520), // RAT_ATOMIC_RSUB_NORET
417
268
    UINT64_C(10772874191460901008), // RAT_ATOMIC_RSUB_RTN
418
268
    UINT64_C(10772874191460901504), // RAT_ATOMIC_SUB_NORET
419
268
    UINT64_C(10772874191460900992), // RAT_ATOMIC_SUB_RTN
420
268
    UINT64_C(10772874191460901408), // RAT_ATOMIC_XCHG_INT_NORET
421
268
    UINT64_C(10772874191460900880), // RAT_ATOMIC_XCHG_INT_RTN
422
268
    UINT64_C(10772874191460901632), // RAT_ATOMIC_XOR_NORET
423
268
    UINT64_C(10772874191460901120), // RAT_ATOMIC_XOR_RTN
424
268
    UINT64_C(10772874191460901136), // RAT_MSKOR
425
268
    UINT64_C(10790888589970383168), // RAT_STORE_DWORD128
426
268
    UINT64_C(10790642299365761344), // RAT_STORE_DWORD32
427
268
    UINT64_C(10790677483737850176), // RAT_STORE_DWORD64
428
268
    UINT64_C(10772874191460900880), // RAT_STORE_TYPED_cm
429
268
    UINT64_C(10772874191460900880), // RAT_STORE_TYPED_eg
430
268
    UINT64_C(10790888589970382880), // RAT_WRITE_CACHELESS_128_eg
431
268
    UINT64_C(10790642299365761056), // RAT_WRITE_CACHELESS_32_eg
432
268
    UINT64_C(10790677483737849888), // RAT_WRITE_CACHELESS_64_eg
433
268
    UINT64_C(74217034874880), // RECIPSQRT_CLAMPED_cm
434
268
    UINT64_C(74217034874880), // RECIPSQRT_CLAMPED_eg
435
268
    UINT64_C(56624848830464), // RECIPSQRT_CLAMPED_r600
436
268
    UINT64_C(75316546502656), // RECIPSQRT_IEEE_cm
437
268
    UINT64_C(75316546502656), // RECIPSQRT_IEEE_eg
438
268
    UINT64_C(57724360458240), // RECIPSQRT_IEEE_r600
439
268
    UINT64_C(72567767433216), // RECIP_CLAMPED_cm
440
268
    UINT64_C(72567767433216), // RECIP_CLAMPED_eg
441
268
    UINT64_C(54975581388800), // RECIP_CLAMPED_r600
442
268
    UINT64_C(73667279060992), // RECIP_IEEE_cm
443
268
    UINT64_C(73667279060992), // RECIP_IEEE_eg
444
268
    UINT64_C(56075093016576), // RECIP_IEEE_r600
445
268
    UINT64_C(81363860455424), // RECIP_UINT_eg
446
268
    UINT64_C(65970697666560), // RECIP_UINT_r600
447
268
    UINT64_C(10445360463872), // RNDNE
448
268
    UINT64_C(4398046511104),  // SETE
449
268
    UINT64_C(6597069766656),  // SETE_DX10
450
268
    UINT64_C(31885837205504), // SETE_INT
451
268
    UINT64_C(7696581394432),  // SETGE_DX10
452
268
    UINT64_C(32985348833280), // SETGE_INT
453
268
    UINT64_C(34634616274944), // SETGE_UINT
454
268
    UINT64_C(7146825580544),  // SETGT_DX10
455
268
    UINT64_C(32435593019392), // SETGT_INT
456
268
    UINT64_C(34084860461056), // SETGT_UINT
457
268
    UINT64_C(8246337208320),  // SETNE_DX10
458
268
    UINT64_C(33535104647168), // SETNE_INT
459
268
    UINT64_C(5497558138880),  // SGE
460
268
    UINT64_C(4947802324992),  // SGT
461
268
    UINT64_C(77515569758208), // SIN_cm
462
268
    UINT64_C(77515569758208), // SIN_eg
463
268
    UINT64_C(60473139527680), // SIN_r600
464
268
    UINT64_C(60473139527680), // SIN_r700
465
268
    UINT64_C(6047313952768),  // SNE
466
268
    UINT64_C(45629732552704), // SUBB_UINT
467
268
    UINT64_C(29137058136064), // SUB_INT
468
268
    UINT64_C(7),  // TEX_GET_GRADIENTS_H
469
268
    UINT64_C(8),  // TEX_GET_GRADIENTS_V
470
268
    UINT64_C(4),  // TEX_GET_TEXTURE_RESINFO
471
268
    UINT64_C(3),  // TEX_LD
472
268
    UINT64_C(35), // TEX_LDPTR
473
268
    UINT64_C(16), // TEX_SAMPLE
474
268
    UINT64_C(24), // TEX_SAMPLE_C
475
268
    UINT64_C(28), // TEX_SAMPLE_C_G
476
268
    UINT64_C(25), // TEX_SAMPLE_C_L
477
268
    UINT64_C(26), // TEX_SAMPLE_C_LB
478
268
    UINT64_C(20), // TEX_SAMPLE_G
479
268
    UINT64_C(17), // TEX_SAMPLE_L
480
268
    UINT64_C(18), // TEX_SAMPLE_LB
481
268
    UINT64_C(11), // TEX_SET_GRADIENTS_H
482
268
    UINT64_C(12), // TEX_SET_GRADIENTS_V
483
268
    UINT64_C(16775081780284751936), // TEX_VTX_CONSTBUF
484
268
    UINT64_C(9236056004066541632),  // TEX_VTX_TEXBUF
485
268
    UINT64_C(9345848836096),  // TRUNC
486
268
    UINT64_C(85761906966528), // UINT_TO_FLT_eg
487
268
    UINT64_C(59923383713792), // UINT_TO_FLT_r600
488
268
    UINT64_C(1769087820812517440),  // VTX_READ_128_cm
489
268
    UINT64_C(1769087821886259264),  // VTX_READ_128_eg
490
268
    UINT64_C(1251983104222953536),  // VTX_READ_16_cm
491
268
    UINT64_C(1251983104357171264),  // VTX_READ_16_eg
492
268
    UINT64_C(1396098292298809408),  // VTX_READ_32_cm
493
268
    UINT64_C(1396098292567244864),  // VTX_READ_32_eg
494
268
    UINT64_C(1684223115334254656),  // VTX_READ_64_cm
495
268
    UINT64_C(1684223115871125568),  // VTX_READ_64_eg
496
268
    UINT64_C(1179925510185025600),  // VTX_READ_8_cm
497
268
    UINT64_C(1179925510252134464),  // VTX_READ_8_eg
498
268
    UINT64_C(9331458427911667712),  // WHILE_LOOP_EG
499
268
    UINT64_C(9439544818968559616),  // WHILE_LOOP_R600
500
268
    UINT64_C(27487790694400), // XOR_INT
501
268
    UINT64_C(0)
502
268
  };
503
268
  const unsigned opcode = MI.getOpcode();
504
268
  uint64_t Value = InstBits[opcode];
505
268
  uint64_t op = 0;
506
268
  (void)op;  // suppress warning
507
268
  switch (opcode) {
508
268
    case R600::CF_CALL_FS_EG:
509
83
    case R600::CF_CALL_FS_R600:
510
83
    case R600::CF_END_CM:
511
83
    case R600::CF_END_EG:
512
83
    case R600::CF_END_R600:
513
83
    case R600::GROUP_BARRIER:
514
83
    case R600::INTERP_PAIR_XY:
515
83
    case R600::INTERP_PAIR_ZW:
516
83
    case R600::INTERP_VEC_LOAD:
517
83
    case R600::PAD: {
518
83
      break;
519
83
    }
520
83
    case R600::CF_CONTINUE_EG:
521
0
    case R600::END_LOOP_EG:
522
0
    case R600::LOOP_BREAK_EG:
523
0
    case R600::WHILE_LOOP_EG: {
524
0
      // op: ADDR
525
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
526
0
      Value |= op & UINT64_C(16777215);
527
0
      break;
528
0
    }
529
14
    case R600::CF_TC_EG:
530
14
    case R600::CF_VC_EG: {
531
14
      // op: ADDR
532
14
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
533
14
      Value |= op & UINT64_C(16777215);
534
14
      // op: COUNT
535
14
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
536
14
      Value |= (op & UINT64_C(63)) << 42;
537
14
      break;
538
14
    }
539
14
    case R600::CF_ELSE_EG:
540
0
    case R600::CF_JUMP_EG:
541
0
    case R600::CF_PUSH_EG:
542
0
    case R600::POP_EG: {
543
0
      // op: ADDR
544
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
545
0
      Value |= op & UINT64_C(16777215);
546
0
      // op: POP_COUNT
547
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
548
0
      Value |= (op & UINT64_C(7)) << 32;
549
0
      break;
550
0
    }
551
32
    case R600::CF_ALU:
552
32
    case R600::CF_ALU_BREAK:
553
32
    case R600::CF_ALU_CONTINUE:
554
32
    case R600::CF_ALU_ELSE_AFTER:
555
32
    case R600::CF_ALU_POP_AFTER:
556
32
    case R600::CF_ALU_PUSH_BEFORE: {
557
32
      // op: ADDR
558
32
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
559
32
      Value |= op & UINT64_C(4194303);
560
32
      // op: KCACHE_BANK0
561
32
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
562
32
      Value |= (op & UINT64_C(15)) << 22;
563
32
      // op: KCACHE_BANK1
564
32
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
565
32
      Value |= (op & UINT64_C(15)) << 26;
566
32
      // op: KCACHE_MODE0
567
32
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
568
32
      Value |= (op & UINT64_C(3)) << 30;
569
32
      // op: KCACHE_MODE1
570
32
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
571
32
      Value |= (op & UINT64_C(3)) << 32;
572
32
      // op: KCACHE_ADDR0
573
32
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
574
32
      Value |= (op & UINT64_C(255)) << 34;
575
32
      // op: KCACHE_ADDR1
576
32
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
577
32
      Value |= (op & UINT64_C(255)) << 42;
578
32
      // op: COUNT
579
32
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
580
32
      Value |= (op & UINT64_C(127)) << 50;
581
32
      break;
582
32
    }
583
32
    case R600::CF_CONTINUE_R600:
584
0
    case R600::CF_PUSH_ELSE_R600:
585
0
    case R600::END_LOOP_R600:
586
0
    case R600::LOOP_BREAK_R600:
587
0
    case R600::WHILE_LOOP_R600: {
588
0
      // op: ADDR
589
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
590
0
      Value |= op & UINT64_C(4294967295);
591
0
      break;
592
0
    }
593
1
    case R600::CF_TC_R600:
594
1
    case R600::CF_VC_R600: {
595
1
      // op: ADDR
596
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
597
1
      Value |= op & UINT64_C(4294967295);
598
1
      // op: CNT
599
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
600
1
      Value |= (op & UINT64_C(8)) << 48;
601
1
      Value |= (op & UINT64_C(7)) << 42;
602
1
      break;
603
1
    }
604
1
    case R600::CF_ELSE_R600:
605
0
    case R600::CF_JUMP_R600:
606
0
    case R600::POP_R600: {
607
0
      // op: ADDR
608
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
609
0
      Value |= op & UINT64_C(4294967295);
610
0
      // op: POP_COUNT
611
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
612
0
      Value |= (op & UINT64_C(7)) << 32;
613
0
      break;
614
0
    }
615
10
    case R600::TEX_GET_GRADIENTS_H:
616
10
    case R600::TEX_GET_GRADIENTS_V:
617
10
    case R600::TEX_GET_TEXTURE_RESINFO:
618
10
    case R600::TEX_LD:
619
10
    case R600::TEX_LDPTR:
620
10
    case R600::TEX_SAMPLE:
621
10
    case R600::TEX_SAMPLE_C:
622
10
    case R600::TEX_SAMPLE_C_G:
623
10
    case R600::TEX_SAMPLE_C_L:
624
10
    case R600::TEX_SAMPLE_C_LB:
625
10
    case R600::TEX_SAMPLE_G:
626
10
    case R600::TEX_SAMPLE_L:
627
10
    case R600::TEX_SAMPLE_LB:
628
10
    case R600::TEX_SET_GRADIENTS_H:
629
10
    case R600::TEX_SET_GRADIENTS_V: {
630
10
      // op: RESOURCE_ID
631
10
      op = getMachineOpValue(MI, MI.getOperand(13), Fixups, STI);
632
10
      Value |= (op & UINT64_C(255)) << 8;
633
10
      // op: SRC_GPR
634
10
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
635
10
      Value |= (op & UINT64_C(127)) << 16;
636
10
      // op: DST_GPR
637
10
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
638
10
      Value |= (op & UINT64_C(127)) << 32;
639
10
      // op: DST_SEL_X
640
10
      op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI);
641
10
      Value |= (op & UINT64_C(7)) << 41;
642
10
      // op: DST_SEL_Y
643
10
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
644
10
      Value |= (op & UINT64_C(7)) << 44;
645
10
      // op: DST_SEL_Z
646
10
      op = getMachineOpValue(MI, MI.getOperand(11), Fixups, STI);
647
10
      Value |= (op & UINT64_C(7)) << 47;
648
10
      // op: DST_SEL_W
649
10
      op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
650
10
      Value |= (op & UINT64_C(7)) << 50;
651
10
      // op: COORD_TYPE_X
652
10
      op = getMachineOpValue(MI, MI.getOperand(15), Fixups, STI);
653
10
      Value |= (op & UINT64_C(1)) << 60;
654
10
      // op: COORD_TYPE_Y
655
10
      op = getMachineOpValue(MI, MI.getOperand(16), Fixups, STI);
656
10
      Value |= (op & UINT64_C(1)) << 61;
657
10
      // op: COORD_TYPE_Z
658
10
      op = getMachineOpValue(MI, MI.getOperand(17), Fixups, STI);
659
10
      Value |= (op & UINT64_C(1)) << 62;
660
10
      // op: COORD_TYPE_W
661
10
      op = getMachineOpValue(MI, MI.getOperand(18), Fixups, STI);
662
10
      Value |= (op & UINT64_C(1)) << 63;
663
10
      break;
664
10
    }
665
10
    case R600::EG_ExportBuf: {
666
0
      // op: arraybase
667
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
668
0
      Value |= op & UINT64_C(8191);
669
0
      // op: type
670
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
671
0
      Value |= (op & UINT64_C(3)) << 13;
672
0
      // op: gpr
673
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
674
0
      Value |= (op & UINT64_C(127)) << 15;
675
0
      // op: arraySize
676
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
677
0
      Value |= (op & UINT64_C(4095)) << 32;
678
0
      // op: compMask
679
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
680
0
      Value |= (op & UINT64_C(15)) << 44;
681
0
      // op: eop
682
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
683
0
      Value |= (op & UINT64_C(1)) << 53;
684
0
      // op: inst
685
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
686
0
      Value |= (op & UINT64_C(255)) << 54;
687
0
      break;
688
10
    }
689
10
    case R600::R600_ExportBuf: {
690
0
      // op: arraybase
691
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
692
0
      Value |= op & UINT64_C(8191);
693
0
      // op: type
694
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
695
0
      Value |= (op & UINT64_C(3)) << 13;
696
0
      // op: gpr
697
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
698
0
      Value |= (op & UINT64_C(127)) << 15;
699
0
      // op: arraySize
700
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
701
0
      Value |= (op & UINT64_C(4095)) << 32;
702
0
      // op: compMask
703
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
704
0
      Value |= (op & UINT64_C(15)) << 44;
705
0
      // op: eop
706
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
707
0
      Value |= (op & UINT64_C(1)) << 53;
708
0
      // op: inst
709
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
710
0
      Value |= (op & UINT64_C(255)) << 55;
711
0
      break;
712
10
    }
713
10
    case R600::EG_ExportSwz: {
714
1
      // op: arraybase
715
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
716
1
      Value |= op & UINT64_C(8191);
717
1
      // op: type
718
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
719
1
      Value |= (op & UINT64_C(3)) << 13;
720
1
      // op: gpr
721
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
722
1
      Value |= (op & UINT64_C(127)) << 15;
723
1
      // op: sw_x
724
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
725
1
      Value |= (op & UINT64_C(7)) << 32;
726
1
      // op: sw_y
727
1
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
728
1
      Value |= (op & UINT64_C(7)) << 35;
729
1
      // op: sw_z
730
1
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
731
1
      Value |= (op & UINT64_C(7)) << 38;
732
1
      // op: sw_w
733
1
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
734
1
      Value |= (op & UINT64_C(7)) << 41;
735
1
      // op: eop
736
1
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
737
1
      Value |= (op & UINT64_C(1)) << 53;
738
1
      // op: inst
739
1
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
740
1
      Value |= (op & UINT64_C(255)) << 54;
741
1
      break;
742
10
    }
743
10
    case R600::R600_ExportSwz: {
744
2
      // op: arraybase
745
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
746
2
      Value |= op & UINT64_C(8191);
747
2
      // op: type
748
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
749
2
      Value |= (op & UINT64_C(3)) << 13;
750
2
      // op: gpr
751
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
752
2
      Value |= (op & UINT64_C(127)) << 15;
753
2
      // op: sw_x
754
2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
755
2
      Value |= (op & UINT64_C(7)) << 32;
756
2
      // op: sw_y
757
2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
758
2
      Value |= (op & UINT64_C(7)) << 35;
759
2
      // op: sw_z
760
2
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
761
2
      Value |= (op & UINT64_C(7)) << 38;
762
2
      // op: sw_w
763
2
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
764
2
      Value |= (op & UINT64_C(7)) << 41;
765
2
      // op: eop
766
2
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
767
2
      Value |= (op & UINT64_C(1)) << 53;
768
2
      // op: inst
769
2
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
770
2
      Value |= (op & UINT64_C(255)) << 55;
771
2
      break;
772
10
    }
773
10
    case R600::TEX_VTX_CONSTBUF:
774
0
    case R600::TEX_VTX_TEXBUF: {
775
0
      // op: dst_gpr
776
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
777
0
      Value |= (op & UINT64_C(127)) << 32;
778
0
      // op: src_gpr
779
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
780
0
      Value |= (op & UINT64_C(127)) << 16;
781
0
      // op: buffer_id
782
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
783
0
      Value |= (op & UINT64_C(255)) << 8;
784
0
      break;
785
0
    }
786
24
    case R600::LITERALS: {
787
24
      // op: literal1
788
24
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
789
24
      Value |= op & UINT64_C(4294967295);
790
24
      // op: literal2
791
24
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
792
24
      Value |= (op & UINT64_C(4294967295)) << 32;
793
24
      break;
794
0
    }
795
0
    case R600::ALU_CLAUSE:
796
0
    case R600::FETCH_CLAUSE: {
797
0
      // op: num
798
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
799
0
      Value |= op & UINT64_C(255);
800
0
      break;
801
0
    }
802
0
    case R600::RAT_STORE_TYPED_cm: {
803
0
      // op: rat_id
804
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
805
0
      Value |= op & UINT64_C(15);
806
0
      // op: rw_gpr
807
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
808
0
      Value |= (op & UINT64_C(127)) << 15;
809
0
      // op: index_gpr
810
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
811
0
      Value |= (op & UINT64_C(127)) << 23;
812
0
      break;
813
0
    }
814
0
    case R600::RAT_STORE_TYPED_eg: {
815
0
      // op: rat_id
816
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
817
0
      Value |= op & UINT64_C(15);
818
0
      // op: rw_gpr
819
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
820
0
      Value |= (op & UINT64_C(127)) << 15;
821
0
      // op: index_gpr
822
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
823
0
      Value |= (op & UINT64_C(127)) << 23;
824
0
      // op: eop
825
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
826
0
      Value |= (op & UINT64_C(1)) << 53;
827
0
      break;
828
0
    }
829
4
    case R600::RAT_MSKOR:
830
4
    case R600::RAT_STORE_DWORD128:
831
4
    case R600::RAT_STORE_DWORD32:
832
4
    case R600::RAT_STORE_DWORD64: {
833
4
      // op: rw_gpr
834
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
835
4
      Value |= (op & UINT64_C(127)) << 15;
836
4
      // op: index_gpr
837
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
838
4
      Value |= (op & UINT64_C(127)) << 23;
839
4
      break;
840
4
    }
841
11
    case R600::RAT_WRITE_CACHELESS_128_eg:
842
11
    case R600::RAT_WRITE_CACHELESS_32_eg:
843
11
    case R600::RAT_WRITE_CACHELESS_64_eg: {
844
11
      // op: rw_gpr
845
11
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
846
11
      Value |= (op & UINT64_C(127)) << 15;
847
11
      // op: index_gpr
848
11
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
849
11
      Value |= (op & UINT64_C(127)) << 23;
850
11
      // op: eop
851
11
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
852
11
      Value |= (op & UINT64_C(1)) << 53;
853
11
      break;
854
11
    }
855
11
    case R600::RAT_ATOMIC_ADD_NORET:
856
0
    case R600::RAT_ATOMIC_ADD_RTN:
857
0
    case R600::RAT_ATOMIC_AND_NORET:
858
0
    case R600::RAT_ATOMIC_AND_RTN:
859
0
    case R600::RAT_ATOMIC_CMPXCHG_INT_NORET:
860
0
    case R600::RAT_ATOMIC_CMPXCHG_INT_RTN:
861
0
    case R600::RAT_ATOMIC_DEC_UINT_NORET:
862
0
    case R600::RAT_ATOMIC_DEC_UINT_RTN:
863
0
    case R600::RAT_ATOMIC_INC_UINT_NORET:
864
0
    case R600::RAT_ATOMIC_INC_UINT_RTN:
865
0
    case R600::RAT_ATOMIC_MAX_INT_NORET:
866
0
    case R600::RAT_ATOMIC_MAX_INT_RTN:
867
0
    case R600::RAT_ATOMIC_MAX_UINT_NORET:
868
0
    case R600::RAT_ATOMIC_MAX_UINT_RTN:
869
0
    case R600::RAT_ATOMIC_MIN_INT_NORET:
870
0
    case R600::RAT_ATOMIC_MIN_INT_RTN:
871
0
    case R600::RAT_ATOMIC_MIN_UINT_NORET:
872
0
    case R600::RAT_ATOMIC_MIN_UINT_RTN:
873
0
    case R600::RAT_ATOMIC_OR_NORET:
874
0
    case R600::RAT_ATOMIC_OR_RTN:
875
0
    case R600::RAT_ATOMIC_RSUB_NORET:
876
0
    case R600::RAT_ATOMIC_RSUB_RTN:
877
0
    case R600::RAT_ATOMIC_SUB_NORET:
878
0
    case R600::RAT_ATOMIC_SUB_RTN:
879
0
    case R600::RAT_ATOMIC_XCHG_INT_NORET:
880
0
    case R600::RAT_ATOMIC_XCHG_INT_RTN:
881
0
    case R600::RAT_ATOMIC_XOR_NORET:
882
0
    case R600::RAT_ATOMIC_XOR_RTN: {
883
0
      // op: rw_gpr
884
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
885
0
      Value |= (op & UINT64_C(127)) << 15;
886
0
      // op: index_gpr
887
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
888
0
      Value |= (op & UINT64_C(127)) << 23;
889
0
      break;
890
0
    }
891
0
    case R600::LDS_CMPST: {
892
0
      // op: src0
893
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
894
0
      Value |= (op & UINT64_C(1536)) << 1;
895
0
      Value |= op & UINT64_C(511);
896
0
      // op: src0_rel
897
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
898
0
      Value |= (op & UINT64_C(1)) << 9;
899
0
      // op: src1
900
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
901
0
      Value |= (op & UINT64_C(1536)) << 14;
902
0
      Value |= (op & UINT64_C(511)) << 13;
903
0
      // op: src1_rel
904
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
905
0
      Value |= (op & UINT64_C(1)) << 22;
906
0
      // op: pred_sel
907
0
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
908
0
      Value |= (op & UINT64_C(3)) << 29;
909
0
      // op: last
910
0
      op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI);
911
0
      Value |= (op & UINT64_C(1)) << 31;
912
0
      // op: src2
913
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
914
0
      Value |= (op & UINT64_C(1536)) << 33;
915
0
      Value |= (op & UINT64_C(511)) << 32;
916
0
      // op: src2_rel
917
0
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
918
0
      Value |= (op & UINT64_C(1)) << 41;
919
0
      // op: bank_swizzle
920
0
      op = getMachineOpValue(MI, MI.getOperand(11), Fixups, STI);
921
0
      Value |= (op & UINT64_C(7)) << 50;
922
0
      break;
923
0
    }
924
0
    case R600::LDS_ADD:
925
0
    case R600::LDS_AND:
926
0
    case R600::LDS_BYTE_WRITE:
927
0
    case R600::LDS_MAX_INT:
928
0
    case R600::LDS_MAX_UINT:
929
0
    case R600::LDS_MIN_INT:
930
0
    case R600::LDS_MIN_UINT:
931
0
    case R600::LDS_OR:
932
0
    case R600::LDS_SHORT_WRITE:
933
0
    case R600::LDS_SUB:
934
0
    case R600::LDS_WRITE:
935
0
    case R600::LDS_WRXCHG:
936
0
    case R600::LDS_XOR: {
937
0
      // op: src0
938
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
939
0
      Value |= (op & UINT64_C(1536)) << 1;
940
0
      Value |= op & UINT64_C(511);
941
0
      // op: src0_rel
942
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
943
0
      Value |= (op & UINT64_C(1)) << 9;
944
0
      // op: src1
945
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
946
0
      Value |= (op & UINT64_C(1536)) << 14;
947
0
      Value |= (op & UINT64_C(511)) << 13;
948
0
      // op: src1_rel
949
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
950
0
      Value |= (op & UINT64_C(1)) << 22;
951
0
      // op: pred_sel
952
0
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
953
0
      Value |= (op & UINT64_C(3)) << 29;
954
0
      // op: last
955
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
956
0
      Value |= (op & UINT64_C(1)) << 31;
957
0
      // op: bank_swizzle
958
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
959
0
      Value |= (op & UINT64_C(7)) << 50;
960
0
      break;
961
0
    }
962
0
    case R600::LDS_BYTE_READ_RET:
963
0
    case R600::LDS_READ_RET:
964
0
    case R600::LDS_SHORT_READ_RET:
965
0
    case R600::LDS_UBYTE_READ_RET:
966
0
    case R600::LDS_USHORT_READ_RET: {
967
0
      // op: src0
968
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
969
0
      Value |= (op & UINT64_C(1536)) << 1;
970
0
      Value |= op & UINT64_C(511);
971
0
      // op: src0_rel
972
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
973
0
      Value |= (op & UINT64_C(1)) << 9;
974
0
      // op: pred_sel
975
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
976
0
      Value |= (op & UINT64_C(3)) << 29;
977
0
      // op: last
978
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
979
0
      Value |= (op & UINT64_C(1)) << 31;
980
0
      // op: bank_swizzle
981
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
982
0
      Value |= (op & UINT64_C(7)) << 50;
983
0
      break;
984
0
    }
985
0
    case R600::LDS_CMPST_RET: {
986
0
      // op: src0
987
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
988
0
      Value |= (op & UINT64_C(1536)) << 1;
989
0
      Value |= op & UINT64_C(511);
990
0
      // op: src0_rel
991
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
992
0
      Value |= (op & UINT64_C(1)) << 9;
993
0
      // op: src1
994
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
995
0
      Value |= (op & UINT64_C(1536)) << 14;
996
0
      Value |= (op & UINT64_C(511)) << 13;
997
0
      // op: src1_rel
998
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
999
0
      Value |= (op & UINT64_C(1)) << 22;
1000
0
      // op: pred_sel
1001
0
      op = getMachineOpValue(MI, MI.getOperand(11), Fixups, STI);
1002
0
      Value |= (op & UINT64_C(3)) << 29;
1003
0
      // op: last
1004
0
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
1005
0
      Value |= (op & UINT64_C(1)) << 31;
1006
0
      // op: src2
1007
0
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
1008
0
      Value |= (op & UINT64_C(1536)) << 33;
1009
0
      Value |= (op & UINT64_C(511)) << 32;
1010
0
      // op: src2_rel
1011
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
1012
0
      Value |= (op & UINT64_C(1)) << 41;
1013
0
      // op: bank_swizzle
1014
0
      op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
1015
0
      Value |= (op & UINT64_C(7)) << 50;
1016
0
      break;
1017
0
    }
1018
0
    case R600::LDS_ADD_RET:
1019
0
    case R600::LDS_AND_RET:
1020
0
    case R600::LDS_MAX_INT_RET:
1021
0
    case R600::LDS_MAX_UINT_RET:
1022
0
    case R600::LDS_MIN_INT_RET:
1023
0
    case R600::LDS_MIN_UINT_RET:
1024
0
    case R600::LDS_OR_RET:
1025
0
    case R600::LDS_SUB_RET:
1026
0
    case R600::LDS_WRXCHG_RET:
1027
0
    case R600::LDS_XOR_RET: {
1028
0
      // op: src0
1029
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
1030
0
      Value |= (op & UINT64_C(1536)) << 1;
1031
0
      Value |= op & UINT64_C(511);
1032
0
      // op: src0_rel
1033
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
1034
0
      Value |= (op & UINT64_C(1)) << 9;
1035
0
      // op: src1
1036
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
1037
0
      Value |= (op & UINT64_C(1536)) << 14;
1038
0
      Value |= (op & UINT64_C(511)) << 13;
1039
0
      // op: src1_rel
1040
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
1041
0
      Value |= (op & UINT64_C(1)) << 22;
1042
0
      // op: pred_sel
1043
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
1044
0
      Value |= (op & UINT64_C(3)) << 29;
1045
0
      // op: last
1046
0
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
1047
0
      Value |= (op & UINT64_C(1)) << 31;
1048
0
      // op: bank_swizzle
1049
0
      op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI);
1050
0
      Value |= (op & UINT64_C(7)) << 50;
1051
0
      break;
1052
0
    }
1053
0
    case R600::BFE_INT_eg:
1054
0
    case R600::BFE_UINT_eg:
1055
0
    case R600::BFI_INT_eg:
1056
0
    case R600::BIT_ALIGN_INT_eg:
1057
0
    case R600::CNDE_INT:
1058
0
    case R600::CNDE_eg:
1059
0
    case R600::CNDE_r600:
1060
0
    case R600::CNDGE_INT:
1061
0
    case R600::CNDGE_eg:
1062
0
    case R600::CNDGE_r600:
1063
0
    case R600::CNDGT_INT:
1064
0
    case R600::CNDGT_eg:
1065
0
    case R600::CNDGT_r600:
1066
0
    case R600::FMA_eg:
1067
0
    case R600::MULADD_IEEE_eg:
1068
0
    case R600::MULADD_IEEE_r600:
1069
0
    case R600::MULADD_INT24_cm:
1070
0
    case R600::MULADD_UINT24_eg:
1071
0
    case R600::MULADD_eg:
1072
0
    case R600::MULADD_r600:
1073
0
    case R600::MUL_LIT_eg:
1074
0
    case R600::MUL_LIT_r600: {
1075
0
      // op: src0
1076
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
1077
0
      Value |= (op & UINT64_C(1536)) << 1;
1078
0
      Value |= op & UINT64_C(511);
1079
0
      // op: src0_rel
1080
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
1081
0
      Value |= (op & UINT64_C(1)) << 9;
1082
0
      // op: src1
1083
0
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
1084
0
      Value |= (op & UINT64_C(1536)) << 14;
1085
0
      Value |= (op & UINT64_C(511)) << 13;
1086
0
      // op: src1_rel
1087
0
      op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI);
1088
0
      Value |= (op & UINT64_C(1)) << 22;
1089
0
      // op: pred_sel
1090
0
      op = getMachineOpValue(MI, MI.getOperand(16), Fixups, STI);
1091
0
      Value |= (op & UINT64_C(3)) << 29;
1092
0
      // op: last
1093
0
      op = getMachineOpValue(MI, MI.getOperand(15), Fixups, STI);
1094
0
      Value |= (op & UINT64_C(1)) << 31;
1095
0
      // op: src0_neg
1096
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
1097
0
      Value |= (op & UINT64_C(1)) << 12;
1098
0
      // op: src1_neg
1099
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
1100
0
      Value |= (op & UINT64_C(1)) << 25;
1101
0
      // op: dst
1102
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
1103
0
      Value |= (op & UINT64_C(1536)) << 52;
1104
0
      Value |= (op & UINT64_C(127)) << 53;
1105
0
      // op: bank_swizzle
1106
0
      op = getMachineOpValue(MI, MI.getOperand(18), Fixups, STI);
1107
0
      Value |= (op & UINT64_C(7)) << 50;
1108
0
      // op: dst_rel
1109
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
1110
0
      Value |= (op & UINT64_C(1)) << 60;
1111
0
      // op: clamp
1112
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
1113
0
      Value |= (op & UINT64_C(1)) << 63;
1114
0
      // op: src2
1115
0
      op = getMachineOpValue(MI, MI.getOperand(11), Fixups, STI);
1116
0
      Value |= (op & UINT64_C(1536)) << 33;
1117
0
      Value |= (op & UINT64_C(511)) << 32;
1118
0
      // op: src2_rel
1119
0
      op = getMachineOpValue(MI, MI.getOperand(13), Fixups, STI);
1120
0
      Value |= (op & UINT64_C(1)) << 41;
1121
0
      // op: src2_neg
1122
0
      op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
1123
0
      Value |= (op & UINT64_C(1)) << 44;
1124
0
      break;
1125
0
    }
1126
10
    case R600::BCNT_INT:
1127
10
    case R600::CEIL:
1128
10
    case R600::COS_cm:
1129
10
    case R600::COS_eg:
1130
10
    case R600::COS_r600:
1131
10
    case R600::COS_r700:
1132
10
    case R600::EXP_IEEE_cm:
1133
10
    case R600::EXP_IEEE_eg:
1134
10
    case R600::EXP_IEEE_r600:
1135
10
    case R600::FFBH_UINT:
1136
10
    case R600::FFBL_INT:
1137
10
    case R600::FLOOR:
1138
10
    case R600::FLT16_TO_FLT32:
1139
10
    case R600::FLT32_TO_FLT16:
1140
10
    case R600::FLT_TO_INT_eg:
1141
10
    case R600::FLT_TO_INT_r600:
1142
10
    case R600::FLT_TO_UINT_eg:
1143
10
    case R600::FLT_TO_UINT_r600:
1144
10
    case R600::FRACT:
1145
10
    case R600::INTERP_LOAD_P0:
1146
10
    case R600::INT_TO_FLT_eg:
1147
10
    case R600::INT_TO_FLT_r600:
1148
10
    case R600::LOG_CLAMPED_eg:
1149
10
    case R600::LOG_CLAMPED_r600:
1150
10
    case R600::LOG_IEEE_cm:
1151
10
    case R600::LOG_IEEE_eg:
1152
10
    case R600::LOG_IEEE_r600:
1153
10
    case R600::MOV:
1154
10
    case R600::MOVA_INT_eg:
1155
10
    case R600::NOT_INT:
1156
10
    case R600::RECIPSQRT_CLAMPED_cm:
1157
10
    case R600::RECIPSQRT_CLAMPED_eg:
1158
10
    case R600::RECIPSQRT_CLAMPED_r600:
1159
10
    case R600::RECIPSQRT_IEEE_cm:
1160
10
    case R600::RECIPSQRT_IEEE_eg:
1161
10
    case R600::RECIPSQRT_IEEE_r600:
1162
10
    case R600::RECIP_CLAMPED_cm:
1163
10
    case R600::RECIP_CLAMPED_eg:
1164
10
    case R600::RECIP_CLAMPED_r600:
1165
10
    case R600::RECIP_IEEE_cm:
1166
10
    case R600::RECIP_IEEE_eg:
1167
10
    case R600::RECIP_IEEE_r600:
1168
10
    case R600::RECIP_UINT_eg:
1169
10
    case R600::RECIP_UINT_r600:
1170
10
    case R600::RNDNE:
1171
10
    case R600::SIN_cm:
1172
10
    case R600::SIN_eg:
1173
10
    case R600::SIN_r600:
1174
10
    case R600::SIN_r700:
1175
10
    case R600::TRUNC:
1176
10
    case R600::UINT_TO_FLT_eg:
1177
10
    case R600::UINT_TO_FLT_r600: {
1178
10
      // op: src0
1179
10
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
1180
10
      Value |= (op & UINT64_C(1536)) << 1;
1181
10
      Value |= op & UINT64_C(511);
1182
10
      // op: src0_rel
1183
10
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
1184
10
      Value |= (op & UINT64_C(1)) << 9;
1185
10
      // op: pred_sel
1186
10
      op = getMachineOpValue(MI, MI.getOperand(11), Fixups, STI);
1187
10
      Value |= (op & UINT64_C(3)) << 29;
1188
10
      // op: last
1189
10
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
1190
10
      Value |= (op & UINT64_C(1)) << 31;
1191
10
      // op: src0_neg
1192
10
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
1193
10
      Value |= (op & UINT64_C(1)) << 12;
1194
10
      // op: dst
1195
10
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
1196
10
      Value |= (op & UINT64_C(1536)) << 52;
1197
10
      Value |= (op & UINT64_C(127)) << 53;
1198
10
      // op: bank_swizzle
1199
10
      op = getMachineOpValue(MI, MI.getOperand(13), Fixups, STI);
1200
10
      Value |= (op & UINT64_C(7)) << 50;
1201
10
      // op: dst_rel
1202
10
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
1203
10
      Value |= (op & UINT64_C(1)) << 60;
1204
10
      // op: clamp
1205
10
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
1206
10
      Value |= (op & UINT64_C(1)) << 63;
1207
10
      // op: src0_abs
1208
10
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
1209
10
      Value |= (op & UINT64_C(1)) << 32;
1210
10
      // op: write
1211
10
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
1212
10
      Value |= (op & UINT64_C(1)) << 36;
1213
10
      // op: omod
1214
10
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
1215
10
      Value |= (op & UINT64_C(3)) << 37;
1216
10
      break;
1217
10
    }
1218
62
    case R600::ADD:
1219
62
    case R600::ADDC_UINT:
1220
62
    case R600::ADD_INT:
1221
62
    case R600::AND_INT:
1222
62
    case R600::ASHR_eg:
1223
62
    case R600::ASHR_r600:
1224
62
    case R600::BFM_INT_eg:
1225
62
    case R600::CUBE_eg_real:
1226
62
    case R600::CUBE_r600_real:
1227
62
    case R600::DOT4_eg:
1228
62
    case R600::DOT4_r600:
1229
62
    case R600::KILLGT:
1230
62
    case R600::LSHL_eg:
1231
62
    case R600::LSHL_r600:
1232
62
    case R600::LSHR_eg:
1233
62
    case R600::LSHR_r600:
1234
62
    case R600::MAX:
1235
62
    case R600::MAX_DX10:
1236
62
    case R600::MAX_INT:
1237
62
    case R600::MAX_UINT:
1238
62
    case R600::MIN:
1239
62
    case R600::MIN_DX10:
1240
62
    case R600::MIN_INT:
1241
62
    case R600::MIN_UINT:
1242
62
    case R600::MUL:
1243
62
    case R600::MULHI_INT_cm:
1244
62
    case R600::MULHI_INT_cm24:
1245
62
    case R600::MULHI_INT_eg:
1246
62
    case R600::MULHI_INT_r600:
1247
62
    case R600::MULHI_UINT24_eg:
1248
62
    case R600::MULHI_UINT_cm:
1249
62
    case R600::MULHI_UINT_cm24:
1250
62
    case R600::MULHI_UINT_eg:
1251
62
    case R600::MULHI_UINT_r600:
1252
62
    case R600::MULLO_INT_cm:
1253
62
    case R600::MULLO_INT_eg:
1254
62
    case R600::MULLO_INT_r600:
1255
62
    case R600::MULLO_UINT_cm:
1256
62
    case R600::MULLO_UINT_eg:
1257
62
    case R600::MULLO_UINT_r600:
1258
62
    case R600::MUL_IEEE:
1259
62
    case R600::MUL_INT24_cm:
1260
62
    case R600::MUL_UINT24_eg:
1261
62
    case R600::OR_INT:
1262
62
    case R600::PRED_SETE:
1263
62
    case R600::PRED_SETE_INT:
1264
62
    case R600::PRED_SETGE:
1265
62
    case R600::PRED_SETGE_INT:
1266
62
    case R600::PRED_SETGT:
1267
62
    case R600::PRED_SETGT_INT:
1268
62
    case R600::PRED_SETNE:
1269
62
    case R600::PRED_SETNE_INT:
1270
62
    case R600::SETE:
1271
62
    case R600::SETE_DX10:
1272
62
    case R600::SETE_INT:
1273
62
    case R600::SETGE_DX10:
1274
62
    case R600::SETGE_INT:
1275
62
    case R600::SETGE_UINT:
1276
62
    case R600::SETGT_DX10:
1277
62
    case R600::SETGT_INT:
1278
62
    case R600::SETGT_UINT:
1279
62
    case R600::SETNE_DX10:
1280
62
    case R600::SETNE_INT:
1281
62
    case R600::SGE:
1282
62
    case R600::SGT:
1283
62
    case R600::SNE:
1284
62
    case R600::SUBB_UINT:
1285
62
    case R600::SUB_INT:
1286
62
    case R600::XOR_INT: {
1287
62
      // op: src0
1288
62
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
1289
62
      Value |= (op & UINT64_C(1536)) << 1;
1290
62
      Value |= op & UINT64_C(511);
1291
62
      // op: src0_rel
1292
62
      op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI);
1293
62
      Value |= (op & UINT64_C(1)) << 9;
1294
62
      // op: src1
1295
62
      op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
1296
62
      Value |= (op & UINT64_C(1536)) << 14;
1297
62
      Value |= (op & UINT64_C(511)) << 13;
1298
62
      // op: src1_rel
1299
62
      op = getMachineOpValue(MI, MI.getOperand(14), Fixups, STI);
1300
62
      Value |= (op & UINT64_C(1)) << 22;
1301
62
      // op: pred_sel
1302
62
      op = getMachineOpValue(MI, MI.getOperand(18), Fixups, STI);
1303
62
      Value |= (op & UINT64_C(3)) << 29;
1304
62
      // op: last
1305
62
      op = getMachineOpValue(MI, MI.getOperand(17), Fixups, STI);
1306
62
      Value |= (op & UINT64_C(1)) << 31;
1307
62
      // op: src0_neg
1308
62
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
1309
62
      Value |= (op & UINT64_C(1)) << 12;
1310
62
      // op: src1_neg
1311
62
      op = getMachineOpValue(MI, MI.getOperand(13), Fixups, STI);
1312
62
      Value |= (op & UINT64_C(1)) << 25;
1313
62
      // op: dst
1314
62
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
1315
62
      Value |= (op & UINT64_C(1536)) << 52;
1316
62
      Value |= (op & UINT64_C(127)) << 53;
1317
62
      // op: bank_swizzle
1318
62
      op = getMachineOpValue(MI, MI.getOperand(20), Fixups, STI);
1319
62
      Value |= (op & UINT64_C(7)) << 50;
1320
62
      // op: dst_rel
1321
62
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
1322
62
      Value |= (op & UINT64_C(1)) << 60;
1323
62
      // op: clamp
1324
62
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
1325
62
      Value |= (op & UINT64_C(1)) << 63;
1326
62
      // op: src0_abs
1327
62
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
1328
62
      Value |= (op & UINT64_C(1)) << 32;
1329
62
      // op: src1_abs
1330
62
      op = getMachineOpValue(MI, MI.getOperand(15), Fixups, STI);
1331
62
      Value |= (op & UINT64_C(1)) << 33;
1332
62
      // op: update_exec_mask
1333
62
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
1334
62
      Value |= (op & UINT64_C(1)) << 34;
1335
62
      // op: update_pred
1336
62
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
1337
62
      Value |= (op & UINT64_C(1)) << 35;
1338
62
      // op: write
1339
62
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
1340
62
      Value |= (op & UINT64_C(1)) << 36;
1341
62
      // op: omod
1342
62
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
1343
62
      Value |= (op & UINT64_C(3)) << 37;
1344
62
      break;
1345
62
    }
1346
62
    case R600::INTERP_XY:
1347
0
    case R600::INTERP_ZW: {
1348
0
      // op: src0
1349
0
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
1350
0
      Value |= (op & UINT64_C(1536)) << 1;
1351
0
      Value |= op & UINT64_C(511);
1352
0
      // op: src0_rel
1353
0
      op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI);
1354
0
      Value |= (op & UINT64_C(1)) << 9;
1355
0
      // op: src1
1356
0
      op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
1357
0
      Value |= (op & UINT64_C(1536)) << 14;
1358
0
      Value |= (op & UINT64_C(511)) << 13;
1359
0
      // op: src1_rel
1360
0
      op = getMachineOpValue(MI, MI.getOperand(14), Fixups, STI);
1361
0
      Value |= (op & UINT64_C(1)) << 22;
1362
0
      // op: pred_sel
1363
0
      op = getMachineOpValue(MI, MI.getOperand(18), Fixups, STI);
1364
0
      Value |= (op & UINT64_C(3)) << 29;
1365
0
      // op: last
1366
0
      op = getMachineOpValue(MI, MI.getOperand(17), Fixups, STI);
1367
0
      Value |= (op & UINT64_C(1)) << 31;
1368
0
      // op: src0_neg
1369
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
1370
0
      Value |= (op & UINT64_C(1)) << 12;
1371
0
      // op: src1_neg
1372
0
      op = getMachineOpValue(MI, MI.getOperand(13), Fixups, STI);
1373
0
      Value |= (op & UINT64_C(1)) << 25;
1374
0
      // op: dst
1375
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
1376
0
      Value |= (op & UINT64_C(1536)) << 52;
1377
0
      Value |= (op & UINT64_C(127)) << 53;
1378
0
      // op: dst_rel
1379
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
1380
0
      Value |= (op & UINT64_C(1)) << 60;
1381
0
      // op: clamp
1382
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
1383
0
      Value |= (op & UINT64_C(1)) << 63;
1384
0
      // op: src0_abs
1385
0
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
1386
0
      Value |= (op & UINT64_C(1)) << 32;
1387
0
      // op: src1_abs
1388
0
      op = getMachineOpValue(MI, MI.getOperand(15), Fixups, STI);
1389
0
      Value |= (op & UINT64_C(1)) << 33;
1390
0
      // op: update_exec_mask
1391
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
1392
0
      Value |= (op & UINT64_C(1)) << 34;
1393
0
      // op: update_pred
1394
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
1395
0
      Value |= (op & UINT64_C(1)) << 35;
1396
0
      // op: write
1397
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
1398
0
      Value |= (op & UINT64_C(1)) << 36;
1399
0
      // op: omod
1400
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
1401
0
      Value |= (op & UINT64_C(3)) << 37;
1402
0
      break;
1403
0
    }
1404
14
    case R600::VTX_READ_128_cm:
1405
14
    case R600::VTX_READ_128_eg:
1406
14
    case R600::VTX_READ_16_cm:
1407
14
    case R600::VTX_READ_16_eg:
1408
14
    case R600::VTX_READ_32_cm:
1409
14
    case R600::VTX_READ_32_eg:
1410
14
    case R600::VTX_READ_64_cm:
1411
14
    case R600::VTX_READ_64_eg:
1412
14
    case R600::VTX_READ_8_cm:
1413
14
    case R600::VTX_READ_8_eg: {
1414
14
      // op: src_gpr
1415
14
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
1416
14
      Value |= (op & UINT64_C(127)) << 16;
1417
14
      // op: buffer_id
1418
14
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
1419
14
      Value |= (op & UINT64_C(255)) << 8;
1420
14
      // op: dst_gpr
1421
14
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
1422
14
      Value |= (op & UINT64_C(127)) << 32;
1423
14
      break;
1424
14
    }
1425
14
  default:
1426
0
    std::string msg;
1427
0
    raw_string_ostream Msg(msg);
1428
0
    Msg << "Not supported instr: " << MI;
1429
0
    report_fatal_error(Msg.str());
1430
268
  }
1431
268
  return Value;
1432
268
}
1433
1434
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
1435
#undef ENABLE_INSTR_PREDICATE_VERIFIER
1436
#include <sstream>
1437
1438
// Bits for subtarget features that participate in instruction matching.
1439
enum SubtargetFeatureBits : uint8_t {
1440
};
1441
1442
#ifndef NDEBUG
1443
static const char *SubtargetFeatureNames[] = {
1444
  nullptr
1445
};
1446
1447
#endif // NDEBUG
1448
FeatureBitset R600MCCodeEmitter::
1449
315
computeAvailableFeatures(const FeatureBitset& FB) const {
1450
315
  FeatureBitset Features;
1451
315
  return Features;
1452
315
}
1453
1454
#ifndef NDEBUG
1455
// Feature bitsets.
1456
enum : uint8_t {
1457
  CEFBS_None,
1458
};
1459
1460
const static FeatureBitset FeatureBitsets[] {
1461
  {}, // CEFBS_None
1462
};
1463
#endif // NDEBUG
1464
1465
void R600MCCodeEmitter::verifyInstructionPredicates(
1466
315
    const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
1467
#ifndef NDEBUG
1468
  static uint8_t RequiredFeaturesRefs[] = {
1469
    CEFBS_None, // PHI = 0
1470
    CEFBS_None, // INLINEASM = 1
1471
    CEFBS_None, // INLINEASM_BR = 2
1472
    CEFBS_None, // CFI_INSTRUCTION = 3
1473
    CEFBS_None, // EH_LABEL = 4
1474
    CEFBS_None, // GC_LABEL = 5
1475
    CEFBS_None, // ANNOTATION_LABEL = 6
1476
    CEFBS_None, // KILL = 7
1477
    CEFBS_None, // EXTRACT_SUBREG = 8
1478
    CEFBS_None, // INSERT_SUBREG = 9
1479
    CEFBS_None, // IMPLICIT_DEF = 10
1480
    CEFBS_None, // SUBREG_TO_REG = 11
1481
    CEFBS_None, // COPY_TO_REGCLASS = 12
1482
    CEFBS_None, // DBG_VALUE = 13
1483
    CEFBS_None, // DBG_LABEL = 14
1484
    CEFBS_None, // REG_SEQUENCE = 15
1485
    CEFBS_None, // COPY = 16
1486
    CEFBS_None, // BUNDLE = 17
1487
    CEFBS_None, // LIFETIME_START = 18
1488
    CEFBS_None, // LIFETIME_END = 19
1489
    CEFBS_None, // STACKMAP = 20
1490
    CEFBS_None, // FENTRY_CALL = 21
1491
    CEFBS_None, // PATCHPOINT = 22
1492
    CEFBS_None, // LOAD_STACK_GUARD = 23
1493
    CEFBS_None, // STATEPOINT = 24
1494
    CEFBS_None, // LOCAL_ESCAPE = 25
1495
    CEFBS_None, // FAULTING_OP = 26
1496
    CEFBS_None, // PATCHABLE_OP = 27
1497
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 28
1498
    CEFBS_None, // PATCHABLE_RET = 29
1499
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 30
1500
    CEFBS_None, // PATCHABLE_TAIL_CALL = 31
1501
    CEFBS_None, // PATCHABLE_EVENT_CALL = 32
1502
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 33
1503
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 34
1504
    CEFBS_None, // G_ADD = 35
1505
    CEFBS_None, // G_SUB = 36
1506
    CEFBS_None, // G_MUL = 37
1507
    CEFBS_None, // G_SDIV = 38
1508
    CEFBS_None, // G_UDIV = 39
1509
    CEFBS_None, // G_SREM = 40
1510
    CEFBS_None, // G_UREM = 41
1511
    CEFBS_None, // G_AND = 42
1512
    CEFBS_None, // G_OR = 43
1513
    CEFBS_None, // G_XOR = 44
1514
    CEFBS_None, // G_IMPLICIT_DEF = 45
1515
    CEFBS_None, // G_PHI = 46
1516
    CEFBS_None, // G_FRAME_INDEX = 47
1517
    CEFBS_None, // G_GLOBAL_VALUE = 48
1518
    CEFBS_None, // G_EXTRACT = 49
1519
    CEFBS_None, // G_UNMERGE_VALUES = 50
1520
    CEFBS_None, // G_INSERT = 51
1521
    CEFBS_None, // G_MERGE_VALUES = 52
1522
    CEFBS_None, // G_BUILD_VECTOR = 53
1523
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 54
1524
    CEFBS_None, // G_CONCAT_VECTORS = 55
1525
    CEFBS_None, // G_PTRTOINT = 56
1526
    CEFBS_None, // G_INTTOPTR = 57
1527
    CEFBS_None, // G_BITCAST = 58
1528
    CEFBS_None, // G_INTRINSIC_TRUNC = 59
1529
    CEFBS_None, // G_INTRINSIC_ROUND = 60
1530
    CEFBS_None, // G_LOAD = 61
1531
    CEFBS_None, // G_SEXTLOAD = 62
1532
    CEFBS_None, // G_ZEXTLOAD = 63
1533
    CEFBS_None, // G_STORE = 64
1534
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65
1535
    CEFBS_None, // G_ATOMIC_CMPXCHG = 66
1536
    CEFBS_None, // G_ATOMICRMW_XCHG = 67
1537
    CEFBS_None, // G_ATOMICRMW_ADD = 68
1538
    CEFBS_None, // G_ATOMICRMW_SUB = 69
1539
    CEFBS_None, // G_ATOMICRMW_AND = 70
1540
    CEFBS_None, // G_ATOMICRMW_NAND = 71
1541
    CEFBS_None, // G_ATOMICRMW_OR = 72
1542
    CEFBS_None, // G_ATOMICRMW_XOR = 73
1543
    CEFBS_None, // G_ATOMICRMW_MAX = 74
1544
    CEFBS_None, // G_ATOMICRMW_MIN = 75
1545
    CEFBS_None, // G_ATOMICRMW_UMAX = 76
1546
    CEFBS_None, // G_ATOMICRMW_UMIN = 77
1547
    CEFBS_None, // G_BRCOND = 78
1548
    CEFBS_None, // G_BRINDIRECT = 79
1549
    CEFBS_None, // G_INTRINSIC = 80
1550
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 81
1551
    CEFBS_None, // G_ANYEXT = 82
1552
    CEFBS_None, // G_TRUNC = 83
1553
    CEFBS_None, // G_CONSTANT = 84
1554
    CEFBS_None, // G_FCONSTANT = 85
1555
    CEFBS_None, // G_VASTART = 86
1556
    CEFBS_None, // G_VAARG = 87
1557
    CEFBS_None, // G_SEXT = 88
1558
    CEFBS_None, // G_ZEXT = 89
1559
    CEFBS_None, // G_SHL = 90
1560
    CEFBS_None, // G_LSHR = 91
1561
    CEFBS_None, // G_ASHR = 92
1562
    CEFBS_None, // G_ICMP = 93
1563
    CEFBS_None, // G_FCMP = 94
1564
    CEFBS_None, // G_SELECT = 95
1565
    CEFBS_None, // G_UADDO = 96
1566
    CEFBS_None, // G_UADDE = 97
1567
    CEFBS_None, // G_USUBO = 98
1568
    CEFBS_None, // G_USUBE = 99
1569
    CEFBS_None, // G_SADDO = 100
1570
    CEFBS_None, // G_SADDE = 101
1571
    CEFBS_None, // G_SSUBO = 102
1572
    CEFBS_None, // G_SSUBE = 103
1573
    CEFBS_None, // G_UMULO = 104
1574
    CEFBS_None, // G_SMULO = 105
1575
    CEFBS_None, // G_UMULH = 106
1576
    CEFBS_None, // G_SMULH = 107
1577
    CEFBS_None, // G_FADD = 108
1578
    CEFBS_None, // G_FSUB = 109
1579
    CEFBS_None, // G_FMUL = 110
1580
    CEFBS_None, // G_FMA = 111
1581
    CEFBS_None, // G_FDIV = 112
1582
    CEFBS_None, // G_FREM = 113
1583
    CEFBS_None, // G_FPOW = 114
1584
    CEFBS_None, // G_FEXP = 115
1585
    CEFBS_None, // G_FEXP2 = 116
1586
    CEFBS_None, // G_FLOG = 117
1587
    CEFBS_None, // G_FLOG2 = 118
1588
    CEFBS_None, // G_FLOG10 = 119
1589
    CEFBS_None, // G_FNEG = 120
1590
    CEFBS_None, // G_FPEXT = 121
1591
    CEFBS_None, // G_FPTRUNC = 122
1592
    CEFBS_None, // G_FPTOSI = 123
1593
    CEFBS_None, // G_FPTOUI = 124
1594
    CEFBS_None, // G_SITOFP = 125
1595
    CEFBS_None, // G_UITOFP = 126
1596
    CEFBS_None, // G_FABS = 127
1597
    CEFBS_None, // G_FCANONICALIZE = 128
1598
    CEFBS_None, // G_GEP = 129
1599
    CEFBS_None, // G_PTR_MASK = 130
1600
    CEFBS_None, // G_BR = 131
1601
    CEFBS_None, // G_INSERT_VECTOR_ELT = 132
1602
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 133
1603
    CEFBS_None, // G_SHUFFLE_VECTOR = 134
1604
    CEFBS_None, // G_CTTZ = 135
1605
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 136
1606
    CEFBS_None, // G_CTLZ = 137
1607
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 138
1608
    CEFBS_None, // G_CTPOP = 139
1609
    CEFBS_None, // G_BSWAP = 140
1610
    CEFBS_None, // G_FCEIL = 141
1611
    CEFBS_None, // G_FCOS = 142
1612
    CEFBS_None, // G_FSIN = 143
1613
    CEFBS_None, // G_FSQRT = 144
1614
    CEFBS_None, // G_FFLOOR = 145
1615
    CEFBS_None, // G_ADDRSPACE_CAST = 146
1616
    CEFBS_None, // G_BLOCK_ADDR = 147
1617
    CEFBS_None, // BRANCH = 148
1618
    CEFBS_None, // BRANCH_COND_f32 = 149
1619
    CEFBS_None, // BRANCH_COND_i32 = 150
1620
    CEFBS_None, // BREAK = 151
1621
    CEFBS_None, // BREAKC_f32 = 152
1622
    CEFBS_None, // BREAKC_i32 = 153
1623
    CEFBS_None, // BREAK_LOGICALNZ_f32 = 154
1624
    CEFBS_None, // BREAK_LOGICALNZ_i32 = 155
1625
    CEFBS_None, // BREAK_LOGICALZ_f32 = 156
1626
    CEFBS_None, // BREAK_LOGICALZ_i32 = 157
1627
    CEFBS_None, // CONST_COPY = 158
1628
    CEFBS_None, // CONTINUE = 159
1629
    CEFBS_None, // CONTINUEC_f32 = 160
1630
    CEFBS_None, // CONTINUEC_i32 = 161
1631
    CEFBS_None, // CONTINUE_LOGICALNZ_f32 = 162
1632
    CEFBS_None, // CONTINUE_LOGICALNZ_i32 = 163
1633
    CEFBS_None, // CONTINUE_LOGICALZ_f32 = 164
1634
    CEFBS_None, // CONTINUE_LOGICALZ_i32 = 165
1635
    CEFBS_None, // CUBE_eg_pseudo = 166
1636
    CEFBS_None, // CUBE_r600_pseudo = 167
1637
    CEFBS_None, // DEFAULT = 168
1638
    CEFBS_None, // DOT_4 = 169
1639
    CEFBS_None, // DUMMY_CHAIN = 170
1640
    CEFBS_None, // ELSE = 171
1641
    CEFBS_None, // END = 172
1642
    CEFBS_None, // ENDFUNC = 173
1643
    CEFBS_None, // ENDIF = 174
1644
    CEFBS_None, // ENDLOOP = 175
1645
    CEFBS_None, // ENDMAIN = 176
1646
    CEFBS_None, // ENDSWITCH = 177
1647
    CEFBS_None, // FABS_R600 = 178
1648
    CEFBS_None, // FNEG_R600 = 179
1649
    CEFBS_None, // FUNC = 180
1650
    CEFBS_None, // IFC_f32 = 181
1651
    CEFBS_None, // IFC_i32 = 182
1652
    CEFBS_None, // IF_LOGICALNZ_f32 = 183
1653
    CEFBS_None, // IF_LOGICALNZ_i32 = 184
1654
    CEFBS_None, // IF_LOGICALZ_f32 = 185
1655
    CEFBS_None, // IF_LOGICALZ_i32 = 186
1656
    CEFBS_None, // IF_PREDICATE_SET = 187
1657
    CEFBS_None, // JUMP = 188
1658
    CEFBS_None, // JUMP_COND = 189
1659
    CEFBS_None, // MASK_WRITE = 190
1660
    CEFBS_None, // MOV_IMM_F32 = 191
1661
    CEFBS_None, // MOV_IMM_GLOBAL_ADDR = 192
1662
    CEFBS_None, // MOV_IMM_I32 = 193
1663
    CEFBS_None, // PRED_X = 194
1664
    CEFBS_None, // R600_EXTRACT_ELT_V2 = 195
1665
    CEFBS_None, // R600_EXTRACT_ELT_V4 = 196
1666
    CEFBS_None, // R600_INSERT_ELT_V2 = 197
1667
    CEFBS_None, // R600_INSERT_ELT_V4 = 198
1668
    CEFBS_None, // R600_RegisterLoad = 199
1669
    CEFBS_None, // R600_RegisterStore = 200
1670
    CEFBS_None, // RETDYN = 201
1671
    CEFBS_None, // RETURN = 202
1672
    CEFBS_None, // TXD = 203
1673
    CEFBS_None, // TXD_SHADOW = 204
1674
    CEFBS_None, // WHILELOOP = 205
1675
    CEFBS_None, // ADD = 206
1676
    CEFBS_None, // ADDC_UINT = 207
1677
    CEFBS_None, // ADD_INT = 208
1678
    CEFBS_None, // ALU_CLAUSE = 209
1679
    CEFBS_None, // AND_INT = 210
1680
    CEFBS_None, // ASHR_eg = 211
1681
    CEFBS_None, // ASHR_r600 = 212
1682
    CEFBS_None, // BCNT_INT = 213
1683
    CEFBS_None, // BFE_INT_eg = 214
1684
    CEFBS_None, // BFE_UINT_eg = 215
1685
    CEFBS_None, // BFI_INT_eg = 216
1686
    CEFBS_None, // BFM_INT_eg = 217
1687
    CEFBS_None, // BIT_ALIGN_INT_eg = 218
1688
    CEFBS_None, // CEIL = 219
1689
    CEFBS_None, // CF_ALU = 220
1690
    CEFBS_None, // CF_ALU_BREAK = 221
1691
    CEFBS_None, // CF_ALU_CONTINUE = 222
1692
    CEFBS_None, // CF_ALU_ELSE_AFTER = 223
1693
    CEFBS_None, // CF_ALU_POP_AFTER = 224
1694
    CEFBS_None, // CF_ALU_PUSH_BEFORE = 225
1695
    CEFBS_None, // CF_CALL_FS_EG = 226
1696
    CEFBS_None, // CF_CALL_FS_R600 = 227
1697
    CEFBS_None, // CF_CONTINUE_EG = 228
1698
    CEFBS_None, // CF_CONTINUE_R600 = 229
1699
    CEFBS_None, // CF_ELSE_EG = 230
1700
    CEFBS_None, // CF_ELSE_R600 = 231
1701
    CEFBS_None, // CF_END_CM = 232
1702
    CEFBS_None, // CF_END_EG = 233
1703
    CEFBS_None, // CF_END_R600 = 234
1704
    CEFBS_None, // CF_JUMP_EG = 235
1705
    CEFBS_None, // CF_JUMP_R600 = 236
1706
    CEFBS_None, // CF_PUSH_EG = 237
1707
    CEFBS_None, // CF_PUSH_ELSE_R600 = 238
1708
    CEFBS_None, // CF_TC_EG = 239
1709
    CEFBS_None, // CF_TC_R600 = 240
1710
    CEFBS_None, // CF_VC_EG = 241
1711
    CEFBS_None, // CF_VC_R600 = 242
1712
    CEFBS_None, // CNDE_INT = 243
1713
    CEFBS_None, // CNDE_eg = 244
1714
    CEFBS_None, // CNDE_r600 = 245
1715
    CEFBS_None, // CNDGE_INT = 246
1716
    CEFBS_None, // CNDGE_eg = 247
1717
    CEFBS_None, // CNDGE_r600 = 248
1718
    CEFBS_None, // CNDGT_INT = 249
1719
    CEFBS_None, // CNDGT_eg = 250
1720
    CEFBS_None, // CNDGT_r600 = 251
1721
    CEFBS_None, // COS_cm = 252
1722
    CEFBS_None, // COS_eg = 253
1723
    CEFBS_None, // COS_r600 = 254
1724
    CEFBS_None, // COS_r700 = 255
1725
    CEFBS_None, // CUBE_eg_real = 256
1726
    CEFBS_None, // CUBE_r600_real = 257
1727
    CEFBS_None, // DOT4_eg = 258
1728
    CEFBS_None, // DOT4_r600 = 259
1729
    CEFBS_None, // EG_ExportBuf = 260
1730
    CEFBS_None, // EG_ExportSwz = 261
1731
    CEFBS_None, // END_LOOP_EG = 262
1732
    CEFBS_None, // END_LOOP_R600 = 263
1733
    CEFBS_None, // EXP_IEEE_cm = 264
1734
    CEFBS_None, // EXP_IEEE_eg = 265
1735
    CEFBS_None, // EXP_IEEE_r600 = 266
1736
    CEFBS_None, // FETCH_CLAUSE = 267
1737
    CEFBS_None, // FFBH_UINT = 268
1738
    CEFBS_None, // FFBL_INT = 269
1739
    CEFBS_None, // FLOOR = 270
1740
    CEFBS_None, // FLT16_TO_FLT32 = 271
1741
    CEFBS_None, // FLT32_TO_FLT16 = 272
1742
    CEFBS_None, // FLT_TO_INT_eg = 273
1743
    CEFBS_None, // FLT_TO_INT_r600 = 274
1744
    CEFBS_None, // FLT_TO_UINT_eg = 275
1745
    CEFBS_None, // FLT_TO_UINT_r600 = 276
1746
    CEFBS_None, // FMA_eg = 277
1747
    CEFBS_None, // FRACT = 278
1748
    CEFBS_None, // GROUP_BARRIER = 279
1749
    CEFBS_None, // INTERP_LOAD_P0 = 280
1750
    CEFBS_None, // INTERP_PAIR_XY = 281
1751
    CEFBS_None, // INTERP_PAIR_ZW = 282
1752
    CEFBS_None, // INTERP_VEC_LOAD = 283
1753
    CEFBS_None, // INTERP_XY = 284
1754
    CEFBS_None, // INTERP_ZW = 285
1755
    CEFBS_None, // INT_TO_FLT_eg = 286
1756
    CEFBS_None, // INT_TO_FLT_r600 = 287
1757
    CEFBS_None, // KILLGT = 288
1758
    CEFBS_None, // LDS_ADD = 289
1759
    CEFBS_None, // LDS_ADD_RET = 290
1760
    CEFBS_None, // LDS_AND = 291
1761
    CEFBS_None, // LDS_AND_RET = 292
1762
    CEFBS_None, // LDS_BYTE_READ_RET = 293
1763
    CEFBS_None, // LDS_BYTE_WRITE = 294
1764
    CEFBS_None, // LDS_CMPST = 295
1765
    CEFBS_None, // LDS_CMPST_RET = 296
1766
    CEFBS_None, // LDS_MAX_INT = 297
1767
    CEFBS_None, // LDS_MAX_INT_RET = 298
1768
    CEFBS_None, // LDS_MAX_UINT = 299
1769
    CEFBS_None, // LDS_MAX_UINT_RET = 300
1770
    CEFBS_None, // LDS_MIN_INT = 301
1771
    CEFBS_None, // LDS_MIN_INT_RET = 302
1772
    CEFBS_None, // LDS_MIN_UINT = 303
1773
    CEFBS_None, // LDS_MIN_UINT_RET = 304
1774
    CEFBS_None, // LDS_OR = 305
1775
    CEFBS_None, // LDS_OR_RET = 306
1776
    CEFBS_None, // LDS_READ_RET = 307
1777
    CEFBS_None, // LDS_SHORT_READ_RET = 308
1778
    CEFBS_None, // LDS_SHORT_WRITE = 309
1779
    CEFBS_None, // LDS_SUB = 310
1780
    CEFBS_None, // LDS_SUB_RET = 311
1781
    CEFBS_None, // LDS_UBYTE_READ_RET = 312
1782
    CEFBS_None, // LDS_USHORT_READ_RET = 313
1783
    CEFBS_None, // LDS_WRITE = 314
1784
    CEFBS_None, // LDS_WRXCHG = 315
1785
    CEFBS_None, // LDS_WRXCHG_RET = 316
1786
    CEFBS_None, // LDS_XOR = 317
1787
    CEFBS_None, // LDS_XOR_RET = 318
1788
    CEFBS_None, // LITERALS = 319
1789
    CEFBS_None, // LOG_CLAMPED_eg = 320
1790
    CEFBS_None, // LOG_CLAMPED_r600 = 321
1791
    CEFBS_None, // LOG_IEEE_cm = 322
1792
    CEFBS_None, // LOG_IEEE_eg = 323
1793
    CEFBS_None, // LOG_IEEE_r600 = 324
1794
    CEFBS_None, // LOOP_BREAK_EG = 325
1795
    CEFBS_None, // LOOP_BREAK_R600 = 326
1796
    CEFBS_None, // LSHL_eg = 327
1797
    CEFBS_None, // LSHL_r600 = 328
1798
    CEFBS_None, // LSHR_eg = 329
1799
    CEFBS_None, // LSHR_r600 = 330
1800
    CEFBS_None, // MAX = 331
1801
    CEFBS_None, // MAX_DX10 = 332
1802
    CEFBS_None, // MAX_INT = 333
1803
    CEFBS_None, // MAX_UINT = 334
1804
    CEFBS_None, // MIN = 335
1805
    CEFBS_None, // MIN_DX10 = 336
1806
    CEFBS_None, // MIN_INT = 337
1807
    CEFBS_None, // MIN_UINT = 338
1808
    CEFBS_None, // MOV = 339
1809
    CEFBS_None, // MOVA_INT_eg = 340
1810
    CEFBS_None, // MUL = 341
1811
    CEFBS_None, // MULADD_IEEE_eg = 342
1812
    CEFBS_None, // MULADD_IEEE_r600 = 343
1813
    CEFBS_None, // MULADD_INT24_cm = 344
1814
    CEFBS_None, // MULADD_UINT24_eg = 345
1815
    CEFBS_None, // MULADD_eg = 346
1816
    CEFBS_None, // MULADD_r600 = 347
1817
    CEFBS_None, // MULHI_INT_cm = 348
1818
    CEFBS_None, // MULHI_INT_cm24 = 349
1819
    CEFBS_None, // MULHI_INT_eg = 350
1820
    CEFBS_None, // MULHI_INT_r600 = 351
1821
    CEFBS_None, // MULHI_UINT24_eg = 352
1822
    CEFBS_None, // MULHI_UINT_cm = 353
1823
    CEFBS_None, // MULHI_UINT_cm24 = 354
1824
    CEFBS_None, // MULHI_UINT_eg = 355
1825
    CEFBS_None, // MULHI_UINT_r600 = 356
1826
    CEFBS_None, // MULLO_INT_cm = 357
1827
    CEFBS_None, // MULLO_INT_eg = 358
1828
    CEFBS_None, // MULLO_INT_r600 = 359
1829
    CEFBS_None, // MULLO_UINT_cm = 360
1830
    CEFBS_None, // MULLO_UINT_eg = 361
1831
    CEFBS_None, // MULLO_UINT_r600 = 362
1832
    CEFBS_None, // MUL_IEEE = 363
1833
    CEFBS_None, // MUL_INT24_cm = 364
1834
    CEFBS_None, // MUL_LIT_eg = 365
1835
    CEFBS_None, // MUL_LIT_r600 = 366
1836
    CEFBS_None, // MUL_UINT24_eg = 367
1837
    CEFBS_None, // NOT_INT = 368
1838
    CEFBS_None, // OR_INT = 369
1839
    CEFBS_None, // PAD = 370
1840
    CEFBS_None, // POP_EG = 371
1841
    CEFBS_None, // POP_R600 = 372
1842
    CEFBS_None, // PRED_SETE = 373
1843
    CEFBS_None, // PRED_SETE_INT = 374
1844
    CEFBS_None, // PRED_SETGE = 375
1845
    CEFBS_None, // PRED_SETGE_INT = 376
1846
    CEFBS_None, // PRED_SETGT = 377
1847
    CEFBS_None, // PRED_SETGT_INT = 378
1848
    CEFBS_None, // PRED_SETNE = 379
1849
    CEFBS_None, // PRED_SETNE_INT = 380
1850
    CEFBS_None, // R600_ExportBuf = 381
1851
    CEFBS_None, // R600_ExportSwz = 382
1852
    CEFBS_None, // RAT_ATOMIC_ADD_NORET = 383
1853
    CEFBS_None, // RAT_ATOMIC_ADD_RTN = 384
1854
    CEFBS_None, // RAT_ATOMIC_AND_NORET = 385
1855
    CEFBS_None, // RAT_ATOMIC_AND_RTN = 386
1856
    CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET = 387
1857
    CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN = 388
1858
    CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET = 389
1859
    CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN = 390
1860
    CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET = 391
1861
    CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN = 392
1862
    CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET = 393
1863
    CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN = 394
1864
    CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET = 395
1865
    CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN = 396
1866
    CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET = 397
1867
    CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN = 398
1868
    CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET = 399
1869
    CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN = 400
1870
    CEFBS_None, // RAT_ATOMIC_OR_NORET = 401
1871
    CEFBS_None, // RAT_ATOMIC_OR_RTN = 402
1872
    CEFBS_None, // RAT_ATOMIC_RSUB_NORET = 403
1873
    CEFBS_None, // RAT_ATOMIC_RSUB_RTN = 404
1874
    CEFBS_None, // RAT_ATOMIC_SUB_NORET = 405
1875
    CEFBS_None, // RAT_ATOMIC_SUB_RTN = 406
1876
    CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET = 407
1877
    CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN = 408
1878
    CEFBS_None, // RAT_ATOMIC_XOR_NORET = 409
1879
    CEFBS_None, // RAT_ATOMIC_XOR_RTN = 410
1880
    CEFBS_None, // RAT_MSKOR = 411
1881
    CEFBS_None, // RAT_STORE_DWORD128 = 412
1882
    CEFBS_None, // RAT_STORE_DWORD32 = 413
1883
    CEFBS_None, // RAT_STORE_DWORD64 = 414
1884
    CEFBS_None, // RAT_STORE_TYPED_cm = 415
1885
    CEFBS_None, // RAT_STORE_TYPED_eg = 416
1886
    CEFBS_None, // RAT_WRITE_CACHELESS_128_eg = 417
1887
    CEFBS_None, // RAT_WRITE_CACHELESS_32_eg = 418
1888
    CEFBS_None, // RAT_WRITE_CACHELESS_64_eg = 419
1889
    CEFBS_None, // RECIPSQRT_CLAMPED_cm = 420
1890
    CEFBS_None, // RECIPSQRT_CLAMPED_eg = 421
1891
    CEFBS_None, // RECIPSQRT_CLAMPED_r600 = 422
1892
    CEFBS_None, // RECIPSQRT_IEEE_cm = 423
1893
    CEFBS_None, // RECIPSQRT_IEEE_eg = 424
1894
    CEFBS_None, // RECIPSQRT_IEEE_r600 = 425
1895
    CEFBS_None, // RECIP_CLAMPED_cm = 426
1896
    CEFBS_None, // RECIP_CLAMPED_eg = 427
1897
    CEFBS_None, // RECIP_CLAMPED_r600 = 428
1898
    CEFBS_None, // RECIP_IEEE_cm = 429
1899
    CEFBS_None, // RECIP_IEEE_eg = 430
1900
    CEFBS_None, // RECIP_IEEE_r600 = 431
1901
    CEFBS_None, // RECIP_UINT_eg = 432
1902
    CEFBS_None, // RECIP_UINT_r600 = 433
1903
    CEFBS_None, // RNDNE = 434
1904
    CEFBS_None, // SETE = 435
1905
    CEFBS_None, // SETE_DX10 = 436
1906
    CEFBS_None, // SETE_INT = 437
1907
    CEFBS_None, // SETGE_DX10 = 438
1908
    CEFBS_None, // SETGE_INT = 439
1909
    CEFBS_None, // SETGE_UINT = 440
1910
    CEFBS_None, // SETGT_DX10 = 441
1911
    CEFBS_None, // SETGT_INT = 442
1912
    CEFBS_None, // SETGT_UINT = 443
1913
    CEFBS_None, // SETNE_DX10 = 444
1914
    CEFBS_None, // SETNE_INT = 445
1915
    CEFBS_None, // SGE = 446
1916
    CEFBS_None, // SGT = 447
1917
    CEFBS_None, // SIN_cm = 448
1918
    CEFBS_None, // SIN_eg = 449
1919
    CEFBS_None, // SIN_r600 = 450
1920
    CEFBS_None, // SIN_r700 = 451
1921
    CEFBS_None, // SNE = 452
1922
    CEFBS_None, // SUBB_UINT = 453
1923
    CEFBS_None, // SUB_INT = 454
1924
    CEFBS_None, // TEX_GET_GRADIENTS_H = 455
1925
    CEFBS_None, // TEX_GET_GRADIENTS_V = 456
1926
    CEFBS_None, // TEX_GET_TEXTURE_RESINFO = 457
1927
    CEFBS_None, // TEX_LD = 458
1928
    CEFBS_None, // TEX_LDPTR = 459
1929
    CEFBS_None, // TEX_SAMPLE = 460
1930
    CEFBS_None, // TEX_SAMPLE_C = 461
1931
    CEFBS_None, // TEX_SAMPLE_C_G = 462
1932
    CEFBS_None, // TEX_SAMPLE_C_L = 463
1933
    CEFBS_None, // TEX_SAMPLE_C_LB = 464
1934
    CEFBS_None, // TEX_SAMPLE_G = 465
1935
    CEFBS_None, // TEX_SAMPLE_L = 466
1936
    CEFBS_None, // TEX_SAMPLE_LB = 467
1937
    CEFBS_None, // TEX_SET_GRADIENTS_H = 468
1938
    CEFBS_None, // TEX_SET_GRADIENTS_V = 469
1939
    CEFBS_None, // TEX_VTX_CONSTBUF = 470
1940
    CEFBS_None, // TEX_VTX_TEXBUF = 471
1941
    CEFBS_None, // TRUNC = 472
1942
    CEFBS_None, // UINT_TO_FLT_eg = 473
1943
    CEFBS_None, // UINT_TO_FLT_r600 = 474
1944
    CEFBS_None, // VTX_READ_128_cm = 475
1945
    CEFBS_None, // VTX_READ_128_eg = 476
1946
    CEFBS_None, // VTX_READ_16_cm = 477
1947
    CEFBS_None, // VTX_READ_16_eg = 478
1948
    CEFBS_None, // VTX_READ_32_cm = 479
1949
    CEFBS_None, // VTX_READ_32_eg = 480
1950
    CEFBS_None, // VTX_READ_64_cm = 481
1951
    CEFBS_None, // VTX_READ_64_eg = 482
1952
    CEFBS_None, // VTX_READ_8_cm = 483
1953
    CEFBS_None, // VTX_READ_8_eg = 484
1954
    CEFBS_None, // WHILE_LOOP_EG = 485
1955
    CEFBS_None, // WHILE_LOOP_R600 = 486
1956
    CEFBS_None, // XOR_INT = 487
1957
  };
1958
1959
  assert(Inst.getOpcode() < 488);
1960
  const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
1961
  FeatureBitset MissingFeatures =
1962
      (AvailableFeatures & RequiredFeatures) ^
1963
      RequiredFeatures;
1964
  if (MissingFeatures.any()) {
1965
    std::ostringstream Msg;
1966
    Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
1967
        << " instruction but the ";
1968
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
1969
      if (MissingFeatures.test(i))
1970
        Msg << SubtargetFeatureNames[i] << " ";
1971
    Msg << "predicate(s) are not met";
1972
    report_fatal_error(Msg.str());
1973
  }
1974
#else
1975
// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF).
1976
315
(void)MCII;
1977
315
#endif // NDEBUG
1978
315
}
1979
#endif