Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/AMDGPU/R600GenSubtargetInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Subtarget Enumeration Source Fragment                                      *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_SUBTARGETINFO_ENUM
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#undef GET_SUBTARGETINFO_ENUM
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namespace llvm {
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namespace R600 {
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enum {
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  FeatureCFALUBug = 0,
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  FeatureCaymanISA = 1,
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  FeatureDX10Clamp = 2,
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  FeatureEvergreen = 3,
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  FeatureFMA = 4,
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  FeatureFP64 = 5,
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  FeatureFetchLimit8 = 6,
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  FeatureFetchLimit16 = 7,
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  FeatureLocalMemorySize0 = 8,
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  FeatureLocalMemorySize32768 = 9,
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  FeatureLocalMemorySize65536 = 10,
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  FeatureNorthernIslands = 11,
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  FeaturePromoteAlloca = 12,
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  FeatureR600 = 13,
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  FeatureR600ALUInst = 14,
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  FeatureR700 = 15,
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  FeatureVertexCache = 16,
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  FeatureWavefrontSize16 = 17,
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  FeatureWavefrontSize32 = 18,
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  FeatureWavefrontSize64 = 19,
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};
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} // end namespace R600
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_ENUM
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#ifdef GET_SUBTARGETINFO_MC_DESC
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#undef GET_SUBTARGETINFO_MC_DESC
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namespace llvm {
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// Sorted (by key) array of values for CPU features.
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extern const llvm::SubtargetFeatureKV R600FeatureKV[] = {
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  { "EVERGREEN", "EVERGREEN GPU generation", { R600::FeatureEvergreen }, { R600::FeatureFetchLimit16, R600::FeatureLocalMemorySize32768 } },
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  { "HasVertexCache", "Specify use of dedicated vertex cache", { R600::FeatureVertexCache }, { } },
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  { "NORTHERN_ISLANDS", "NORTHERN_ISLANDS GPU generation", { R600::FeatureNorthernIslands }, { R600::FeatureFetchLimit16, R600::FeatureWavefrontSize64, R600::FeatureLocalMemorySize32768 } },
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  { "R600", "R600 GPU generation", { R600::FeatureR600 }, { R600::FeatureR600ALUInst, R600::FeatureFetchLimit8, R600::FeatureLocalMemorySize0 } },
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  { "R600ALUInst", "Older version of ALU instructions encoding", { R600::FeatureR600ALUInst }, { } },
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  { "R700", "R700 GPU generation", { R600::FeatureR700 }, { R600::FeatureFetchLimit16, R600::FeatureLocalMemorySize0 } },
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  { "caymanISA", "Use Cayman ISA", { R600::FeatureCaymanISA }, { } },
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  { "cfalubug", "GPU has CF_ALU bug", { R600::FeatureCFALUBug }, { } },
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  { "dx10-clamp", "clamp modifier clamps NaNs to 0.0", { R600::FeatureDX10Clamp }, { } },
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  { "fetch16", "Limit the maximum number of fetches in a clause to 16", { R600::FeatureFetchLimit16 }, { } },
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  { "fetch8", "Limit the maximum number of fetches in a clause to 8", { R600::FeatureFetchLimit8 }, { } },
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  { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", { R600::FeatureFMA }, { } },
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  { "fp64", "Enable double precision operations", { R600::FeatureFP64 }, { } },
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  { "localmemorysize0", "The size of local memory in bytes", { R600::FeatureLocalMemorySize0 }, { } },
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  { "localmemorysize32768", "The size of local memory in bytes", { R600::FeatureLocalMemorySize32768 }, { } },
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  { "localmemorysize65536", "The size of local memory in bytes", { R600::FeatureLocalMemorySize65536 }, { } },
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  { "promote-alloca", "Enable promote alloca pass", { R600::FeaturePromoteAlloca }, { } },
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  { "wavefrontsize16", "The number of threads per wavefront", { R600::FeatureWavefrontSize16 }, { } },
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  { "wavefrontsize32", "The number of threads per wavefront", { R600::FeatureWavefrontSize32 }, { } },
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  { "wavefrontsize64", "The number of threads per wavefront", { R600::FeatureWavefrontSize64 }, { } },
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};
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// Sorted (by key) array of values for CPU subtype.
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extern const llvm::SubtargetFeatureKV R600SubTypeKV[] = {
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  { "barts", "Select the barts processor", { R600::FeatureNorthernIslands, R600::FeatureVertexCache, R600::FeatureCFALUBug }, { } },
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  { "caicos", "Select the caicos processor", { R600::FeatureNorthernIslands, R600::FeatureCFALUBug }, { } },
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  { "cayman", "Select the cayman processor", { R600::FeatureNorthernIslands, R600::FeatureCaymanISA, R600::FeatureFMA }, { } },
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  { "cedar", "Select the cedar processor", { R600::FeatureEvergreen, R600::FeatureWavefrontSize32, R600::FeatureVertexCache, R600::FeatureCFALUBug }, { } },
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  { "cypress", "Select the cypress processor", { R600::FeatureEvergreen, R600::FeatureWavefrontSize64, R600::FeatureVertexCache, R600::FeatureFMA }, { } },
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  { "juniper", "Select the juniper processor", { R600::FeatureEvergreen, R600::FeatureWavefrontSize64, R600::FeatureVertexCache }, { } },
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  { "r600", "Select the r600 processor", { R600::FeatureR600, R600::FeatureWavefrontSize64, R600::FeatureVertexCache }, { } },
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  { "r630", "Select the r630 processor", { R600::FeatureR600, R600::FeatureWavefrontSize32, R600::FeatureVertexCache }, { } },
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  { "redwood", "Select the redwood processor", { R600::FeatureEvergreen, R600::FeatureWavefrontSize64, R600::FeatureVertexCache, R600::FeatureCFALUBug }, { } },
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  { "rs880", "Select the rs880 processor", { R600::FeatureR600, R600::FeatureWavefrontSize16 }, { } },
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  { "rv670", "Select the rv670 processor", { R600::FeatureR600, R600::FeatureWavefrontSize64, R600::FeatureVertexCache }, { } },
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  { "rv710", "Select the rv710 processor", { R600::FeatureR700, R600::FeatureWavefrontSize32, R600::FeatureVertexCache }, { } },
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  { "rv730", "Select the rv730 processor", { R600::FeatureR700, R600::FeatureWavefrontSize32, R600::FeatureVertexCache }, { } },
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  { "rv770", "Select the rv770 processor", { R600::FeatureR700, R600::FeatureWavefrontSize64, R600::FeatureVertexCache }, { } },
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  { "sumo", "Select the sumo processor", { R600::FeatureEvergreen, R600::FeatureWavefrontSize64, R600::FeatureCFALUBug }, { } },
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  { "turks", "Select the turks processor", { R600::FeatureNorthernIslands, R600::FeatureVertexCache, R600::FeatureCFALUBug }, { } },
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};
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#ifdef DBGFIELD
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#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
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#endif
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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#define DBGFIELD(x) x,
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#else
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#define DBGFIELD(x)
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#endif
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// Functional units for "R600_VLIW5_Itin"
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namespace R600_VLIW5_ItinFU {
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  const unsigned ALU_X = 1 << 0;
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  const unsigned ALU_Y = 1 << 1;
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  const unsigned ALU_Z = 1 << 2;
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  const unsigned ALU_W = 1 << 3;
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  const unsigned TRANS = 1 << 4;
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  const unsigned ALU_NULL = 1 << 5;
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} // end namespace R600_VLIW5_ItinFU
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// Functional units for "R600_VLIW4_Itin"
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namespace R600_VLIW4_ItinFU {
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  const unsigned ALU_X = 1 << 0;
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  const unsigned ALU_Y = 1 << 1;
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  const unsigned ALU_Z = 1 << 2;
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  const unsigned ALU_W = 1 << 3;
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  const unsigned ALU_NULL = 1 << 4;
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} // end namespace R600_VLIW4_ItinFU
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extern const llvm::InstrStage R600Stages[] = {
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  { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
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  { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
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  { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
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  { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
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  { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
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  { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
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  { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
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  { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
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  { 0, 0, 0, llvm::InstrStage::Required } // End stages
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};
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extern const unsigned R600OperandCycles[] = {
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  0, // No itinerary
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  0 // End operand cycles
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};
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extern const unsigned R600ForwardingPaths[] = {
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 0, // No itinerary
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 0 // End bypass tables
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};
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static const llvm::InstrItinerary R600_VLIW5_Itin[] = {
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  { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
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  { 1, 1, 2, 0, 0 }, // 1 NullALU
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  { 1, 2, 3, 0, 0 }, // 2 VecALU
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  { 1, 3, 4, 0, 0 }, // 3 AnyALU
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  { 1, 4, 5, 0, 0 }, // 4 TransALU
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  { 1, 5, 6, 0, 0 }, // 5 XALU
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  { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
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};
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static const llvm::InstrItinerary R600_VLIW4_Itin[] = {
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  { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
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  { 1, 6, 7, 0, 0 }, // 1 NullALU
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  { 1, 7, 8, 0, 0 }, // 2 VecALU
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  { 1, 7, 8, 0, 0 }, // 3 AnyALU
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  { 1, 6, 7, 0, 0 }, // 4 TransALU
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  { 0, 0, 0, 0, 0 }, // 5 XALU
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  { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
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};
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// ===============================================================
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// Data tables for the new per-operand machine model.
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// {ProcResourceIdx, Cycles}
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extern const llvm::MCWriteProcResEntry R600WriteProcResTable[] = {
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  { 0,  0}, // Invalid
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}; // R600WriteProcResTable
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// {Cycles, WriteResourceID}
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extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[] = {
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  { 0,  0}, // Invalid
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}; // R600WriteLatencyTable
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// {UseIdx, WriteResourceID, Cycles}
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extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[] = {
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  {0,  0,  0}, // Invalid
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}; // R600ReadAdvanceTable
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static const llvm::MCSchedModel NoSchedModel = {
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  MCSchedModel::DefaultIssueWidth,
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  MCSchedModel::DefaultMicroOpBufferSize,
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  MCSchedModel::DefaultLoopMicroOpBufferSize,
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  MCSchedModel::DefaultLoadLatency,
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  MCSchedModel::DefaultHighLatency,
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  MCSchedModel::DefaultMispredictPenalty,
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  false, // PostRAScheduler
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  false, // CompleteModel
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  0, // Processor ID
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  nullptr, nullptr, 0, 0, // No instruction-level machine model.
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  nullptr, // No Itinerary
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  nullptr // No extra processor descriptor
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};
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static const llvm::MCSchedModel R600_VLIW5_ItinModel = {
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  MCSchedModel::DefaultIssueWidth,
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  MCSchedModel::DefaultMicroOpBufferSize,
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  MCSchedModel::DefaultLoopMicroOpBufferSize,
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  MCSchedModel::DefaultLoadLatency,
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  MCSchedModel::DefaultHighLatency,
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  MCSchedModel::DefaultMispredictPenalty,
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  false, // PostRAScheduler
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  false, // CompleteModel
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  1, // Processor ID
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  nullptr, nullptr, 0, 0, // No instruction-level machine model.
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  R600_VLIW5_Itin,
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  nullptr // No extra processor descriptor
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};
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static const llvm::MCSchedModel R600_VLIW4_ItinModel = {
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  MCSchedModel::DefaultIssueWidth,
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  MCSchedModel::DefaultMicroOpBufferSize,
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  MCSchedModel::DefaultLoopMicroOpBufferSize,
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  MCSchedModel::DefaultLoadLatency,
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  MCSchedModel::DefaultHighLatency,
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  MCSchedModel::DefaultMispredictPenalty,
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  false, // PostRAScheduler
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  false, // CompleteModel
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  2, // Processor ID
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  nullptr, nullptr, 0, 0, // No instruction-level machine model.
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  R600_VLIW4_Itin,
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  nullptr // No extra processor descriptor
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};
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// Sorted (by key) array of itineraries for CPU subtype.
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extern const llvm::SubtargetInfoKV R600ProcSchedKV[] = {
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  { "barts", (const void *)&R600_VLIW5_ItinModel },
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  { "caicos", (const void *)&R600_VLIW5_ItinModel },
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  { "cayman", (const void *)&R600_VLIW4_ItinModel },
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  { "cedar", (const void *)&R600_VLIW5_ItinModel },
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  { "cypress", (const void *)&R600_VLIW5_ItinModel },
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  { "juniper", (const void *)&R600_VLIW5_ItinModel },
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  { "r600", (const void *)&R600_VLIW5_ItinModel },
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  { "r630", (const void *)&R600_VLIW5_ItinModel },
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  { "redwood", (const void *)&R600_VLIW5_ItinModel },
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  { "rs880", (const void *)&R600_VLIW5_ItinModel },
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  { "rv670", (const void *)&R600_VLIW5_ItinModel },
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  { "rv710", (const void *)&R600_VLIW5_ItinModel },
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  { "rv730", (const void *)&R600_VLIW5_ItinModel },
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  { "rv770", (const void *)&R600_VLIW5_ItinModel },
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  { "sumo", (const void *)&R600_VLIW5_ItinModel },
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  { "turks", (const void *)&R600_VLIW5_ItinModel },
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};
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#undef DBGFIELD
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namespace R600_MC {
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unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
245
0
    const MCInst *MI, unsigned CPUID) {
246
0
  // Don't know how to resolve this scheduling class.
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0
  return 0;
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0
}
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} // end of namespace R600_MC
250
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struct R600GenMCSubtargetInfo : public MCSubtargetInfo {
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  R600GenMCSubtargetInfo(const Triple &TT, 
253
    StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
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    ArrayRef<SubtargetFeatureKV> PD,
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    const SubtargetInfoKV *ProcSched,
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    const MCWriteProcResEntry *WPR,
257
    const MCWriteLatencyEntry *WL,
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    const MCReadAdvanceEntry *RA, const InstrStage *IS,
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    const unsigned *OC, const unsigned *FP) :
260
      MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
261
291
                      WPR, WL, RA, IS, OC, FP) { }
262
263
  unsigned resolveVariantSchedClass(unsigned SchedClass,
264
0
      const MCInst *MI, unsigned CPUID) const override {
265
0
    return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 
266
0
  }
267
};
268
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static inline MCSubtargetInfo *createR600MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
270
291
  return new R600GenMCSubtargetInfo(TT, CPU, FS, R600FeatureKV, R600SubTypeKV, 
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                      R600ProcSchedKV, R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable, 
272
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                      R600Stages, R600OperandCycles, R600ForwardingPaths);
273
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}
274
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_MC_DESC
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#ifdef GET_SUBTARGETINFO_TARGET_DESC
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#undef GET_SUBTARGETINFO_TARGET_DESC
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#include "llvm/Support/Debug.h"
284
#include "llvm/Support/raw_ostream.h"
285
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// ParseSubtargetFeatures - Parses features string setting specified
287
// subtarget options.
288
286
void llvm::R600Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
289
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  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
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  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
291
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  InitMCProcessorInfo(CPU, FS);
292
286
  const FeatureBitset& Bits = getFeatureBits();
293
286
  if (Bits[R600::FeatureCFALUBug]) 
CFALUBug = true172
;
294
286
  if (Bits[R600::FeatureCaymanISA]) 
CaymanISA = true33
;
295
286
  if (Bits[R600::FeatureDX10Clamp]) DX10Clamp = true;
296
286
  if (Bits[R600::FeatureEvergreen] && 
Gen < R600Subtarget::EVERGREEN214
)
Gen = R600Subtarget::EVERGREEN214
;
297
286
  if (Bits[R600::FeatureFMA]) 
FMA = true80
;
298
286
  if (Bits[R600::FeatureFP64]) 
FP64 = true0
;
299
286
  if (Bits[R600::FeatureFetchLimit8] && 
TexVTXClauseSize < 819
)
TexVTXClauseSize = 819
;
300
286
  if (Bits[R600::FeatureFetchLimit16] && 
TexVTXClauseSize < 16266
)
TexVTXClauseSize = 16266
;
301
286
  if (Bits[R600::FeatureLocalMemorySize0] && 
LocalMemorySize < 027
)
LocalMemorySize = 00
;
302
286
  if (Bits[R600::FeatureLocalMemorySize32768] && 
LocalMemorySize < 32768258
)
LocalMemorySize = 32768258
;
303
286
  if (Bits[R600::FeatureLocalMemorySize65536] && 
LocalMemorySize < 655360
)
LocalMemorySize = 655360
;
304
286
  if (Bits[R600::FeatureNorthernIslands] && 
Gen < R600Subtarget::NORTHERN_ISLANDS44
)
Gen = R600Subtarget::NORTHERN_ISLANDS44
;
305
286
  if (Bits[R600::FeaturePromoteAlloca]) 
EnablePromoteAlloca = true285
;
306
286
  if (Bits[R600::FeatureR600] && 
Gen < R600Subtarget::R60019
)
Gen = R600Subtarget::R6000
;
307
286
  if (Bits[R600::FeatureR600ALUInst]) 
R600ALUInst = false19
;
308
286
  if (Bits[R600::FeatureR700] && 
Gen < R600Subtarget::R7008
)
Gen = R600Subtarget::R7008
;
309
286
  if (Bits[R600::FeatureVertexCache]) 
HasVertexCache = true241
;
310
286
  if (Bits[R600::FeatureWavefrontSize16] && 
WavefrontSize < 164
)
WavefrontSize = 164
;
311
286
  if (Bits[R600::FeatureWavefrontSize32] && 
WavefrontSize < 3212
)
WavefrontSize = 3212
;
312
286
  if (Bits[R600::FeatureWavefrontSize64] && 
WavefrontSize < 64269
)
WavefrontSize = 64269
;
313
286
}
314
#endif // GET_SUBTARGETINFO_TARGET_DESC
315
316
317
#ifdef GET_SUBTARGETINFO_HEADER
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#undef GET_SUBTARGETINFO_HEADER
319
320
namespace llvm {
321
class DFAPacketizer;
322
namespace R600_MC {
323
unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
324
}
325
326
struct R600GenSubtargetInfo : public TargetSubtargetInfo {
327
  explicit R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
328
public:
329
  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
330
  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
331
  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
332
};
333
} // end namespace llvm
334
335
#endif // GET_SUBTARGETINFO_HEADER
336
337
338
#ifdef GET_SUBTARGETINFO_CTOR
339
#undef GET_SUBTARGETINFO_CTOR
340
341
#include "llvm/CodeGen/TargetSchedule.h"
342
343
namespace llvm {
344
extern const llvm::SubtargetFeatureKV R600FeatureKV[];
345
extern const llvm::SubtargetFeatureKV R600SubTypeKV[];
346
extern const llvm::SubtargetInfoKV R600ProcSchedKV[];
347
extern const llvm::MCWriteProcResEntry R600WriteProcResTable[];
348
extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[];
349
extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[];
350
extern const llvm::InstrStage R600Stages[];
351
extern const unsigned R600OperandCycles[];
352
extern const unsigned R600ForwardingPaths[];
353
R600GenSubtargetInfo::R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
354
  : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(R600FeatureKV, 20), makeArrayRef(R600SubTypeKV, 16), 
355
                        R600ProcSchedKV, R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable, 
356
286
                        R600Stages, R600OperandCycles, R600ForwardingPaths) {}
357
358
unsigned R600GenSubtargetInfo
359
0
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
360
0
  report_fatal_error("Expected a variant SchedClass");
361
0
} // R600GenSubtargetInfo::resolveSchedClass
362
363
unsigned R600GenSubtargetInfo
364
0
::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
365
0
  return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
366
0
} // R600GenSubtargetInfo::resolveVariantSchedClass
367
} // end namespace llvm
368
369
#endif // GET_SUBTARGETINFO_CTOR
370