Coverage Report

Created: 2018-12-11 00:00

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenAsmMatcher.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Matcher Source Fragment                                           *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_ASSEMBLER_HEADER
11
#undef GET_ASSEMBLER_HEADER
12
  // This should be included into the middle of the declaration of
13
  // your subclasses implementation of MCTargetAsmParser.
14
  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15
  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16
                       const OperandVector &Operands);
17
  void convertToMapAndConstraints(unsigned Kind,
18
                           const OperandVector &Operands) override;
19
  unsigned MatchInstructionImpl(const OperandVector &Operands,
20
                                MCInst &Inst,
21
                                SmallVectorImpl<NearMissInfo> *NearMisses,
22
                                bool matchingInlineAsm,
23
                                unsigned VariantID = 0);
24
  OperandMatchResultTy MatchOperandParserImpl(
25
    OperandVector &Operands,
26
    StringRef Mnemonic,
27
    bool ParseForAllFeatures = false);
28
  OperandMatchResultTy tryCustomParseOperand(
29
    OperandVector &Operands,
30
    unsigned MCK);
31
32
#endif // GET_ASSEMBLER_HEADER_INFO
33
34
35
#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
36
#undef GET_OPERAND_DIAGNOSTIC_TYPES
37
38
  Match_AlignedMemory16,
39
  Match_AlignedMemory32,
40
  Match_AlignedMemory64,
41
  Match_AlignedMemory64or128,
42
  Match_AlignedMemory64or128or256,
43
  Match_AlignedMemoryNone,
44
  Match_ComplexRotationEven,
45
  Match_ComplexRotationOdd,
46
  Match_DPR,
47
  Match_DPR_8,
48
  Match_DPR_RegList,
49
  Match_DPR_VFP2,
50
  Match_DupAlignedMemory16,
51
  Match_DupAlignedMemory32,
52
  Match_DupAlignedMemory64,
53
  Match_DupAlignedMemory64or128,
54
  Match_DupAlignedMemoryNone,
55
  Match_GPR,
56
  Match_GPRnopc,
57
  Match_GPRsp,
58
  Match_GPRwithAPSR,
59
  Match_Imm0_1,
60
  Match_Imm0_15,
61
  Match_Imm0_239,
62
  Match_Imm0_255,
63
  Match_Imm0_3,
64
  Match_Imm0_31,
65
  Match_Imm0_32,
66
  Match_Imm0_4095,
67
  Match_Imm0_63,
68
  Match_Imm0_65535,
69
  Match_Imm0_65535Expr,
70
  Match_Imm0_7,
71
  Match_Imm16,
72
  Match_Imm1_15,
73
  Match_Imm1_31,
74
  Match_Imm1_7,
75
  Match_Imm24bit,
76
  Match_Imm256_65535Expr,
77
  Match_Imm32,
78
  Match_Imm8,
79
  Match_Imm8_255,
80
  Match_ImmRange1_16,
81
  Match_ImmRange1_32,
82
  Match_ImmThumbSR,
83
  Match_PKHLSLImm,
84
  Match_QPR,
85
  Match_QPR_8,
86
  Match_QPR_VFP2,
87
  Match_SPR,
88
  Match_SPRRegList,
89
  Match_SPR_8,
90
  Match_SetEndImm,
91
  Match_ShrImm16,
92
  Match_ShrImm32,
93
  Match_ShrImm64,
94
  Match_ShrImm8,
95
  Match_hGPR,
96
  Match_rGPR,
97
  Match_tGPR,
98
  END_OPERAND_DIAGNOSTIC_TYPES
99
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
100
101
102
#ifdef GET_REGISTER_MATCHER
103
#undef GET_REGISTER_MATCHER
104
105
// Flags for subtarget features that participate in instruction matching.
106
enum SubtargetFeatureFlag : uint64_t {
107
  Feature_HasV4T = (1ULL << 22),
108
  Feature_HasV5T = (1ULL << 23),
109
  Feature_HasV5TE = (1ULL << 24),
110
  Feature_HasV6 = (1ULL << 25),
111
  Feature_HasV6M = (1ULL << 27),
112
  Feature_HasV8MBaseline = (1ULL << 32),
113
  Feature_HasV8MMainline = (1ULL << 33),
114
  Feature_HasV6T2 = (1ULL << 28),
115
  Feature_HasV6K = (1ULL << 26),
116
  Feature_HasV7 = (1ULL << 29),
117
  Feature_HasV8 = (1ULL << 31),
118
  Feature_PreV8 = (1ULL << 48),
119
  Feature_HasV8_1a = (1ULL << 34),
120
  Feature_HasV8_2a = (1ULL << 35),
121
  Feature_HasV8_3a = (1ULL << 36),
122
  Feature_HasV8_4a = (1ULL << 37),
123
  Feature_HasV8_5a = (1ULL << 38),
124
  Feature_HasVFP2 = (1ULL << 39),
125
  Feature_HasVFP3 = (1ULL << 40),
126
  Feature_HasVFP4 = (1ULL << 41),
127
  Feature_HasDPVFP = (1ULL << 7),
128
  Feature_HasFPARMv8 = (1ULL << 14),
129
  Feature_HasNEON = (1ULL << 17),
130
  Feature_HasSHA2 = (1ULL << 19),
131
  Feature_HasAES = (1ULL << 1),
132
  Feature_HasCrypto = (1ULL << 4),
133
  Feature_HasDotProd = (1ULL << 11),
134
  Feature_HasCRC = (1ULL << 3),
135
  Feature_HasRAS = (1ULL << 18),
136
  Feature_HasFP16 = (1ULL << 12),
137
  Feature_HasFullFP16 = (1ULL << 15),
138
  Feature_HasFP16FML = (1ULL << 13),
139
  Feature_HasDivideInThumb = (1ULL << 10),
140
  Feature_HasDivideInARM = (1ULL << 9),
141
  Feature_HasDSP = (1ULL << 8),
142
  Feature_HasDB = (1ULL << 5),
143
  Feature_HasDFB = (1ULL << 6),
144
  Feature_HasV7Clrex = (1ULL << 30),
145
  Feature_HasAcquireRelease = (1ULL << 2),
146
  Feature_HasMP = (1ULL << 16),
147
  Feature_HasVirtualization = (1ULL << 42),
148
  Feature_HasTrustZone = (1ULL << 21),
149
  Feature_Has8MSecExt = (1ULL << 0),
150
  Feature_IsThumb = (1ULL << 46),
151
  Feature_IsThumb2 = (1ULL << 47),
152
  Feature_IsMClass = (1ULL << 44),
153
  Feature_IsNotMClass = (1ULL << 45),
154
  Feature_IsARM = (1ULL << 43),
155
  Feature_UseNaClTrap = (1ULL << 49),
156
  Feature_UseNegativeImmediates = (1ULL << 50),
157
  Feature_HasSpecCtrl = (1ULL << 20),
158
  Feature_None = 0
159
};
160
161
68.3k
static unsigned MatchRegisterName(StringRef Name) {
162
68.3k
  switch (Name.size()) {
163
68.3k
  
default: break87
;
164
68.3k
  case 2:  // 43 strings to match.
165
59.2k
    switch (Name[0]) {
166
59.2k
    
default: break702
;
167
59.2k
    case 'd':  // 10 strings to match.
168
10.9k
      switch (Name[1]) {
169
10.9k
      
default: break0
;
170
10.9k
      case '0':  // 1 string to match.
171
3.86k
        return 14;  // "d0"
172
10.9k
      case '1':  // 1 string to match.
173
2.18k
        return 15;  // "d1"
174
10.9k
      case '2':  // 1 string to match.
175
2.39k
        return 16;  // "d2"
176
10.9k
      case '3':  // 1 string to match.
177
784
        return 17;  // "d3"
178
10.9k
      case '4':  // 1 string to match.
179
689
        return 18;  // "d4"
180
10.9k
      case '5':  // 1 string to match.
181
149
        return 19;  // "d5"
182
10.9k
      case '6':  // 1 string to match.
183
476
        return 20;  // "d6"
184
10.9k
      case '7':  // 1 string to match.
185
281
        return 21;  // "d7"
186
10.9k
      case '8':  // 1 string to match.
187
95
        return 22;  // "d8"
188
10.9k
      case '9':  // 1 string to match.
189
83
        return 23;  // "d9"
190
0
      }
191
0
      break;
192
1.96k
    case 'l':  // 1 string to match.
193
1.96k
      if (Name[1] != 'r')
194
10
        break;
195
1.95k
      return 10;   // "lr"
196
1.95k
    case 'p':  // 1 string to match.
197
848
      if (Name[1] != 'c')
198
21
        break;
199
827
      return 11;   // "pc"
200
3.97k
    case 'q':  // 10 strings to match.
201
3.97k
      switch (Name[1]) {
202
3.97k
      
default: break0
;
203
3.97k
      case '0':  // 1 string to match.
204
702
        return 50;  // "q0"
205
3.97k
      case '1':  // 1 string to match.
206
633
        return 51;  // "q1"
207
3.97k
      case '2':  // 1 string to match.
208
416
        return 52;  // "q2"
209
3.97k
      case '3':  // 1 string to match.
210
176
        return 53;  // "q3"
211
3.97k
      case '4':  // 1 string to match.
212
208
        return 54;  // "q4"
213
3.97k
      case '5':  // 1 string to match.
214
114
        return 55;  // "q5"
215
3.97k
      case '6':  // 1 string to match.
216
92
        return 56;  // "q6"
217
3.97k
      case '7':  // 1 string to match.
218
100
        return 57;  // "q7"
219
3.97k
      case '8':  // 1 string to match.
220
1.19k
        return 58;  // "q8"
221
3.97k
      case '9':  // 1 string to match.
222
342
        return 59;  // "q9"
223
0
      }
224
0
      break;
225
37.5k
    case 'r':  // 10 strings to match.
226
37.5k
      switch (Name[1]) {
227
37.5k
      
default: break0
;
228
37.5k
      case '0':  // 1 string to match.
229
10.8k
        return 66;  // "r0"
230
37.5k
      case '1':  // 1 string to match.
231
5.01k
        return 67;  // "r1"
232
37.5k
      case '2':  // 1 string to match.
233
3.90k
        return 68;  // "r2"
234
37.5k
      case '3':  // 1 string to match.
235
3.87k
        return 69;  // "r3"
236
37.5k
      case '4':  // 1 string to match.
237
4.90k
        return 70;  // "r4"
238
37.5k
      case '5':  // 1 string to match.
239
2.33k
        return 71;  // "r5"
240
37.5k
      case '6':  // 1 string to match.
241
2.79k
        return 72;  // "r6"
242
37.5k
      case '7':  // 1 string to match.
243
1.65k
        return 73;  // "r7"
244
37.5k
      case '8':  // 1 string to match.
245
1.51k
        return 74;  // "r8"
246
37.5k
      case '9':  // 1 string to match.
247
769
        return 75;  // "r9"
248
0
      }
249
0
      break;
250
3.22k
    case 's':  // 11 strings to match.
251
3.22k
      switch (Name[1]) {
252
3.22k
      
default: break5
;
253
3.22k
      case '0':  // 1 string to match.
254
1.33k
        return 79;  // "s0"
255
3.22k
      case '1':  // 1 string to match.
256
322
        return 80;  // "s1"
257
3.22k
      case '2':  // 1 string to match.
258
195
        return 81;  // "s2"
259
3.22k
      case '3':  // 1 string to match.
260
71
        return 82;  // "s3"
261
3.22k
      case '4':  // 1 string to match.
262
90
        return 83;  // "s4"
263
3.22k
      case '5':  // 1 string to match.
264
33
        return 84;  // "s5"
265
3.22k
      case '6':  // 1 string to match.
266
37
        return 85;  // "s6"
267
3.22k
      case '7':  // 1 string to match.
268
29
        return 86;  // "s7"
269
3.22k
      case '8':  // 1 string to match.
270
25
        return 87;  // "s8"
271
3.22k
      case '9':  // 1 string to match.
272
17
        return 88;  // "s9"
273
3.22k
      case 'p':  // 1 string to match.
274
1.07k
        return 12;  // "sp"
275
5
      }
276
5
      break;
277
738
    }
278
738
    break;
279
8.49k
  case 3:  // 53 strings to match.
280
8.49k
    switch (Name[0]) {
281
8.49k
    
default: break2.07k
;
282
8.49k
    case 'd':  // 22 strings to match.
283
3.54k
      switch (Name[1]) {
284
3.54k
      
default: break0
;
285
3.54k
      case '1':  // 10 strings to match.
286
3.15k
        switch (Name[2]) {
287
3.15k
        
default: break0
;
288
3.15k
        case '0':  // 1 string to match.
289
75
          return 24;  // "d10"
290
3.15k
        case '1':  // 1 string to match.
291
85
          return 25;  // "d11"
292
3.15k
        case '2':  // 1 string to match.
293
111
          return 26;  // "d12"
294
3.15k
        case '3':  // 1 string to match.
295
66
          return 27;  // "d13"
296
3.15k
        case '4':  // 1 string to match.
297
66
          return 28;  // "d14"
298
3.15k
        case '5':  // 1 string to match.
299
60
          return 29;  // "d15"
300
3.15k
        case '6':  // 1 string to match.
301
1.51k
          return 30;  // "d16"
302
3.15k
        case '7':  // 1 string to match.
303
663
          return 31;  // "d17"
304
3.15k
        case '8':  // 1 string to match.
305
317
          return 32;  // "d18"
306
3.15k
        case '9':  // 1 string to match.
307
202
          return 33;  // "d19"
308
0
        }
309
0
        break;
310
347
      case '2':  // 10 strings to match.
311
347
        switch (Name[2]) {
312
347
        
default: break0
;
313
347
        case '0':  // 1 string to match.
314
86
          return 34;  // "d20"
315
347
        case '1':  // 1 string to match.
316
74
          return 35;  // "d21"
317
347
        case '2':  // 1 string to match.
318
57
          return 36;  // "d22"
319
347
        case '3':  // 1 string to match.
320
56
          return 37;  // "d23"
321
347
        case '4':  // 1 string to match.
322
20
          return 38;  // "d24"
323
347
        case '5':  // 1 string to match.
324
12
          return 39;  // "d25"
325
347
        case '6':  // 1 string to match.
326
16
          return 40;  // "d26"
327
347
        case '7':  // 1 string to match.
328
10
          return 41;  // "d27"
329
347
        case '8':  // 1 string to match.
330
8
          return 42;  // "d28"
331
347
        case '9':  // 1 string to match.
332
8
          return 43;  // "d29"
333
0
        }
334
0
        break;
335
39
      case '3':  // 2 strings to match.
336
39
        switch (Name[2]) {
337
39
        
default: break0
;
338
39
        case '0':  // 1 string to match.
339
19
          return 44;  // "d30"
340
39
        case '1':  // 1 string to match.
341
20
          return 45;  // "d31"
342
0
        }
343
0
        break;
344
0
      }
345
0
      break;
346
151
    case 'q':  // 6 strings to match.
347
151
      if (Name[1] != '1')
348
0
        break;
349
151
      switch (Name[2]) {
350
151
      
default: break0
;
351
151
      case '0':  // 1 string to match.
352
52
        return 60;  // "q10"
353
151
      case '1':  // 1 string to match.
354
27
        return 61;  // "q11"
355
151
      case '2':  // 1 string to match.
356
27
        return 62;  // "q12"
357
151
      case '3':  // 1 string to match.
358
17
        return 63;  // "q13"
359
151
      case '4':  // 1 string to match.
360
19
        return 64;  // "q14"
361
151
      case '5':  // 1 string to match.
362
9
        return 65;  // "q15"
363
0
      }
364
0
      break;
365
2.19k
    case 'r':  // 3 strings to match.
366
2.19k
      if (Name[1] != '1')
367
214
        break;
368
1.98k
      switch (Name[2]) {
369
1.98k
      
default: break48
;
370
1.98k
      case '0':  // 1 string to match.
371
422
        return 76;  // "r10"
372
1.98k
      case '1':  // 1 string to match.
373
350
        return 77;  // "r11"
374
1.98k
      case '2':  // 1 string to match.
375
1.16k
        return 78;  // "r12"
376
48
      }
377
48
      break;
378
527
    case 's':  // 22 strings to match.
379
527
      switch (Name[1]) {
380
527
      
default: break0
;
381
527
      case '1':  // 10 strings to match.
382
462
        switch (Name[2]) {
383
462
        
default: break0
;
384
462
        case '0':  // 1 string to match.
385
14
          return 89;  // "s10"
386
462
        case '1':  // 1 string to match.
387
9
          return 90;  // "s11"
388
462
        case '2':  // 1 string to match.
389
57
          return 91;  // "s12"
390
462
        case '3':  // 1 string to match.
391
18
          return 92;  // "s13"
392
462
        case '4':  // 1 string to match.
393
116
          return 93;  // "s14"
394
462
        case '5':  // 1 string to match.
395
202
          return 94;  // "s15"
396
462
        case '6':  // 1 string to match.
397
6
          return 95;  // "s16"
398
462
        case '7':  // 1 string to match.
399
40
          return 96;  // "s17"
400
462
        case '8':  // 1 string to match.
401
0
          return 97;  // "s18"
402
462
        case '9':  // 1 string to match.
403
0
          return 98;  // "s19"
404
0
        }
405
0
        break;
406
57
      case '2':  // 10 strings to match.
407
57
        switch (Name[2]) {
408
57
        
default: break0
;
409
57
        case '0':  // 1 string to match.
410
0
          return 99;  // "s20"
411
57
        case '1':  // 1 string to match.
412
7
          return 100;  // "s21"
413
57
        case '2':  // 1 string to match.
414
0
          return 101;  // "s22"
415
57
        case '3':  // 1 string to match.
416
24
          return 102;  // "s23"
417
57
        case '4':  // 1 string to match.
418
6
          return 103;  // "s24"
419
57
        case '5':  // 1 string to match.
420
1
          return 104;  // "s25"
421
57
        case '6':  // 1 string to match.
422
3
          return 105;  // "s26"
423
57
        case '7':  // 1 string to match.
424
0
          return 106;  // "s27"
425
57
        case '8':  // 1 string to match.
426
16
          return 107;  // "s28"
427
57
        case '9':  // 1 string to match.
428
0
          return 108;  // "s29"
429
0
        }
430
0
        break;
431
8
      case '3':  // 2 strings to match.
432
8
        switch (Name[2]) {
433
8
        
default: break0
;
434
8
        case '0':  // 1 string to match.
435
6
          return 109;  // "s30"
436
8
        case '1':  // 1 string to match.
437
2
          return 110;  // "s31"
438
0
        }
439
0
        break;
440
0
      }
441
0
      break;
442
2.34k
    }
443
2.34k
    break;
444
2.34k
  case 4:  // 3 strings to match.
445
70
    switch (Name[0]) {
446
70
    
default: break42
;
447
70
    case 'a':  // 1 string to match.
448
4
      if (memcmp(Name.data()+1, "psr", 3) != 0)
449
0
        break;
450
4
      return 1;  // "apsr"
451
9
    case 'c':  // 1 string to match.
452
9
      if (memcmp(Name.data()+1, "psr", 3) != 0)
453
0
        break;
454
9
      return 3;  // "cpsr"
455
15
    case 's':  // 1 string to match.
456
15
      if (memcmp(Name.data()+1, "psr", 3) != 0)
457
11
        break;
458
4
      return 13;  // "spsr"
459
53
    }
460
53
    break;
461
225
  case 5:  // 6 strings to match.
462
225
    switch (Name[0]) {
463
225
    
default: break26
;
464
225
    case 'f':  // 3 strings to match.
465
167
      if (Name[1] != 'p')
466
0
        break;
467
167
      switch (Name[2]) {
468
167
      
default: break0
;
469
167
      case 'e':  // 1 string to match.
470
9
        if (memcmp(Name.data()+3, "xc", 2) != 0)
471
0
          break;
472
9
        return 4;  // "fpexc"
473
158
      case 's':  // 2 strings to match.
474
158
        switch (Name[3]) {
475
158
        
default: break0
;
476
158
        case 'c':  // 1 string to match.
477
133
          if (Name[4] != 'r')
478
0
            break;
479
133
          return 6;  // "fpscr"
480
133
        case 'i':  // 1 string to match.
481
25
          if (Name[4] != 'd')
482
0
            break;
483
25
          return 8;  // "fpsid"
484
0
        }
485
0
        break;
486
0
      }
487
0
      break;
488
32
    case 'm':  // 3 strings to match.
489
32
      if (memcmp(Name.data()+1, "vfr", 3) != 0)
490
0
        break;
491
32
      switch (Name[4]) {
492
32
      
default: break0
;
493
32
      case '0':  // 1 string to match.
494
8
        return 47;  // "mvfr0"
495
32
      case '1':  // 1 string to match.
496
8
        return 48;  // "mvfr1"
497
32
      case '2':  // 1 string to match.
498
16
        return 49;  // "mvfr2"
499
0
      }
500
0
      break;
501
26
    }
502
26
    break;
503
45
  case 6:  // 1 string to match.
504
45
    if (memcmp(Name.data()+0, "fpinst", 6) != 0)
505
43
      break;
506
2
    return 5;  // "fpinst"
507
11
  case 7:  // 2 strings to match.
508
11
    switch (Name[0]) {
509
11
    
default: break7
;
510
11
    case 'f':  // 1 string to match.
511
2
      if (memcmp(Name.data()+1, "pinst2", 6) != 0)
512
0
        break;
513
2
      return 46;   // "fpinst2"
514
2
    case 'i':  // 1 string to match.
515
2
      if (memcmp(Name.data()+1, "tstate", 6) != 0)
516
2
        break;
517
0
      return 9;  // "itstate"
518
9
    }
519
9
    break;
520
92
  case 9:  // 1 string to match.
521
92
    if (memcmp(Name.data()+0, "apsr_nzcv", 9) != 0)
522
3
      break;
523
89
    return 2;  // "apsr_nzcv"
524
89
  case 10:   // 1 string to match.
525
9
    if (memcmp(Name.data()+0, "fpscr_nzcv", 10) != 0)
526
9
      break;
527
0
    return 7;  // "fpscr_nzcv"
528
3.30k
  }
529
3.30k
  return 0;
530
3.30k
}
531
532
#endif // GET_REGISTER_MATCHER
533
534
535
#ifdef GET_SUBTARGET_FEATURE_NAME
536
#undef GET_SUBTARGET_FEATURE_NAME
537
538
// User-level names for subtarget features that participate in
539
// instruction matching.
540
2.33k
static const char *getSubtargetFeatureName(uint64_t Val) {
541
2.33k
  switch(Val) {
542
2.33k
  
case Feature_HasV4T: return "armv4t"0
;
543
2.33k
  
case Feature_HasV5T: return "armv5t"1
;
544
2.33k
  
case Feature_HasV5TE: return "armv5te"0
;
545
2.33k
  
case Feature_HasV6: return "armv6"0
;
546
2.33k
  
case Feature_HasV6M: return "armv6m or armv6t2"12
;
547
2.33k
  
case Feature_HasV8MBaseline: return "armv8m.base"12
;
548
2.33k
  
case Feature_HasV8MMainline: return "armv8m.main"2
;
549
2.33k
  
case Feature_HasV6T2: return "armv6t2"4
;
550
2.33k
  
case Feature_HasV6K: return "armv6k"5
;
551
2.33k
  
case Feature_HasV7: return "armv7"6
;
552
2.33k
  
case Feature_HasV8: return "armv8"113
;
553
2.33k
  
case Feature_PreV8: return "armv7 or earlier"2
;
554
2.33k
  
case Feature_HasV8_1a: return "armv8.1a"36
;
555
2.33k
  
case Feature_HasV8_2a: return "armv8.2a"0
;
556
2.33k
  
case Feature_HasV8_3a: return "armv8.3a"42
;
557
2.33k
  
case Feature_HasV8_4a: return "armv8.4a"0
;
558
2.33k
  
case Feature_HasV8_5a: return "armv8.5a"0
;
559
2.33k
  
case Feature_HasVFP2: return "VFP2"12
;
560
2.33k
  
case Feature_HasVFP3: return "VFP3"0
;
561
2.33k
  
case Feature_HasVFP4: return "VFP4"0
;
562
2.33k
  
case Feature_HasDPVFP: return "double precision VFP"52
;
563
2.33k
  
case Feature_HasFPARMv8: return "FPARMv8"669
;
564
2.33k
  
case Feature_HasNEON: return "NEON"319
;
565
2.33k
  
case Feature_HasSHA2: return "sha2"0
;
566
2.33k
  
case Feature_HasAES: return "aes"0
;
567
2.33k
  
case Feature_HasCrypto: return "crypto"105
;
568
2.33k
  
case Feature_HasDotProd: return "dotprod"64
;
569
2.33k
  
case Feature_HasCRC: return "crc"42
;
570
2.33k
  
case Feature_HasRAS: return "ras"0
;
571
2.33k
  
case Feature_HasFP16: return "half-float conversions"4
;
572
2.33k
  
case Feature_HasFullFP16: return "full half-float"384
;
573
2.33k
  
case Feature_HasFP16FML: return "full half-float fml"80
;
574
2.33k
  
case Feature_HasDivideInThumb: return "divide in THUMB"11
;
575
2.33k
  
case Feature_HasDivideInARM: return "divide in ARM"11
;
576
2.33k
  
case Feature_HasDSP: return "dsp"12
;
577
2.33k
  
case Feature_HasDB: return "data-barriers"5
;
578
2.33k
  
case Feature_HasDFB: return "full-data-barrier"2
;
579
2.33k
  
case Feature_HasV7Clrex: return "v7 clrex"2
;
580
2.33k
  
case Feature_HasAcquireRelease: return "acquire/release"28
;
581
2.33k
  
case Feature_HasMP: return "mp-extensions"13
;
582
2.33k
  
case Feature_HasVirtualization: return "virtualization-extensions"0
;
583
2.33k
  
case Feature_HasTrustZone: return "TrustZone"11
;
584
2.33k
  
case Feature_Has8MSecExt: return "ARMv8-M Security Extensions"0
;
585
2.33k
  
case Feature_IsThumb: return "thumb"5
;
586
2.33k
  
case Feature_IsThumb2: return "thumb2"93
;
587
2.33k
  
case Feature_IsMClass: return "armv*m"0
;
588
2.33k
  
case Feature_IsNotMClass: return "!armv*m"22
;
589
2.33k
  
case Feature_IsARM: return "arm-mode"96
;
590
2.33k
  
case Feature_UseNaClTrap: return "NaCl"0
;
591
2.33k
  
case Feature_UseNegativeImmediates: return "NegativeImmediates"53
;
592
2.33k
  
case Feature_HasSpecCtrl: return "specctrl"2
;
593
2.33k
  
default: return "(unknown)"0
;
594
2.33k
  }
595
2.33k
}
596
597
#endif // GET_SUBTARGET_FEATURE_NAME
598
599
600
#ifdef GET_MATCHER_IMPLEMENTATION
601
#undef GET_MATCHER_IMPLEMENTATION
602
603
69.5k
static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID) {
604
69.5k
  switch (VariantID) {
605
69.5k
    case 0:
606
69.5k
    break;
607
69.5k
  }
608
69.5k
  switch (Mnemonic.size()) {
609
69.5k
  
default: break13.3k
;
610
69.5k
  case 3:  // 4 strings to match.
611
23.0k
    switch (Mnemonic[0]) {
612
23.0k
    
default: break19.6k
;
613
23.0k
    case 'r':  // 1 string to match.
614
650
      if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
615
646
        break;
616
4
      Mnemonic = "rfeia";  // "rfe"
617
4
      return;
618
2.77k
    case 's':  // 3 strings to match.
619
2.77k
      switch (Mnemonic[1]) {
620
2.77k
      
default: break2.69k
;
621
2.77k
      case 'm':  // 1 string to match.
622
39
        if (Mnemonic[2] != 'i')
623
36
          break;
624
3
        Mnemonic = "smc";  // "smi"
625
3
        return;
626
16
      case 'r':  // 1 string to match.
627
16
        if (Mnemonic[2] != 's')
628
0
          break;
629
16
        Mnemonic = "srsia";  // "srs"
630
16
        return;
631
18
      case 'w':  // 1 string to match.
632
18
        if (Mnemonic[2] != 'i')
633
16
          break;
634
2
        Mnemonic = "svc";  // "swi"
635
2
        return;
636
2.75k
      }
637
2.75k
      break;
638
23.0k
    }
639
23.0k
    break;
640
23.0k
  case 4:  // 10 strings to match.
641
13.0k
    switch (Mnemonic[0]) {
642
13.0k
    
default: break6.90k
;
643
13.0k
    case 'f':  // 8 strings to match.
644
9
      switch (Mnemonic[1]) {
645
9
      default: break;
646
9
      case 'l':  // 2 strings to match.
647
0
        if (Mnemonic[2] != 'd')
648
0
          break;
649
0
        switch (Mnemonic[3]) {
650
0
        default: break;
651
0
        case 'd':  // 1 string to match.
652
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fldd"
653
0
            Mnemonic = "vldr";
654
0
          return;
655
0
        case 's':  // 1 string to match.
656
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "flds"
657
0
            Mnemonic = "vldr";
658
0
          return;
659
0
        }
660
0
        break;
661
0
      case 'm':  // 4 strings to match.
662
0
        switch (Mnemonic[2]) {
663
0
        default: break;
664
0
        case 'r':  // 2 strings to match.
665
0
          switch (Mnemonic[3]) {
666
0
          default: break;
667
0
          case 's':  // 1 string to match.
668
0
            if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmrs"
669
0
              Mnemonic = "vmov";
670
0
            return;
671
0
          case 'x':  // 1 string to match.
672
0
            if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmrx"
673
0
              Mnemonic = "vmrs";
674
0
            return;
675
0
          }
676
0
          break;
677
0
        case 's':  // 1 string to match.
678
0
          if (Mnemonic[3] != 'r')
679
0
            break;
680
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmsr"
681
0
            Mnemonic = "vmov";
682
0
          return;
683
0
        case 'x':  // 1 string to match.
684
0
          if (Mnemonic[3] != 'r')
685
0
            break;
686
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmxr"
687
0
            Mnemonic = "vmsr";
688
0
          return;
689
0
        }
690
0
        break;
691
0
      case 's':  // 2 strings to match.
692
0
        if (Mnemonic[2] != 't')
693
0
          break;
694
0
        switch (Mnemonic[3]) {
695
0
        default: break;
696
0
        case 'd':  // 1 string to match.
697
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fstd"
698
0
            Mnemonic = "vstr";
699
0
          return;
700
0
        case 's':  // 1 string to match.
701
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fsts"
702
0
            Mnemonic = "vstr";
703
0
          return;
704
0
        }
705
0
        break;
706
9
      }
707
9
      break;
708
6.15k
    case 'v':  // 2 strings to match.
709
6.15k
      switch (Mnemonic[1]) {
710
6.15k
      
default: break2.89k
;
711
6.15k
      case 'l':  // 1 string to match.
712
1.75k
        if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
713
1.74k
          break;
714
12
        Mnemonic = "vldmia";   // "vldm"
715
12
        return;
716
1.50k
      case 's':  // 1 string to match.
717
1.50k
        if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
718
1.48k
          break;
719
13
        Mnemonic = "vstmia";   // "vstm"
720
13
        return;
721
6.12k
      }
722
6.12k
      break;
723
13.0k
    }
724
13.0k
    break;
725
13.0k
  case 5:  // 51 strings to match.
726
7.24k
    switch (Mnemonic[0]) {
727
7.24k
    
default: break2.24k
;
728
7.24k
    case 'f':  // 18 strings to match.
729
0
      switch (Mnemonic[1]) {
730
0
      default: break;
731
0
      case 'a':  // 2 strings to match.
732
0
        if (memcmp(Mnemonic.data()+2, "dd", 2) != 0)
733
0
          break;
734
0
        switch (Mnemonic[4]) {
735
0
        default: break;
736
0
        case 'd':  // 1 string to match.
737
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "faddd"
738
0
            Mnemonic = "vadd.f64";
739
0
          return;
740
0
        case 's':  // 1 string to match.
741
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fadds"
742
0
            Mnemonic = "vadd.f32";
743
0
          return;
744
0
        }
745
0
        break;
746
0
      case 'c':  // 4 strings to match.
747
0
        switch (Mnemonic[2]) {
748
0
        default: break;
749
0
        case 'm':  // 2 strings to match.
750
0
          if (Mnemonic[3] != 'p')
751
0
            break;
752
0
          switch (Mnemonic[4]) {
753
0
          default: break;
754
0
          case 'd':  // 1 string to match.
755
0
            if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fcmpd"
756
0
              Mnemonic = "vcmp.f64";
757
0
            return;
758
0
          case 's':  // 1 string to match.
759
0
            if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fcmps"
760
0
              Mnemonic = "vcmp.f32";
761
0
            return;
762
0
          }
763
0
          break;
764
0
        case 'p':  // 2 strings to match.
765
0
          if (Mnemonic[3] != 'y')
766
0
            break;
767
0
          switch (Mnemonic[4]) {
768
0
          default: break;
769
0
          case 'd':  // 1 string to match.
770
0
            if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fcpyd"
771
0
              Mnemonic = "vmov.f64";
772
0
            return;
773
0
          case 's':  // 1 string to match.
774
0
            if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fcpys"
775
0
              Mnemonic = "vmov.f32";
776
0
            return;
777
0
          }
778
0
          break;
779
0
        }
780
0
        break;
781
0
      case 'd':  // 2 strings to match.
782
0
        if (memcmp(Mnemonic.data()+2, "iv", 2) != 0)
783
0
          break;
784
0
        switch (Mnemonic[4]) {
785
0
        default: break;
786
0
        case 'd':  // 1 string to match.
787
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fdivd"
788
0
            Mnemonic = "vdiv.f64";
789
0
          return;
790
0
        case 's':  // 1 string to match.
791
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fdivs"
792
0
            Mnemonic = "vdiv.f32";
793
0
          return;
794
0
        }
795
0
        break;
796
0
      case 'm':  // 8 strings to match.
797
0
        switch (Mnemonic[2]) {
798
0
        default: break;
799
0
        case 'a':  // 2 strings to match.
800
0
          if (Mnemonic[3] != 'c')
801
0
            break;
802
0
          switch (Mnemonic[4]) {
803
0
          default: break;
804
0
          case 'd':  // 1 string to match.
805
0
            if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmacd"
806
0
              Mnemonic = "vmla.f64";
807
0
            return;
808
0
          case 's':  // 1 string to match.
809
0
            if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmacs"
810
0
              Mnemonic = "vmla.f32";
811
0
            return;
812
0
          }
813
0
          break;
814
0
        case 'd':  // 1 string to match.
815
0
          if (memcmp(Mnemonic.data()+3, "rr", 2) != 0)
816
0
            break;
817
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmdrr"
818
0
            Mnemonic = "vmov";
819
0
          return;
820
0
        case 'r':  // 3 strings to match.
821
0
          switch (Mnemonic[3]) {
822
0
          default: break;
823
0
          case 'd':  // 2 strings to match.
824
0
            switch (Mnemonic[4]) {
825
0
            default: break;
826
0
            case 'd':  // 1 string to match.
827
0
              if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmrdd"
828
0
                Mnemonic = "vmov";
829
0
              return;
830
0
            case 's':  // 1 string to match.
831
0
              if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmrds"
832
0
                Mnemonic = "vmov";
833
0
              return;
834
0
            }
835
0
            break;
836
0
          case 'r':  // 1 string to match.
837
0
            if (Mnemonic[4] != 'd')
838
0
              break;
839
0
            if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmrrd"
840
0
              Mnemonic = "vmov";
841
0
            return;
842
0
          }
843
0
          break;
844
0
        case 'u':  // 2 strings to match.
845
0
          if (Mnemonic[3] != 'l')
846
0
            break;
847
0
          switch (Mnemonic[4]) {
848
0
          default: break;
849
0
          case 'd':  // 1 string to match.
850
0
            if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmuld"
851
0
              Mnemonic = "vmul.f64";
852
0
            return;
853
0
          case 's':  // 1 string to match.
854
0
            if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fmuls"
855
0
              Mnemonic = "vmul.f32";
856
0
            return;
857
0
          }
858
0
          break;
859
0
        }
860
0
        break;
861
0
      case 'n':  // 2 strings to match.
862
0
        if (memcmp(Mnemonic.data()+2, "eg", 2) != 0)
863
0
          break;
864
0
        switch (Mnemonic[4]) {
865
0
        default: break;
866
0
        case 'd':  // 1 string to match.
867
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fnegd"
868
0
            Mnemonic = "vneg.f64";
869
0
          return;
870
0
        case 's':  // 1 string to match.
871
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fnegs"
872
0
            Mnemonic = "vneg.f32";
873
0
          return;
874
0
        }
875
0
        break;
876
0
      }
877
0
      break;
878
1.38k
    case 'l':  // 3 strings to match.
879
1.38k
      if (memcmp(Mnemonic.data()+1, "dm", 2) != 0)
880
1.16k
        break;
881
217
      switch (Mnemonic[3]) {
882
217
      
default: break131
;
883
217
      case 'e':  // 1 string to match.
884
15
        if (Mnemonic[4] != 'a')
885
13
          break;
886
2
        Mnemonic = "ldmdb";  // "ldmea"
887
2
        return;
888
19
      case 'f':  // 1 string to match.
889
19
        if (Mnemonic[4] != 'd')
890
0
          break;
891
19
        Mnemonic = "ldm";  // "ldmfd"
892
19
        return;
893
52
      case 'i':  // 1 string to match.
894
52
        if (Mnemonic[4] != 'a')
895
24
          break;
896
28
        Mnemonic = "ldm";  // "ldmia"
897
28
        return;
898
168
      }
899
168
      break;
900
207
    case 'r':  // 4 strings to match.
901
207
      if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
902
129
        break;
903
78
      switch (Mnemonic[3]) {
904
78
      
default: break62
;
905
78
      case 'e':  // 2 strings to match.
906
8
        switch (Mnemonic[4]) {
907
8
        
default: break0
;
908
8
        case 'a':  // 1 string to match.
909
4
          Mnemonic = "rfedb";  // "rfeea"
910
4
          return;
911
8
        case 'd':  // 1 string to match.
912
4
          Mnemonic = "rfeib";  // "rfeed"
913
4
          return;
914
0
        }
915
0
        break;
916
8
      case 'f':  // 2 strings to match.
917
8
        switch (Mnemonic[4]) {
918
8
        
default: break0
;
919
8
        case 'a':  // 1 string to match.
920
4
          Mnemonic = "rfeda";  // "rfefa"
921
4
          return;
922
8
        case 'd':  // 1 string to match.
923
4
          Mnemonic = "rfeia";  // "rfefd"
924
4
          return;
925
0
        }
926
0
        break;
927
62
      }
928
62
      break;
929
1.54k
    case 's':  // 7 strings to match.
930
1.54k
      switch (Mnemonic[1]) {
931
1.54k
      
default: break482
;
932
1.54k
      case 'r':  // 4 strings to match.
933
210
        if (Mnemonic[2] != 's')
934
0
          break;
935
210
        switch (Mnemonic[3]) {
936
210
        
default: break162
;
937
210
        case 'e':  // 2 strings to match.
938
24
          switch (Mnemonic[4]) {
939
24
          
default: break0
;
940
24
          case 'a':  // 1 string to match.
941
16
            Mnemonic = "srsia";  // "srsea"
942
16
            return;
943
24
          case 'd':  // 1 string to match.
944
8
            Mnemonic = "srsda";  // "srsed"
945
8
            return;
946
0
          }
947
0
          break;
948
24
        case 'f':  // 2 strings to match.
949
24
          switch (Mnemonic[4]) {
950
24
          
default: break0
;
951
24
          case 'a':  // 1 string to match.
952
8
            Mnemonic = "srsib";  // "srsfa"
953
8
            return;
954
24
          case 'd':  // 1 string to match.
955
16
            Mnemonic = "srsdb";  // "srsfd"
956
16
            return;
957
0
          }
958
0
          break;
959
162
        }
960
162
        break;
961
852
      case 't':  // 3 strings to match.
962
852
        if (Mnemonic[2] != 'm')
963
638
          break;
964
214
        switch (Mnemonic[3]) {
965
214
        
default: break150
;
966
214
        case 'e':  // 1 string to match.
967
4
          if (Mnemonic[4] != 'a')
968
0
            break;
969
4
          Mnemonic = "stm";  // "stmea"
970
4
          return;
971
10
        case 'f':  // 1 string to match.
972
10
          if (Mnemonic[4] != 'd')
973
0
            break;
974
10
          Mnemonic = "stmdb";  // "stmfd"
975
10
          return;
976
50
        case 'i':  // 1 string to match.
977
50
          if (Mnemonic[4] != 'a')
978
32
            break;
979
18
          Mnemonic = "stm";  // "stmia"
980
18
          return;
981
182
        }
982
182
        break;
983
1.46k
      }
984
1.46k
      break;
985
1.86k
    case 'v':  // 19 strings to match.
986
1.86k
      switch (Mnemonic[1]) {
987
1.86k
      
default: break746
;
988
1.86k
      case 'a':  // 3 strings to match.
989
118
        switch (Mnemonic[2]) {
990
118
        
default: break64
;
991
118
        case 'b':  // 1 string to match.
992
24
          if (memcmp(Mnemonic.data()+3, "sq", 2) != 0)
993
24
            break;
994
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vabsq"
995
0
            Mnemonic = "vabs";
996
0
          return;
997
30
        case 'd':  // 1 string to match.
998
30
          if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
999
30
            break;
1000
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vaddq"
1001
0
            Mnemonic = "vadd";
1002
0
          return;
1003
0
        case 'n':  // 1 string to match.
1004
0
          if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
1005
0
            break;
1006
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vandq"
1007
0
            Mnemonic = "vand";
1008
0
          return;
1009
118
        }
1010
118
        break;
1011
118
      case 'b':  // 1 string to match.
1012
0
        if (memcmp(Mnemonic.data()+2, "icq", 3) != 0)
1013
0
          break;
1014
0
        if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vbicq"
1015
0
          Mnemonic = "vbic";
1016
0
        return;
1017
814
      case 'c':  // 3 strings to match.
1018
814
        switch (Mnemonic[2]) {
1019
814
        
default: break278
;
1020
814
        case 'e':  // 1 string to match.
1021
0
          if (memcmp(Mnemonic.data()+3, "qq", 2) != 0)
1022
0
            break;
1023
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vceqq"
1024
0
            Mnemonic = "vceq";
1025
0
          return;
1026
0
        case 'l':  // 1 string to match.
1027
0
          if (memcmp(Mnemonic.data()+3, "eq", 2) != 0)
1028
0
            break;
1029
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vcleq"
1030
0
            Mnemonic = "vcle";
1031
0
          return;
1032
536
        case 'v':  // 1 string to match.
1033
536
          if (memcmp(Mnemonic.data()+3, "tq", 2) != 0)
1034
536
            break;
1035
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vcvtq"
1036
0
            Mnemonic = "vcvt";
1037
0
          return;
1038
814
        }
1039
814
        break;
1040
814
      case 'e':  // 1 string to match.
1041
0
        if (memcmp(Mnemonic.data()+2, "orq", 3) != 0)
1042
0
          break;
1043
0
        if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "veorq"
1044
0
          Mnemonic = "veor";
1045
0
        return;
1046
75
      case 'm':  // 5 strings to match.
1047
75
        switch (Mnemonic[2]) {
1048
75
        
default: break26
;
1049
75
        case 'a':  // 1 string to match.
1050
0
          if (memcmp(Mnemonic.data()+3, "xq", 2) != 0)
1051
0
            break;
1052
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vmaxq"
1053
0
            Mnemonic = "vmax";
1054
0
          return;
1055
0
        case 'i':  // 1 string to match.
1056
0
          if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1057
0
            break;
1058
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vminq"
1059
0
            Mnemonic = "vmin";
1060
0
          return;
1061
22
        case 'o':  // 1 string to match.
1062
22
          if (memcmp(Mnemonic.data()+3, "vq", 2) != 0)
1063
22
            break;
1064
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vmovq"
1065
0
            Mnemonic = "vmov";
1066
0
          return;
1067
27
        case 'u':  // 1 string to match.
1068
27
          if (memcmp(Mnemonic.data()+3, "lq", 2) != 0)
1069
27
            break;
1070
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vmulq"
1071
0
            Mnemonic = "vmul";
1072
0
          return;
1073
0
        case 'v':  // 1 string to match.
1074
0
          if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1075
0
            break;
1076
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vmvnq"
1077
0
            Mnemonic = "vmvn";
1078
0
          return;
1079
75
        }
1080
75
        break;
1081
75
      case 'o':  // 1 string to match.
1082
0
        if (memcmp(Mnemonic.data()+2, "rrq", 3) != 0)
1083
0
          break;
1084
0
        if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vorrq"
1085
0
          Mnemonic = "vorr";
1086
0
        return;
1087
115
      case 's':  // 4 strings to match.
1088
115
        switch (Mnemonic[2]) {
1089
115
        
default: break73
;
1090
115
        case 'h':  // 2 strings to match.
1091
24
          switch (Mnemonic[3]) {
1092
24
          
default: break0
;
1093
24
          case 'l':  // 1 string to match.
1094
18
            if (Mnemonic[4] != 'q')
1095
18
              break;
1096
0
            if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vshlq"
1097
0
              Mnemonic = "vshl";
1098
0
            return;
1099
6
          case 'r':  // 1 string to match.
1100
6
            if (Mnemonic[4] != 'q')
1101
6
              break;
1102
0
            if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vshrq"
1103
0
              Mnemonic = "vshr";
1104
0
            return;
1105
24
          }
1106
24
          break;
1107
24
        case 'u':  // 1 string to match.
1108
18
          if (memcmp(Mnemonic.data()+3, "bq", 2) != 0)
1109
18
            break;
1110
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vsubq"
1111
0
            Mnemonic = "vsub";
1112
0
          return;
1113
0
        case 'w':  // 1 string to match.
1114
0
          if (memcmp(Mnemonic.data()+3, "pq", 2) != 0)
1115
0
            break;
1116
0
          if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vswpq"
1117
0
            Mnemonic = "vswp";
1118
0
          return;
1119
115
        }
1120
115
        break;
1121
115
      case 'z':  // 1 string to match.
1122
0
        if (memcmp(Mnemonic.data()+2, "ipq", 3) != 0)
1123
0
          break;
1124
0
        if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vzipq"
1125
0
          Mnemonic = "vzip";
1126
0
        return;
1127
1.86k
      }
1128
1.86k
      break;
1129
7.10k
    }
1130
7.10k
    break;
1131
7.10k
  case 6:  // 10 strings to match.
1132
4.73k
    if (Mnemonic[0] != 'f')
1133
4.71k
      break;
1134
18
    switch (Mnemonic[1]) {
1135
18
    
default: break16
;
1136
18
    case 's':  // 4 strings to match.
1137
2
      switch (Mnemonic[2]) {
1138
2
      
default: break0
;
1139
2
      case 'i':  // 2 strings to match.
1140
0
        if (memcmp(Mnemonic.data()+3, "to", 2) != 0)
1141
0
          break;
1142
0
        switch (Mnemonic[5]) {
1143
0
        default: break;
1144
0
        case 'd':  // 1 string to match.
1145
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fsitod"
1146
0
            Mnemonic = "vcvt.f64.s32";
1147
0
          return;
1148
0
        case 's':  // 1 string to match.
1149
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fsitos"
1150
0
            Mnemonic = "vcvt.f32.s32";
1151
0
          return;
1152
0
        }
1153
0
        break;
1154
2
      case 'q':  // 2 strings to match.
1155
2
        if (memcmp(Mnemonic.data()+3, "rt", 2) != 0)
1156
0
          break;
1157
2
        switch (Mnemonic[5]) {
1158
2
        
default: break0
;
1159
2
        case 'd':  // 1 string to match.
1160
1
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fsqrtd"
1161
1
            Mnemonic = "vsqrt";
1162
1
          return;
1163
2
        case 's':  // 1 string to match.
1164
1
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fsqrts"
1165
1
            Mnemonic = "vsqrt";
1166
1
          return;
1167
0
        }
1168
0
        break;
1169
0
      }
1170
0
      break;
1171
0
    case 't':  // 4 strings to match.
1172
0
      if (Mnemonic[2] != 'o')
1173
0
        break;
1174
0
      switch (Mnemonic[3]) {
1175
0
      default: break;
1176
0
      case 's':  // 2 strings to match.
1177
0
        if (Mnemonic[4] != 'i')
1178
0
          break;
1179
0
        switch (Mnemonic[5]) {
1180
0
        default: break;
1181
0
        case 'd':  // 1 string to match.
1182
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "ftosid"
1183
0
            Mnemonic = "vcvtr.s32.f64";
1184
0
          return;
1185
0
        case 's':  // 1 string to match.
1186
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "ftosis"
1187
0
            Mnemonic = "vcvtr.s32.f32";
1188
0
          return;
1189
0
        }
1190
0
        break;
1191
0
      case 'u':  // 2 strings to match.
1192
0
        if (Mnemonic[4] != 'i')
1193
0
          break;
1194
0
        switch (Mnemonic[5]) {
1195
0
        default: break;
1196
0
        case 'd':  // 1 string to match.
1197
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "ftouid"
1198
0
            Mnemonic = "vcvtr.u32.f64";
1199
0
          return;
1200
0
        case 's':  // 1 string to match.
1201
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "ftouis"
1202
0
            Mnemonic = "vcvtr.u32.f32";
1203
0
          return;
1204
0
        }
1205
0
        break;
1206
0
      }
1207
0
      break;
1208
0
    case 'u':  // 2 strings to match.
1209
0
      if (memcmp(Mnemonic.data()+2, "ito", 3) != 0)
1210
0
        break;
1211
0
      switch (Mnemonic[5]) {
1212
0
      default: break;
1213
0
      case 'd':  // 1 string to match.
1214
0
        if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fuitod"
1215
0
          Mnemonic = "vcvt.f64.u32";
1216
0
        return;
1217
0
      case 's':  // 1 string to match.
1218
0
        if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fuitos"
1219
0
          Mnemonic = "vcvt.f32.u32";
1220
0
        return;
1221
0
      }
1222
0
      break;
1223
16
    }
1224
16
    break;
1225
4.32k
  case 7:  // 8 strings to match.
1226
4.32k
    if (Mnemonic[0] != 'f')
1227
4.28k
      break;
1228
46
    switch (Mnemonic[1]) {
1229
46
    
default: break14
;
1230
46
    case 'l':  // 2 strings to match.
1231
12
      if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
1232
0
        break;
1233
12
      switch (Mnemonic[4]) {
1234
12
      
default: break8
;
1235
12
      case 'e':  // 1 string to match.
1236
2
        if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1237
0
          break;
1238
2
        if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fldmeax"
1239
2
          Mnemonic = "fldmdbx";
1240
2
        return;
1241
2
      case 'f':  // 1 string to match.
1242
2
        if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1243
0
          break;
1244
2
        if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fldmfdx"
1245
2
          Mnemonic = "fldmiax";
1246
2
        return;
1247
8
      }
1248
8
      break;
1249
20
    case 's':  // 2 strings to match.
1250
20
      if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
1251
0
        break;
1252
20
      switch (Mnemonic[4]) {
1253
20
      
default: break16
;
1254
20
      case 'e':  // 1 string to match.
1255
2
        if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1256
0
          break;
1257
2
        if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fstmeax"
1258
2
          Mnemonic = "fstmiax";
1259
2
        return;
1260
2
      case 'f':  // 1 string to match.
1261
2
        if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1262
0
          break;
1263
2
        if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "fstmfdx"
1264
2
          Mnemonic = "fstmdbx";
1265
2
        return;
1266
16
      }
1267
16
      break;
1268
16
    case 't':  // 4 strings to match.
1269
0
      if (Mnemonic[2] != 'o')
1270
0
        break;
1271
0
      switch (Mnemonic[3]) {
1272
0
      default: break;
1273
0
      case 's':  // 2 strings to match.
1274
0
        if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1275
0
          break;
1276
0
        switch (Mnemonic[6]) {
1277
0
        default: break;
1278
0
        case 'd':  // 1 string to match.
1279
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "ftosizd"
1280
0
            Mnemonic = "vcvt.s32.f64";
1281
0
          return;
1282
0
        case 's':  // 1 string to match.
1283
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "ftosizs"
1284
0
            Mnemonic = "vcvt.s32.f32";
1285
0
          return;
1286
0
        }
1287
0
        break;
1288
0
      case 'u':  // 2 strings to match.
1289
0
        if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1290
0
          break;
1291
0
        switch (Mnemonic[6]) {
1292
0
        default: break;
1293
0
        case 'd':  // 1 string to match.
1294
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "ftouizd"
1295
0
            Mnemonic = "vcvt.u32.f64";
1296
0
          return;
1297
0
        case 's':  // 1 string to match.
1298
0
          if ((Features & Feature_HasVFP2) == Feature_HasVFP2)  // "ftouizs"
1299
0
            Mnemonic = "vcvt.u32.f32";
1300
0
          return;
1301
0
        }
1302
0
        break;
1303
0
      }
1304
0
      break;
1305
38
    }
1306
38
    break;
1307
2.41k
  case 8:  // 5 strings to match.
1308
2.41k
    switch (Mnemonic[0]) {
1309
2.41k
    
default: break2.05k
;
1310
2.41k
    case 'q':  // 1 string to match.
1311
8
      if (memcmp(Mnemonic.data()+1, "subaddx", 7) != 0)
1312
8
        break;
1313
0
      Mnemonic = "qsax";   // "qsubaddx"
1314
0
      return;
1315
308
    case 's':  // 2 strings to match.
1316
308
      switch (Mnemonic[1]) {
1317
308
      
default: break290
;
1318
308
      case 'a':  // 1 string to match.
1319
10
        if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1320
6
          break;
1321
4
        Mnemonic = "sasx";   // "saddsubx"
1322
4
        return;
1323
8
      case 's':  // 1 string to match.
1324
8
        if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1325
4
          break;
1326
4
        Mnemonic = "ssax";   // "ssubaddx"
1327
4
        return;
1328
300
      }
1329
300
      break;
1330
300
    case 'u':  // 2 strings to match.
1331
49
      switch (Mnemonic[1]) {
1332
49
      
default: break29
;
1333
49
      case 'a':  // 1 string to match.
1334
8
        if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1335
4
          break;
1336
4
        Mnemonic = "uasx";   // "uaddsubx"
1337
4
        return;
1338
12
      case 's':  // 1 string to match.
1339
12
        if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1340
8
          break;
1341
4
        Mnemonic = "usax";   // "usubaddx"
1342
4
        return;
1343
41
      }
1344
41
      break;
1345
2.40k
    }
1346
2.40k
    break;
1347
2.40k
  case 9:  // 8 strings to match.
1348
1.21k
    switch (Mnemonic[0]) {
1349
1.21k
    
default: break87
;
1350
1.21k
    case 's':  // 2 strings to match.
1351
70
      if (Mnemonic[1] != 'h')
1352
32
        break;
1353
38
      switch (Mnemonic[2]) {
1354
38
      
default: break0
;
1355
38
      case 'a':  // 1 string to match.
1356
30
        if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1357
26
          break;
1358
4
        Mnemonic = "shasx";  // "shaddsubx"
1359
4
        return;
1360
8
      case 's':  // 1 string to match.
1361
8
        if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1362
4
          break;
1363
4
        Mnemonic = "shsax";  // "shsubaddx"
1364
4
        return;
1365
30
      }
1366
30
      break;
1367
40
    case 'u':  // 4 strings to match.
1368
40
      switch (Mnemonic[1]) {
1369
40
      
default: break8
;
1370
40
      case 'h':  // 2 strings to match.
1371
16
        switch (Mnemonic[2]) {
1372
16
        
default: break0
;
1373
16
        case 'a':  // 1 string to match.
1374
8
          if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1375
4
            break;
1376
4
          Mnemonic = "uhasx";  // "uhaddsubx"
1377
4
          return;
1378
8
        case 's':  // 1 string to match.
1379
8
          if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1380
4
            break;
1381
4
          Mnemonic = "uhsax";  // "uhsubaddx"
1382
4
          return;
1383
8
        }
1384
8
        break;
1385
16
      case 'q':  // 2 strings to match.
1386
16
        switch (Mnemonic[2]) {
1387
16
        
default: break0
;
1388
16
        case 'a':  // 1 string to match.
1389
8
          if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1390
4
            break;
1391
4
          Mnemonic = "uqasx";  // "uqaddsubx"
1392
4
          return;
1393
8
        case 's':  // 1 string to match.
1394
8
          if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1395
4
            break;
1396
4
          Mnemonic = "uqsax";  // "uqsubaddx"
1397
4
          return;
1398
8
        }
1399
8
        break;
1400
24
      }
1401
24
      break;
1402
1.01k
    case 'v':  // 2 strings to match.
1403
1.01k
      if (memcmp(Mnemonic.data()+1, "movq.f", 6) != 0)
1404
1.01k
        break;
1405
0
      switch (Mnemonic[7]) {
1406
0
      default: break;
1407
0
      case '3':  // 1 string to match.
1408
0
        if (Mnemonic[8] != '2')
1409
0
          break;
1410
0
        if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vmovq.f32"
1411
0
          Mnemonic = "vmov.f32";
1412
0
        return;
1413
0
      case '6':  // 1 string to match.
1414
0
        if (Mnemonic[8] != '4')
1415
0
          break;
1416
0
        if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vmovq.f64"
1417
0
          Mnemonic = "vmov.f64";
1418
0
        return;
1419
0
      }
1420
0
      break;
1421
1.19k
    }
1422
1.19k
    break;
1423
1.19k
  case 11:   // 2 strings to match.
1424
153
    if (memcmp(Mnemonic.data()+0, "vrecpeq.", 8) != 0)
1425
153
      break;
1426
0
    switch (Mnemonic[8]) {
1427
0
    default: break;
1428
0
    case 'f':  // 1 string to match.
1429
0
      if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
1430
0
        break;
1431
0
      if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vrecpeq.f32"
1432
0
        Mnemonic = "vrecpe.f32";
1433
0
      return;
1434
0
    case 'u':  // 1 string to match.
1435
0
      if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
1436
0
        break;
1437
0
      if ((Features & Feature_HasNEON) == Feature_HasNEON)  // "vrecpeq.u32"
1438
0
        Mnemonic = "vrecpe.u32";
1439
0
      return;
1440
0
    }
1441
0
    break;
1442
69.5k
  }
1443
69.5k
}
1444
1445
enum {
1446
  Tie0_1_1,
1447
  Tie0_2_2,
1448
  Tie0_3_3,
1449
  Tie0_4_4,
1450
  Tie0_4_5,
1451
  Tie1_1_1,
1452
  Tie1_3_3,
1453
  Tie1_4_4,
1454
  Tie2_4_4,
1455
};
1456
1457
static const uint8_t TiedAsmOperandTable[][3] = {
1458
  /* Tie0_1_1 */ { 0, 1, 1 },
1459
  /* Tie0_2_2 */ { 0, 2, 2 },
1460
  /* Tie0_3_3 */ { 0, 3, 3 },
1461
  /* Tie0_4_4 */ { 0, 4, 4 },
1462
  /* Tie0_4_5 */ { 0, 4, 5 },
1463
  /* Tie1_1_1 */ { 1, 1, 1 },
1464
  /* Tie1_3_3 */ { 1, 3, 3 },
1465
  /* Tie1_4_4 */ { 1, 4, 4 },
1466
  /* Tie2_4_4 */ { 2, 4, 4 },
1467
};
1468
1469
namespace {
1470
enum OperatorConversionKind {
1471
  CVT_Done,
1472
  CVT_Reg,
1473
  CVT_Tied,
1474
  CVT_95_Reg,
1475
  CVT_95_addCCOutOperands,
1476
  CVT_95_addCondCodeOperands,
1477
  CVT_95_addRegShiftedRegOperands,
1478
  CVT_95_addModImmOperands,
1479
  CVT_95_addModImmNotOperands,
1480
  CVT_95_addRegShiftedImmOperands,
1481
  CVT_95_addImmOperands,
1482
  CVT_95_addT2SOImmNotOperands,
1483
  CVT_95_addImm0_95_508s4Operands,
1484
  CVT_regSP,
1485
  CVT_95_addImm0_95_508s4NegOperands,
1486
  CVT_95_addImm0_95_4095NegOperands,
1487
  CVT_95_addThumbModImmNeg8_95_255Operands,
1488
  CVT_95_addT2SOImmNegOperands,
1489
  CVT_95_addModImmNegOperands,
1490
  CVT_95_addImm0_95_1020s4Operands,
1491
  CVT_95_addThumbModImmNeg1_95_7Operands,
1492
  CVT_95_addUnsignedOffset_95_b8s2Operands,
1493
  CVT_95_addAdrLabelOperands,
1494
  CVT_95_addARMBranchTargetOperands,
1495
  CVT_cvtThumbBranches,
1496
  CVT_95_addBitfieldOperands,
1497
  CVT_imm_95_0,
1498
  CVT_95_addThumbBranchTargetOperands,
1499
  CVT_95_addCoprocNumOperands,
1500
  CVT_95_addCoprocRegOperands,
1501
  CVT_95_addProcIFlagsOperands,
1502
  CVT_imm_95_20,
1503
  CVT_imm_95_12,
1504
  CVT_imm_95_15,
1505
  CVT_95_addMemBarrierOptOperands,
1506
  CVT_imm_95_16,
1507
  CVT_95_addFPImmOperands,
1508
  CVT_95_addDPRRegListOperands,
1509
  CVT_imm_95_1,
1510
  CVT_95_addInstSyncBarrierOptOperands,
1511
  CVT_95_addITCondCodeOperands,
1512
  CVT_95_addITMaskOperands,
1513
  CVT_95_addMemNoOffsetOperands,
1514
  CVT_95_addAddrMode5Operands,
1515
  CVT_95_addCoprocOptionOperands,
1516
  CVT_95_addPostIdxImm8s4Operands,
1517
  CVT_95_addRegListOperands,
1518
  CVT_95_addThumbMemPCOperands,
1519
  CVT_95_addConstPoolAsmImmOperands,
1520
  CVT_95_addMemThumbRIs4Operands,
1521
  CVT_95_addMemThumbRROperands,
1522
  CVT_95_addMemThumbSPIOperands,
1523
  CVT_95_addMemImm12OffsetOperands,
1524
  CVT_95_addMemNegImm8OffsetOperands,
1525
  CVT_95_addMemRegOffsetOperands,
1526
  CVT_95_addMemUImm12OffsetOperands,
1527
  CVT_95_addT2MemRegOffsetOperands,
1528
  CVT_95_addMemPCRelImm12Operands,
1529
  CVT_95_addMemImm8OffsetOperands,
1530
  CVT_95_addAM2OffsetImmOperands,
1531
  CVT_95_addPostIdxRegShiftedOperands,
1532
  CVT_95_addMemThumbRIs1Operands,
1533
  CVT_95_addMemPosImm8OffsetOperands,
1534
  CVT_95_addMemImm8s4OffsetOperands,
1535
  CVT_95_addAddrMode3Operands,
1536
  CVT_95_addAM3OffsetOperands,
1537
  CVT_95_addMemImm0_95_1020s4OffsetOperands,
1538
  CVT_95_addMemThumbRIs2Operands,
1539
  CVT_95_addPostIdxRegOperands,
1540
  CVT_95_addPostIdxImm8Operands,
1541
  CVT_reg0,
1542
  CVT_regCPSR,
1543
  CVT_imm_95_14,
1544
  CVT_95_addBankedRegOperands,
1545
  CVT_95_addMSRMaskOperands,
1546
  CVT_cvtThumbMultiply,
1547
  CVT_regR8,
1548
  CVT_regR0,
1549
  CVT_95_addPKHASRImmOperands,
1550
  CVT_imm_95_4,
1551
  CVT_95_addImm1_95_32Operands,
1552
  CVT_imm_95_5,
1553
  CVT_95_addShifterImmOperands,
1554
  CVT_95_addImm1_95_16Operands,
1555
  CVT_95_addRotImmOperands,
1556
  CVT_95_addMemTBBOperands,
1557
  CVT_95_addMemTBHOperands,
1558
  CVT_95_addTraceSyncBarrierOptOperands,
1559
  CVT_95_addNEONi16splatNotOperands,
1560
  CVT_95_addNEONi32splatNotOperands,
1561
  CVT_95_addNEONi16splatOperands,
1562
  CVT_95_addNEONi32splatOperands,
1563
  CVT_95_addComplexRotationOddOperands,
1564
  CVT_95_addComplexRotationEvenOperands,
1565
  CVT_95_addVectorIndex64Operands,
1566
  CVT_95_addVectorIndex32Operands,
1567
  CVT_95_addFBits16Operands,
1568
  CVT_95_addFBits32Operands,
1569
  CVT_95_addVectorIndex16Operands,
1570
  CVT_95_addVectorIndex8Operands,
1571
  CVT_95_addVecListOperands,
1572
  CVT_95_addDupAlignedMemory16Operands,
1573
  CVT_95_addAlignedMemory64or128Operands,
1574
  CVT_95_addAlignedMemory64or128or256Operands,
1575
  CVT_95_addAlignedMemory64Operands,
1576
  CVT_95_addVecListIndexedOperands,
1577
  CVT_95_addAlignedMemory16Operands,
1578
  CVT_95_addDupAlignedMemory32Operands,
1579
  CVT_95_addAlignedMemory32Operands,
1580
  CVT_95_addDupAlignedMemoryNoneOperands,
1581
  CVT_95_addAlignedMemoryNoneOperands,
1582
  CVT_95_addAlignedMemoryOperands,
1583
  CVT_95_addDupAlignedMemory64Operands,
1584
  CVT_95_addDupAlignedMemory64or128Operands,
1585
  CVT_95_addSPRRegListOperands,
1586
  CVT_95_addAddrMode5FP16Operands,
1587
  CVT_95_addNEONi32vmovOperands,
1588
  CVT_95_addNEONvmovi8ReplicateOperands,
1589
  CVT_95_addNEONvmovi16ReplicateOperands,
1590
  CVT_95_addNEONi32vmovNegOperands,
1591
  CVT_95_addNEONvmovi32ReplicateOperands,
1592
  CVT_95_addNEONi64splatOperands,
1593
  CVT_95_addNEONi8splatOperands,
1594
  CVT_95_addNEONinvi8ReplicateOperands,
1595
  CVT_imm_95_2,
1596
  CVT_imm_95_3,
1597
  CVT_NUM_CONVERTERS
1598
};
1599
1600
enum InstructionConversionKind {
1601
  Convert_NoOperands,
1602
  Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1,
1603
  Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
1604
  Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
1605
  Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
1606
  Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
1607
  Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
1608
  Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
1609
  Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
1610
  Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
1611
  Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
1612
  Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0,
1613
  Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0,
1614
  Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0,
1615
  Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
1616
  Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0,
1617
  Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0,
1618
  Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0,
1619
  Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0,
1620
  Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0,
1621
  Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0,
1622
  Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1,
1623
  Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1,
1624
  Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1,
1625
  Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
1626
  Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0,
1627
  Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0,
1628
  Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0,
1629
  Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0,
1630
  Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0,
1631
  Convert__Reg1_1__Imm0_40951_3__CondCode2_0,
1632
  Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0,
1633
  Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0,
1634
  Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0,
1635
  Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
1636
  Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1,
1637
  Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1,
1638
  Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1,
1639
  Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
1640
  Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0,
1641
  Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0,
1642
  Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0,
1643
  Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0,
1644
  Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0,
1645
  Convert__Reg1_1__Imm1_2__CondCode2_0,
1646
  Convert__Reg1_1__AdrLabel1_2__CondCode2_0,
1647
  Convert__Reg1_2__Imm1_3__CondCode2_0,
1648
  Convert__Reg1_1__Tie0_1_1__Reg1_2,
1649
  Convert__Reg1_1__Reg1_2,
1650
  Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
1651
  Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
1652
  Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
1653
  Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
1654
  Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
1655
  Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0,
1656
  Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1,
1657
  Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0,
1658
  Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0,
1659
  Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
1660
  Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1,
1661
  Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
1662
  Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0,
1663
  Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0,
1664
  Convert__ARMBranchTarget1_1__CondCode2_0,
1665
  ConvertCustom_cvtThumbBranches,
1666
  Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0,
1667
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0,
1668
  Convert__imm_95_0,
1669
  Convert__Imm0_2551_0,
1670
  Convert__Imm0_655351_0,
1671
  Convert__ARMBranchTarget1_0,
1672
  Convert__CondCode2_0__ThumbBranchTarget1_1,
1673
  Convert__Reg1_0,
1674
  Convert__ThumbBranchTarget1_0,
1675
  Convert__Reg1_1__CondCode2_0,
1676
  Convert__CondCode2_0__Reg1_1,
1677
  Convert__CondCode2_0__ARMBranchTarget1_1,
1678
  Convert__CondCode2_0,
1679
  Convert__Reg1_0__ThumbBranchTarget1_1,
1680
  Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
1681
  Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
1682
  Convert__Reg1_1__Reg1_2__CondCode2_0,
1683
  Convert__Reg1_1__ModImmNeg1_2__CondCode2_0,
1684
  Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0,
1685
  Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0,
1686
  Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0,
1687
  Convert__Reg1_1__T2SOImm1_2__CondCode2_0,
1688
  Convert__Reg1_1__ModImm1_2__CondCode2_0,
1689
  Convert__Reg1_2__Reg1_3__CondCode2_0,
1690
  Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0,
1691
  Convert__Reg1_2__T2SOImm1_3__CondCode2_0,
1692
  Convert__Reg1_1__Imm0_2551_2__CondCode2_0,
1693
  Convert__Imm0_311_0,
1694
  Convert__Imm0_311_1,
1695
  Convert__Imm1_0__ProcIFlags1_1,
1696
  Convert__Imm1_0__ProcIFlags1_2,
1697
  Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2,
1698
  Convert__Imm1_0__ProcIFlags1_1__Imm1_2,
1699
  Convert__Imm1_0__ProcIFlags1_2__Imm1_3,
1700
  Convert__Reg1_0__Reg1_1__Reg1_2,
1701
  Convert__imm_95_20__CondCode2_0,
1702
  Convert__Imm0_151_1__CondCode2_0,
1703
  Convert__imm_95_12,
1704
  Convert__imm_95_12__CondCode2_0,
1705
  Convert__imm_95_15,
1706
  Convert__imm_95_15__CondCode2_0,
1707
  Convert__MemBarrierOpt1_0,
1708
  Convert__MemBarrierOpt1_1__CondCode2_0,
1709
  Convert__imm_95_0__CondCode2_0,
1710
  Convert__imm_95_16__CondCode2_0,
1711
  Convert__Reg1_1__FPImm1_2__CondCode2_0,
1712
  Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3,
1713
  Convert__Reg1_1__CondCode2_0__DPRRegList1_2,
1714
  Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0,
1715
  Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0,
1716
  Convert__Imm0_2391_1__CondCode2_0,
1717
  Convert__Imm0_2391_2__CondCode2_0,
1718
  Convert__Imm0_631_0,
1719
  Convert__Imm0_655351_1,
1720
  Convert__InstSyncBarrierOpt1_0,
1721
  Convert__InstSyncBarrierOpt1_1__CondCode2_0,
1722
  Convert__ITCondCode1_1__ITMask1_0,
1723
  Convert__Reg1_1__MemNoOffset1_2__CondCode2_0,
1724
  Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0,
1725
  Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0,
1726
  Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0,
1727
  Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0,
1728
  Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2,
1729
  Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3,
1730
  Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3,
1731
  Convert__Reg1_1__CondCode2_0__RegList1_2,
1732
  Convert__Reg1_2__CondCode2_0__RegList1_3,
1733
  Convert__Reg1_1__CondCode2_0__RegList1_3,
1734
  Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3,
1735
  Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4,
1736
  Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0,
1737
  Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0,
1738
  Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0,
1739
  Convert__Reg1_1__MemThumbRR2_2__CondCode2_0,
1740
  Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0,
1741
  Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0,
1742
  Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0,
1743
  Convert__Reg1_1__MemRegOffset3_2__CondCode2_0,
1744
  Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0,
1745
  Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0,
1746
  Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0,
1747
  Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0,
1748
  Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0,
1749
  Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0,
1750
  Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0,
1751
  Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0,
1752
  Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0,
1753
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0,
1754
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0,
1755
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0,
1756
  Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0,
1757
  Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0,
1758
  Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0,
1759
  Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
1760
  Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
1761
  Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0,
1762
  Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0,
1763
  Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0,
1764
  Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0,
1765
  Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0,
1766
  Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0,
1767
  Convert__Reg1_1__AddrMode33_2__CondCode2_0,
1768
  Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0,
1769
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0,
1770
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0,
1771
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0,
1772
  Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1,
1773
  Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0,
1774
  Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0,
1775
  Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
1776
  Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1,
1777
  Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
1778
  Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
1779
  Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0,
1780
  Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0,
1781
  Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
1782
  Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
1783
  Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
1784
  Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0,
1785
  Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
1786
  Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0,
1787
  Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4,
1788
  Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
1789
  Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
1790
  Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0,
1791
  Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0,
1792
  Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0,
1793
  Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0,
1794
  Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1,
1795
  Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
1796
  Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
1797
  Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
1798
  Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
1799
  Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0,
1800
  Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0,
1801
  Convert__Reg1_2__Reg1_3__CondCode2_0__reg0,
1802
  Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
1803
  Convert__Reg1_0__Reg1_1,
1804
  Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0,
1805
  Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR,
1806
  Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR,
1807
  Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR,
1808
  Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR,
1809
  Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0,
1810
  Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
1811
  Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
1812
  Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0,
1813
  Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
1814
  Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0,
1815
  Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4,
1816
  Convert__Reg1_1__BankedReg1_2__CondCode2_0,
1817
  Convert__Reg1_1__MSRMask1_2__CondCode2_0,
1818
  Convert__BankedReg1_1__Reg1_2__CondCode2_0,
1819
  Convert__MSRMask1_1__Reg1_2__CondCode2_0,
1820
  Convert__MSRMask1_1__ModImm1_2__CondCode2_0,
1821
  Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0,
1822
  ConvertCustom_cvtThumbMultiply,
1823
  Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1,
1824
  Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
1825
  Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
1826
  Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
1827
  Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0,
1828
  Convert__regR8__regR8__imm_95_14__imm_95_0,
1829
  Convert__regR0__regR0__CondCode2_0__reg0,
1830
  Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
1831
  Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0,
1832
  Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0,
1833
  Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0,
1834
  Convert__MemImm12Offset2_0,
1835
  Convert__MemRegOffset3_0,
1836
  Convert__Imm1_1__CondCode2_0,
1837
  Convert__MemNegImm8Offset2_1__CondCode2_0,
1838
  Convert__MemUImm12Offset2_1__CondCode2_0,
1839
  Convert__T2MemRegOffset3_1__CondCode2_0,
1840
  Convert__MemPCRelImm121_1__CondCode2_0,
1841
  Convert__CondCode2_0__RegList1_1,
1842
  Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1,
1843
  Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2,
1844
  Convert__imm_95_4__imm_95_14__imm_95_0,
1845
  Convert__imm_95_4,
1846
  Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0,
1847
  Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0,
1848
  Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0,
1849
  Convert__SetEndImm1_0,
1850
  Convert__Imm0_11_0,
1851
  Convert__imm_95_4__CondCode2_0,
1852
  Convert__imm_95_5__CondCode2_0,
1853
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3,
1854
  Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0,
1855
  Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0,
1856
  Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0,
1857
  Convert__Imm0_311_2,
1858
  Convert__Imm0_311_1__CondCode2_0,
1859
  Convert__Imm0_311_2__CondCode2_0,
1860
  Convert__Imm0_311_3__CondCode2_0,
1861
  Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0,
1862
  Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0,
1863
  Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0,
1864
  Convert__imm_95_0__imm_95_14__imm_95_0,
1865
  Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0,
1866
  Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0,
1867
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0,
1868
  Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0,
1869
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0,
1870
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0,
1871
  Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0,
1872
  Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0,
1873
  Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
1874
  Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0,
1875
  Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
1876
  Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0,
1877
  Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0,
1878
  Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0,
1879
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0,
1880
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0,
1881
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0,
1882
  Convert__Imm0_2551_3__CondCode2_0,
1883
  Convert__Imm0_2551_1__CondCode2_0,
1884
  Convert__Imm24bit1_1__CondCode2_0,
1885
  Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
1886
  Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0,
1887
  Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
1888
  Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0,
1889
  Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
1890
  Convert__MemTBB2_1__CondCode2_0,
1891
  Convert__MemTBH2_1__CondCode2_0,
1892
  Convert__TraceSyncBarrierOpt1_0,
1893
  Convert__TraceSyncBarrierOpt1_1__CondCode2_0,
1894
  Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0,
1895
  Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0,
1896
  Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0,
1897
  Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0,
1898
  Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0,
1899
  Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
1900
  Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0,
1901
  Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0,
1902
  Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0,
1903
  Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0,
1904
  Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0,
1905
  Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0,
1906
  Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0,
1907
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0,
1908
  Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0,
1909
  Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4,
1910
  Convert__Reg1_2__Reg1_2__CondCode2_0,
1911
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4,
1912
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5,
1913
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5,
1914
  Convert__Reg1_2__CondCode2_0,
1915
  Convert__Reg1_3__Reg1_4__CondCode2_0,
1916
  Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0,
1917
  Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0,
1918
  Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0,
1919
  Convert__Reg1_2__Reg1_3,
1920
  Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
1921
  Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
1922
  Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0,
1923
  Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0,
1924
  Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0,
1925
  Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0,
1926
  Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0,
1927
  Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0,
1928
  Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0,
1929
  Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0,
1930
  Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0,
1931
  Convert__Reg1_1__Reg1_2__Reg1_3,
1932
  Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4,
1933
  Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4,
1934
  Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
1935
  Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0,
1936
  Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0,
1937
  Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
1938
  Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0,
1939
  Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0,
1940
  Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0,
1941
  Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
1942
  Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
1943
  Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
1944
  Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
1945
  Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
1946
  Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
1947
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
1948
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
1949
  Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
1950
  Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
1951
  Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0,
1952
  Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
1953
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
1954
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
1955
  Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
1956
  Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
1957
  Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
1958
  Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
1959
  Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
1960
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
1961
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
1962
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
1963
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
1964
  Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
1965
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
1966
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
1967
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
1968
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
1969
  Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
1970
  Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0,
1971
  Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
1972
  Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
1973
  Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
1974
  Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0,
1975
  Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
1976
  Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
1977
  Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
1978
  Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
1979
  Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
1980
  Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
1981
  Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
1982
  Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0,
1983
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
1984
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
1985
  Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
1986
  Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
1987
  Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
1988
  Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
1989
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
1990
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
1991
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
1992
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
1993
  Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
1994
  Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
1995
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
1996
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
1997
  Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
1998
  Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
1999
  Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2000
  Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2001
  Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0,
2002
  Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2003
  Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2004
  Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2005
  Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2006
  Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2007
  Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2008
  Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2009
  Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2010
  Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2011
  Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2012
  Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2013
  Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2014
  Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2015
  Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0,
2016
  Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0,
2017
  Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0,
2018
  Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0,
2019
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2020
  Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2021
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2022
  Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0,
2023
  Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2024
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2025
  Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2026
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2027
  Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2028
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2029
  Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0,
2030
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2031
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2032
  Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2033
  Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2034
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2035
  Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2036
  Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2037
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2038
  Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2039
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2040
  Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2041
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2042
  Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2043
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2044
  Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0,
2045
  Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0,
2046
  Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0,
2047
  Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0,
2048
  Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3,
2049
  Convert__Reg1_1__CondCode2_0__SPRRegList1_2,
2050
  Convert__Reg1_1__AddrMode52_2__CondCode2_0,
2051
  Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0,
2052
  Convert__Reg1_2__AddrMode52_3__CondCode2_0,
2053
  Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2054
  Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2055
  Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0,
2056
  Convert__Reg1_2__FPImm1_3__CondCode2_0,
2057
  Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0,
2058
  Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0,
2059
  Convert__Reg1_2__NEONi16splat1_3__CondCode2_0,
2060
  Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0,
2061
  Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0,
2062
  Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0,
2063
  Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0,
2064
  Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0,
2065
  Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0,
2066
  Convert__Reg1_2__NEONi64splat1_3__CondCode2_0,
2067
  Convert__Reg1_2__NEONi8splat1_3__CondCode2_0,
2068
  Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0,
2069
  Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0,
2070
  Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0,
2071
  Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0,
2072
  Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
2073
  Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
2074
  Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2075
  Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2076
  Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0,
2077
  Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0,
2078
  Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0,
2079
  Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0,
2080
  Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1,
2081
  Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1,
2082
  Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2,
2083
  Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2,
2084
  Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0,
2085
  Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0,
2086
  Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0,
2087
  Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0,
2088
  Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0,
2089
  Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0,
2090
  Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0,
2091
  Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0,
2092
  Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0,
2093
  Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0,
2094
  Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0,
2095
  Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0,
2096
  Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0,
2097
  Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0,
2098
  Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0,
2099
  Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0,
2100
  Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0,
2101
  Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0,
2102
  Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3,
2103
  Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4,
2104
  Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0,
2105
  Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0,
2106
  Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0,
2107
  Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0,
2108
  Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0,
2109
  Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0,
2110
  Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0,
2111
  Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0,
2112
  Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
2113
  Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
2114
  Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
2115
  Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
2116
  Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
2117
  Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0,
2118
  Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
2119
  Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0,
2120
  Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
2121
  Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0,
2122
  Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
2123
  Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0,
2124
  Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0,
2125
  Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
2126
  Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
2127
  Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0,
2128
  Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
2129
  Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
2130
  Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0,
2131
  Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
2132
  Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
2133
  Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
2134
  Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
2135
  Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0,
2136
  Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0,
2137
  Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0,
2138
  Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0,
2139
  Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0,
2140
  Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0,
2141
  Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0,
2142
  Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0,
2143
  Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0,
2144
  Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0,
2145
  Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0,
2146
  Convert__imm_95_2__CondCode2_0,
2147
  Convert__imm_95_3__CondCode2_0,
2148
  Convert__imm_95_1__CondCode2_0,
2149
  CVT_NUM_SIGNATURES
2150
};
2151
2152
} // end anonymous namespace
2153
2154
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][17] = {
2155
  // Convert_NoOperands
2156
  { CVT_Done },
2157
  // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1
2158
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2159
  // Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
2160
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2161
  // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
2162
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2163
  // Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
2164
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2165
  // Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
2166
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2167
  // Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
2168
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2169
  // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
2170
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2171
  // Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
2172
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2173
  // Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
2174
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2175
  // Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
2176
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2177
  // Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0
2178
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedRegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2179
  // Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0
2180
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2181
  // Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0
2182
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2183
  // Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
2184
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2185
  // Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0
2186
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addRegShiftedImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2187
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0
2188
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2189
  // Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0
2190
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2191
  // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0
2192
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2193
  // Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0
2194
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2195
  // Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0
2196
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_4095NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2197
  // Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1
2198
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2199
  // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1
2200
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2201
  // Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1
2202
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addThumbModImmNeg8_95_255Operands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2203
  // Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
2204
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2205
  // Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0
2206
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2207
  // Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0
2208
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2209
  // Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0
2210
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2211
  // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0
2212
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2213
  // Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0
2214
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_1020s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2215
  // Convert__Reg1_1__Imm0_40951_3__CondCode2_0
2216
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2217
  // Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0
2218
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2219
  // Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0
2220
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_4095NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2221
  // Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0
2222
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2223
  // Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
2224
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2225
  // Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1
2226
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2227
  // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1
2228
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2229
  // Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1
2230
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addThumbModImmNeg1_95_7Operands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2231
  // Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
2232
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2233
  // Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0
2234
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2235
  // Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0
2236
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2237
  // Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0
2238
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNegOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2239
  // Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0
2240
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2241
  // Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0
2242
  { CVT_95_Reg, 2, CVT_95_addUnsignedOffset_95_b8s2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2243
  // Convert__Reg1_1__Imm1_2__CondCode2_0
2244
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2245
  // Convert__Reg1_1__AdrLabel1_2__CondCode2_0
2246
  { CVT_95_Reg, 2, CVT_95_addAdrLabelOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2247
  // Convert__Reg1_2__Imm1_3__CondCode2_0
2248
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2249
  // Convert__Reg1_1__Tie0_1_1__Reg1_2
2250
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_Done },
2251
  // Convert__Reg1_1__Reg1_2
2252
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2253
  // Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
2254
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2255
  // Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
2256
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2257
  // Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
2258
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2259
  // Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
2260
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2261
  // Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
2262
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2263
  // Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0
2264
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNotOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2265
  // Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1
2266
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2267
  // Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0
2268
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2269
  // Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0
2270
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2271
  // Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
2272
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2273
  // Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1
2274
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2275
  // Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
2276
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2277
  // Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0
2278
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2279
  // Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0
2280
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2281
  // Convert__ARMBranchTarget1_1__CondCode2_0
2282
  { CVT_95_addARMBranchTargetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2283
  // ConvertCustom_cvtThumbBranches
2284
  { CVT_cvtThumbBranches, 0, CVT_Done },
2285
  // Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0
2286
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addBitfieldOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2287
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0
2288
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addBitfieldOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2289
  // Convert__imm_95_0
2290
  { CVT_imm_95_0, 0, CVT_Done },
2291
  // Convert__Imm0_2551_0
2292
  { CVT_95_addImmOperands, 1, CVT_Done },
2293
  // Convert__Imm0_655351_0
2294
  { CVT_95_addImmOperands, 1, CVT_Done },
2295
  // Convert__ARMBranchTarget1_0
2296
  { CVT_95_addARMBranchTargetOperands, 1, CVT_Done },
2297
  // Convert__CondCode2_0__ThumbBranchTarget1_1
2298
  { CVT_95_addCondCodeOperands, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
2299
  // Convert__Reg1_0
2300
  { CVT_95_Reg, 1, CVT_Done },
2301
  // Convert__ThumbBranchTarget1_0
2302
  { CVT_95_addThumbBranchTargetOperands, 1, CVT_Done },
2303
  // Convert__Reg1_1__CondCode2_0
2304
  { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2305
  // Convert__CondCode2_0__Reg1_1
2306
  { CVT_95_addCondCodeOperands, 1, CVT_95_Reg, 2, CVT_Done },
2307
  // Convert__CondCode2_0__ARMBranchTarget1_1
2308
  { CVT_95_addCondCodeOperands, 1, CVT_95_addARMBranchTargetOperands, 2, CVT_Done },
2309
  // Convert__CondCode2_0
2310
  { CVT_95_addCondCodeOperands, 1, CVT_Done },
2311
  // Convert__Reg1_0__ThumbBranchTarget1_1
2312
  { CVT_95_Reg, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
2313
  // Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
2314
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
2315
  // Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
2316
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2317
  // Convert__Reg1_1__Reg1_2__CondCode2_0
2318
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2319
  // Convert__Reg1_1__ModImmNeg1_2__CondCode2_0
2320
  { CVT_95_Reg, 2, CVT_95_addModImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2321
  // Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0
2322
  { CVT_95_Reg, 2, CVT_95_addT2SOImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2323
  // Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0
2324
  { CVT_95_Reg, 2, CVT_95_addRegShiftedImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2325
  // Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0
2326
  { CVT_95_Reg, 2, CVT_95_addRegShiftedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2327
  // Convert__Reg1_1__T2SOImm1_2__CondCode2_0
2328
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2329
  // Convert__Reg1_1__ModImm1_2__CondCode2_0
2330
  { CVT_95_Reg, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2331
  // Convert__Reg1_2__Reg1_3__CondCode2_0
2332
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2333
  // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0
2334
  { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2335
  // Convert__Reg1_2__T2SOImm1_3__CondCode2_0
2336
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2337
  // Convert__Reg1_1__Imm0_2551_2__CondCode2_0
2338
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2339
  // Convert__Imm0_311_0
2340
  { CVT_95_addImmOperands, 1, CVT_Done },
2341
  // Convert__Imm0_311_1
2342
  { CVT_95_addImmOperands, 2, CVT_Done },
2343
  // Convert__Imm1_0__ProcIFlags1_1
2344
  { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_Done },
2345
  // Convert__Imm1_0__ProcIFlags1_2
2346
  { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_Done },
2347
  // Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2
2348
  { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2349
  // Convert__Imm1_0__ProcIFlags1_1__Imm1_2
2350
  { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2351
  // Convert__Imm1_0__ProcIFlags1_2__Imm1_3
2352
  { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2353
  // Convert__Reg1_0__Reg1_1__Reg1_2
2354
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2355
  // Convert__imm_95_20__CondCode2_0
2356
  { CVT_imm_95_20, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2357
  // Convert__Imm0_151_1__CondCode2_0
2358
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2359
  // Convert__imm_95_12
2360
  { CVT_imm_95_12, 0, CVT_Done },
2361
  // Convert__imm_95_12__CondCode2_0
2362
  { CVT_imm_95_12, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2363
  // Convert__imm_95_15
2364
  { CVT_imm_95_15, 0, CVT_Done },
2365
  // Convert__imm_95_15__CondCode2_0
2366
  { CVT_imm_95_15, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2367
  // Convert__MemBarrierOpt1_0
2368
  { CVT_95_addMemBarrierOptOperands, 1, CVT_Done },
2369
  // Convert__MemBarrierOpt1_1__CondCode2_0
2370
  { CVT_95_addMemBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2371
  // Convert__imm_95_0__CondCode2_0
2372
  { CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2373
  // Convert__imm_95_16__CondCode2_0
2374
  { CVT_imm_95_16, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2375
  // Convert__Reg1_1__FPImm1_2__CondCode2_0
2376
  { CVT_95_Reg, 2, CVT_95_addFPImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2377
  // Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3
2378
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 4, CVT_Done },
2379
  // Convert__Reg1_1__CondCode2_0__DPRRegList1_2
2380
  { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
2381
  // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0
2382
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2383
  // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0
2384
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2385
  // Convert__Imm0_2391_1__CondCode2_0
2386
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2387
  // Convert__Imm0_2391_2__CondCode2_0
2388
  { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2389
  // Convert__Imm0_631_0
2390
  { CVT_95_addImmOperands, 1, CVT_Done },
2391
  // Convert__Imm0_655351_1
2392
  { CVT_95_addImmOperands, 2, CVT_Done },
2393
  // Convert__InstSyncBarrierOpt1_0
2394
  { CVT_95_addInstSyncBarrierOptOperands, 1, CVT_Done },
2395
  // Convert__InstSyncBarrierOpt1_1__CondCode2_0
2396
  { CVT_95_addInstSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2397
  // Convert__ITCondCode1_1__ITMask1_0
2398
  { CVT_95_addITCondCodeOperands, 2, CVT_95_addITMaskOperands, 1, CVT_Done },
2399
  // Convert__Reg1_1__MemNoOffset1_2__CondCode2_0
2400
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2401
  // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0
2402
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2403
  // Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0
2404
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2405
  // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0
2406
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCoprocOptionOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2407
  // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0
2408
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addPostIdxImm8s4Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2409
  // Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2
2410
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addAddrMode5Operands, 3, CVT_Done },
2411
  // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3
2412
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCoprocOptionOperands, 4, CVT_Done },
2413
  // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3
2414
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addPostIdxImm8s4Operands, 4, CVT_Done },
2415
  // Convert__Reg1_1__CondCode2_0__RegList1_2
2416
  { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done },
2417
  // Convert__Reg1_2__CondCode2_0__RegList1_3
2418
  { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
2419
  // Convert__Reg1_1__CondCode2_0__RegList1_3
2420
  { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
2421
  // Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3
2422
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
2423
  // Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4
2424
  { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 5, CVT_Done },
2425
  // Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0
2426
  { CVT_95_Reg, 2, CVT_95_addThumbMemPCOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2427
  // Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0
2428
  { CVT_95_Reg, 2, CVT_95_addConstPoolAsmImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2429
  // Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0
2430
  { CVT_95_Reg, 2, CVT_95_addMemThumbRIs4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2431
  // Convert__Reg1_1__MemThumbRR2_2__CondCode2_0
2432
  { CVT_95_Reg, 2, CVT_95_addMemThumbRROperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2433
  // Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0
2434
  { CVT_95_Reg, 2, CVT_95_addMemThumbSPIOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2435
  // Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0
2436
  { CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2437
  // Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0
2438
  { CVT_95_Reg, 2, CVT_95_addMemNegImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2439
  // Convert__Reg1_1__MemRegOffset3_2__CondCode2_0
2440
  { CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2441
  // Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0
2442
  { CVT_95_Reg, 2, CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2443
  // Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0
2444
  { CVT_95_Reg, 2, CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2445
  // Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0
2446
  { CVT_95_Reg, 2, CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2447
  // Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0
2448
  { CVT_95_Reg, 3, CVT_95_addConstPoolAsmImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2449
  // Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0
2450
  { CVT_95_Reg, 3, CVT_95_addMemUImm12OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2451
  // Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0
2452
  { CVT_95_Reg, 3, CVT_95_addT2MemRegOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2453
  // Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0
2454
  { CVT_95_Reg, 3, CVT_95_addMemPCRelImm12Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2455
  // Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0
2456
  { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2457
  // Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0
2458
  { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2459
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0
2460
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2461
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0
2462
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2463
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0
2464
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2465
  // Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0
2466
  { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2467
  // Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0
2468
  { CVT_95_Reg, 2, CVT_95_addMemThumbRIs1Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2469
  // Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0
2470
  { CVT_95_Reg, 2, CVT_95_addMemPosImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2471
  // Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
2472
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2473
  // Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
2474
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2475
  // Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0
2476
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2477
  // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0
2478
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2479
  // Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0
2480
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2481
  // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0
2482
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2483
  // Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0
2484
  { CVT_95_Reg, 2, CVT_95_addMemImm0_95_1020s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2485
  // Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0
2486
  { CVT_95_Reg, 2, CVT_95_addMemThumbRIs2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2487
  // Convert__Reg1_1__AddrMode33_2__CondCode2_0
2488
  { CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2489
  // Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0
2490
  { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2491
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0
2492
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2493
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0
2494
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2495
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0
2496
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2497
  // Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1
2498
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2499
  // Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0
2500
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2501
  // Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0
2502
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2503
  // Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
2504
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2505
  // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1
2506
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2507
  // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
2508
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2509
  // Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
2510
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2511
  // Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0
2512
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2513
  // Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0
2514
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2515
  // Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
2516
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2517
  // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
2518
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2519
  // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
2520
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
2521
  // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0
2522
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
2523
  // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
2524
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2525
  // Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0
2526
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2527
  // Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4
2528
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_Done },
2529
  // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
2530
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2531
  // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
2532
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2533
  // Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0
2534
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2535
  // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0
2536
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2537
  // Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0
2538
  { CVT_95_Reg, 2, CVT_95_addT2SOImmNotOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2539
  // Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0
2540
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2541
  // Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1
2542
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2543
  // Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
2544
  { CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2545
  // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
2546
  { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2547
  // Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
2548
  { CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2549
  // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
2550
  { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2551
  // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0
2552
  { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2553
  // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0
2554
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2555
  // Convert__Reg1_2__Reg1_3__CondCode2_0__reg0
2556
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2557
  // Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
2558
  { CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2559
  // Convert__Reg1_0__Reg1_1
2560
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
2561
  // Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0
2562
  { CVT_95_Reg, 1, CVT_regCPSR, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2563
  // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR
2564
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2565
  // Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR
2566
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2567
  // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR
2568
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2569
  // Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR
2570
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2571
  // Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0
2572
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2573
  // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
2574
  { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2575
  // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
2576
  { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
2577
  // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0
2578
  { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
2579
  // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
2580
  { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2581
  // Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0
2582
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2583
  // Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4
2584
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 5, CVT_Done },
2585
  // Convert__Reg1_1__BankedReg1_2__CondCode2_0
2586
  { CVT_95_Reg, 2, CVT_95_addBankedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2587
  // Convert__Reg1_1__MSRMask1_2__CondCode2_0
2588
  { CVT_95_Reg, 2, CVT_95_addMSRMaskOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2589
  // Convert__BankedReg1_1__Reg1_2__CondCode2_0
2590
  { CVT_95_addBankedRegOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2591
  // Convert__MSRMask1_1__Reg1_2__CondCode2_0
2592
  { CVT_95_addMSRMaskOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2593
  // Convert__MSRMask1_1__ModImm1_2__CondCode2_0
2594
  { CVT_95_addMSRMaskOperands, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2595
  // Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0
2596
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2597
  // ConvertCustom_cvtThumbMultiply
2598
  { CVT_cvtThumbMultiply, 0, CVT_Done },
2599
  // Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1
2600
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2601
  // Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
2602
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2603
  // Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
2604
  { CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2605
  // Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
2606
  { CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2607
  // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0
2608
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2609
  // Convert__regR8__regR8__imm_95_14__imm_95_0
2610
  { CVT_regR8, 0, CVT_regR8, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2611
  // Convert__regR0__regR0__CondCode2_0__reg0
2612
  { CVT_regR0, 0, CVT_regR0, 0, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2613
  // Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
2614
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2615
  // Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0
2616
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2617
  // Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0
2618
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2619
  // Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0
2620
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addPKHASRImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2621
  // Convert__MemImm12Offset2_0
2622
  { CVT_95_addMemImm12OffsetOperands, 1, CVT_Done },
2623
  // Convert__MemRegOffset3_0
2624
  { CVT_95_addMemRegOffsetOperands, 1, CVT_Done },
2625
  // Convert__Imm1_1__CondCode2_0
2626
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2627
  // Convert__MemNegImm8Offset2_1__CondCode2_0
2628
  { CVT_95_addMemNegImm8OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2629
  // Convert__MemUImm12Offset2_1__CondCode2_0
2630
  { CVT_95_addMemUImm12OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2631
  // Convert__T2MemRegOffset3_1__CondCode2_0
2632
  { CVT_95_addT2MemRegOffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2633
  // Convert__MemPCRelImm121_1__CondCode2_0
2634
  { CVT_95_addMemPCRelImm12Operands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2635
  // Convert__CondCode2_0__RegList1_1
2636
  { CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done },
2637
  // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1
2638
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done },
2639
  // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2
2640
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done },
2641
  // Convert__imm_95_4__imm_95_14__imm_95_0
2642
  { CVT_imm_95_4, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2643
  // Convert__imm_95_4
2644
  { CVT_imm_95_4, 0, CVT_Done },
2645
  // Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0
2646
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2647
  // Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0
2648
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2649
  // Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0
2650
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addImm1_95_32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2651
  // Convert__SetEndImm1_0
2652
  { CVT_95_addImmOperands, 1, CVT_Done },
2653
  // Convert__Imm0_11_0
2654
  { CVT_95_addImmOperands, 1, CVT_Done },
2655
  // Convert__imm_95_4__CondCode2_0
2656
  { CVT_imm_95_4, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2657
  // Convert__imm_95_5__CondCode2_0
2658
  { CVT_imm_95_5, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2659
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3
2660
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2661
  // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0
2662
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
2663
  // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0
2664
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2665
  // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0
2666
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2667
  // Convert__Imm0_311_2
2668
  { CVT_95_addImmOperands, 3, CVT_Done },
2669
  // Convert__Imm0_311_1__CondCode2_0
2670
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2671
  // Convert__Imm0_311_2__CondCode2_0
2672
  { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2673
  // Convert__Imm0_311_3__CondCode2_0
2674
  { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2675
  // Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0
2676
  { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2677
  // Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0
2678
  { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2679
  // Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0
2680
  { CVT_95_Reg, 2, CVT_95_addImm1_95_16Operands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2681
  // Convert__imm_95_0__imm_95_14__imm_95_0
2682
  { CVT_imm_95_0, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2683
  // Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0
2684
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemNoOffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2685
  // Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0
2686
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2687
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0
2688
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2689
  // Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0
2690
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2691
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0
2692
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2693
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0
2694
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2695
  // Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0
2696
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2697
  // Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0
2698
  { CVT_95_Reg, 2, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2699
  // Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
2700
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2701
  // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0
2702
  { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2703
  // Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
2704
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2705
  // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0
2706
  { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2707
  // Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0
2708
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm0_95_1020s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2709
  // Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0
2710
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2711
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0
2712
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2713
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0
2714
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2715
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0
2716
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2717
  // Convert__Imm0_2551_3__CondCode2_0
2718
  { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2719
  // Convert__Imm0_2551_1__CondCode2_0
2720
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2721
  // Convert__Imm24bit1_1__CondCode2_0
2722
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2723
  // Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
2724
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2725
  // Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0
2726
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2727
  // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
2728
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2729
  // Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0
2730
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRotImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2731
  // Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
2732
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2733
  // Convert__MemTBB2_1__CondCode2_0
2734
  { CVT_95_addMemTBBOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2735
  // Convert__MemTBH2_1__CondCode2_0
2736
  { CVT_95_addMemTBHOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2737
  // Convert__TraceSyncBarrierOpt1_0
2738
  { CVT_95_addTraceSyncBarrierOptOperands, 1, CVT_Done },
2739
  // Convert__TraceSyncBarrierOpt1_1__CondCode2_0
2740
  { CVT_95_addTraceSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2741
  // Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0
2742
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2743
  // Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0
2744
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2745
  // Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0
2746
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2747
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0
2748
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2749
  // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0
2750
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2751
  // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
2752
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2753
  // Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0
2754
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2755
  // Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0
2756
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2757
  // Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0
2758
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2759
  // Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0
2760
  { CVT_95_Reg, 3, CVT_95_addNEONi16splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2761
  // Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0
2762
  { CVT_95_Reg, 3, CVT_95_addNEONi32splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2763
  // Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0
2764
  { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
2765
  // Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0
2766
  { CVT_95_Reg, 3, CVT_95_addNEONi32splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
2767
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0
2768
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2769
  // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0
2770
  { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2771
  // Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4
2772
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
2773
  // Convert__Reg1_2__Reg1_2__CondCode2_0
2774
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2775
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4
2776
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
2777
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5
2778
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex64Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
2779
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5
2780
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
2781
  // Convert__Reg1_2__CondCode2_0
2782
  { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2783
  // Convert__Reg1_3__Reg1_4__CondCode2_0
2784
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2785
  // Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0
2786
  { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2787
  // Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0
2788
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2789
  // Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0
2790
  { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2791
  // Convert__Reg1_2__Reg1_3
2792
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2793
  // Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
2794
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2795
  // Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
2796
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2797
  // Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0
2798
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex8Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2799
  // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0
2800
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2801
  // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0
2802
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2803
  // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0
2804
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2805
  // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0
2806
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2807
  // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0
2808
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2809
  // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0
2810
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2811
  // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0
2812
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2813
  // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0
2814
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2815
  // Convert__Reg1_1__Reg1_2__Reg1_3
2816
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2817
  // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4
2818
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done },
2819
  // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4
2820
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
2821
  // Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
2822
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2823
  // Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0
2824
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2825
  // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0
2826
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2827
  // Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
2828
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2829
  // Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0
2830
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2831
  // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0
2832
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2833
  // Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0
2834
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2835
  // Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
2836
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2837
  // Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
2838
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2839
  // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0
2840
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2841
  // Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2842
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2843
  // Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2844
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2845
  // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2846
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2847
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
2848
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2849
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
2850
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2851
  // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
2852
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2853
  // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
2854
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2855
  // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0
2856
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2857
  // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
2858
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2859
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
2860
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2861
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
2862
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2863
  // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
2864
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2865
  // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
2866
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2867
  // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
2868
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2869
  // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
2870
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2871
  // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
2872
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2873
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
2874
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2875
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
2876
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2877
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
2878
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2879
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
2880
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2881
  // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
2882
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2883
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
2884
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2885
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2886
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2887
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
2888
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2889
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2890
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2891
  // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2892
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2893
  // Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0
2894
  { CVT_95_Reg, 4, CVT_95_addAlignedMemoryOperands, 9, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2895
  // Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
2896
  { CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2897
  // Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
2898
  { CVT_95_Reg, 4, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2899
  // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
2900
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2901
  // Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0
2902
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2903
  // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
2904
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2905
  // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
2906
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2907
  // Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2908
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2909
  // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2910
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2911
  // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0
2912
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2913
  // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0
2914
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2915
  // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
2916
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2917
  // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0
2918
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2919
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
2920
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2921
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
2922
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2923
  // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
2924
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2925
  // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
2926
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2927
  // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
2928
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2929
  // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
2930
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2931
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
2932
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2933
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
2934
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2935
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
2936
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2937
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
2938
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2939
  // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2940
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2941
  // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2942
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2943
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
2944
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2945
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
2946
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2947
  // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
2948
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2949
  // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2950
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2951
  // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2952
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2953
  // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2954
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2955
  // Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0
2956
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2957
  // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2958
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2959
  // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2960
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2961
  // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2962
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2963
  // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2964
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2965
  // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2966
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2967
  // Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2968
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2969
  // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2970
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2971
  // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2972
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2973
  // Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2974
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2975
  // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2976
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2977
  // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2978
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2979
  // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2980
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2981
  // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2982
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2983
  // Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0
2984
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addCondCodeOperands, 1, CVT_Done },
2985
  // Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0
2986
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done },
2987
  // Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0
2988
  { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_addAlignedMemoryOperands, 14, CVT_95_addCondCodeOperands, 1, CVT_Done },
2989
  // Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0
2990
  { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 14, CVT_95_addImmOperands, 15, CVT_95_addCondCodeOperands, 1, CVT_Done },
2991
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2992
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2993
  // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
2994
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2995
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2996
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2997
  // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0
2998
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2999
  // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
3000
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3001
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
3002
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3003
  // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
3004
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3005
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
3006
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3007
  // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
3008
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3009
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3010
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3011
  // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0
3012
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3013
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3014
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3015
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3016
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3017
  // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
3018
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3019
  // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3020
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3021
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3022
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3023
  // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
3024
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3025
  // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3026
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3027
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
3028
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3029
  // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3030
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3031
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
3032
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3033
  // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3034
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3035
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3036
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3037
  // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3038
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3039
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3040
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3041
  // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0
3042
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done },
3043
  // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0
3044
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_addCondCodeOperands, 1, CVT_Done },
3045
  // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0
3046
  { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addCondCodeOperands, 1, CVT_Done },
3047
  // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0
3048
  { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addImmOperands, 18, CVT_95_addCondCodeOperands, 1, CVT_Done },
3049
  // Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3
3050
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 4, CVT_Done },
3051
  // Convert__Reg1_1__CondCode2_0__SPRRegList1_2
3052
  { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
3053
  // Convert__Reg1_1__AddrMode52_2__CondCode2_0
3054
  { CVT_95_Reg, 2, CVT_95_addAddrMode5Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3055
  // Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0
3056
  { CVT_95_Reg, 3, CVT_95_addAddrMode5FP16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3057
  // Convert__Reg1_2__AddrMode52_3__CondCode2_0
3058
  { CVT_95_Reg, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3059
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
3060
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3061
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
3062
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3063
  // Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0
3064
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3065
  // Convert__Reg1_2__FPImm1_3__CondCode2_0
3066
  { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3067
  // Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0
3068
  { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3069
  // Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0
3070
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3071
  // Convert__Reg1_2__NEONi16splat1_3__CondCode2_0
3072
  { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3073
  // Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0
3074
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3075
  // Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0
3076
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3077
  // Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0
3078
  { CVT_95_Reg, 3, CVT_95_addNEONi32vmovNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3079
  // Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0
3080
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3081
  // Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0
3082
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3083
  // Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0
3084
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi32ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3085
  // Convert__Reg1_2__NEONi64splat1_3__CondCode2_0
3086
  { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3087
  // Convert__Reg1_2__NEONi8splat1_3__CondCode2_0
3088
  { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3089
  // Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0
3090
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3091
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0
3092
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3093
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0
3094
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3095
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0
3096
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3097
  // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
3098
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3099
  // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
3100
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3101
  // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
3102
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3103
  // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
3104
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3105
  // Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0
3106
  { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3107
  // Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0
3108
  { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3109
  // Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0
3110
  { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3111
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0
3112
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3113
  // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1
3114
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 2, CVT_Done },
3115
  // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1
3116
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 2, CVT_Done },
3117
  // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2
3118
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
3119
  // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2
3120
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
3121
  // Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0
3122
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3123
  // Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0
3124
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3125
  // Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0
3126
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3127
  // Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0
3128
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3129
  // Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0
3130
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3131
  // Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0
3132
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3133
  // Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0
3134
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3135
  // Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0
3136
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3137
  // Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0
3138
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3139
  // Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0
3140
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3141
  // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0
3142
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3143
  // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0
3144
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3145
  // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0
3146
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3147
  // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0
3148
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3149
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0
3150
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3151
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0
3152
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3153
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0
3154
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3155
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0
3156
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3157
  // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3
3158
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3159
  // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4
3160
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
3161
  // Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0
3162
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3163
  // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0
3164
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3165
  // Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0
3166
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3167
  // Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0
3168
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3169
  // Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0
3170
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3171
  // Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0
3172
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3173
  // Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0
3174
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3175
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0
3176
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3177
  // Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
3178
  { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3179
  // Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
3180
  { CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3181
  // Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
3182
  { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3183
  // Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
3184
  { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3185
  // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
3186
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3187
  // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0
3188
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3189
  // Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
3190
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3191
  // Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0
3192
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3193
  // Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
3194
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3195
  // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0
3196
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3197
  // Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
3198
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3199
  // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0
3200
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3201
  // Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0
3202
  { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3203
  // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
3204
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3205
  // Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
3206
  { CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3207
  // Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0
3208
  { CVT_imm_95_0, 0, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_addImmOperands, 11, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3209
  // Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
3210
  { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3211
  // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
3212
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3213
  // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0
3214
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3215
  // Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
3216
  { CVT_95_addAlignedMemoryOperands, 8, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3217
  // Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
3218
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3219
  // Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
3220
  { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
3221
  // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
3222
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
3223
  // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0
3224
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
3225
  // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0
3226
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3227
  // Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0
3228
  { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3229
  // Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0
3230
  { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3231
  // Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0
3232
  { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3233
  // Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0
3234
  { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3235
  // Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0
3236
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3237
  // Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0
3238
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3239
  // Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0
3240
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3241
  // Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0
3242
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3243
  // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0
3244
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
3245
  // Convert__imm_95_2__CondCode2_0
3246
  { CVT_imm_95_2, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
3247
  // Convert__imm_95_3__CondCode2_0
3248
  { CVT_imm_95_3, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
3249
  // Convert__imm_95_1__CondCode2_0
3250
  { CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
3251
};
3252
3253
void ARMAsmParser::
3254
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
3255
43.1k
                const OperandVector &Operands) {
3256
43.1k
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
3257
43.1k
  const uint8_t *Converter = ConversionTable[Kind];
3258
43.1k
  unsigned OpIdx;
3259
43.1k
  Inst.setOpcode(Opcode);
3260
180k
  for (const uint8_t *p = Converter; *p; 
p+= 2137k
) {
3261
137k
    OpIdx = *(p + 1);
3262
137k
    switch (*p) {
3263
137k
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
3264
137k
    case CVT_Reg:
3265
0
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
3266
0
      break;
3267
137k
    case CVT_Tied: {
3268
3.31k
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
3269
3.31k
                          std::begin(TiedAsmOperandTable)) &&
3270
3.31k
             "Tied operand not found");
3271
3.31k
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
3272
3.31k
      if (TiedResOpnd != (uint8_t) -1)
3273
3.31k
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
3274
3.31k
      break;
3275
137k
    }
3276
137k
    case CVT_95_Reg:
3277
50.0k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
3278
50.0k
      break;
3279
137k
    case CVT_95_addCCOutOperands:
3280
7.22k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addCCOutOperands(Inst, 1);
3281
7.22k
      break;
3282
137k
    case CVT_95_addCondCodeOperands:
3283
32.1k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 2);
3284
32.1k
      break;
3285
137k
    case CVT_95_addRegShiftedRegOperands:
3286
241
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedRegOperands(Inst, 3);
3287
241
      break;
3288
137k
    case CVT_95_addModImmOperands:
3289
1.09k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmOperands(Inst, 1);
3290
1.09k
      break;
3291
137k
    case CVT_95_addModImmNotOperands:
3292
49
      static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNotOperands(Inst, 1);
3293
49
      break;
3294
137k
    case CVT_95_addRegShiftedImmOperands:
3295
2.30k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedImmOperands(Inst, 2);
3296
2.30k
      break;
3297
137k
    case CVT_95_addImmOperands:
3298
5.56k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
3299
5.56k
      break;
3300
137k
    case CVT_95_addT2SOImmNotOperands:
3301
69
      static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNotOperands(Inst, 1);
3302
69
      break;
3303
137k
    case CVT_95_addImm0_95_508s4Operands:
3304
51
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4Operands(Inst, 1);
3305
51
      break;
3306
137k
    case CVT_regSP:
3307
315
      Inst.addOperand(MCOperand::createReg(ARM::SP));
3308
315
      break;
3309
137k
    case CVT_95_addImm0_95_508s4NegOperands:
3310
6
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4NegOperands(Inst, 1);
3311
6
      break;
3312
137k
    case CVT_95_addImm0_95_4095NegOperands:
3313
18
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_4095NegOperands(Inst, 1);
3314
18
      break;
3315
137k
    case CVT_95_addThumbModImmNeg8_95_255Operands:
3316
4
      static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg8_255Operands(Inst, 1);
3317
4
      break;
3318
137k
    case CVT_95_addT2SOImmNegOperands:
3319
67
      static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNegOperands(Inst, 1);
3320
67
      break;
3321
137k
    case CVT_95_addModImmNegOperands:
3322
36
      static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNegOperands(Inst, 1);
3323
36
      break;
3324
137k
    case CVT_95_addImm0_95_1020s4Operands:
3325
41
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_1020s4Operands(Inst, 1);
3326
41
      break;
3327
137k
    case CVT_95_addThumbModImmNeg1_95_7Operands:
3328
4
      static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg1_7Operands(Inst, 1);
3329
4
      break;
3330
137k
    case CVT_95_addUnsignedOffset_95_b8s2Operands:
3331
31
      static_cast<ARMOperand&>(*Operands[OpIdx]).addUnsignedOffset_b8s2Operands(Inst, 1);
3332
31
      break;
3333
137k
    case CVT_95_addAdrLabelOperands:
3334
26
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1);
3335
26
      break;
3336
137k
    case CVT_95_addARMBranchTargetOperands:
3337
1.19k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addARMBranchTargetOperands(Inst, 1);
3338
1.19k
      break;
3339
137k
    case CVT_cvtThumbBranches:
3340
946
      cvtThumbBranches(Inst, Operands);
3341
946
      break;
3342
137k
    case CVT_95_addBitfieldOperands:
3343
45
      static_cast<ARMOperand&>(*Operands[OpIdx]).addBitfieldOperands(Inst, 1);
3344
45
      break;
3345
137k
    case CVT_imm_95_0:
3346
1.44k
      Inst.addOperand(MCOperand::createImm(0));
3347
1.44k
      break;
3348
137k
    case CVT_95_addThumbBranchTargetOperands:
3349
318
      static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbBranchTargetOperands(Inst, 1);
3350
318
      break;
3351
137k
    case CVT_95_addCoprocNumOperands:
3352
1.40k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocNumOperands(Inst, 1);
3353
1.40k
      break;
3354
137k
    case CVT_95_addCoprocRegOperands:
3355
1.52k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocRegOperands(Inst, 1);
3356
1.52k
      break;
3357
137k
    case CVT_95_addProcIFlagsOperands:
3358
71
      static_cast<ARMOperand&>(*Operands[OpIdx]).addProcIFlagsOperands(Inst, 1);
3359
71
      break;
3360
137k
    case CVT_imm_95_20:
3361
8
      Inst.addOperand(MCOperand::createImm(20));
3362
8
      break;
3363
137k
    case CVT_imm_95_12:
3364
4
      Inst.addOperand(MCOperand::createImm(12));
3365
4
      break;
3366
137k
    case CVT_imm_95_15:
3367
549
      Inst.addOperand(MCOperand::createImm(15));
3368
549
      break;
3369
137k
    case CVT_95_addMemBarrierOptOperands:
3370
256
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemBarrierOptOperands(Inst, 1);
3371
256
      break;
3372
137k
    case CVT_imm_95_16:
3373
3
      Inst.addOperand(MCOperand::createImm(16));
3374
3
      break;
3375
137k
    case CVT_95_addFPImmOperands:
3376
37
      static_cast<ARMOperand&>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
3377
37
      break;
3378
137k
    case CVT_95_addDPRRegListOperands:
3379
79
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDPRRegListOperands(Inst, 1);
3380
79
      break;
3381
137k
    case CVT_imm_95_1:
3382
34
      Inst.addOperand(MCOperand::createImm(1));
3383
34
      break;
3384
137k
    case CVT_95_addInstSyncBarrierOptOperands:
3385
18
      static_cast<ARMOperand&>(*Operands[OpIdx]).addInstSyncBarrierOptOperands(Inst, 1);
3386
18
      break;
3387
137k
    case CVT_95_addITCondCodeOperands:
3388
7.43k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addITCondCodeOperands(Inst, 1);
3389
7.43k
      break;
3390
137k
    case CVT_95_addITMaskOperands:
3391
7.43k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addITMaskOperands(Inst, 1);
3392
7.43k
      break;
3393
137k
    case CVT_95_addMemNoOffsetOperands:
3394
1.26k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNoOffsetOperands(Inst, 1);
3395
1.26k
      break;
3396
137k
    case CVT_95_addAddrMode5Operands:
3397
745
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5Operands(Inst, 2);
3398
745
      break;
3399
137k
    case CVT_95_addCoprocOptionOperands:
3400
142
      static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocOptionOperands(Inst, 1);
3401
142
      break;
3402
137k
    case CVT_95_addPostIdxImm8s4Operands:
3403
352
      static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8s4Operands(Inst, 1);
3404
352
      break;
3405
137k
    case CVT_95_addRegListOperands:
3406
1.34k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
3407
1.34k
      break;
3408
137k
    case CVT_95_addThumbMemPCOperands:
3409
50
      static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbMemPCOperands(Inst, 1);
3410
50
      break;
3411
137k
    case CVT_95_addConstPoolAsmImmOperands:
3412
549
      static_cast<ARMOperand&>(*Operands[OpIdx]).addConstPoolAsmImmOperands(Inst, 1);
3413
549
      break;
3414
137k
    case CVT_95_addMemThumbRIs4Operands:
3415
84
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs4Operands(Inst, 2);
3416
84
      break;
3417
137k
    case CVT_95_addMemThumbRROperands:
3418
39
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRROperands(Inst, 2);
3419
39
      break;
3420
137k
    case CVT_95_addMemThumbSPIOperands:
3421
47
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbSPIOperands(Inst, 2);
3422
47
      break;
3423
137k
    case CVT_95_addMemImm12OffsetOperands:
3424
230
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm12OffsetOperands(Inst, 2);
3425
230
      break;
3426
137k
    case CVT_95_addMemNegImm8OffsetOperands:
3427
102
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNegImm8OffsetOperands(Inst, 2);
3428
102
      break;
3429
137k
    case CVT_95_addMemRegOffsetOperands:
3430
90
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemRegOffsetOperands(Inst, 3);
3431
90
      break;
3432
137k
    case CVT_95_addMemUImm12OffsetOperands:
3433
340
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemUImm12OffsetOperands(Inst, 2);
3434
340
      break;
3435
137k
    case CVT_95_addT2MemRegOffsetOperands:
3436
321
      static_cast<ARMOperand&>(*Operands[OpIdx]).addT2MemRegOffsetOperands(Inst, 3);
3437
321
      break;
3438
137k
    case CVT_95_addMemPCRelImm12Operands:
3439
53
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemPCRelImm12Operands(Inst, 1);
3440
53
      break;
3441
137k
    case CVT_95_addMemImm8OffsetOperands:
3442
103
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm8OffsetOperands(Inst, 2);
3443
103
      break;
3444
137k
    case CVT_95_addAM2OffsetImmOperands:
3445
43
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAM2OffsetImmOperands(Inst, 2);
3446
43
      break;
3447
137k
    case CVT_95_addPostIdxRegShiftedOperands:
3448
36
      static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegShiftedOperands(Inst, 2);
3449
36
      break;
3450
137k
    case CVT_95_addMemThumbRIs1Operands:
3451
23
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs1Operands(Inst, 2);
3452
23
      break;
3453
137k
    case CVT_95_addMemPosImm8OffsetOperands:
3454
42
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemPosImm8OffsetOperands(Inst, 2);
3455
42
      break;
3456
137k
    case CVT_95_addMemImm8s4OffsetOperands:
3457
145
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm8s4OffsetOperands(Inst, 2);
3458
145
      break;
3459
137k
    case CVT_95_addAddrMode3Operands:
3460
147
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode3Operands(Inst, 3);
3461
147
      break;
3462
137k
    case CVT_95_addAM3OffsetOperands:
3463
78
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAM3OffsetOperands(Inst, 2);
3464
78
      break;
3465
137k
    case CVT_95_addMemImm0_95_1020s4OffsetOperands:
3466
364
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm0_1020s4OffsetOperands(Inst, 2);
3467
364
      break;
3468
137k
    case CVT_95_addMemThumbRIs2Operands:
3469
30
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs2Operands(Inst, 2);
3470
30
      break;
3471
137k
    case CVT_95_addPostIdxRegOperands:
3472
12
      static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegOperands(Inst, 2);
3473
12
      break;
3474
137k
    case CVT_95_addPostIdxImm8Operands:
3475
16
      static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8Operands(Inst, 1);
3476
16
      break;
3477
137k
    case CVT_reg0:
3478
331
      Inst.addOperand(MCOperand::createReg(0));
3479
331
      break;
3480
137k
    case CVT_regCPSR:
3481
242
      Inst.addOperand(MCOperand::createReg(ARM::CPSR));
3482
242
      break;
3483
137k
    case CVT_imm_95_14:
3484
127
      Inst.addOperand(MCOperand::createImm(14));
3485
127
      break;
3486
137k
    case CVT_95_addBankedRegOperands:
3487
198
      static_cast<ARMOperand&>(*Operands[OpIdx]).addBankedRegOperands(Inst, 1);
3488
198
      break;
3489
137k
    case CVT_95_addMSRMaskOperands:
3490
342
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMSRMaskOperands(Inst, 1);
3491
342
      break;
3492
137k
    case CVT_cvtThumbMultiply:
3493
30
      cvtThumbMultiply(Inst, Operands);
3494
30
      break;
3495
137k
    case CVT_regR8:
3496
68
      Inst.addOperand(MCOperand::createReg(ARM::R8));
3497
68
      break;
3498
137k
    case CVT_regR0:
3499
4
      Inst.addOperand(MCOperand::createReg(ARM::R0));
3500
4
      break;
3501
137k
    case CVT_95_addPKHASRImmOperands:
3502
12
      static_cast<ARMOperand&>(*Operands[OpIdx]).addPKHASRImmOperands(Inst, 1);
3503
12
      break;
3504
137k
    case CVT_imm_95_4:
3505
35
      Inst.addOperand(MCOperand::createImm(4));
3506
35
      break;
3507
137k
    case CVT_95_addImm1_95_32Operands:
3508
156
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_32Operands(Inst, 1);
3509
156
      break;
3510
137k
    case CVT_imm_95_5:
3511
13
      Inst.addOperand(MCOperand::createImm(5));
3512
13
      break;
3513
137k
    case CVT_95_addShifterImmOperands:
3514
44
      static_cast<ARMOperand&>(*Operands[OpIdx]).addShifterImmOperands(Inst, 1);
3515
44
      break;
3516
137k
    case CVT_95_addImm1_95_16Operands:
3517
18
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_16Operands(Inst, 1);
3518
18
      break;
3519
137k
    case CVT_95_addRotImmOperands:
3520
330
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRotImmOperands(Inst, 1);
3521
330
      break;
3522
137k
    case CVT_95_addMemTBBOperands:
3523
7
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBBOperands(Inst, 2);
3524
7
      break;
3525
137k
    case CVT_95_addMemTBHOperands:
3526
7
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBHOperands(Inst, 2);
3527
7
      break;
3528
137k
    case CVT_95_addTraceSyncBarrierOptOperands:
3529
2
      static_cast<ARMOperand&>(*Operands[OpIdx]).addTraceSyncBarrierOptOperands(Inst, 1);
3530
2
      break;
3531
137k
    case CVT_95_addNEONi16splatNotOperands:
3532
4
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatNotOperands(Inst, 1);
3533
4
      break;
3534
137k
    case CVT_95_addNEONi32splatNotOperands:
3535
8
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatNotOperands(Inst, 1);
3536
8
      break;
3537
137k
    case CVT_95_addNEONi16splatOperands:
3538
16
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatOperands(Inst, 1);
3539
16
      break;
3540
137k
    case CVT_95_addNEONi32splatOperands:
3541
11
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatOperands(Inst, 1);
3542
11
      break;
3543
137k
    case CVT_95_addComplexRotationOddOperands:
3544
40
      static_cast<ARMOperand&>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1);
3545
40
      break;
3546
137k
    case CVT_95_addComplexRotationEvenOperands:
3547
120
      static_cast<ARMOperand&>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1);
3548
120
      break;
3549
137k
    case CVT_95_addVectorIndex64Operands:
3550
40
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex64Operands(Inst, 1);
3551
40
      break;
3552
137k
    case CVT_95_addVectorIndex32Operands:
3553
175
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex32Operands(Inst, 1);
3554
175
      break;
3555
137k
    case CVT_95_addFBits16Operands:
3556
28
      static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits16Operands(Inst, 1);
3557
28
      break;
3558
137k
    case CVT_95_addFBits32Operands:
3559
28
      static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits32Operands(Inst, 1);
3560
28
      break;
3561
137k
    case CVT_95_addVectorIndex16Operands:
3562
134
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex16Operands(Inst, 1);
3563
134
      break;
3564
137k
    case CVT_95_addVectorIndex8Operands:
3565
22
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex8Operands(Inst, 1);
3566
22
      break;
3567
137k
    case CVT_95_addVecListOperands:
3568
1.07k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListOperands(Inst, 1);
3569
1.07k
      break;
3570
137k
    case CVT_95_addDupAlignedMemory16Operands:
3571
24
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory16Operands(Inst, 2);
3572
24
      break;
3573
137k
    case CVT_95_addAlignedMemory64or128Operands:
3574
290
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128Operands(Inst, 2);
3575
290
      break;
3576
137k
    case CVT_95_addAlignedMemory64or128or256Operands:
3577
393
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128or256Operands(Inst, 2);
3578
393
      break;
3579
137k
    case CVT_95_addAlignedMemory64Operands:
3580
346
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64Operands(Inst, 2);
3581
346
      break;
3582
137k
    case CVT_95_addVecListIndexedOperands:
3583
327
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListIndexedOperands(Inst, 2);
3584
327
      break;
3585
137k
    case CVT_95_addAlignedMemory16Operands:
3586
38
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory16Operands(Inst, 2);
3587
38
      break;
3588
137k
    case CVT_95_addDupAlignedMemory32Operands:
3589
42
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory32Operands(Inst, 2);
3590
42
      break;
3591
137k
    case CVT_95_addAlignedMemory32Operands:
3592
66
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory32Operands(Inst, 2);
3593
66
      break;
3594
137k
    case CVT_95_addDupAlignedMemoryNoneOperands:
3595
48
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemoryNoneOperands(Inst, 2);
3596
48
      break;
3597
137k
    case CVT_95_addAlignedMemoryNoneOperands:
3598
80
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryNoneOperands(Inst, 2);
3599
80
      break;
3600
137k
    case CVT_95_addAlignedMemoryOperands:
3601
0
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryOperands(Inst, 2);
3602
0
      break;
3603
137k
    case CVT_95_addDupAlignedMemory64Operands:
3604
36
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64Operands(Inst, 2);
3605
36
      break;
3606
137k
    case CVT_95_addDupAlignedMemory64or128Operands:
3607
24
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64or128Operands(Inst, 2);
3608
24
      break;
3609
137k
    case CVT_95_addSPRRegListOperands:
3610
12
      static_cast<ARMOperand&>(*Operands[OpIdx]).addSPRRegListOperands(Inst, 1);
3611
12
      break;
3612
137k
    case CVT_95_addAddrMode5FP16Operands:
3613
32
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5FP16Operands(Inst, 2);
3614
32
      break;
3615
137k
    case CVT_95_addNEONi32vmovOperands:
3616
38
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovOperands(Inst, 1);
3617
38
      break;
3618
137k
    case CVT_95_addNEONvmovi8ReplicateOperands:
3619
8
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi8ReplicateOperands(Inst, 1);
3620
8
      break;
3621
137k
    case CVT_95_addNEONvmovi16ReplicateOperands:
3622
16
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi16ReplicateOperands(Inst, 1);
3623
16
      break;
3624
137k
    case CVT_95_addNEONi32vmovNegOperands:
3625
0
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovNegOperands(Inst, 1);
3626
0
      break;
3627
137k
    case CVT_95_addNEONvmovi32ReplicateOperands:
3628
8
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi32ReplicateOperands(Inst, 1);
3629
8
      break;
3630
137k
    case CVT_95_addNEONi64splatOperands:
3631
8
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi64splatOperands(Inst, 1);
3632
8
      break;
3633
137k
    case CVT_95_addNEONi8splatOperands:
3634
4
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi8splatOperands(Inst, 1);
3635
4
      break;
3636
137k
    case CVT_95_addNEONinvi8ReplicateOperands:
3637
10
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONinvi8ReplicateOperands(Inst, 1);
3638
10
      break;
3639
137k
    case CVT_imm_95_2:
3640
34
      Inst.addOperand(MCOperand::createImm(2));
3641
34
      break;
3642
137k
    case CVT_imm_95_3:
3643
34
      Inst.addOperand(MCOperand::createImm(3));
3644
34
      break;
3645
137k
    }
3646
137k
  }
3647
43.1k
}
3648
3649
void ARMAsmParser::
3650
convertToMapAndConstraints(unsigned Kind,
3651
0
                           const OperandVector &Operands) {
3652
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
3653
0
  unsigned NumMCOperands = 0;
3654
0
  const uint8_t *Converter = ConversionTable[Kind];
3655
0
  for (const uint8_t *p = Converter; *p; p+= 2) {
3656
0
    switch (*p) {
3657
0
    default: llvm_unreachable("invalid conversion entry!");
3658
0
    case CVT_Reg:
3659
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3660
0
      Operands[*(p + 1)]->setConstraint("r");
3661
0
      ++NumMCOperands;
3662
0
      break;
3663
0
    case CVT_Tied:
3664
0
      ++NumMCOperands;
3665
0
      break;
3666
0
    case CVT_95_Reg:
3667
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3668
0
      Operands[*(p + 1)]->setConstraint("r");
3669
0
      NumMCOperands += 1;
3670
0
      break;
3671
0
    case CVT_95_addCCOutOperands:
3672
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3673
0
      Operands[*(p + 1)]->setConstraint("m");
3674
0
      NumMCOperands += 1;
3675
0
      break;
3676
0
    case CVT_95_addCondCodeOperands:
3677
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3678
0
      Operands[*(p + 1)]->setConstraint("m");
3679
0
      NumMCOperands += 2;
3680
0
      break;
3681
0
    case CVT_95_addRegShiftedRegOperands:
3682
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3683
0
      Operands[*(p + 1)]->setConstraint("m");
3684
0
      NumMCOperands += 3;
3685
0
      break;
3686
0
    case CVT_95_addModImmOperands:
3687
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3688
0
      Operands[*(p + 1)]->setConstraint("m");
3689
0
      NumMCOperands += 1;
3690
0
      break;
3691
0
    case CVT_95_addModImmNotOperands:
3692
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3693
0
      Operands[*(p + 1)]->setConstraint("m");
3694
0
      NumMCOperands += 1;
3695
0
      break;
3696
0
    case CVT_95_addRegShiftedImmOperands:
3697
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3698
0
      Operands[*(p + 1)]->setConstraint("m");
3699
0
      NumMCOperands += 2;
3700
0
      break;
3701
0
    case CVT_95_addImmOperands:
3702
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3703
0
      Operands[*(p + 1)]->setConstraint("m");
3704
0
      NumMCOperands += 1;
3705
0
      break;
3706
0
    case CVT_95_addT2SOImmNotOperands:
3707
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3708
0
      Operands[*(p + 1)]->setConstraint("m");
3709
0
      NumMCOperands += 1;
3710
0
      break;
3711
0
    case CVT_95_addImm0_95_508s4Operands:
3712
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3713
0
      Operands[*(p + 1)]->setConstraint("m");
3714
0
      NumMCOperands += 1;
3715
0
      break;
3716
0
    case CVT_regSP:
3717
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3718
0
      Operands[*(p + 1)]->setConstraint("m");
3719
0
      ++NumMCOperands;
3720
0
      break;
3721
0
    case CVT_95_addImm0_95_508s4NegOperands:
3722
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3723
0
      Operands[*(p + 1)]->setConstraint("m");
3724
0
      NumMCOperands += 1;
3725
0
      break;
3726
0
    case CVT_95_addImm0_95_4095NegOperands:
3727
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3728
0
      Operands[*(p + 1)]->setConstraint("m");
3729
0
      NumMCOperands += 1;
3730
0
      break;
3731
0
    case CVT_95_addThumbModImmNeg8_95_255Operands:
3732
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3733
0
      Operands[*(p + 1)]->setConstraint("m");
3734
0
      NumMCOperands += 1;
3735
0
      break;
3736
0
    case CVT_95_addT2SOImmNegOperands:
3737
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3738
0
      Operands[*(p + 1)]->setConstraint("m");
3739
0
      NumMCOperands += 1;
3740
0
      break;
3741
0
    case CVT_95_addModImmNegOperands:
3742
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3743
0
      Operands[*(p + 1)]->setConstraint("m");
3744
0
      NumMCOperands += 1;
3745
0
      break;
3746
0
    case CVT_95_addImm0_95_1020s4Operands:
3747
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3748
0
      Operands[*(p + 1)]->setConstraint("m");
3749
0
      NumMCOperands += 1;
3750
0
      break;
3751
0
    case CVT_95_addThumbModImmNeg1_95_7Operands:
3752
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3753
0
      Operands[*(p + 1)]->setConstraint("m");
3754
0
      NumMCOperands += 1;
3755
0
      break;
3756
0
    case CVT_95_addUnsignedOffset_95_b8s2Operands:
3757
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3758
0
      Operands[*(p + 1)]->setConstraint("m");
3759
0
      NumMCOperands += 1;
3760
0
      break;
3761
0
    case CVT_95_addAdrLabelOperands:
3762
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3763
0
      Operands[*(p + 1)]->setConstraint("m");
3764
0
      NumMCOperands += 1;
3765
0
      break;
3766
0
    case CVT_95_addARMBranchTargetOperands:
3767
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3768
0
      Operands[*(p + 1)]->setConstraint("m");
3769
0
      NumMCOperands += 1;
3770
0
      break;
3771
0
    case CVT_95_addBitfieldOperands:
3772
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3773
0
      Operands[*(p + 1)]->setConstraint("m");
3774
0
      NumMCOperands += 1;
3775
0
      break;
3776
0
    case CVT_imm_95_0:
3777
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3778
0
      Operands[*(p + 1)]->setConstraint("");
3779
0
      ++NumMCOperands;
3780
0
      break;
3781
0
    case CVT_95_addThumbBranchTargetOperands:
3782
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3783
0
      Operands[*(p + 1)]->setConstraint("m");
3784
0
      NumMCOperands += 1;
3785
0
      break;
3786
0
    case CVT_95_addCoprocNumOperands:
3787
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3788
0
      Operands[*(p + 1)]->setConstraint("m");
3789
0
      NumMCOperands += 1;
3790
0
      break;
3791
0
    case CVT_95_addCoprocRegOperands:
3792
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3793
0
      Operands[*(p + 1)]->setConstraint("m");
3794
0
      NumMCOperands += 1;
3795
0
      break;
3796
0
    case CVT_95_addProcIFlagsOperands:
3797
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3798
0
      Operands[*(p + 1)]->setConstraint("m");
3799
0
      NumMCOperands += 1;
3800
0
      break;
3801
0
    case CVT_imm_95_20:
3802
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3803
0
      Operands[*(p + 1)]->setConstraint("");
3804
0
      ++NumMCOperands;
3805
0
      break;
3806
0
    case CVT_imm_95_12:
3807
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3808
0
      Operands[*(p + 1)]->setConstraint("");
3809
0
      ++NumMCOperands;
3810
0
      break;
3811
0
    case CVT_imm_95_15:
3812
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3813
0
      Operands[*(p + 1)]->setConstraint("");
3814
0
      ++NumMCOperands;
3815
0
      break;
3816
0
    case CVT_95_addMemBarrierOptOperands:
3817
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3818
0
      Operands[*(p + 1)]->setConstraint("m");
3819
0
      NumMCOperands += 1;
3820
0
      break;
3821
0
    case CVT_imm_95_16:
3822
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3823
0
      Operands[*(p + 1)]->setConstraint("");
3824
0
      ++NumMCOperands;
3825
0
      break;
3826
0
    case CVT_95_addFPImmOperands:
3827
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3828
0
      Operands[*(p + 1)]->setConstraint("m");
3829
0
      NumMCOperands += 1;
3830
0
      break;
3831
0
    case CVT_95_addDPRRegListOperands:
3832
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3833
0
      Operands[*(p + 1)]->setConstraint("m");
3834
0
      NumMCOperands += 1;
3835
0
      break;
3836
0
    case CVT_imm_95_1:
3837
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3838
0
      Operands[*(p + 1)]->setConstraint("");
3839
0
      ++NumMCOperands;
3840
0
      break;
3841
0
    case CVT_95_addInstSyncBarrierOptOperands:
3842
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3843
0
      Operands[*(p + 1)]->setConstraint("m");
3844
0
      NumMCOperands += 1;
3845
0
      break;
3846
0
    case CVT_95_addITCondCodeOperands:
3847
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3848
0
      Operands[*(p + 1)]->setConstraint("m");
3849
0
      NumMCOperands += 1;
3850
0
      break;
3851
0
    case CVT_95_addITMaskOperands:
3852
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3853
0
      Operands[*(p + 1)]->setConstraint("m");
3854
0
      NumMCOperands += 1;
3855
0
      break;
3856
0
    case CVT_95_addMemNoOffsetOperands:
3857
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3858
0
      Operands[*(p + 1)]->setConstraint("m");
3859
0
      NumMCOperands += 1;
3860
0
      break;
3861
0
    case CVT_95_addAddrMode5Operands:
3862
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3863
0
      Operands[*(p + 1)]->setConstraint("m");
3864
0
      NumMCOperands += 2;
3865
0
      break;
3866
0
    case CVT_95_addCoprocOptionOperands:
3867
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3868
0
      Operands[*(p + 1)]->setConstraint("m");
3869
0
      NumMCOperands += 1;
3870
0
      break;
3871
0
    case CVT_95_addPostIdxImm8s4Operands:
3872
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3873
0
      Operands[*(p + 1)]->setConstraint("m");
3874
0
      NumMCOperands += 1;
3875
0
      break;
3876
0
    case CVT_95_addRegListOperands:
3877
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3878
0
      Operands[*(p + 1)]->setConstraint("m");
3879
0
      NumMCOperands += 1;
3880
0
      break;
3881
0
    case CVT_95_addThumbMemPCOperands:
3882
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3883
0
      Operands[*(p + 1)]->setConstraint("m");
3884
0
      NumMCOperands += 1;
3885
0
      break;
3886
0
    case CVT_95_addConstPoolAsmImmOperands:
3887
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3888
0
      Operands[*(p + 1)]->setConstraint("m");
3889
0
      NumMCOperands += 1;
3890
0
      break;
3891
0
    case CVT_95_addMemThumbRIs4Operands:
3892
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3893
0
      Operands[*(p + 1)]->setConstraint("m");
3894
0
      NumMCOperands += 2;
3895
0
      break;
3896
0
    case CVT_95_addMemThumbRROperands:
3897
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3898
0
      Operands[*(p + 1)]->setConstraint("m");
3899
0
      NumMCOperands += 2;
3900
0
      break;
3901
0
    case CVT_95_addMemThumbSPIOperands:
3902
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3903
0
      Operands[*(p + 1)]->setConstraint("m");
3904
0
      NumMCOperands += 2;
3905
0
      break;
3906
0
    case CVT_95_addMemImm12OffsetOperands:
3907
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3908
0
      Operands[*(p + 1)]->setConstraint("m");
3909
0
      NumMCOperands += 2;
3910
0
      break;
3911
0
    case CVT_95_addMemNegImm8OffsetOperands:
3912
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3913
0
      Operands[*(p + 1)]->setConstraint("m");
3914
0
      NumMCOperands += 2;
3915
0
      break;
3916
0
    case CVT_95_addMemRegOffsetOperands:
3917
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3918
0
      Operands[*(p + 1)]->setConstraint("m");
3919
0
      NumMCOperands += 3;
3920
0
      break;
3921
0
    case CVT_95_addMemUImm12OffsetOperands:
3922
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3923
0
      Operands[*(p + 1)]->setConstraint("m");
3924
0
      NumMCOperands += 2;
3925
0
      break;
3926
0
    case CVT_95_addT2MemRegOffsetOperands:
3927
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3928
0
      Operands[*(p + 1)]->setConstraint("m");
3929
0
      NumMCOperands += 3;
3930
0
      break;
3931
0
    case CVT_95_addMemPCRelImm12Operands:
3932
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3933
0
      Operands[*(p + 1)]->setConstraint("m");
3934
0
      NumMCOperands += 1;
3935
0
      break;
3936
0
    case CVT_95_addMemImm8OffsetOperands:
3937
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3938
0
      Operands[*(p + 1)]->setConstraint("m");
3939
0
      NumMCOperands += 2;
3940
0
      break;
3941
0
    case CVT_95_addAM2OffsetImmOperands:
3942
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3943
0
      Operands[*(p + 1)]->setConstraint("m");
3944
0
      NumMCOperands += 2;
3945
0
      break;
3946
0
    case CVT_95_addPostIdxRegShiftedOperands:
3947
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3948
0
      Operands[*(p + 1)]->setConstraint("m");
3949
0
      NumMCOperands += 2;
3950
0
      break;
3951
0
    case CVT_95_addMemThumbRIs1Operands:
3952
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3953
0
      Operands[*(p + 1)]->setConstraint("m");
3954
0
      NumMCOperands += 2;
3955
0
      break;
3956
0
    case CVT_95_addMemPosImm8OffsetOperands:
3957
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3958
0
      Operands[*(p + 1)]->setConstraint("m");
3959
0
      NumMCOperands += 2;
3960
0
      break;
3961
0
    case CVT_95_addMemImm8s4OffsetOperands:
3962
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3963
0
      Operands[*(p + 1)]->setConstraint("m");
3964
0
      NumMCOperands += 2;
3965
0
      break;
3966
0
    case CVT_95_addAddrMode3Operands:
3967
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3968
0
      Operands[*(p + 1)]->setConstraint("m");
3969
0
      NumMCOperands += 3;
3970
0
      break;
3971
0
    case CVT_95_addAM3OffsetOperands:
3972
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3973
0
      Operands[*(p + 1)]->setConstraint("m");
3974
0
      NumMCOperands += 2;
3975
0
      break;
3976
0
    case CVT_95_addMemImm0_95_1020s4OffsetOperands:
3977
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3978
0
      Operands[*(p + 1)]->setConstraint("m");
3979
0
      NumMCOperands += 2;
3980
0
      break;
3981
0
    case CVT_95_addMemThumbRIs2Operands:
3982
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3983
0
      Operands[*(p + 1)]->setConstraint("m");
3984
0
      NumMCOperands += 2;
3985
0
      break;
3986
0
    case CVT_95_addPostIdxRegOperands:
3987
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3988
0
      Operands[*(p + 1)]->setConstraint("m");
3989
0
      NumMCOperands += 2;
3990
0
      break;
3991
0
    case CVT_95_addPostIdxImm8Operands:
3992
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3993
0
      Operands[*(p + 1)]->setConstraint("m");
3994
0
      NumMCOperands += 1;
3995
0
      break;
3996
0
    case CVT_reg0:
3997
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3998
0
      Operands[*(p + 1)]->setConstraint("m");
3999
0
      ++NumMCOperands;
4000
0
      break;
4001
0
    case CVT_regCPSR:
4002
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4003
0
      Operands[*(p + 1)]->setConstraint("m");
4004
0
      ++NumMCOperands;
4005
0
      break;
4006
0
    case CVT_imm_95_14:
4007
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4008
0
      Operands[*(p + 1)]->setConstraint("");
4009
0
      ++NumMCOperands;
4010
0
      break;
4011
0
    case CVT_95_addBankedRegOperands:
4012
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4013
0
      Operands[*(p + 1)]->setConstraint("m");
4014
0
      NumMCOperands += 1;
4015
0
      break;
4016
0
    case CVT_95_addMSRMaskOperands:
4017
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4018
0
      Operands[*(p + 1)]->setConstraint("m");
4019
0
      NumMCOperands += 1;
4020
0
      break;
4021
0
    case CVT_regR8:
4022
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4023
0
      Operands[*(p + 1)]->setConstraint("m");
4024
0
      ++NumMCOperands;
4025
0
      break;
4026
0
    case CVT_regR0:
4027
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4028
0
      Operands[*(p + 1)]->setConstraint("m");
4029
0
      ++NumMCOperands;
4030
0
      break;
4031
0
    case CVT_95_addPKHASRImmOperands:
4032
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4033
0
      Operands[*(p + 1)]->setConstraint("m");
4034
0
      NumMCOperands += 1;
4035
0
      break;
4036
0
    case CVT_imm_95_4:
4037
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4038
0
      Operands[*(p + 1)]->setConstraint("");
4039
0
      ++NumMCOperands;
4040
0
      break;
4041
0
    case CVT_95_addImm1_95_32Operands:
4042
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4043
0
      Operands[*(p + 1)]->setConstraint("m");
4044
0
      NumMCOperands += 1;
4045
0
      break;
4046
0
    case CVT_imm_95_5:
4047
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4048
0
      Operands[*(p + 1)]->setConstraint("");
4049
0
      ++NumMCOperands;
4050
0
      break;
4051
0
    case CVT_95_addShifterImmOperands:
4052
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4053
0
      Operands[*(p + 1)]->setConstraint("m");
4054
0
      NumMCOperands += 1;
4055
0
      break;
4056
0
    case CVT_95_addImm1_95_16Operands:
4057
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4058
0
      Operands[*(p + 1)]->setConstraint("m");
4059
0
      NumMCOperands += 1;
4060
0
      break;
4061
0
    case CVT_95_addRotImmOperands:
4062
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4063
0
      Operands[*(p + 1)]->setConstraint("m");
4064
0
      NumMCOperands += 1;
4065
0
      break;
4066
0
    case CVT_95_addMemTBBOperands:
4067
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4068
0
      Operands[*(p + 1)]->setConstraint("m");
4069
0
      NumMCOperands += 2;
4070
0
      break;
4071
0
    case CVT_95_addMemTBHOperands:
4072
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4073
0
      Operands[*(p + 1)]->setConstraint("m");
4074
0
      NumMCOperands += 2;
4075
0
      break;
4076
0
    case CVT_95_addTraceSyncBarrierOptOperands:
4077
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4078
0
      Operands[*(p + 1)]->setConstraint("m");
4079
0
      NumMCOperands += 1;
4080
0
      break;
4081
0
    case CVT_95_addNEONi16splatNotOperands:
4082
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4083
0
      Operands[*(p + 1)]->setConstraint("m");
4084
0
      NumMCOperands += 1;
4085
0
      break;
4086
0
    case CVT_95_addNEONi32splatNotOperands:
4087
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4088
0
      Operands[*(p + 1)]->setConstraint("m");
4089
0
      NumMCOperands += 1;
4090
0
      break;
4091
0
    case CVT_95_addNEONi16splatOperands:
4092
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4093
0
      Operands[*(p + 1)]->setConstraint("m");
4094
0
      NumMCOperands += 1;
4095
0
      break;
4096
0
    case CVT_95_addNEONi32splatOperands:
4097
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4098
0
      Operands[*(p + 1)]->setConstraint("m");
4099
0
      NumMCOperands += 1;
4100
0
      break;
4101
0
    case CVT_95_addComplexRotationOddOperands:
4102
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4103
0
      Operands[*(p + 1)]->setConstraint("m");
4104
0
      NumMCOperands += 1;
4105
0
      break;
4106
0
    case CVT_95_addComplexRotationEvenOperands:
4107
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4108
0
      Operands[*(p + 1)]->setConstraint("m");
4109
0
      NumMCOperands += 1;
4110
0
      break;
4111
0
    case CVT_95_addVectorIndex64Operands:
4112
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4113
0
      Operands[*(p + 1)]->setConstraint("m");
4114
0
      NumMCOperands += 1;
4115
0
      break;
4116
0
    case CVT_95_addVectorIndex32Operands:
4117
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4118
0
      Operands[*(p + 1)]->setConstraint("m");
4119
0
      NumMCOperands += 1;
4120
0
      break;
4121
0
    case CVT_95_addFBits16Operands:
4122
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4123
0
      Operands[*(p + 1)]->setConstraint("m");
4124
0
      NumMCOperands += 1;
4125
0
      break;
4126
0
    case CVT_95_addFBits32Operands:
4127
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4128
0
      Operands[*(p + 1)]->setConstraint("m");
4129
0
      NumMCOperands += 1;
4130
0
      break;
4131
0
    case CVT_95_addVectorIndex16Operands:
4132
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4133
0
      Operands[*(p + 1)]->setConstraint("m");
4134
0
      NumMCOperands += 1;
4135
0
      break;
4136
0
    case CVT_95_addVectorIndex8Operands:
4137
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4138
0
      Operands[*(p + 1)]->setConstraint("m");
4139
0
      NumMCOperands += 1;
4140
0
      break;
4141
0
    case CVT_95_addVecListOperands:
4142
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4143
0
      Operands[*(p + 1)]->setConstraint("m");
4144
0
      NumMCOperands += 1;
4145
0
      break;
4146
0
    case CVT_95_addDupAlignedMemory16Operands:
4147
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4148
0
      Operands[*(p + 1)]->setConstraint("m");
4149
0
      NumMCOperands += 2;
4150
0
      break;
4151
0
    case CVT_95_addAlignedMemory64or128Operands:
4152
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4153
0
      Operands[*(p + 1)]->setConstraint("m");
4154
0
      NumMCOperands += 2;
4155
0
      break;
4156
0
    case CVT_95_addAlignedMemory64or128or256Operands:
4157
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4158
0
      Operands[*(p + 1)]->setConstraint("m");
4159
0
      NumMCOperands += 2;
4160
0
      break;
4161
0
    case CVT_95_addAlignedMemory64Operands:
4162
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4163
0
      Operands[*(p + 1)]->setConstraint("m");
4164
0
      NumMCOperands += 2;
4165
0
      break;
4166
0
    case CVT_95_addVecListIndexedOperands:
4167
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4168
0
      Operands[*(p + 1)]->setConstraint("m");
4169
0
      NumMCOperands += 2;
4170
0
      break;
4171
0
    case CVT_95_addAlignedMemory16Operands:
4172
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4173
0
      Operands[*(p + 1)]->setConstraint("m");
4174
0
      NumMCOperands += 2;
4175
0
      break;
4176
0
    case CVT_95_addDupAlignedMemory32Operands:
4177
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4178
0
      Operands[*(p + 1)]->setConstraint("m");
4179
0
      NumMCOperands += 2;
4180
0
      break;
4181
0
    case CVT_95_addAlignedMemory32Operands:
4182
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4183
0
      Operands[*(p + 1)]->setConstraint("m");
4184
0
      NumMCOperands += 2;
4185
0
      break;
4186
0
    case CVT_95_addDupAlignedMemoryNoneOperands:
4187
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4188
0
      Operands[*(p + 1)]->setConstraint("m");
4189
0
      NumMCOperands += 2;
4190
0
      break;
4191
0
    case CVT_95_addAlignedMemoryNoneOperands:
4192
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4193
0
      Operands[*(p + 1)]->setConstraint("m");
4194
0
      NumMCOperands += 2;
4195
0
      break;
4196
0
    case CVT_95_addAlignedMemoryOperands:
4197
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4198
0
      Operands[*(p + 1)]->setConstraint("m");
4199
0
      NumMCOperands += 2;
4200
0
      break;
4201
0
    case CVT_95_addDupAlignedMemory64Operands:
4202
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4203
0
      Operands[*(p + 1)]->setConstraint("m");
4204
0
      NumMCOperands += 2;
4205
0
      break;
4206
0
    case CVT_95_addDupAlignedMemory64or128Operands:
4207
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4208
0
      Operands[*(p + 1)]->setConstraint("m");
4209
0
      NumMCOperands += 2;
4210
0
      break;
4211
0
    case CVT_95_addSPRRegListOperands:
4212
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4213
0
      Operands[*(p + 1)]->setConstraint("m");
4214
0
      NumMCOperands += 1;
4215
0
      break;
4216
0
    case CVT_95_addAddrMode5FP16Operands:
4217
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4218
0
      Operands[*(p + 1)]->setConstraint("m");
4219
0
      NumMCOperands += 2;
4220
0
      break;
4221
0
    case CVT_95_addNEONi32vmovOperands:
4222
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4223
0
      Operands[*(p + 1)]->setConstraint("m");
4224
0
      NumMCOperands += 1;
4225
0
      break;
4226
0
    case CVT_95_addNEONvmovi8ReplicateOperands:
4227
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4228
0
      Operands[*(p + 1)]->setConstraint("m");
4229
0
      NumMCOperands += 1;
4230
0
      break;
4231
0
    case CVT_95_addNEONvmovi16ReplicateOperands:
4232
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4233
0
      Operands[*(p + 1)]->setConstraint("m");
4234
0
      NumMCOperands += 1;
4235
0
      break;
4236
0
    case CVT_95_addNEONi32vmovNegOperands:
4237
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4238
0
      Operands[*(p + 1)]->setConstraint("m");
4239
0
      NumMCOperands += 1;
4240
0
      break;
4241
0
    case CVT_95_addNEONvmovi32ReplicateOperands:
4242
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4243
0
      Operands[*(p + 1)]->setConstraint("m");
4244
0
      NumMCOperands += 1;
4245
0
      break;
4246
0
    case CVT_95_addNEONi64splatOperands:
4247
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4248
0
      Operands[*(p + 1)]->setConstraint("m");
4249
0
      NumMCOperands += 1;
4250
0
      break;
4251
0
    case CVT_95_addNEONi8splatOperands:
4252
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4253
0
      Operands[*(p + 1)]->setConstraint("m");
4254
0
      NumMCOperands += 1;
4255
0
      break;
4256
0
    case CVT_95_addNEONinvi8ReplicateOperands:
4257
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4258
0
      Operands[*(p + 1)]->setConstraint("m");
4259
0
      NumMCOperands += 1;
4260
0
      break;
4261
0
    case CVT_imm_95_2:
4262
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4263
0
      Operands[*(p + 1)]->setConstraint("");
4264
0
      ++NumMCOperands;
4265
0
      break;
4266
0
    case CVT_imm_95_3:
4267
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4268
0
      Operands[*(p + 1)]->setConstraint("");
4269
0
      ++NumMCOperands;
4270
0
      break;
4271
0
    }
4272
0
  }
4273
0
}
4274
4275
namespace {
4276
4277
/// MatchClassKind - The kinds of classes which participate in
4278
/// instruction matching.
4279
enum MatchClassKind {
4280
  InvalidMatchClass = 0,
4281
  OptionalMatchClass = 1,
4282
  MCK__DOT_d, // '.d'
4283
  MCK__DOT_f, // '.f'
4284
  MCK__DOT_s16, // '.s16'
4285
  MCK__DOT_s32, // '.s32'
4286
  MCK__DOT_s64, // '.s64'
4287
  MCK__DOT_s8, // '.s8'
4288
  MCK__DOT_u16, // '.u16'
4289
  MCK__DOT_u32, // '.u32'
4290
  MCK__DOT_u64, // '.u64'
4291
  MCK__DOT_u8, // '.u8'
4292
  MCK__DOT_f32, // '.f32'
4293
  MCK__DOT_f64, // '.f64'
4294
  MCK__DOT_i16, // '.i16'
4295
  MCK__DOT_i32, // '.i32'
4296
  MCK__DOT_i64, // '.i64'
4297
  MCK__DOT_i8, // '.i8'
4298
  MCK__DOT_p16, // '.p16'
4299
  MCK__DOT_p8, // '.p8'
4300
  MCK__EXCLAIM_, // '!'
4301
  MCK__35_0, // '#0'
4302
  MCK__DOT_16, // '.16'
4303
  MCK__DOT_32, // '.32'
4304
  MCK__DOT_64, // '.64'
4305
  MCK__DOT_8, // '.8'
4306
  MCK__DOT_f16, // '.f16'
4307
  MCK__DOT_p64, // '.p64'
4308
  MCK__DOT_w, // '.w'
4309
  MCK__91_, // '['
4310
  MCK__93_, // ']'
4311
  MCK__94_, // '^'
4312
  MCK__123_, // '{'
4313
  MCK__125_, // '}'
4314
  MCK_LAST_TOKEN = MCK__125_,
4315
  MCK_Reg75, // derived register class
4316
  MCK_Reg59, // derived register class
4317
  MCK_Reg11, // derived register class
4318
  MCK_APSR, // register class 'APSR'
4319
  MCK_APSR_NZCV, // register class 'APSR_NZCV'
4320
  MCK_CCR, // register class 'CCR,CPSR'
4321
  MCK_FPEXC, // register class 'FPEXC'
4322
  MCK_FPINST, // register class 'FPINST'
4323
  MCK_FPINST2, // register class 'FPINST2'
4324
  MCK_FPSCR, // register class 'FPSCR'
4325
  MCK_FPSID, // register class 'FPSID'
4326
  MCK_GPRsp, // register class 'GPRsp,SP'
4327
  MCK_LR, // register class 'LR'
4328
  MCK_MVFR0, // register class 'MVFR0'
4329
  MCK_MVFR1, // register class 'MVFR1'
4330
  MCK_MVFR2, // register class 'MVFR2'
4331
  MCK_PC, // register class 'PC'
4332
  MCK_SPSR, // register class 'SPSR'
4333
  MCK_Reg100, // derived register class
4334
  MCK_Reg73, // derived register class
4335
  MCK_Reg68, // derived register class
4336
  MCK_Reg60, // derived register class
4337
  MCK_Reg101, // derived register class
4338
  MCK_Reg88, // derived register class
4339
  MCK_Reg83, // derived register class
4340
  MCK_Reg74, // derived register class
4341
  MCK_Reg72, // derived register class
4342
  MCK_Reg61, // derived register class
4343
  MCK_Reg45, // derived register class
4344
  MCK_Reg102, // derived register class
4345
  MCK_Reg93, // derived register class
4346
  MCK_Reg89, // derived register class
4347
  MCK_Reg84, // derived register class
4348
  MCK_Reg69, // derived register class
4349
  MCK_Reg62, // derived register class
4350
  MCK_Reg46, // derived register class
4351
  MCK_Reg0, // derived register class
4352
  MCK_QPR_8, // register class 'QPR_8'
4353
  MCK_Reg63, // derived register class
4354
  MCK_Reg57, // derived register class
4355
  MCK_tcGPR, // register class 'tcGPR'
4356
  MCK_Reg103, // derived register class
4357
  MCK_Reg94, // derived register class
4358
  MCK_Reg76, // derived register class
4359
  MCK_Reg70, // derived register class
4360
  MCK_Reg64, // derived register class
4361
  MCK_Reg58, // derived register class
4362
  MCK_Reg40, // derived register class
4363
  MCK_Reg10, // derived register class
4364
  MCK_Reg104, // derived register class
4365
  MCK_Reg90, // derived register class
4366
  MCK_Reg85, // derived register class
4367
  MCK_Reg77, // derived register class
4368
  MCK_Reg65, // derived register class
4369
  MCK_Reg55, // derived register class
4370
  MCK_Reg47, // derived register class
4371
  MCK_Reg26, // derived register class
4372
  MCK_Reg8, // derived register class
4373
  MCK_GPRPair, // register class 'GPRPair'
4374
  MCK_Reg105, // derived register class
4375
  MCK_Reg95, // derived register class
4376
  MCK_Reg91, // derived register class
4377
  MCK_Reg86, // derived register class
4378
  MCK_Reg78, // derived register class
4379
  MCK_Reg66, // derived register class
4380
  MCK_Reg56, // derived register class
4381
  MCK_Reg48, // derived register class
4382
  MCK_Reg41, // derived register class
4383
  MCK_Reg27, // derived register class
4384
  MCK_DPR_8, // register class 'DPR_8'
4385
  MCK_QPR_VFP2, // register class 'QPR_VFP2'
4386
  MCK_hGPR, // register class 'hGPR'
4387
  MCK_tGPR, // register class 'tGPR'
4388
  MCK_tGPRwithpc, // register class 'tGPRwithpc'
4389
  MCK_Reg96, // derived register class
4390
  MCK_Reg53, // derived register class
4391
  MCK_QQQQPR, // register class 'QQQQPR'
4392
  MCK_Reg106, // derived register class
4393
  MCK_Reg97, // derived register class
4394
  MCK_Reg79, // derived register class
4395
  MCK_Reg54, // derived register class
4396
  MCK_Reg42, // derived register class
4397
  MCK_rGPR, // register class 'rGPR'
4398
  MCK_Reg92, // derived register class
4399
  MCK_Reg87, // derived register class
4400
  MCK_Reg80, // derived register class
4401
  MCK_Reg51, // derived register class
4402
  MCK_Reg24, // derived register class
4403
  MCK_GPRnopc, // register class 'GPRnopc'
4404
  MCK_QQPR, // register class 'QQPR'
4405
  MCK_Reg98, // derived register class
4406
  MCK_Reg81, // derived register class
4407
  MCK_Reg52, // derived register class
4408
  MCK_Reg43, // derived register class
4409
  MCK_Reg25, // derived register class
4410
  MCK_DPR_VFP2, // register class 'DPR_VFP2'
4411
  MCK_GPR, // register class 'GPR'
4412
  MCK_GPRwithAPSR, // register class 'GPRwithAPSR'
4413
  MCK_QPR, // register class 'QPR'
4414
  MCK_SPR_8, // register class 'SPR_8'
4415
  MCK_DTripleSpc, // register class 'DTripleSpc,DQuadSpc'
4416
  MCK_DQuad, // register class 'DQuad'
4417
  MCK_DPairSpc, // register class 'DPairSpc'
4418
  MCK_DTriple, // register class 'DTriple'
4419
  MCK_DPair, // register class 'DPair'
4420
  MCK_DPR, // register class 'DPR'
4421
  MCK_HPR, // register class 'HPR,SPR'
4422
  MCK_LAST_REGISTER = MCK_HPR,
4423
  MCK_AM2OffsetImm, // user defined class 'AM2OffsetImmAsmOperand'
4424
  MCK_AM3Offset, // user defined class 'AM3OffsetAsmOperand'
4425
  MCK_ARMBranchTarget, // user defined class 'ARMBranchTarget'
4426
  MCK_AddrMode3, // user defined class 'AddrMode3AsmOperand'
4427
  MCK_AddrMode5, // user defined class 'AddrMode5AsmOperand'
4428
  MCK_AddrMode5FP16, // user defined class 'AddrMode5FP16AsmOperand'
4429
  MCK_AlignedMemory16, // user defined class 'AddrMode6Align16AsmOperand'
4430
  MCK_AlignedMemory32, // user defined class 'AddrMode6Align32AsmOperand'
4431
  MCK_AlignedMemory64, // user defined class 'AddrMode6Align64AsmOperand'
4432
  MCK_AlignedMemory64or128, // user defined class 'AddrMode6Align64or128AsmOperand'
4433
  MCK_AlignedMemory64or128or256, // user defined class 'AddrMode6Align64or128or256AsmOperand'
4434
  MCK_AlignedMemoryNone, // user defined class 'AddrMode6AlignNoneAsmOperand'
4435
  MCK_AlignedMemory, // user defined class 'AddrMode6AsmOperand'
4436
  MCK_DupAlignedMemory16, // user defined class 'AddrMode6dupAlign16AsmOperand'
4437
  MCK_DupAlignedMemory32, // user defined class 'AddrMode6dupAlign32AsmOperand'
4438
  MCK_DupAlignedMemory64, // user defined class 'AddrMode6dupAlign64AsmOperand'
4439
  MCK_DupAlignedMemory64or128, // user defined class 'AddrMode6dupAlign64or128AsmOperand'
4440
  MCK_DupAlignedMemoryNone, // user defined class 'AddrMode6dupAlignNoneAsmOperand'
4441
  MCK_AdrLabel, // user defined class 'AdrLabelAsmOperand'
4442
  MCK_BankedReg, // user defined class 'BankedRegOperand'
4443
  MCK_Bitfield, // user defined class 'BitfieldAsmOperand'
4444
  MCK_CCOut, // user defined class 'CCOutOperand'
4445
  MCK_CondCode, // user defined class 'CondCodeOperand'
4446
  MCK_CoprocNum, // user defined class 'CoprocNumAsmOperand'
4447
  MCK_CoprocOption, // user defined class 'CoprocOptionAsmOperand'
4448
  MCK_CoprocReg, // user defined class 'CoprocRegAsmOperand'
4449
  MCK_DPRRegList, // user defined class 'DPRRegListAsmOperand'
4450
  MCK_FPImm, // user defined class 'FPImmOperand'
4451
  MCK_Imm0_15, // user defined class 'Imm0_15AsmOperand'
4452
  MCK_Imm0_1, // user defined class 'Imm0_1AsmOperand'
4453
  MCK_Imm0_239, // user defined class 'Imm0_239AsmOperand'
4454
  MCK_Imm0_255, // user defined class 'Imm0_255AsmOperand'
4455
  MCK_Imm0_31, // user defined class 'Imm0_31AsmOperand'
4456
  MCK_Imm0_32, // user defined class 'Imm0_32AsmOperand'
4457
  MCK_Imm0_3, // user defined class 'Imm0_3AsmOperand'
4458
  MCK_Imm0_63, // user defined class 'Imm0_63AsmOperand'
4459
  MCK_Imm0_65535, // user defined class 'Imm0_65535AsmOperand'
4460
  MCK_Imm0_65535Expr, // user defined class 'Imm0_65535ExprAsmOperand'
4461
  MCK_Imm0_7, // user defined class 'Imm0_7AsmOperand'
4462
  MCK_Imm16, // user defined class 'Imm16AsmOperand'
4463
  MCK_Imm1_15, // user defined class 'Imm1_15AsmOperand'
4464
  MCK_Imm1_16, // user defined class 'Imm1_16AsmOperand'
4465
  MCK_Imm1_31, // user defined class 'Imm1_31AsmOperand'
4466
  MCK_Imm1_32, // user defined class 'Imm1_32AsmOperand'
4467
  MCK_Imm1_7, // user defined class 'Imm1_7AsmOperand'
4468
  MCK_Imm24bit, // user defined class 'Imm24bitAsmOperand'
4469
  MCK_Imm256_65535Expr, // user defined class 'Imm256_65535ExprAsmOperand'
4470
  MCK_Imm32, // user defined class 'Imm32AsmOperand'
4471
  MCK_Imm8, // user defined class 'Imm8AsmOperand'
4472
  MCK_Imm8_255, // user defined class 'Imm8_255AsmOperand'
4473
  MCK_Imm, // user defined class 'ImmAsmOperand'
4474
  MCK_InstSyncBarrierOpt, // user defined class 'InstSyncBarrierOptOperand'
4475
  MCK_MSRMask, // user defined class 'MSRMaskOperand'
4476
  MCK_MemBarrierOpt, // user defined class 'MemBarrierOptOperand'
4477
  MCK_MemImm0_1020s4Offset, // user defined class 'MemImm0_1020s4OffsetAsmOperand'
4478
  MCK_MemImm12Offset, // user defined class 'MemImm12OffsetAsmOperand'
4479
  MCK_MemImm8Offset, // user defined class 'MemImm8OffsetAsmOperand'
4480
  MCK_MemImm8s4Offset, // user defined class 'MemImm8s4OffsetAsmOperand'
4481
  MCK_MemNegImm8Offset, // user defined class 'MemNegImm8OffsetAsmOperand'
4482
  MCK_MemNoOffset, // user defined class 'MemNoOffsetAsmOperand'
4483
  MCK_MemPosImm8Offset, // user defined class 'MemPosImm8OffsetAsmOperand'
4484
  MCK_MemRegOffset, // user defined class 'MemRegOffsetAsmOperand'
4485
  MCK_ModImm, // user defined class 'ModImmAsmOperand'
4486
  MCK_ModImmNeg, // user defined class 'ModImmNegAsmOperand'
4487
  MCK_ModImmNot, // user defined class 'ModImmNotAsmOperand'
4488
  MCK_PKHASRImm, // user defined class 'PKHASRAsmOperand'
4489
  MCK_PKHLSLImm, // user defined class 'PKHLSLAsmOperand'
4490
  MCK_PostIdxImm8, // user defined class 'PostIdxImm8AsmOperand'
4491
  MCK_PostIdxImm8s4, // user defined class 'PostIdxImm8s4AsmOperand'
4492
  MCK_PostIdxReg, // user defined class 'PostIdxRegAsmOperand'
4493
  MCK_PostIdxRegShifted, // user defined class 'PostIdxRegShiftedAsmOperand'
4494
  MCK_ProcIFlags, // user defined class 'ProcIFlagsOperand'
4495
  MCK_RegList, // user defined class 'RegListAsmOperand'
4496
  MCK_RotImm, // user defined class 'RotImmAsmOperand'
4497
  MCK_SPRRegList, // user defined class 'SPRRegListAsmOperand'
4498
  MCK_SetEndImm, // user defined class 'SetEndAsmOperand'
4499
  MCK_RegShiftedImm, // user defined class 'ShiftedImmAsmOperand'
4500
  MCK_RegShiftedReg, // user defined class 'ShiftedRegAsmOperand'
4501
  MCK_ShifterImm, // user defined class 'ShifterImmAsmOperand'
4502
  MCK_ThumbBranchTarget, // user defined class 'ThumbBranchTarget'
4503
  MCK_ThumbMemPC, // user defined class 'ThumbMemPC'
4504
  MCK_ThumbModImmNeg1_7, // user defined class 'ThumbModImmNeg1_7AsmOperand'
4505
  MCK_ThumbModImmNeg8_255, // user defined class 'ThumbModImmNeg8_255AsmOperand'
4506
  MCK_ImmThumbSR, // user defined class 'ThumbSRImmAsmOperand'
4507
  MCK_TraceSyncBarrierOpt, // user defined class 'TraceSyncBarrierOptOperand'
4508
  MCK_UnsignedOffset_b8s2, // user defined class 'UnsignedOffset_b8s2'
4509
  MCK_VecListDPairAllLanes, // user defined class 'VecListDPairAllLanesAsmOperand'
4510
  MCK_VecListDPair, // user defined class 'VecListDPairAsmOperand'
4511
  MCK_VecListDPairSpacedAllLanes, // user defined class 'VecListDPairSpacedAllLanesAsmOperand'
4512
  MCK_VecListDPairSpaced, // user defined class 'VecListDPairSpacedAsmOperand'
4513
  MCK_VecListFourDAllLanes, // user defined class 'VecListFourDAllLanesAsmOperand'
4514
  MCK_VecListFourD, // user defined class 'VecListFourDAsmOperand'
4515
  MCK_VecListFourDByteIndexed, // user defined class 'VecListFourDByteIndexAsmOperand'
4516
  MCK_VecListFourDHWordIndexed, // user defined class 'VecListFourDHWordIndexAsmOperand'
4517
  MCK_VecListFourDWordIndexed, // user defined class 'VecListFourDWordIndexAsmOperand'
4518
  MCK_VecListFourQAllLanes, // user defined class 'VecListFourQAllLanesAsmOperand'
4519
  MCK_VecListFourQ, // user defined class 'VecListFourQAsmOperand'
4520
  MCK_VecListFourQHWordIndexed, // user defined class 'VecListFourQHWordIndexAsmOperand'
4521
  MCK_VecListFourQWordIndexed, // user defined class 'VecListFourQWordIndexAsmOperand'
4522
  MCK_VecListOneDAllLanes, // user defined class 'VecListOneDAllLanesAsmOperand'
4523
  MCK_VecListOneD, // user defined class 'VecListOneDAsmOperand'
4524
  MCK_VecListOneDByteIndexed, // user defined class 'VecListOneDByteIndexAsmOperand'
4525
  MCK_VecListOneDHWordIndexed, // user defined class 'VecListOneDHWordIndexAsmOperand'
4526
  MCK_VecListOneDWordIndexed, // user defined class 'VecListOneDWordIndexAsmOperand'
4527
  MCK_VecListThreeDAllLanes, // user defined class 'VecListThreeDAllLanesAsmOperand'
4528
  MCK_VecListThreeD, // user defined class 'VecListThreeDAsmOperand'
4529
  MCK_VecListThreeDByteIndexed, // user defined class 'VecListThreeDByteIndexAsmOperand'
4530
  MCK_VecListThreeDHWordIndexed, // user defined class 'VecListThreeDHWordIndexAsmOperand'
4531
  MCK_VecListThreeDWordIndexed, // user defined class 'VecListThreeDWordIndexAsmOperand'
4532
  MCK_VecListThreeQAllLanes, // user defined class 'VecListThreeQAllLanesAsmOperand'
4533
  MCK_VecListThreeQ, // user defined class 'VecListThreeQAsmOperand'
4534
  MCK_VecListThreeQHWordIndexed, // user defined class 'VecListThreeQHWordIndexAsmOperand'
4535
  MCK_VecListThreeQWordIndexed, // user defined class 'VecListThreeQWordIndexAsmOperand'
4536
  MCK_VecListTwoDByteIndexed, // user defined class 'VecListTwoDByteIndexAsmOperand'
4537
  MCK_VecListTwoDHWordIndexed, // user defined class 'VecListTwoDHWordIndexAsmOperand'
4538
  MCK_VecListTwoDWordIndexed, // user defined class 'VecListTwoDWordIndexAsmOperand'
4539
  MCK_VecListTwoQHWordIndexed, // user defined class 'VecListTwoQHWordIndexAsmOperand'
4540
  MCK_VecListTwoQWordIndexed, // user defined class 'VecListTwoQWordIndexAsmOperand'
4541
  MCK_VectorIndex16, // user defined class 'VectorIndex16Operand'
4542
  MCK_VectorIndex32, // user defined class 'VectorIndex32Operand'
4543
  MCK_VectorIndex64, // user defined class 'VectorIndex64Operand'
4544
  MCK_VectorIndex8, // user defined class 'VectorIndex8Operand'
4545
  MCK_MemTBB, // user defined class 'addrmode_tbb_asmoperand'
4546
  MCK_MemTBH, // user defined class 'addrmode_tbh_asmoperand'
4547
  MCK_ComplexRotationEven, // user defined class 'anonymous_3115'
4548
  MCK_ComplexRotationOdd, // user defined class 'anonymous_3116'
4549
  MCK_NEONi16vmovi8Replicate, // user defined class 'anonymous_4174'
4550
  MCK_NEONi16invi8Replicate, // user defined class 'anonymous_4176'
4551
  MCK_NEONi32vmovi8Replicate, // user defined class 'anonymous_4179'
4552
  MCK_NEONi32invi8Replicate, // user defined class 'anonymous_4181'
4553
  MCK_NEONi64vmovi8Replicate, // user defined class 'anonymous_4188'
4554
  MCK_NEONi64invi8Replicate, // user defined class 'anonymous_4190'
4555
  MCK_NEONi32vmovi16Replicate, // user defined class 'anonymous_4201'
4556
  MCK_NEONi64vmovi16Replicate, // user defined class 'anonymous_4204'
4557
  MCK_NEONi64vmovi32Replicate, // user defined class 'anonymous_4211'
4558
  MCK_ConstPoolAsmImm, // user defined class 'const_pool_asm_operand'
4559
  MCK_FBits16, // user defined class 'fbits16_asm_operand'
4560
  MCK_FBits32, // user defined class 'fbits32_asm_operand'
4561
  MCK_Imm0_4095, // user defined class 'imm0_4095_asmoperand'
4562
  MCK_Imm0_4095Neg, // user defined class 'imm0_4095_neg_asmoperand'
4563
  MCK_ITMask, // user defined class 'it_mask_asmoperand'
4564
  MCK_ITCondCode, // user defined class 'it_pred_asmoperand'
4565
  MCK_NEONi16splat, // user defined class 'nImmSplatI16AsmOperand'
4566
  MCK_NEONi32splat, // user defined class 'nImmSplatI32AsmOperand'
4567
  MCK_NEONi64splat, // user defined class 'nImmSplatI64AsmOperand'
4568
  MCK_NEONi8splat, // user defined class 'nImmSplatI8AsmOperand'
4569
  MCK_NEONi16splatNot, // user defined class 'nImmSplatNotI16AsmOperand'
4570
  MCK_NEONi32splatNot, // user defined class 'nImmSplatNotI32AsmOperand'
4571
  MCK_NEONi32vmov, // user defined class 'nImmVMOVI32AsmOperand'
4572
  MCK_NEONi32vmovNeg, // user defined class 'nImmVMOVI32NegAsmOperand'
4573
  MCK_ShrImm16, // user defined class 'shr_imm16_asm_operand'
4574
  MCK_ShrImm32, // user defined class 'shr_imm32_asm_operand'
4575
  MCK_ShrImm64, // user defined class 'shr_imm64_asm_operand'
4576
  MCK_ShrImm8, // user defined class 'shr_imm8_asm_operand'
4577
  MCK_T2SOImm, // user defined class 't2_so_imm_asmoperand'
4578
  MCK_T2SOImmNeg, // user defined class 't2_so_imm_neg_asmoperand'
4579
  MCK_T2SOImmNot, // user defined class 't2_so_imm_not_asmoperand'
4580
  MCK_MemUImm12Offset, // user defined class 't2addrmode_imm12_asmoperand'
4581
  MCK_T2MemRegOffset, // user defined class 't2addrmode_so_reg_asmoperand'
4582
  MCK_Imm8s4, // user defined class 't2am_imm8s4_offset_asmoperand'
4583
  MCK_MemPCRelImm12, // user defined class 't2ldr_pcrel_imm12_asmoperand'
4584
  MCK_MemThumbRIs1, // user defined class 't_addrmode_is1_asm_operand'
4585
  MCK_MemThumbRIs2, // user defined class 't_addrmode_is2_asm_operand'
4586
  MCK_MemThumbRIs4, // user defined class 't_addrmode_is4_asm_operand'
4587
  MCK_MemThumbRR, // user defined class 't_addrmode_rr_asm_operand'
4588
  MCK_MemThumbSPI, // user defined class 't_addrmode_sp_asm_operand'
4589
  MCK_Imm0_1020s4, // user defined class 't_imm0_1020s4_asmoperand'
4590
  MCK_Imm0_508s4, // user defined class 't_imm0_508s4_asmoperand'
4591
  MCK_Imm0_508s4Neg, // user defined class 't_imm0_508s4_neg_asmoperand'
4592
  NumMatchClassKinds
4593
};
4594
4595
}
4596
4597
4.82k
static const char *getMatchKindDiag(ARMAsmParser::ARMMatchResultTy MatchResult) {
4598
4.82k
  switch (MatchResult) {
4599
4.82k
  case ARMAsmParser::Match_GPRsp:
4600
3
    return "operand must be a register sp";
4601
4.82k
  case ARMAsmParser::Match_QPR_8:
4602
0
    return "operand must be a register in range [q0, q3]";
4603
4.82k
  case ARMAsmParser::Match_DPR_8:
4604
0
    return "operand must be a register in range [d0, d7]";
4605
4.82k
  case ARMAsmParser::Match_QPR_VFP2:
4606
0
    return "operand must be a register in range [q0, q7]";
4607
4.82k
  case ARMAsmParser::Match_hGPR:
4608
0
    return "operand must be a register in range [r8, r15]";
4609
4.82k
  case ARMAsmParser::Match_tGPR:
4610
39
    return "operand must be a register in range [r0, r7]";
4611
4.82k
  case ARMAsmParser::Match_GPRnopc:
4612
118
    return "operand must be a register in range [r0, r14]";
4613
4.82k
  case ARMAsmParser::Match_DPR_VFP2:
4614
4
    return "operand must be a register in range [d0, d15]";
4615
4.82k
  case ARMAsmParser::Match_GPR:
4616
59
    return "operand must be a register in range [r0, r15]";
4617
4.82k
  case ARMAsmParser::Match_GPRwithAPSR:
4618
0
    return "operand must be a register in range [r0, r14] or apsr_nzcv";
4619
4.82k
  case ARMAsmParser::Match_QPR:
4620
26
    return "operand must be a register in range [q0, q15]";
4621
4.82k
  case ARMAsmParser::Match_SPR_8:
4622
0
    return "operand must be a register in range [s0, s15]";
4623
4.82k
  case ARMAsmParser::Match_SPR:
4624
4
    return "operand must be a register in range [s0, s31]";
4625
4.82k
  case ARMAsmParser::Match_AlignedMemory16:
4626
48
    return "alignment must be 16 or omitted";
4627
4.82k
  case ARMAsmParser::Match_AlignedMemory32:
4628
84
    return "alignment must be 32 or omitted";
4629
4.82k
  case ARMAsmParser::Match_AlignedMemory64:
4630
432
    return "alignment must be 64 or omitted";
4631
4.82k
  case ARMAsmParser::Match_AlignedMemory64or128:
4632
213
    return "alignment must be 64, 128 or omitted";
4633
4.82k
  case ARMAsmParser::Match_AlignedMemory64or128or256:
4634
150
    return "alignment must be 64, 128, 256 or omitted";
4635
4.82k
  case ARMAsmParser::Match_AlignedMemoryNone:
4636
180
    return "alignment must be omitted";
4637
4.82k
  case ARMAsmParser::Match_DupAlignedMemory16:
4638
48
    return "alignment must be 16 or omitted";
4639
4.82k
  case ARMAsmParser::Match_DupAlignedMemory32:
4640
72
    return "alignment must be 32 or omitted";
4641
4.82k
  case ARMAsmParser::Match_DupAlignedMemory64:
4642
48
    return "alignment must be 64 or omitted";
4643
4.82k
  case ARMAsmParser::Match_DupAlignedMemory64or128:
4644
18
    return "alignment must be 64, 128 or omitted";
4645
4.82k
  case ARMAsmParser::Match_DupAlignedMemoryNone:
4646
120
    return "alignment must be omitted";
4647
4.82k
  case ARMAsmParser::Match_Imm0_15:
4648
15
    return "operand must be an immediate in the range [0,15]";
4649
4.82k
  case ARMAsmParser::Match_Imm0_1:
4650
4
    return "operand must be an immediate in the range [0,1]";
4651
4.82k
  case ARMAsmParser::Match_Imm0_239:
4652
4
    return "operand must be an immediate in the range [0,239]";
4653
4.82k
  case ARMAsmParser::Match_Imm0_255:
4654
23
    return "operand must be an immediate in the range [0,255]";
4655
4.82k
  case ARMAsmParser::Match_Imm0_31:
4656
8
    return "operand must be an immediate in the range [0,31]";
4657
4.82k
  case ARMAsmParser::Match_Imm0_32:
4658
0
    return "operand must be an immediate in the range [0,32]";
4659
4.82k
  case ARMAsmParser::Match_Imm0_3:
4660
0
    return "operand must be an immediate in the range [0,3]";
4661
4.82k
  case ARMAsmParser::Match_Imm0_63:
4662
2
    return "operand must be an immediate in the range [0,63]";
4663
4.82k
  case ARMAsmParser::Match_Imm0_65535:
4664
6
    return "operand must be an immediate in the range [0,65535]";
4665
4.82k
  case ARMAsmParser::Match_Imm0_65535Expr:
4666
8
    return "operand must be an immediate in the range [0,0xffff] or a relocatable expression";
4667
4.82k
  case ARMAsmParser::Match_Imm0_7:
4668
30
    return "operand must be an immediate in the range [0,7]";
4669
4.82k
  case ARMAsmParser::Match_Imm16:
4670
0
    return "operand must be an immediate in the range [16,16]";
4671
4.82k
  case ARMAsmParser::Match_Imm1_15:
4672
0
    return "operand must be an immediate in the range [1,15]";
4673
4.82k
  case ARMAsmParser::Match_ImmRange1_16:
4674
4
    return "operand must be an immediate in the range [1,16]";
4675
4.82k
  case ARMAsmParser::Match_Imm1_31:
4676
4
    return "operand must be an immediate in the range [1,31]";
4677
4.82k
  case ARMAsmParser::Match_ImmRange1_32:
4678
4
    return "operand must be an immediate in the range [1,32]";
4679
4.82k
  case ARMAsmParser::Match_Imm1_7:
4680
0
    return "operand must be an immediate in the range [1,7]";
4681
4.82k
  case ARMAsmParser::Match_Imm24bit:
4682
2
    return "operand must be an immediate in the range [0,0xffffff]";
4683
4.82k
  case ARMAsmParser::Match_Imm256_65535Expr:
4684
5
    return "operand must be an immediate in the range [256,65535]";
4685
4.82k
  case ARMAsmParser::Match_Imm32:
4686
0
    return "operand must be an immediate in the range [32,32]";
4687
4.82k
  case ARMAsmParser::Match_Imm8:
4688
0
    return "operand must be an immediate in the range [8,8]";
4689
4.82k
  case ARMAsmParser::Match_Imm8_255:
4690
0
    return "operand must be an immediate in the range [8,255]";
4691
4.82k
  case ARMAsmParser::Match_PKHLSLImm:
4692
0
    return "operand must be an immediate in the range [0,31]";
4693
4.82k
  case ARMAsmParser::Match_SPRRegList:
4694
8
    return "operand must be a list of registers in range [s0, s31]";
4695
4.82k
  case ARMAsmParser::Match_SetEndImm:
4696
0
    return "operand must be an immediate in the range [0,1]";