Coverage Report

Created: 2019-03-22 08:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenAsmMatcher.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Matcher Source Fragment                                           *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_ASSEMBLER_HEADER
11
#undef GET_ASSEMBLER_HEADER
12
  // This should be included into the middle of the declaration of
13
  // your subclasses implementation of MCTargetAsmParser.
14
  FeatureBitset ComputeAvailableFeatures(const FeatureBitset& FB) const;
15
  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16
                       const OperandVector &Operands);
17
  void convertToMapAndConstraints(unsigned Kind,
18
                           const OperandVector &Operands) override;
19
  unsigned MatchInstructionImpl(const OperandVector &Operands,
20
                                MCInst &Inst,
21
                                SmallVectorImpl<NearMissInfo> *NearMisses,
22
                                bool matchingInlineAsm,
23
                                unsigned VariantID = 0);
24
  OperandMatchResultTy MatchOperandParserImpl(
25
    OperandVector &Operands,
26
    StringRef Mnemonic,
27
    bool ParseForAllFeatures = false);
28
  OperandMatchResultTy tryCustomParseOperand(
29
    OperandVector &Operands,
30
    unsigned MCK);
31
32
#endif // GET_ASSEMBLER_HEADER_INFO
33
34
35
#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
36
#undef GET_OPERAND_DIAGNOSTIC_TYPES
37
38
  Match_AlignedMemory16,
39
  Match_AlignedMemory32,
40
  Match_AlignedMemory64,
41
  Match_AlignedMemory64or128,
42
  Match_AlignedMemory64or128or256,
43
  Match_AlignedMemoryNone,
44
  Match_ComplexRotationEven,
45
  Match_ComplexRotationOdd,
46
  Match_DPR,
47
  Match_DPR_8,
48
  Match_DPR_RegList,
49
  Match_DPR_VFP2,
50
  Match_DupAlignedMemory16,
51
  Match_DupAlignedMemory32,
52
  Match_DupAlignedMemory64,
53
  Match_DupAlignedMemory64or128,
54
  Match_DupAlignedMemoryNone,
55
  Match_GPR,
56
  Match_GPRnopc,
57
  Match_GPRsp,
58
  Match_GPRwithAPSR,
59
  Match_Imm0_1,
60
  Match_Imm0_15,
61
  Match_Imm0_239,
62
  Match_Imm0_255,
63
  Match_Imm0_3,
64
  Match_Imm0_31,
65
  Match_Imm0_32,
66
  Match_Imm0_4095,
67
  Match_Imm0_63,
68
  Match_Imm0_65535,
69
  Match_Imm0_65535Expr,
70
  Match_Imm0_7,
71
  Match_Imm16,
72
  Match_Imm1_15,
73
  Match_Imm1_31,
74
  Match_Imm1_7,
75
  Match_Imm24bit,
76
  Match_Imm256_65535Expr,
77
  Match_Imm32,
78
  Match_Imm8,
79
  Match_Imm8_255,
80
  Match_ImmRange1_16,
81
  Match_ImmRange1_32,
82
  Match_ImmThumbSR,
83
  Match_PKHLSLImm,
84
  Match_QPR,
85
  Match_QPR_8,
86
  Match_QPR_VFP2,
87
  Match_SPR,
88
  Match_SPRRegList,
89
  Match_SPR_8,
90
  Match_SetEndImm,
91
  Match_ShrImm16,
92
  Match_ShrImm32,
93
  Match_ShrImm64,
94
  Match_ShrImm8,
95
  Match_hGPR,
96
  Match_rGPR,
97
  Match_tGPR,
98
  END_OPERAND_DIAGNOSTIC_TYPES
99
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
100
101
102
#ifdef GET_REGISTER_MATCHER
103
#undef GET_REGISTER_MATCHER
104
105
// Bits for subtarget features that participate in instruction matching.
106
enum SubtargetFeatureBits : uint8_t {
107
  Feature_HasV4TBit = 22,
108
  Feature_HasV5TBit = 23,
109
  Feature_HasV5TEBit = 24,
110
  Feature_HasV6Bit = 25,
111
  Feature_HasV6MBit = 27,
112
  Feature_HasV8MBaselineBit = 32,
113
  Feature_HasV8MMainlineBit = 33,
114
  Feature_HasV6T2Bit = 28,
115
  Feature_HasV6KBit = 26,
116
  Feature_HasV7Bit = 29,
117
  Feature_HasV8Bit = 31,
118
  Feature_PreV8Bit = 48,
119
  Feature_HasV8_1aBit = 34,
120
  Feature_HasV8_2aBit = 35,
121
  Feature_HasV8_3aBit = 36,
122
  Feature_HasV8_4aBit = 37,
123
  Feature_HasV8_5aBit = 38,
124
  Feature_HasVFP2Bit = 39,
125
  Feature_HasVFP3Bit = 40,
126
  Feature_HasVFP4Bit = 41,
127
  Feature_HasDPVFPBit = 7,
128
  Feature_HasFPARMv8Bit = 14,
129
  Feature_HasNEONBit = 17,
130
  Feature_HasSHA2Bit = 20,
131
  Feature_HasAESBit = 1,
132
  Feature_HasCryptoBit = 4,
133
  Feature_HasDotProdBit = 11,
134
  Feature_HasCRCBit = 3,
135
  Feature_HasRASBit = 18,
136
  Feature_HasFP16Bit = 12,
137
  Feature_HasFullFP16Bit = 15,
138
  Feature_HasFP16FMLBit = 13,
139
  Feature_HasDivideInThumbBit = 10,
140
  Feature_HasDivideInARMBit = 9,
141
  Feature_HasDSPBit = 8,
142
  Feature_HasDBBit = 5,
143
  Feature_HasDFBBit = 6,
144
  Feature_HasV7ClrexBit = 30,
145
  Feature_HasAcquireReleaseBit = 2,
146
  Feature_HasMPBit = 16,
147
  Feature_HasVirtualizationBit = 42,
148
  Feature_HasTrustZoneBit = 21,
149
  Feature_Has8MSecExtBit = 0,
150
  Feature_IsThumbBit = 46,
151
  Feature_IsThumb2Bit = 47,
152
  Feature_IsMClassBit = 44,
153
  Feature_IsNotMClassBit = 45,
154
  Feature_IsARMBit = 43,
155
  Feature_UseNaClTrapBit = 49,
156
  Feature_UseNegativeImmediatesBit = 50,
157
  Feature_HasSBBit = 19,
158
};
159
160
68.5k
static unsigned MatchRegisterName(StringRef Name) {
161
68.5k
  switch (Name.size()) {
162
68.5k
  
default: break87
;
163
68.5k
  case 2:  // 43 strings to match.
164
59.5k
    switch (Name[0]) {
165
59.5k
    
default: break702
;
166
59.5k
    case 'd':  // 10 strings to match.
167
11.0k
      switch (Name[1]) {
168
11.0k
      
default: break0
;
169
11.0k
      case '0':  // 1 string to match.
170
3.87k
        return 14;  // "d0"
171
11.0k
      case '1':  // 1 string to match.
172
2.19k
        return 15;  // "d1"
173
11.0k
      case '2':  // 1 string to match.
174
2.39k
        return 16;  // "d2"
175
11.0k
      case '3':  // 1 string to match.
176
784
        return 17;  // "d3"
177
11.0k
      case '4':  // 1 string to match.
178
693
        return 18;  // "d4"
179
11.0k
      case '5':  // 1 string to match.
180
149
        return 19;  // "d5"
181
11.0k
      case '6':  // 1 string to match.
182
476
        return 20;  // "d6"
183
11.0k
      case '7':  // 1 string to match.
184
281
        return 21;  // "d7"
185
11.0k
      case '8':  // 1 string to match.
186
97
        return 22;  // "d8"
187
11.0k
      case '9':  // 1 string to match.
188
83
        return 23;  // "d9"
189
0
      }
190
0
      break;
191
1.97k
    case 'l':  // 1 string to match.
192
1.97k
      if (Name[1] != 'r')
193
10
        break;
194
1.96k
      return 10;   // "lr"
195
1.96k
    case 'p':  // 1 string to match.
196
860
      if (Name[1] != 'c')
197
21
        break;
198
839
      return 11;   // "pc"
199
3.99k
    case 'q':  // 10 strings to match.
200
3.99k
      switch (Name[1]) {
201
3.99k
      
default: break0
;
202
3.99k
      case '0':  // 1 string to match.
203
712
        return 50;  // "q0"
204
3.99k
      case '1':  // 1 string to match.
205
641
        return 51;  // "q1"
206
3.99k
      case '2':  // 1 string to match.
207
416
        return 52;  // "q2"
208
3.99k
      case '3':  // 1 string to match.
209
176
        return 53;  // "q3"
210
3.99k
      case '4':  // 1 string to match.
211
212
        return 54;  // "q4"
212
3.99k
      case '5':  // 1 string to match.
213
114
        return 55;  // "q5"
214
3.99k
      case '6':  // 1 string to match.
215
92
        return 56;  // "q6"
216
3.99k
      case '7':  // 1 string to match.
217
100
        return 57;  // "q7"
218
3.99k
      case '8':  // 1 string to match.
219
1.19k
        return 58;  // "q8"
220
3.99k
      case '9':  // 1 string to match.
221
342
        return 59;  // "q9"
222
0
      }
223
0
      break;
224
37.5k
    case 'r':  // 10 strings to match.
225
37.5k
      switch (Name[1]) {
226
37.5k
      
default: break0
;
227
37.5k
      case '0':  // 1 string to match.
228
10.8k
        return 66;  // "r0"
229
37.5k
      case '1':  // 1 string to match.
230
5.01k
        return 67;  // "r1"
231
37.5k
      case '2':  // 1 string to match.
232
3.90k
        return 68;  // "r2"
233
37.5k
      case '3':  // 1 string to match.
234
3.87k
        return 69;  // "r3"
235
37.5k
      case '4':  // 1 string to match.
236
4.90k
        return 70;  // "r4"
237
37.5k
      case '5':  // 1 string to match.
238
2.33k
        return 71;  // "r5"
239
37.5k
      case '6':  // 1 string to match.
240
2.79k
        return 72;  // "r6"
241
37.5k
      case '7':  // 1 string to match.
242
1.65k
        return 73;  // "r7"
243
37.5k
      case '8':  // 1 string to match.
244
1.51k
        return 74;  // "r8"
245
37.5k
      case '9':  // 1 string to match.
246
769
        return 75;  // "r9"
247
0
      }
248
0
      break;
249
3.37k
    case 's':  // 11 strings to match.
250
3.37k
      switch (Name[1]) {
251
3.37k
      
default: break5
;
252
3.37k
      case '0':  // 1 string to match.
253
1.39k
        return 79;  // "s0"
254
3.37k
      case '1':  // 1 string to match.
255
354
        return 80;  // "s1"
256
3.37k
      case '2':  // 1 string to match.
257
217
        return 81;  // "s2"
258
3.37k
      case '3':  // 1 string to match.
259
77
        return 82;  // "s3"
260
3.37k
      case '4':  // 1 string to match.
261
104
        return 83;  // "s4"
262
3.37k
      case '5':  // 1 string to match.
263
33
        return 84;  // "s5"
264
3.37k
      case '6':  // 1 string to match.
265
37
        return 85;  // "s6"
266
3.37k
      case '7':  // 1 string to match.
267
37
        return 86;  // "s7"
268
3.37k
      case '8':  // 1 string to match.
269
25
        return 87;  // "s8"
270
3.37k
      case '9':  // 1 string to match.
271
19
        return 88;  // "s9"
272
3.37k
      case 'p':  // 1 string to match.
273
1.07k
        return 12;  // "sp"
274
5
      }
275
5
      break;
276
738
    }
277
738
    break;
278
8.50k
  case 3:  // 53 strings to match.
279
8.50k
    switch (Name[0]) {
280
8.50k
    
default: break2.07k
;
281
8.50k
    case 'd':  // 22 strings to match.
282
3.54k
      switch (Name[1]) {
283
3.54k
      
default: break0
;
284
3.54k
      case '1':  // 10 strings to match.
285
3.15k
        switch (Name[2]) {
286
3.15k
        
default: break0
;
287
3.15k
        case '0':  // 1 string to match.
288
75
          return 24;  // "d10"
289
3.15k
        case '1':  // 1 string to match.
290
85
          return 25;  // "d11"
291
3.15k
        case '2':  // 1 string to match.
292
111
          return 26;  // "d12"
293
3.15k
        case '3':  // 1 string to match.
294
66
          return 27;  // "d13"
295
3.15k
        case '4':  // 1 string to match.
296
66
          return 28;  // "d14"
297
3.15k
        case '5':  // 1 string to match.
298
60
          return 29;  // "d15"
299
3.15k
        case '6':  // 1 string to match.
300
1.51k
          return 30;  // "d16"
301
3.15k
        case '7':  // 1 string to match.
302
663
          return 31;  // "d17"
303
3.15k
        case '8':  // 1 string to match.
304
317
          return 32;  // "d18"
305
3.15k
        case '9':  // 1 string to match.
306
202
          return 33;  // "d19"
307
0
        }
308
0
        break;
309
347
      case '2':  // 10 strings to match.
310
347
        switch (Name[2]) {
311
347
        
default: break0
;
312
347
        case '0':  // 1 string to match.
313
86
          return 34;  // "d20"
314
347
        case '1':  // 1 string to match.
315
74
          return 35;  // "d21"
316
347
        case '2':  // 1 string to match.
317
57
          return 36;  // "d22"
318
347
        case '3':  // 1 string to match.
319
56
          return 37;  // "d23"
320
347
        case '4':  // 1 string to match.
321
20
          return 38;  // "d24"
322
347
        case '5':  // 1 string to match.
323
12
          return 39;  // "d25"
324
347
        case '6':  // 1 string to match.
325
16
          return 40;  // "d26"
326
347
        case '7':  // 1 string to match.
327
10
          return 41;  // "d27"
328
347
        case '8':  // 1 string to match.
329
8
          return 42;  // "d28"
330
347
        case '9':  // 1 string to match.
331
8
          return 43;  // "d29"
332
0
        }
333
0
        break;
334
39
      case '3':  // 2 strings to match.
335
39
        switch (Name[2]) {
336
39
        
default: break0
;
337
39
        case '0':  // 1 string to match.
338
19
          return 44;  // "d30"
339
39
        case '1':  // 1 string to match.
340
20
          return 45;  // "d31"
341
0
        }
342
0
        break;
343
0
      }
344
0
      break;
345
151
    case 'q':  // 6 strings to match.
346
151
      if (Name[1] != '1')
347
0
        break;
348
151
      switch (Name[2]) {
349
151
      
default: break0
;
350
151
      case '0':  // 1 string to match.
351
52
        return 60;  // "q10"
352
151
      case '1':  // 1 string to match.
353
27
        return 61;  // "q11"
354
151
      case '2':  // 1 string to match.
355
27
        return 62;  // "q12"
356
151
      case '3':  // 1 string to match.
357
17
        return 63;  // "q13"
358
151
      case '4':  // 1 string to match.
359
19
        return 64;  // "q14"
360
151
      case '5':  // 1 string to match.
361
9
        return 65;  // "q15"
362
0
      }
363
0
      break;
364
2.19k
    case 'r':  // 3 strings to match.
365
2.19k
      if (Name[1] != '1')
366
214
        break;
367
1.98k
      switch (Name[2]) {
368
1.98k
      
default: break51
;
369
1.98k
      case '0':  // 1 string to match.
370
422
        return 76;  // "r10"
371
1.98k
      case '1':  // 1 string to match.
372
350
        return 77;  // "r11"
373
1.98k
      case '2':  // 1 string to match.
374
1.16k
        return 78;  // "r12"
375
51
      }
376
51
      break;
377
535
    case 's':  // 22 strings to match.
378
535
      switch (Name[1]) {
379
535
      
default: break0
;
380
535
      case '1':  // 10 strings to match.
381
468
        switch (Name[2]) {
382
468
        
default: break0
;
383
468
        case '0':  // 1 string to match.
384
16
          return 89;  // "s10"
385
468
        case '1':  // 1 string to match.
386
9
          return 90;  // "s11"
387
468
        case '2':  // 1 string to match.
388
57
          return 91;  // "s12"
389
468
        case '3':  // 1 string to match.
390
18
          return 92;  // "s13"
391
468
        case '4':  // 1 string to match.
392
118
          return 93;  // "s14"
393
468
        case '5':  // 1 string to match.
394
202
          return 94;  // "s15"
395
468
        case '6':  // 1 string to match.
396
8
          return 95;  // "s16"
397
468
        case '7':  // 1 string to match.
398
40
          return 96;  // "s17"
399
468
        case '8':  // 1 string to match.
400
0
          return 97;  // "s18"
401
468
        case '9':  // 1 string to match.
402
0
          return 98;  // "s19"
403
0
        }
404
0
        break;
405
59
      case '2':  // 10 strings to match.
406
59
        switch (Name[2]) {
407
59
        
default: break0
;
408
59
        case '0':  // 1 string to match.
409
0
          return 99;  // "s20"
410
59
        case '1':  // 1 string to match.
411
7
          return 100;  // "s21"
412
59
        case '2':  // 1 string to match.
413
0
          return 101;  // "s22"
414
59
        case '3':  // 1 string to match.
415
24
          return 102;  // "s23"
416
59
        case '4':  // 1 string to match.
417
8
          return 103;  // "s24"
418
59
        case '5':  // 1 string to match.
419
1
          return 104;  // "s25"
420
59
        case '6':  // 1 string to match.
421
3
          return 105;  // "s26"
422
59
        case '7':  // 1 string to match.
423
0
          return 106;  // "s27"
424
59
        case '8':  // 1 string to match.
425
16
          return 107;  // "s28"
426
59
        case '9':  // 1 string to match.
427
0
          return 108;  // "s29"
428
0
        }
429
0
        break;
430
8
      case '3':  // 2 strings to match.
431
8
        switch (Name[2]) {
432
8
        
default: break0
;
433
8
        case '0':  // 1 string to match.
434
6
          return 109;  // "s30"
435
8
        case '1':  // 1 string to match.
436
2
          return 110;  // "s31"
437
0
        }
438
0
        break;
439
0
      }
440
0
      break;
441
2.34k
    }
442
2.34k
    break;
443
2.34k
  case 4:  // 3 strings to match.
444
70
    switch (Name[0]) {
445
70
    
default: break42
;
446
70
    case 'a':  // 1 string to match.
447
4
      if (memcmp(Name.data()+1, "psr", 3) != 0)
448
0
        break;
449
4
      return 1;  // "apsr"
450
9
    case 'c':  // 1 string to match.
451
9
      if (memcmp(Name.data()+1, "psr", 3) != 0)
452
0
        break;
453
9
      return 3;  // "cpsr"
454
15
    case 's':  // 1 string to match.
455
15
      if (memcmp(Name.data()+1, "psr", 3) != 0)
456
11
        break;
457
4
      return 13;  // "spsr"
458
53
    }
459
53
    break;
460
225
  case 5:  // 6 strings to match.
461
225
    switch (Name[0]) {
462
225
    
default: break26
;
463
225
    case 'f':  // 3 strings to match.
464
167
      if (Name[1] != 'p')
465
0
        break;
466
167
      switch (Name[2]) {
467
167
      
default: break0
;
468
167
      case 'e':  // 1 string to match.
469
9
        if (memcmp(Name.data()+3, "xc", 2) != 0)
470
0
          break;
471
9
        return 4;  // "fpexc"
472
158
      case 's':  // 2 strings to match.
473
158
        switch (Name[3]) {
474
158
        
default: break0
;
475
158
        case 'c':  // 1 string to match.
476
133
          if (Name[4] != 'r')
477
0
            break;
478
133
          return 6;  // "fpscr"
479
133
        case 'i':  // 1 string to match.
480
25
          if (Name[4] != 'd')
481
0
            break;
482
25
          return 8;  // "fpsid"
483
0
        }
484
0
        break;
485
0
      }
486
0
      break;
487
32
    case 'm':  // 3 strings to match.
488
32
      if (memcmp(Name.data()+1, "vfr", 3) != 0)
489
0
        break;
490
32
      switch (Name[4]) {
491
32
      
default: break0
;
492
32
      case '0':  // 1 string to match.
493
8
        return 47;  // "mvfr0"
494
32
      case '1':  // 1 string to match.
495
8
        return 48;  // "mvfr1"
496
32
      case '2':  // 1 string to match.
497
16
        return 49;  // "mvfr2"
498
0
      }
499
0
      break;
500
26
    }
501
26
    break;
502
45
  case 6:  // 1 string to match.
503
45
    if (memcmp(Name.data()+0, "fpinst", 6) != 0)
504
43
      break;
505
2
    return 5;  // "fpinst"
506
11
  case 7:  // 2 strings to match.
507
11
    switch (Name[0]) {
508
11
    
default: break7
;
509
11
    case 'f':  // 1 string to match.
510
2
      if (memcmp(Name.data()+1, "pinst2", 6) != 0)
511
0
        break;
512
2
      return 46;   // "fpinst2"
513
2
    case 'i':  // 1 string to match.
514
2
      if (memcmp(Name.data()+1, "tstate", 6) != 0)
515
2
        break;
516
0
      return 9;  // "itstate"
517
9
    }
518
9
    break;
519
92
  case 9:  // 1 string to match.
520
92
    if (memcmp(Name.data()+0, "apsr_nzcv", 9) != 0)
521
3
      break;
522
89
    return 2;  // "apsr_nzcv"
523
89
  case 10:   // 1 string to match.
524
9
    if (memcmp(Name.data()+0, "fpscr_nzcv", 10) != 0)
525
9
      break;
526
0
    return 7;  // "fpscr_nzcv"
527
3.31k
  }
528
3.31k
  return 0;
529
3.31k
}
530
531
#endif // GET_REGISTER_MATCHER
532
533
534
#ifdef GET_SUBTARGET_FEATURE_NAME
535
#undef GET_SUBTARGET_FEATURE_NAME
536
537
// User-level names for subtarget features that participate in
538
// instruction matching.
539
2.33k
static const char *getSubtargetFeatureName(uint64_t Val) {
540
2.33k
  switch(Val) {
541
2.33k
  
case Feature_HasV4TBit: return "armv4t"0
;
542
2.33k
  
case Feature_HasV5TBit: return "armv5t"1
;
543
2.33k
  
case Feature_HasV5TEBit: return "armv5te"0
;
544
2.33k
  
case Feature_HasV6Bit: return "armv6"0
;
545
2.33k
  
case Feature_HasV6MBit: return "armv6m or armv6t2"12
;
546
2.33k
  
case Feature_HasV8MBaselineBit: return "armv8m.base"12
;
547
2.33k
  
case Feature_HasV8MMainlineBit: return "armv8m.main"2
;
548
2.33k
  
case Feature_HasV6T2Bit: return "armv6t2"4
;
549
2.33k
  
case Feature_HasV6KBit: return "armv6k"5
;
550
2.33k
  
case Feature_HasV7Bit: return "armv7"6
;
551
2.33k
  
case Feature_HasV8Bit: return "armv8"113
;
552
2.33k
  
case Feature_PreV8Bit: return "armv7 or earlier"2
;
553
2.33k
  
case Feature_HasV8_1aBit: return "armv8.1a"36
;
554
2.33k
  
case Feature_HasV8_2aBit: return "armv8.2a"0
;
555
2.33k
  
case Feature_HasV8_3aBit: return "armv8.3a"42
;
556
2.33k
  
case Feature_HasV8_4aBit: return "armv8.4a"0
;
557
2.33k
  
case Feature_HasV8_5aBit: return "armv8.5a"0
;
558
2.33k
  
case Feature_HasVFP2Bit: return "VFP2"12
;
559
2.33k
  
case Feature_HasVFP3Bit: return "VFP3"0
;
560
2.33k
  
case Feature_HasVFP4Bit: return "VFP4"0
;
561
2.33k
  
case Feature_HasDPVFPBit: return "double precision VFP"52
;
562
2.33k
  
case Feature_HasFPARMv8Bit: return "FPARMv8"669
;
563
2.33k
  
case Feature_HasNEONBit: return "NEON"319
;
564
2.33k
  
case Feature_HasSHA2Bit: return "sha2"0
;
565
2.33k
  
case Feature_HasAESBit: return "aes"0
;
566
2.33k
  
case Feature_HasCryptoBit: return "crypto"105
;
567
2.33k
  
case Feature_HasDotProdBit: return "dotprod"64
;
568
2.33k
  
case Feature_HasCRCBit: return "crc"42
;
569
2.33k
  
case Feature_HasRASBit: return "ras"0
;
570
2.33k
  
case Feature_HasFP16Bit: return "half-float conversions"4
;
571
2.33k
  
case Feature_HasFullFP16Bit: return "full half-float"384
;
572
2.33k
  
case Feature_HasFP16FMLBit: return "full half-float fml"80
;
573
2.33k
  
case Feature_HasDivideInThumbBit: return "divide in THUMB"11
;
574
2.33k
  
case Feature_HasDivideInARMBit: return "divide in ARM"11
;
575
2.33k
  
case Feature_HasDSPBit: return "dsp"12
;
576
2.33k
  
case Feature_HasDBBit: return "data-barriers"5
;
577
2.33k
  
case Feature_HasDFBBit: return "full-data-barrier"2
;
578
2.33k
  
case Feature_HasV7ClrexBit: return "v7 clrex"2
;
579
2.33k
  
case Feature_HasAcquireReleaseBit: return "acquire/release"28
;
580
2.33k
  
case Feature_HasMPBit: return "mp-extensions"13
;
581
2.33k
  
case Feature_HasVirtualizationBit: return "virtualization-extensions"0
;
582
2.33k
  
case Feature_HasTrustZoneBit: return "TrustZone"11
;
583
2.33k
  
case Feature_Has8MSecExtBit: return "ARMv8-M Security Extensions"0
;
584
2.33k
  
case Feature_IsThumbBit: return "thumb"5
;
585
2.33k
  
case Feature_IsThumb2Bit: return "thumb2"93
;
586
2.33k
  
case Feature_IsMClassBit: return "armv*m"0
;
587
2.33k
  
case Feature_IsNotMClassBit: return "!armv*m"22
;
588
2.33k
  
case Feature_IsARMBit: return "arm-mode"96
;
589
2.33k
  
case Feature_UseNaClTrapBit: return "NaCl"0
;
590
2.33k
  
case Feature_UseNegativeImmediatesBit: return "NegativeImmediates"53
;
591
2.33k
  
case Feature_HasSBBit: return "sb"2
;
592
2.33k
  
default: return "(unknown)"0
;
593
2.33k
  }
594
2.33k
}
595
596
#endif // GET_SUBTARGET_FEATURE_NAME
597
598
599
#ifdef GET_MATCHER_IMPLEMENTATION
600
#undef GET_MATCHER_IMPLEMENTATION
601
602
69.8k
static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
603
69.8k
  switch (VariantID) {
604
69.8k
    case 0:
605
69.8k
    break;
606
69.8k
  }
607
69.8k
  switch (Mnemonic.size()) {
608
69.8k
  
default: break13.4k
;
609
69.8k
  case 3:  // 4 strings to match.
610
23.0k
    switch (Mnemonic[0]) {
611
23.0k
    
default: break19.6k
;
612
23.0k
    case 'r':  // 1 string to match.
613
650
      if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
614
646
        break;
615
4
      Mnemonic = "rfeia";  // "rfe"
616
4
      return;
617
2.77k
    case 's':  // 3 strings to match.
618
2.77k
      switch (Mnemonic[1]) {
619
2.77k
      
default: break2.69k
;
620
2.77k
      case 'm':  // 1 string to match.
621
39
        if (Mnemonic[2] != 'i')
622
36
          break;
623
3
        Mnemonic = "smc";  // "smi"
624
3
        return;
625
16
      case 'r':  // 1 string to match.
626
16
        if (Mnemonic[2] != 's')
627
0
          break;
628
16
        Mnemonic = "srsia";  // "srs"
629
16
        return;
630
18
      case 'w':  // 1 string to match.
631
18
        if (Mnemonic[2] != 'i')
632
16
          break;
633
2
        Mnemonic = "svc";  // "swi"
634
2
        return;
635
2.75k
      }
636
2.75k
      break;
637
23.0k
    }
638
23.0k
    break;
639
23.0k
  case 4:  // 10 strings to match.
640
13.1k
    switch (Mnemonic[0]) {
641
13.1k
    
default: break6.90k
;
642
13.1k
    case 'f':  // 8 strings to match.
643
9
      switch (Mnemonic[1]) {
644
9
      default: break;
645
9
      case 'l':  // 2 strings to match.
646
0
        if (Mnemonic[2] != 'd')
647
0
          break;
648
0
        switch (Mnemonic[3]) {
649
0
        default: break;
650
0
        case 'd':  // 1 string to match.
651
0
          if (Features.test(Feature_HasVFP2Bit))  // "fldd"
652
0
            Mnemonic = "vldr";
653
0
          return;
654
0
        case 's':  // 1 string to match.
655
0
          if (Features.test(Feature_HasVFP2Bit))  // "flds"
656
0
            Mnemonic = "vldr";
657
0
          return;
658
0
        }
659
0
        break;
660
0
      case 'm':  // 4 strings to match.
661
0
        switch (Mnemonic[2]) {
662
0
        default: break;
663
0
        case 'r':  // 2 strings to match.
664
0
          switch (Mnemonic[3]) {
665
0
          default: break;
666
0
          case 's':  // 1 string to match.
667
0
            if (Features.test(Feature_HasVFP2Bit))  // "fmrs"
668
0
              Mnemonic = "vmov";
669
0
            return;
670
0
          case 'x':  // 1 string to match.
671
0
            if (Features.test(Feature_HasVFP2Bit))  // "fmrx"
672
0
              Mnemonic = "vmrs";
673
0
            return;
674
0
          }
675
0
          break;
676
0
        case 's':  // 1 string to match.
677
0
          if (Mnemonic[3] != 'r')
678
0
            break;
679
0
          if (Features.test(Feature_HasVFP2Bit))  // "fmsr"
680
0
            Mnemonic = "vmov";
681
0
          return;
682
0
        case 'x':  // 1 string to match.
683
0
          if (Mnemonic[3] != 'r')
684
0
            break;
685
0
          if (Features.test(Feature_HasVFP2Bit))  // "fmxr"
686
0
            Mnemonic = "vmsr";
687
0
          return;
688
0
        }
689
0
        break;
690
0
      case 's':  // 2 strings to match.
691
0
        if (Mnemonic[2] != 't')
692
0
          break;
693
0
        switch (Mnemonic[3]) {
694
0
        default: break;
695
0
        case 'd':  // 1 string to match.
696
0
          if (Features.test(Feature_HasVFP2Bit))  // "fstd"
697
0
            Mnemonic = "vstr";
698
0
          return;
699
0
        case 's':  // 1 string to match.
700
0
          if (Features.test(Feature_HasVFP2Bit))  // "fsts"
701
0
            Mnemonic = "vstr";
702
0
          return;
703
0
        }
704
0
        break;
705
9
      }
706
9
      break;
707
6.20k
    case 'v':  // 2 strings to match.
708
6.20k
      switch (Mnemonic[1]) {
709
6.20k
      
default: break2.92k
;
710
6.20k
      case 'l':  // 1 string to match.
711
1.76k
        if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
712
1.75k
          break;
713
12
        Mnemonic = "vldmia";   // "vldm"
714
12
        return;
715
1.51k
      case 's':  // 1 string to match.
716
1.51k
        if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
717
1.49k
          break;
718
13
        Mnemonic = "vstmia";   // "vstm"
719
13
        return;
720
6.17k
      }
721
6.17k
      break;
722
13.0k
    }
723
13.0k
    break;
724
13.0k
  case 5:  // 51 strings to match.
725
7.28k
    switch (Mnemonic[0]) {
726
7.28k
    
default: break2.24k
;
727
7.28k
    case 'f':  // 18 strings to match.
728
0
      switch (Mnemonic[1]) {
729
0
      default: break;
730
0
      case 'a':  // 2 strings to match.
731
0
        if (memcmp(Mnemonic.data()+2, "dd", 2) != 0)
732
0
          break;
733
0
        switch (Mnemonic[4]) {
734
0
        default: break;
735
0
        case 'd':  // 1 string to match.
736
0
          if (Features.test(Feature_HasVFP2Bit))  // "faddd"
737
0
            Mnemonic = "vadd.f64";
738
0
          return;
739
0
        case 's':  // 1 string to match.
740
0
          if (Features.test(Feature_HasVFP2Bit))  // "fadds"
741
0
            Mnemonic = "vadd.f32";
742
0
          return;
743
0
        }
744
0
        break;
745
0
      case 'c':  // 4 strings to match.
746
0
        switch (Mnemonic[2]) {
747
0
        default: break;
748
0
        case 'm':  // 2 strings to match.
749
0
          if (Mnemonic[3] != 'p')
750
0
            break;
751
0
          switch (Mnemonic[4]) {
752
0
          default: break;
753
0
          case 'd':  // 1 string to match.
754
0
            if (Features.test(Feature_HasVFP2Bit))  // "fcmpd"
755
0
              Mnemonic = "vcmp.f64";
756
0
            return;
757
0
          case 's':  // 1 string to match.
758
0
            if (Features.test(Feature_HasVFP2Bit))  // "fcmps"
759
0
              Mnemonic = "vcmp.f32";
760
0
            return;
761
0
          }
762
0
          break;
763
0
        case 'p':  // 2 strings to match.
764
0
          if (Mnemonic[3] != 'y')
765
0
            break;
766
0
          switch (Mnemonic[4]) {
767
0
          default: break;
768
0
          case 'd':  // 1 string to match.
769
0
            if (Features.test(Feature_HasVFP2Bit))  // "fcpyd"
770
0
              Mnemonic = "vmov.f64";
771
0
            return;
772
0
          case 's':  // 1 string to match.
773
0
            if (Features.test(Feature_HasVFP2Bit))  // "fcpys"
774
0
              Mnemonic = "vmov.f32";
775
0
            return;
776
0
          }
777
0
          break;
778
0
        }
779
0
        break;
780
0
      case 'd':  // 2 strings to match.
781
0
        if (memcmp(Mnemonic.data()+2, "iv", 2) != 0)
782
0
          break;
783
0
        switch (Mnemonic[4]) {
784
0
        default: break;
785
0
        case 'd':  // 1 string to match.
786
0
          if (Features.test(Feature_HasVFP2Bit))  // "fdivd"
787
0
            Mnemonic = "vdiv.f64";
788
0
          return;
789
0
        case 's':  // 1 string to match.
790
0
          if (Features.test(Feature_HasVFP2Bit))  // "fdivs"
791
0
            Mnemonic = "vdiv.f32";
792
0
          return;
793
0
        }
794
0
        break;
795
0
      case 'm':  // 8 strings to match.
796
0
        switch (Mnemonic[2]) {
797
0
        default: break;
798
0
        case 'a':  // 2 strings to match.
799
0
          if (Mnemonic[3] != 'c')
800
0
            break;
801
0
          switch (Mnemonic[4]) {
802
0
          default: break;
803
0
          case 'd':  // 1 string to match.
804
0
            if (Features.test(Feature_HasVFP2Bit))  // "fmacd"
805
0
              Mnemonic = "vmla.f64";
806
0
            return;
807
0
          case 's':  // 1 string to match.
808
0
            if (Features.test(Feature_HasVFP2Bit))  // "fmacs"
809
0
              Mnemonic = "vmla.f32";
810
0
            return;
811
0
          }
812
0
          break;
813
0
        case 'd':  // 1 string to match.
814
0
          if (memcmp(Mnemonic.data()+3, "rr", 2) != 0)
815
0
            break;
816
0
          if (Features.test(Feature_HasVFP2Bit))  // "fmdrr"
817
0
            Mnemonic = "vmov";
818
0
          return;
819
0
        case 'r':  // 3 strings to match.
820
0
          switch (Mnemonic[3]) {
821
0
          default: break;
822
0
          case 'd':  // 2 strings to match.
823
0
            switch (Mnemonic[4]) {
824
0
            default: break;
825
0
            case 'd':  // 1 string to match.
826
0
              if (Features.test(Feature_HasVFP2Bit))  // "fmrdd"
827
0
                Mnemonic = "vmov";
828
0
              return;
829
0
            case 's':  // 1 string to match.
830
0
              if (Features.test(Feature_HasVFP2Bit))  // "fmrds"
831
0
                Mnemonic = "vmov";
832
0
              return;
833
0
            }
834
0
            break;
835
0
          case 'r':  // 1 string to match.
836
0
            if (Mnemonic[4] != 'd')
837
0
              break;
838
0
            if (Features.test(Feature_HasVFP2Bit))  // "fmrrd"
839
0
              Mnemonic = "vmov";
840
0
            return;
841
0
          }
842
0
          break;
843
0
        case 'u':  // 2 strings to match.
844
0
          if (Mnemonic[3] != 'l')
845
0
            break;
846
0
          switch (Mnemonic[4]) {
847
0
          default: break;
848
0
          case 'd':  // 1 string to match.
849
0
            if (Features.test(Feature_HasVFP2Bit))  // "fmuld"
850
0
              Mnemonic = "vmul.f64";
851
0
            return;
852
0
          case 's':  // 1 string to match.
853
0
            if (Features.test(Feature_HasVFP2Bit))  // "fmuls"
854
0
              Mnemonic = "vmul.f32";
855
0
            return;
856
0
          }
857
0
          break;
858
0
        }
859
0
        break;
860
0
      case 'n':  // 2 strings to match.
861
0
        if (memcmp(Mnemonic.data()+2, "eg", 2) != 0)
862
0
          break;
863
0
        switch (Mnemonic[4]) {
864
0
        default: break;
865
0
        case 'd':  // 1 string to match.
866
0
          if (Features.test(Feature_HasVFP2Bit))  // "fnegd"
867
0
            Mnemonic = "vneg.f64";
868
0
          return;
869
0
        case 's':  // 1 string to match.
870
0
          if (Features.test(Feature_HasVFP2Bit))  // "fnegs"
871
0
            Mnemonic = "vneg.f32";
872
0
          return;
873
0
        }
874
0
        break;
875
0
      }
876
0
      break;
877
1.38k
    case 'l':  // 3 strings to match.
878
1.38k
      if (memcmp(Mnemonic.data()+1, "dm", 2) != 0)
879
1.16k
        break;
880
217
      switch (Mnemonic[3]) {
881
217
      
default: break131
;
882
217
      case 'e':  // 1 string to match.
883
15
        if (Mnemonic[4] != 'a')
884
13
          break;
885
2
        Mnemonic = "ldmdb";  // "ldmea"
886
2
        return;
887
19
      case 'f':  // 1 string to match.
888
19
        if (Mnemonic[4] != 'd')
889
0
          break;
890
19
        Mnemonic = "ldm";  // "ldmfd"
891
19
        return;
892
52
      case 'i':  // 1 string to match.
893
52
        if (Mnemonic[4] != 'a')
894
24
          break;
895
28
        Mnemonic = "ldm";  // "ldmia"
896
28
        return;
897
168
      }
898
168
      break;
899
207
    case 'r':  // 4 strings to match.
900
207
      if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
901
129
        break;
902
78
      switch (Mnemonic[3]) {
903
78
      
default: break62
;
904
78
      case 'e':  // 2 strings to match.
905
8
        switch (Mnemonic[4]) {
906
8
        
default: break0
;
907
8
        case 'a':  // 1 string to match.
908
4
          Mnemonic = "rfedb";  // "rfeea"
909
4
          return;
910
8
        case 'd':  // 1 string to match.
911
4
          Mnemonic = "rfeib";  // "rfeed"
912
4
          return;
913
0
        }
914
0
        break;
915
8
      case 'f':  // 2 strings to match.
916
8
        switch (Mnemonic[4]) {
917
8
        
default: break0
;
918
8
        case 'a':  // 1 string to match.
919
4
          Mnemonic = "rfeda";  // "rfefa"
920
4
          return;
921
8
        case 'd':  // 1 string to match.
922
4
          Mnemonic = "rfeia";  // "rfefd"
923
4
          return;
924
0
        }
925
0
        break;
926
62
      }
927
62
      break;
928
1.54k
    case 's':  // 7 strings to match.
929
1.54k
      switch (Mnemonic[1]) {
930
1.54k
      
default: break482
;
931
1.54k
      case 'r':  // 4 strings to match.
932
210
        if (Mnemonic[2] != 's')
933
0
          break;
934
210
        switch (Mnemonic[3]) {
935
210
        
default: break162
;
936
210
        case 'e':  // 2 strings to match.
937
24
          switch (Mnemonic[4]) {
938
24
          
default: break0
;
939
24
          case 'a':  // 1 string to match.
940
16
            Mnemonic = "srsia";  // "srsea"
941
16
            return;
942
24
          case 'd':  // 1 string to match.
943
8
            Mnemonic = "srsda";  // "srsed"
944
8
            return;
945
0
          }
946
0
          break;
947
24
        case 'f':  // 2 strings to match.
948
24
          switch (Mnemonic[4]) {
949
24
          
default: break0
;
950
24
          case 'a':  // 1 string to match.
951
8
            Mnemonic = "srsib";  // "srsfa"
952
8
            return;
953
24
          case 'd':  // 1 string to match.
954
16
            Mnemonic = "srsdb";  // "srsfd"
955
16
            return;
956
0
          }
957
0
          break;
958
162
        }
959
162
        break;
960
852
      case 't':  // 3 strings to match.
961
852
        if (Mnemonic[2] != 'm')
962
638
          break;
963
214
        switch (Mnemonic[3]) {
964
214
        
default: break150
;
965
214
        case 'e':  // 1 string to match.
966
4
          if (Mnemonic[4] != 'a')
967
0
            break;
968
4
          Mnemonic = "stm";  // "stmea"
969
4
          return;
970
10
        case 'f':  // 1 string to match.
971
10
          if (Mnemonic[4] != 'd')
972
0
            break;
973
10
          Mnemonic = "stmdb";  // "stmfd"
974
10
          return;
975
50
        case 'i':  // 1 string to match.
976
50
          if (Mnemonic[4] != 'a')
977
32
            break;
978
18
          Mnemonic = "stm";  // "stmia"
979
18
          return;
980
182
        }
981
182
        break;
982
1.46k
      }
983
1.46k
      break;
984
1.90k
    case 'v':  // 19 strings to match.
985
1.90k
      switch (Mnemonic[1]) {
986
1.90k
      
default: break768
;
987
1.90k
      case 'a':  // 3 strings to match.
988
118
        switch (Mnemonic[2]) {
989
118
        
default: break64
;
990
118
        case 'b':  // 1 string to match.
991
24
          if (memcmp(Mnemonic.data()+3, "sq", 2) != 0)
992
24
            break;
993
0
          if (Features.test(Feature_HasNEONBit))  // "vabsq"
994
0
            Mnemonic = "vabs";
995
0
          return;
996
30
        case 'd':  // 1 string to match.
997
30
          if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
998
30
            break;
999
0
          if (Features.test(Feature_HasNEONBit))  // "vaddq"
1000
0
            Mnemonic = "vadd";
1001
0
          return;
1002
0
        case 'n':  // 1 string to match.
1003
0
          if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
1004
0
            break;
1005
0
          if (Features.test(Feature_HasNEONBit))  // "vandq"
1006
0
            Mnemonic = "vand";
1007
0
          return;
1008
118
        }
1009
118
        break;
1010
118
      case 'b':  // 1 string to match.
1011
0
        if (memcmp(Mnemonic.data()+2, "icq", 3) != 0)
1012
0
          break;
1013
0
        if (Features.test(Feature_HasNEONBit))  // "vbicq"
1014
0
          Mnemonic = "vbic";
1015
0
        return;
1016
820
      case 'c':  // 3 strings to match.
1017
820
        switch (Mnemonic[2]) {
1018
820
        
default: break282
;
1019
820
        case 'e':  // 1 string to match.
1020
0
          if (memcmp(Mnemonic.data()+3, "qq", 2) != 0)
1021
0
            break;
1022
0
          if (Features.test(Feature_HasNEONBit))  // "vceqq"
1023
0
            Mnemonic = "vceq";
1024
0
          return;
1025
0
        case 'l':  // 1 string to match.
1026
0
          if (memcmp(Mnemonic.data()+3, "eq", 2) != 0)
1027
0
            break;
1028
0
          if (Features.test(Feature_HasNEONBit))  // "vcleq"
1029
0
            Mnemonic = "vcle";
1030
0
          return;
1031
538
        case 'v':  // 1 string to match.
1032
538
          if (memcmp(Mnemonic.data()+3, "tq", 2) != 0)
1033
538
            break;
1034
0
          if (Features.test(Feature_HasNEONBit))  // "vcvtq"
1035
0
            Mnemonic = "vcvt";
1036
0
          return;
1037
820
        }
1038
820
        break;
1039
820
      case 'e':  // 1 string to match.
1040
0
        if (memcmp(Mnemonic.data()+2, "orq", 3) != 0)
1041
0
          break;
1042
0
        if (Features.test(Feature_HasNEONBit))  // "veorq"
1043
0
          Mnemonic = "veor";
1044
0
        return;
1045
75
      case 'm':  // 5 strings to match.
1046
75
        switch (Mnemonic[2]) {
1047
75
        
default: break26
;
1048
75
        case 'a':  // 1 string to match.
1049
0
          if (memcmp(Mnemonic.data()+3, "xq", 2) != 0)
1050
0
            break;
1051
0
          if (Features.test(Feature_HasNEONBit))  // "vmaxq"
1052
0
            Mnemonic = "vmax";
1053
0
          return;
1054
0
        case 'i':  // 1 string to match.
1055
0
          if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1056
0
            break;
1057
0
          if (Features.test(Feature_HasNEONBit))  // "vminq"
1058
0
            Mnemonic = "vmin";
1059
0
          return;
1060
22
        case 'o':  // 1 string to match.
1061
22
          if (memcmp(Mnemonic.data()+3, "vq", 2) != 0)
1062
22
            break;
1063
0
          if (Features.test(Feature_HasNEONBit))  // "vmovq"
1064
0
            Mnemonic = "vmov";
1065
0
          return;
1066
27
        case 'u':  // 1 string to match.
1067
27
          if (memcmp(Mnemonic.data()+3, "lq", 2) != 0)
1068
27
            break;
1069
0
          if (Features.test(Feature_HasNEONBit))  // "vmulq"
1070
0
            Mnemonic = "vmul";
1071
0
          return;
1072
0
        case 'v':  // 1 string to match.
1073
0
          if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1074
0
            break;
1075
0
          if (Features.test(Feature_HasNEONBit))  // "vmvnq"
1076
0
            Mnemonic = "vmvn";
1077
0
          return;
1078
75
        }
1079
75
        break;
1080
75
      case 'o':  // 1 string to match.
1081
0
        if (memcmp(Mnemonic.data()+2, "rrq", 3) != 0)
1082
0
          break;
1083
0
        if (Features.test(Feature_HasNEONBit))  // "vorrq"
1084
0
          Mnemonic = "vorr";
1085
0
        return;
1086
125
      case 's':  // 4 strings to match.
1087
125
        switch (Mnemonic[2]) {
1088
125
        
default: break83
;
1089
125
        case 'h':  // 2 strings to match.
1090
24
          switch (Mnemonic[3]) {
1091
24
          
default: break0
;
1092
24
          case 'l':  // 1 string to match.
1093
18
            if (Mnemonic[4] != 'q')
1094
18
              break;
1095
0
            if (Features.test(Feature_HasNEONBit))  // "vshlq"
1096
0
              Mnemonic = "vshl";
1097
0
            return;
1098
6
          case 'r':  // 1 string to match.
1099
6
            if (Mnemonic[4] != 'q')
1100
6
              break;
1101
0
            if (Features.test(Feature_HasNEONBit))  // "vshrq"
1102
0
              Mnemonic = "vshr";
1103
0
            return;
1104
24
          }
1105
24
          break;
1106
24
        case 'u':  // 1 string to match.
1107
18
          if (memcmp(Mnemonic.data()+3, "bq", 2) != 0)
1108
18
            break;
1109
0
          if (Features.test(Feature_HasNEONBit))  // "vsubq"
1110
0
            Mnemonic = "vsub";
1111
0
          return;
1112
0
        case 'w':  // 1 string to match.
1113
0
          if (memcmp(Mnemonic.data()+3, "pq", 2) != 0)
1114
0
            break;
1115
0
          if (Features.test(Feature_HasNEONBit))  // "vswpq"
1116
0
            Mnemonic = "vswp";
1117
0
          return;
1118
125
        }
1119
125
        break;
1120
125
      case 'z':  // 1 string to match.
1121
0
        if (memcmp(Mnemonic.data()+2, "ipq", 3) != 0)
1122
0
          break;
1123
0
        if (Features.test(Feature_HasNEONBit))  // "vzipq"
1124
0
          Mnemonic = "vzip";
1125
0
        return;
1126
1.90k
      }
1127
1.90k
      break;
1128
7.13k
    }
1129
7.13k
    break;
1130
7.13k
  case 6:  // 10 strings to match.
1131
4.73k
    if (Mnemonic[0] != 'f')
1132
4.71k
      break;
1133
18
    switch (Mnemonic[1]) {
1134
18
    
default: break16
;
1135
18
    case 's':  // 4 strings to match.
1136
2
      switch (Mnemonic[2]) {
1137
2
      
default: break0
;
1138
2
      case 'i':  // 2 strings to match.
1139
0
        if (memcmp(Mnemonic.data()+3, "to", 2) != 0)
1140
0
          break;
1141
0
        switch (Mnemonic[5]) {
1142
0
        default: break;
1143
0
        case 'd':  // 1 string to match.
1144
0
          if (Features.test(Feature_HasVFP2Bit))  // "fsitod"
1145
0
            Mnemonic = "vcvt.f64.s32";
1146
0
          return;
1147
0
        case 's':  // 1 string to match.
1148
0
          if (Features.test(Feature_HasVFP2Bit))  // "fsitos"
1149
0
            Mnemonic = "vcvt.f32.s32";
1150
0
          return;
1151
0
        }
1152
0
        break;
1153
2
      case 'q':  // 2 strings to match.
1154
2
        if (memcmp(Mnemonic.data()+3, "rt", 2) != 0)
1155
0
          break;
1156
2
        switch (Mnemonic[5]) {
1157
2
        
default: break0
;
1158
2
        case 'd':  // 1 string to match.
1159
1
          if (Features.test(Feature_HasVFP2Bit))  // "fsqrtd"
1160
1
            Mnemonic = "vsqrt";
1161
1
          return;
1162
2
        case 's':  // 1 string to match.
1163
1
          if (Features.test(Feature_HasVFP2Bit))  // "fsqrts"
1164
1
            Mnemonic = "vsqrt";
1165
1
          return;
1166
0
        }
1167
0
        break;
1168
0
      }
1169
0
      break;
1170
0
    case 't':  // 4 strings to match.
1171
0
      if (Mnemonic[2] != 'o')
1172
0
        break;
1173
0
      switch (Mnemonic[3]) {
1174
0
      default: break;
1175
0
      case 's':  // 2 strings to match.
1176
0
        if (Mnemonic[4] != 'i')
1177
0
          break;
1178
0
        switch (Mnemonic[5]) {
1179
0
        default: break;
1180
0
        case 'd':  // 1 string to match.
1181
0
          if (Features.test(Feature_HasVFP2Bit))  // "ftosid"
1182
0
            Mnemonic = "vcvtr.s32.f64";
1183
0
          return;
1184
0
        case 's':  // 1 string to match.
1185
0
          if (Features.test(Feature_HasVFP2Bit))  // "ftosis"
1186
0
            Mnemonic = "vcvtr.s32.f32";
1187
0
          return;
1188
0
        }
1189
0
        break;
1190
0
      case 'u':  // 2 strings to match.
1191
0
        if (Mnemonic[4] != 'i')
1192
0
          break;
1193
0
        switch (Mnemonic[5]) {
1194
0
        default: break;
1195
0
        case 'd':  // 1 string to match.
1196
0
          if (Features.test(Feature_HasVFP2Bit))  // "ftouid"
1197
0
            Mnemonic = "vcvtr.u32.f64";
1198
0
          return;
1199
0
        case 's':  // 1 string to match.
1200
0
          if (Features.test(Feature_HasVFP2Bit))  // "ftouis"
1201
0
            Mnemonic = "vcvtr.u32.f32";
1202
0
          return;
1203
0
        }
1204
0
        break;
1205
0
      }
1206
0
      break;
1207
0
    case 'u':  // 2 strings to match.
1208
0
      if (memcmp(Mnemonic.data()+2, "ito", 3) != 0)
1209
0
        break;
1210
0
      switch (Mnemonic[5]) {
1211
0
      default: break;
1212
0
      case 'd':  // 1 string to match.
1213
0
        if (Features.test(Feature_HasVFP2Bit))  // "fuitod"
1214
0
          Mnemonic = "vcvt.f64.u32";
1215
0
        return;
1216
0
      case 's':  // 1 string to match.
1217
0
        if (Features.test(Feature_HasVFP2Bit))  // "fuitos"
1218
0
          Mnemonic = "vcvt.f32.u32";
1219
0
        return;
1220
0
      }
1221
0
      break;
1222
16
    }
1223
16
    break;
1224
4.32k
  case 7:  // 8 strings to match.
1225
4.32k
    if (Mnemonic[0] != 'f')
1226
4.28k
      break;
1227
46
    switch (Mnemonic[1]) {
1228
46
    
default: break14
;
1229
46
    case 'l':  // 2 strings to match.
1230
12
      if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
1231
0
        break;
1232
12
      switch (Mnemonic[4]) {
1233
12
      
default: break8
;
1234
12
      case 'e':  // 1 string to match.
1235
2
        if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1236
0
          break;
1237
2
        if (Features.test(Feature_HasVFP2Bit))  // "fldmeax"
1238
2
          Mnemonic = "fldmdbx";
1239
2
        return;
1240
2
      case 'f':  // 1 string to match.
1241
2
        if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1242
0
          break;
1243
2
        if (Features.test(Feature_HasVFP2Bit))  // "fldmfdx"
1244
2
          Mnemonic = "fldmiax";
1245
2
        return;
1246
8
      }
1247
8
      break;
1248
20
    case 's':  // 2 strings to match.
1249
20
      if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
1250
0
        break;
1251
20
      switch (Mnemonic[4]) {
1252
20
      
default: break16
;
1253
20
      case 'e':  // 1 string to match.
1254
2
        if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1255
0
          break;
1256
2
        if (Features.test(Feature_HasVFP2Bit))  // "fstmeax"
1257
2
          Mnemonic = "fstmiax";
1258
2
        return;
1259
2
      case 'f':  // 1 string to match.
1260
2
        if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1261
0
          break;
1262
2
        if (Features.test(Feature_HasVFP2Bit))  // "fstmfdx"
1263
2
          Mnemonic = "fstmdbx";
1264
2
        return;
1265
16
      }
1266
16
      break;
1267
16
    case 't':  // 4 strings to match.
1268
0
      if (Mnemonic[2] != 'o')
1269
0
        break;
1270
0
      switch (Mnemonic[3]) {
1271
0
      default: break;
1272
0
      case 's':  // 2 strings to match.
1273
0
        if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1274
0
          break;
1275
0
        switch (Mnemonic[6]) {
1276
0
        default: break;
1277
0
        case 'd':  // 1 string to match.
1278
0
          if (Features.test(Feature_HasVFP2Bit))  // "ftosizd"
1279
0
            Mnemonic = "vcvt.s32.f64";
1280
0
          return;
1281
0
        case 's':  // 1 string to match.
1282
0
          if (Features.test(Feature_HasVFP2Bit))  // "ftosizs"
1283
0
            Mnemonic = "vcvt.s32.f32";
1284
0
          return;
1285
0
        }
1286
0
        break;
1287
0
      case 'u':  // 2 strings to match.
1288
0
        if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1289
0
          break;
1290
0
        switch (Mnemonic[6]) {
1291
0
        default: break;
1292
0
        case 'd':  // 1 string to match.
1293
0
          if (Features.test(Feature_HasVFP2Bit))  // "ftouizd"
1294
0
            Mnemonic = "vcvt.u32.f64";
1295
0
          return;
1296
0
        case 's':  // 1 string to match.
1297
0
          if (Features.test(Feature_HasVFP2Bit))  // "ftouizs"
1298
0
            Mnemonic = "vcvt.u32.f32";
1299
0
          return;
1300
0
        }
1301
0
        break;
1302
0
      }
1303
0
      break;
1304
38
    }
1305
38
    break;
1306
2.43k
  case 8:  // 5 strings to match.
1307
2.43k
    switch (Mnemonic[0]) {
1308
2.43k
    
default: break2.06k
;
1309
2.43k
    case 'q':  // 1 string to match.
1310
8
      if (memcmp(Mnemonic.data()+1, "subaddx", 7) != 0)
1311
8
        break;
1312
0
      Mnemonic = "qsax";   // "qsubaddx"
1313
0
      return;
1314
308
    case 's':  // 2 strings to match.
1315
308
      switch (Mnemonic[1]) {
1316
308
      
default: break290
;
1317
308
      case 'a':  // 1 string to match.
1318
10
        if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1319
6
          break;
1320
4
        Mnemonic = "sasx";   // "saddsubx"
1321
4
        return;
1322
8
      case 's':  // 1 string to match.
1323
8
        if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1324
4
          break;
1325
4
        Mnemonic = "ssax";   // "ssubaddx"
1326
4
        return;
1327
300
      }
1328
300
      break;
1329
300
    case 'u':  // 2 strings to match.
1330
49
      switch (Mnemonic[1]) {
1331
49
      
default: break29
;
1332
49
      case 'a':  // 1 string to match.
1333
8
        if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1334
4
          break;
1335
4
        Mnemonic = "uasx";   // "uaddsubx"
1336
4
        return;
1337
12
      case 's':  // 1 string to match.
1338
12
        if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1339
8
          break;
1340
4
        Mnemonic = "usax";   // "usubaddx"
1341
4
        return;
1342
41
      }
1343
41
      break;
1344
2.41k
    }
1345
2.41k
    break;
1346
2.41k
  case 9:  // 8 strings to match.
1347
1.23k
    switch (Mnemonic[0]) {
1348
1.23k
    
default: break87
;
1349
1.23k
    case 's':  // 2 strings to match.
1350
70
      if (Mnemonic[1] != 'h')
1351
32
        break;
1352
38
      switch (Mnemonic[2]) {
1353
38
      
default: break0
;
1354
38
      case 'a':  // 1 string to match.
1355
30
        if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1356
26
          break;
1357
4
        Mnemonic = "shasx";  // "shaddsubx"
1358
4
        return;
1359
8
      case 's':  // 1 string to match.
1360
8
        if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1361
4
          break;
1362
4
        Mnemonic = "shsax";  // "shsubaddx"
1363
4
        return;
1364
30
      }
1365
30
      break;
1366
40
    case 'u':  // 4 strings to match.
1367
40
      switch (Mnemonic[1]) {
1368
40
      
default: break8
;
1369
40
      case 'h':  // 2 strings to match.
1370
16
        switch (Mnemonic[2]) {
1371
16
        
default: break0
;
1372
16
        case 'a':  // 1 string to match.
1373
8
          if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1374
4
            break;
1375
4
          Mnemonic = "uhasx";  // "uhaddsubx"
1376
4
          return;
1377
8
        case 's':  // 1 string to match.
1378
8
          if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1379
4
            break;
1380
4
          Mnemonic = "uhsax";  // "uhsubaddx"
1381
4
          return;
1382
8
        }
1383
8
        break;
1384
16
      case 'q':  // 2 strings to match.
1385
16
        switch (Mnemonic[2]) {
1386
16
        
default: break0
;
1387
16
        case 'a':  // 1 string to match.
1388
8
          if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1389
4
            break;
1390
4
          Mnemonic = "uqasx";  // "uqaddsubx"
1391
4
          return;
1392
8
        case 's':  // 1 string to match.
1393
8
          if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1394
4
            break;
1395
4
          Mnemonic = "uqsax";  // "uqsubaddx"
1396
4
          return;
1397
8
        }
1398
8
        break;
1399
24
      }
1400
24
      break;
1401
1.03k
    case 'v':  // 2 strings to match.
1402
1.03k
      if (memcmp(Mnemonic.data()+1, "movq.f", 6) != 0)
1403
1.03k
        break;
1404
0
      switch (Mnemonic[7]) {
1405
0
      default: break;
1406
0
      case '3':  // 1 string to match.
1407
0
        if (Mnemonic[8] != '2')
1408
0
          break;
1409
0
        if (Features.test(Feature_HasNEONBit))  // "vmovq.f32"
1410
0
          Mnemonic = "vmov.f32";
1411
0
        return;
1412
0
      case '6':  // 1 string to match.
1413
0
        if (Mnemonic[8] != '4')
1414
0
          break;
1415
0
        if (Features.test(Feature_HasNEONBit))  // "vmovq.f64"
1416
0
          Mnemonic = "vmov.f64";
1417
0
        return;
1418
0
      }
1419
0
      break;
1420
1.21k
    }
1421
1.21k
    break;
1422
1.21k
  case 11:   // 2 strings to match.
1423
169
    if (memcmp(Mnemonic.data()+0, "vrecpeq.", 8) != 0)
1424
169
      break;
1425
0
    switch (Mnemonic[8]) {
1426
0
    default: break;
1427
0
    case 'f':  // 1 string to match.
1428
0
      if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
1429
0
        break;
1430
0
      if (Features.test(Feature_HasNEONBit))  // "vrecpeq.f32"
1431
0
        Mnemonic = "vrecpe.f32";
1432
0
      return;
1433
0
    case 'u':  // 1 string to match.
1434
0
      if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
1435
0
        break;
1436
0
      if (Features.test(Feature_HasNEONBit))  // "vrecpeq.u32"
1437
0
        Mnemonic = "vrecpe.u32";
1438
0
      return;
1439
0
    }
1440
0
    break;
1441
69.8k
  }
1442
69.8k
}
1443
1444
enum {
1445
  Tie0_1_1,
1446
  Tie0_2_2,
1447
  Tie0_3_3,
1448
  Tie0_4_4,
1449
  Tie0_4_5,
1450
  Tie1_1_1,
1451
  Tie1_3_3,
1452
  Tie1_4_4,
1453
  Tie2_4_4,
1454
};
1455
1456
static const uint8_t TiedAsmOperandTable[][3] = {
1457
  /* Tie0_1_1 */ { 0, 1, 1 },
1458
  /* Tie0_2_2 */ { 0, 2, 2 },
1459
  /* Tie0_3_3 */ { 0, 3, 3 },
1460
  /* Tie0_4_4 */ { 0, 4, 4 },
1461
  /* Tie0_4_5 */ { 0, 4, 5 },
1462
  /* Tie1_1_1 */ { 1, 1, 1 },
1463
  /* Tie1_3_3 */ { 1, 3, 3 },
1464
  /* Tie1_4_4 */ { 1, 4, 4 },
1465
  /* Tie2_4_4 */ { 2, 4, 4 },
1466
};
1467
1468
namespace {
1469
enum OperatorConversionKind {
1470
  CVT_Done,
1471
  CVT_Reg,
1472
  CVT_Tied,
1473
  CVT_95_Reg,
1474
  CVT_95_addCCOutOperands,
1475
  CVT_95_addCondCodeOperands,
1476
  CVT_95_addRegShiftedRegOperands,
1477
  CVT_95_addModImmOperands,
1478
  CVT_95_addModImmNotOperands,
1479
  CVT_95_addRegShiftedImmOperands,
1480
  CVT_95_addImmOperands,
1481
  CVT_95_addT2SOImmNotOperands,
1482
  CVT_95_addImm0_95_508s4Operands,
1483
  CVT_regSP,
1484
  CVT_95_addImm0_95_508s4NegOperands,
1485
  CVT_95_addImm0_95_4095NegOperands,
1486
  CVT_95_addThumbModImmNeg8_95_255Operands,
1487
  CVT_95_addT2SOImmNegOperands,
1488
  CVT_95_addModImmNegOperands,
1489
  CVT_95_addImm0_95_1020s4Operands,
1490
  CVT_95_addThumbModImmNeg1_95_7Operands,
1491
  CVT_95_addUnsignedOffset_95_b8s2Operands,
1492
  CVT_95_addAdrLabelOperands,
1493
  CVT_95_addARMBranchTargetOperands,
1494
  CVT_cvtThumbBranches,
1495
  CVT_95_addBitfieldOperands,
1496
  CVT_imm_95_0,
1497
  CVT_95_addThumbBranchTargetOperands,
1498
  CVT_95_addCoprocNumOperands,
1499
  CVT_95_addCoprocRegOperands,
1500
  CVT_95_addProcIFlagsOperands,
1501
  CVT_imm_95_20,
1502
  CVT_imm_95_12,
1503
  CVT_imm_95_15,
1504
  CVT_95_addMemBarrierOptOperands,
1505
  CVT_imm_95_16,
1506
  CVT_95_addFPImmOperands,
1507
  CVT_95_addDPRRegListOperands,
1508
  CVT_imm_95_1,
1509
  CVT_95_addInstSyncBarrierOptOperands,
1510
  CVT_95_addITCondCodeOperands,
1511
  CVT_95_addITMaskOperands,
1512
  CVT_95_addMemNoOffsetOperands,
1513
  CVT_95_addAddrMode5Operands,
1514
  CVT_95_addCoprocOptionOperands,
1515
  CVT_95_addPostIdxImm8s4Operands,
1516
  CVT_95_addRegListOperands,
1517
  CVT_95_addThumbMemPCOperands,
1518
  CVT_95_addConstPoolAsmImmOperands,
1519
  CVT_95_addMemThumbRIs4Operands,
1520
  CVT_95_addMemThumbRROperands,
1521
  CVT_95_addMemThumbSPIOperands,
1522
  CVT_95_addMemImm12OffsetOperands,
1523
  CVT_95_addMemNegImm8OffsetOperands,
1524
  CVT_95_addMemRegOffsetOperands,
1525
  CVT_95_addMemUImm12OffsetOperands,
1526
  CVT_95_addT2MemRegOffsetOperands,
1527
  CVT_95_addMemPCRelImm12Operands,
1528
  CVT_95_addMemImm8OffsetOperands,
1529
  CVT_95_addAM2OffsetImmOperands,
1530
  CVT_95_addPostIdxRegShiftedOperands,
1531
  CVT_95_addMemThumbRIs1Operands,
1532
  CVT_95_addMemPosImm8OffsetOperands,
1533
  CVT_95_addMemImm8s4OffsetOperands,
1534
  CVT_95_addAddrMode3Operands,
1535
  CVT_95_addAM3OffsetOperands,
1536
  CVT_95_addMemImm0_95_1020s4OffsetOperands,
1537
  CVT_95_addMemThumbRIs2Operands,
1538
  CVT_95_addPostIdxRegOperands,
1539
  CVT_95_addPostIdxImm8Operands,
1540
  CVT_reg0,
1541
  CVT_regCPSR,
1542
  CVT_imm_95_14,
1543
  CVT_95_addBankedRegOperands,
1544
  CVT_95_addMSRMaskOperands,
1545
  CVT_cvtThumbMultiply,
1546
  CVT_regR8,
1547
  CVT_regR0,
1548
  CVT_95_addPKHASRImmOperands,
1549
  CVT_imm_95_4,
1550
  CVT_95_addImm1_95_32Operands,
1551
  CVT_imm_95_5,
1552
  CVT_95_addShifterImmOperands,
1553
  CVT_95_addImm1_95_16Operands,
1554
  CVT_95_addRotImmOperands,
1555
  CVT_95_addMemTBBOperands,
1556
  CVT_95_addMemTBHOperands,
1557
  CVT_95_addTraceSyncBarrierOptOperands,
1558
  CVT_95_addNEONi16splatNotOperands,
1559
  CVT_95_addNEONi32splatNotOperands,
1560
  CVT_95_addNEONi16splatOperands,
1561
  CVT_95_addNEONi32splatOperands,
1562
  CVT_95_addComplexRotationOddOperands,
1563
  CVT_95_addComplexRotationEvenOperands,
1564
  CVT_95_addVectorIndex64Operands,
1565
  CVT_95_addVectorIndex32Operands,
1566
  CVT_95_addFBits16Operands,
1567
  CVT_95_addFBits32Operands,
1568
  CVT_95_addVectorIndex16Operands,
1569
  CVT_95_addVectorIndex8Operands,
1570
  CVT_95_addVecListOperands,
1571
  CVT_95_addDupAlignedMemory16Operands,
1572
  CVT_95_addAlignedMemory64or128Operands,
1573
  CVT_95_addAlignedMemory64or128or256Operands,
1574
  CVT_95_addAlignedMemory64Operands,
1575
  CVT_95_addVecListIndexedOperands,
1576
  CVT_95_addAlignedMemory16Operands,
1577
  CVT_95_addDupAlignedMemory32Operands,
1578
  CVT_95_addAlignedMemory32Operands,
1579
  CVT_95_addDupAlignedMemoryNoneOperands,
1580
  CVT_95_addAlignedMemoryNoneOperands,
1581
  CVT_95_addAlignedMemoryOperands,
1582
  CVT_95_addDupAlignedMemory64Operands,
1583
  CVT_95_addDupAlignedMemory64or128Operands,
1584
  CVT_95_addSPRRegListOperands,
1585
  CVT_95_addAddrMode5FP16Operands,
1586
  CVT_95_addNEONi32vmovOperands,
1587
  CVT_95_addNEONvmovi8ReplicateOperands,
1588
  CVT_95_addNEONvmovi16ReplicateOperands,
1589
  CVT_95_addNEONi32vmovNegOperands,
1590
  CVT_95_addNEONvmovi32ReplicateOperands,
1591
  CVT_95_addNEONi64splatOperands,
1592
  CVT_95_addNEONi8splatOperands,
1593
  CVT_95_addNEONinvi8ReplicateOperands,
1594
  CVT_imm_95_2,
1595
  CVT_imm_95_3,
1596
  CVT_NUM_CONVERTERS
1597
};
1598
1599
enum InstructionConversionKind {
1600
  Convert_NoOperands,
1601
  Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1,
1602
  Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
1603
  Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
1604
  Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
1605
  Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
1606
  Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
1607
  Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
1608
  Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
1609
  Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
1610
  Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
1611
  Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0,
1612
  Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0,
1613
  Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0,
1614
  Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
1615
  Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0,
1616
  Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0,
1617
  Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0,
1618
  Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0,
1619
  Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0,
1620
  Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0,
1621
  Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1,
1622
  Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1,
1623
  Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1,
1624
  Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
1625
  Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0,
1626
  Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0,
1627
  Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0,
1628
  Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0,
1629
  Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0,
1630
  Convert__Reg1_1__Imm0_40951_3__CondCode2_0,
1631
  Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0,
1632
  Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0,
1633
  Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0,
1634
  Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
1635
  Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1,
1636
  Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1,
1637
  Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1,
1638
  Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
1639
  Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0,
1640
  Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0,
1641
  Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0,
1642
  Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0,
1643
  Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0,
1644
  Convert__Reg1_1__Imm1_2__CondCode2_0,
1645
  Convert__Reg1_1__AdrLabel1_2__CondCode2_0,
1646
  Convert__Reg1_2__Imm1_3__CondCode2_0,
1647
  Convert__Reg1_1__Tie0_1_1__Reg1_2,
1648
  Convert__Reg1_1__Reg1_2,
1649
  Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
1650
  Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
1651
  Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
1652
  Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
1653
  Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
1654
  Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0,
1655
  Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1,
1656
  Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0,
1657
  Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0,
1658
  Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
1659
  Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1,
1660
  Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
1661
  Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0,
1662
  Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0,
1663
  Convert__ARMBranchTarget1_1__CondCode2_0,
1664
  ConvertCustom_cvtThumbBranches,
1665
  Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0,
1666
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0,
1667
  Convert__imm_95_0,
1668
  Convert__Imm0_2551_0,
1669
  Convert__Imm0_655351_0,
1670
  Convert__ARMBranchTarget1_0,
1671
  Convert__CondCode2_0__ThumbBranchTarget1_1,
1672
  Convert__Reg1_0,
1673
  Convert__ThumbBranchTarget1_0,
1674
  Convert__Reg1_1__CondCode2_0,
1675
  Convert__CondCode2_0__Reg1_1,
1676
  Convert__CondCode2_0__ARMBranchTarget1_1,
1677
  Convert__CondCode2_0,
1678
  Convert__Reg1_0__ThumbBranchTarget1_1,
1679
  Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
1680
  Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
1681
  Convert__Reg1_1__Reg1_2__CondCode2_0,
1682
  Convert__Reg1_1__ModImmNeg1_2__CondCode2_0,
1683
  Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0,
1684
  Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0,
1685
  Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0,
1686
  Convert__Reg1_1__T2SOImm1_2__CondCode2_0,
1687
  Convert__Reg1_1__ModImm1_2__CondCode2_0,
1688
  Convert__Reg1_2__Reg1_3__CondCode2_0,
1689
  Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0,
1690
  Convert__Reg1_2__T2SOImm1_3__CondCode2_0,
1691
  Convert__Reg1_1__Imm0_2551_2__CondCode2_0,
1692
  Convert__Imm0_311_0,
1693
  Convert__Imm0_311_1,
1694
  Convert__Imm1_0__ProcIFlags1_1,
1695
  Convert__Imm1_0__ProcIFlags1_2,
1696
  Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2,
1697
  Convert__Imm1_0__ProcIFlags1_1__Imm1_2,
1698
  Convert__Imm1_0__ProcIFlags1_2__Imm1_3,
1699
  Convert__Reg1_0__Reg1_1__Reg1_2,
1700
  Convert__imm_95_20__CondCode2_0,
1701
  Convert__Imm0_151_1__CondCode2_0,
1702
  Convert__imm_95_12,
1703
  Convert__imm_95_12__CondCode2_0,
1704
  Convert__imm_95_15,
1705
  Convert__imm_95_15__CondCode2_0,
1706
  Convert__MemBarrierOpt1_0,
1707
  Convert__MemBarrierOpt1_1__CondCode2_0,
1708
  Convert__imm_95_0__CondCode2_0,
1709
  Convert__imm_95_16__CondCode2_0,
1710
  Convert__Reg1_1__FPImm1_2__CondCode2_0,
1711
  Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3,
1712
  Convert__Reg1_1__CondCode2_0__DPRRegList1_2,
1713
  Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0,
1714
  Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0,
1715
  Convert__Imm0_2391_1__CondCode2_0,
1716
  Convert__Imm0_2391_2__CondCode2_0,
1717
  Convert__Imm0_631_0,
1718
  Convert__Imm0_655351_1,
1719
  Convert__InstSyncBarrierOpt1_0,
1720
  Convert__InstSyncBarrierOpt1_1__CondCode2_0,
1721
  Convert__ITCondCode1_1__ITMask1_0,
1722
  Convert__Reg1_1__MemNoOffset1_2__CondCode2_0,
1723
  Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0,
1724
  Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0,
1725
  Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0,
1726
  Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0,
1727
  Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2,
1728
  Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3,
1729
  Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3,
1730
  Convert__Reg1_1__CondCode2_0__RegList1_2,
1731
  Convert__Reg1_2__CondCode2_0__RegList1_3,
1732
  Convert__Reg1_1__CondCode2_0__RegList1_3,
1733
  Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3,
1734
  Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4,
1735
  Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0,
1736
  Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0,
1737
  Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0,
1738
  Convert__Reg1_1__MemThumbRR2_2__CondCode2_0,
1739
  Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0,
1740
  Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0,
1741
  Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0,
1742
  Convert__Reg1_1__MemRegOffset3_2__CondCode2_0,
1743
  Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0,
1744
  Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0,
1745
  Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0,
1746
  Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0,
1747
  Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0,
1748
  Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0,
1749
  Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0,
1750
  Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0,
1751
  Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0,
1752
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0,
1753
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0,
1754
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0,
1755
  Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0,
1756
  Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0,
1757
  Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0,
1758
  Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
1759
  Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
1760
  Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0,
1761
  Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0,
1762
  Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0,
1763
  Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0,
1764
  Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0,
1765
  Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0,
1766
  Convert__Reg1_1__AddrMode33_2__CondCode2_0,
1767
  Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0,
1768
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0,
1769
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0,
1770
  Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0,
1771
  Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1,
1772
  Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0,
1773
  Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0,
1774
  Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
1775
  Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1,
1776
  Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
1777
  Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
1778
  Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0,
1779
  Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0,
1780
  Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
1781
  Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
1782
  Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
1783
  Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0,
1784
  Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
1785
  Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0,
1786
  Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4,
1787
  Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
1788
  Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
1789
  Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0,
1790
  Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0,
1791
  Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0,
1792
  Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0,
1793
  Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1,
1794
  Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
1795
  Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
1796
  Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
1797
  Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
1798
  Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0,
1799
  Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0,
1800
  Convert__Reg1_2__Reg1_3__CondCode2_0__reg0,
1801
  Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
1802
  Convert__Reg1_0__Reg1_1,
1803
  Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0,
1804
  Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR,
1805
  Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR,
1806
  Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR,
1807
  Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR,
1808
  Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0,
1809
  Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
1810
  Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
1811
  Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0,
1812
  Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
1813
  Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0,
1814
  Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4,
1815
  Convert__Reg1_1__BankedReg1_2__CondCode2_0,
1816
  Convert__Reg1_1__MSRMask1_2__CondCode2_0,
1817
  Convert__BankedReg1_1__Reg1_2__CondCode2_0,
1818
  Convert__MSRMask1_1__Reg1_2__CondCode2_0,
1819
  Convert__MSRMask1_1__ModImm1_2__CondCode2_0,
1820
  Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0,
1821
  ConvertCustom_cvtThumbMultiply,
1822
  Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1,
1823
  Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
1824
  Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
1825
  Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
1826
  Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0,
1827
  Convert__regR8__regR8__imm_95_14__imm_95_0,
1828
  Convert__regR0__regR0__CondCode2_0__reg0,
1829
  Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
1830
  Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0,
1831
  Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0,
1832
  Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0,
1833
  Convert__MemImm12Offset2_0,
1834
  Convert__MemRegOffset3_0,
1835
  Convert__Imm1_1__CondCode2_0,
1836
  Convert__MemNegImm8Offset2_1__CondCode2_0,
1837
  Convert__MemUImm12Offset2_1__CondCode2_0,
1838
  Convert__T2MemRegOffset3_1__CondCode2_0,
1839
  Convert__MemPCRelImm121_1__CondCode2_0,
1840
  Convert__CondCode2_0__RegList1_1,
1841
  Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1,
1842
  Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2,
1843
  Convert__imm_95_4__imm_95_14__imm_95_0,
1844
  Convert__imm_95_4,
1845
  Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0,
1846
  Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0,
1847
  Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0,
1848
  Convert__SetEndImm1_0,
1849
  Convert__Imm0_11_0,
1850
  Convert__imm_95_4__CondCode2_0,
1851
  Convert__imm_95_5__CondCode2_0,
1852
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3,
1853
  Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0,
1854
  Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0,
1855
  Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0,
1856
  Convert__Imm0_311_2,
1857
  Convert__Imm0_311_1__CondCode2_0,
1858
  Convert__Imm0_311_2__CondCode2_0,
1859
  Convert__Imm0_311_3__CondCode2_0,
1860
  Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0,
1861
  Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0,
1862
  Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0,
1863
  Convert__imm_95_0__imm_95_14__imm_95_0,
1864
  Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0,
1865
  Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0,
1866
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0,
1867
  Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0,
1868
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0,
1869
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0,
1870
  Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0,
1871
  Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0,
1872
  Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
1873
  Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0,
1874
  Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
1875
  Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0,
1876
  Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0,
1877
  Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0,
1878
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0,
1879
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0,
1880
  Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0,
1881
  Convert__Imm0_2551_3__CondCode2_0,
1882
  Convert__Imm0_2551_1__CondCode2_0,
1883
  Convert__Imm24bit1_1__CondCode2_0,
1884
  Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
1885
  Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0,
1886
  Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
1887
  Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0,
1888
  Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
1889
  Convert__MemTBB2_1__CondCode2_0,
1890
  Convert__MemTBH2_1__CondCode2_0,
1891
  Convert__TraceSyncBarrierOpt1_0,
1892
  Convert__TraceSyncBarrierOpt1_1__CondCode2_0,
1893
  Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0,
1894
  Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0,
1895
  Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0,
1896
  Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0,
1897
  Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0,
1898
  Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
1899
  Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0,
1900
  Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0,
1901
  Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0,
1902
  Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0,
1903
  Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0,
1904
  Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0,
1905
  Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0,
1906
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0,
1907
  Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0,
1908
  Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4,
1909
  Convert__Reg1_2__Reg1_2__CondCode2_0,
1910
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4,
1911
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5,
1912
  Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5,
1913
  Convert__Reg1_2__CondCode2_0,
1914
  Convert__Reg1_3__Reg1_4__CondCode2_0,
1915
  Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0,
1916
  Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0,
1917
  Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0,
1918
  Convert__Reg1_2__Reg1_3,
1919
  Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
1920
  Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
1921
  Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0,
1922
  Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0,
1923
  Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0,
1924
  Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0,
1925
  Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0,
1926
  Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0,
1927
  Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0,
1928
  Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0,
1929
  Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0,
1930
  Convert__Reg1_1__Reg1_2__Reg1_3,
1931
  Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4,
1932
  Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4,
1933
  Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
1934
  Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0,
1935
  Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0,
1936
  Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
1937
  Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0,
1938
  Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0,
1939
  Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0,
1940
  Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
1941
  Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
1942
  Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
1943
  Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
1944
  Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
1945
  Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
1946
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
1947
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
1948
  Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
1949
  Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
1950
  Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0,
1951
  Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
1952
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
1953
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
1954
  Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
1955
  Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
1956
  Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
1957
  Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
1958
  Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
1959
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
1960
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
1961
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
1962
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
1963
  Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
1964
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
1965
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
1966
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
1967
  Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
1968
  Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
1969
  Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0,
1970
  Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
1971
  Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
1972
  Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
1973
  Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0,
1974
  Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
1975
  Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
1976
  Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
1977
  Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
1978
  Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
1979
  Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
1980
  Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
1981
  Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0,
1982
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
1983
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
1984
  Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
1985
  Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
1986
  Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
1987
  Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
1988
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
1989
  Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
1990
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
1991
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
1992
  Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
1993
  Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
1994
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
1995
  Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
1996
  Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
1997
  Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
1998
  Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
1999
  Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2000
  Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0,
2001
  Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2002
  Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2003
  Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2004
  Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2005
  Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2006
  Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2007
  Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2008
  Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2009
  Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2010
  Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2011
  Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2012
  Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2013
  Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2014
  Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0,
2015
  Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0,
2016
  Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0,
2017
  Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0,
2018
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2019
  Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2020
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2021
  Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0,
2022
  Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2023
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2024
  Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2025
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2026
  Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2027
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2028
  Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0,
2029
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2030
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2031
  Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2032
  Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2033
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2034
  Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2035
  Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2036
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2037
  Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2038
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2039
  Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2040
  Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2041
  Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2042
  Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2043
  Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0,
2044
  Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0,
2045
  Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0,
2046
  Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0,
2047
  Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3,
2048
  Convert__Reg1_1__CondCode2_0__SPRRegList1_2,
2049
  Convert__Reg1_1__AddrMode52_2__CondCode2_0,
2050
  Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0,
2051
  Convert__Reg1_2__AddrMode52_3__CondCode2_0,
2052
  Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2053
  Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2054
  Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0,
2055
  Convert__Reg1_2__FPImm1_3__CondCode2_0,
2056
  Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0,
2057
  Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0,
2058
  Convert__Reg1_2__NEONi16splat1_3__CondCode2_0,
2059
  Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0,
2060
  Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0,
2061
  Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0,
2062
  Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0,
2063
  Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0,
2064
  Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0,
2065
  Convert__Reg1_2__NEONi64splat1_3__CondCode2_0,
2066
  Convert__Reg1_2__NEONi8splat1_3__CondCode2_0,
2067
  Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0,
2068
  Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0,
2069
  Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0,
2070
  Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0,
2071
  Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
2072
  Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
2073
  Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2074
  Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2075
  Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0,
2076
  Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0,
2077
  Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0,
2078
  Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0,
2079
  Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1,
2080
  Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1,
2081
  Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2,
2082
  Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2,
2083
  Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0,
2084
  Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0,
2085
  Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0,
2086
  Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0,
2087
  Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0,
2088
  Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0,
2089
  Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0,
2090
  Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0,
2091
  Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0,
2092
  Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0,
2093
  Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0,
2094
  Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0,
2095
  Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0,
2096
  Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0,
2097
  Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0,
2098
  Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0,
2099
  Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0,
2100
  Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0,
2101
  Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3,
2102
  Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4,
2103
  Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0,
2104
  Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0,
2105
  Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0,
2106
  Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0,
2107
  Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0,
2108
  Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0,
2109
  Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0,
2110
  Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0,
2111
  Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
2112
  Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
2113
  Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
2114
  Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
2115
  Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
2116
  Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0,
2117
  Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
2118
  Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0,
2119
  Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
2120
  Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0,
2121
  Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
2122
  Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0,
2123
  Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0,
2124
  Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
2125
  Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
2126
  Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0,
2127
  Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
2128
  Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
2129
  Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0,
2130
  Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
2131
  Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
2132
  Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
2133
  Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
2134
  Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0,
2135
  Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0,
2136
  Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0,
2137
  Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0,
2138
  Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0,
2139
  Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0,
2140
  Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0,
2141
  Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0,
2142
  Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0,
2143
  Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0,
2144
  Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0,
2145
  Convert__imm_95_2__CondCode2_0,
2146
  Convert__imm_95_3__CondCode2_0,
2147
  Convert__imm_95_1__CondCode2_0,
2148
  CVT_NUM_SIGNATURES
2149
};
2150
2151
} // end anonymous namespace
2152
2153
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][17] = {
2154
  // Convert_NoOperands
2155
  { CVT_Done },
2156
  // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1
2157
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2158
  // Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
2159
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2160
  // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
2161
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2162
  // Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
2163
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2164
  // Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
2165
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2166
  // Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
2167
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2168
  // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
2169
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2170
  // Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
2171
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2172
  // Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
2173
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2174
  // Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
2175
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2176
  // Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0
2177
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedRegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2178
  // Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0
2179
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2180
  // Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0
2181
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2182
  // Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
2183
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2184
  // Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0
2185
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addRegShiftedImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2186
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0
2187
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2188
  // Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0
2189
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2190
  // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0
2191
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2192
  // Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0
2193
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2194
  // Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0
2195
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_4095NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2196
  // Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1
2197
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2198
  // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1
2199
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2200
  // Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1
2201
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addThumbModImmNeg8_95_255Operands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2202
  // Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
2203
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2204
  // Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0
2205
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2206
  // Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0
2207
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2208
  // Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0
2209
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2210
  // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0
2211
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2212
  // Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0
2213
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_1020s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2214
  // Convert__Reg1_1__Imm0_40951_3__CondCode2_0
2215
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2216
  // Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0
2217
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2218
  // Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0
2219
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_4095NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2220
  // Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0
2221
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2222
  // Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
2223
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2224
  // Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1
2225
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2226
  // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1
2227
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2228
  // Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1
2229
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addThumbModImmNeg1_95_7Operands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2230
  // Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
2231
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2232
  // Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0
2233
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2234
  // Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0
2235
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2236
  // Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0
2237
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNegOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2238
  // Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0
2239
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2240
  // Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0
2241
  { CVT_95_Reg, 2, CVT_95_addUnsignedOffset_95_b8s2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2242
  // Convert__Reg1_1__Imm1_2__CondCode2_0
2243
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2244
  // Convert__Reg1_1__AdrLabel1_2__CondCode2_0
2245
  { CVT_95_Reg, 2, CVT_95_addAdrLabelOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2246
  // Convert__Reg1_2__Imm1_3__CondCode2_0
2247
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2248
  // Convert__Reg1_1__Tie0_1_1__Reg1_2
2249
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_Done },
2250
  // Convert__Reg1_1__Reg1_2
2251
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2252
  // Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
2253
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2254
  // Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
2255
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2256
  // Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
2257
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2258
  // Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
2259
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2260
  // Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
2261
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2262
  // Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0
2263
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNotOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2264
  // Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1
2265
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2266
  // Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0
2267
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2268
  // Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0
2269
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2270
  // Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
2271
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2272
  // Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1
2273
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2274
  // Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
2275
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2276
  // Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0
2277
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2278
  // Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0
2279
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2280
  // Convert__ARMBranchTarget1_1__CondCode2_0
2281
  { CVT_95_addARMBranchTargetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2282
  // ConvertCustom_cvtThumbBranches
2283
  { CVT_cvtThumbBranches, 0, CVT_Done },
2284
  // Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0
2285
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addBitfieldOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2286
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0
2287
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addBitfieldOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2288
  // Convert__imm_95_0
2289
  { CVT_imm_95_0, 0, CVT_Done },
2290
  // Convert__Imm0_2551_0
2291
  { CVT_95_addImmOperands, 1, CVT_Done },
2292
  // Convert__Imm0_655351_0
2293
  { CVT_95_addImmOperands, 1, CVT_Done },
2294
  // Convert__ARMBranchTarget1_0
2295
  { CVT_95_addARMBranchTargetOperands, 1, CVT_Done },
2296
  // Convert__CondCode2_0__ThumbBranchTarget1_1
2297
  { CVT_95_addCondCodeOperands, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
2298
  // Convert__Reg1_0
2299
  { CVT_95_Reg, 1, CVT_Done },
2300
  // Convert__ThumbBranchTarget1_0
2301
  { CVT_95_addThumbBranchTargetOperands, 1, CVT_Done },
2302
  // Convert__Reg1_1__CondCode2_0
2303
  { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2304
  // Convert__CondCode2_0__Reg1_1
2305
  { CVT_95_addCondCodeOperands, 1, CVT_95_Reg, 2, CVT_Done },
2306
  // Convert__CondCode2_0__ARMBranchTarget1_1
2307
  { CVT_95_addCondCodeOperands, 1, CVT_95_addARMBranchTargetOperands, 2, CVT_Done },
2308
  // Convert__CondCode2_0
2309
  { CVT_95_addCondCodeOperands, 1, CVT_Done },
2310
  // Convert__Reg1_0__ThumbBranchTarget1_1
2311
  { CVT_95_Reg, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
2312
  // Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
2313
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
2314
  // Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
2315
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2316
  // Convert__Reg1_1__Reg1_2__CondCode2_0
2317
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2318
  // Convert__Reg1_1__ModImmNeg1_2__CondCode2_0
2319
  { CVT_95_Reg, 2, CVT_95_addModImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2320
  // Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0
2321
  { CVT_95_Reg, 2, CVT_95_addT2SOImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2322
  // Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0
2323
  { CVT_95_Reg, 2, CVT_95_addRegShiftedImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2324
  // Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0
2325
  { CVT_95_Reg, 2, CVT_95_addRegShiftedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2326
  // Convert__Reg1_1__T2SOImm1_2__CondCode2_0
2327
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2328
  // Convert__Reg1_1__ModImm1_2__CondCode2_0
2329
  { CVT_95_Reg, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2330
  // Convert__Reg1_2__Reg1_3__CondCode2_0
2331
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2332
  // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0
2333
  { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2334
  // Convert__Reg1_2__T2SOImm1_3__CondCode2_0
2335
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2336
  // Convert__Reg1_1__Imm0_2551_2__CondCode2_0
2337
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2338
  // Convert__Imm0_311_0
2339
  { CVT_95_addImmOperands, 1, CVT_Done },
2340
  // Convert__Imm0_311_1
2341
  { CVT_95_addImmOperands, 2, CVT_Done },
2342
  // Convert__Imm1_0__ProcIFlags1_1
2343
  { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_Done },
2344
  // Convert__Imm1_0__ProcIFlags1_2
2345
  { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_Done },
2346
  // Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2
2347
  { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2348
  // Convert__Imm1_0__ProcIFlags1_1__Imm1_2
2349
  { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2350
  // Convert__Imm1_0__ProcIFlags1_2__Imm1_3
2351
  { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2352
  // Convert__Reg1_0__Reg1_1__Reg1_2
2353
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2354
  // Convert__imm_95_20__CondCode2_0
2355
  { CVT_imm_95_20, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2356
  // Convert__Imm0_151_1__CondCode2_0
2357
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2358
  // Convert__imm_95_12
2359
  { CVT_imm_95_12, 0, CVT_Done },
2360
  // Convert__imm_95_12__CondCode2_0
2361
  { CVT_imm_95_12, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2362
  // Convert__imm_95_15
2363
  { CVT_imm_95_15, 0, CVT_Done },
2364
  // Convert__imm_95_15__CondCode2_0
2365
  { CVT_imm_95_15, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2366
  // Convert__MemBarrierOpt1_0
2367
  { CVT_95_addMemBarrierOptOperands, 1, CVT_Done },
2368
  // Convert__MemBarrierOpt1_1__CondCode2_0
2369
  { CVT_95_addMemBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2370
  // Convert__imm_95_0__CondCode2_0
2371
  { CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2372
  // Convert__imm_95_16__CondCode2_0
2373
  { CVT_imm_95_16, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2374
  // Convert__Reg1_1__FPImm1_2__CondCode2_0
2375
  { CVT_95_Reg, 2, CVT_95_addFPImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2376
  // Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3
2377
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 4, CVT_Done },
2378
  // Convert__Reg1_1__CondCode2_0__DPRRegList1_2
2379
  { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
2380
  // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0
2381
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2382
  // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0
2383
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2384
  // Convert__Imm0_2391_1__CondCode2_0
2385
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2386
  // Convert__Imm0_2391_2__CondCode2_0
2387
  { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2388
  // Convert__Imm0_631_0
2389
  { CVT_95_addImmOperands, 1, CVT_Done },
2390
  // Convert__Imm0_655351_1
2391
  { CVT_95_addImmOperands, 2, CVT_Done },
2392
  // Convert__InstSyncBarrierOpt1_0
2393
  { CVT_95_addInstSyncBarrierOptOperands, 1, CVT_Done },
2394
  // Convert__InstSyncBarrierOpt1_1__CondCode2_0
2395
  { CVT_95_addInstSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2396
  // Convert__ITCondCode1_1__ITMask1_0
2397
  { CVT_95_addITCondCodeOperands, 2, CVT_95_addITMaskOperands, 1, CVT_Done },
2398
  // Convert__Reg1_1__MemNoOffset1_2__CondCode2_0
2399
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2400
  // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0
2401
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2402
  // Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0
2403
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2404
  // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0
2405
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCoprocOptionOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2406
  // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0
2407
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addPostIdxImm8s4Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2408
  // Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2
2409
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addAddrMode5Operands, 3, CVT_Done },
2410
  // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3
2411
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCoprocOptionOperands, 4, CVT_Done },
2412
  // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3
2413
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addPostIdxImm8s4Operands, 4, CVT_Done },
2414
  // Convert__Reg1_1__CondCode2_0__RegList1_2
2415
  { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done },
2416
  // Convert__Reg1_2__CondCode2_0__RegList1_3
2417
  { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
2418
  // Convert__Reg1_1__CondCode2_0__RegList1_3
2419
  { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
2420
  // Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3
2421
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
2422
  // Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4
2423
  { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 5, CVT_Done },
2424
  // Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0
2425
  { CVT_95_Reg, 2, CVT_95_addThumbMemPCOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2426
  // Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0
2427
  { CVT_95_Reg, 2, CVT_95_addConstPoolAsmImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2428
  // Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0
2429
  { CVT_95_Reg, 2, CVT_95_addMemThumbRIs4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2430
  // Convert__Reg1_1__MemThumbRR2_2__CondCode2_0
2431
  { CVT_95_Reg, 2, CVT_95_addMemThumbRROperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2432
  // Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0
2433
  { CVT_95_Reg, 2, CVT_95_addMemThumbSPIOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2434
  // Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0
2435
  { CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2436
  // Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0
2437
  { CVT_95_Reg, 2, CVT_95_addMemNegImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2438
  // Convert__Reg1_1__MemRegOffset3_2__CondCode2_0
2439
  { CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2440
  // Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0
2441
  { CVT_95_Reg, 2, CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2442
  // Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0
2443
  { CVT_95_Reg, 2, CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2444
  // Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0
2445
  { CVT_95_Reg, 2, CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2446
  // Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0
2447
  { CVT_95_Reg, 3, CVT_95_addConstPoolAsmImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2448
  // Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0
2449
  { CVT_95_Reg, 3, CVT_95_addMemUImm12OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2450
  // Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0
2451
  { CVT_95_Reg, 3, CVT_95_addT2MemRegOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2452
  // Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0
2453
  { CVT_95_Reg, 3, CVT_95_addMemPCRelImm12Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2454
  // Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0
2455
  { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2456
  // Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0
2457
  { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2458
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0
2459
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2460
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0
2461
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2462
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0
2463
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2464
  // Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0
2465
  { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2466
  // Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0
2467
  { CVT_95_Reg, 2, CVT_95_addMemThumbRIs1Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2468
  // Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0
2469
  { CVT_95_Reg, 2, CVT_95_addMemPosImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2470
  // Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
2471
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2472
  // Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
2473
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2474
  // Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0
2475
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2476
  // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0
2477
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2478
  // Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0
2479
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2480
  // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0
2481
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2482
  // Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0
2483
  { CVT_95_Reg, 2, CVT_95_addMemImm0_95_1020s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2484
  // Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0
2485
  { CVT_95_Reg, 2, CVT_95_addMemThumbRIs2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2486
  // Convert__Reg1_1__AddrMode33_2__CondCode2_0
2487
  { CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2488
  // Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0
2489
  { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2490
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0
2491
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2492
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0
2493
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2494
  // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0
2495
  { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2496
  // Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1
2497
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2498
  // Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0
2499
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2500
  // Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0
2501
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2502
  // Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
2503
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2504
  // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1
2505
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2506
  // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
2507
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2508
  // Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
2509
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2510
  // Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0
2511
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2512
  // Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0
2513
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2514
  // Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
2515
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2516
  // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
2517
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2518
  // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
2519
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
2520
  // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0
2521
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
2522
  // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
2523
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2524
  // Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0
2525
  { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2526
  // Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4
2527
  { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_Done },
2528
  // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
2529
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2530
  // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
2531
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2532
  // Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0
2533
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2534
  // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0
2535
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2536
  // Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0
2537
  { CVT_95_Reg, 2, CVT_95_addT2SOImmNotOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2538
  // Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0
2539
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2540
  // Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1
2541
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2542
  // Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
2543
  { CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2544
  // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
2545
  { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2546
  // Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
2547
  { CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2548
  // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
2549
  { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2550
  // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0
2551
  { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2552
  // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0
2553
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2554
  // Convert__Reg1_2__Reg1_3__CondCode2_0__reg0
2555
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2556
  // Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
2557
  { CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2558
  // Convert__Reg1_0__Reg1_1
2559
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
2560
  // Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0
2561
  { CVT_95_Reg, 1, CVT_regCPSR, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2562
  // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR
2563
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2564
  // Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR
2565
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2566
  // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR
2567
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2568
  // Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR
2569
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2570
  // Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0
2571
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2572
  // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
2573
  { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2574
  // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
2575
  { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
2576
  // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0
2577
  { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
2578
  // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
2579
  { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2580
  // Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0
2581
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2582
  // Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4
2583
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 5, CVT_Done },
2584
  // Convert__Reg1_1__BankedReg1_2__CondCode2_0
2585
  { CVT_95_Reg, 2, CVT_95_addBankedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2586
  // Convert__Reg1_1__MSRMask1_2__CondCode2_0
2587
  { CVT_95_Reg, 2, CVT_95_addMSRMaskOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2588
  // Convert__BankedReg1_1__Reg1_2__CondCode2_0
2589
  { CVT_95_addBankedRegOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2590
  // Convert__MSRMask1_1__Reg1_2__CondCode2_0
2591
  { CVT_95_addMSRMaskOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2592
  // Convert__MSRMask1_1__ModImm1_2__CondCode2_0
2593
  { CVT_95_addMSRMaskOperands, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2594
  // Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0
2595
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2596
  // ConvertCustom_cvtThumbMultiply
2597
  { CVT_cvtThumbMultiply, 0, CVT_Done },
2598
  // Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1
2599
  { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2600
  // Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
2601
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2602
  // Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
2603
  { CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2604
  // Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
2605
  { CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2606
  // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0
2607
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2608
  // Convert__regR8__regR8__imm_95_14__imm_95_0
2609
  { CVT_regR8, 0, CVT_regR8, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2610
  // Convert__regR0__regR0__CondCode2_0__reg0
2611
  { CVT_regR0, 0, CVT_regR0, 0, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2612
  // Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
2613
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2614
  // Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0
2615
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2616
  // Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0
2617
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2618
  // Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0
2619
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addPKHASRImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2620
  // Convert__MemImm12Offset2_0
2621
  { CVT_95_addMemImm12OffsetOperands, 1, CVT_Done },
2622
  // Convert__MemRegOffset3_0
2623
  { CVT_95_addMemRegOffsetOperands, 1, CVT_Done },
2624
  // Convert__Imm1_1__CondCode2_0
2625
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2626
  // Convert__MemNegImm8Offset2_1__CondCode2_0
2627
  { CVT_95_addMemNegImm8OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2628
  // Convert__MemUImm12Offset2_1__CondCode2_0
2629
  { CVT_95_addMemUImm12OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2630
  // Convert__T2MemRegOffset3_1__CondCode2_0
2631
  { CVT_95_addT2MemRegOffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2632
  // Convert__MemPCRelImm121_1__CondCode2_0
2633
  { CVT_95_addMemPCRelImm12Operands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2634
  // Convert__CondCode2_0__RegList1_1
2635
  { CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done },
2636
  // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1
2637
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done },
2638
  // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2
2639
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done },
2640
  // Convert__imm_95_4__imm_95_14__imm_95_0
2641
  { CVT_imm_95_4, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2642
  // Convert__imm_95_4
2643
  { CVT_imm_95_4, 0, CVT_Done },
2644
  // Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0
2645
  { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2646
  // Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0
2647
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2648
  // Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0
2649
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addImm1_95_32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2650
  // Convert__SetEndImm1_0
2651
  { CVT_95_addImmOperands, 1, CVT_Done },
2652
  // Convert__Imm0_11_0
2653
  { CVT_95_addImmOperands, 1, CVT_Done },
2654
  // Convert__imm_95_4__CondCode2_0
2655
  { CVT_imm_95_4, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2656
  // Convert__imm_95_5__CondCode2_0
2657
  { CVT_imm_95_5, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2658
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3
2659
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2660
  // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0
2661
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
2662
  // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0
2663
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2664
  // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0
2665
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2666
  // Convert__Imm0_311_2
2667
  { CVT_95_addImmOperands, 3, CVT_Done },
2668
  // Convert__Imm0_311_1__CondCode2_0
2669
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2670
  // Convert__Imm0_311_2__CondCode2_0
2671
  { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2672
  // Convert__Imm0_311_3__CondCode2_0
2673
  { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2674
  // Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0
2675
  { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2676
  // Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0
2677
  { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2678
  // Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0
2679
  { CVT_95_Reg, 2, CVT_95_addImm1_95_16Operands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2680
  // Convert__imm_95_0__imm_95_14__imm_95_0
2681
  { CVT_imm_95_0, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2682
  // Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0
2683
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemNoOffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2684
  // Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0
2685
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2686
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0
2687
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2688
  // Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0
2689
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2690
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0
2691
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2692
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0
2693
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2694
  // Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0
2695
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2696
  // Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0
2697
  { CVT_95_Reg, 2, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2698
  // Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
2699
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2700
  // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0
2701
  { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2702
  // Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
2703
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2704
  // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0
2705
  { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2706
  // Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0
2707
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm0_95_1020s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2708
  // Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0
2709
  { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2710
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0
2711
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2712
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0
2713
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2714
  // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0
2715
  { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2716
  // Convert__Imm0_2551_3__CondCode2_0
2717
  { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2718
  // Convert__Imm0_2551_1__CondCode2_0
2719
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2720
  // Convert__Imm24bit1_1__CondCode2_0
2721
  { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2722
  // Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
2723
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2724
  // Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0
2725
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2726
  // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
2727
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2728
  // Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0
2729
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRotImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2730
  // Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
2731
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2732
  // Convert__MemTBB2_1__CondCode2_0
2733
  { CVT_95_addMemTBBOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2734
  // Convert__MemTBH2_1__CondCode2_0
2735
  { CVT_95_addMemTBHOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2736
  // Convert__TraceSyncBarrierOpt1_0
2737
  { CVT_95_addTraceSyncBarrierOptOperands, 1, CVT_Done },
2738
  // Convert__TraceSyncBarrierOpt1_1__CondCode2_0
2739
  { CVT_95_addTraceSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2740
  // Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0
2741
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2742
  // Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0
2743
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2744
  // Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0
2745
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2746
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0
2747
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2748
  // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0
2749
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2750
  // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
2751
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2752
  // Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0
2753
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2754
  // Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0
2755
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2756
  // Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0
2757
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2758
  // Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0
2759
  { CVT_95_Reg, 3, CVT_95_addNEONi16splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2760
  // Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0
2761
  { CVT_95_Reg, 3, CVT_95_addNEONi32splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2762
  // Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0
2763
  { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
2764
  // Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0
2765
  { CVT_95_Reg, 3, CVT_95_addNEONi32splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
2766
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0
2767
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2768
  // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0
2769
  { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2770
  // Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4
2771
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
2772
  // Convert__Reg1_2__Reg1_2__CondCode2_0
2773
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2774
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4
2775
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
2776
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5
2777
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex64Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
2778
  // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5
2779
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
2780
  // Convert__Reg1_2__CondCode2_0
2781
  { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2782
  // Convert__Reg1_3__Reg1_4__CondCode2_0
2783
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2784
  // Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0
2785
  { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2786
  // Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0
2787
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2788
  // Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0
2789
  { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2790
  // Convert__Reg1_2__Reg1_3
2791
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2792
  // Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
2793
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2794
  // Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
2795
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2796
  // Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0
2797
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex8Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2798
  // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0
2799
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2800
  // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0
2801
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2802
  // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0
2803
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2804
  // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0
2805
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2806
  // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0
2807
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2808
  // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0
2809
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2810
  // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0
2811
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2812
  // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0
2813
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2814
  // Convert__Reg1_1__Reg1_2__Reg1_3
2815
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2816
  // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4
2817
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done },
2818
  // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4
2819
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
2820
  // Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
2821
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2822
  // Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0
2823
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2824
  // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0
2825
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2826
  // Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
2827
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2828
  // Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0
2829
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2830
  // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0
2831
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2832
  // Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0
2833
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2834
  // Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
2835
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2836
  // Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
2837
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2838
  // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0
2839
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2840
  // Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2841
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2842
  // Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2843
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2844
  // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2845
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2846
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
2847
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2848
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
2849
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2850
  // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
2851
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2852
  // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
2853
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2854
  // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0
2855
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2856
  // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
2857
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2858
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
2859
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2860
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
2861
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2862
  // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
2863
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2864
  // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
2865
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2866
  // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
2867
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2868
  // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
2869
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2870
  // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
2871
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2872
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
2873
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2874
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
2875
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2876
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
2877
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2878
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
2879
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2880
  // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
2881
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2882
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
2883
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2884
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2885
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2886
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
2887
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2888
  // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2889
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2890
  // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2891
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2892
  // Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0
2893
  { CVT_95_Reg, 4, CVT_95_addAlignedMemoryOperands, 9, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2894
  // Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
2895
  { CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2896
  // Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
2897
  { CVT_95_Reg, 4, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2898
  // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
2899
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2900
  // Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0
2901
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2902
  // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
2903
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2904
  // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
2905
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2906
  // Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2907
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2908
  // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2909
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2910
  // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0
2911
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2912
  // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0
2913
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2914
  // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
2915
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2916
  // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0
2917
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2918
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
2919
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2920
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
2921
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2922
  // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
2923
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2924
  // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
2925
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2926
  // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
2927
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2928
  // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
2929
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2930
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
2931
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2932
  // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
2933
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2934
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
2935
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2936
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
2937
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2938
  // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2939
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2940
  // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2941
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2942
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
2943
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2944
  // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
2945
  { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2946
  // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
2947
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2948
  // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2949
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2950
  // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2951
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2952
  // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2953
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2954
  // Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0
2955
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2956
  // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2957
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2958
  // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2959
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2960
  // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2961
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2962
  // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2963
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2964
  // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2965
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2966
  // Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2967
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2968
  // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2969
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2970
  // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2971
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2972
  // Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2973
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2974
  // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2975
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2976
  // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2977
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2978
  // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2979
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2980
  // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2981
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2982
  // Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0
2983
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addCondCodeOperands, 1, CVT_Done },
2984
  // Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0
2985
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done },
2986
  // Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0
2987
  { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_addAlignedMemoryOperands, 14, CVT_95_addCondCodeOperands, 1, CVT_Done },
2988
  // Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0
2989
  { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 14, CVT_95_addImmOperands, 15, CVT_95_addCondCodeOperands, 1, CVT_Done },
2990
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2991
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2992
  // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
2993
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2994
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2995
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2996
  // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0
2997
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2998
  // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
2999
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3000
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
3001
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3002
  // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
3003
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3004
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
3005
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3006
  // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
3007
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3008
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3009
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3010
  // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0
3011
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3012
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3013
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3014
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3015
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3016
  // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
3017
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3018
  // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3019
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3020
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3021
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3022
  // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
3023
  { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3024
  // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3025
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3026
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
3027
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3028
  // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3029
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3030
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
3031
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3032
  // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3033
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3034
  // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3035
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3036
  // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3037
  { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3038
  // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3039
  { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3040
  // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0
3041
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done },
3042
  // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0
3043
  { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_addCondCodeOperands, 1, CVT_Done },
3044
  // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0
3045
  { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addCondCodeOperands, 1, CVT_Done },
3046
  // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0
3047
  { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addImmOperands, 18, CVT_95_addCondCodeOperands, 1, CVT_Done },
3048
  // Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3
3049
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 4, CVT_Done },
3050
  // Convert__Reg1_1__CondCode2_0__SPRRegList1_2
3051
  { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
3052
  // Convert__Reg1_1__AddrMode52_2__CondCode2_0
3053
  { CVT_95_Reg, 2, CVT_95_addAddrMode5Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3054
  // Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0
3055
  { CVT_95_Reg, 3, CVT_95_addAddrMode5FP16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3056
  // Convert__Reg1_2__AddrMode52_3__CondCode2_0
3057
  { CVT_95_Reg, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3058
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
3059
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3060
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
3061
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3062
  // Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0
3063
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3064
  // Convert__Reg1_2__FPImm1_3__CondCode2_0
3065
  { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3066
  // Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0
3067
  { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3068
  // Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0
3069
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3070
  // Convert__Reg1_2__NEONi16splat1_3__CondCode2_0
3071
  { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3072
  // Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0
3073
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3074
  // Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0
3075
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3076
  // Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0
3077
  { CVT_95_Reg, 3, CVT_95_addNEONi32vmovNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3078
  // Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0
3079
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3080
  // Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0
3081
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3082
  // Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0
3083
  { CVT_95_Reg, 3, CVT_95_addNEONvmovi32ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3084
  // Convert__Reg1_2__NEONi64splat1_3__CondCode2_0
3085
  { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3086
  // Convert__Reg1_2__NEONi8splat1_3__CondCode2_0
3087
  { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3088
  // Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0
3089
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3090
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0
3091
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3092
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0
3093
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3094
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0
3095
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3096
  // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
3097
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3098
  // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
3099
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3100
  // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
3101
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3102
  // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
3103
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3104
  // Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0
3105
  { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3106
  // Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0
3107
  { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3108
  // Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0
3109
  { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3110
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0
3111
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3112
  // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1
3113
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 2, CVT_Done },
3114
  // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1
3115
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 2, CVT_Done },
3116
  // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2
3117
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
3118
  // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2
3119
  { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
3120
  // Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0
3121
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3122
  // Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0
3123
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3124
  // Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0
3125
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3126
  // Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0
3127
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3128
  // Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0
3129
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3130
  // Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0
3131
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3132
  // Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0
3133
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3134
  // Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0
3135
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3136
  // Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0
3137
  { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3138
  // Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0
3139
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3140
  // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0
3141
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3142
  // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0
3143
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3144
  // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0
3145
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3146
  // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0
3147
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3148
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0
3149
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3150
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0
3151
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3152
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0
3153
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3154
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0
3155
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3156
  // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3
3157
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3158
  // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4
3159
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
3160
  // Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0
3161
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3162
  // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0
3163
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3164
  // Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0
3165
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3166
  // Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0
3167
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3168
  // Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0
3169
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3170
  // Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0
3171
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3172
  // Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0
3173
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3174
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0
3175
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3176
  // Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
3177
  { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3178
  // Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
3179
  { CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3180
  // Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
3181
  { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3182
  // Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
3183
  { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3184
  // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
3185
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3186
  // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0
3187
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3188
  // Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
3189
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3190
  // Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0
3191
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3192
  // Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
3193
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3194
  // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0
3195
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3196
  // Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
3197
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3198
  // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0
3199
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3200
  // Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0
3201
  { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3202
  // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
3203
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3204
  // Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
3205
  { CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3206
  // Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0
3207
  { CVT_imm_95_0, 0, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_addImmOperands, 11, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3208
  // Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
3209
  { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3210
  // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
3211
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3212
  // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0
3213
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3214
  // Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
3215
  { CVT_95_addAlignedMemoryOperands, 8, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3216
  // Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
3217
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3218
  // Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
3219
  { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
3220
  // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
3221
  { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
3222
  // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0
3223
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
3224
  // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0
3225
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3226
  // Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0
3227
  { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3228
  // Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0
3229
  { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3230
  // Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0
3231
  { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3232
  // Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0
3233
  { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3234
  // Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0
3235
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3236
  // Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0
3237
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3238
  // Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0
3239
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3240
  // Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0
3241
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3242
  // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0
3243
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
3244
  // Convert__imm_95_2__CondCode2_0
3245
  { CVT_imm_95_2, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
3246
  // Convert__imm_95_3__CondCode2_0
3247
  { CVT_imm_95_3, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
3248
  // Convert__imm_95_1__CondCode2_0
3249
  { CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
3250
};
3251
3252
void ARMAsmParser::
3253
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
3254
43.2k
                const OperandVector &Operands) {
3255
43.2k
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
3256
43.2k
  const uint8_t *Converter = ConversionTable[Kind];
3257
43.2k
  unsigned OpIdx;
3258
43.2k
  Inst.setOpcode(Opcode);
3259
181k
  for (const uint8_t *p = Converter; *p; 
p+= 2138k
) {
3260
138k
    OpIdx = *(p + 1);
3261
138k
    switch (*p) {
3262
138k
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
3263
138k
    case CVT_Reg:
3264
0
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
3265
0
      break;
3266
138k
    case CVT_Tied: {
3267
3.35k
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
3268
3.35k
                          std::begin(TiedAsmOperandTable)) &&
3269
3.35k
             "Tied operand not found");
3270
3.35k
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
3271
3.35k
      if (TiedResOpnd != (uint8_t) -1)
3272
3.35k
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
3273
3.35k
      break;
3274
138k
    }
3275
138k
    case CVT_95_Reg:
3276
50.2k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
3277
50.2k
      break;
3278
138k
    case CVT_95_addCCOutOperands:
3279
7.22k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addCCOutOperands(Inst, 1);
3280
7.22k
      break;
3281
138k
    case CVT_95_addCondCodeOperands:
3282
32.2k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 2);
3283
32.2k
      break;
3284
138k
    case CVT_95_addRegShiftedRegOperands:
3285
241
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedRegOperands(Inst, 3);
3286
241
      break;
3287
138k
    case CVT_95_addModImmOperands:
3288
1.09k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmOperands(Inst, 1);
3289
1.09k
      break;
3290
138k
    case CVT_95_addModImmNotOperands:
3291
49
      static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNotOperands(Inst, 1);
3292
49
      break;
3293
138k
    case CVT_95_addRegShiftedImmOperands:
3294
2.30k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedImmOperands(Inst, 2);
3295
2.30k
      break;
3296
138k
    case CVT_95_addImmOperands:
3297
5.56k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
3298
5.56k
      break;
3299
138k
    case CVT_95_addT2SOImmNotOperands:
3300
69
      static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNotOperands(Inst, 1);
3301
69
      break;
3302
138k
    case CVT_95_addImm0_95_508s4Operands:
3303
51
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4Operands(Inst, 1);
3304
51
      break;
3305
138k
    case CVT_regSP:
3306
315
      Inst.addOperand(MCOperand::createReg(ARM::SP));
3307
315
      break;
3308
138k
    case CVT_95_addImm0_95_508s4NegOperands:
3309
6
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4NegOperands(Inst, 1);
3310
6
      break;
3311
138k
    case CVT_95_addImm0_95_4095NegOperands:
3312
18
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_4095NegOperands(Inst, 1);
3313
18
      break;
3314
138k
    case CVT_95_addThumbModImmNeg8_95_255Operands:
3315
4
      static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg8_255Operands(Inst, 1);
3316
4
      break;
3317
138k
    case CVT_95_addT2SOImmNegOperands:
3318
67
      static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNegOperands(Inst, 1);
3319
67
      break;
3320
138k
    case CVT_95_addModImmNegOperands:
3321
36
      static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNegOperands(Inst, 1);
3322
36
      break;
3323
138k
    case CVT_95_addImm0_95_1020s4Operands:
3324
41
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_1020s4Operands(Inst, 1);
3325
41
      break;
3326
138k
    case CVT_95_addThumbModImmNeg1_95_7Operands:
3327
4
      static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg1_7Operands(Inst, 1);
3328
4
      break;
3329
138k
    case CVT_95_addUnsignedOffset_95_b8s2Operands:
3330
31
      static_cast<ARMOperand&>(*Operands[OpIdx]).addUnsignedOffset_b8s2Operands(Inst, 1);
3331
31
      break;
3332
138k
    case CVT_95_addAdrLabelOperands:
3333
26
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1);
3334
26
      break;
3335
138k
    case CVT_95_addARMBranchTargetOperands:
3336
1.20k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addARMBranchTargetOperands(Inst, 1);
3337
1.20k
      break;
3338
138k
    case CVT_cvtThumbBranches:
3339
947
      cvtThumbBranches(Inst, Operands);
3340
947
      break;
3341
138k
    case CVT_95_addBitfieldOperands:
3342
45
      static_cast<ARMOperand&>(*Operands[OpIdx]).addBitfieldOperands(Inst, 1);
3343
45
      break;
3344
138k
    case CVT_imm_95_0:
3345
1.44k
      Inst.addOperand(MCOperand::createImm(0));
3346
1.44k
      break;
3347
138k
    case CVT_95_addThumbBranchTargetOperands:
3348
331
      static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbBranchTargetOperands(Inst, 1);
3349
331
      break;
3350
138k
    case CVT_95_addCoprocNumOperands:
3351
1.40k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocNumOperands(Inst, 1);
3352
1.40k
      break;
3353
138k
    case CVT_95_addCoprocRegOperands:
3354
1.52k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocRegOperands(Inst, 1);
3355
1.52k
      break;
3356
138k
    case CVT_95_addProcIFlagsOperands:
3357
71
      static_cast<ARMOperand&>(*Operands[OpIdx]).addProcIFlagsOperands(Inst, 1);
3358
71
      break;
3359
138k
    case CVT_imm_95_20:
3360
8
      Inst.addOperand(MCOperand::createImm(20));
3361
8
      break;
3362
138k
    case CVT_imm_95_12:
3363
4
      Inst.addOperand(MCOperand::createImm(12));
3364
4
      break;
3365
138k
    case CVT_imm_95_15:
3366
549
      Inst.addOperand(MCOperand::createImm(15));
3367
549
      break;
3368
138k
    case CVT_95_addMemBarrierOptOperands:
3369
256
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemBarrierOptOperands(Inst, 1);
3370
256
      break;
3371
138k
    case CVT_imm_95_16:
3372
3
      Inst.addOperand(MCOperand::createImm(16));
3373
3
      break;
3374
138k
    case CVT_95_addFPImmOperands:
3375
39
      static_cast<ARMOperand&>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
3376
39
      break;
3377
138k
    case CVT_95_addDPRRegListOperands:
3378
79
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDPRRegListOperands(Inst, 1);
3379
79
      break;
3380
138k
    case CVT_imm_95_1:
3381
34
      Inst.addOperand(MCOperand::createImm(1));
3382
34
      break;
3383
138k
    case CVT_95_addInstSyncBarrierOptOperands:
3384
18
      static_cast<ARMOperand&>(*Operands[OpIdx]).addInstSyncBarrierOptOperands(Inst, 1);
3385
18
      break;
3386
138k
    case CVT_95_addITCondCodeOperands:
3387
7.43k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addITCondCodeOperands(Inst, 1);
3388
7.43k
      break;
3389
138k
    case CVT_95_addITMaskOperands:
3390
7.43k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addITMaskOperands(Inst, 1);
3391
7.43k
      break;
3392
138k
    case CVT_95_addMemNoOffsetOperands:
3393
1.26k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNoOffsetOperands(Inst, 1);
3394
1.26k
      break;
3395
138k
    case CVT_95_addAddrMode5Operands:
3396
745
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5Operands(Inst, 2);
3397
745
      break;
3398
138k
    case CVT_95_addCoprocOptionOperands:
3399
142
      static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocOptionOperands(Inst, 1);
3400
142
      break;
3401
138k
    case CVT_95_addPostIdxImm8s4Operands:
3402
352
      static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8s4Operands(Inst, 1);
3403
352
      break;
3404
138k
    case CVT_95_addRegListOperands:
3405
1.34k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
3406
1.34k
      break;
3407
138k
    case CVT_95_addThumbMemPCOperands:
3408
50
      static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbMemPCOperands(Inst, 1);
3409
50
      break;
3410
138k
    case CVT_95_addConstPoolAsmImmOperands:
3411
549
      static_cast<ARMOperand&>(*Operands[OpIdx]).addConstPoolAsmImmOperands(Inst, 1);
3412
549
      break;
3413
138k
    case CVT_95_addMemThumbRIs4Operands:
3414
84
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs4Operands(Inst, 2);
3415
84
      break;
3416
138k
    case CVT_95_addMemThumbRROperands:
3417
39
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRROperands(Inst, 2);
3418
39
      break;
3419
138k
    case CVT_95_addMemThumbSPIOperands:
3420
47
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbSPIOperands(Inst, 2);
3421
47
      break;
3422
138k
    case CVT_95_addMemImm12OffsetOperands:
3423
230
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm12OffsetOperands(Inst, 2);
3424
230
      break;
3425
138k
    case CVT_95_addMemNegImm8OffsetOperands:
3426
102
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNegImm8OffsetOperands(Inst, 2);
3427
102
      break;
3428
138k
    case CVT_95_addMemRegOffsetOperands:
3429
90
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemRegOffsetOperands(Inst, 3);
3430
90
      break;
3431
138k
    case CVT_95_addMemUImm12OffsetOperands:
3432
340
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemUImm12OffsetOperands(Inst, 2);
3433
340
      break;
3434
138k
    case CVT_95_addT2MemRegOffsetOperands:
3435
321
      static_cast<ARMOperand&>(*Operands[OpIdx]).addT2MemRegOffsetOperands(Inst, 3);
3436
321
      break;
3437
138k
    case CVT_95_addMemPCRelImm12Operands:
3438
53
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemPCRelImm12Operands(Inst, 1);
3439
53
      break;
3440
138k
    case CVT_95_addMemImm8OffsetOperands:
3441
103
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm8OffsetOperands(Inst, 2);
3442
103
      break;
3443
138k
    case CVT_95_addAM2OffsetImmOperands:
3444
43
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAM2OffsetImmOperands(Inst, 2);
3445
43
      break;
3446
138k
    case CVT_95_addPostIdxRegShiftedOperands:
3447
36
      static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegShiftedOperands(Inst, 2);
3448
36
      break;
3449
138k
    case CVT_95_addMemThumbRIs1Operands:
3450
23
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs1Operands(Inst, 2);
3451
23
      break;
3452
138k
    case CVT_95_addMemPosImm8OffsetOperands:
3453
42
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemPosImm8OffsetOperands(Inst, 2);
3454
42
      break;
3455
138k
    case CVT_95_addMemImm8s4OffsetOperands:
3456
145
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm8s4OffsetOperands(Inst, 2);
3457
145
      break;
3458
138k
    case CVT_95_addAddrMode3Operands:
3459
147
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode3Operands(Inst, 3);
3460
147
      break;
3461
138k
    case CVT_95_addAM3OffsetOperands:
3462
78
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAM3OffsetOperands(Inst, 2);
3463
78
      break;
3464
138k
    case CVT_95_addMemImm0_95_1020s4OffsetOperands:
3465
364
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm0_1020s4OffsetOperands(Inst, 2);
3466
364
      break;
3467
138k
    case CVT_95_addMemThumbRIs2Operands:
3468
30
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs2Operands(Inst, 2);
3469
30
      break;
3470
138k
    case CVT_95_addPostIdxRegOperands:
3471
12
      static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegOperands(Inst, 2);
3472
12
      break;
3473
138k
    case CVT_95_addPostIdxImm8Operands:
3474
16
      static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8Operands(Inst, 1);
3475
16
      break;
3476
138k
    case CVT_reg0:
3477
331
      Inst.addOperand(MCOperand::createReg(0));
3478
331
      break;
3479
138k
    case CVT_regCPSR:
3480
242
      Inst.addOperand(MCOperand::createReg(ARM::CPSR));
3481
242
      break;
3482
138k
    case CVT_imm_95_14:
3483
127
      Inst.addOperand(MCOperand::createImm(14));
3484
127
      break;
3485
138k
    case CVT_95_addBankedRegOperands:
3486
198
      static_cast<ARMOperand&>(*Operands[OpIdx]).addBankedRegOperands(Inst, 1);
3487
198
      break;
3488
138k
    case CVT_95_addMSRMaskOperands:
3489
342
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMSRMaskOperands(Inst, 1);
3490
342
      break;
3491
138k
    case CVT_cvtThumbMultiply:
3492
30
      cvtThumbMultiply(Inst, Operands);
3493
30
      break;
3494
138k
    case CVT_regR8:
3495
68
      Inst.addOperand(MCOperand::createReg(ARM::R8));
3496
68
      break;
3497
138k
    case CVT_regR0:
3498
4
      Inst.addOperand(MCOperand::createReg(ARM::R0));
3499
4
      break;
3500
138k
    case CVT_95_addPKHASRImmOperands:
3501
12
      static_cast<ARMOperand&>(*Operands[OpIdx]).addPKHASRImmOperands(Inst, 1);
3502
12
      break;
3503
138k
    case CVT_imm_95_4:
3504
35
      Inst.addOperand(MCOperand::createImm(4));
3505
35
      break;
3506
138k
    case CVT_95_addImm1_95_32Operands:
3507
156
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_32Operands(Inst, 1);
3508
156
      break;
3509
138k
    case CVT_imm_95_5:
3510
13
      Inst.addOperand(MCOperand::createImm(5));
3511
13
      break;
3512
138k
    case CVT_95_addShifterImmOperands:
3513
44
      static_cast<ARMOperand&>(*Operands[OpIdx]).addShifterImmOperands(Inst, 1);
3514
44
      break;
3515
138k
    case CVT_95_addImm1_95_16Operands:
3516
18
      static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_16Operands(Inst, 1);
3517
18
      break;
3518
138k
    case CVT_95_addRotImmOperands:
3519
330
      static_cast<ARMOperand&>(*Operands[OpIdx]).addRotImmOperands(Inst, 1);
3520
330
      break;
3521
138k
    case CVT_95_addMemTBBOperands:
3522
7
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBBOperands(Inst, 2);
3523
7
      break;
3524
138k
    case CVT_95_addMemTBHOperands:
3525
7
      static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBHOperands(Inst, 2);
3526
7
      break;
3527
138k
    case CVT_95_addTraceSyncBarrierOptOperands:
3528
2
      static_cast<ARMOperand&>(*Operands[OpIdx]).addTraceSyncBarrierOptOperands(Inst, 1);
3529
2
      break;
3530
138k
    case CVT_95_addNEONi16splatNotOperands:
3531
4
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatNotOperands(Inst, 1);
3532
4
      break;
3533
138k
    case CVT_95_addNEONi32splatNotOperands:
3534
8
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatNotOperands(Inst, 1);
3535
8
      break;
3536
138k
    case CVT_95_addNEONi16splatOperands:
3537
16
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatOperands(Inst, 1);
3538
16
      break;
3539
138k
    case CVT_95_addNEONi32splatOperands:
3540
11
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatOperands(Inst, 1);
3541
11
      break;
3542
138k
    case CVT_95_addComplexRotationOddOperands:
3543
40
      static_cast<ARMOperand&>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1);
3544
40
      break;
3545
138k
    case CVT_95_addComplexRotationEvenOperands:
3546
120
      static_cast<ARMOperand&>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1);
3547
120
      break;
3548
138k
    case CVT_95_addVectorIndex64Operands:
3549
40
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex64Operands(Inst, 1);
3550
40
      break;
3551
138k
    case CVT_95_addVectorIndex32Operands:
3552
183
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex32Operands(Inst, 1);
3553
183
      break;
3554
138k
    case CVT_95_addFBits16Operands:
3555
28
      static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits16Operands(Inst, 1);
3556
28
      break;
3557
138k
    case CVT_95_addFBits32Operands:
3558
28
      static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits32Operands(Inst, 1);
3559
28
      break;
3560
138k
    case CVT_95_addVectorIndex16Operands:
3561
134
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex16Operands(Inst, 1);
3562
134
      break;
3563
138k
    case CVT_95_addVectorIndex8Operands:
3564
22
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex8Operands(Inst, 1);
3565
22
      break;
3566
138k
    case CVT_95_addVecListOperands:
3567
1.07k
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListOperands(Inst, 1);
3568
1.07k
      break;
3569
138k
    case CVT_95_addDupAlignedMemory16Operands:
3570
24
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory16Operands(Inst, 2);
3571
24
      break;
3572
138k
    case CVT_95_addAlignedMemory64or128Operands:
3573
290
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128Operands(Inst, 2);
3574
290
      break;
3575
138k
    case CVT_95_addAlignedMemory64or128or256Operands:
3576
393
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128or256Operands(Inst, 2);
3577
393
      break;
3578
138k
    case CVT_95_addAlignedMemory64Operands:
3579
346
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64Operands(Inst, 2);
3580
346
      break;
3581
138k
    case CVT_95_addVecListIndexedOperands:
3582
327
      static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListIndexedOperands(Inst, 2);
3583
327
      break;
3584
138k
    case CVT_95_addAlignedMemory16Operands:
3585
38
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory16Operands(Inst, 2);
3586
38
      break;
3587
138k
    case CVT_95_addDupAlignedMemory32Operands:
3588
42
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory32Operands(Inst, 2);
3589
42
      break;
3590
138k
    case CVT_95_addAlignedMemory32Operands:
3591
66
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory32Operands(Inst, 2);
3592
66
      break;
3593
138k
    case CVT_95_addDupAlignedMemoryNoneOperands:
3594
48
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemoryNoneOperands(Inst, 2);
3595
48
      break;
3596
138k
    case CVT_95_addAlignedMemoryNoneOperands:
3597
80
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryNoneOperands(Inst, 2);
3598
80
      break;
3599
138k
    case CVT_95_addAlignedMemoryOperands:
3600
0
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryOperands(Inst, 2);
3601
0
      break;
3602
138k
    case CVT_95_addDupAlignedMemory64Operands:
3603
36
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64Operands(Inst, 2);
3604
36
      break;
3605
138k
    case CVT_95_addDupAlignedMemory64or128Operands:
3606
24
      static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64or128Operands(Inst, 2);
3607
24
      break;
3608
138k
    case CVT_95_addSPRRegListOperands:
3609
12
      static_cast<ARMOperand&>(*Operands[OpIdx]).addSPRRegListOperands(Inst, 1);
3610
12
      break;
3611
138k
    case CVT_95_addAddrMode5FP16Operands:
3612
48
      static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5FP16Operands(Inst, 2);
3613
48
      break;
3614
138k
    case CVT_95_addNEONi32vmovOperands:
3615
38
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovOperands(Inst, 1);
3616
38
      break;
3617
138k
    case CVT_95_addNEONvmovi8ReplicateOperands:
3618
8
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi8ReplicateOperands(Inst, 1);
3619
8
      break;
3620
138k
    case CVT_95_addNEONvmovi16ReplicateOperands:
3621
16
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi16ReplicateOperands(Inst, 1);
3622
16
      break;
3623
138k
    case CVT_95_addNEONi32vmovNegOperands:
3624
0
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovNegOperands(Inst, 1);
3625
0
      break;
3626
138k
    case CVT_95_addNEONvmovi32ReplicateOperands:
3627
8
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi32ReplicateOperands(Inst, 1);
3628
8
      break;
3629
138k
    case CVT_95_addNEONi64splatOperands:
3630
8
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi64splatOperands(Inst, 1);
3631
8
      break;
3632
138k
    case CVT_95_addNEONi8splatOperands:
3633
4
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi8splatOperands(Inst, 1);
3634
4
      break;
3635
138k
    case CVT_95_addNEONinvi8ReplicateOperands:
3636
10
      static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONinvi8ReplicateOperands(Inst, 1);
3637
10
      break;
3638
138k
    case CVT_imm_95_2:
3639
34
      Inst.addOperand(MCOperand::createImm(2));
3640
34
      break;
3641
138k
    case CVT_imm_95_3:
3642
34
      Inst.addOperand(MCOperand::createImm(3));
3643
34
      break;
3644
138k
    }
3645
138k
  }
3646
43.2k
}
3647
3648
void ARMAsmParser::
3649
convertToMapAndConstraints(unsigned Kind,
3650
0
                           const OperandVector &Operands) {
3651
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
3652
0
  unsigned NumMCOperands = 0;
3653
0
  const uint8_t *Converter = ConversionTable[Kind];
3654
0
  for (const uint8_t *p = Converter; *p; p+= 2) {
3655
0
    switch (*p) {
3656
0
    default: llvm_unreachable("invalid conversion entry!");
3657
0
    case CVT_Reg:
3658
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3659
0
      Operands[*(p + 1)]->setConstraint("r");
3660
0
      ++NumMCOperands;
3661
0
      break;
3662
0
    case CVT_Tied:
3663
0
      ++NumMCOperands;
3664
0
      break;
3665
0
    case CVT_95_Reg:
3666
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3667
0
      Operands[*(p + 1)]->setConstraint("r");
3668
0
      NumMCOperands += 1;
3669
0
      break;
3670
0
    case CVT_95_addCCOutOperands:
3671
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3672
0
      Operands[*(p + 1)]->setConstraint("m");
3673
0
      NumMCOperands += 1;
3674
0
      break;
3675
0
    case CVT_95_addCondCodeOperands:
3676
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3677
0
      Operands[*(p + 1)]->setConstraint("m");
3678
0
      NumMCOperands += 2;
3679
0
      break;
3680
0
    case CVT_95_addRegShiftedRegOperands:
3681
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3682
0
      Operands[*(p + 1)]->setConstraint("m");
3683
0
      NumMCOperands += 3;
3684
0
      break;
3685
0
    case CVT_95_addModImmOperands:
3686
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3687
0
      Operands[*(p + 1)]->setConstraint("m");
3688
0
      NumMCOperands += 1;
3689
0
      break;
3690
0
    case CVT_95_addModImmNotOperands:
3691
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3692
0
      Operands[*(p + 1)]->setConstraint("m");
3693
0
      NumMCOperands += 1;
3694
0
      break;
3695
0
    case CVT_95_addRegShiftedImmOperands:
3696
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3697
0
      Operands[*(p + 1)]->setConstraint("m");
3698
0
      NumMCOperands += 2;
3699
0
      break;
3700
0
    case CVT_95_addImmOperands:
3701
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3702
0
      Operands[*(p + 1)]->setConstraint("m");
3703
0
      NumMCOperands += 1;
3704
0
      break;
3705
0
    case CVT_95_addT2SOImmNotOperands:
3706
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3707
0
      Operands[*(p + 1)]->setConstraint("m");
3708
0
      NumMCOperands += 1;
3709
0
      break;
3710
0
    case CVT_95_addImm0_95_508s4Operands:
3711
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3712
0
      Operands[*(p + 1)]->setConstraint("m");
3713
0
      NumMCOperands += 1;
3714
0
      break;
3715
0
    case CVT_regSP:
3716
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3717
0
      Operands[*(p + 1)]->setConstraint("m");
3718
0
      ++NumMCOperands;
3719
0
      break;
3720
0
    case CVT_95_addImm0_95_508s4NegOperands:
3721
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3722
0
      Operands[*(p + 1)]->setConstraint("m");
3723
0
      NumMCOperands += 1;
3724
0
      break;
3725
0
    case CVT_95_addImm0_95_4095NegOperands:
3726
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3727
0
      Operands[*(p + 1)]->setConstraint("m");
3728
0
      NumMCOperands += 1;
3729
0
      break;
3730
0
    case CVT_95_addThumbModImmNeg8_95_255Operands:
3731
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3732
0
      Operands[*(p + 1)]->setConstraint("m");
3733
0
      NumMCOperands += 1;
3734
0
      break;
3735
0
    case CVT_95_addT2SOImmNegOperands:
3736
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3737
0
      Operands[*(p + 1)]->setConstraint("m");
3738
0
      NumMCOperands += 1;
3739
0
      break;
3740
0
    case CVT_95_addModImmNegOperands:
3741
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3742
0
      Operands[*(p + 1)]->setConstraint("m");
3743
0
      NumMCOperands += 1;
3744
0
      break;
3745
0
    case CVT_95_addImm0_95_1020s4Operands:
3746
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3747
0
      Operands[*(p + 1)]->setConstraint("m");
3748
0
      NumMCOperands += 1;
3749
0
      break;
3750
0
    case CVT_95_addThumbModImmNeg1_95_7Operands:
3751
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3752
0
      Operands[*(p + 1)]->setConstraint("m");
3753
0
      NumMCOperands += 1;
3754
0
      break;
3755
0
    case CVT_95_addUnsignedOffset_95_b8s2Operands:
3756
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3757
0
      Operands[*(p + 1)]->setConstraint("m");
3758
0
      NumMCOperands += 1;
3759
0
      break;
3760
0
    case CVT_95_addAdrLabelOperands:
3761
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3762
0
      Operands[*(p + 1)]->setConstraint("m");
3763
0
      NumMCOperands += 1;
3764
0
      break;
3765
0
    case CVT_95_addARMBranchTargetOperands:
3766
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3767
0
      Operands[*(p + 1)]->setConstraint("m");
3768
0
      NumMCOperands += 1;
3769
0
      break;
3770
0
    case CVT_95_addBitfieldOperands:
3771
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3772
0
      Operands[*(p + 1)]->setConstraint("m");
3773
0
      NumMCOperands += 1;
3774
0
      break;
3775
0
    case CVT_imm_95_0:
3776
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3777
0
      Operands[*(p + 1)]->setConstraint("");
3778
0
      ++NumMCOperands;
3779
0
      break;
3780
0
    case CVT_95_addThumbBranchTargetOperands:
3781
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3782
0
      Operands[*(p + 1)]->setConstraint("m");
3783
0
      NumMCOperands += 1;
3784
0
      break;
3785
0
    case CVT_95_addCoprocNumOperands:
3786
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3787
0
      Operands[*(p + 1)]->setConstraint("m");
3788
0
      NumMCOperands += 1;
3789
0
      break;
3790
0
    case CVT_95_addCoprocRegOperands:
3791
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3792
0
      Operands[*(p + 1)]->setConstraint("m");
3793
0
      NumMCOperands += 1;
3794
0
      break;
3795
0
    case CVT_95_addProcIFlagsOperands:
3796
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3797
0
      Operands[*(p + 1)]->setConstraint("m");
3798
0
      NumMCOperands += 1;
3799
0
      break;
3800
0
    case CVT_imm_95_20:
3801
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3802
0
      Operands[*(p + 1)]->setConstraint("");
3803
0
      ++NumMCOperands;
3804
0
      break;
3805
0
    case CVT_imm_95_12:
3806
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3807
0
      Operands[*(p + 1)]->setConstraint("");
3808
0
      ++NumMCOperands;
3809
0
      break;
3810
0
    case CVT_imm_95_15:
3811
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3812
0
      Operands[*(p + 1)]->setConstraint("");
3813
0
      ++NumMCOperands;
3814
0
      break;
3815
0
    case CVT_95_addMemBarrierOptOperands:
3816
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3817
0
      Operands[*(p + 1)]->setConstraint("m");
3818
0
      NumMCOperands += 1;
3819
0
      break;
3820
0
    case CVT_imm_95_16:
3821
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3822
0
      Operands[*(p + 1)]->setConstraint("");
3823
0
      ++NumMCOperands;
3824
0
      break;
3825
0
    case CVT_95_addFPImmOperands:
3826
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3827
0
      Operands[*(p + 1)]->setConstraint("m");
3828
0
      NumMCOperands += 1;
3829
0
      break;
3830
0
    case CVT_95_addDPRRegListOperands:
3831
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3832
0
      Operands[*(p + 1)]->setConstraint("m");
3833
0
      NumMCOperands += 1;
3834
0
      break;
3835
0
    case CVT_imm_95_1:
3836
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3837
0
      Operands[*(p + 1)]->setConstraint("");
3838
0
      ++NumMCOperands;
3839
0
      break;
3840
0
    case CVT_95_addInstSyncBarrierOptOperands:
3841
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3842
0
      Operands[*(p + 1)]->setConstraint("m");
3843
0
      NumMCOperands += 1;
3844
0
      break;
3845
0
    case CVT_95_addITCondCodeOperands:
3846
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3847
0
      Operands[*(p + 1)]->setConstraint("m");
3848
0
      NumMCOperands += 1;
3849
0
      break;
3850
0
    case CVT_95_addITMaskOperands:
3851
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3852
0
      Operands[*(p + 1)]->setConstraint("m");
3853
0
      NumMCOperands += 1;
3854
0
      break;
3855
0
    case CVT_95_addMemNoOffsetOperands:
3856
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3857
0
      Operands[*(p + 1)]->setConstraint("m");
3858
0
      NumMCOperands += 1;
3859
0
      break;
3860
0
    case CVT_95_addAddrMode5Operands:
3861
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3862
0
      Operands[*(p + 1)]->setConstraint("m");
3863
0
      NumMCOperands += 2;
3864
0
      break;
3865
0
    case CVT_95_addCoprocOptionOperands:
3866
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3867
0
      Operands[*(p + 1)]->setConstraint("m");
3868
0
      NumMCOperands += 1;
3869
0
      break;
3870
0
    case CVT_95_addPostIdxImm8s4Operands:
3871
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3872
0
      Operands[*(p + 1)]->setConstraint("m");
3873
0
      NumMCOperands += 1;
3874
0
      break;
3875
0
    case CVT_95_addRegListOperands:
3876
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3877
0
      Operands[*(p + 1)]->setConstraint("m");
3878
0
      NumMCOperands += 1;
3879
0
      break;
3880
0
    case CVT_95_addThumbMemPCOperands:
3881
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3882
0
      Operands[*(p + 1)]->setConstraint("m");
3883
0
      NumMCOperands += 1;
3884
0
      break;
3885
0
    case CVT_95_addConstPoolAsmImmOperands:
3886
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3887
0
      Operands[*(p + 1)]->setConstraint("m");
3888
0
      NumMCOperands += 1;
3889
0
      break;
3890
0
    case CVT_95_addMemThumbRIs4Operands:
3891
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3892
0
      Operands[*(p + 1)]->setConstraint("m");
3893
0
      NumMCOperands += 2;
3894
0
      break;
3895
0
    case CVT_95_addMemThumbRROperands:
3896
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3897
0
      Operands[*(p + 1)]->setConstraint("m");
3898
0
      NumMCOperands += 2;
3899
0
      break;
3900
0
    case CVT_95_addMemThumbSPIOperands:
3901
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3902
0
      Operands[*(p + 1)]->setConstraint("m");
3903
0
      NumMCOperands += 2;
3904
0
      break;
3905
0
    case CVT_95_addMemImm12OffsetOperands:
3906
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3907
0
      Operands[*(p + 1)]->setConstraint("m");
3908
0
      NumMCOperands += 2;
3909
0
      break;
3910
0
    case CVT_95_addMemNegImm8OffsetOperands:
3911
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3912
0
      Operands[*(p + 1)]->setConstraint("m");
3913
0
      NumMCOperands += 2;
3914
0
      break;
3915
0
    case CVT_95_addMemRegOffsetOperands:
3916
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3917
0
      Operands[*(p + 1)]->setConstraint("m");
3918
0
      NumMCOperands += 3;
3919
0
      break;
3920
0
    case CVT_95_addMemUImm12OffsetOperands:
3921
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3922
0
      Operands[*(p + 1)]->setConstraint("m");
3923
0
      NumMCOperands += 2;
3924
0
      break;
3925
0
    case CVT_95_addT2MemRegOffsetOperands:
3926
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3927
0
      Operands[*(p + 1)]->setConstraint("m");
3928
0
      NumMCOperands += 3;
3929
0
      break;
3930
0
    case CVT_95_addMemPCRelImm12Operands:
3931
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3932
0
      Operands[*(p + 1)]->setConstraint("m");
3933
0
      NumMCOperands += 1;
3934
0
      break;
3935
0
    case CVT_95_addMemImm8OffsetOperands:
3936
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3937
0
      Operands[*(p + 1)]->setConstraint("m");
3938
0
      NumMCOperands += 2;
3939
0
      break;
3940
0
    case CVT_95_addAM2OffsetImmOperands:
3941
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3942
0
      Operands[*(p + 1)]->setConstraint("m");
3943
0
      NumMCOperands += 2;
3944
0
      break;
3945
0
    case CVT_95_addPostIdxRegShiftedOperands:
3946
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3947
0
      Operands[*(p + 1)]->setConstraint("m");
3948
0
      NumMCOperands += 2;
3949
0
      break;
3950
0
    case CVT_95_addMemThumbRIs1Operands:
3951
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3952
0
      Operands[*(p + 1)]->setConstraint("m");
3953
0
      NumMCOperands += 2;
3954
0
      break;
3955
0
    case CVT_95_addMemPosImm8OffsetOperands:
3956
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3957
0
      Operands[*(p + 1)]->setConstraint("m");
3958
0
      NumMCOperands += 2;
3959
0
      break;
3960
0
    case CVT_95_addMemImm8s4OffsetOperands:
3961
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3962
0
      Operands[*(p + 1)]->setConstraint("m");
3963
0
      NumMCOperands += 2;
3964
0
      break;
3965
0
    case CVT_95_addAddrMode3Operands:
3966
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3967
0
      Operands[*(p + 1)]->setConstraint("m");
3968
0
      NumMCOperands += 3;
3969
0
      break;
3970
0
    case CVT_95_addAM3OffsetOperands:
3971
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3972
0
      Operands[*(p + 1)]->setConstraint("m");
3973
0
      NumMCOperands += 2;
3974
0
      break;
3975
0
    case CVT_95_addMemImm0_95_1020s4OffsetOperands:
3976
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3977
0
      Operands[*(p + 1)]->setConstraint("m");
3978
0
      NumMCOperands += 2;
3979
0
      break;
3980
0
    case CVT_95_addMemThumbRIs2Operands:
3981
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3982
0
      Operands[*(p + 1)]->setConstraint("m");
3983
0
      NumMCOperands += 2;
3984
0
      break;
3985
0
    case CVT_95_addPostIdxRegOperands:
3986
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3987
0
      Operands[*(p + 1)]->setConstraint("m");
3988
0
      NumMCOperands += 2;
3989
0
      break;
3990
0
    case CVT_95_addPostIdxImm8Operands:
3991
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3992
0
      Operands[*(p + 1)]->setConstraint("m");
3993
0
      NumMCOperands += 1;
3994
0
      break;
3995
0
    case CVT_reg0:
3996
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3997
0
      Operands[*(p + 1)]->setConstraint("m");
3998
0
      ++NumMCOperands;
3999
0
      break;
4000
0
    case CVT_regCPSR:
4001
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4002
0
      Operands[*(p + 1)]->setConstraint("m");
4003
0
      ++NumMCOperands;
4004
0
      break;
4005
0
    case CVT_imm_95_14:
4006
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4007
0
      Operands[*(p + 1)]->setConstraint("");
4008
0
      ++NumMCOperands;
4009
0
      break;
4010
0
    case CVT_95_addBankedRegOperands:
4011
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4012
0
      Operands[*(p + 1)]->setConstraint("m");
4013
0
      NumMCOperands += 1;
4014
0
      break;
4015
0
    case CVT_95_addMSRMaskOperands:
4016
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4017
0
      Operands[*(p + 1)]->setConstraint("m");
4018
0
      NumMCOperands += 1;
4019
0
      break;
4020
0
    case CVT_regR8:
4021
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4022
0
      Operands[*(p + 1)]->setConstraint("m");
4023
0
      ++NumMCOperands;
4024
0
      break;
4025
0
    case CVT_regR0:
4026
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4027
0
      Operands[*(p + 1)]->setConstraint("m");
4028
0
      ++NumMCOperands;
4029
0
      break;
4030
0
    case CVT_95_addPKHASRImmOperands:
4031
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4032
0
      Operands[*(p + 1)]->setConstraint("m");
4033
0
      NumMCOperands += 1;
4034
0
      break;
4035
0
    case CVT_imm_95_4:
4036
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4037
0
      Operands[*(p + 1)]->setConstraint("");
4038
0
      ++NumMCOperands;
4039
0
      break;
4040
0
    case CVT_95_addImm1_95_32Operands:
4041
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4042
0
      Operands[*(p + 1)]->setConstraint("m");
4043
0
      NumMCOperands += 1;
4044
0
      break;
4045
0
    case CVT_imm_95_5:
4046
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4047
0
      Operands[*(p + 1)]->setConstraint("");
4048
0
      ++NumMCOperands;
4049
0
      break;
4050
0
    case CVT_95_addShifterImmOperands:
4051
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4052
0
      Operands[*(p + 1)]->setConstraint("m");
4053
0
      NumMCOperands += 1;
4054
0
      break;
4055
0
    case CVT_95_addImm1_95_16Operands:
4056
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4057
0
      Operands[*(p + 1)]->setConstraint("m");
4058
0
      NumMCOperands += 1;
4059
0
      break;
4060
0
    case CVT_95_addRotImmOperands:
4061
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4062
0
      Operands[*(p + 1)]->setConstraint("m");
4063
0
      NumMCOperands += 1;
4064
0
      break;
4065
0
    case CVT_95_addMemTBBOperands:
4066
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4067
0
      Operands[*(p + 1)]->setConstraint("m");
4068
0
      NumMCOperands += 2;
4069
0
      break;
4070
0
    case CVT_95_addMemTBHOperands:
4071
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4072
0
      Operands[*(p + 1)]->setConstraint("m");
4073
0
      NumMCOperands += 2;
4074
0
      break;
4075
0
    case CVT_95_addTraceSyncBarrierOptOperands:
4076
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4077
0
      Operands[*(p + 1)]->setConstraint("m");
4078
0
      NumMCOperands += 1;
4079
0
      break;
4080
0
    case CVT_95_addNEONi16splatNotOperands:
4081
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4082
0
      Operands[*(p + 1)]->setConstraint("m");
4083
0
      NumMCOperands += 1;
4084
0
      break;
4085
0
    case CVT_95_addNEONi32splatNotOperands:
4086
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4087
0
      Operands[*(p + 1)]->setConstraint("m");
4088
0
      NumMCOperands += 1;
4089
0
      break;
4090
0
    case CVT_95_addNEONi16splatOperands:
4091
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4092
0
      Operands[*(p + 1)]->setConstraint("m");
4093
0
      NumMCOperands += 1;
4094
0
      break;
4095
0
    case CVT_95_addNEONi32splatOperands:
4096
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4097
0
      Operands[*(p + 1)]->setConstraint("m");
4098
0
      NumMCOperands += 1;
4099
0
      break;
4100
0
    case CVT_95_addComplexRotationOddOperands:
4101
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4102
0
      Operands[*(p + 1)]->setConstraint("m");
4103
0
      NumMCOperands += 1;
4104
0
      break;
4105
0
    case CVT_95_addComplexRotationEvenOperands:
4106
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4107
0
      Operands[*(p + 1)]->setConstraint("m");
4108
0
      NumMCOperands += 1;
4109
0
      break;
4110
0
    case CVT_95_addVectorIndex64Operands:
4111
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4112
0
      Operands[*(p + 1)]->setConstraint("m");
4113
0
      NumMCOperands += 1;
4114
0
      break;
4115
0
    case CVT_95_addVectorIndex32Operands:
4116
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4117
0
      Operands[*(p + 1)]->setConstraint("m");
4118
0
      NumMCOperands += 1;
4119
0
      break;
4120
0
    case CVT_95_addFBits16Operands:
4121
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4122
0
      Operands[*(p + 1)]->setConstraint("m");
4123
0
      NumMCOperands += 1;
4124
0
      break;
4125
0
    case CVT_95_addFBits32Operands:
4126
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4127
0
      Operands[*(p + 1)]->setConstraint("m");
4128
0
      NumMCOperands += 1;
4129
0
      break;
4130
0
    case CVT_95_addVectorIndex16Operands:
4131
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4132
0
      Operands[*(p + 1)]->setConstraint("m");
4133
0
      NumMCOperands += 1;
4134
0
      break;
4135
0
    case CVT_95_addVectorIndex8Operands:
4136
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4137
0
      Operands[*(p + 1)]->setConstraint("m");
4138
0
      NumMCOperands += 1;
4139
0
      break;
4140
0
    case CVT_95_addVecListOperands:
4141
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4142
0
      Operands[*(p + 1)]->setConstraint("m");
4143
0
      NumMCOperands += 1;
4144
0
      break;
4145
0
    case CVT_95_addDupAlignedMemory16Operands:
4146
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4147
0
      Operands[*(p + 1)]->setConstraint("m");
4148
0
      NumMCOperands += 2;
4149
0
      break;
4150
0
    case CVT_95_addAlignedMemory64or128Operands:
4151
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4152
0
      Operands[*(p + 1)]->setConstraint("m");
4153
0
      NumMCOperands += 2;
4154
0
      break;
4155
0
    case CVT_95_addAlignedMemory64or128or256Operands:
4156
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4157
0
      Operands[*(p + 1)]->setConstraint("m");
4158
0
      NumMCOperands += 2;
4159
0
      break;
4160
0
    case CVT_95_addAlignedMemory64Operands:
4161
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4162
0
      Operands[*(p + 1)]->setConstraint("m");
4163
0
      NumMCOperands += 2;
4164
0
      break;
4165
0
    case CVT_95_addVecListIndexedOperands:
4166
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4167
0
      Operands[*(p + 1)]->setConstraint("m");
4168
0
      NumMCOperands += 2;
4169
0
      break;
4170
0
    case CVT_95_addAlignedMemory16Operands:
4171
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4172
0
      Operands[*(p + 1)]->setConstraint("m");
4173
0
      NumMCOperands += 2;
4174
0
      break;
4175
0
    case CVT_95_addDupAlignedMemory32Operands:
4176
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4177
0
      Operands[*(p + 1)]->setConstraint("m");
4178
0
      NumMCOperands += 2;
4179
0
      break;
4180
0
    case CVT_95_addAlignedMemory32Operands:
4181
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4182
0
      Operands[*(p + 1)]->setConstraint("m");
4183
0
      NumMCOperands += 2;
4184
0
      break;
4185
0
    case CVT_95_addDupAlignedMemoryNoneOperands:
4186
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4187
0
      Operands[*(p + 1)]->setConstraint("m");
4188
0
      NumMCOperands += 2;
4189
0
      break;
4190
0
    case CVT_95_addAlignedMemoryNoneOperands:
4191
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4192
0
      Operands[*(p + 1)]->setConstraint("m");
4193
0
      NumMCOperands += 2;
4194
0
      break;
4195
0
    case CVT_95_addAlignedMemoryOperands:
4196
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4197
0
      Operands[*(p + 1)]->setConstraint("m");
4198
0
      NumMCOperands += 2;
4199
0
      break;
4200
0
    case CVT_95_addDupAlignedMemory64Operands:
4201
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4202
0
      Operands[*(p + 1)]->setConstraint("m");
4203
0
      NumMCOperands += 2;
4204
0
      break;
4205
0
    case CVT_95_addDupAlignedMemory64or128Operands:
4206
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4207
0
      Operands[*(p + 1)]->setConstraint("m");
4208
0
      NumMCOperands += 2;
4209
0
      break;
4210
0
    case CVT_95_addSPRRegListOperands:
4211
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4212
0
      Operands[*(p + 1)]->setConstraint("m");
4213
0
      NumMCOperands += 1;
4214
0
      break;
4215
0
    case CVT_95_addAddrMode5FP16Operands:
4216
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4217
0
      Operands[*(p + 1)]->setConstraint("m");
4218
0
      NumMCOperands += 2;
4219
0
      break;
4220
0
    case CVT_95_addNEONi32vmovOperands:
4221
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4222
0
      Operands[*(p + 1)]->setConstraint("m");
4223
0
      NumMCOperands += 1;
4224
0
      break;
4225
0
    case CVT_95_addNEONvmovi8ReplicateOperands:
4226
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4227
0
      Operands[*(p + 1)]->setConstraint("m");
4228
0
      NumMCOperands += 1;
4229
0
      break;
4230
0
    case CVT_95_addNEONvmovi16ReplicateOperands:
4231
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4232
0
      Operands[*(p + 1)]->setConstraint("m");
4233
0
      NumMCOperands += 1;
4234
0
      break;
4235
0
    case CVT_95_addNEONi32vmovNegOperands:
4236
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4237
0
      Operands[*(p + 1)]->setConstraint("m");
4238
0
      NumMCOperands += 1;
4239
0
      break;
4240
0
    case CVT_95_addNEONvmovi32ReplicateOperands:
4241
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4242
0
      Operands[*(p + 1)]->setConstraint("m");
4243
0
      NumMCOperands += 1;
4244
0
      break;
4245
0
    case CVT_95_addNEONi64splatOperands:
4246
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4247
0
      Operands[*(p + 1)]->setConstraint("m");
4248
0
      NumMCOperands += 1;
4249
0
      break;
4250
0
    case CVT_95_addNEONi8splatOperands:
4251
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4252
0
      Operands[*(p + 1)]->setConstraint("m");
4253
0
      NumMCOperands += 1;
4254
0
      break;
4255
0
    case CVT_95_addNEONinvi8ReplicateOperands:
4256
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4257
0
      Operands[*(p + 1)]->setConstraint("m");
4258
0
      NumMCOperands += 1;
4259
0
      break;
4260
0
    case CVT_imm_95_2:
4261
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4262
0
      Operands[*(p + 1)]->setConstraint("");
4263
0
      ++NumMCOperands;
4264
0
      break;
4265
0
    case CVT_imm_95_3:
4266
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4267
0
      Operands[*(p + 1)]->setConstraint("");
4268
0
      ++NumMCOperands;
4269
0
      break;
4270
0
    }
4271
0
  }
4272
0
}
4273
4274
namespace {
4275
4276
/// MatchClassKind - The kinds of classes which participate in
4277
/// instruction matching.
4278
enum MatchClassKind {
4279
  InvalidMatchClass = 0,
4280
  OptionalMatchClass = 1,
4281
  MCK__DOT_d, // '.d'
4282
  MCK__DOT_f, // '.f'
4283
  MCK__DOT_s16, // '.s16'
4284
  MCK__DOT_s32, // '.s32'
4285
  MCK__DOT_s64, // '.s64'
4286
  MCK__DOT_s8, // '.s8'
4287
  MCK__DOT_u16, // '.u16'
4288
  MCK__DOT_u32, // '.u32'
4289
  MCK__DOT_u64, // '.u64'
4290
  MCK__DOT_u8, // '.u8'
4291
  MCK__DOT_f32, // '.f32'
4292
  MCK__DOT_f64, // '.f64'
4293
  MCK__DOT_i16, // '.i16'
4294
  MCK__DOT_i32, // '.i32'
4295
  MCK__DOT_i64, // '.i64'
4296
  MCK__DOT_i8, // '.i8'
4297
  MCK__DOT_p16, // '.p16'
4298
  MCK__DOT_p8, // '.p8'
4299
  MCK__EXCLAIM_, // '!'
4300
  MCK__35_0, // '#0'
4301
  MCK__DOT_16, // '.16'
4302
  MCK__DOT_32, // '.32'
4303
  MCK__DOT_64, // '.64'
4304
  MCK__DOT_8, // '.8'
4305
  MCK__DOT_f16, // '.f16'
4306
  MCK__DOT_p64, // '.p64'
4307
  MCK__DOT_w, // '.w'
4308
  MCK__91_, // '['
4309
  MCK__93_, // ']'
4310
  MCK__94_, // '^'
4311
  MCK__123_, // '{'
4312
  MCK__125_, // '}'
4313
  MCK_LAST_TOKEN = MCK__125_,
4314
  MCK_Reg75, // derived register class
4315
  MCK_Reg59, // derived register class
4316
  MCK_Reg11, // derived register class
4317
  MCK_APSR, // register class 'APSR'
4318
  MCK_APSR_NZCV, // register class 'APSR_NZCV'
4319
  MCK_CCR, // register class 'CCR,CPSR'
4320
  MCK_FPEXC, // register class 'FPEXC'
4321
  MCK_FPINST, // register class 'FPINST'
4322
  MCK_FPINST2, // register class 'FPINST2'
4323
  MCK_FPSCR, // register class 'FPSCR'
4324
  MCK_FPSID, // register class 'FPSID'
4325
  MCK_GPRsp, // register class 'GPRsp,SP'
4326
  MCK_LR, // register class 'LR'
4327
  MCK_MVFR0, // register class 'MVFR0'
4328
  MCK_MVFR1, // register class 'MVFR1'
4329
  MCK_MVFR2, // register class 'MVFR2'
4330
  MCK_PC, // register class 'PC'
4331
  MCK_SPSR, // register class 'SPSR'
4332
  MCK_Reg100, // derived register class
4333
  MCK_Reg73, // derived register class
4334
  MCK_Reg68, // derived register class
4335
  MCK_Reg60, // derived register class
4336
  MCK_Reg101, // derived register class
4337
  MCK_Reg88, // derived register class
4338
  MCK_Reg83, // derived register class
4339
  MCK_Reg74, // derived register class
4340
  MCK_Reg72, // derived register class
4341
  MCK_Reg61, // derived register class
4342
  MCK_Reg45, // derived register class
4343
  MCK_Reg102, // derived register class
4344
  MCK_Reg93, // derived register class
4345
  MCK_Reg89, // derived register class
4346
  MCK_Reg84, // derived register class
4347
  MCK_Reg69, // derived register class
4348
  MCK_Reg62, // derived register class
4349
  MCK_Reg46, // derived register class
4350
  MCK_Reg0, // derived register class
4351
  MCK_QPR_8, // register class 'QPR_8'
4352
  MCK_Reg63, // derived register class
4353
  MCK_Reg57, // derived register class
4354
  MCK_tcGPR, // register class 'tcGPR'
4355
  MCK_Reg103, // derived register class
4356
  MCK_Reg94, // derived register class
4357
  MCK_Reg76, // derived register class
4358
  MCK_Reg70, // derived register class
4359
  MCK_Reg64, // derived register class
4360
  MCK_Reg58, // derived register class
4361
  MCK_Reg40, // derived register class
4362
  MCK_Reg10, // derived register class
4363
  MCK_Reg104, // derived register class
4364
  MCK_Reg90, // derived register class
4365
  MCK_Reg85, // derived register class
4366
  MCK_Reg77, // derived register class
4367
  MCK_Reg65, // derived register class
4368
  MCK_Reg55, // derived register class
4369
  MCK_Reg47, // derived register class
4370
  MCK_Reg26, // derived register class
4371
  MCK_Reg8, // derived register class
4372
  MCK_GPRPair, // register class 'GPRPair'
4373
  MCK_Reg105, // derived register class
4374
  MCK_Reg95, // derived register class
4375
  MCK_Reg91, // derived register class
4376
  MCK_Reg86, // derived register class
4377
  MCK_Reg78, // derived register class
4378
  MCK_Reg66, // derived register class
4379
  MCK_Reg56, // derived register class
4380
  MCK_Reg48, // derived register class
4381
  MCK_Reg41, // derived register class
4382
  MCK_Reg27, // derived register class
4383
  MCK_DPR_8, // register class 'DPR_8'
4384
  MCK_QPR_VFP2, // register class 'QPR_VFP2'
4385
  MCK_hGPR, // register class 'hGPR'
4386
  MCK_tGPR, // register class 'tGPR'
4387
  MCK_tGPRwithpc, // register class 'tGPRwithpc'
4388
  MCK_Reg96, // derived register class
4389
  MCK_Reg53, // derived register class
4390
  MCK_QQQQPR, // register class 'QQQQPR'
4391
  MCK_Reg106, // derived register class
4392
  MCK_Reg97, // derived register class
4393
  MCK_Reg79, // derived register class
4394
  MCK_Reg54, // derived register class
4395
  MCK_Reg42, // derived register class
4396
  MCK_rGPR, // register class 'rGPR'
4397
  MCK_Reg92, // derived register class
4398
  MCK_Reg87, // derived register class
4399
  MCK_Reg80, // derived register class
4400
  MCK_Reg51, // derived register class
4401
  MCK_Reg24, // derived register class
4402
  MCK_GPRnopc, // register class 'GPRnopc'
4403
  MCK_QQPR, // register class 'QQPR'
4404
  MCK_Reg98, // derived register class
4405
  MCK_Reg81, // derived register class
4406
  MCK_Reg52, // derived register class
4407
  MCK_Reg43, // derived register class
4408
  MCK_Reg25, // derived register class
4409
  MCK_DPR_VFP2, // register class 'DPR_VFP2'
4410
  MCK_GPR, // register class 'GPR'
4411
  MCK_GPRwithAPSR, // register class 'GPRwithAPSR'
4412
  MCK_QPR, // register class 'QPR'
4413
  MCK_SPR_8, // register class 'SPR_8'
4414
  MCK_DTripleSpc, // register class 'DTripleSpc,DQuadSpc'
4415
  MCK_DQuad, // register class 'DQuad'
4416
  MCK_DPairSpc, // register class 'DPairSpc'
4417
  MCK_DTriple, // register class 'DTriple'
4418
  MCK_DPair, // register class 'DPair'
4419
  MCK_DPR, // register class 'DPR'
4420
  MCK_HPR, // register class 'HPR,SPR'
4421
  MCK_LAST_REGISTER = MCK_HPR,
4422
  MCK_AM2OffsetImm, // user defined class 'AM2OffsetImmAsmOperand'
4423
  MCK_AM3Offset, // user defined class 'AM3OffsetAsmOperand'
4424
  MCK_ARMBranchTarget, // user defined class 'ARMBranchTarget'
4425
  MCK_AddrMode3, // user defined class 'AddrMode3AsmOperand'
4426
  MCK_AddrMode5, // user defined class 'AddrMode5AsmOperand'
4427
  MCK_AddrMode5FP16, // user defined class 'AddrMode5FP16AsmOperand'
4428
  MCK_AlignedMemory16, // user defined class 'AddrMode6Align16AsmOperand'
4429
  MCK_AlignedMemory32, // user defined class 'AddrMode6Align32AsmOperand'
4430
  MCK_AlignedMemory64, // user defined class 'AddrMode6Align64AsmOperand'
4431
  MCK_AlignedMemory64or128, // user defined class 'AddrMode6Align64or128AsmOperand'
4432
  MCK_AlignedMemory64or128or256, // user defined class 'AddrMode6Align64or128or256AsmOperand'
4433
  MCK_AlignedMemoryNone, // user defined class 'AddrMode6AlignNoneAsmOperand'
4434
  MCK_AlignedMemory, // user defined class 'AddrMode6AsmOperand'
4435
  MCK_DupAlignedMemory16, // user defined class 'AddrMode6dupAlign16AsmOperand'
4436
  MCK_DupAlignedMemory32, // user defined class 'AddrMode6dupAlign32AsmOperand'
4437
  MCK_DupAlignedMemory64, // user defined class 'AddrMode6dupAlign64AsmOperand'
4438
  MCK_DupAlignedMemory64or128, // user defined class 'AddrMode6dupAlign64or128AsmOperand'
4439
  MCK_DupAlignedMemoryNone, // user defined class 'AddrMode6dupAlignNoneAsmOperand'
4440
  MCK_AdrLabel, // user defined class 'AdrLabelAsmOperand'
4441
  MCK_BankedReg, // user defined class 'BankedRegOperand'
4442
  MCK_Bitfield, // user defined class 'BitfieldAsmOperand'
4443
  MCK_CCOut, // user defined class 'CCOutOperand'
4444
  MCK_CondCode, // user defined class 'CondCodeOperand'
4445
  MCK_CoprocNum, // user defined class 'CoprocNumAsmOperand'
4446
  MCK_CoprocOption, // user defined class 'CoprocOptionAsmOperand'
4447
  MCK_CoprocReg, // user defined class 'CoprocRegAsmOperand'
4448
  MCK_DPRRegList, // user defined class 'DPRRegListAsmOperand'
4449
  MCK_FPImm, // user defined class 'FPImmOperand'
4450
  MCK_Imm0_15, // user defined class 'Imm0_15AsmOperand'
4451
  MCK_Imm0_1, // user defined class 'Imm0_1AsmOperand'
4452
  MCK_Imm0_239, // user defined class 'Imm0_239AsmOperand'
4453
  MCK_Imm0_255, // user defined class 'Imm0_255AsmOperand'
4454
  MCK_Imm0_31, // user defined class 'Imm0_31AsmOperand'
4455
  MCK_Imm0_32, // user defined class 'Imm0_32AsmOperand'
4456
  MCK_Imm0_3, // user defined class 'Imm0_3AsmOperand'
4457
  MCK_Imm0_63, // user defined class 'Imm0_63AsmOperand'
4458
  MCK_Imm0_65535, // user defined class 'Imm0_65535AsmOperand'
4459
  MCK_Imm0_65535Expr, // user defined class 'Imm0_65535ExprAsmOperand'
4460
  MCK_Imm0_7, // user defined class 'Imm0_7AsmOperand'
4461
  MCK_Imm16, // user defined class 'Imm16AsmOperand'
4462
  MCK_Imm1_15, // user defined class 'Imm1_15AsmOperand'
4463
  MCK_Imm1_16, // user defined class 'Imm1_16AsmOperand'
4464
  MCK_Imm1_31, // user defined class 'Imm1_31AsmOperand'
4465
  MCK_Imm1_32, // user defined class 'Imm1_32AsmOperand'
4466
  MCK_Imm1_7, // user defined class 'Imm1_7AsmOperand'
4467
  MCK_Imm24bit, // user defined class 'Imm24bitAsmOperand'
4468
  MCK_Imm256_65535Expr, // user defined class 'Imm256_65535ExprAsmOperand'
4469
  MCK_Imm32, // user defined class 'Imm32AsmOperand'
4470
  MCK_Imm8, // user defined class 'Imm8AsmOperand'
4471
  MCK_Imm8_255, // user defined class 'Imm8_255AsmOperand'
4472
  MCK_Imm, // user defined class 'ImmAsmOperand'
4473
  MCK_InstSyncBarrierOpt, // user defined class 'InstSyncBarrierOptOperand'
4474
  MCK_MSRMask, // user defined class 'MSRMaskOperand'
4475
  MCK_MemBarrierOpt, // user defined class 'MemBarrierOptOperand'
4476
  MCK_MemImm0_1020s4Offset, // user defined class 'MemImm0_1020s4OffsetAsmOperand'
4477
  MCK_MemImm12Offset, // user defined class 'MemImm12OffsetAsmOperand'
4478
  MCK_MemImm8Offset, // user defined class 'MemImm8OffsetAsmOperand'
4479
  MCK_MemImm8s4Offset, // user defined class 'MemImm8s4OffsetAsmOperand'
4480
  MCK_MemNegImm8Offset, // user defined class 'MemNegImm8OffsetAsmOperand'
4481
  MCK_MemNoOffset, // user defined class 'MemNoOffsetAsmOperand'
4482
  MCK_MemPosImm8Offset, // user defined class 'MemPosImm8OffsetAsmOperand'
4483
  MCK_MemRegOffset, // user defined class 'MemRegOffsetAsmOperand'
4484
  MCK_ModImm, // user defined class 'ModImmAsmOperand'
4485
  MCK_ModImmNeg, // user defined class 'ModImmNegAsmOperand'
4486
  MCK_ModImmNot, // user defined class 'ModImmNotAsmOperand'
4487
  MCK_PKHASRImm, // user defined class 'PKHASRAsmOperand'
4488
  MCK_PKHLSLImm, // user defined class 'PKHLSLAsmOperand'
4489
  MCK_PostIdxImm8, // user defined class 'PostIdxImm8AsmOperand'
4490
  MCK_PostIdxImm8s4, // user defined class 'PostIdxImm8s4AsmOperand'
4491
  MCK_PostIdxReg, // user defined class 'PostIdxRegAsmOperand'
4492
  MCK_PostIdxRegShifted, // user defined class 'PostIdxRegShiftedAsmOperand'
4493
  MCK_ProcIFlags, // user defined class 'ProcIFlagsOperand'
4494
  MCK_RegList, // user defined class 'RegListAsmOperand'
4495
  MCK_RotImm, // user defined class 'RotImmAsmOperand'
4496
  MCK_SPRRegList, // user defined class 'SPRRegListAsmOperand'
4497
  MCK_SetEndImm, // user defined class 'SetEndAsmOperand'
4498
  MCK_RegShiftedImm, // user defined class 'ShiftedImmAsmOperand'
4499
  MCK_RegShiftedReg, // user defined class 'ShiftedRegAsmOperand'
4500
  MCK_ShifterImm, // user defined class 'ShifterImmAsmOperand'
4501
  MCK_ThumbBranchTarget, // user defined class 'ThumbBranchTarget'
4502
  MCK_ThumbMemPC, // user defined class 'ThumbMemPC'
4503
  MCK_ThumbModImmNeg1_7, // user defined class 'ThumbModImmNeg1_7AsmOperand'
4504
  MCK_ThumbModImmNeg8_255, // user defined class 'ThumbModImmNeg8_255AsmOperand'
4505
  MCK_ImmThumbSR, // user defined class 'ThumbSRImmAsmOperand'
4506
  MCK_TraceSyncBarrierOpt, // user defined class 'TraceSyncBarrierOptOperand'
4507
  MCK_UnsignedOffset_b8s2, // user defined class 'UnsignedOffset_b8s2'
4508
  MCK_VecListDPairAllLanes, // user defined class 'VecListDPairAllLanesAsmOperand'
4509
  MCK_VecListDPair, // user defined class 'VecListDPairAsmOperand'
4510
  MCK_VecListDPairSpacedAllLanes, // user defined class 'VecListDPairSpacedAllLanesAsmOperand'
4511
  MCK_VecListDPairSpaced, // user defined class 'VecListDPairSpacedAsmOperand'
4512
  MCK_VecListFourDAllLanes, // user defined class 'VecListFourDAllLanesAsmOperand'
4513
  MCK_VecListFourD, // user defined class 'VecListFourDAsmOperand'
4514
  MCK_VecListFourDByteIndexed, // user defined class 'VecListFourDByteIndexAsmOperand'
4515
  MCK_VecListFourDHWordIndexed, // user defined class 'VecListFourDHWordIndexAsmOperand'
4516
  MCK_VecListFourDWordIndexed, // user defined class 'VecListFourDWordIndexAsmOperand'
4517
  MCK_VecListFourQAllLanes, // user defined class 'VecListFourQAllLanesAsmOperand'
4518
  MCK_VecListFourQ, // user defined class 'VecListFourQAsmOperand'
4519
  MCK_VecListFourQHWordIndexed, // user defined class 'VecListFourQHWordIndexAsmOperand'
4520
  MCK_VecListFourQWordIndexed, // user defined class 'VecListFourQWordIndexAsmOperand'
4521
  MCK_VecListOneDAllLanes, // user defined class 'VecListOneDAllLanesAsmOperand'
4522
  MCK_VecListOneD, // user defined class 'VecListOneDAsmOperand'
4523
  MCK_VecListOneDByteIndexed, // user defined class 'VecListOneDByteIndexAsmOperand'
4524
  MCK_VecListOneDHWordIndexed, // user defined class 'VecListOneDHWordIndexAsmOperand'
4525
  MCK_VecListOneDWordIndexed, // user defined class 'VecListOneDWordIndexAsmOperand'
4526
  MCK_VecListThreeDAllLanes, // user defined class 'VecListThreeDAllLanesAsmOperand'
4527
  MCK_VecListThreeD, // user defined class 'VecListThreeDAsmOperand'
4528
  MCK_VecListThreeDByteIndexed, // user defined class 'VecListThreeDByteIndexAsmOperand'
4529
  MCK_VecListThreeDHWordIndexed, // user defined class 'VecListThreeDHWordIndexAsmOperand'
4530
  MCK_VecListThreeDWordIndexed, // user defined class 'VecListThreeDWordIndexAsmOperand'
4531
  MCK_VecListThreeQAllLanes, // user defined class 'VecListThreeQAllLanesAsmOperand'
4532
  MCK_VecListThreeQ, // user defined class 'VecListThreeQAsmOperand'
4533
  MCK_VecListThreeQHWordIndexed, // user defined class 'VecListThreeQHWordIndexAsmOperand'
4534
  MCK_VecListThreeQWordIndexed, // user defined class 'VecListThreeQWordIndexAsmOperand'
4535
  MCK_VecListTwoDByteIndexed, // user defined class 'VecListTwoDByteIndexAsmOperand'
4536
  MCK_VecListTwoDHWordIndexed, // user defined class 'VecListTwoDHWordIndexAsmOperand'
4537
  MCK_VecListTwoDWordIndexed, // user defined class 'VecListTwoDWordIndexAsmOperand'
4538
  MCK_VecListTwoQHWordIndexed, // user defined class 'VecListTwoQHWordIndexAsmOperand'
4539
  MCK_VecListTwoQWordIndexed, // user defined class 'VecListTwoQWordIndexAsmOperand'
4540
  MCK_VectorIndex16, // user defined class 'VectorIndex16Operand'
4541
  MCK_VectorIndex32, // user defined class 'VectorIndex32Operand'
4542
  MCK_VectorIndex64, // user defined class 'VectorIndex64Operand'
4543
  MCK_VectorIndex8, // user defined class 'VectorIndex8Operand'
4544
  MCK_MemTBB, // user defined class 'addrmode_tbb_asmoperand'
4545
  MCK_MemTBH, // user defined class 'addrmode_tbh_asmoperand'
4546
  MCK_ComplexRotationEven, // user defined class 'anonymous_3603'
4547
  MCK_ComplexRotationOdd, // user defined class 'anonymous_3604'
4548
  MCK_NEONi16vmovi8Replicate, // user defined class 'anonymous_4666'
4549
  MCK_NEONi16invi8Replicate, // user defined class 'anonymous_4668'
4550
  MCK_NEONi32vmovi8Replicate, // user defined class 'anonymous_4671'
4551
  MCK_NEONi32invi8Replicate, // user defined class 'anonymous_4673'
4552
  MCK_NEONi64vmovi8Replicate, // user defined class 'anonymous_4680'
4553
  MCK_NEONi64invi8Replicate, // user defined class 'anonymous_4682'
4554
  MCK_NEONi32vmovi16Replicate, // user defined class 'anonymous_4693'
4555
  MCK_NEONi64vmovi16Replicate, // user defined class 'anonymous_4696'
4556
  MCK_NEONi64vmovi32Replicate, // user defined class 'anonymous_4703'
4557
  MCK_ConstPoolAsmImm, // user defined class 'const_pool_asm_operand'
4558
  MCK_FBits16, // user defined class 'fbits16_asm_operand'
4559
  MCK_FBits32, // user defined class 'fbits32_asm_operand'
4560
  MCK_Imm0_4095, // user defined class 'imm0_4095_asmoperand'
4561
  MCK_Imm0_4095Neg, // user defined class 'imm0_4095_neg_asmoperand'
4562
  MCK_ITMask, // user defined class 'it_mask_asmoperand'
4563
  MCK_ITCondCode, // user defined class 'it_pred_asmoperand'
4564
  MCK_NEONi16splat, // user defined class 'nImmSplatI16AsmOperand'
4565
  MCK_NEONi32splat, // user defined class 'nImmSplatI32AsmOperand'
4566
  MCK_NEONi64splat, // user defined class 'nImmSplatI64AsmOperand'
4567
  MCK_NEONi8splat, // user defined class 'nImmSplatI8AsmOperand'
4568
  MCK_NEONi16splatNot, // user defined class 'nImmSplatNotI16AsmOperand'
4569
  MCK_NEONi32splatNot, // user defined class 'nImmSplatNotI32AsmOperand'
4570
  MCK_NEONi32vmov, // user defined class 'nImmVMOVI32AsmOperand'
4571
  MCK_NEONi32vmovNeg, // user defined class 'nImmVMOVI32NegAsmOperand'
4572
  MCK_ShrImm16, // user defined class 'shr_imm16_asm_operand'
4573
  MCK_ShrImm32, // user defined class 'shr_imm32_asm_operand'
4574
  MCK_ShrImm64, // user defined class 'shr_imm64_asm_operand'
4575
  MCK_ShrImm8, // user defined class 'shr_imm8_asm_operand'
4576
  MCK_T2SOImm, // user defined class 't2_so_imm_asmoperand'
4577
  MCK_T2SOImmNeg, // user defined class 't2_so_imm_neg_asmoperand'
4578
  MCK_T2SOImmNot, // user defined class 't2_so_imm_not_asmoperand'
4579
  MCK_MemUImm12Offset, // user defined class 't2addrmode_imm12_asmoperand'
4580
  MCK_T2MemRegOffset, // user defined class 't2addrmode_so_reg_asmoperand'
4581
  MCK_Imm8s4, // user defined class 't2am_imm8s4_offset_asmoperand'
4582
  MCK_MemPCRelImm12, // user defined class 't2ldr_pcrel_imm12_asmoperand'
4583
  MCK_MemThumbRIs1, // user defined class 't_addrmode_is1_asm_operand'
4584
  MCK_MemThumbRIs2, // user defined class 't_addrmode_is2_asm_operand'
4585
  MCK_MemThumbRIs4, // user defined class 't_addrmode_is4_asm_operand'
4586
  MCK_MemThumbRR, // user defined class 't_addrmode_rr_asm_operand'
4587
  MCK_MemThumbSPI, // user defined class 't_addrmode_sp_asm_operand'
4588
  MCK_Imm0_1020s4, // user defined class 't_imm0_1020s4_asmoperand'
4589
  MCK_Imm0_508s4, // user defined class 't_imm0_508s4_asmoperand'
4590
  MCK_Imm0_508s4Neg, // user defined class 't_imm0_508s4_neg_asmoperand'
4591
  NumMatchClassKinds
4592
};
4593
4594
}
4595
4596
4.82k
static const char *getMatchKindDiag(ARMAsmParser::ARMMatchResultTy MatchResult) {
4597
4.82k
  switch (MatchResult) {
4598
4.82k
  case ARMAsmParser::Match_GPRsp:
4599
3
    return "operand must be a register sp";
4600
4.82k
  case ARMAsmParser::Match_QPR_8:
4601
0
    return "operand must be a register in range [q0, q3]";
4602
4.82k
  case ARMAsmParser::Match_DPR_8:
4603
2
    return "operand must be a register in range [d0, d7]";
4604
4.82k
  case ARMAsmParser::Match_QPR_VFP2:
4605
0
    return "operand must be a register in range [q0, q7]";
4606
4.82k
  case ARMAsmParser::Match_hGPR:
4607
0
    return "operand must be a register in range [r8, r15]";
4608
4.82k
  case ARMAsmParser::Match_tGPR:
4609
39
    return "operand must be a register in range [r0, r7]";
4610
4.82k
  case ARMAsmParser::Match_GPRnopc:
4611
118
    return "operand must be a register in range [r0, r14]";
4612
4.82k
  case ARMAsmParser::Match_DPR_VFP2:
4613
4
    return "operand must be a register in range [d0, d15]";
4614
4.82k
  case ARMAsmParser::Match_GPR:
4615
59
    return "operand must be a register in range [r0, r15]";
4616
4.82k
  case ARMAsmParser::Match_GPRwithAPSR:
4617
0
    return "operand must be a register in range [r0, r14] or apsr_nzcv";
4618
4.82k
  case ARMAsmParser::Match_QPR:
4619
26
    return "operand must be a register in range [q0, q15]";
4620
4.82k
  case ARMAsmParser::Match_SPR_8:
4621
2
    return "operand must be a register in range [s0, s15]";
4622
4.82k
  case ARMAsmParser::Match_SPR:
4623
4
    return "operand must be a register in range [s0, s31]";
4624
4.82k
  case ARMAsmParser::Match_AlignedMemory16:
4625
48
    return "alignment must be 16 or omitted";
4626
4.82k
  case ARMAsmParser::Match_AlignedMemory32:
4627
84
    return "alignment must be 32 or omitted";
4628
4.82k
  case ARMAsmParser::Match_AlignedMemory64:
4629
432
    return "alignment must be 64 or omitted";
4630
4.82k
  case ARMAsmParser::Match_AlignedMemory64or128:
4631
213
    return "alignment must be 64, 128 or omitted";
4632
4.82k
  case ARMAsmParser::Match_AlignedMemory64or128or256:
4633
150
    return "alignment must be 64, 128, 256 or omitted";
4634
4.82k
  case ARMAsmParser::Match_AlignedMemoryNone:
4635
180
    return "alignment must be omitted";
4636
4.82k
  case ARMAsmParser::Match_DupAlignedMemory16:
4637
48
    return "alignment must be 16 or omitted";
4638
4.82k
  case ARMAsmParser::Match_DupAlignedMemory32:
4639
72
    return "alignment must be 32 or omitted";
4640
4.82k
  case ARMAsmParser::Match_DupAlignedMemory64:
4641
48
    return "alignment must be 64 or omitted";
4642
4.82k
  case ARMAsmParser::Match_DupAlignedMemory64or128:
4643
18
    return "alignment must be 64, 128 or omitted";
4644
4.82k
  case ARMAsmParser::Match_DupAlignedMemoryNone:
4645
120
    return "alignment must be omitted";
4646
4.82k
  case ARMAsmParser::Match_Imm0_15:
4647
15
    return "operand must be an immediate in the range [0,15]";
4648
4.82k
  case ARMAsmParser::Match_Imm0_1:
4649
4
    return "operand must be an immediate in the range [0,1]";
4650
4.82k
  case ARMAsmParser::Match_Imm0_239:
4651
4
    return "operand must be an immediate in the range [0,239]";
4652
4.82k
  case ARMAsmParser::Match_Imm0_255:
4653
23
    return "operand must be an immediate in the range [0,255]";
4654
4.82k
  case ARMAsmParser::Match_Imm0_31:
4655
8
    return "operand must be an immediate in the range [0,31]";
4656
4.82k
  case ARMAsmParser::Match_Imm0_32:
4657
0
    return "operand must be an immediate in the range [0,32]";
4658
4.82k
  case ARMAsmParser::Match_Imm0_3:
4659
0
    return "operand must be an immediate in the range [0,3]";
4660
4.82k
  case ARMAsmParser::Match_Imm0_63:
4661
2
    return "operand must be an immediate in the range [0,63]";
4662
4.82k
  case ARMAsmParser::Match_Imm0_65535:
4663
6
    return "operand must be an immediate in the range [0,65535]";
4664
4.82k
  case ARMAsmParser::Match_Imm0_65535Expr:
4665
8
    return "operand must be an immediate in the range [0,0xffff] or a relocatable expression";
4666
4.82k
  case ARMAsmParser::Match_Imm0_7:
4667
30
    return "operand must be an immediate in the range [0,7]";
4668
4.82k
  case ARMAsmParser::Match_Imm16:
4669
0
    return "operand must be an immediate in the range [16,16]";
4670
4.82k
  case ARMAsmParser::Match_Imm1_15:
4671
0
    return "operand must be an immediate in the range [1,15]";
4672
4.82k
  case ARMAsmParser::Match_ImmRange1_16:
4673
4
    return "operand must be an immediate in the range [1,16]";
4674
4.82k
  case ARMAsmParser::Match_Imm1_31:
4675
4
    return "operand must be an immediate in the range [1,31]";
4676
4.82k
  case ARMAsmParser::Match_ImmRange1_32:
4677
4
    return "operand must be an immediate in the range [1,32]";
4678
4.82k
  case ARMAsmParser::Match_Imm1_7:
4679
0
    return "operand must be an immediate in the range [1,7]";
4680
4.82k
  case ARMAsmParser::Match_Imm24bit:
4681
2
    return "operand must be an immediate in the range [0,0xffffff]";
4682
4.82k
  case ARMAsmParser::Match_Imm256_65535Expr:
4683
5
    return "operand must be an immediate in the range [256,65535]";
4684
4.82k
  case ARMAsmParser::Match_Imm32:
4685
0
    return "operand must be an immediate in the range [32,32]";
4686
4.82k
  case ARMAsmParser::Match_Imm8:
4687
0
    return "operand must be an immediate in the range [8,8]";
4688
4.82k
  case ARMAsmParser::Match_Imm8_255:
4689
0
    return "operand must be an immediate in the range [8,255]";
4690
4.82k
  case ARMAsmParser::Match_PKHLSLImm:
4691
0
    return "operand must be an immediate in the range [0,31]";
4692
4.82k
  case ARMAsmParser::Match_SPRRegList:
4693
8
    return "operand must be a list of registers in range [s0, s31]";
4694
4.82k
  case ARMAsmParser::Match_SetEndImm:
4695
0
    return "operand must be an immediate in the range [0,1]";
4696
4.82k
  case ARMAsmParser::Match_ImmThumbSR:
4697
6
    return "operand must be an immediate in the range [1,32]";
4698
4.82k
  case ARMAsmParser::Match_ComplexRotationEven:
4699
24
    return "complex rotation must be 0, 90, 180 or 270";
4700
4.82k
  case ARMAsmParser::Match_ComplexRotationOdd:
4701
20
    return "complex rotation must be 90 or 270";
4702
4.82k
  case ARMAsmParser::Match_Imm0_4095:
4703
5
    return "operand must be an immediate in the range [0,4095]";
4704
4.82k
  case ARMAsmParser::Match_ShrImm16: