Coverage Report

Created: 2019-02-15 18:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenFastISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* "Fast" Instruction Selector for the ARM target                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
// FastEmit Immediate Predicate functions.
11
503
static bool Predicate_mod_imm(int64_t Imm) {
12
503
13
503
    return ARM_AM::getSOImmVal(Imm) != -1;
14
503
  
15
503
}
16
0
static bool Predicate_imm0_65535(int64_t Imm) {
17
0
18
0
  return Imm >= 0 && Imm < 65536;
19
0
20
0
}
21
461
static bool Predicate_imm0_7(int64_t Imm) {
22
461
23
461
  return Imm >= 0 && 
Imm < 8448
;
24
461
25
461
}
26
461
static bool Predicate_imm8_255(int64_t Imm) {
27
461
28
461
  return Imm >= 8 && 
Imm < 256420
;
29
461
30
461
}
31
461
static bool Predicate_imm0_255(int64_t Imm) {
32
461
 return Imm >= 0 && 
Imm < 256448
;
33
461
}
34
461
static bool Predicate_t2_so_imm(int64_t Imm) {
35
461
36
461
    return ARM_AM::getT2SOImmVal(Imm) != -1;
37
461
  
38
461
}
39
235
static bool Predicate_imm0_4095(int64_t Imm) {
40
235
41
235
  return Imm >= 0 && 
Imm < 4096223
;
42
235
43
235
}
44
46
static bool Predicate_imm1_31(int64_t Imm) {
45
46
 return Imm > 0 && 
Imm < 3234
;
46
46
}
47
40
static bool Predicate_imm0_31(int64_t Imm) {
48
40
49
40
  return Imm >= 0 && 
Imm < 3228
;
50
40
51
40
}
52
40
static bool Predicate_shr_imm8(int64_t Imm) {
53
40
 return Imm > 0 && 
Imm <= 828
;
54
40
}
55
40
static bool Predicate_shr_imm16(int64_t Imm) {
56
40
 return Imm > 0 && 
Imm <= 1628
;
57
40
}
58
40
static bool Predicate_shr_imm32(int64_t Imm) {
59
40
 return Imm > 0 && 
Imm <= 3228
;
60
40
}
61
40
static bool Predicate_VectorIndex32(int64_t Imm) {
62
40
63
40
  return ((uint64_t)Imm) < 2;
64
40
65
40
}
66
0
static bool Predicate_t2_so_imm_neg(int64_t Imm) {
67
0
68
0
  return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
69
0
70
0
}
71
72
73
// FastEmit functions for ARMISD::CALL.
74
75
0
unsigned fastEmit_ARMISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
76
0
  if (RetVT.SimpleTy != MVT::isVoid)
77
0
    return 0;
78
0
  if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
79
0
    return fastEmitInst_r(ARM::BLX, &ARM::GPRRegClass, Op0, Op0IsKill);
80
0
  }
81
0
  return 0;
82
0
}
83
84
unsigned fastEmit_ARMISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
85
  switch (VT.SimpleTy) {
86
  case MVT::i32: return fastEmit_ARMISD_CALL_MVT_i32_r(RetVT, Op0, Op0IsKill);
87
  default: return 0;
88
  }
89
}
90
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// FastEmit functions for ARMISD::CALL_NOLINK.
92
93
0
unsigned fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
94
0
  if (RetVT.SimpleTy != MVT::isVoid)
95
0
    return 0;
96
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
97
0
    return fastEmitInst_r(ARM::tBX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
98
0
  }
99
0
  if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
100
0
    return fastEmitInst_r(ARM::BMOVPCRX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
101
0
  }
102
0
  if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
103
0
    return fastEmitInst_r(ARM::BX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
104
0
  }
105
0
  return 0;
106
0
}
107
108
unsigned fastEmit_ARMISD_CALL_NOLINK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
109
  switch (VT.SimpleTy) {
110
  case MVT::i32: return fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(RetVT, Op0, Op0IsKill);
111
  default: return 0;
112
  }
113
}
114
115
// FastEmit functions for ARMISD::CALL_PRED.
116
117
0
unsigned fastEmit_ARMISD_CALL_PRED_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
118
0
  if (RetVT.SimpleTy != MVT::isVoid)
119
0
    return 0;
120
0
  if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
121
0
    return fastEmitInst_r(ARM::BLX_pred, &ARM::GPRRegClass, Op0, Op0IsKill);
122
0
  }
123
0
  return 0;
124
0
}
125
126
unsigned fastEmit_ARMISD_CALL_PRED_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
127
  switch (VT.SimpleTy) {
128
  case MVT::i32: return fastEmit_ARMISD_CALL_PRED_MVT_i32_r(RetVT, Op0, Op0IsKill);
129
  default: return 0;
130
  }
131
}
132
133
// FastEmit functions for ARMISD::RRX.
134
135
0
unsigned fastEmit_ARMISD_RRX_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
136
0
  if (RetVT.SimpleTy != MVT::i32)
137
0
    return 0;
138
0
  if ((Subtarget->isThumb2())) {
139
0
    return fastEmitInst_r(ARM::t2RRX, &ARM::rGPRRegClass, Op0, Op0IsKill);
140
0
  }
141
0
  if ((!Subtarget->isThumb())) {
142
0
    return fastEmitInst_r(ARM::RRX, &ARM::GPRRegClass, Op0, Op0IsKill);
143
0
  }
144
0
  return 0;
145
0
}
146
147
unsigned fastEmit_ARMISD_RRX_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
148
  switch (VT.SimpleTy) {
149
  case MVT::i32: return fastEmit_ARMISD_RRX_MVT_i32_r(RetVT, Op0, Op0IsKill);
150
  default: return 0;
151
  }
152
}
153
154
// FastEmit functions for ARMISD::SRA_FLAG.
155
156
0
unsigned fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
157
0
  if (RetVT.SimpleTy != MVT::i32)
158
0
    return 0;
159
0
  if ((Subtarget->isThumb2())) {
160
0
    return fastEmitInst_r(ARM::t2MOVsra_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
161
0
  }
162
0
  if ((!Subtarget->isThumb())) {
163
0
    return fastEmitInst_r(ARM::MOVsra_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
164
0
  }
165
0
  return 0;
166
0
}
167
168
unsigned fastEmit_ARMISD_SRA_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
169
  switch (VT.SimpleTy) {
170
  case MVT::i32: return fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
171
  default: return 0;
172
  }
173
}
174
175
// FastEmit functions for ARMISD::SRL_FLAG.
176
177
0
unsigned fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
178
0
  if (RetVT.SimpleTy != MVT::i32)
179
0
    return 0;
180
0
  if ((Subtarget->isThumb2())) {
181
0
    return fastEmitInst_r(ARM::t2MOVsrl_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
182
0
  }
183
0
  if ((!Subtarget->isThumb())) {
184
0
    return fastEmitInst_r(ARM::MOVsrl_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
185
0
  }
186
0
  return 0;
187
0
}
188
189
unsigned fastEmit_ARMISD_SRL_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
190
  switch (VT.SimpleTy) {
191
  case MVT::i32: return fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
192
  default: return 0;
193
  }
194
}
195
196
// FastEmit functions for ARMISD::TC_RETURN.
197
198
0
unsigned fastEmit_ARMISD_TC_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
199
0
  if (RetVT.SimpleTy != MVT::isVoid)
200
0
    return 0;
201
0
  return fastEmitInst_r(ARM::TCRETURNri, &ARM::tcGPRRegClass, Op0, Op0IsKill);
202
0
}
203
204
unsigned fastEmit_ARMISD_TC_RETURN_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
205
  switch (VT.SimpleTy) {
206
  case MVT::i32: return fastEmit_ARMISD_TC_RETURN_MVT_i32_r(RetVT, Op0, Op0IsKill);
207
  default: return 0;
208
  }
209
}
210
211
// FastEmit functions for ARMISD::VCEQZ.
212
213
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
214
0
  if (RetVT.SimpleTy != MVT::v8i8)
215
0
    return 0;
216
0
  if ((Subtarget->hasNEON())) {
217
0
    return fastEmitInst_r(ARM::VCEQzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
218
0
  }
219
0
  return 0;
220
0
}
221
222
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
223
0
  if (RetVT.SimpleTy != MVT::v16i8)
224
0
    return 0;
225
0
  if ((Subtarget->hasNEON())) {
226
0
    return fastEmitInst_r(ARM::VCEQzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
227
0
  }
228
0
  return 0;
229
0
}
230
231
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
232
0
  if (RetVT.SimpleTy != MVT::v4i16)
233
0
    return 0;
234
0
  if ((Subtarget->hasNEON())) {
235
0
    return fastEmitInst_r(ARM::VCEQzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
236
0
  }
237
0
  return 0;
238
0
}
239
240
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
241
0
  if (RetVT.SimpleTy != MVT::v8i16)
242
0
    return 0;
243
0
  if ((Subtarget->hasNEON())) {
244
0
    return fastEmitInst_r(ARM::VCEQzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
245
0
  }
246
0
  return 0;
247
0
}
248
249
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
250
0
  if (RetVT.SimpleTy != MVT::v2i32)
251
0
    return 0;
252
0
  if ((Subtarget->hasNEON())) {
253
0
    return fastEmitInst_r(ARM::VCEQzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
254
0
  }
255
0
  return 0;
256
0
}
257
258
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
259
0
  if (RetVT.SimpleTy != MVT::v4i32)
260
0
    return 0;
261
0
  if ((Subtarget->hasNEON())) {
262
0
    return fastEmitInst_r(ARM::VCEQzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
263
0
  }
264
0
  return 0;
265
0
}
266
267
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
268
0
  if (RetVT.SimpleTy != MVT::v4i16)
269
0
    return 0;
270
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
271
0
    return fastEmitInst_r(ARM::VCEQzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
272
0
  }
273
0
  return 0;
274
0
}
275
276
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
277
0
  if (RetVT.SimpleTy != MVT::v8i16)
278
0
    return 0;
279
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
280
0
    return fastEmitInst_r(ARM::VCEQzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
281
0
  }
282
0
  return 0;
283
0
}
284
285
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
286
0
  if (RetVT.SimpleTy != MVT::v2i32)
287
0
    return 0;
288
0
  if ((Subtarget->hasNEON())) {
289
0
    return fastEmitInst_r(ARM::VCEQzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
290
0
  }
291
0
  return 0;
292
0
}
293
294
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
295
0
  if (RetVT.SimpleTy != MVT::v4i32)
296
0
    return 0;
297
0
  if ((Subtarget->hasNEON())) {
298
0
    return fastEmitInst_r(ARM::VCEQzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
299
0
  }
300
0
  return 0;
301
0
}
302
303
unsigned fastEmit_ARMISD_VCEQZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
304
  switch (VT.SimpleTy) {
305
  case MVT::v8i8: return fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
306
  case MVT::v16i8: return fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
307
  case MVT::v4i16: return fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
308
  case MVT::v8i16: return fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
309
  case MVT::v2i32: return fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
310
  case MVT::v4i32: return fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
311
  case MVT::v4f16: return fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
312
  case MVT::v8f16: return fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
313
  case MVT::v2f32: return fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
314
  case MVT::v4f32: return fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
315
  default: return 0;
316
  }
317
}
318
319
// FastEmit functions for ARMISD::VCGEZ.
320
321
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
322
0
  if (RetVT.SimpleTy != MVT::v8i8)
323
0
    return 0;
324
0
  if ((Subtarget->hasNEON())) {
325
0
    return fastEmitInst_r(ARM::VCGEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
326
0
  }
327
0
  return 0;
328
0
}
329
330
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
331
0
  if (RetVT.SimpleTy != MVT::v16i8)
332
0
    return 0;
333
0
  if ((Subtarget->hasNEON())) {
334
0
    return fastEmitInst_r(ARM::VCGEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
335
0
  }
336
0
  return 0;
337
0
}
338
339
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
340
0
  if (RetVT.SimpleTy != MVT::v4i16)
341
0
    return 0;
342
0
  if ((Subtarget->hasNEON())) {
343
0
    return fastEmitInst_r(ARM::VCGEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
344
0
  }
345
0
  return 0;
346
0
}
347
348
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
349
0
  if (RetVT.SimpleTy != MVT::v8i16)
350
0
    return 0;
351
0
  if ((Subtarget->hasNEON())) {
352
0
    return fastEmitInst_r(ARM::VCGEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
353
0
  }
354
0
  return 0;
355
0
}
356
357
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
358
0
  if (RetVT.SimpleTy != MVT::v2i32)
359
0
    return 0;
360
0
  if ((Subtarget->hasNEON())) {
361
0
    return fastEmitInst_r(ARM::VCGEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
362
0
  }
363
0
  return 0;
364
0
}
365
366
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
367
0
  if (RetVT.SimpleTy != MVT::v4i32)
368
0
    return 0;
369
0
  if ((Subtarget->hasNEON())) {
370
0
    return fastEmitInst_r(ARM::VCGEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
371
0
  }
372
0
  return 0;
373
0
}
374
375
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
376
0
  if (RetVT.SimpleTy != MVT::v4i16)
377
0
    return 0;
378
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
379
0
    return fastEmitInst_r(ARM::VCGEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
380
0
  }
381
0
  return 0;
382
0
}
383
384
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
385
0
  if (RetVT.SimpleTy != MVT::v8i16)
386
0
    return 0;
387
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
388
0
    return fastEmitInst_r(ARM::VCGEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
389
0
  }
390
0
  return 0;
391
0
}
392
393
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
394
0
  if (RetVT.SimpleTy != MVT::v2i32)
395
0
    return 0;
396
0
  if ((Subtarget->hasNEON())) {
397
0
    return fastEmitInst_r(ARM::VCGEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
398
0
  }
399
0
  return 0;
400
0
}
401
402
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
403
0
  if (RetVT.SimpleTy != MVT::v4i32)
404
0
    return 0;
405
0
  if ((Subtarget->hasNEON())) {
406
0
    return fastEmitInst_r(ARM::VCGEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
407
0
  }
408
0
  return 0;
409
0
}
410
411
unsigned fastEmit_ARMISD_VCGEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
412
  switch (VT.SimpleTy) {
413
  case MVT::v8i8: return fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
414
  case MVT::v16i8: return fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
415
  case MVT::v4i16: return fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
416
  case MVT::v8i16: return fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
417
  case MVT::v2i32: return fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
418
  case MVT::v4i32: return fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
419
  case MVT::v4f16: return fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
420
  case MVT::v8f16: return fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
421
  case MVT::v2f32: return fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
422
  case MVT::v4f32: return fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
423
  default: return 0;
424
  }
425
}
426
427
// FastEmit functions for ARMISD::VCGTZ.
428
429
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
430
0
  if (RetVT.SimpleTy != MVT::v8i8)
431
0
    return 0;
432
0
  if ((Subtarget->hasNEON())) {
433
0
    return fastEmitInst_r(ARM::VCGTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
434
0
  }
435
0
  return 0;
436
0
}
437
438
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
439
0
  if (RetVT.SimpleTy != MVT::v16i8)
440
0
    return 0;
441
0
  if ((Subtarget->hasNEON())) {
442
0
    return fastEmitInst_r(ARM::VCGTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
443
0
  }
444
0
  return 0;
445
0
}
446
447
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
448
0
  if (RetVT.SimpleTy != MVT::v4i16)
449
0
    return 0;
450
0
  if ((Subtarget->hasNEON())) {
451
0
    return fastEmitInst_r(ARM::VCGTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
452
0
  }
453
0
  return 0;
454
0
}
455
456
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
457
0
  if (RetVT.SimpleTy != MVT::v8i16)
458
0
    return 0;
459
0
  if ((Subtarget->hasNEON())) {
460
0
    return fastEmitInst_r(ARM::VCGTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
461
0
  }
462
0
  return 0;
463
0
}
464
465
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
466
0
  if (RetVT.SimpleTy != MVT::v2i32)
467
0
    return 0;
468
0
  if ((Subtarget->hasNEON())) {
469
0
    return fastEmitInst_r(ARM::VCGTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
470
0
  }
471
0
  return 0;
472
0
}
473
474
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
475
0
  if (RetVT.SimpleTy != MVT::v4i32)
476
0
    return 0;
477
0
  if ((Subtarget->hasNEON())) {
478
0
    return fastEmitInst_r(ARM::VCGTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
479
0
  }
480
0
  return 0;
481
0
}
482
483
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
484
0
  if (RetVT.SimpleTy != MVT::v4i16)
485
0
    return 0;
486
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
487
0
    return fastEmitInst_r(ARM::VCGTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
488
0
  }
489
0
  return 0;
490
0
}
491
492
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
493
0
  if (RetVT.SimpleTy != MVT::v8i16)
494
0
    return 0;
495
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
496
0
    return fastEmitInst_r(ARM::VCGTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
497
0
  }
498
0
  return 0;
499
0
}
500
501
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
502
0
  if (RetVT.SimpleTy != MVT::v2i32)
503
0
    return 0;
504
0
  if ((Subtarget->hasNEON())) {
505
0
    return fastEmitInst_r(ARM::VCGTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
506
0
  }
507
0
  return 0;
508
0
}
509
510
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
511
0
  if (RetVT.SimpleTy != MVT::v4i32)
512
0
    return 0;
513
0
  if ((Subtarget->hasNEON())) {
514
0
    return fastEmitInst_r(ARM::VCGTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
515
0
  }
516
0
  return 0;
517
0
}
518
519
unsigned fastEmit_ARMISD_VCGTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
520
  switch (VT.SimpleTy) {
521
  case MVT::v8i8: return fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
522
  case MVT::v16i8: return fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
523
  case MVT::v4i16: return fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
524
  case MVT::v8i16: return fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
525
  case MVT::v2i32: return fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
526
  case MVT::v4i32: return fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
527
  case MVT::v4f16: return fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
528
  case MVT::v8f16: return fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
529
  case MVT::v2f32: return fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
530
  case MVT::v4f32: return fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
531
  default: return 0;
532
  }
533
}
534
535
// FastEmit functions for ARMISD::VCLEZ.
536
537
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
538
0
  if (RetVT.SimpleTy != MVT::v8i8)
539
0
    return 0;
540
0
  if ((Subtarget->hasNEON())) {
541
0
    return fastEmitInst_r(ARM::VCLEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
542
0
  }
543
0
  return 0;
544
0
}
545
546
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
547
0
  if (RetVT.SimpleTy != MVT::v16i8)
548
0
    return 0;
549
0
  if ((Subtarget->hasNEON())) {
550
0
    return fastEmitInst_r(ARM::VCLEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
551
0
  }
552
0
  return 0;
553
0
}
554
555
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
556
0
  if (RetVT.SimpleTy != MVT::v4i16)
557
0
    return 0;
558
0
  if ((Subtarget->hasNEON())) {
559
0
    return fastEmitInst_r(ARM::VCLEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
560
0
  }
561
0
  return 0;
562
0
}
563
564
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
565
0
  if (RetVT.SimpleTy != MVT::v8i16)
566
0
    return 0;
567
0
  if ((Subtarget->hasNEON())) {
568
0
    return fastEmitInst_r(ARM::VCLEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
569
0
  }
570
0
  return 0;
571
0
}
572
573
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
574
0
  if (RetVT.SimpleTy != MVT::v2i32)
575
0
    return 0;
576
0
  if ((Subtarget->hasNEON())) {
577
0
    return fastEmitInst_r(ARM::VCLEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
578
0
  }
579
0
  return 0;
580
0
}
581
582
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
583
0
  if (RetVT.SimpleTy != MVT::v4i32)
584
0
    return 0;
585
0
  if ((Subtarget->hasNEON())) {
586
0
    return fastEmitInst_r(ARM::VCLEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
587
0
  }
588
0
  return 0;
589
0
}
590
591
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
592
0
  if (RetVT.SimpleTy != MVT::v4i16)
593
0
    return 0;
594
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
595
0
    return fastEmitInst_r(ARM::VCLEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
596
0
  }
597
0
  return 0;
598
0
}
599
600
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
601
0
  if (RetVT.SimpleTy != MVT::v8i16)
602
0
    return 0;
603
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
604
0
    return fastEmitInst_r(ARM::VCLEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
605
0
  }
606
0
  return 0;
607
0
}
608
609
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
610
0
  if (RetVT.SimpleTy != MVT::v2i32)
611
0
    return 0;
612
0
  if ((Subtarget->hasNEON())) {
613
0
    return fastEmitInst_r(ARM::VCLEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
614
0
  }
615
0
  return 0;
616
0
}
617
618
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
619
0
  if (RetVT.SimpleTy != MVT::v4i32)
620
0
    return 0;
621
0
  if ((Subtarget->hasNEON())) {
622
0
    return fastEmitInst_r(ARM::VCLEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
623
0
  }
624
0
  return 0;
625
0
}
626
627
unsigned fastEmit_ARMISD_VCLEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
628
  switch (VT.SimpleTy) {
629
  case MVT::v8i8: return fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
630
  case MVT::v16i8: return fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
631
  case MVT::v4i16: return fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
632
  case MVT::v8i16: return fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
633
  case MVT::v2i32: return fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
634
  case MVT::v4i32: return fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
635
  case MVT::v4f16: return fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
636
  case MVT::v8f16: return fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
637
  case MVT::v2f32: return fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
638
  case MVT::v4f32: return fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
639
  default: return 0;
640
  }
641
}
642
643
// FastEmit functions for ARMISD::VCLTZ.
644
645
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
646
0
  if (RetVT.SimpleTy != MVT::v8i8)
647
0
    return 0;
648
0
  if ((Subtarget->hasNEON())) {
649
0
    return fastEmitInst_r(ARM::VCLTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
650
0
  }
651
0
  return 0;
652
0
}
653
654
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
655
0
  if (RetVT.SimpleTy != MVT::v16i8)
656
0
    return 0;
657
0
  if ((Subtarget->hasNEON())) {
658
0
    return fastEmitInst_r(ARM::VCLTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
659
0
  }
660
0
  return 0;
661
0
}
662
663
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
664
0
  if (RetVT.SimpleTy != MVT::v4i16)
665
0
    return 0;
666
0
  if ((Subtarget->hasNEON())) {
667
0
    return fastEmitInst_r(ARM::VCLTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
668
0
  }
669
0
  return 0;
670
0
}
671
672
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
673
0
  if (RetVT.SimpleTy != MVT::v8i16)
674
0
    return 0;
675
0
  if ((Subtarget->hasNEON())) {
676
0
    return fastEmitInst_r(ARM::VCLTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
677
0
  }
678
0
  return 0;
679
0
}
680
681
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
682
0
  if (RetVT.SimpleTy != MVT::v2i32)
683
0
    return 0;
684
0
  if ((Subtarget->hasNEON())) {
685
0
    return fastEmitInst_r(ARM::VCLTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
686
0
  }
687
0
  return 0;
688
0
}
689
690
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
691
0
  if (RetVT.SimpleTy != MVT::v4i32)
692
0
    return 0;
693
0
  if ((Subtarget->hasNEON())) {
694
0
    return fastEmitInst_r(ARM::VCLTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
695
0
  }
696
0
  return 0;
697
0
}
698
699
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
700
0
  if (RetVT.SimpleTy != MVT::v4i16)
701
0
    return 0;
702
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
703
0
    return fastEmitInst_r(ARM::VCLTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
704
0
  }
705
0
  return 0;
706
0
}
707
708
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
709
0
  if (RetVT.SimpleTy != MVT::v8i16)
710
0
    return 0;
711
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
712
0
    return fastEmitInst_r(ARM::VCLTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
713
0
  }
714
0
  return 0;
715
0
}
716
717
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
718
0
  if (RetVT.SimpleTy != MVT::v2i32)
719
0
    return 0;
720
0
  if ((Subtarget->hasNEON())) {
721
0
    return fastEmitInst_r(ARM::VCLTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
722
0
  }
723
0
  return 0;
724
0
}
725
726
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
727
0
  if (RetVT.SimpleTy != MVT::v4i32)
728
0
    return 0;
729
0
  if ((Subtarget->hasNEON())) {
730
0
    return fastEmitInst_r(ARM::VCLTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
731
0
  }
732
0
  return 0;
733
0
}
734
735
unsigned fastEmit_ARMISD_VCLTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
736
  switch (VT.SimpleTy) {
737
  case MVT::v8i8: return fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
738
  case MVT::v16i8: return fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
739
  case MVT::v4i16: return fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
740
  case MVT::v8i16: return fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
741
  case MVT::v2i32: return fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
742
  case MVT::v4i32: return fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
743
  case MVT::v4f16: return fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
744
  case MVT::v8f16: return fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
745
  case MVT::v2f32: return fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
746
  case MVT::v4f32: return fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
747
  default: return 0;
748
  }
749
}
750
751
// FastEmit functions for ARMISD::VDUP.
752
753
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
754
0
  if ((Subtarget->hasNEON())) {
755
0
    return fastEmitInst_r(ARM::VDUP8d, &ARM::DPRRegClass, Op0, Op0IsKill);
756
0
  }
757
0
  return 0;
758
0
}
759
760
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
761
0
  if ((Subtarget->hasNEON())) {
762
0
    return fastEmitInst_r(ARM::VDUP8q, &ARM::QPRRegClass, Op0, Op0IsKill);
763
0
  }
764
0
  return 0;
765
0
}
766
767
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
768
0
  if ((Subtarget->hasNEON())) {
769
0
    return fastEmitInst_r(ARM::VDUP16d, &ARM::DPRRegClass, Op0, Op0IsKill);
770
0
  }
771
0
  return 0;
772
0
}
773
774
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
775
0
  if ((Subtarget->hasNEON())) {
776
0
    return fastEmitInst_r(ARM::VDUP16q, &ARM::QPRRegClass, Op0, Op0IsKill);
777
0
  }
778
0
  return 0;
779
0
}
780
781
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
782
0
  if ((!Subtarget->hasSlowVDUP32()) && (Subtarget->hasNEON())) {
783
0
    return fastEmitInst_r(ARM::VDUP32d, &ARM::DPRRegClass, Op0, Op0IsKill);
784
0
  }
785
0
  return 0;
786
0
}
787
788
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
789
0
  if ((Subtarget->hasNEON())) {
790
0
    return fastEmitInst_r(ARM::VDUP32q, &ARM::QPRRegClass, Op0, Op0IsKill);
791
0
  }
792
0
  return 0;
793
0
}
794
795
unsigned fastEmit_ARMISD_VDUP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
796
switch (RetVT.SimpleTy) {
797
  case MVT::v8i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(Op0, Op0IsKill);
798
  case MVT::v16i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(Op0, Op0IsKill);
799
  case MVT::v4i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(Op0, Op0IsKill);
800
  case MVT::v8i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(Op0, Op0IsKill);
801
  case MVT::v2i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(Op0, Op0IsKill);
802
  case MVT::v4i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill);
803
  default: return 0;
804
}
805
}
806
807
unsigned fastEmit_ARMISD_VDUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
808
  switch (VT.SimpleTy) {
809
  case MVT::i32: return fastEmit_ARMISD_VDUP_MVT_i32_r(RetVT, Op0, Op0IsKill);
810
  default: return 0;
811
  }
812
}
813
814
// FastEmit functions for ARMISD::VMOVSR.
815
816
0
unsigned fastEmit_ARMISD_VMOVSR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
817
0
  if (RetVT.SimpleTy != MVT::f32)
818
0
    return 0;
819
0
  if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) {
820
0
    return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
821
0
  }
822
0
  return 0;
823
0
}
824
825
unsigned fastEmit_ARMISD_VMOVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
826
  switch (VT.SimpleTy) {
827
  case MVT::i32: return fastEmit_ARMISD_VMOVSR_MVT_i32_r(RetVT, Op0, Op0IsKill);
828
  default: return 0;
829
  }
830
}
831
832
// FastEmit functions for ARMISD::VMOVhr.
833
834
0
unsigned fastEmit_ARMISD_VMOVhr_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
835
0
  if (RetVT.SimpleTy != MVT::f16)
836
0
    return 0;
837
0
  if ((Subtarget->hasFullFP16())) {
838
0
    return fastEmitInst_r(ARM::VMOVHR, &ARM::HPRRegClass, Op0, Op0IsKill);
839
0
  }
840
0
  return 0;
841
0
}
842
843
unsigned fastEmit_ARMISD_VMOVhr_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
844
  switch (VT.SimpleTy) {
845
  case MVT::i32: return fastEmit_ARMISD_VMOVhr_MVT_i32_r(RetVT, Op0, Op0IsKill);
846
  default: return 0;
847
  }
848
}
849
850
// FastEmit functions for ARMISD::VMOVrh.
851
852
0
unsigned fastEmit_ARMISD_VMOVrh_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
853
0
  if (RetVT.SimpleTy != MVT::i32)
854
0
    return 0;
855
0
  if ((Subtarget->hasFullFP16())) {
856
0
    return fastEmitInst_r(ARM::VMOVRH, &ARM::GPRRegClass, Op0, Op0IsKill);
857
0
  }
858
0
  return 0;
859
0
}
860
861
unsigned fastEmit_ARMISD_VMOVrh_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
862
  switch (VT.SimpleTy) {
863
  case MVT::f16: return fastEmit_ARMISD_VMOVrh_MVT_f16_r(RetVT, Op0, Op0IsKill);
864
  default: return 0;
865
  }
866
}
867
868
// FastEmit functions for ARMISD::VREV16.
869
870
0
unsigned fastEmit_ARMISD_VREV16_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
871
0
  if (RetVT.SimpleTy != MVT::v8i8)
872
0
    return 0;
873
0
  if ((Subtarget->hasNEON())) {
874
0
    return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
875
0
  }
876
0
  return 0;
877
0
}
878
879
0
unsigned fastEmit_ARMISD_VREV16_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
880
0
  if (RetVT.SimpleTy != MVT::v16i8)
881
0
    return 0;
882
0
  if ((Subtarget->hasNEON())) {
883
0
    return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
884
0
  }
885
0
  return 0;
886
0
}
887
888
unsigned fastEmit_ARMISD_VREV16_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
889
  switch (VT.SimpleTy) {
890
  case MVT::v8i8: return fastEmit_ARMISD_VREV16_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
891
  case MVT::v16i8: return fastEmit_ARMISD_VREV16_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
892
  default: return 0;
893
  }
894
}
895
896
// FastEmit functions for ARMISD::VREV32.
897
898
0
unsigned fastEmit_ARMISD_VREV32_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
899
0
  if (RetVT.SimpleTy != MVT::v8i8)
900
0
    return 0;
901
0
  if ((Subtarget->hasNEON())) {
902
0
    return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
903
0
  }
904
0
  return 0;
905
0
}
906
907
0
unsigned fastEmit_ARMISD_VREV32_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
908
0
  if (RetVT.SimpleTy != MVT::v16i8)
909
0
    return 0;
910
0
  if ((Subtarget->hasNEON())) {
911
0
    return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
912
0
  }
913
0
  return 0;
914
0
}
915
916
0
unsigned fastEmit_ARMISD_VREV32_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
917
0
  if (RetVT.SimpleTy != MVT::v4i16)
918
0
    return 0;
919
0
  if ((Subtarget->hasNEON())) {
920
0
    return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
921
0
  }
922
0
  return 0;
923
0
}
924
925
0
unsigned fastEmit_ARMISD_VREV32_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
926
0
  if (RetVT.SimpleTy != MVT::v8i16)
927
0
    return 0;
928
0
  if ((Subtarget->hasNEON())) {
929
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
930
0
  }
931
0
  return 0;
932
0
}
933
934
unsigned fastEmit_ARMISD_VREV32_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
935
  switch (VT.SimpleTy) {
936
  case MVT::v8i8: return fastEmit_ARMISD_VREV32_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
937
  case MVT::v16i8: return fastEmit_ARMISD_VREV32_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
938
  case MVT::v4i16: return fastEmit_ARMISD_VREV32_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
939
  case MVT::v8i16: return fastEmit_ARMISD_VREV32_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
940
  default: return 0;
941
  }
942
}
943
944
// FastEmit functions for ARMISD::VREV64.
945
946
0
unsigned fastEmit_ARMISD_VREV64_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
947
0
  if (RetVT.SimpleTy != MVT::v8i8)
948
0
    return 0;
949
0
  if ((Subtarget->hasNEON())) {
950
0
    return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
951
0
  }
952
0
  return 0;
953
0
}
954
955
0
unsigned fastEmit_ARMISD_VREV64_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
956
0
  if (RetVT.SimpleTy != MVT::v16i8)
957
0
    return 0;
958
0
  if ((Subtarget->hasNEON())) {
959
0
    return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
960
0
  }
961
0
  return 0;
962
0
}
963
964
0
unsigned fastEmit_ARMISD_VREV64_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
965
0
  if (RetVT.SimpleTy != MVT::v4i16)
966
0
    return 0;
967
0
  if ((Subtarget->hasNEON())) {
968
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
969
0
  }
970
0
  return 0;
971
0
}
972
973
0
unsigned fastEmit_ARMISD_VREV64_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
974
0
  if (RetVT.SimpleTy != MVT::v8i16)
975
0
    return 0;
976
0
  if ((Subtarget->hasNEON())) {
977
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
978
0
  }
979
0
  return 0;
980
0
}
981
982
0
unsigned fastEmit_ARMISD_VREV64_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
983
0
  if (RetVT.SimpleTy != MVT::v2i32)
984
0
    return 0;
985
0
  if ((Subtarget->hasNEON())) {
986
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
987
0
  }
988
0
  return 0;
989
0
}
990
991
0
unsigned fastEmit_ARMISD_VREV64_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
992
0
  if (RetVT.SimpleTy != MVT::v4i32)
993
0
    return 0;
994
0
  if ((Subtarget->hasNEON())) {
995
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
996
0
  }
997
0
  return 0;
998
0
}
999
1000
0
unsigned fastEmit_ARMISD_VREV64_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1001
0
  if (RetVT.SimpleTy != MVT::v4f16)
1002
0
    return 0;
1003
0
  return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1004
0
}
1005
1006
0
unsigned fastEmit_ARMISD_VREV64_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1007
0
  if (RetVT.SimpleTy != MVT::v8f16)
1008
0
    return 0;
1009
0
  return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1010
0
}
1011
1012
0
unsigned fastEmit_ARMISD_VREV64_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1013
0
  if (RetVT.SimpleTy != MVT::v2f32)
1014
0
    return 0;
1015
0
  return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1016
0
}
1017
1018
0
unsigned fastEmit_ARMISD_VREV64_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1019
0
  if (RetVT.SimpleTy != MVT::v4f32)
1020
0
    return 0;
1021
0
  return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1022
0
}
1023
1024
unsigned fastEmit_ARMISD_VREV64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1025
  switch (VT.SimpleTy) {
1026
  case MVT::v8i8: return fastEmit_ARMISD_VREV64_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1027
  case MVT::v16i8: return fastEmit_ARMISD_VREV64_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1028
  case MVT::v4i16: return fastEmit_ARMISD_VREV64_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1029
  case MVT::v8i16: return fastEmit_ARMISD_VREV64_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1030
  case MVT::v2i32: return fastEmit_ARMISD_VREV64_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1031
  case MVT::v4i32: return fastEmit_ARMISD_VREV64_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1032
  case MVT::v4f16: return fastEmit_ARMISD_VREV64_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
1033
  case MVT::v8f16: return fastEmit_ARMISD_VREV64_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
1034
  case MVT::v2f32: return fastEmit_ARMISD_VREV64_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
1035
  case MVT::v4f32: return fastEmit_ARMISD_VREV64_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
1036
  default: return 0;
1037
  }
1038
}
1039
1040
// FastEmit functions for ARMISD::WIN__DBZCHK.
1041
1042
0
unsigned fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1043
0
  if (RetVT.SimpleTy != MVT::isVoid)
1044
0
    return 0;
1045
0
  return fastEmitInst_r(ARM::WIN__DBZCHK, &ARM::tGPRRegClass, Op0, Op0IsKill);
1046
0
}
1047
1048
unsigned fastEmit_ARMISD_WIN__DBZCHK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1049
  switch (VT.SimpleTy) {
1050
  case MVT::i32: return fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(RetVT, Op0, Op0IsKill);
1051
  default: return 0;
1052
  }
1053
}
1054
1055
// FastEmit functions for ISD::ABS.
1056
1057
0
unsigned fastEmit_ISD_ABS_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1058
0
  if (RetVT.SimpleTy != MVT::v8i8)
1059
0
    return 0;
1060
0
  if ((Subtarget->hasNEON())) {
1061
0
    return fastEmitInst_r(ARM::VABSv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
1062
0
  }
1063
0
  return 0;
1064
0
}
1065
1066
0
unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1067
0
  if (RetVT.SimpleTy != MVT::v16i8)
1068
0
    return 0;
1069
0
  if ((Subtarget->hasNEON())) {
1070
0
    return fastEmitInst_r(ARM::VABSv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
1071
0
  }
1072
0
  return 0;
1073
0
}
1074
1075
0
unsigned fastEmit_ISD_ABS_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1076
0
  if (RetVT.SimpleTy != MVT::v4i16)
1077
0
    return 0;
1078
0
  if ((Subtarget->hasNEON())) {
1079
0
    return fastEmitInst_r(ARM::VABSv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
1080
0
  }
1081
0
  return 0;
1082
0
}
1083
1084
0
unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1085
0
  if (RetVT.SimpleTy != MVT::v8i16)
1086
0
    return 0;
1087
0
  if ((Subtarget->hasNEON())) {
1088
0
    return fastEmitInst_r(ARM::VABSv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
1089
0
  }
1090
0
  return 0;
1091
0
}
1092
1093
0
unsigned fastEmit_ISD_ABS_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1094
0
  if (RetVT.SimpleTy != MVT::v2i32)
1095
0
    return 0;
1096
0
  if ((Subtarget->hasNEON())) {
1097
0
    return fastEmitInst_r(ARM::VABSv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
1098
0
  }
1099
0
  return 0;
1100
0
}
1101
1102
0
unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1103
0
  if (RetVT.SimpleTy != MVT::v4i32)
1104
0
    return 0;
1105
0
  if ((Subtarget->hasNEON())) {
1106
0
    return fastEmitInst_r(ARM::VABSv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
1107
0
  }
1108
0
  return 0;
1109
0
}
1110
1111
unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1112
  switch (VT.SimpleTy) {
1113
  case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1114
  case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1115
  case MVT::v4i16: return fastEmit_ISD_ABS_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1116
  case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1117
  case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1118
  case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1119
  default: return 0;
1120
  }
1121
}
1122
1123
// FastEmit functions for ISD::ANY_EXTEND.
1124
1125
0
unsigned fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1126
0
  if (RetVT.SimpleTy != MVT::v8i16)
1127
0
    return 0;
1128
0
  return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
1129
0
}
1130
1131
0
unsigned fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1132
0
  if (RetVT.SimpleTy != MVT::v4i32)
1133
0
    return 0;
1134
0
  return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
1135
0
}
1136
1137
0
unsigned fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1138
0
  if (RetVT.SimpleTy != MVT::v2i64)
1139
0
    return 0;
1140
0
  return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
1141
0
}
1142
1143
unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1144
  switch (VT.SimpleTy) {
1145
  case MVT::v8i8: return fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1146
  case MVT::v4i16: return fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1147
  case MVT::v2i32: return fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1148
  default: return 0;
1149
  }
1150
}
1151
1152
// FastEmit functions for ISD::BITCAST.
1153
1154
0
unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1155
0
  if (RetVT.SimpleTy != MVT::f32)
1156
0
    return 0;
1157
0
  if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) {
1158
0
    return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
1159
0
  }
1160
0
  return 0;
1161
0
}
1162
1163
81
unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1164
81
  if (RetVT.SimpleTy != MVT::i32)
1165
0
    return 0;
1166
81
  if ((Subtarget->hasVFP2())) {
1167
81
    return fastEmitInst_r(ARM::VMOVRS, &ARM::GPRRegClass, Op0, Op0IsKill);
1168
81
  }
1169
0
  return 0;
1170
0
}
1171
1172
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1173
0
  if ((MF->getDataLayout().isBigEndian())) {
1174
0
    return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1175
0
  }
1176
0
  return 0;
1177
0
}
1178
1179
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1180
0
  if ((MF->getDataLayout().isBigEndian())) {
1181
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1182
0
  }
1183
0
  return 0;
1184
0
}
1185
1186
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1187
0
  if ((MF->getDataLayout().isBigEndian())) {
1188
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1189
0
  }
1190
0
  return 0;
1191
0
}
1192
1193
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1194
0
  if ((MF->getDataLayout().isBigEndian())) {
1195
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1196
0
  }
1197
0
  return 0;
1198
0
}
1199
1200
unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1201
switch (RetVT.SimpleTy) {
1202
  case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(Op0, Op0IsKill);
1203
  case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(Op0, Op0IsKill);
1204
  case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0, Op0IsKill);
1205
  case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(Op0, Op0IsKill);
1206
  default: return 0;
1207
}
1208
}
1209
1210
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1211
0
  if ((MF->getDataLayout().isBigEndian())) {
1212
0
    return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1213
0
  }
1214
0
  return 0;
1215
0
}
1216
1217
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1218
0
  if ((MF->getDataLayout().isBigEndian())) {
1219
0
    return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1220
0
  }
1221
0
  return 0;
1222
0
}
1223
1224
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1225
0
  if ((MF->getDataLayout().isBigEndian())) {
1226
0
    return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1227
0
  }
1228
0
  return 0;
1229
0
}
1230
1231
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1232
0
  if ((MF->getDataLayout().isBigEndian())) {
1233
0
    return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1234
0
  }
1235
0
  return 0;
1236
0
}
1237
1238
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1239
0
  if ((MF->getDataLayout().isBigEndian())) {
1240
0
    return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1241
0
  }
1242
0
  return 0;
1243
0
}
1244
1245
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1246
switch (RetVT.SimpleTy) {
1247
  case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(Op0, Op0IsKill);
1248
  case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(Op0, Op0IsKill);
1249
  case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0, Op0IsKill);
1250
  case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0, Op0IsKill);
1251
  case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(Op0, Op0IsKill);
1252
  default: return 0;
1253
}
1254
}
1255
1256
0
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1257
0
  if ((MF->getDataLayout().isBigEndian())) {
1258
0
    return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1259
0
  }
1260
0
  return 0;
1261
0
}
1262
1263
2
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1264
2
  if ((MF->getDataLayout().isBigEndian())) {
1265
0
    return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1266
0
  }
1267
2
  return 0;
1268
2
}
1269
1270
0
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1271
0
  if ((MF->getDataLayout().isBigEndian())) {
1272
0
    return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1273
0
  }
1274
0
  return 0;
1275
0
}
1276
1277
0
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1278
0
  if ((MF->getDataLayout().isBigEndian())) {
1279
0
    return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1280
0
  }
1281
0
  return 0;
1282
0
}
1283
1284
0
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1285
0
  if ((MF->getDataLayout().isBigEndian())) {
1286
0
    return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1287
0
  }
1288
0
  return 0;
1289
0
}
1290
1291
2
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1292
2
switch (RetVT.SimpleTy) {
1293
2
  
case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill)0
;
1294
2
  case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
1295
2
  
case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill)0
;
1296
2
  
case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(Op0, Op0IsKill)0
;
1297
2
  
case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(Op0, Op0IsKill)0
;
1298
2
  
default: return 00
;
1299
2
}
1300
2
}
1301
1302
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1303
0
  if ((MF->getDataLayout().isBigEndian())) {
1304
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1305
0
  }
1306
0
  return 0;
1307
0
}
1308
1309
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1310
0
  if ((MF->getDataLayout().isBigEndian())) {
1311
0
    return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1312
0
  }
1313
0
  return 0;
1314
0
}
1315
1316
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1317
0
  if ((MF->getDataLayout().isBigEndian())) {
1318
0
    return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1319
0
  }
1320
0
  return 0;
1321
0
}
1322
1323
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1324
0
  if ((MF->getDataLayout().isBigEndian())) {
1325
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1326
0
  }
1327
0
  return 0;
1328
0
}
1329
1330
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1331
0
  if ((MF->getDataLayout().isBigEndian())) {
1332
0
    return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1333
0
  }
1334
0
  return 0;
1335
0
}
1336
1337
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1338
switch (RetVT.SimpleTy) {
1339
  case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(Op0, Op0IsKill);
1340
  case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(Op0, Op0IsKill);
1341
  case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0, Op0IsKill);
1342
  case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0, Op0IsKill);
1343
  case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(Op0, Op0IsKill);
1344
  default: return 0;
1345
}
1346
}
1347
1348
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1349
0
  if ((MF->getDataLayout().isBigEndian())) {
1350
0
    return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1351
0
  }
1352
0
  return 0;
1353
0
}
1354
1355
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1356
0
  if ((MF->getDataLayout().isBigEndian())) {
1357
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1358
0
  }
1359
0
  return 0;
1360
0
}
1361
1362
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1363
0
  if ((MF->getDataLayout().isBigEndian())) {
1364
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1365
0
  }
1366
0
  return 0;
1367
0
}
1368
1369
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1370
0
  if ((MF->getDataLayout().isBigEndian())) {
1371
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1372
0
  }
1373
0
  return 0;
1374
0
}
1375
1376
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1377
0
  if ((MF->getDataLayout().isBigEndian())) {
1378
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1379
0
  }
1380
0
  return 0;
1381
0
}
1382
1383
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1384
switch (RetVT.SimpleTy) {
1385
  case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(Op0, Op0IsKill);
1386
  case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
1387
  case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
1388
  case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(Op0, Op0IsKill);
1389
  case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(Op0, Op0IsKill);
1390
  default: return 0;
1391
}
1392
}
1393
1394
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1395
0
  if ((MF->getDataLayout().isBigEndian())) {
1396
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1397
0
  }
1398
0
  return 0;
1399
0
}
1400
1401
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1402
0
  if ((MF->getDataLayout().isBigEndian())) {
1403
0
    return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1404
0
  }
1405
0
  return 0;
1406
0
}
1407
1408
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1409
0
  if ((MF->getDataLayout().isBigEndian())) {
1410
0
    return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1411
0
  }
1412
0
  return 0;
1413
0
}
1414
1415
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1416
0
  if ((MF->getDataLayout().isBigEndian())) {
1417
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1418
0
  }
1419
0
  return 0;
1420
0
}
1421
1422
unsigned fastEmit_ISD_BITCAST_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1423
switch (RetVT.SimpleTy) {
1424
  case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(Op0, Op0IsKill);
1425
  case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(Op0, Op0IsKill);
1426
  case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(Op0, Op0IsKill);
1427
  case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0, Op0IsKill);
1428
  default: return 0;
1429
}
1430
}
1431
1432
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1433
0
  if ((MF->getDataLayout().isBigEndian())) {
1434
0
    return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1435
0
  }
1436
0
  return 0;
1437
0
}
1438
1439
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1440
0
  if ((MF->getDataLayout().isBigEndian())) {
1441
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1442
0
  }
1443
0
  return 0;
1444
0
}
1445
1446
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1447
0
  if ((MF->getDataLayout().isBigEndian())) {
1448
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1449
0
  }
1450
0
  return 0;
1451
0
}
1452
1453
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1454
0
  if ((MF->getDataLayout().isBigEndian())) {
1455
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1456
0
  }
1457
0
  return 0;
1458
0
}
1459
1460
unsigned fastEmit_ISD_BITCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1461
switch (RetVT.SimpleTy) {
1462
  case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill);
1463
  case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill);
1464
  case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(Op0, Op0IsKill);
1465
  case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(Op0, Op0IsKill);
1466
  default: return 0;
1467
}
1468
}
1469
1470
0
unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1471
0
  if ((MF->getDataLayout().isBigEndian())) {
1472
0
    return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1473
0
  }
1474
0
  return 0;
1475
0
}
1476
1477
0
unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1478
0
  if ((MF->getDataLayout().isBigEndian())) {
1479
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1480
0
  }
1481
0
  return 0;
1482
0
}
1483
1484
0
unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1485
0
  if ((MF->getDataLayout().isBigEndian())) {
1486
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1487
0
  }
1488
0
  return 0;
1489
0
}
1490
1491
0
unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1492
0
  if ((MF->getDataLayout().isBigEndian())) {
1493
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1494
0
  }
1495
0
  return 0;
1496
0
}
1497
1498
unsigned fastEmit_ISD_BITCAST_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1499
switch (RetVT.SimpleTy) {
1500
  case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(Op0, Op0IsKill);
1501
  case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(Op0, Op0IsKill);
1502
  case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0, Op0IsKill);
1503
  case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(Op0, Op0IsKill);
1504
  default: return 0;
1505
}
1506
}
1507
1508
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1509
0
  if ((MF->getDataLayout().isBigEndian())) {
1510
0
    return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1511
0
  }
1512
0
  return 0;
1513
0
}
1514
1515
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1516
0
  if ((MF->getDataLayout().isBigEndian())) {
1517
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1518
0
  }
1519
0
  return 0;
1520
0
}
1521
1522
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1523
0
  if ((MF->getDataLayout().isBigEndian())) {
1524
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1525
0
  }
1526
0
  return 0;
1527
0
}
1528
1529
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1530
0
  if ((MF->getDataLayout().isBigEndian())) {
1531
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1532
0
  }
1533
0
  return 0;
1534
0
}
1535
1536
unsigned fastEmit_ISD_BITCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1537
switch (RetVT.SimpleTy) {
1538
  case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill);
1539
  case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill);
1540
  case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill);
1541
  case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(Op0, Op0IsKill);
1542
  default: return 0;
1543
}
1544
}
1545
1546
0
unsigned fastEmit_ISD_BITCAST_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1547
0
  if (RetVT.SimpleTy != MVT::f64)
1548
0
    return 0;
1549
0
  if ((MF->getDataLayout().isBigEndian())) {
1550
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1551
0
  }
1552
0
  return 0;
1553
0
}
1554
1555
0
unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1556
0
  if ((MF->getDataLayout().isBigEndian())) {
1557
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1558
0
  }
1559
0
  return 0;
1560
0
}
1561
1562
0
unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1563
0
  if ((MF->getDataLayout().isBigEndian())) {
1564
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1565
0
  }
1566
0
  return 0;
1567
0
}
1568
1569
unsigned fastEmit_ISD_BITCAST_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1570
switch (RetVT.SimpleTy) {
1571
  case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(Op0, Op0IsKill);
1572
  case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(Op0, Op0IsKill);
1573
  default: return 0;
1574
}
1575
}
1576
1577
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1578
0
  if ((MF->getDataLayout().isBigEndian())) {
1579
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1580
0
  }
1581
0
  return 0;
1582
0
}
1583
1584
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1585
0
  if ((MF->getDataLayout().isBigEndian())) {
1586
0
    return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1587
0
  }
1588
0
  return 0;
1589
0
}
1590
1591
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1592
0
  if ((MF->getDataLayout().isBigEndian())) {
1593
0
    return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1594
0
  }
1595
0
  return 0;
1596
0
}
1597
1598
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1599
0
  if ((MF->getDataLayout().isBigEndian())) {
1600
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1601
0
  }
1602
0
  return 0;
1603
0
}
1604
1605
unsigned fastEmit_ISD_BITCAST_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1606
switch (RetVT.SimpleTy) {
1607
  case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(Op0, Op0IsKill);
1608
  case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(Op0, Op0IsKill);
1609
  case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(Op0, Op0IsKill);
1610
  case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0, Op0IsKill);
1611
  default: return 0;
1612
}
1613
}
1614
1615
0
unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1616
0
  if ((MF->getDataLayout().isBigEndian())) {
1617
0
    return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1618
0
  }
1619
0
  return 0;
1620
0
}
1621
1622
0
unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1623
0
  if ((MF->getDataLayout().isBigEndian())) {
1624
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1625
0
  }
1626
0
  return 0;
1627
0
}
1628
1629
0
unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1630
0
  if ((MF->getDataLayout().isBigEndian())) {
1631
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1632
0
  }
1633
0
  return 0;
1634
0
}
1635
1636
0
unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1637
0
  if ((MF->getDataLayout().isBigEndian())) {
1638
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1639
0
  }
1640
0
  return 0;
1641
0
}
1642
1643
unsigned fastEmit_ISD_BITCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1644
switch (RetVT.SimpleTy) {
1645
  case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(Op0, Op0IsKill);
1646
  case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(Op0, Op0IsKill);
1647
  case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill);
1648
  case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(Op0, Op0IsKill);
1649
  default: return 0;
1650
}
1651
}
1652
1653
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1654
0
  if ((MF->getDataLayout().isBigEndian())) {
1655
0
    return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1656
0
  }
1657
0
  return 0;
1658
0
}
1659
1660
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1661
0
  if ((MF->getDataLayout().isBigEndian())) {
1662
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1663
0
  }
1664
0
  return 0;
1665
0
}
1666
1667
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1668
0
  if ((MF->getDataLayout().isBigEndian())) {
1669
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1670
0
  }
1671
0
  return 0;
1672
0
}
1673
1674
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) {
1675
0
  if ((MF->getDataLayout().isBigEndian())) {
1676
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1677
0
  }
1678
0
  return 0;
1679
0
}
1680
1681
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1682
0
  if ((MF->getDataLayout().isBigEndian())) {
1683
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1684
0
  }
1685
0
  return 0;
1686
0
}
1687
1688
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1689
switch (RetVT.SimpleTy) {
1690
  case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(Op0, Op0IsKill);
1691
  case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(Op0, Op0IsKill);
1692
  case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill);
1693
  case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(Op0, Op0IsKill);
1694
  case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(Op0, Op0IsKill);
1695
  default: return 0;
1696
}
1697
}
1698
1699
83
unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1700
83
  switch (VT.SimpleTy) {
1701
83
  
case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill)0
;
1702
83
  
case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill)81
;
1703
83
  
case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill)0
;
1704
83
  
case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v8i8_r(RetVT, Op0, Op0IsKill)0
;
1705
83
  
case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v16i8_r(RetVT, Op0, Op0IsKill)2
;
1706
83
  
case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v4i16_r(RetVT, Op0, Op0IsKill)0
;
1707
83
  
case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v8i16_r(RetVT, Op0, Op0IsKill)0
;
1708
83
  
case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v2i32_r(RetVT, Op0, Op0IsKill)0
;
1709
83
  
case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v4i32_r(RetVT, Op0, Op0IsKill)0
;
1710
83
  
case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0, Op0IsKill)0
;
1711
83
  
case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v2i64_r(RetVT, Op0, Op0IsKill)0
;
1712
83
  
case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v4f16_r(RetVT, Op0, Op0IsKill)0
;
1713
83
  
case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v8f16_r(RetVT, Op0, Op0IsKill)0
;
1714
83
  
case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v2f32_r(RetVT, Op0, Op0IsKill)0
;
1715
83
  
case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v4f32_r(RetVT, Op0, Op0IsKill)0
;
1716
83
  
case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v2f64_r(RetVT, Op0, Op0IsKill)0
;
1717
83
  
default: return 00
;
1718
83
  }
1719
83
}
1720
1721
// FastEmit functions for ISD::BITREVERSE.
1722
1723
0
unsigned fastEmit_ISD_BITREVERSE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1724
0
  if (RetVT.SimpleTy != MVT::i32)
1725
0
    return 0;
1726
0
  if ((Subtarget->isThumb2())) {
1727
0
    return fastEmitInst_r(ARM::t2RBIT, &ARM::rGPRRegClass, Op0, Op0IsKill);
1728
0
  }
1729
0
  if ((Subtarget->hasV6T2Ops()) && (!Subtarget->isThumb())) {
1730
0
    return fastEmitInst_r(ARM::RBIT, &ARM::GPRRegClass, Op0, Op0IsKill);
1731
0
  }
1732
0
  return 0;
1733
0
}
1734
1735
unsigned fastEmit_ISD_BITREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1736
  switch (VT.SimpleTy) {
1737
  case MVT::i32: return fastEmit_ISD_BITREVERSE_MVT_i32_r(RetVT, Op0, Op0IsKill);
1738
  default: return 0;
1739
  }
1740
}
1741
1742
// FastEmit functions for ISD::BRIND.
1743
1744
0
unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1745
0
  if (RetVT.SimpleTy != MVT::isVoid)
1746
0
    return 0;
1747
0
  if ((Subtarget->isThumb())) {
1748
0
    return fastEmitInst_r(ARM::tBRIND, &ARM::GPRRegClass, Op0, Op0IsKill);
1749
0
  }
1750
0
  if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
1751
0
    return fastEmitInst_r(ARM::MOVPCRX, &ARM::GPRRegClass, Op0, Op0IsKill);
1752
0
  }
1753
0
  if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
1754
0
    return fastEmitInst_r(ARM::BX, &ARM::GPRRegClass, Op0, Op0IsKill);
1755
0
  }
1756
0
  return 0;
1757
0
}
1758
1759
unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1760
  switch (VT.SimpleTy) {
1761
  case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
1762
  default: return 0;
1763
  }
1764
}
1765
1766
// FastEmit functions for ISD::BSWAP.
1767
1768
0
unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1769
0
  if (RetVT.SimpleTy != MVT::i32)
1770
0
    return 0;
1771
0
  if ((Subtarget->isThumb2())) {
1772
0
    return fastEmitInst_r(ARM::t2REV, &ARM::rGPRRegClass, Op0, Op0IsKill);
1773
0
  }
1774
0
  if ((Subtarget->hasV6Ops()) && (Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
1775
0
    return fastEmitInst_r(ARM::tREV, &ARM::tGPRRegClass, Op0, Op0IsKill);
1776
0
  }
1777
0
  if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
1778
0
    return fastEmitInst_r(ARM::REV, &ARM::GPRRegClass, Op0, Op0IsKill);
1779
0
  }
1780
0
  return 0;
1781
0
}
1782
1783
unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1784
  switch (VT.SimpleTy) {
1785
  case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0, Op0IsKill);
1786
  default: return 0;
1787
  }
1788
}
1789
1790
// FastEmit functions for ISD::CTLZ.
1791
1792
0
unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1793
0
  if (RetVT.SimpleTy != MVT::i32)
1794
0
    return 0;
1795
0
  if ((Subtarget->isThumb2())) {
1796
0
    return fastEmitInst_r(ARM::t2CLZ, &ARM::rGPRRegClass, Op0, Op0IsKill);
1797
0
  }
1798
0
  if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
1799
0
    return fastEmitInst_r(ARM::CLZ, &ARM::GPRRegClass, Op0, Op0IsKill);
1800
0
  }
1801
0
  return 0;
1802
0
}
1803
1804
0
unsigned fastEmit_ISD_CTLZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1805
0
  if (RetVT.SimpleTy != MVT::v8i8)
1806
0
    return 0;
1807
0
  if ((Subtarget->hasNEON())) {
1808
0
    return fastEmitInst_r(ARM::VCLZv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
1809
0
  }
1810
0
  return 0;
1811
0
}
1812
1813
0
unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1814
0
  if (RetVT.SimpleTy != MVT::v16i8)
1815
0
    return 0;
1816
0
  if ((Subtarget->hasNEON())) {
1817
0
    return fastEmitInst_r(ARM::VCLZv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
1818
0
  }
1819
0
  return 0;
1820
0
}
1821
1822
0
unsigned fastEmit_ISD_CTLZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1823
0
  if (RetVT.SimpleTy != MVT::v4i16)
1824
0
    return 0;
1825
0
  if ((Subtarget->hasNEON())) {
1826
0
    return fastEmitInst_r(ARM::VCLZv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
1827
0
  }
1828
0
  return 0;
1829
0
}
1830
1831
0
unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1832
0
  if (RetVT.SimpleTy != MVT::v8i16)
1833
0
    return 0;
1834
0
  if ((Subtarget->hasNEON())) {
1835
0
    return fastEmitInst_r(ARM::VCLZv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
1836
0
  }
1837
0
  return 0;
1838
0
}
1839
1840
0
unsigned fastEmit_ISD_CTLZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1841
0
  if (RetVT.SimpleTy != MVT::v2i32)
1842
0
    return 0;
1843
0
  if ((Subtarget->hasNEON())) {
1844
0
    return fastEmitInst_r(ARM::VCLZv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
1845
0
  }
1846
0
  return 0;
1847
0
}
1848
1849
0
unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1850
0
  if (RetVT.SimpleTy != MVT::v4i32)
1851
0
    return 0;
1852
0
  if ((Subtarget->hasNEON())) {
1853
0
    return fastEmitInst_r(ARM::VCLZv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
1854
0
  }
1855
0
  return 0;
1856
0
}
1857
1858
unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1859
  switch (VT.SimpleTy) {
1860
  case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
1861
  case MVT::v8i8: return fastEmit_ISD_CTLZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1862
  case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1863
  case MVT::v4i16: return fastEmit_ISD_CTLZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1864
  case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1865
  case MVT::v2i32: return fastEmit_ISD_CTLZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1866
  case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1867
  default: return 0;
1868
  }
1869
}
1870
1871
// FastEmit functions for ISD::CTPOP.
1872
1873
0
unsigned fastEmit_ISD_CTPOP_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1874
0
  if (RetVT.SimpleTy != MVT::v8i8)
1875
0
    return 0;
1876
0
  if ((Subtarget->hasNEON())) {
1877
0
    return fastEmitInst_r(ARM::VCNTd, &ARM::DPRRegClass, Op0, Op0IsKill);
1878
0
  }
1879
0
  return 0;
1880
0
}
1881
1882
0
unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1883
0
  if (RetVT.SimpleTy != MVT::v16i8)
1884
0
    return 0;
1885
0
  if ((Subtarget->hasNEON())) {
1886
0
    return fastEmitInst_r(ARM::VCNTq, &ARM::QPRRegClass, Op0, Op0IsKill);
1887
0
  }
1888
0
  return 0;
1889
0
}
1890
1891
unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1892
  switch (VT.SimpleTy) {
1893
  case MVT::v8i8: return fastEmit_ISD_CTPOP_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1894
  case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1895
  default: return 0;
1896
  }
1897
}
1898
1899
// FastEmit functions for ISD::FABS.
1900
1901
0
unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1902
0
  if (RetVT.SimpleTy != MVT::f32)
1903
0
    return 0;
1904
0
  if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
1905
0
    return fastEmitInst_r(ARM::VABSS, &ARM::SPRRegClass, Op0, Op0IsKill);
1906
0
  }
1907
0
  return 0;
1908
0
}
1909
1910
0
unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1911
0
  if (RetVT.SimpleTy != MVT::f64)
1912
0
    return 0;
1913
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
1914
0
    return fastEmitInst_r(ARM::VABSD, &ARM::DPRRegClass, Op0, Op0IsKill);
1915
0
  }
1916
0
  return 0;
1917
0
}
1918
1919
0
unsigned fastEmit_ISD_FABS_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1920
0
  if (RetVT.SimpleTy != MVT::v4f16)
1921
0
    return 0;
1922
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
1923
0
    return fastEmitInst_r(ARM::VABShd, &ARM::DPRRegClass, Op0, Op0IsKill);
1924
0
  }
1925
0
  return 0;
1926
0
}
1927
1928
0
unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1929
0
  if (RetVT.SimpleTy != MVT::v8f16)
1930
0
    return 0;
1931
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
1932
0
    return fastEmitInst_r(ARM::VABShq, &ARM::QPRRegClass, Op0, Op0IsKill);
1933
0
  }
1934
0
  return 0;
1935
0
}
1936
1937
0
unsigned fastEmit_ISD_FABS_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1938
0
  if (RetVT.SimpleTy != MVT::v2f32)
1939
0
    return 0;
1940
0
  if ((Subtarget->hasNEON())) {
1941
0
    return fastEmitInst_r(ARM::VABSfd, &ARM::DPRRegClass, Op0, Op0IsKill);
1942
0
  }
1943
0
  return 0;
1944
0
}
1945
1946
0
unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1947
0
  if (RetVT.SimpleTy != MVT::v4f32)
1948
0
    return 0;
1949
0
  if ((Subtarget->hasNEON())) {
1950
0
    return fastEmitInst_r(ARM::VABSfq, &ARM::QPRRegClass, Op0, Op0IsKill);
1951
0
  }
1952
0
  return 0;
1953
0
}
1954
1955
unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1956
  switch (VT.SimpleTy) {
1957
  case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
1958
  case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
1959
  case MVT::v4f16: return fastEmit_ISD_FABS_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
1960
  case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
1961
  case MVT::v2f32: return fastEmit_ISD_FABS_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
1962
  case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
1963
  default: return 0;
1964
  }
1965
}
1966
1967
// FastEmit functions for ISD::FCEIL.
1968
1969
0
unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1970
0
  if (RetVT.SimpleTy != MVT::f32)
1971
0
    return 0;
1972
0
  if ((Subtarget->hasFPARMv8())) {
1973
0
    return fastEmitInst_r(ARM::VRINTPS, &ARM::SPRRegClass, Op0, Op0IsKill);
1974
0
  }
1975
0
  return 0;
1976
0
}
1977
1978
0
unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1979
0
  if (RetVT.SimpleTy != MVT::f64)
1980
0
    return 0;
1981
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
1982
0
    return fastEmitInst_r(ARM::VRINTPD, &ARM::DPRRegClass, Op0, Op0IsKill);
1983
0
  }
1984
0
  return 0;
1985
0
}
1986
1987
unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1988
  switch (VT.SimpleTy) {
1989
  case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
1990
  case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
1991
  default: return 0;
1992
  }
1993
}
1994
1995
// FastEmit functions for ISD::FFLOOR.
1996
1997
0
unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1998
0
  if (RetVT.SimpleTy != MVT::f32)
1999
0
    return 0;
2000
0
  if ((Subtarget->hasFPARMv8())) {
2001
0
    return fastEmitInst_r(ARM::VRINTMS, &ARM::SPRRegClass, Op0, Op0IsKill);
2002
0
  }
2003
0
  return 0;
2004
0
}
2005
2006
0
unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2007
0
  if (RetVT.SimpleTy != MVT::f64)
2008
0
    return 0;
2009
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2010
0
    return fastEmitInst_r(ARM::VRINTMD, &ARM::DPRRegClass, Op0, Op0IsKill);
2011
0
  }
2012
0
  return 0;
2013
0
}
2014
2015
unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2016
  switch (VT.SimpleTy) {
2017
  case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
2018
  case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
2019
  default: return 0;
2020
  }
2021
}
2022
2023
// FastEmit functions for ISD::FNEARBYINT.
2024
2025
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2026
0
  if (RetVT.SimpleTy != MVT::f32)
2027
0
    return 0;
2028
0
  if ((Subtarget->hasFPARMv8())) {
2029
0
    return fastEmitInst_r(ARM::VRINTRS, &ARM::SPRRegClass, Op0, Op0IsKill);
2030
0
  }
2031
0
  return 0;
2032
0
}
2033
2034
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2035
0
  if (RetVT.SimpleTy != MVT::f64)
2036
0
    return 0;
2037
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2038
0
    return fastEmitInst_r(ARM::VRINTRD, &ARM::DPRRegClass, Op0, Op0IsKill);
2039
0
  }
2040
0
  return 0;
2041
0
}
2042
2043
unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2044
  switch (VT.SimpleTy) {
2045
  case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
2046
  case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
2047
  default: return 0;
2048
  }
2049
}
2050
2051
// FastEmit functions for ISD::FNEG.
2052
2053
0
unsigned fastEmit_ISD_FNEG_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2054
0
  if (RetVT.SimpleTy != MVT::f16)
2055
0
    return 0;
2056
0
  if ((Subtarget->hasFullFP16())) {
2057
0
    return fastEmitInst_r(ARM::VNEGH, &ARM::HPRRegClass, Op0, Op0IsKill);
2058
0
  }
2059
0
  return 0;
2060
0
}
2061
2062
0
unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2063
0
  if (RetVT.SimpleTy != MVT::f32)
2064
0
    return 0;
2065
0
  if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
2066
0
    return fastEmitInst_r(ARM::VNEGS, &ARM::SPRRegClass, Op0, Op0IsKill);
2067
0
  }
2068
0
  return 0;
2069
0
}
2070
2071
0
unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2072
0
  if (RetVT.SimpleTy != MVT::f64)
2073
0
    return 0;
2074
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2075
0
    return fastEmitInst_r(ARM::VNEGD, &ARM::DPRRegClass, Op0, Op0IsKill);
2076
0
  }
2077
0
  return 0;
2078
0
}
2079
2080
0
unsigned fastEmit_ISD_FNEG_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2081
0
  if (RetVT.SimpleTy != MVT::v4f16)
2082
0
    return 0;
2083
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2084
0
    return fastEmitInst_r(ARM::VNEGhd, &ARM::DPRRegClass, Op0, Op0IsKill);
2085
0
  }
2086
0
  return 0;
2087
0
}
2088
2089
0
unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2090
0
  if (RetVT.SimpleTy != MVT::v8f16)
2091
0
    return 0;
2092
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2093
0
    return fastEmitInst_r(ARM::VNEGhq, &ARM::QPRRegClass, Op0, Op0IsKill);
2094
0
  }
2095
0
  return 0;
2096
0
}
2097
2098
0
unsigned fastEmit_ISD_FNEG_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2099
0
  if (RetVT.SimpleTy != MVT::v2f32)
2100
0
    return 0;
2101
0
  if ((Subtarget->hasNEON())) {
2102
0
    return fastEmitInst_r(ARM::VNEGfd, &ARM::DPRRegClass, Op0, Op0IsKill);
2103
0
  }
2104
0
  return 0;
2105
0
}
2106
2107
0
unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2108
0
  if (RetVT.SimpleTy != MVT::v4f32)
2109
0
    return 0;
2110
0
  if ((Subtarget->hasNEON())) {
2111
0
    return fastEmitInst_r(ARM::VNEGf32q, &ARM::QPRRegClass, Op0, Op0IsKill);
2112
0
  }
2113
0
  return 0;
2114
0
}
2115
2116
unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2117
  switch (VT.SimpleTy) {
2118
  case MVT::f16: return fastEmit_ISD_FNEG_MVT_f16_r(RetVT, Op0, Op0IsKill);
2119
  case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
2120
  case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
2121
  case MVT::v4f16: return fastEmit_ISD_FNEG_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
2122
  case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
2123
  case MVT::v2f32: return fastEmit_ISD_FNEG_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
2124
  case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
2125
  default: return 0;
2126
  }
2127
}
2128
2129
// FastEmit functions for ISD::FP_EXTEND.
2130
2131
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2132
0
  if (RetVT.SimpleTy != MVT::f64)
2133
0
    return 0;
2134
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2135
0
    return fastEmitInst_r(ARM::VCVTDS, &ARM::DPRRegClass, Op0, Op0IsKill);
2136
0
  }
2137
0
  return 0;
2138
0
}
2139
2140
unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2141
  switch (VT.SimpleTy) {
2142
  case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
2143
  default: return 0;
2144
  }
2145
}
2146
2147
// FastEmit functions for ISD::FP_ROUND.
2148
2149
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2150
0
  if (RetVT.SimpleTy != MVT::f32)
2151
0
    return 0;
2152
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2153
0
    return fastEmitInst_r(ARM::VCVTSD, &ARM::SPRRegClass, Op0, Op0IsKill);
2154
0
  }
2155
0
  return 0;
2156
0
}
2157
2158
unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2159
  switch (VT.SimpleTy) {
2160
  case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
2161
  default: return 0;
2162
  }
2163
}
2164
2165
// FastEmit functions for ISD::FP_TO_SINT.
2166
2167
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2168
0
  if (RetVT.SimpleTy != MVT::v4i16)
2169
0
    return 0;
2170
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2171
0
    return fastEmitInst_r(ARM::VCVTh2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
2172
0
  }
2173
0
  return 0;
2174
0
}
2175
2176
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2177
0
  if (RetVT.SimpleTy != MVT::v8i16)
2178
0
    return 0;
2179
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2180
0
    return fastEmitInst_r(ARM::VCVTh2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
2181
0
  }
2182
0
  return 0;
2183
0
}
2184
2185
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2186
0
  if (RetVT.SimpleTy != MVT::v2i32)
2187
0
    return 0;
2188
0
  if ((Subtarget->hasNEON())) {
2189
0
    return fastEmitInst_r(ARM::VCVTf2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
2190
0
  }
2191
0
  return 0;
2192
0
}
2193
2194
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2195
0
  if (RetVT.SimpleTy != MVT::v4i32)
2196
0
    return 0;
2197
0
  if ((Subtarget->hasNEON())) {
2198
0
    return fastEmitInst_r(ARM::VCVTf2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
2199
0
  }
2200
0
  return 0;
2201
0
}
2202
2203
6
unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2204
6
  switch (VT.SimpleTy) {
2205
6
  
case MVT::v4f16: return fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill)0
;
2206
6
  
case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill)0
;
2207
6
  
case MVT::v2f32: return fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill)0
;
2208
6
  
case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill)0
;
2209
6
  default: return 0;
2210
6
  }
2211
6
}
2212
2213
// FastEmit functions for ISD::FP_TO_UINT.
2214
2215
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2216
0
  if (RetVT.SimpleTy != MVT::v4i16)
2217
0
    return 0;
2218
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2219
0
    return fastEmitInst_r(ARM::VCVTh2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
2220
0
  }
2221
0
  return 0;
2222
0
}
2223
2224
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2225
0
  if (RetVT.SimpleTy != MVT::v8i16)
2226
0
    return 0;
2227
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2228
0
    return fastEmitInst_r(ARM::VCVTh2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
2229
0
  }
2230
0
  return 0;
2231
0
}
2232
2233
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2234
0
  if (RetVT.SimpleTy != MVT::v2i32)
2235
0
    return 0;
2236
0
  if ((Subtarget->hasNEON())) {
2237
0
    return fastEmitInst_r(ARM::VCVTf2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
2238
0
  }
2239
0
  return 0;
2240
0
}
2241
2242
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2243
0
  if (RetVT.SimpleTy != MVT::v4i32)
2244
0
    return 0;
2245
0
  if ((Subtarget->hasNEON())) {
2246
0
    return fastEmitInst_r(ARM::VCVTf2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
2247
0
  }
2248
0
  return 0;
2249
0
}
2250
2251
unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2252
  switch (VT.SimpleTy) {
2253
  case MVT::v4f16: return fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
2254
  case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
2255
  case MVT::v2f32: return fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
2256
  case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
2257
  default: return 0;
2258
  }
2259
}
2260
2261
// FastEmit functions for ISD::FRINT.
2262
2263
0
unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2264
0
  if (RetVT.SimpleTy != MVT::f32)
2265
0
    return 0;
2266
0
  if ((Subtarget->hasFPARMv8())) {
2267
0
    return fastEmitInst_r(ARM::VRINTXS, &ARM::SPRRegClass, Op0, Op0IsKill);
2268
0
  }
2269
0
  return 0;
2270
0
}
2271
2272
0
unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2273
0
  if (RetVT.SimpleTy != MVT::f64)
2274
0
    return 0;
2275
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2276
0
    return fastEmitInst_r(ARM::VRINTXD, &ARM::DPRRegClass, Op0, Op0IsKill);
2277
0
  }
2278
0
  return 0;
2279
0
}
2280
2281
unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2282
  switch (VT.SimpleTy) {
2283
  case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
2284
  case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
2285
  default: return 0;
2286
  }
2287
}
2288
2289
// FastEmit functions for ISD::FROUND.
2290
2291
0
unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2292
0
  if (RetVT.SimpleTy != MVT::f32)
2293
0
    return 0;
2294
0
  if ((Subtarget->hasFPARMv8())) {
2295
0
    return fastEmitInst_r(ARM::VRINTAS, &ARM::SPRRegClass, Op0, Op0IsKill);
2296
0
  }
2297
0
  return 0;
2298
0
}
2299
2300
0
unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2301
0
  if (RetVT.SimpleTy != MVT::f64)
2302
0
    return 0;
2303
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2304
0
    return fastEmitInst_r(ARM::VRINTAD, &ARM::DPRRegClass, Op0, Op0IsKill);
2305
0
  }
2306
0
  return 0;
2307
0
}
2308
2309
unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2310
  switch (VT.SimpleTy) {
2311
  case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
2312
  case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
2313
  default: return 0;
2314
  }
2315
}
2316
2317
// FastEmit functions for ISD::FSQRT.
2318
2319
0
unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2320
0
  if (RetVT.SimpleTy != MVT::f32)
2321
0
    return 0;
2322
0
  if ((Subtarget->hasVFP2())) {
2323
0
    return fastEmitInst_r(ARM::VSQRTS, &ARM::SPRRegClass, Op0, Op0IsKill);
2324
0
  }
2325
0
  return 0;
2326
0
}
2327
2328
0
unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2329
0
  if (RetVT.SimpleTy != MVT::f64)
2330
0
    return 0;
2331
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2332
0
    return fastEmitInst_r(ARM::VSQRTD, &ARM::DPRRegClass, Op0, Op0IsKill);
2333
0
  }
2334
0
  return 0;
2335
0
}
2336
2337
unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2338
  switch (VT.SimpleTy) {
2339
  case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
2340
  case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
2341
  default: return 0;
2342
  }
2343
}
2344
2345
// FastEmit functions for ISD::FTRUNC.
2346
2347
0
unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2348
0
  if (RetVT.SimpleTy != MVT::f32)
2349
0
    return 0;
2350
0
  if ((Subtarget->hasFPARMv8())) {
2351
0
    return fastEmitInst_r(ARM::VRINTZS, &ARM::SPRRegClass, Op0, Op0IsKill);
2352
0
  }
2353
0
  return 0;
2354
0
}
2355
2356
0
unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2357
0
  if (RetVT.SimpleTy != MVT::f64)
2358
0
    return 0;
2359
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2360
0
    return fastEmitInst_r(ARM::VRINTZD, &ARM::DPRRegClass, Op0, Op0IsKill);
2361
0
  }
2362
0
  return 0;
2363
0
}
2364
2365
unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2366
  switch (VT.SimpleTy) {
2367
  case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
2368
  case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
2369
  default: return 0;
2370
  }
2371
}
2372
2373
// FastEmit functions for ISD::SIGN_EXTEND.
2374
2375
0
unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2376
0
  if (RetVT.SimpleTy != MVT::v8i16)
2377
0
    return 0;
2378
0
  if ((Subtarget->hasNEON())) {
2379
0
    return fastEmitInst_r(ARM::VMOVLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
2380
0
  }
2381
0
  return 0;
2382
0
}
2383
2384
0
unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2385
0
  if (RetVT.SimpleTy != MVT::v4i32)
2386
0
    return 0;
2387
0
  if ((Subtarget->hasNEON())) {
2388
0
    return fastEmitInst_r(ARM::VMOVLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
2389
0
  }
2390
0
  return 0;
2391
0
}
2392
2393
0
unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2394
0
  if (RetVT.SimpleTy != MVT::v2i64)
2395
0
    return 0;
2396
0
  if ((Subtarget->hasNEON())) {
2397
0
    return fastEmitInst_r(ARM::VMOVLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
2398
0
  }
2399
0
  return 0;
2400
0
}
2401
2402
1
unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2403
1
  switch (VT.SimpleTy) {
2404
1
  
case MVT::v8i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill)0
;
2405
1
  
case MVT::v4i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill)0
;
2406
1
  
case MVT::v2i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill)0
;
2407
1
  default: return 0;
2408
1
  }
2409
1
}
2410
2411
// FastEmit functions for ISD::SINT_TO_FP.
2412
2413
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2414
0
  if (RetVT.SimpleTy != MVT::v4f16)
2415
0
    return 0;
2416
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2417
0
    return fastEmitInst_r(ARM::VCVTs2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
2418
0
  }
2419
0
  return 0;
2420
0
}
2421
2422
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2423
0
  if (RetVT.SimpleTy != MVT::v8f16)
2424
0
    return 0;
2425
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2426
0
    return fastEmitInst_r(ARM::VCVTs2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
2427
0
  }
2428
0
  return 0;
2429
0
}
2430
2431
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2432
0
  if (RetVT.SimpleTy != MVT::v2f32)
2433
0
    return 0;
2434
0
  if ((Subtarget->hasNEON())) {
2435
0
    return fastEmitInst_r(ARM::VCVTs2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
2436
0
  }
2437
0
  return 0;
2438
0
}
2439
2440
2
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2441
2
  if (RetVT.SimpleTy != MVT::v4f32)
2442
0
    return 0;
2443
2
  if ((Subtarget->hasNEON())) {
2444
2
    return fastEmitInst_r(ARM::VCVTs2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
2445
2
  }
2446
0
  return 0;
2447
0
}
2448
2449
9
unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2450
9
  switch (VT.SimpleTy) {
2451
9
  
case MVT::v4i16: return fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill)0
;
2452
9
  
case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill)0
;
2453
9
  
case MVT::v2i32: return fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill)0
;
2454
9
  
case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill)2
;
2455
9
  
default: return 07
;
2456
9
  }
2457
9
}
2458
2459
// FastEmit functions for ISD::TRUNCATE.
2460
2461
0
unsigned fastEmit_ISD_TRUNCATE_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2462
0
  if (RetVT.SimpleTy != MVT::v8i8)
2463
0
    return 0;
2464
0
  if ((Subtarget->hasNEON())) {
2465
0
    return fastEmitInst_r(ARM::VMOVNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
2466
0
  }
2467
0
  return 0;
2468
0
}
2469
2470
0
unsigned fastEmit_ISD_TRUNCATE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2471
0
  if (RetVT.SimpleTy != MVT::v4i16)
2472
0
    return 0;
2473
0
  if ((Subtarget->hasNEON())) {
2474
0
    return fastEmitInst_r(ARM::VMOVNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
2475
0
  }
2476
0
  return 0;
2477
0
}
2478
2479
0
unsigned fastEmit_ISD_TRUNCATE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2480
0
  if (RetVT.SimpleTy != MVT::v2i32)
2481
0
    return 0;
2482
0
  if ((Subtarget->hasNEON())) {
2483
0
    return fastEmitInst_r(ARM::VMOVNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
2484
0
  }
2485
0
  return 0;
2486
0
}
2487
2488
unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2489
  switch (VT.SimpleTy) {
2490
  case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
2491
  case MVT::v4i32: return fastEmit_ISD_TRUNCATE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
2492
  case MVT::v2i64: return fastEmit_ISD_TRUNCATE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
2493
  default: return 0;
2494
  }
2495
}
2496
2497
// FastEmit functions for ISD::UINT_TO_FP.
2498
2499
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2500
0
  if (RetVT.SimpleTy != MVT::v4f16)
2501
0
    return 0;
2502
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2503
0
    return fastEmitInst_r(ARM::VCVTu2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
2504
0
  }
2505
0
  return 0;
2506
0
}
2507
2508
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2509
0
  if (RetVT.SimpleTy != MVT::v8f16)
2510
0
    return 0;
2511
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2512
0
    return fastEmitInst_r(ARM::VCVTu2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
2513
0
  }
2514
0
  return 0;
2515
0
}
2516
2517
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2518
0
  if (RetVT.SimpleTy != MVT::v2f32)
2519
0
    return 0;
2520
0
  if ((Subtarget->hasNEON())) {
2521
0
    return fastEmitInst_r(ARM::VCVTu2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
2522
0
  }
2523
0
  return 0;
2524
0
}
2525
2526
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2527
0
  if (RetVT.SimpleTy != MVT::v4f32)
2528
0
    return 0;
2529
0
  if ((Subtarget->hasNEON())) {
2530
0
    return fastEmitInst_r(ARM::VCVTu2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
2531
0
  }
2532
0
  return 0;
2533
0
}
2534
2535
unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2536
  switch (VT.SimpleTy) {
2537
  case MVT::v4i16: return fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
2538
  case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
2539
  case MVT::v2i32: return fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
2540
  case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
2541
  default: return 0;
2542
  }
2543
}
2544
2545
// FastEmit functions for ISD::ZERO_EXTEND.
2546
2547
0
unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2548
0
  if (RetVT.SimpleTy != MVT::v8i16)
2549
0
    return 0;
2550
0
  if ((Subtarget->hasNEON())) {
2551
0
    return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
2552
0
  }
2553
0
  return 0;
2554
0
}
2555
2556
0
unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2557
0
  if (RetVT.SimpleTy != MVT::v4i32)
2558
0
    return 0;
2559
0
  if ((Subtarget->hasNEON())) {
2560
0
    return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
2561
0
  }
2562
0
  return 0;
2563
0
}
2564
2565
0
unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2566
0
  if (RetVT.SimpleTy != MVT::v2i64)
2567
0
    return 0;
2568
0
  if ((Subtarget->hasNEON())) {
2569
0
    return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
2570
0
  }
2571
0
  return 0;
2572
0
}
2573
2574
unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2575
  switch (VT.SimpleTy) {
2576
  case MVT::v8i8: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
2577
  case MVT::v4i16: return fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
2578
  case MVT::v2i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
2579
  default: return 0;
2580
  }
2581
}
2582
2583
// Top-level FastEmit function.
2584
2585
99
unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
2586
99
  switch (Opcode) {
2587
99
  
case ARMISD::CALL: return fastEmit_ARMISD_CALL_r(VT, RetVT, Op0, Op0IsKill)0
;
2588
99
  
case ARMISD::CALL_NOLINK: return fastEmit_ARMISD_CALL_NOLINK_r(VT, RetVT, Op0, Op0IsKill)0
;
2589
99
  
case ARMISD::CALL_PRED: return fastEmit_ARMISD_CALL_PRED_r(VT, RetVT, Op0, Op0IsKill)0
;
2590
99
  
case ARMISD::RRX: return fastEmit_ARMISD_RRX_r(VT, RetVT, Op0, Op0IsKill)0
;
2591
99
  
case ARMISD::SRA_FLAG: return fastEmit_ARMISD_SRA_FLAG_r(VT, RetVT, Op0, Op0IsKill)0
;
2592
99
  
case ARMISD::SRL_FLAG: return fastEmit_ARMISD_SRL_FLAG_r(VT, RetVT, Op0, Op0IsKill)0
;
2593
99
  
case ARMISD::TC_RETURN: return fastEmit_ARMISD_TC_RETURN_r(VT, RetVT, Op0, Op0IsKill)0
;
2594
99
  
case ARMISD::VCEQZ: return fastEmit_ARMISD_VCEQZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2595
99
  
case ARMISD::VCGEZ: return fastEmit_ARMISD_VCGEZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2596
99
  
case ARMISD::VCGTZ: return fastEmit_ARMISD_VCGTZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2597
99
  
case ARMISD::VCLEZ: return fastEmit_ARMISD_VCLEZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2598
99
  
case ARMISD::VCLTZ: return fastEmit_ARMISD_VCLTZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2599
99
  
case ARMISD::VDUP: return fastEmit_ARMISD_VDUP_r(VT, RetVT, Op0, Op0IsKill)0
;
2600
99
  
case ARMISD::VMOVSR: return fastEmit_ARMISD_VMOVSR_r(VT, RetVT, Op0, Op0IsKill)0
;
2601
99
  
case ARMISD::VMOVhr: return fastEmit_ARMISD_VMOVhr_r(VT, RetVT, Op0, Op0IsKill)0
;
2602
99
  
case ARMISD::VMOVrh: return fastEmit_ARMISD_VMOVrh_r(VT, RetVT, Op0, Op0IsKill)0
;
2603
99
  
case ARMISD::VREV16: return fastEmit_ARMISD_VREV16_r(VT, RetVT, Op0, Op0IsKill)0
;
2604
99
  
case ARMISD::VREV32: return fastEmit_ARMISD_VREV32_r(VT, RetVT, Op0, Op0IsKill)0
;
2605
99
  
case ARMISD::VREV64: return fastEmit_ARMISD_VREV64_r(VT, RetVT, Op0, Op0IsKill)0
;
2606
99
  
case ARMISD::WIN__DBZCHK: return fastEmit_ARMISD_WIN__DBZCHK_r(VT, RetVT, Op0, Op0IsKill)0
;
2607
99
  
case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0, Op0IsKill)0
;
2608
99
  
case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
2609
99
  
case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill)83
;
2610
99
  
case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill)0
;
2611
99
  
case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill)0
;
2612
99
  
case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill)0
;
2613
99
  
case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2614
99
  
case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill)0
;
2615
99
  
case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill)0
;
2616
99
  
case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill)0
;
2617
99
  
case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill)0
;
2618
99
  
case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill)0
;
2619
99
  
case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill)0
;
2620
99
  
case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
2621
99
  
case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill)0
;
2622
99
  
case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill)6
;
2623
99
  
case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill)0
;
2624
99
  
case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill)0
;
2625
99
  
case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill)0
;
2626
99
  
case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill)0
;
2627
99
  
case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill)0
;
2628
99
  
case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill)1
;
2629
99
  
case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)9
;
2630
99
  
case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill)0
;
2631
99
  
case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)0
;
2632
99
  
case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
2633
99
  
default: return 00
;
2634
99
  }
2635
99
}
2636
2637
// FastEmit functions for ARMISD::CMP.
2638
2639
0
unsigned fastEmit_ARMISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2640
0
  if (RetVT.SimpleTy != MVT::isVoid)
2641
0
    return 0;
2642
0
  if ((Subtarget->isThumb2())) {
2643
0
    return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2644
0
  }
2645
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
2646
0
    return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2647
0
  }
2648
0
  if ((!Subtarget->isThumb())) {
2649
0
    return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2650
0
  }
2651
0
  return 0;
2652
0
}
2653
2654
unsigned fastEmit_ARMISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2655
  switch (VT.SimpleTy) {
2656
  case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2657
  default: return 0;
2658
  }
2659
}
2660
2661
// FastEmit functions for ARMISD::CMPZ.
2662
2663
0
unsigned fastEmit_ARMISD_CMPZ_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2664
0
  if (RetVT.SimpleTy != MVT::isVoid)
2665
0
    return 0;
2666
0
  if ((Subtarget->isThumb2())) {
2667
0
    return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2668
0
  }
2669
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
2670
0
    return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2671
0
  }
2672
0
  if ((!Subtarget->isThumb())) {
2673
0
    return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2674
0
  }
2675
0
  return 0;
2676
0
}
2677
2678
unsigned fastEmit_ARMISD_CMPZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2679
  switch (VT.SimpleTy) {
2680
  case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2681
  default: return 0;
2682
  }
2683
}
2684
2685
// FastEmit functions for ARMISD::EH_SJLJ_LONGJMP.
2686
2687
0
unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2688
0
  if (RetVT.SimpleTy != MVT::isVoid)
2689
0
    return 0;
2690
0
  if ((Subtarget->isThumb()) && (Subtarget->isTargetWindows())) {
2691
0
    return fastEmitInst_rr(ARM::tInt_WIN_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2692
0
  }
2693
0
  if ((!Subtarget->isTargetWindows()) && (Subtarget->isThumb())) {
2694
0
    return fastEmitInst_rr(ARM::tInt_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2695
0
  }
2696
0
  if ((!Subtarget->isThumb())) {
2697
0
    return fastEmitInst_rr(ARM::Int_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2698
0
  }
2699
0
  return 0;
2700
0
}
2701
2702
unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2703
  switch (VT.SimpleTy) {
2704
  case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2705
  default: return 0;
2706
  }
2707
}
2708
2709
// FastEmit functions for ARMISD::EH_SJLJ_SETJMP.
2710
2711
0
unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2712
0
  if (RetVT.SimpleTy != MVT::i32)
2713
0
    return 0;
2714
0
  if ((Subtarget->isThumb2()) && (!Subtarget->hasVFP2())) {
2715
0
    return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp_nofp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2716
0
  }
2717
0
  if ((Subtarget->hasVFP2()) && (Subtarget->isThumb2())) {
2718
0
    return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2719
0
  }
2720
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
2721
0
    return fastEmitInst_rr(ARM::tInt_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2722
0
  }
2723
0
  if ((!Subtarget->isThumb()) && (!Subtarget->hasVFP2())) {
2724
0
    return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp_nofp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2725
0
  }
2726
0
  if ((Subtarget->hasVFP2()) && (!Subtarget->isThumb())) {
2727
0
    return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2728
0
  }
2729
0
  return 0;
2730
0
}
2731
2732
unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2733
  switch (VT.SimpleTy) {
2734
  case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2735
  default: return 0;
2736
  }
2737
}
2738
2739
// FastEmit functions for ARMISD::SMULWB.
2740
2741
0
unsigned fastEmit_ARMISD_SMULWB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2742
0
  if (RetVT.SimpleTy != MVT::i32)
2743
0
    return 0;
2744
0
  if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
2745
0
    return fastEmitInst_rr(ARM::t2SMULWB, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2746
0
  }
2747
0
  if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
2748
0
    return fastEmitInst_rr(ARM::SMULWB, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2749
0
  }
2750
0
  return 0;
2751
0
}
2752
2753
unsigned fastEmit_ARMISD_SMULWB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2754
  switch (VT.SimpleTy) {
2755
  case MVT::i32: return fastEmit_ARMISD_SMULWB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2756
  default: return 0;
2757
  }
2758
}
2759
2760
// FastEmit functions for ARMISD::SMULWT.
2761
2762
0
unsigned fastEmit_ARMISD_SMULWT_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2763
0
  if (RetVT.SimpleTy != MVT::i32)
2764
0
    return 0;
2765
0
  if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
2766
0
    return fastEmitInst_rr(ARM::t2SMULWT, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2767
0
  }
2768
0
  if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
2769
0
    return fastEmitInst_rr(ARM::SMULWT, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2770
0
  }
2771
0
  return 0;
2772
0
}
2773
2774
unsigned fastEmit_ARMISD_SMULWT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2775
  switch (VT.SimpleTy) {
2776
  case MVT::i32: return fastEmit_ARMISD_SMULWT_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2777
  default: return 0;
2778
  }
2779
}
2780
2781
// FastEmit functions for ARMISD::SUBS.
2782
2783
0
unsigned fastEmit_ARMISD_SUBS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2784
0
  if (RetVT.SimpleTy != MVT::i32)
2785
0
    return 0;
2786
0
  if ((Subtarget->isThumb2())) {
2787
0
    return fastEmitInst_rr(ARM::t2SUBSrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2788
0
  }
2789
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
2790
0
    return fastEmitInst_rr(ARM::tSUBSrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2791
0
  }
2792
0
  if ((!Subtarget->isThumb())) {
2793
0
    return fastEmitInst_rr(ARM::SUBSrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2794
0
  }
2795
0
  return 0;
2796
0
}
2797
2798
unsigned fastEmit_ARMISD_SUBS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2799
  switch (VT.SimpleTy) {
2800
  case MVT::i32: return fastEmit_ARMISD_SUBS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2801
  default: return 0;
2802
  }
2803
}
2804
2805
// FastEmit functions for ARMISD::VCEQ.
2806
2807
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2808
0
  if (RetVT.SimpleTy != MVT::v8i8)
2809
0
    return 0;
2810
0
  if ((Subtarget->hasNEON())) {
2811
0
    return fastEmitInst_rr(ARM::VCEQv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2812
0
  }
2813
0
  return 0;
2814
0
}
2815
2816
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2817
0
  if (RetVT.SimpleTy != MVT::v16i8)
2818
0
    return 0;
2819
0
  if ((Subtarget->hasNEON())) {
2820
0
    return fastEmitInst_rr(ARM::VCEQv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2821
0
  }
2822
0
  return 0;
2823
0
}
2824
2825
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2826
0
  if (RetVT.SimpleTy != MVT::v4i16)
2827
0
    return 0;
2828
0
  if ((Subtarget->hasNEON())) {
2829
0
    return fastEmitInst_rr(ARM::VCEQv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2830
0
  }
2831
0
  return 0;
2832
0
}
2833
2834
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2835
0
  if (RetVT.SimpleTy != MVT::v8i16)
2836
0
    return 0;
2837
0
  if ((Subtarget->hasNEON())) {
2838
0
    return fastEmitInst_rr(ARM::VCEQv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2839
0
  }
2840
0
  return 0;
2841
0
}
2842
2843
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2844
0
  if (RetVT.SimpleTy != MVT::v2i32)
2845
0
    return 0;
2846
0
  if ((Subtarget->hasNEON())) {
2847
0
    return fastEmitInst_rr(ARM::VCEQv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2848
0
  }
2849
0
  return 0;
2850
0
}
2851
2852
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2853
0
  if (RetVT.SimpleTy != MVT::v4i32)
2854
0
    return 0;
2855
0
  if ((Subtarget->hasNEON())) {
2856
0
    return fastEmitInst_rr(ARM::VCEQv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2857
0
  }
2858
0
  return 0;
2859
0
}
2860
2861
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2862
0
  if (RetVT.SimpleTy != MVT::v4i16)
2863
0
    return 0;
2864
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2865
0
    return fastEmitInst_rr(ARM::VCEQhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2866
0
  }
2867
0
  return 0;
2868
0
}
2869
2870
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2871
0
  if (RetVT.SimpleTy != MVT::v8i16)
2872
0
    return 0;
2873
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2874
0
    return fastEmitInst_rr(ARM::VCEQhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2875
0
  }
2876
0
  return 0;
2877
0
}
2878
2879
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2880
0
  if (RetVT.SimpleTy != MVT::v2i32)
2881
0
    return 0;
2882
0
  if ((Subtarget->hasNEON())) {
2883
0
    return fastEmitInst_rr(ARM::VCEQfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2884
0
  }
2885
0
  return 0;
2886
0
}
2887
2888
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2889
0
  if (RetVT.SimpleTy != MVT::v4i32)
2890
0
    return 0;
2891
0
  if ((Subtarget->hasNEON())) {
2892
0
    return fastEmitInst_rr(ARM::VCEQfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2893
0
  }
2894
0
  return 0;
2895
0
}
2896
2897
unsigned fastEmit_ARMISD_VCEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2898
  switch (VT.SimpleTy) {
2899
  case MVT::v8i8: return fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2900
  case MVT::v16i8: return fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2901
  case MVT::v4i16: return fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2902
  case MVT::v8i16: return fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2903
  case MVT::v2i32: return fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2904
  case MVT::v4i32: return fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2905
  case MVT::v4f16: return fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2906
  case MVT::v8f16: return fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2907
  case MVT::v2f32: return fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2908
  case MVT::v4f32: return fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2909
  default: return 0;
2910
  }
2911
}
2912
2913
// FastEmit functions for ARMISD::VCGE.
2914
2915
0
unsigned fastEmit_ARMISD_VCGE_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2916
0
  if (RetVT.SimpleTy != MVT::v8i8)
2917
0
    return 0;
2918
0
  if ((Subtarget->hasNEON())) {
2919
0
    return fastEmitInst_rr(ARM::VCGEsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2920
0
  }
2921
0
  return 0;
2922
0
}
2923
2924
0
unsigned fastEmit_ARMISD_VCGE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2925
0
  if (RetVT.SimpleTy != MVT::v16i8)
2926
0
    return 0;
2927
0
  if ((Subtarget->hasNEON())) {
2928
0
    return fastEmitInst_rr(ARM::VCGEsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2929
0
  }
2930
0
  return 0;
2931
0
}
2932
2933
0
unsigned fastEmit_ARMISD_VCGE_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2934
0
  if (RetVT.SimpleTy != MVT::v4i16)
2935
0
    return 0;
2936
0
  if ((Subtarget->hasNEON())) {
2937
0
    return fastEmitInst_rr(ARM::VCGEsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2938
0
  }
2939
0
  return 0;
2940
0
}
2941
2942
0
unsigned fastEmit_ARMISD_VCGE_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2943
0
  if (RetVT.SimpleTy != MVT::v8i16)
2944
0
    return 0;
2945
0
  if ((Subtarget->hasNEON())) {
2946
0
    return fastEmitInst_rr(ARM::VCGEsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2947
0
  }
2948
0
  return 0;
2949
0
}
2950
2951
0
unsigned fastEmit_ARMISD_VCGE_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2952
0
  if (RetVT.SimpleTy != MVT::v2i32)
2953
0
    return 0;
2954
0
  if ((Subtarget->hasNEON())) {
2955
0
    return fastEmitInst_rr(ARM::VCGEsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2956
0
  }
2957
0
  return 0;
2958
0
}
2959
2960
0
unsigned fastEmit_ARMISD_VCGE_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2961
0
  if (RetVT.SimpleTy != MVT::v4i32)
2962
0
    return 0;
2963
0
  if ((Subtarget->hasNEON())) {
2964
0
    return fastEmitInst_rr(ARM::VCGEsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2965
0
  }
2966
0
  return 0;
2967
0
}
2968
2969
0
unsigned fastEmit_ARMISD_VCGE_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2970
0
  if (RetVT.SimpleTy != MVT::v4i16)
2971
0
    return 0;
2972
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2973
0
    return fastEmitInst_rr(ARM::VCGEhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2974
0
  }
2975
0
  return 0;
2976
0
}
2977
2978
0
unsigned fastEmit_ARMISD_VCGE_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2979
0
  if (RetVT.SimpleTy != MVT::v8i16)
2980
0
    return 0;
2981
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2982
0
    return fastEmitInst_rr(ARM::VCGEhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2983
0
  }
2984
0
  return 0;
2985
0
}
2986
2987
0
unsigned fastEmit_ARMISD_VCGE_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2988
0
  if (RetVT.SimpleTy != MVT::v2i32)
2989
0
    return 0;
2990
0
  if ((Subtarget->hasNEON())) {
2991
0
    return fastEmitInst_rr(ARM::VCGEfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2992
0
  }
2993
0
  return 0;
2994
0
}
2995
2996
0
unsigned fastEmit_ARMISD_VCGE_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2997
0
  if (RetVT.SimpleTy != MVT::v4i32)
2998
0
    return 0;
2999
0
  if ((Subtarget->hasNEON())) {
3000
0
    return fastEmitInst_rr(ARM::VCGEfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3001
0
  }
3002
0
  return 0;
3003
0
}
3004
3005
unsigned fastEmit_ARMISD_VCGE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3006
  switch (VT.SimpleTy) {
3007
  case MVT::v8i8: return fastEmit_ARMISD_VCGE_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3008
  case MVT::v16i8: return fastEmit_ARMISD_VCGE_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3009
  case MVT::v4i16: return fastEmit_ARMISD_VCGE_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3010
  case MVT::v8i16: return fastEmit_ARMISD_VCGE_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3011
  case MVT::v2i32: return fastEmit_ARMISD_VCGE_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3012
  case MVT::v4i32: return fastEmit_ARMISD_VCGE_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3013
  case MVT::v4f16: return fastEmit_ARMISD_VCGE_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3014
  case MVT::v8f16: return fastEmit_ARMISD_VCGE_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3015
  case MVT::v2f32: return fastEmit_ARMISD_VCGE_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3016
  case MVT::v4f32: return fastEmit_ARMISD_VCGE_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3017
  default: return 0;
3018
  }
3019
}
3020
3021
// FastEmit functions for ARMISD::VCGEU.
3022
3023
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3024
0
  if (RetVT.SimpleTy != MVT::v8i8)
3025
0
    return 0;
3026
0
  if ((Subtarget->hasNEON())) {
3027
0
    return fastEmitInst_rr(ARM::VCGEuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3028
0
  }
3029
0
  return 0;
3030
0
}
3031
3032
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3033
0
  if (RetVT.SimpleTy != MVT::v16i8)
3034
0
    return 0;
3035
0
  if ((Subtarget->hasNEON())) {
3036
0
    return fastEmitInst_rr(ARM::VCGEuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3037
0
  }
3038
0
  return 0;
3039
0
}
3040
3041
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3042
0
  if (RetVT.SimpleTy != MVT::v4i16)
3043
0
    return 0;
3044
0
  if ((Subtarget->hasNEON())) {
3045
0
    return fastEmitInst_rr(ARM::VCGEuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3046
0
  }
3047
0
  return 0;
3048
0
}
3049
3050
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3051
0
  if (RetVT.SimpleTy != MVT::v8i16)
3052
0
    return 0;
3053
0
  if ((Subtarget->hasNEON())) {
3054
0
    return fastEmitInst_rr(ARM::VCGEuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3055
0
  }
3056
0
  return 0;
3057
0
}
3058
3059
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3060
0
  if (RetVT.SimpleTy != MVT::v2i32)
3061
0
    return 0;
3062
0
  if ((Subtarget->hasNEON())) {
3063
0
    return fastEmitInst_rr(ARM::VCGEuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3064
0
  }
3065
0
  return 0;
3066
0
}
3067
3068
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3069
0
  if (RetVT.SimpleTy != MVT::v4i32)
3070
0
    return 0;
3071
0
  if ((Subtarget->hasNEON())) {
3072
0
    return fastEmitInst_rr(ARM::VCGEuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3073
0
  }
3074
0
  return 0;
3075
0
}
3076
3077
unsigned fastEmit_ARMISD_VCGEU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3078
  switch (VT.SimpleTy) {
3079
  case MVT::v8i8: return fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3080
  case MVT::v16i8: return fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3081
  case MVT::v4i16: return fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3082
  case MVT::v8i16: return fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3083
  case MVT::v2i32: return fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3084
  case MVT::v4i32: return fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3085
  default: return 0;
3086
  }
3087
}
3088
3089
// FastEmit functions for ARMISD::VCGT.
3090
3091
0
unsigned fastEmit_ARMISD_VCGT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3092
0
  if (RetVT.SimpleTy != MVT::v8i8)
3093
0
    return 0;
3094
0
  if ((Subtarget->hasNEON())) {
3095
0
    return fastEmitInst_rr(ARM::VCGTsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3096
0
  }
3097
0
  return 0;
3098
0
}
3099
3100
0
unsigned fastEmit_ARMISD_VCGT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3101
0
  if (RetVT.SimpleTy != MVT::v16i8)
3102
0
    return 0;
3103
0
  if ((Subtarget->hasNEON())) {
3104
0
    return fastEmitInst_rr(ARM::VCGTsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3105
0
  }
3106
0
  return 0;
3107
0
}
3108
3109
0
unsigned fastEmit_ARMISD_VCGT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3110
0
  if (RetVT.SimpleTy != MVT::v4i16)
3111
0
    return 0;
3112
0
  if ((Subtarget->hasNEON())) {
3113
0
    return fastEmitInst_rr(ARM::VCGTsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3114
0
  }
3115
0
  return 0;
3116
0
}
3117
3118
0
unsigned fastEmit_ARMISD_VCGT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3119
0
  if (RetVT.SimpleTy != MVT::v8i16)
3120
0
    return 0;
3121
0
  if ((Subtarget->hasNEON())) {
3122
0
    return fastEmitInst_rr(ARM::VCGTsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3123
0
  }
3124
0
  return 0;
3125
0
}
3126
3127
0
unsigned fastEmit_ARMISD_VCGT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3128
0
  if (RetVT.SimpleTy != MVT::v2i32)
3129
0
    return 0;
3130
0
  if ((Subtarget->hasNEON())) {
3131
0
    return fastEmitInst_rr(ARM::VCGTsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3132
0
  }
3133
0
  return 0;
3134
0
}
3135
3136
0
unsigned fastEmit_ARMISD_VCGT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3137
0
  if (RetVT.SimpleTy != MVT::v4i32)
3138
0
    return 0;
3139
0
  if ((Subtarget->hasNEON())) {
3140
0
    return fastEmitInst_rr(ARM::VCGTsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3141
0
  }
3142
0
  return 0;
3143
0
}
3144
3145
0
unsigned fastEmit_ARMISD_VCGT_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3146
0
  if (RetVT.SimpleTy != MVT::v4i16)
3147
0
    return 0;
3148
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3149
0
    return fastEmitInst_rr(ARM::VCGThd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3150
0
  }
3151
0
  return 0;
3152
0
}
3153
3154
0
unsigned fastEmit_ARMISD_VCGT_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3155
0
  if (RetVT.SimpleTy != MVT::v8i16)
3156
0
    return 0;
3157
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3158
0
    return fastEmitInst_rr(ARM::VCGThq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3159
0
  }
3160
0
  return 0;
3161
0
}
3162
3163
0
unsigned fastEmit_ARMISD_VCGT_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3164
0
  if (RetVT.SimpleTy != MVT::v2i32)
3165
0
    return 0;
3166
0
  if ((Subtarget->hasNEON())) {
3167
0
    return fastEmitInst_rr(ARM::VCGTfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3168
0
  }
3169
0
  return 0;
3170
0
}
3171
3172
0
unsigned fastEmit_ARMISD_VCGT_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3173
0
  if (RetVT.SimpleTy != MVT::v4i32)
3174
0
    return 0;
3175
0
  if ((Subtarget->hasNEON())) {
3176
0
    return fastEmitInst_rr(ARM::VCGTfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3177
0
  }
3178
0
  return 0;
3179
0
}
3180
3181
unsigned fastEmit_ARMISD_VCGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3182
  switch (VT.SimpleTy) {
3183
  case MVT::v8i8: return fastEmit_ARMISD_VCGT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3184
  case MVT::v16i8: return fastEmit_ARMISD_VCGT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3185
  case MVT::v4i16: return fastEmit_ARMISD_VCGT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3186
  case MVT::v8i16: return fastEmit_ARMISD_VCGT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3187
  case MVT::v2i32: return fastEmit_ARMISD_VCGT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3188
  case MVT::v4i32: return fastEmit_ARMISD_VCGT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3189
  case MVT::v4f16: return fastEmit_ARMISD_VCGT_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3190
  case MVT::v8f16: return fastEmit_ARMISD_VCGT_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3191
  case MVT::v2f32: return fastEmit_ARMISD_VCGT_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3192
  case MVT::v4f32: return fastEmit_ARMISD_VCGT_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3193
  default: return 0;
3194
  }
3195
}
3196
3197
// FastEmit functions for ARMISD::VCGTU.
3198
3199
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3200
0
  if (RetVT.SimpleTy != MVT::v8i8)
3201
0
    return 0;
3202
0
  if ((Subtarget->hasNEON())) {
3203
0
    return fastEmitInst_rr(ARM::VCGTuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3204
0
  }
3205
0
  return 0;
3206
0
}
3207
3208
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3209
0
  if (RetVT.SimpleTy != MVT::v16i8)
3210
0
    return 0;
3211
0
  if ((Subtarget->hasNEON())) {
3212
0
    return fastEmitInst_rr(ARM::VCGTuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3213
0
  }
3214
0
  return 0;
3215
0
}
3216
3217
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3218
0
  if (RetVT.SimpleTy != MVT::v4i16)
3219
0
    return 0;
3220
0
  if ((Subtarget->hasNEON())) {
3221
0
    return fastEmitInst_rr(ARM::VCGTuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3222
0
  }
3223
0
  return 0;
3224
0
}
3225
3226
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3227
0
  if (RetVT.SimpleTy != MVT::v8i16)
3228
0
    return 0;
3229
0
  if ((Subtarget->hasNEON())) {
3230
0
    return fastEmitInst_rr(ARM::VCGTuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3231
0
  }
3232
0
  return 0;
3233
0
}
3234
3235
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3236
0
  if (RetVT.SimpleTy != MVT::v2i32)
3237
0
    return 0;
3238
0
  if ((Subtarget->hasNEON())) {
3239
0
    return fastEmitInst_rr(ARM::VCGTuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3240
0
  }
3241
0
  return 0;
3242
0
}
3243
3244
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3245
0
  if (RetVT.SimpleTy != MVT::v4i32)
3246
0
    return 0;
3247
0
  if ((Subtarget->hasNEON())) {
3248
0
    return fastEmitInst_rr(ARM::VCGTuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3249
0
  }
3250
0
  return 0;
3251
0
}
3252
3253
unsigned fastEmit_ARMISD_VCGTU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3254
  switch (VT.SimpleTy) {
3255
  case MVT::v8i8: return fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3256
  case MVT::v16i8: return fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3257
  case MVT::v4i16: return fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3258
  case MVT::v8i16: return fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3259
  case MVT::v2i32: return fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3260
  case MVT::v4i32: return fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3261
  default: return 0;
3262
  }
3263
}
3264
3265
// FastEmit functions for ARMISD::VMOVDRR.
3266
3267
0
unsigned fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3268
0
  if (RetVT.SimpleTy != MVT::f64)
3269
0
    return 0;
3270
0
  if ((Subtarget->hasVFP2())) {
3271
0
    return fastEmitInst_rr(ARM::VMOVDRR, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3272
0
  }
3273
0
  return 0;
3274
0
}
3275
3276
unsigned fastEmit_ARMISD_VMOVDRR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3277
  switch (VT.SimpleTy) {
3278
  case MVT::i32: return fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3279
  default: return 0;
3280
  }
3281
}
3282
3283
// FastEmit functions for ARMISD::VMULLs.
3284
3285
0
unsigned fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3286
0
  if (RetVT.SimpleTy != MVT::v8i16)
3287
0
    return 0;
3288
0
  if ((Subtarget->hasNEON())) {
3289
0
    return fastEmitInst_rr(ARM::VMULLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3290
0
  }
3291
0
  return 0;
3292
0
}
3293
3294
0
unsigned fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3295
0
  if (RetVT.SimpleTy != MVT::v4i32)
3296
0
    return 0;
3297
0
  if ((Subtarget->hasNEON())) {
3298
0
    return fastEmitInst_rr(ARM::VMULLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3299
0
  }
3300
0
  return 0;
3301
0
}
3302
3303
0
unsigned fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3304
0
  if (RetVT.SimpleTy != MVT::v2i64)
3305
0
    return 0;
3306
0
  if ((Subtarget->hasNEON())) {
3307
0
    return fastEmitInst_rr(ARM::VMULLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3308
0
  }
3309
0
  return 0;
3310
0
}
3311
3312
unsigned fastEmit_ARMISD_VMULLs_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3313
  switch (VT.SimpleTy) {
3314
  case MVT::v8i8: return fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3315
  case MVT::v4i16: return fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3316
  case MVT::v2i32: return fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3317
  default: return 0;
3318
  }
3319
}
3320
3321
// FastEmit functions for ARMISD::VMULLu.
3322
3323
0
unsigned fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3324
0
  if (RetVT.SimpleTy != MVT::v8i16)
3325
0
    return 0;
3326
0
  if ((Subtarget->hasNEON())) {
3327
0
    return fastEmitInst_rr(ARM::VMULLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3328
0
  }
3329
0
  return 0;
3330
0
}
3331
3332
0
unsigned fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3333
0
  if (RetVT.SimpleTy != MVT::v4i32)
3334
0
    return 0;
3335
0
  if ((Subtarget->hasNEON())) {
3336
0
    return fastEmitInst_rr(ARM::VMULLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3337
0
  }
3338
0
  return 0;
3339
0
}
3340
3341
0
unsigned fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3342
0
  if (RetVT.SimpleTy != MVT::v2i64)
3343
0
    return 0;
3344
0
  if ((Subtarget->hasNEON())) {
3345
0
    return fastEmitInst_rr(ARM::VMULLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3346
0
  }
3347
0
  return 0;
3348
0
}
3349
3350
unsigned fastEmit_ARMISD_VMULLu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3351
  switch (VT.SimpleTy) {
3352
  case MVT::v8i8: return fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3353
  case MVT::v4i16: return fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3354
  case MVT::v2i32: return fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3355
  default: return 0;
3356
  }
3357
}
3358
3359
// FastEmit functions for ARMISD::VTBL1.
3360
3361
0
unsigned fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3362
0
  if (RetVT.SimpleTy != MVT::v8i8)
3363
0
    return 0;
3364
0
  if ((Subtarget->hasNEON())) {
3365
0
    return fastEmitInst_rr(ARM::VTBL1, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3366
0
  }
3367
0
  return 0;
3368
0
}
3369
3370
unsigned fastEmit_ARMISD_VTBL1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3371
  switch (VT.SimpleTy) {
3372
  case MVT::v8i8: return fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3373
  default: return 0;
3374
  }
3375
}
3376
3377
// FastEmit functions for ARMISD::VTST.
3378
3379
0
unsigned fastEmit_ARMISD_VTST_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3380
0
  if (RetVT.SimpleTy != MVT::v8i8)
3381
0
    return 0;
3382
0
  if ((Subtarget->hasNEON())) {
3383
0
    return fastEmitInst_rr(ARM::VTSTv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3384
0
  }
3385
0
  return 0;
3386
0
}
3387
3388
0
unsigned fastEmit_ARMISD_VTST_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3389
0
  if (RetVT.SimpleTy != MVT::v16i8)
3390
0
    return 0;
3391
0
  if ((Subtarget->hasNEON())) {
3392
0
    return fastEmitInst_rr(ARM::VTSTv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3393
0
  }
3394
0
  return 0;
3395
0
}
3396
3397
0
unsigned fastEmit_ARMISD_VTST_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3398
0
  if (RetVT.SimpleTy != MVT::v4i16)
3399
0
    return 0;
3400
0
  if ((Subtarget->hasNEON())) {
3401
0
    return fastEmitInst_rr(ARM::VTSTv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3402
0
  }
3403
0
  return 0;
3404
0
}
3405
3406
0
unsigned fastEmit_ARMISD_VTST_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3407
0
  if (RetVT.SimpleTy != MVT::v8i16)
3408
0
    return 0;
3409
0
  if ((Subtarget->hasNEON())) {
3410
0
    return fastEmitInst_rr(ARM::VTSTv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3411
0
  }
3412
0
  return 0;
3413
0
}
3414
3415
0
unsigned fastEmit_ARMISD_VTST_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3416
0
  if (RetVT.SimpleTy != MVT::v2i32)
3417
0
    return 0;
3418
0
  if ((Subtarget->hasNEON())) {
3419
0
    return fastEmitInst_rr(ARM::VTSTv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3420
0
  }
3421
0
  return 0;
3422
0
}
3423
3424
0
unsigned fastEmit_ARMISD_VTST_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3425
0
  if (RetVT.SimpleTy != MVT::v4i32)
3426
0
    return 0;
3427
0
  if ((Subtarget->hasNEON())) {
3428
0
    return fastEmitInst_rr(ARM::VTSTv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3429
0
  }
3430
0
  return 0;
3431
0
}
3432
3433
unsigned fastEmit_ARMISD_VTST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3434
  switch (VT.SimpleTy) {
3435
  case MVT::v8i8: return fastEmit_ARMISD_VTST_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3436
  case MVT::v16i8: return fastEmit_ARMISD_VTST_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3437
  case MVT::v4i16: return fastEmit_ARMISD_VTST_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3438
  case MVT::v8i16: return fastEmit_ARMISD_VTST_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3439
  case MVT::v2i32: return fastEmit_ARMISD_VTST_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3440
  case MVT::v4i32: return fastEmit_ARMISD_VTST_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3441
  default: return 0;
3442
  }
3443
}
3444
3445
// FastEmit functions for ISD::ADD.
3446
3447
94
unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3448
94
  if (RetVT.SimpleTy != MVT::i32)
3449
0
    return 0;
3450
94
  if ((Subtarget->isThumb2())) {
3451
20
    return fastEmitInst_rr(ARM::t2ADDrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3452
20
  }
3453
74
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
3454
0
    return fastEmitInst_rr(ARM::tADDrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3455
0
  }
3456
74
  if ((!Subtarget->isThumb())) {
3457
74
    return fastEmitInst_rr(ARM::ADDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3458
74
  }
3459
0
  return 0;
3460
0
}
3461
3462
0
unsigned fastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3463
0
  if (RetVT.SimpleTy != MVT::v8i8)
3464
0
    return 0;
3465
0
  if ((Subtarget->hasNEON())) {
3466
0
    return fastEmitInst_rr(ARM::VADDv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3467
0
  }
3468
0
  return 0;
3469
0
}
3470
3471
0
unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3472
0
  if (RetVT.SimpleTy != MVT::v16i8)
3473
0
    return 0;
3474
0
  if ((Subtarget->hasNEON())) {
3475
0
    return fastEmitInst_rr(ARM::VADDv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3476
0
  }
3477
0
  return 0;
3478
0
}
3479
3480
0
unsigned fastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3481
0
  if (RetVT.SimpleTy != MVT::v4i16)
3482
0
    return 0;
3483
0
  if ((Subtarget->hasNEON())) {
3484
0
    return fastEmitInst_rr(ARM::VADDv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3485
0
  }
3486
0
  return 0;
3487
0
}
3488
3489
0
unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3490
0
  if (RetVT.SimpleTy != MVT::v8i16)
3491
0
    return 0;
3492
0
  if ((Subtarget->hasNEON())) {
3493
0
    return fastEmitInst_rr(ARM::VADDv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3494
0
  }
3495
0
  return 0;
3496
0
}
3497
3498
0
unsigned fastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3499
0
  if (RetVT.SimpleTy != MVT::v2i32)
3500
0
    return 0;
3501
0
  if ((Subtarget->hasNEON())) {
3502
0
    return fastEmitInst_rr(ARM::VADDv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3503
0
  }
3504
0
  return 0;
3505
0
}
3506
3507
0
unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3508
0
  if (RetVT.SimpleTy != MVT::v4i32)
3509
0
    return 0;
3510
0
  if ((Subtarget->hasNEON())) {
3511
0
    return fastEmitInst_rr(ARM::VADDv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3512
0
  }
3513
0
  return 0;
3514
0
}
3515
3516
0
unsigned fastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3517
0
  if (RetVT.SimpleTy != MVT::v1i64)
3518
0
    return 0;
3519
0
  if ((Subtarget->hasNEON())) {
3520
0
    return fastEmitInst_rr(ARM::VADDv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3521
0
  }
3522
0
  return 0;
3523
0
}
3524
3525
0
unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3526
0
  if (RetVT.SimpleTy != MVT::v2i64)
3527
0
    return 0;
3528
0
  if ((Subtarget->hasNEON())) {
3529
0
    return fastEmitInst_rr(ARM::VADDv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3530
0
  }
3531
0
  return 0;
3532
0
}
3533
3534
94
unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3535
94
  switch (VT.SimpleTy) {
3536
94
  case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3537
94
  
case MVT::v8i8: return fastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3538
94
  
case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3539
94
  
case MVT::v4i16: return fastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3540
94
  
case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3541
94
  
case MVT::v2i32: return fastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3542
94
  
case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3543
94
  
case MVT::v1i64: return fastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3544
94
  
case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3545
94
  
default: return 00
;
3546
94
  }
3547
94
}
3548
3549
// FastEmit functions for ISD::AND.
3550
3551
0
unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3552
0
  if (RetVT.SimpleTy != MVT::i32)
3553
0
    return 0;
3554
0
  if ((Subtarget->isThumb2())) {
3555
0
    return fastEmitInst_rr(ARM::t2ANDrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3556
0
  }
3557
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
3558
0
    return fastEmitInst_rr(ARM::tAND, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3559
0
  }
3560
0
  if ((!Subtarget->isThumb())) {
3561
0
    return fastEmitInst_rr(ARM::ANDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3562
0
  }
3563
0
  return 0;
3564
0
}
3565
3566
0
unsigned fastEmit_ISD_AND_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3567
0
  if (RetVT.SimpleTy != MVT::v2i32)
3568
0
    return 0;
3569
0
  if ((Subtarget->hasNEON())) {
3570
0
    return fastEmitInst_rr(ARM::VANDd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3571
0
  }
3572
0
  return 0;
3573
0
}
3574
3575
0
unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3576
0
  if (RetVT.SimpleTy != MVT::v4i32)
3577
0
    return 0;
3578
0
  if ((Subtarget->hasNEON())) {
3579
0
    return fastEmitInst_rr(ARM::VANDq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3580
0
  }
3581
0
  return 0;
3582
0
}
3583
3584
unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3585
  switch (VT.SimpleTy) {
3586
  case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3587
  case MVT::v2i32: return fastEmit_ISD_AND_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3588
  case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3589
  default: return 0;
3590
  }
3591
}
3592
3593
// FastEmit functions for ISD::FADD.
3594
3595
0
unsigned fastEmit_ISD_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3596
0
  if (RetVT.SimpleTy != MVT::f16)
3597
0
    return 0;
3598
0
  if ((Subtarget->hasFullFP16())) {
3599
0
    return fastEmitInst_rr(ARM::VADDH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3600
0
  }
3601
0
  return 0;
3602
0
}
3603
3604
17
unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3605
17
  if (RetVT.SimpleTy != MVT::f32)
3606
0
    return 0;
3607
17
  if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
3608
17
    return fastEmitInst_rr(ARM::VADDS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3609
17
  }
3610
0
  return 0;
3611
0
}
3612
3613
15
unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3614
15
  if (RetVT.SimpleTy != MVT::f64)
3615
0
    return 0;
3616
15
  if ((!Subtarget->isFPOnlySP()) && 
(Subtarget->hasVFP2())14
) {
3617
14
    return fastEmitInst_rr(ARM::VADDD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3618
14
  }
3619
1
  return 0;
3620
1
}
3621
3622
0
unsigned fastEmit_ISD_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3623
0
  if (RetVT.SimpleTy != MVT::v4f16)
3624
0
    return 0;
3625
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3626
0
    return fastEmitInst_rr(ARM::VADDhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3627
0
  }
3628
0
  return 0;
3629
0
}
3630
3631
0
unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3632
0
  if (RetVT.SimpleTy != MVT::v8f16)
3633
0
    return 0;
3634
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3635
0
    return fastEmitInst_rr(ARM::VADDhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3636
0
  }
3637
0
  return 0;
3638
0
}
3639
3640
0
unsigned fastEmit_ISD_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3641
0
  if (RetVT.SimpleTy != MVT::v2f32)
3642
0
    return 0;
3643
0
  if ((Subtarget->hasNEON())) {
3644
0
    return fastEmitInst_rr(ARM::VADDfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3645
0
  }
3646
0
  return 0;
3647
0
}
3648
3649
0
unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3650
0
  if (RetVT.SimpleTy != MVT::v4f32)
3651
0
    return 0;
3652
0
  if ((Subtarget->hasNEON())) {
3653
0
    return fastEmitInst_rr(ARM::VADDfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3654
0
  }
3655
0
  return 0;
3656
0
}
3657
3658
33
unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3659
33
  switch (VT.SimpleTy) {
3660
33
  
case MVT::f16: return fastEmit_ISD_FADD_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3661
33
  
case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)17
;
3662
33
  
case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)15
;
3663
33
  
case MVT::v4f16: return fastEmit_ISD_FADD_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3664
33
  
case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3665
33
  
case MVT::v2f32: return fastEmit_ISD_FADD_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3666
33
  
case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3667
33
  
default: return 01
;
3668
33
  }
3669
33
}
3670
3671
// FastEmit functions for ISD::FDIV.
3672
3673
0
unsigned fastEmit_ISD_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3674
0
  if (RetVT.SimpleTy != MVT::f16)
3675
0
    return 0;
3676
0
  if ((Subtarget->hasFullFP16())) {
3677
0
    return fastEmitInst_rr(ARM::VDIVH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3678
0
  }
3679
0
  return 0;
3680
0
}
3681
3682
0
unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3683
0
  if (RetVT.SimpleTy != MVT::f32)
3684
0
    return 0;
3685
0
  if ((Subtarget->hasVFP2())) {
3686
0
    return fastEmitInst_rr(ARM::VDIVS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3687
0
  }
3688
0
  return 0;
3689
0
}
3690
3691
0
unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3692
0
  if (RetVT.SimpleTy != MVT::f64)
3693
0
    return 0;
3694
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
3695
0
    return fastEmitInst_rr(ARM::VDIVD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3696
0
  }
3697
0
  return 0;
3698
0
}
3699
3700
unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3701
  switch (VT.SimpleTy) {
3702
  case MVT::f16: return fastEmit_ISD_FDIV_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3703
  case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3704
  case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3705
  default: return 0;
3706
  }
3707
}
3708
3709
// FastEmit functions for ISD::FMAXIMUM.
3710
3711
0
unsigned fastEmit_ISD_FMAXIMUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3712
0
  if (RetVT.SimpleTy != MVT::v4f16)
3713
0
    return 0;
3714
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3715
0
    return fastEmitInst_rr(ARM::VMAXhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3716
0
  }
3717
0
  return 0;
3718
0
}
3719
3720
0
unsigned fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3721
0
  if (RetVT.SimpleTy != MVT::v8f16)
3722
0
    return 0;
3723
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3724
0
    return fastEmitInst_rr(ARM::VMAXhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3725
0
  }
3726
0
  return 0;
3727
0
}
3728
3729
0
unsigned fastEmit_ISD_FMAXIMUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3730
0
  if (RetVT.SimpleTy != MVT::v2f32)
3731
0
    return 0;
3732
0
  if ((Subtarget->hasNEON())) {
3733
0
    return fastEmitInst_rr(ARM::VMAXfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3734
0
  }
3735
0
  return 0;
3736
0
}
3737
3738
0
unsigned fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3739
0
  if (RetVT.SimpleTy != MVT::v4f32)
3740
0
    return 0;
3741
0
  if ((Subtarget->hasNEON())) {
3742
0
    return fastEmitInst_rr(ARM::VMAXfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3743
0
  }
3744
0
  return 0;
3745
0
}
3746
3747
unsigned fastEmit_ISD_FMAXIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3748
  switch (VT.SimpleTy) {
3749
  case MVT::v4f16: return fastEmit_ISD_FMAXIMUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3750
  case MVT::v8f16: return fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3751
  case MVT::v2f32: return fastEmit_ISD_FMAXIMUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3752
  case MVT::v4f32: return fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3753
  default: return 0;
3754
  }
3755
}
3756
3757
// FastEmit functions for ISD::FMAXNUM.
3758
3759
0
unsigned fastEmit_ISD_FMAXNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3760
0
  if (RetVT.SimpleTy != MVT::f16)
3761
0
    return 0;
3762
0
  if ((Subtarget->hasFullFP16())) {
3763
0
    return fastEmitInst_rr(ARM::VMAXNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3764
0
  }
3765
0
  return 0;
3766
0
}
3767
3768
0
unsigned fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3769
0
  if (RetVT.SimpleTy != MVT::f32)
3770
0
    return 0;
3771
0
  if ((Subtarget->hasFPARMv8())) {
3772
0
    return fastEmitInst_rr(ARM::VMAXNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3773
0
  }
3774
0
  return 0;
3775
0
}
3776
3777
0
unsigned fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3778
0
  if (RetVT.SimpleTy != MVT::f64)
3779
0
    return 0;
3780
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
3781
0
    return fastEmitInst_rr(ARM::VMAXNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3782
0
  }
3783
0
  return 0;
3784
0
}
3785
3786
0
unsigned fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3787
0
  if (RetVT.SimpleTy != MVT::v4f16)
3788
0
    return 0;
3789
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3790
0
    return fastEmitInst_rr(ARM::VMAXNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3791
0
  }
3792
0
  return 0;
3793
0
}
3794
3795
0
unsigned fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3796
0
  if (RetVT.SimpleTy != MVT::v8f16)
3797
0
    return 0;
3798
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3799
0
    return fastEmitInst_rr(ARM::VMAXNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3800
0
  }
3801
0
  return 0;
3802
0
}
3803
3804
0
unsigned fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3805
0
  if (RetVT.SimpleTy != MVT::v2f32)
3806
0
    return 0;
3807
0
  if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3808
0
    return fastEmitInst_rr(ARM::VMAXNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3809
0
  }
3810
0
  return 0;
3811
0
}
3812
3813
0
unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3814
0
  if (RetVT.SimpleTy != MVT::v4f32)
3815
0
    return 0;
3816
0
  if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3817
0
    return fastEmitInst_rr(ARM::VMAXNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3818
0
  }
3819
0
  return 0;
3820
0
}
3821
3822
unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3823
  switch (VT.SimpleTy) {
3824
  case MVT::f16: return fastEmit_ISD_FMAXNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3825
  case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3826
  case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3827
  case MVT::v4f16: return fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3828
  case MVT::v8f16: return fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3829
  case MVT::v2f32: return fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3830
  case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3831
  default: return 0;
3832
  }
3833
}
3834
3835
// FastEmit functions for ISD::FMINIMUM.
3836
3837
0
unsigned fastEmit_ISD_FMINIMUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3838
0
  if (RetVT.SimpleTy != MVT::v4f16)
3839
0
    return 0;
3840
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3841
0
    return fastEmitInst_rr(ARM::VMINhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3842
0
  }
3843
0
  return 0;
3844
0
}
3845
3846
0
unsigned fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3847
0
  if (RetVT.SimpleTy != MVT::v8f16)
3848
0
    return 0;
3849
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3850
0
    return fastEmitInst_rr(ARM::VMINhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3851
0
  }
3852
0
  return 0;
3853
0
}
3854
3855
0
unsigned fastEmit_ISD_FMINIMUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3856
0
  if (RetVT.SimpleTy != MVT::v2f32)
3857
0
    return 0;
3858
0
  if ((Subtarget->hasNEON())) {
3859
0
    return fastEmitInst_rr(ARM::VMINfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3860
0
  }
3861
0
  return 0;
3862
0
}
3863
3864
0
unsigned fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3865
0
  if (RetVT.SimpleTy != MVT::v4f32)
3866
0
    return 0;
3867
0
  if ((Subtarget->hasNEON())) {
3868
0
    return fastEmitInst_rr(ARM::VMINfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3869
0
  }
3870
0
  return 0;
3871
0
}
3872
3873
unsigned fastEmit_ISD_FMINIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3874
  switch (VT.SimpleTy) {
3875
  case MVT::v4f16: return fastEmit_ISD_FMINIMUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3876
  case MVT::v8f16: return fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3877
  case MVT::v2f32: return fastEmit_ISD_FMINIMUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3878
  case MVT::v4f32: return fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3879
  default: return 0;
3880
  }
3881
}
3882
3883
// FastEmit functions for ISD::FMINNUM.
3884
3885
0
unsigned fastEmit_ISD_FMINNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3886
0
  if (RetVT.SimpleTy != MVT::f16)
3887
0
    return 0;
3888
0
  if ((Subtarget->hasFullFP16())) {
3889
0
    return fastEmitInst_rr(ARM::VMINNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3890
0
  }
3891
0
  return 0;
3892
0
}
3893
3894
0
unsigned fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3895
0
  if (RetVT.SimpleTy != MVT::f32)
3896
0
    return 0;
3897
0
  if ((Subtarget->hasFPARMv8())) {
3898
0
    return fastEmitInst_rr(ARM::VMINNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3899
0
  }
3900
0
  return 0;
3901
0
}
3902
3903
0
unsigned fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3904
0
  if (RetVT.SimpleTy != MVT::f64)
3905
0
    return 0;
3906
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
3907
0
    return fastEmitInst_rr(ARM::VMINNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3908
0
  }
3909
0
  return 0;
3910
0
}
3911
3912
0
unsigned fastEmit_ISD_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3913
0
  if (RetVT.SimpleTy != MVT::v4f16)
3914
0
    return 0;
3915
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3916
0
    return fastEmitInst_rr(ARM::VMINNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3917
0
  }
3918
0
  return 0;
3919
0
}
3920
3921
0
unsigned fastEmit_ISD_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3922
0
  if (RetVT.SimpleTy != MVT::v8f16)
3923
0
    return 0;
3924
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3925
0
    return fastEmitInst_rr(ARM::VMINNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3926
0
  }
3927
0
  return 0;
3928
0
}
3929
3930
0
unsigned fastEmit_ISD_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3931
0
  if (RetVT.SimpleTy != MVT::v2f32)
3932
0
    return 0;
3933
0
  if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3934
0
    return fastEmitInst_rr(ARM::VMINNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3935
0
  }
3936
0
  return 0;
3937
0
}
3938
3939
0
unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3940
0
  if (RetVT.SimpleTy != MVT::v4f32)
3941
0
    return 0;
3942
0
  if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3943
0
    return fastEmitInst_rr(ARM::VMINNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3944
0
  }
3945
0
  return 0;
3946
0
}
3947
3948
unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3949
  switch (VT.SimpleTy) {
3950
  case MVT::f16: return fastEmit_ISD_FMINNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3951
  case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3952
  case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3953
  case MVT::v4f16: return fastEmit_ISD_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3954
  case MVT::v8f16: return fastEmit_ISD_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3955
  case MVT::v2f32: return fastEmit_ISD_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3956
  case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3957
  default: return 0;
3958
  }
3959
}
3960
3961
// FastEmit functions for ISD::FMUL.
3962
3963
0
unsigned fastEmit_ISD_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3964
0
  if (RetVT.SimpleTy != MVT::f16)
3965
0
    return 0;
3966
0
  if ((Subtarget->hasFullFP16())) {
3967
0
    return fastEmitInst_rr(ARM::VMULH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3968
0
  }
3969
0
  return 0;
3970
0
}
3971
3972
1
unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3973
1
  if (RetVT.SimpleTy != MVT::f32)
3974
0
    return 0;
3975
1
  if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
3976
1
    return fastEmitInst_rr(ARM::VMULS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3977
1
  }
3978
0
  return 0;
3979
0
}
3980
3981
0
unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3982
0
  if (RetVT.SimpleTy != MVT::f64)
3983
0
    return 0;
3984
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
3985
0
    return fastEmitInst_rr(ARM::VMULD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3986
0
  }
3987
0
  return 0;
3988
0
}
3989
3990
0
unsigned fastEmit_ISD_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3991
0
  if (RetVT.SimpleTy != MVT::v4f16)
3992
0
    return 0;
3993
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3994
0
    return fastEmitInst_rr(ARM::VMULhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3995
0
  }
3996
0
  return 0;
3997
0
}
3998
3999
0
unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4000
0
  if (RetVT.SimpleTy != MVT::v8f16)
4001
0
    return 0;
4002
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
4003
0
    return fastEmitInst_rr(ARM::VMULhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4004
0
  }
4005
0
  return 0;
4006
0
}
4007
4008
0
unsigned fastEmit_ISD_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4009
0
  if (RetVT.SimpleTy != MVT::v2f32)
4010
0
    return 0;
4011
0
  if ((Subtarget->hasNEON())) {
4012
0
    return fastEmitInst_rr(ARM::VMULfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4013
0
  }
4014
0
  return 0;
4015
0
}
4016
4017
0
unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4018
0
  if (RetVT.SimpleTy != MVT::v4f32)
4019
0
    return 0;
4020
0
  if ((Subtarget->hasNEON())) {
4021
0
    return fastEmitInst_rr(ARM::VMULfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4022
0
  }
4023
0
  return 0;
4024
0
}
4025
4026
1
unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4027
1
  switch (VT.SimpleTy) {
4028
1
  
case MVT::f16: return fastEmit_ISD_FMUL_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4029
1
  case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4030
1
  
case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4031
1
  
case MVT::v4f16: return fastEmit_ISD_FMUL_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4032
1
  
case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4033
1
  
case MVT::v2f32: return fastEmit_ISD_FMUL_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4034
1
  
case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4035
1
  
default: return 00
;
4036
1
  }
4037
1
}
4038
4039
// FastEmit functions for ISD::FSUB.
4040
4041
0
unsigned fastEmit_ISD_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4042
0
  if (RetVT.SimpleTy != MVT::f16)
4043
0
    return 0;
4044
0
  if ((Subtarget->hasFullFP16())) {
4045
0
    return fastEmitInst_rr(ARM::VSUBH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4046
0
  }
4047
0
  return 0;
4048
0
}
4049
4050
0
unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4051
0
  if (RetVT.SimpleTy != MVT::f32)
4052
0
    return 0;
4053
0
  if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
4054
0
    return fastEmitInst_rr(ARM::VSUBS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4055
0
  }
4056
0
  return 0;
4057
0
}
4058
4059
0
unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4060
0
  if (RetVT.SimpleTy != MVT::f64)
4061
0
    return 0;
4062
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
4063
0
    return fastEmitInst_rr(ARM::VSUBD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4064
0
  }
4065
0
  return 0;
4066
0
}
4067
4068
0
unsigned fastEmit_ISD_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4069
0
  if (RetVT.SimpleTy != MVT::v4f16)
4070
0
    return 0;
4071
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
4072
0
    return fastEmitInst_rr(ARM::VSUBhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4073
0
  }
4074
0
  return 0;
4075
0
}
4076
4077
0
unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4078
0
  if (RetVT.SimpleTy != MVT::v8f16)
4079
0
    return 0;
4080
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
4081
0
    return fastEmitInst_rr(ARM::VSUBhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4082
0
  }
4083
0
  return 0;
4084
0
}
4085
4086
0
unsigned fastEmit_ISD_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4087
0
  if (RetVT.SimpleTy != MVT::v2f32)
4088
0
    return 0;
4089
0
  if ((Subtarget->hasNEON())) {
4090
0
    return fastEmitInst_rr(ARM::VSUBfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4091
0
  }
4092
0
  return 0;
4093
0
}
4094
4095
0
unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4096
0
  if (RetVT.SimpleTy != MVT::v4f32)
4097
0
    return 0;
4098
0
  if ((Subtarget->hasNEON())) {
4099
0
    return fastEmitInst_rr(ARM::VSUBfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4100
0
  }
4101
0
  return 0;
4102
0
}
4103
4104
unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4105
  switch (VT.SimpleTy) {
4106
  case MVT::f16: return fastEmit_ISD_FSUB_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4107
  case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4108
  case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4109
  case MVT::v4f16: return fastEmit_ISD_FSUB_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4110
  case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4111
  case MVT::v2f32: return fastEmit_ISD_FSUB_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4112
  case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4113
  default: return 0;
4114
  }
4115
}
4116
4117
// FastEmit functions for ISD::MUL.
4118
4119
3
unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4120
3
  if (RetVT.SimpleTy != MVT::i32)
4121
0
    return 0;
4122
3
  if ((Subtarget->isThumb2())) {
4123
3
    return fastEmitInst_rr(ARM::t2MUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4124
3
  }
4125
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4126
0
    return fastEmitInst_rr(ARM::tMUL, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4127
0
  }
4128
0
  if ((!Subtarget->isThumb()) && (!Subtarget->hasV6Ops()) && (Subtarget->useMulOps())) {
4129
0
    return fastEmitInst_rr(ARM::MULv5, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4130
0
  }
4131
0
  if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
4132
0
    return fastEmitInst_rr(ARM::MUL, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4133
0
  }
4134
0
  return 0;
4135
0
}
4136
4137
0
unsigned fastEmit_ISD_MUL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4138
0
  if (RetVT.SimpleTy != MVT::v8i8)
4139
0
    return 0;
4140
0
  if ((Subtarget->hasNEON())) {
4141
0
    return fastEmitInst_rr(ARM::VMULv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4142
0
  }
4143
0
  return 0;
4144
0
}
4145
4146
0
unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4147
0
  if (RetVT.SimpleTy != MVT::v16i8)
4148
0
    return 0;
4149
0
  if ((Subtarget->hasNEON())) {
4150
0
    return fastEmitInst_rr(ARM::VMULv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4151
0
  }
4152
0
  return 0;
4153
0
}
4154
4155
0
unsigned fastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4156
0
  if (RetVT.SimpleTy != MVT::v4i16)
4157
0
    return 0;
4158
0
  if ((Subtarget->hasNEON())) {
4159
0
    return fastEmitInst_rr(ARM::VMULv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4160
0
  }
4161
0
  return 0;
4162
0
}
4163
4164
0
unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4165
0
  if (RetVT.SimpleTy != MVT::v8i16)
4166
0
    return 0;
4167
0
  if ((Subtarget->hasNEON())) {
4168
0
    return fastEmitInst_rr(ARM::VMULv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4169
0
  }
4170
0
  return 0;
4171
0
}
4172
4173
0
unsigned fastEmit_ISD_MUL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4174
0
  if (RetVT.SimpleTy != MVT::v2i32)
4175
0
    return 0;
4176
0
  if ((Subtarget->hasNEON())) {
4177
0
    return fastEmitInst_rr(ARM::VMULv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4178
0
  }
4179
0
  return 0;
4180
0
}
4181
4182
0
unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4183
0
  if (RetVT.SimpleTy != MVT::v4i32)
4184
0
    return 0;
4185
0
  if ((Subtarget->hasNEON())) {
4186
0
    return fastEmitInst_rr(ARM::VMULv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4187
0
  }
4188
0
  return 0;
4189
0
}
4190
4191
3
unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4192
3
  switch (VT.SimpleTy) {
4193
3
  case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4194
3
  
case MVT::v8i8: return fastEmit_ISD_MUL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4195
3
  
case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4196
3
  
case MVT::v4i16: return fastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4197
3
  
case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4198
3
  
case MVT::v2i32: return fastEmit_ISD_MUL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4199
3
  
case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4200
3
  
default: return 00
;
4201
3
  }
4202
3
}
4203
4204
// FastEmit functions for ISD::MULHS.
4205
4206
0
unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4207
0
  if (RetVT.SimpleTy != MVT::i32)
4208
0
    return 0;
4209
0
  if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
4210
0
    return fastEmitInst_rr(ARM::t2SMMUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4211
0
  }
4212
0
  if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
4213
0
    return fastEmitInst_rr(ARM::SMMUL, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4214
0
  }
4215
0
  return 0;
4216
0
}
4217
4218
unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4219
  switch (VT.SimpleTy) {
4220
  case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4221
  default: return 0;
4222
  }
4223
}
4224
4225
// FastEmit functions for ISD::OR.
4226
4227
3
unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4228
3
  if (RetVT.SimpleTy != MVT::i32)
4229
0
    return 0;
4230
3
  if ((Subtarget->isThumb2())) {
4231
1
    return fastEmitInst_rr(ARM::t2ORRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4232
1
  }
4233
2
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
4234
0
    return fastEmitInst_rr(ARM::tORR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4235
0
  }
4236
2
  if ((!Subtarget->isThumb())) {
4237
2
    return fastEmitInst_rr(ARM::ORRrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4238
2
  }
4239
0
  return 0;
4240
0
}
4241
4242
0
unsigned fastEmit_ISD_OR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4243
0
  if (RetVT.SimpleTy != MVT::v2i32)
4244
0
    return 0;
4245
0
  if ((Subtarget->hasNEON())) {
4246
0
    return fastEmitInst_rr(ARM::VORRd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4247
0
  }
4248
0
  return 0;
4249
0
}
4250
4251
0
unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4252
0
  if (RetVT.SimpleTy != MVT::v4i32)
4253
0
    return 0;
4254
0
  if ((Subtarget->hasNEON())) {
4255
0
    return fastEmitInst_rr(ARM::VORRq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4256
0
  }
4257
0
  return 0;
4258
0
}
4259
4260
3
unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4261
3
  switch (VT.SimpleTy) {
4262
3
  case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4263
3
  
case MVT::v2i32: return fastEmit_ISD_OR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4264
3
  
case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4265
3
  
default: return 00
;
4266
3
  }
4267
3
}
4268
4269
// FastEmit functions for ISD::ROTR.
4270
4271
0
unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4272
0
  if (RetVT.SimpleTy != MVT::i32)
4273
0
    return 0;
4274
0
  if ((Subtarget->isThumb2())) {
4275
0
    return fastEmitInst_rr(ARM::t2RORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4276
0
  }
4277
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4278
0
    return fastEmitInst_rr(ARM::tROR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4279
0
  }
4280
0
  return 0;
4281
0
}
4282
4283
unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4284
  switch (VT.SimpleTy) {
4285
  case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4286
  default: return 0;
4287
  }
4288
}
4289
4290
// FastEmit functions for ISD::SDIV.
4291
4292
4
unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4293
4
  if (RetVT.SimpleTy != MVT::i32)
4294
0
    return 0;
4295
4
  if ((Subtarget->hasDivideInThumbMode()) && 
(Subtarget->hasV8MBaselineOps())0
&&
(Subtarget->isThumb())0
) {
4296
0
    return fastEmitInst_rr(ARM::t2SDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4297
0
  }
4298
4
  if ((Subtarget->hasDivideInARMMode()) && 
(!Subtarget->isThumb())0
) {
4299
0
    return fastEmitInst_rr(ARM::SDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4300
0
  }
4301
4
  return 0;
4302
4
}
4303
4304
4
unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4305
4
  switch (VT.SimpleTy) {
4306
4
  case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4307
4
  
default: return 00
;
4308
4
  }
4309
4
}
4310
4311
// FastEmit functions for ISD::SHL.
4312
4313
6
unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4314
6
  if (RetVT.SimpleTy != MVT::i32)
4315
0
    return 0;
4316
6
  if ((Subtarget->isThumb2())) {
4317
0
    return fastEmitInst_rr(ARM::t2LSLrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4318
0
  }
4319
6
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
4320
0
    return fastEmitInst_rr(ARM::tLSLrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4321
0
  }
4322
6
  return 0;
4323
6
}
4324
4325
6
unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4326
6
  switch (VT.SimpleTy) {
4327
6
  case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4328
6
  
default: return 00
;
4329
6
  }
4330
6
}
4331
4332
// FastEmit functions for ISD::SMAX.
4333
4334
0
unsigned fastEmit_ISD_SMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4335
0
  if (RetVT.SimpleTy != MVT::v8i8)
4336
0
    return 0;
4337
0
  if ((Subtarget->hasNEON())) {
4338
0
    return fastEmitInst_rr(ARM::VMAXsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4339
0
  }
4340
0
  return 0;
4341
0
}
4342
4343
0
unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4344
0
  if (RetVT.SimpleTy != MVT::v16i8)
4345
0
    return 0;
4346
0
  if ((Subtarget->hasNEON())) {
4347
0
    return fastEmitInst_rr(ARM::VMAXsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4348
0
  }
4349
0
  return 0;
4350
0
}
4351
4352
0
unsigned fastEmit_ISD_SMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4353
0
  if (RetVT.SimpleTy != MVT::v4i16)
4354
0
    return 0;
4355
0
  if ((Subtarget->hasNEON())) {
4356
0
    return fastEmitInst_rr(ARM::VMAXsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4357
0
  }
4358
0
  return 0;
4359
0
}
4360
4361
0
unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4362
0
  if (RetVT.SimpleTy != MVT::v8i16)
4363
0
    return 0;
4364
0
  if ((Subtarget->hasNEON())) {
4365
0
    return fastEmitInst_rr(ARM::VMAXsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4366
0
  }
4367
0
  return 0;
4368
0
}
4369
4370
0
unsigned fastEmit_ISD_SMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4371
0
  if (RetVT.SimpleTy != MVT::v2i32)
4372
0
    return 0;
4373
0
  if ((Subtarget->hasNEON())) {
4374
0
    return fastEmitInst_rr(ARM::VMAXsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4375
0
  }
4376
0
  return 0;
4377
0
}
4378
4379
0
unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4380
0
  if (RetVT.SimpleTy != MVT::v4i32)
4381
0
    return 0;
4382
0
  if ((Subtarget->hasNEON())) {
4383
0
    return fastEmitInst_rr(ARM::VMAXsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4384
0
  }
4385
0
  return 0;
4386
0
}
4387
4388
unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4389
  switch (VT.SimpleTy) {
4390
  case MVT::v8i8: return fastEmit_ISD_SMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4391
  case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4392
  case MVT::v4i16: return fastEmit_ISD_SMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4393
  case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4394
  case MVT::v2i32: return fastEmit_ISD_SMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4395
  case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4396
  default: return 0;
4397
  }
4398
}
4399
4400
// FastEmit functions for ISD::SMIN.
4401
4402
0
unsigned fastEmit_ISD_SMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4403
0
  if (RetVT.SimpleTy != MVT::v8i8)
4404
0
    return 0;
4405
0
  if ((Subtarget->hasNEON())) {
4406
0
    return fastEmitInst_rr(ARM::VMINsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4407
0
  }
4408
0
  return 0;
4409
0
}
4410
4411
0
unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4412
0
  if (RetVT.SimpleTy != MVT::v16i8)
4413
0
    return 0;
4414
0
  if ((Subtarget->hasNEON())) {
4415
0
    return fastEmitInst_rr(ARM::VMINsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4416
0
  }
4417
0
  return 0;
4418
0
}
4419
4420
0
unsigned fastEmit_ISD_SMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4421
0
  if (RetVT.SimpleTy != MVT::v4i16)
4422
0
    return 0;
4423
0
  if ((Subtarget->hasNEON())) {
4424
0
    return fastEmitInst_rr(ARM::VMINsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4425
0
  }
4426
0
  return 0;
4427
0
}
4428
4429
0
unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4430
0
  if (RetVT.SimpleTy != MVT::v8i16)
4431
0
    return 0;
4432
0
  if ((Subtarget->hasNEON())) {
4433
0
    return fastEmitInst_rr(ARM::VMINsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4434
0
  }
4435
0
  return 0;
4436
0
}
4437
4438
0
unsigned fastEmit_ISD_SMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4439
0
  if (RetVT.SimpleTy != MVT::v2i32)
4440
0
    return 0;
4441
0
  if ((Subtarget->hasNEON())) {
4442
0
    return fastEmitInst_rr(ARM::VMINsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4443
0
  }
4444
0
  return 0;
4445
0
}
4446
4447
0
unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4448
0
  if (RetVT.SimpleTy != MVT::v4i32)
4449
0
    return 0;
4450
0
  if ((Subtarget->hasNEON())) {
4451
0
    return fastEmitInst_rr(ARM::VMINsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4452
0
  }
4453
0
  return 0;
4454
0
}
4455
4456
unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4457
  switch (VT.SimpleTy) {
4458
  case MVT::v8i8: return fastEmit_ISD_SMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4459
  case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4460
  case MVT::v4i16: return fastEmit_ISD_SMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4461
  case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4462
  case MVT::v2i32: return fastEmit_ISD_SMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4463
  case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4464
  default: return 0;
4465
  }
4466
}
4467
4468
// FastEmit functions for ISD::SRA.
4469
4470
4
unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4471
4
  if (RetVT.SimpleTy != MVT::i32)
4472
0
    return 0;
4473
4
  if ((Subtarget->isThumb2())) {
4474
0
    return fastEmitInst_rr(ARM::t2ASRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4475
0
  }
4476
4
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
4477
0
    return fastEmitInst_rr(ARM::tASRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4478
0
  }
4479
4
  return 0;
4480
4
}
4481
4482
4
unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4483
4
  switch (VT.SimpleTy) {
4484
4
  case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4485
4
  
default: return 00
;
4486
4
  }
4487
4
}
4488
4489
// FastEmit functions for ISD::SRL.
4490
4491
6
unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4492
6
  if (RetVT.SimpleTy != MVT::i32)
4493
0
    return 0;
4494
6
  if ((Subtarget->isThumb2())) {
4495
2
    return fastEmitInst_rr(ARM::t2LSRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4496
2
  }
4497
4
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
4498
0
    return fastEmitInst_rr(ARM::tLSRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4499
0
  }
4500
4
  return 0;
4501
4
}
4502
4503
6
unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4504
6
  switch (VT.SimpleTy) {
4505
6
  case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4506
6
  
default: return 00
;
4507
6
  }
4508
6
}
4509
4510
// FastEmit functions for ISD::SUB.
4511
4512
3
unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4513
3
  if (RetVT.SimpleTy != MVT::i32)
4514
0
    return 0;
4515
3
  if ((Subtarget->isThumb2())) {
4516
1
    return fastEmitInst_rr(ARM::t2SUBrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4517
1
  }
4518
2
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
4519
0
    return fastEmitInst_rr(ARM::tSUBrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4520
0
  }
4521
2
  if ((!Subtarget->isThumb())) {
4522
2
    return fastEmitInst_rr(ARM::SUBrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4523
2
  }
4524
0
  return 0;
4525
0
}
4526
4527
0
unsigned fastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4528
0
  if (RetVT.SimpleTy != MVT::v8i8)
4529
0
    return 0;
4530
0
  if ((Subtarget->hasNEON())) {
4531
0
    return fastEmitInst_rr(ARM::VSUBv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4532
0
  }
4533
0
  return 0;
4534
0
}
4535
4536
0
unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4537
0
  if (RetVT.SimpleTy != MVT::v16i8)
4538
0
    return 0;
4539
0
  if ((Subtarget->hasNEON())) {
4540
0
    return fastEmitInst_rr(ARM::VSUBv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4541
0
  }
4542
0
  return 0;
4543
0
}
4544
4545