Coverage Report

Created: 2018-07-20 23:04

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenFastISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* "Fast" Instruction Selector for the ARM target                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
// FastEmit Immediate Predicate functions.
11
504
static bool Predicate_mod_imm(int64_t Imm) {
12
504
13
504
    return ARM_AM::getSOImmVal(Imm) != -1;
14
504
  
15
504
}
16
0
static bool Predicate_imm0_65535(int64_t Imm) {
17
0
18
0
  return Imm >= 0 && Imm < 65536;
19
0
20
0
}
21
462
static bool Predicate_imm0_7(int64_t Imm) {
22
462
23
462
  return Imm >= 0 && 
Imm < 8449
;
24
462
25
462
}
26
462
static bool Predicate_imm8_255(int64_t Imm) {
27
462
28
462
  return Imm >= 8 && 
Imm < 256422
;
29
462
30
462
}
31
462
static bool Predicate_imm0_255(int64_t Imm) {
32
462
 return Imm >= 0 && 
Imm < 256449
;
33
462
}
34
462
static bool Predicate_t2_so_imm(int64_t Imm) {
35
462
36
462
    return ARM_AM::getT2SOImmVal(Imm) != -1;
37
462
  
38
462
}
39
234
static bool Predicate_imm0_4095(int64_t Imm) {
40
234
41
234
  return Imm >= 0 && 
Imm < 4096222
;
42
234
43
234
}
44
45
static bool Predicate_imm1_31(int64_t Imm) {
45
45
 return Imm > 0 && 
Imm < 3233
;
46
45
}
47
39
static bool Predicate_imm0_31(int64_t Imm) {
48
39
49
39
  return Imm >= 0 && 
Imm < 3227
;
50
39
51
39
}
52
39
static bool Predicate_shr_imm8(int64_t Imm) {
53
39
 return Imm > 0 && 
Imm <= 827
;
54
39
}
55
39
static bool Predicate_shr_imm16(int64_t Imm) {
56
39
 return Imm > 0 && 
Imm <= 1627
;
57
39
}
58
39
static bool Predicate_shr_imm32(int64_t Imm) {
59
39
 return Imm > 0 && 
Imm <= 3227
;
60
39
}
61
39
static bool Predicate_VectorIndex32(int64_t Imm) {
62
39
63
39
  return ((uint64_t)Imm) < 2;
64
39
65
39
}
66
0
static bool Predicate_t2_so_imm_neg(int64_t Imm) {
67
0
68
0
  return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
69
0
70
0
}
71
72
73
// FastEmit functions for ARMISD::CALL.
74
75
0
unsigned fastEmit_ARMISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
76
0
  if (RetVT.SimpleTy != MVT::isVoid)
77
0
    return 0;
78
0
  if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
79
0
    return fastEmitInst_r(ARM::BLX, &ARM::GPRRegClass, Op0, Op0IsKill);
80
0
  }
81
0
  return 0;
82
0
}
83
84
unsigned fastEmit_ARMISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
85
  switch (VT.SimpleTy) {
86
  case MVT::i32: return fastEmit_ARMISD_CALL_MVT_i32_r(RetVT, Op0, Op0IsKill);
87
  default: return 0;
88
  }
89
}
90
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// FastEmit functions for ARMISD::CALL_NOLINK.
92
93
0
unsigned fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
94
0
  if (RetVT.SimpleTy != MVT::isVoid)
95
0
    return 0;
96
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
97
0
    return fastEmitInst_r(ARM::tBX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
98
0
  }
99
0
  if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
100
0
    return fastEmitInst_r(ARM::BMOVPCRX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
101
0
  }
102
0
  if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
103
0
    return fastEmitInst_r(ARM::BX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
104
0
  }
105
0
  return 0;
106
0
}
107
108
unsigned fastEmit_ARMISD_CALL_NOLINK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
109
  switch (VT.SimpleTy) {
110
  case MVT::i32: return fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(RetVT, Op0, Op0IsKill);
111
  default: return 0;
112
  }
113
}
114
115
// FastEmit functions for ARMISD::CALL_PRED.
116
117
0
unsigned fastEmit_ARMISD_CALL_PRED_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
118
0
  if (RetVT.SimpleTy != MVT::isVoid)
119
0
    return 0;
120
0
  if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
121
0
    return fastEmitInst_r(ARM::BLX_pred, &ARM::GPRRegClass, Op0, Op0IsKill);
122
0
  }
123
0
  return 0;
124
0
}
125
126
unsigned fastEmit_ARMISD_CALL_PRED_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
127
  switch (VT.SimpleTy) {
128
  case MVT::i32: return fastEmit_ARMISD_CALL_PRED_MVT_i32_r(RetVT, Op0, Op0IsKill);
129
  default: return 0;
130
  }
131
}
132
133
// FastEmit functions for ARMISD::RRX.
134
135
0
unsigned fastEmit_ARMISD_RRX_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
136
0
  if (RetVT.SimpleTy != MVT::i32)
137
0
    return 0;
138
0
  if ((Subtarget->isThumb2())) {
139
0
    return fastEmitInst_r(ARM::t2RRX, &ARM::rGPRRegClass, Op0, Op0IsKill);
140
0
  }
141
0
  if ((!Subtarget->isThumb())) {
142
0
    return fastEmitInst_r(ARM::RRX, &ARM::GPRRegClass, Op0, Op0IsKill);
143
0
  }
144
0
  return 0;
145
0
}
146
147
unsigned fastEmit_ARMISD_RRX_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
148
  switch (VT.SimpleTy) {
149
  case MVT::i32: return fastEmit_ARMISD_RRX_MVT_i32_r(RetVT, Op0, Op0IsKill);
150
  default: return 0;
151
  }
152
}
153
154
// FastEmit functions for ARMISD::SRA_FLAG.
155
156
0
unsigned fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
157
0
  if (RetVT.SimpleTy != MVT::i32)
158
0
    return 0;
159
0
  if ((Subtarget->isThumb2())) {
160
0
    return fastEmitInst_r(ARM::t2MOVsra_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
161
0
  }
162
0
  if ((!Subtarget->isThumb())) {
163
0
    return fastEmitInst_r(ARM::MOVsra_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
164
0
  }
165
0
  return 0;
166
0
}
167
168
unsigned fastEmit_ARMISD_SRA_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
169
  switch (VT.SimpleTy) {
170
  case MVT::i32: return fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
171
  default: return 0;
172
  }
173
}
174
175
// FastEmit functions for ARMISD::SRL_FLAG.
176
177
0
unsigned fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
178
0
  if (RetVT.SimpleTy != MVT::i32)
179
0
    return 0;
180
0
  if ((Subtarget->isThumb2())) {
181
0
    return fastEmitInst_r(ARM::t2MOVsrl_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
182
0
  }
183
0
  if ((!Subtarget->isThumb())) {
184
0
    return fastEmitInst_r(ARM::MOVsrl_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
185
0
  }
186
0
  return 0;
187
0
}
188
189
unsigned fastEmit_ARMISD_SRL_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
190
  switch (VT.SimpleTy) {
191
  case MVT::i32: return fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
192
  default: return 0;
193
  }
194
}
195
196
// FastEmit functions for ARMISD::TC_RETURN.
197
198
0
unsigned fastEmit_ARMISD_TC_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
199
0
  if (RetVT.SimpleTy != MVT::isVoid)
200
0
    return 0;
201
0
  return fastEmitInst_r(ARM::TCRETURNri, &ARM::tcGPRRegClass, Op0, Op0IsKill);
202
0
}
203
204
unsigned fastEmit_ARMISD_TC_RETURN_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
205
  switch (VT.SimpleTy) {
206
  case MVT::i32: return fastEmit_ARMISD_TC_RETURN_MVT_i32_r(RetVT, Op0, Op0IsKill);
207
  default: return 0;
208
  }
209
}
210
211
// FastEmit functions for ARMISD::VCEQZ.
212
213
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
214
0
  if (RetVT.SimpleTy != MVT::v8i8)
215
0
    return 0;
216
0
  if ((Subtarget->hasNEON())) {
217
0
    return fastEmitInst_r(ARM::VCEQzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
218
0
  }
219
0
  return 0;
220
0
}
221
222
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
223
0
  if (RetVT.SimpleTy != MVT::v16i8)
224
0
    return 0;
225
0
  if ((Subtarget->hasNEON())) {
226
0
    return fastEmitInst_r(ARM::VCEQzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
227
0
  }
228
0
  return 0;
229
0
}
230
231
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
232
0
  if (RetVT.SimpleTy != MVT::v4i16)
233
0
    return 0;
234
0
  if ((Subtarget->hasNEON())) {
235
0
    return fastEmitInst_r(ARM::VCEQzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
236
0
  }
237
0
  return 0;
238
0
}
239
240
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
241
0
  if (RetVT.SimpleTy != MVT::v8i16)
242
0
    return 0;
243
0
  if ((Subtarget->hasNEON())) {
244
0
    return fastEmitInst_r(ARM::VCEQzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
245
0
  }
246
0
  return 0;
247
0
}
248
249
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
250
0
  if (RetVT.SimpleTy != MVT::v2i32)
251
0
    return 0;
252
0
  if ((Subtarget->hasNEON())) {
253
0
    return fastEmitInst_r(ARM::VCEQzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
254
0
  }
255
0
  return 0;
256
0
}
257
258
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
259
0
  if (RetVT.SimpleTy != MVT::v4i32)
260
0
    return 0;
261
0
  if ((Subtarget->hasNEON())) {
262
0
    return fastEmitInst_r(ARM::VCEQzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
263
0
  }
264
0
  return 0;
265
0
}
266
267
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
268
0
  if (RetVT.SimpleTy != MVT::v4i16)
269
0
    return 0;
270
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
271
0
    return fastEmitInst_r(ARM::VCEQzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
272
0
  }
273
0
  return 0;
274
0
}
275
276
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
277
0
  if (RetVT.SimpleTy != MVT::v8i16)
278
0
    return 0;
279
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
280
0
    return fastEmitInst_r(ARM::VCEQzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
281
0
  }
282
0
  return 0;
283
0
}
284
285
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
286
0
  if (RetVT.SimpleTy != MVT::v2i32)
287
0
    return 0;
288
0
  if ((Subtarget->hasNEON())) {
289
0
    return fastEmitInst_r(ARM::VCEQzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
290
0
  }
291
0
  return 0;
292
0
}
293
294
0
unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
295
0
  if (RetVT.SimpleTy != MVT::v4i32)
296
0
    return 0;
297
0
  if ((Subtarget->hasNEON())) {
298
0
    return fastEmitInst_r(ARM::VCEQzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
299
0
  }
300
0
  return 0;
301
0
}
302
303
unsigned fastEmit_ARMISD_VCEQZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
304
  switch (VT.SimpleTy) {
305
  case MVT::v8i8: return fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
306
  case MVT::v16i8: return fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
307
  case MVT::v4i16: return fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
308
  case MVT::v8i16: return fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
309
  case MVT::v2i32: return fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
310
  case MVT::v4i32: return fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
311
  case MVT::v4f16: return fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
312
  case MVT::v8f16: return fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
313
  case MVT::v2f32: return fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
314
  case MVT::v4f32: return fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
315
  default: return 0;
316
  }
317
}
318
319
// FastEmit functions for ARMISD::VCGEZ.
320
321
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
322
0
  if (RetVT.SimpleTy != MVT::v8i8)
323
0
    return 0;
324
0
  if ((Subtarget->hasNEON())) {
325
0
    return fastEmitInst_r(ARM::VCGEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
326
0
  }
327
0
  return 0;
328
0
}
329
330
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
331
0
  if (RetVT.SimpleTy != MVT::v16i8)
332
0
    return 0;
333
0
  if ((Subtarget->hasNEON())) {
334
0
    return fastEmitInst_r(ARM::VCGEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
335
0
  }
336
0
  return 0;
337
0
}
338
339
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
340
0
  if (RetVT.SimpleTy != MVT::v4i16)
341
0
    return 0;
342
0
  if ((Subtarget->hasNEON())) {
343
0
    return fastEmitInst_r(ARM::VCGEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
344
0
  }
345
0
  return 0;
346
0
}
347
348
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
349
0
  if (RetVT.SimpleTy != MVT::v8i16)
350
0
    return 0;
351
0
  if ((Subtarget->hasNEON())) {
352
0
    return fastEmitInst_r(ARM::VCGEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
353
0
  }
354
0
  return 0;
355
0
}
356
357
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
358
0
  if (RetVT.SimpleTy != MVT::v2i32)
359
0
    return 0;
360
0
  if ((Subtarget->hasNEON())) {
361
0
    return fastEmitInst_r(ARM::VCGEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
362
0
  }
363
0
  return 0;
364
0
}
365
366
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
367
0
  if (RetVT.SimpleTy != MVT::v4i32)
368
0
    return 0;
369
0
  if ((Subtarget->hasNEON())) {
370
0
    return fastEmitInst_r(ARM::VCGEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
371
0
  }
372
0
  return 0;
373
0
}
374
375
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
376
0
  if (RetVT.SimpleTy != MVT::v4i16)
377
0
    return 0;
378
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
379
0
    return fastEmitInst_r(ARM::VCGEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
380
0
  }
381
0
  return 0;
382
0
}
383
384
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
385
0
  if (RetVT.SimpleTy != MVT::v8i16)
386
0
    return 0;
387
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
388
0
    return fastEmitInst_r(ARM::VCGEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
389
0
  }
390
0
  return 0;
391
0
}
392
393
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
394
0
  if (RetVT.SimpleTy != MVT::v2i32)
395
0
    return 0;
396
0
  if ((Subtarget->hasNEON())) {
397
0
    return fastEmitInst_r(ARM::VCGEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
398
0
  }
399
0
  return 0;
400
0
}
401
402
0
unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
403
0
  if (RetVT.SimpleTy != MVT::v4i32)
404
0
    return 0;
405
0
  if ((Subtarget->hasNEON())) {
406
0
    return fastEmitInst_r(ARM::VCGEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
407
0
  }
408
0
  return 0;
409
0
}
410
411
unsigned fastEmit_ARMISD_VCGEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
412
  switch (VT.SimpleTy) {
413
  case MVT::v8i8: return fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
414
  case MVT::v16i8: return fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
415
  case MVT::v4i16: return fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
416
  case MVT::v8i16: return fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
417
  case MVT::v2i32: return fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
418
  case MVT::v4i32: return fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
419
  case MVT::v4f16: return fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
420
  case MVT::v8f16: return fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
421
  case MVT::v2f32: return fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
422
  case MVT::v4f32: return fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
423
  default: return 0;
424
  }
425
}
426
427
// FastEmit functions for ARMISD::VCGTZ.
428
429
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
430
0
  if (RetVT.SimpleTy != MVT::v8i8)
431
0
    return 0;
432
0
  if ((Subtarget->hasNEON())) {
433
0
    return fastEmitInst_r(ARM::VCGTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
434
0
  }
435
0
  return 0;
436
0
}
437
438
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
439
0
  if (RetVT.SimpleTy != MVT::v16i8)
440
0
    return 0;
441
0
  if ((Subtarget->hasNEON())) {
442
0
    return fastEmitInst_r(ARM::VCGTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
443
0
  }
444
0
  return 0;
445
0
}
446
447
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
448
0
  if (RetVT.SimpleTy != MVT::v4i16)
449
0
    return 0;
450
0
  if ((Subtarget->hasNEON())) {
451
0
    return fastEmitInst_r(ARM::VCGTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
452
0
  }
453
0
  return 0;
454
0
}
455
456
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
457
0
  if (RetVT.SimpleTy != MVT::v8i16)
458
0
    return 0;
459
0
  if ((Subtarget->hasNEON())) {
460
0
    return fastEmitInst_r(ARM::VCGTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
461
0
  }
462
0
  return 0;
463
0
}
464
465
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
466
0
  if (RetVT.SimpleTy != MVT::v2i32)
467
0
    return 0;
468
0
  if ((Subtarget->hasNEON())) {
469
0
    return fastEmitInst_r(ARM::VCGTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
470
0
  }
471
0
  return 0;
472
0
}
473
474
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
475
0
  if (RetVT.SimpleTy != MVT::v4i32)
476
0
    return 0;
477
0
  if ((Subtarget->hasNEON())) {
478
0
    return fastEmitInst_r(ARM::VCGTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
479
0
  }
480
0
  return 0;
481
0
}
482
483
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
484
0
  if (RetVT.SimpleTy != MVT::v4i16)
485
0
    return 0;
486
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
487
0
    return fastEmitInst_r(ARM::VCGTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
488
0
  }
489
0
  return 0;
490
0
}
491
492
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
493
0
  if (RetVT.SimpleTy != MVT::v8i16)
494
0
    return 0;
495
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
496
0
    return fastEmitInst_r(ARM::VCGTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
497
0
  }
498
0
  return 0;
499
0
}
500
501
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
502
0
  if (RetVT.SimpleTy != MVT::v2i32)
503
0
    return 0;
504
0
  if ((Subtarget->hasNEON())) {
505
0
    return fastEmitInst_r(ARM::VCGTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
506
0
  }
507
0
  return 0;
508
0
}
509
510
0
unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
511
0
  if (RetVT.SimpleTy != MVT::v4i32)
512
0
    return 0;
513
0
  if ((Subtarget->hasNEON())) {
514
0
    return fastEmitInst_r(ARM::VCGTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
515
0
  }
516
0
  return 0;
517
0
}
518
519
unsigned fastEmit_ARMISD_VCGTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
520
  switch (VT.SimpleTy) {
521
  case MVT::v8i8: return fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
522
  case MVT::v16i8: return fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
523
  case MVT::v4i16: return fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
524
  case MVT::v8i16: return fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
525
  case MVT::v2i32: return fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
526
  case MVT::v4i32: return fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
527
  case MVT::v4f16: return fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
528
  case MVT::v8f16: return fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
529
  case MVT::v2f32: return fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
530
  case MVT::v4f32: return fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
531
  default: return 0;
532
  }
533
}
534
535
// FastEmit functions for ARMISD::VCLEZ.
536
537
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
538
0
  if (RetVT.SimpleTy != MVT::v8i8)
539
0
    return 0;
540
0
  if ((Subtarget->hasNEON())) {
541
0
    return fastEmitInst_r(ARM::VCLEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
542
0
  }
543
0
  return 0;
544
0
}
545
546
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
547
0
  if (RetVT.SimpleTy != MVT::v16i8)
548
0
    return 0;
549
0
  if ((Subtarget->hasNEON())) {
550
0
    return fastEmitInst_r(ARM::VCLEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
551
0
  }
552
0
  return 0;
553
0
}
554
555
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
556
0
  if (RetVT.SimpleTy != MVT::v4i16)
557
0
    return 0;
558
0
  if ((Subtarget->hasNEON())) {
559
0
    return fastEmitInst_r(ARM::VCLEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
560
0
  }
561
0
  return 0;
562
0
}
563
564
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
565
0
  if (RetVT.SimpleTy != MVT::v8i16)
566
0
    return 0;
567
0
  if ((Subtarget->hasNEON())) {
568
0
    return fastEmitInst_r(ARM::VCLEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
569
0
  }
570
0
  return 0;
571
0
}
572
573
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
574
0
  if (RetVT.SimpleTy != MVT::v2i32)
575
0
    return 0;
576
0
  if ((Subtarget->hasNEON())) {
577
0
    return fastEmitInst_r(ARM::VCLEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
578
0
  }
579
0
  return 0;
580
0
}
581
582
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
583
0
  if (RetVT.SimpleTy != MVT::v4i32)
584
0
    return 0;
585
0
  if ((Subtarget->hasNEON())) {
586
0
    return fastEmitInst_r(ARM::VCLEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
587
0
  }
588
0
  return 0;
589
0
}
590
591
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
592
0
  if (RetVT.SimpleTy != MVT::v4i16)
593
0
    return 0;
594
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
595
0
    return fastEmitInst_r(ARM::VCLEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
596
0
  }
597
0
  return 0;
598
0
}
599
600
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
601
0
  if (RetVT.SimpleTy != MVT::v8i16)
602
0
    return 0;
603
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
604
0
    return fastEmitInst_r(ARM::VCLEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
605
0
  }
606
0
  return 0;
607
0
}
608
609
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
610
0
  if (RetVT.SimpleTy != MVT::v2i32)
611
0
    return 0;
612
0
  if ((Subtarget->hasNEON())) {
613
0
    return fastEmitInst_r(ARM::VCLEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
614
0
  }
615
0
  return 0;
616
0
}
617
618
0
unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
619
0
  if (RetVT.SimpleTy != MVT::v4i32)
620
0
    return 0;
621
0
  if ((Subtarget->hasNEON())) {
622
0
    return fastEmitInst_r(ARM::VCLEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
623
0
  }
624
0
  return 0;
625
0
}
626
627
unsigned fastEmit_ARMISD_VCLEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
628
  switch (VT.SimpleTy) {
629
  case MVT::v8i8: return fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
630
  case MVT::v16i8: return fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
631
  case MVT::v4i16: return fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
632
  case MVT::v8i16: return fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
633
  case MVT::v2i32: return fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
634
  case MVT::v4i32: return fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
635
  case MVT::v4f16: return fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
636
  case MVT::v8f16: return fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
637
  case MVT::v2f32: return fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
638
  case MVT::v4f32: return fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
639
  default: return 0;
640
  }
641
}
642
643
// FastEmit functions for ARMISD::VCLTZ.
644
645
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
646
0
  if (RetVT.SimpleTy != MVT::v8i8)
647
0
    return 0;
648
0
  if ((Subtarget->hasNEON())) {
649
0
    return fastEmitInst_r(ARM::VCLTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
650
0
  }
651
0
  return 0;
652
0
}
653
654
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
655
0
  if (RetVT.SimpleTy != MVT::v16i8)
656
0
    return 0;
657
0
  if ((Subtarget->hasNEON())) {
658
0
    return fastEmitInst_r(ARM::VCLTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
659
0
  }
660
0
  return 0;
661
0
}
662
663
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
664
0
  if (RetVT.SimpleTy != MVT::v4i16)
665
0
    return 0;
666
0
  if ((Subtarget->hasNEON())) {
667
0
    return fastEmitInst_r(ARM::VCLTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
668
0
  }
669
0
  return 0;
670
0
}
671
672
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
673
0
  if (RetVT.SimpleTy != MVT::v8i16)
674
0
    return 0;
675
0
  if ((Subtarget->hasNEON())) {
676
0
    return fastEmitInst_r(ARM::VCLTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
677
0
  }
678
0
  return 0;
679
0
}
680
681
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
682
0
  if (RetVT.SimpleTy != MVT::v2i32)
683
0
    return 0;
684
0
  if ((Subtarget->hasNEON())) {
685
0
    return fastEmitInst_r(ARM::VCLTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
686
0
  }
687
0
  return 0;
688
0
}
689
690
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
691
0
  if (RetVT.SimpleTy != MVT::v4i32)
692
0
    return 0;
693
0
  if ((Subtarget->hasNEON())) {
694
0
    return fastEmitInst_r(ARM::VCLTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
695
0
  }
696
0
  return 0;
697
0
}
698
699
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
700
0
  if (RetVT.SimpleTy != MVT::v4i16)
701
0
    return 0;
702
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
703
0
    return fastEmitInst_r(ARM::VCLTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
704
0
  }
705
0
  return 0;
706
0
}
707
708
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
709
0
  if (RetVT.SimpleTy != MVT::v8i16)
710
0
    return 0;
711
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
712
0
    return fastEmitInst_r(ARM::VCLTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
713
0
  }
714
0
  return 0;
715
0
}
716
717
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
718
0
  if (RetVT.SimpleTy != MVT::v2i32)
719
0
    return 0;
720
0
  if ((Subtarget->hasNEON())) {
721
0
    return fastEmitInst_r(ARM::VCLTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
722
0
  }
723
0
  return 0;
724
0
}
725
726
0
unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
727
0
  if (RetVT.SimpleTy != MVT::v4i32)
728
0
    return 0;
729
0
  if ((Subtarget->hasNEON())) {
730
0
    return fastEmitInst_r(ARM::VCLTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
731
0
  }
732
0
  return 0;
733
0
}
734
735
unsigned fastEmit_ARMISD_VCLTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
736
  switch (VT.SimpleTy) {
737
  case MVT::v8i8: return fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
738
  case MVT::v16i8: return fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
739
  case MVT::v4i16: return fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
740
  case MVT::v8i16: return fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
741
  case MVT::v2i32: return fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
742
  case MVT::v4i32: return fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
743
  case MVT::v4f16: return fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
744
  case MVT::v8f16: return fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
745
  case MVT::v2f32: return fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
746
  case MVT::v4f32: return fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
747
  default: return 0;
748
  }
749
}
750
751
// FastEmit functions for ARMISD::VDUP.
752
753
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
754
0
  if ((Subtarget->hasNEON())) {
755
0
    return fastEmitInst_r(ARM::VDUP8d, &ARM::DPRRegClass, Op0, Op0IsKill);
756
0
  }
757
0
  return 0;
758
0
}
759
760
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
761
0
  if ((Subtarget->hasNEON())) {
762
0
    return fastEmitInst_r(ARM::VDUP8q, &ARM::QPRRegClass, Op0, Op0IsKill);
763
0
  }
764
0
  return 0;
765
0
}
766
767
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
768
0
  if ((Subtarget->hasNEON())) {
769
0
    return fastEmitInst_r(ARM::VDUP16d, &ARM::DPRRegClass, Op0, Op0IsKill);
770
0
  }
771
0
  return 0;
772
0
}
773
774
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
775
0
  if ((Subtarget->hasNEON())) {
776
0
    return fastEmitInst_r(ARM::VDUP16q, &ARM::QPRRegClass, Op0, Op0IsKill);
777
0
  }
778
0
  return 0;
779
0
}
780
781
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
782
0
  if ((!Subtarget->hasSlowVDUP32()) && (Subtarget->hasNEON())) {
783
0
    return fastEmitInst_r(ARM::VDUP32d, &ARM::DPRRegClass, Op0, Op0IsKill);
784
0
  }
785
0
  return 0;
786
0
}
787
788
0
unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
789
0
  if ((Subtarget->hasNEON())) {
790
0
    return fastEmitInst_r(ARM::VDUP32q, &ARM::QPRRegClass, Op0, Op0IsKill);
791
0
  }
792
0
  return 0;
793
0
}
794
795
unsigned fastEmit_ARMISD_VDUP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
796
switch (RetVT.SimpleTy) {
797
  case MVT::v8i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(Op0, Op0IsKill);
798
  case MVT::v16i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(Op0, Op0IsKill);
799
  case MVT::v4i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(Op0, Op0IsKill);
800
  case MVT::v8i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(Op0, Op0IsKill);
801
  case MVT::v2i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(Op0, Op0IsKill);
802
  case MVT::v4i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill);
803
  default: return 0;
804
}
805
}
806
807
unsigned fastEmit_ARMISD_VDUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
808
  switch (VT.SimpleTy) {
809
  case MVT::i32: return fastEmit_ARMISD_VDUP_MVT_i32_r(RetVT, Op0, Op0IsKill);
810
  default: return 0;
811
  }
812
}
813
814
// FastEmit functions for ARMISD::VMOVSR.
815
816
0
unsigned fastEmit_ARMISD_VMOVSR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
817
0
  if (RetVT.SimpleTy != MVT::f32)
818
0
    return 0;
819
0
  if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) {
820
0
    return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
821
0
  }
822
0
  return 0;
823
0
}
824
825
unsigned fastEmit_ARMISD_VMOVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
826
  switch (VT.SimpleTy) {
827
  case MVT::i32: return fastEmit_ARMISD_VMOVSR_MVT_i32_r(RetVT, Op0, Op0IsKill);
828
  default: return 0;
829
  }
830
}
831
832
// FastEmit functions for ARMISD::VMOVhr.
833
834
0
unsigned fastEmit_ARMISD_VMOVhr_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
835
0
  if (RetVT.SimpleTy != MVT::f16)
836
0
    return 0;
837
0
  if ((Subtarget->hasFullFP16())) {
838
0
    return fastEmitInst_r(ARM::VMOVHR, &ARM::HPRRegClass, Op0, Op0IsKill);
839
0
  }
840
0
  return 0;
841
0
}
842
843
unsigned fastEmit_ARMISD_VMOVhr_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
844
  switch (VT.SimpleTy) {
845
  case MVT::i32: return fastEmit_ARMISD_VMOVhr_MVT_i32_r(RetVT, Op0, Op0IsKill);
846
  default: return 0;
847
  }
848
}
849
850
// FastEmit functions for ARMISD::VMOVrh.
851
852
0
unsigned fastEmit_ARMISD_VMOVrh_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
853
0
  if (RetVT.SimpleTy != MVT::i32)
854
0
    return 0;
855
0
  if ((Subtarget->hasFullFP16())) {
856
0
    return fastEmitInst_r(ARM::VMOVRH, &ARM::GPRRegClass, Op0, Op0IsKill);
857
0
  }
858
0
  return 0;
859
0
}
860
861
unsigned fastEmit_ARMISD_VMOVrh_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
862
  switch (VT.SimpleTy) {
863
  case MVT::f16: return fastEmit_ARMISD_VMOVrh_MVT_f16_r(RetVT, Op0, Op0IsKill);
864
  default: return 0;
865
  }
866
}
867
868
// FastEmit functions for ARMISD::VREV16.
869
870
0
unsigned fastEmit_ARMISD_VREV16_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
871
0
  if (RetVT.SimpleTy != MVT::v8i8)
872
0
    return 0;
873
0
  if ((Subtarget->hasNEON())) {
874
0
    return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
875
0
  }
876
0
  return 0;
877
0
}
878
879
0
unsigned fastEmit_ARMISD_VREV16_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
880
0
  if (RetVT.SimpleTy != MVT::v16i8)
881
0
    return 0;
882
0
  if ((Subtarget->hasNEON())) {
883
0
    return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
884
0
  }
885
0
  return 0;
886
0
}
887
888
unsigned fastEmit_ARMISD_VREV16_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
889
  switch (VT.SimpleTy) {
890
  case MVT::v8i8: return fastEmit_ARMISD_VREV16_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
891
  case MVT::v16i8: return fastEmit_ARMISD_VREV16_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
892
  default: return 0;
893
  }
894
}
895
896
// FastEmit functions for ARMISD::VREV32.
897
898
0
unsigned fastEmit_ARMISD_VREV32_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
899
0
  if (RetVT.SimpleTy != MVT::v8i8)
900
0
    return 0;
901
0
  if ((Subtarget->hasNEON())) {
902
0
    return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
903
0
  }
904
0
  return 0;
905
0
}
906
907
0
unsigned fastEmit_ARMISD_VREV32_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
908
0
  if (RetVT.SimpleTy != MVT::v16i8)
909
0
    return 0;
910
0
  if ((Subtarget->hasNEON())) {
911
0
    return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
912
0
  }
913
0
  return 0;
914
0
}
915
916
0
unsigned fastEmit_ARMISD_VREV32_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
917
0
  if (RetVT.SimpleTy != MVT::v4i16)
918
0
    return 0;
919
0
  if ((Subtarget->hasNEON())) {
920
0
    return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
921
0
  }
922
0
  return 0;
923
0
}
924
925
0
unsigned fastEmit_ARMISD_VREV32_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
926
0
  if (RetVT.SimpleTy != MVT::v8i16)
927
0
    return 0;
928
0
  if ((Subtarget->hasNEON())) {
929
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
930
0
  }
931
0
  return 0;
932
0
}
933
934
unsigned fastEmit_ARMISD_VREV32_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
935
  switch (VT.SimpleTy) {
936
  case MVT::v8i8: return fastEmit_ARMISD_VREV32_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
937
  case MVT::v16i8: return fastEmit_ARMISD_VREV32_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
938
  case MVT::v4i16: return fastEmit_ARMISD_VREV32_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
939
  case MVT::v8i16: return fastEmit_ARMISD_VREV32_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
940
  default: return 0;
941
  }
942
}
943
944
// FastEmit functions for ARMISD::VREV64.
945
946
0
unsigned fastEmit_ARMISD_VREV64_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
947
0
  if (RetVT.SimpleTy != MVT::v8i8)
948
0
    return 0;
949
0
  if ((Subtarget->hasNEON())) {
950
0
    return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
951
0
  }
952
0
  return 0;
953
0
}
954
955
0
unsigned fastEmit_ARMISD_VREV64_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
956
0
  if (RetVT.SimpleTy != MVT::v16i8)
957
0
    return 0;
958
0
  if ((Subtarget->hasNEON())) {
959
0
    return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
960
0
  }
961
0
  return 0;
962
0
}
963
964
0
unsigned fastEmit_ARMISD_VREV64_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
965
0
  if (RetVT.SimpleTy != MVT::v4i16)
966
0
    return 0;
967
0
  if ((Subtarget->hasNEON())) {
968
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
969
0
  }
970
0
  return 0;
971
0
}
972
973
0
unsigned fastEmit_ARMISD_VREV64_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
974
0
  if (RetVT.SimpleTy != MVT::v8i16)
975
0
    return 0;
976
0
  if ((Subtarget->hasNEON())) {
977
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
978
0
  }
979
0
  return 0;
980
0
}
981
982
0
unsigned fastEmit_ARMISD_VREV64_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
983
0
  if (RetVT.SimpleTy != MVT::v2i32)
984
0
    return 0;
985
0
  if ((Subtarget->hasNEON())) {
986
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
987
0
  }
988
0
  return 0;
989
0
}
990
991
0
unsigned fastEmit_ARMISD_VREV64_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
992
0
  if (RetVT.SimpleTy != MVT::v4i32)
993
0
    return 0;
994
0
  if ((Subtarget->hasNEON())) {
995
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
996
0
  }
997
0
  return 0;
998
0
}
999
1000
0
unsigned fastEmit_ARMISD_VREV64_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1001
0
  if (RetVT.SimpleTy != MVT::v2f32)
1002
0
    return 0;
1003
0
  return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1004
0
}
1005
1006
0
unsigned fastEmit_ARMISD_VREV64_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1007
0
  if (RetVT.SimpleTy != MVT::v4f32)
1008
0
    return 0;
1009
0
  return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1010
0
}
1011
1012
unsigned fastEmit_ARMISD_VREV64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1013
  switch (VT.SimpleTy) {
1014
  case MVT::v8i8: return fastEmit_ARMISD_VREV64_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1015
  case MVT::v16i8: return fastEmit_ARMISD_VREV64_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1016
  case MVT::v4i16: return fastEmit_ARMISD_VREV64_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1017
  case MVT::v8i16: return fastEmit_ARMISD_VREV64_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1018
  case MVT::v2i32: return fastEmit_ARMISD_VREV64_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1019
  case MVT::v4i32: return fastEmit_ARMISD_VREV64_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1020
  case MVT::v2f32: return fastEmit_ARMISD_VREV64_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
1021
  case MVT::v4f32: return fastEmit_ARMISD_VREV64_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
1022
  default: return 0;
1023
  }
1024
}
1025
1026
// FastEmit functions for ARMISD::WIN__DBZCHK.
1027
1028
0
unsigned fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1029
0
  if (RetVT.SimpleTy != MVT::isVoid)
1030
0
    return 0;
1031
0
  return fastEmitInst_r(ARM::WIN__DBZCHK, &ARM::tGPRRegClass, Op0, Op0IsKill);
1032
0
}
1033
1034
unsigned fastEmit_ARMISD_WIN__DBZCHK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1035
  switch (VT.SimpleTy) {
1036
  case MVT::i32: return fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(RetVT, Op0, Op0IsKill);
1037
  default: return 0;
1038
  }
1039
}
1040
1041
// FastEmit functions for ISD::ABS.
1042
1043
0
unsigned fastEmit_ISD_ABS_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1044
0
  if (RetVT.SimpleTy != MVT::v8i8)
1045
0
    return 0;
1046
0
  if ((Subtarget->hasNEON())) {
1047
0
    return fastEmitInst_r(ARM::VABSv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
1048
0
  }
1049
0
  return 0;
1050
0
}
1051
1052
0
unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1053
0
  if (RetVT.SimpleTy != MVT::v16i8)
1054
0
    return 0;
1055
0
  if ((Subtarget->hasNEON())) {
1056
0
    return fastEmitInst_r(ARM::VABSv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
1057
0
  }
1058
0
  return 0;
1059
0
}
1060
1061
0
unsigned fastEmit_ISD_ABS_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1062
0
  if (RetVT.SimpleTy != MVT::v4i16)
1063
0
    return 0;
1064
0
  if ((Subtarget->hasNEON())) {
1065
0
    return fastEmitInst_r(ARM::VABSv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
1066
0
  }
1067
0
  return 0;
1068
0
}
1069
1070
0
unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1071
0
  if (RetVT.SimpleTy != MVT::v8i16)
1072
0
    return 0;
1073
0
  if ((Subtarget->hasNEON())) {
1074
0
    return fastEmitInst_r(ARM::VABSv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
1075
0
  }
1076
0
  return 0;
1077
0
}
1078
1079
0
unsigned fastEmit_ISD_ABS_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1080
0
  if (RetVT.SimpleTy != MVT::v2i32)
1081
0
    return 0;
1082
0
  if ((Subtarget->hasNEON())) {
1083
0
    return fastEmitInst_r(ARM::VABSv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
1084
0
  }
1085
0
  return 0;
1086
0
}
1087
1088
0
unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1089
0
  if (RetVT.SimpleTy != MVT::v4i32)
1090
0
    return 0;
1091
0
  if ((Subtarget->hasNEON())) {
1092
0
    return fastEmitInst_r(ARM::VABSv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
1093
0
  }
1094
0
  return 0;
1095
0
}
1096
1097
unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1098
  switch (VT.SimpleTy) {
1099
  case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1100
  case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1101
  case MVT::v4i16: return fastEmit_ISD_ABS_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1102
  case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1103
  case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1104
  case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1105
  default: return 0;
1106
  }
1107
}
1108
1109
// FastEmit functions for ISD::ANY_EXTEND.
1110
1111
0
unsigned fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1112
0
  if (RetVT.SimpleTy != MVT::v8i16)
1113
0
    return 0;
1114
0
  return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
1115
0
}
1116
1117
0
unsigned fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1118
0
  if (RetVT.SimpleTy != MVT::v4i32)
1119
0
    return 0;
1120
0
  return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
1121
0
}
1122
1123
0
unsigned fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1124
0
  if (RetVT.SimpleTy != MVT::v2i64)
1125
0
    return 0;
1126
0
  return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
1127
0
}
1128
1129
unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1130
  switch (VT.SimpleTy) {
1131
  case MVT::v8i8: return fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1132
  case MVT::v4i16: return fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1133
  case MVT::v2i32: return fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1134
  default: return 0;
1135
  }
1136
}
1137
1138
// FastEmit functions for ISD::BITCAST.
1139
1140
0
unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1141
0
  if (RetVT.SimpleTy != MVT::f32)
1142
0
    return 0;
1143
0
  if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) {
1144
0
    return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
1145
0
  }
1146
0
  return 0;
1147
0
}
1148
1149
81
unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1150
81
  if (RetVT.SimpleTy != MVT::i32)
1151
0
    return 0;
1152
81
  if ((Subtarget->hasVFP2())) {
1153
81
    return fastEmitInst_r(ARM::VMOVRS, &ARM::GPRRegClass, Op0, Op0IsKill);
1154
81
  }
1155
0
  return 0;
1156
0
}
1157
1158
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1159
0
  if ((MF->getDataLayout().isBigEndian())) {
1160
0
    return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1161
0
  }
1162
0
  return 0;
1163
0
}
1164
1165
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1166
0
  if ((MF->getDataLayout().isBigEndian())) {
1167
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1168
0
  }
1169
0
  return 0;
1170
0
}
1171
1172
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1173
0
  if ((MF->getDataLayout().isBigEndian())) {
1174
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1175
0
  }
1176
0
  return 0;
1177
0
}
1178
1179
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1180
0
  if ((MF->getDataLayout().isBigEndian())) {
1181
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1182
0
  }
1183
0
  return 0;
1184
0
}
1185
1186
unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1187
switch (RetVT.SimpleTy) {
1188
  case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(Op0, Op0IsKill);
1189
  case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(Op0, Op0IsKill);
1190
  case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0, Op0IsKill);
1191
  case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(Op0, Op0IsKill);
1192
  default: return 0;
1193
}
1194
}
1195
1196
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1197
0
  if ((MF->getDataLayout().isBigEndian())) {
1198
0
    return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1199
0
  }
1200
0
  return 0;
1201
0
}
1202
1203
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1204
0
  if ((MF->getDataLayout().isBigEndian())) {
1205
0
    return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1206
0
  }
1207
0
  return 0;
1208
0
}
1209
1210
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1211
0
  if ((MF->getDataLayout().isBigEndian())) {
1212
0
    return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1213
0
  }
1214
0
  return 0;
1215
0
}
1216
1217
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1218
0
  if ((MF->getDataLayout().isBigEndian())) {
1219
0
    return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1220
0
  }
1221
0
  return 0;
1222
0
}
1223
1224
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1225
0
  if ((MF->getDataLayout().isBigEndian())) {
1226
0
    return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1227
0
  }
1228
0
  return 0;
1229
0
}
1230
1231
unsigned fastEmit_ISD_BITCAST_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1232
switch (RetVT.SimpleTy) {
1233
  case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(Op0, Op0IsKill);
1234
  case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(Op0, Op0IsKill);
1235
  case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0, Op0IsKill);
1236
  case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0, Op0IsKill);
1237
  case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(Op0, Op0IsKill);
1238
  default: return 0;
1239
}
1240
}
1241
1242
0
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1243
0
  if ((MF->getDataLayout().isBigEndian())) {
1244
0
    return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1245
0
  }
1246
0
  return 0;
1247
0
}
1248
1249
2
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1250
2
  if ((MF->getDataLayout().isBigEndian())) {
1251
0
    return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1252
0
  }
1253
2
  return 0;
1254
2
}
1255
1256
0
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1257
0
  if ((MF->getDataLayout().isBigEndian())) {
1258
0
    return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1259
0
  }
1260
0
  return 0;
1261
0
}
1262
1263
0
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1264
0
  if ((MF->getDataLayout().isBigEndian())) {
1265
0
    return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1266
0
  }
1267
0
  return 0;
1268
0
}
1269
1270
0
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1271
0
  if ((MF->getDataLayout().isBigEndian())) {
1272
0
    return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1273
0
  }
1274
0
  return 0;
1275
0
}
1276
1277
2
unsigned fastEmit_ISD_BITCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1278
2
switch (RetVT.SimpleTy) {
1279
2
  
case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill)0
;
1280
2
  case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
1281
2
  
case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill)0
;
1282
2
  
case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(Op0, Op0IsKill)0
;
1283
2
  
case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(Op0, Op0IsKill)0
;
1284
2
  
default: return 00
;
1285
2
}
1286
2
}
1287
1288
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1289
0
  if ((MF->getDataLayout().isBigEndian())) {
1290
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1291
0
  }
1292
0
  return 0;
1293
0
}
1294
1295
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1296
0
  if ((MF->getDataLayout().isBigEndian())) {
1297
0
    return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1298
0
  }
1299
0
  return 0;
1300
0
}
1301
1302
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1303
0
  if ((MF->getDataLayout().isBigEndian())) {
1304
0
    return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1305
0
  }
1306
0
  return 0;
1307
0
}
1308
1309
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1310
0
  if ((MF->getDataLayout().isBigEndian())) {
1311
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1312
0
  }
1313
0
  return 0;
1314
0
}
1315
1316
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1317
0
  if ((MF->getDataLayout().isBigEndian())) {
1318
0
    return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1319
0
  }
1320
0
  return 0;
1321
0
}
1322
1323
unsigned fastEmit_ISD_BITCAST_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1324
switch (RetVT.SimpleTy) {
1325
  case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(Op0, Op0IsKill);
1326
  case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(Op0, Op0IsKill);
1327
  case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0, Op0IsKill);
1328
  case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0, Op0IsKill);
1329
  case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(Op0, Op0IsKill);
1330
  default: return 0;
1331
}
1332
}
1333
1334
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1335
0
  if ((MF->getDataLayout().isBigEndian())) {
1336
0
    return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1337
0
  }
1338
0
  return 0;
1339
0
}
1340
1341
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1342
0
  if ((MF->getDataLayout().isBigEndian())) {
1343
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1344
0
  }
1345
0
  return 0;
1346
0
}
1347
1348
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1349
0
  if ((MF->getDataLayout().isBigEndian())) {
1350
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1351
0
  }
1352
0
  return 0;
1353
0
}
1354
1355
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1356
0
  if ((MF->getDataLayout().isBigEndian())) {
1357
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1358
0
  }
1359
0
  return 0;
1360
0
}
1361
1362
0
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1363
0
  if ((MF->getDataLayout().isBigEndian())) {
1364
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1365
0
  }
1366
0
  return 0;
1367
0
}
1368
1369
unsigned fastEmit_ISD_BITCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1370
switch (RetVT.SimpleTy) {
1371
  case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(Op0, Op0IsKill);
1372
  case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
1373
  case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
1374
  case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(Op0, Op0IsKill);
1375
  case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(Op0, Op0IsKill);
1376
  default: return 0;
1377
}
1378
}
1379
1380
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1381
0
  if ((MF->getDataLayout().isBigEndian())) {
1382
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1383
0
  }
1384
0
  return 0;
1385
0
}
1386
1387
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1388
0
  if ((MF->getDataLayout().isBigEndian())) {
1389
0
    return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1390
0
  }
1391
0
  return 0;
1392
0
}
1393
1394
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1395
0
  if ((MF->getDataLayout().isBigEndian())) {
1396
0
    return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1397
0
  }
1398
0
  return 0;
1399
0
}
1400
1401
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1402
0
  if ((MF->getDataLayout().isBigEndian())) {
1403
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1404
0
  }
1405
0
  return 0;
1406
0
}
1407
1408
unsigned fastEmit_ISD_BITCAST_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1409
switch (RetVT.SimpleTy) {
1410
  case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(Op0, Op0IsKill);
1411
  case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(Op0, Op0IsKill);
1412
  case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(Op0, Op0IsKill);
1413
  case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0, Op0IsKill);
1414
  default: return 0;
1415
}
1416
}
1417
1418
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1419
0
  if ((MF->getDataLayout().isBigEndian())) {
1420
0
    return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1421
0
  }
1422
0
  return 0;
1423
0
}
1424
1425
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1426
0
  if ((MF->getDataLayout().isBigEndian())) {
1427
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1428
0
  }
1429
0
  return 0;
1430
0
}
1431
1432
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1433
0
  if ((MF->getDataLayout().isBigEndian())) {
1434
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1435
0
  }
1436
0
  return 0;
1437
0
}
1438
1439
0
unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1440
0
  if ((MF->getDataLayout().isBigEndian())) {
1441
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1442
0
  }
1443
0
  return 0;
1444
0
}
1445
1446
unsigned fastEmit_ISD_BITCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1447
switch (RetVT.SimpleTy) {
1448
  case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill);
1449
  case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill);
1450
  case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(Op0, Op0IsKill);
1451
  case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(Op0, Op0IsKill);
1452
  default: return 0;
1453
}
1454
}
1455
1456
0
unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1457
0
  if ((MF->getDataLayout().isBigEndian())) {
1458
0
    return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1459
0
  }
1460
0
  return 0;
1461
0
}
1462
1463
0
unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1464
0
  if ((MF->getDataLayout().isBigEndian())) {
1465
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1466
0
  }
1467
0
  return 0;
1468
0
}
1469
1470
0
unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1471
0
  if ((MF->getDataLayout().isBigEndian())) {
1472
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1473
0
  }
1474
0
  return 0;
1475
0
}
1476
1477
0
unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1478
0
  if ((MF->getDataLayout().isBigEndian())) {
1479
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1480
0
  }
1481
0
  return 0;
1482
0
}
1483
1484
unsigned fastEmit_ISD_BITCAST_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1485
switch (RetVT.SimpleTy) {
1486
  case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(Op0, Op0IsKill);
1487
  case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(Op0, Op0IsKill);
1488
  case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0, Op0IsKill);
1489
  case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(Op0, Op0IsKill);
1490
  default: return 0;
1491
}
1492
}
1493
1494
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1495
0
  if ((MF->getDataLayout().isBigEndian())) {
1496
0
    return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1497
0
  }
1498
0
  return 0;
1499
0
}
1500
1501
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1502
0
  if ((MF->getDataLayout().isBigEndian())) {
1503
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1504
0
  }
1505
0
  return 0;
1506
0
}
1507
1508
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1509
0
  if ((MF->getDataLayout().isBigEndian())) {
1510
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1511
0
  }
1512
0
  return 0;
1513
0
}
1514
1515
0
unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1516
0
  if ((MF->getDataLayout().isBigEndian())) {
1517
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1518
0
  }
1519
0
  return 0;
1520
0
}
1521
1522
unsigned fastEmit_ISD_BITCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1523
switch (RetVT.SimpleTy) {
1524
  case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill);
1525
  case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill);
1526
  case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill);
1527
  case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(Op0, Op0IsKill);
1528
  default: return 0;
1529
}
1530
}
1531
1532
0
unsigned fastEmit_ISD_BITCAST_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1533
0
  if (RetVT.SimpleTy != MVT::f64)
1534
0
    return 0;
1535
0
  if ((MF->getDataLayout().isBigEndian())) {
1536
0
    return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1537
0
  }
1538
0
  return 0;
1539
0
}
1540
1541
0
unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1542
0
  if ((MF->getDataLayout().isBigEndian())) {
1543
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1544
0
  }
1545
0
  return 0;
1546
0
}
1547
1548
0
unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1549
0
  if ((MF->getDataLayout().isBigEndian())) {
1550
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1551
0
  }
1552
0
  return 0;
1553
0
}
1554
1555
unsigned fastEmit_ISD_BITCAST_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1556
switch (RetVT.SimpleTy) {
1557
  case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(Op0, Op0IsKill);
1558
  case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(Op0, Op0IsKill);
1559
  default: return 0;
1560
}
1561
}
1562
1563
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1564
0
  if ((MF->getDataLayout().isBigEndian())) {
1565
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1566
0
  }
1567
0
  return 0;
1568
0
}
1569
1570
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1571
0
  if ((MF->getDataLayout().isBigEndian())) {
1572
0
    return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1573
0
  }
1574
0
  return 0;
1575
0
}
1576
1577
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1578
0
  if ((MF->getDataLayout().isBigEndian())) {
1579
0
    return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1580
0
  }
1581
0
  return 0;
1582
0
}
1583
1584
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1585
0
  if ((MF->getDataLayout().isBigEndian())) {
1586
0
    return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1587
0
  }
1588
0
  return 0;
1589
0
}
1590
1591
unsigned fastEmit_ISD_BITCAST_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1592
switch (RetVT.SimpleTy) {
1593
  case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(Op0, Op0IsKill);
1594
  case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(Op0, Op0IsKill);
1595
  case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(Op0, Op0IsKill);
1596
  case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0, Op0IsKill);
1597
  default: return 0;
1598
}
1599
}
1600
1601
0
unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1602
0
  if ((MF->getDataLayout().isBigEndian())) {
1603
0
    return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1604
0
  }
1605
0
  return 0;
1606
0
}
1607
1608
0
unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1609
0
  if ((MF->getDataLayout().isBigEndian())) {
1610
0
    return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1611
0
  }
1612
0
  return 0;
1613
0
}
1614
1615
0
unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1616
0
  if ((MF->getDataLayout().isBigEndian())) {
1617
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1618
0
  }
1619
0
  return 0;
1620
0
}
1621
1622
0
unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1623
0
  if ((MF->getDataLayout().isBigEndian())) {
1624
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1625
0
  }
1626
0
  return 0;
1627
0
}
1628
1629
unsigned fastEmit_ISD_BITCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1630
switch (RetVT.SimpleTy) {
1631
  case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(Op0, Op0IsKill);
1632
  case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(Op0, Op0IsKill);
1633
  case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill);
1634
  case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(Op0, Op0IsKill);
1635
  default: return 0;
1636
}
1637
}
1638
1639
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1640
0
  if ((MF->getDataLayout().isBigEndian())) {
1641
0
    return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1642
0
  }
1643
0
  return 0;
1644
0
}
1645
1646
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1647
0
  if ((MF->getDataLayout().isBigEndian())) {
1648
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1649
0
  }
1650
0
  return 0;
1651
0
}
1652
1653
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1654
0
  if ((MF->getDataLayout().isBigEndian())) {
1655
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1656
0
  }
1657
0
  return 0;
1658
0
}
1659
1660
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) {
1661
0
  if ((MF->getDataLayout().isBigEndian())) {
1662
0
    return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1663
0
  }
1664
0
  return 0;
1665
0
}
1666
1667
0
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1668
0
  if ((MF->getDataLayout().isBigEndian())) {
1669
0
    return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1670
0
  }
1671
0
  return 0;
1672
0
}
1673
1674
unsigned fastEmit_ISD_BITCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1675
switch (RetVT.SimpleTy) {
1676
  case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(Op0, Op0IsKill);
1677
  case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(Op0, Op0IsKill);
1678
  case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill);
1679
  case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(Op0, Op0IsKill);
1680
  case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(Op0, Op0IsKill);
1681
  default: return 0;
1682
}
1683
}
1684
1685
83
unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1686
83
  switch (VT.SimpleTy) {
1687
83
  
case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill)0
;
1688
83
  
case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill)81
;
1689
83
  
case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill)0
;
1690
83
  
case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v8i8_r(RetVT, Op0, Op0IsKill)0
;
1691
83
  
case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v16i8_r(RetVT, Op0, Op0IsKill)2
;
1692
83
  
case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v4i16_r(RetVT, Op0, Op0IsKill)0
;
1693
83
  
case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v8i16_r(RetVT, Op0, Op0IsKill)0
;
1694
83
  
case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v2i32_r(RetVT, Op0, Op0IsKill)0
;
1695
83
  
case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v4i32_r(RetVT, Op0, Op0IsKill)0
;
1696
83
  
case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0, Op0IsKill)0
;
1697
83
  
case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v2i64_r(RetVT, Op0, Op0IsKill)0
;
1698
83
  
case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v4f16_r(RetVT, Op0, Op0IsKill)0
;
1699
83
  
case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v8f16_r(RetVT, Op0, Op0IsKill)0
;
1700
83
  
case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v2f32_r(RetVT, Op0, Op0IsKill)0
;
1701
83
  
case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v4f32_r(RetVT, Op0, Op0IsKill)0
;
1702
83
  
case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v2f64_r(RetVT, Op0, Op0IsKill)0
;
1703
83
  
default: return 00
;
1704
83
  }
1705
83
}
1706
1707
// FastEmit functions for ISD::BITREVERSE.
1708
1709
0
unsigned fastEmit_ISD_BITREVERSE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1710
0
  if (RetVT.SimpleTy != MVT::i32)
1711
0
    return 0;
1712
0
  if ((Subtarget->isThumb2())) {
1713
0
    return fastEmitInst_r(ARM::t2RBIT, &ARM::rGPRRegClass, Op0, Op0IsKill);
1714
0
  }
1715
0
  if ((Subtarget->hasV6T2Ops()) && (!Subtarget->isThumb())) {
1716
0
    return fastEmitInst_r(ARM::RBIT, &ARM::GPRRegClass, Op0, Op0IsKill);
1717
0
  }
1718
0
  return 0;
1719
0
}
1720
1721
unsigned fastEmit_ISD_BITREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1722
  switch (VT.SimpleTy) {
1723
  case MVT::i32: return fastEmit_ISD_BITREVERSE_MVT_i32_r(RetVT, Op0, Op0IsKill);
1724
  default: return 0;
1725
  }
1726
}
1727
1728
// FastEmit functions for ISD::BRIND.
1729
1730
0
unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1731
0
  if (RetVT.SimpleTy != MVT::isVoid)
1732
0
    return 0;
1733
0
  if ((Subtarget->isThumb())) {
1734
0
    return fastEmitInst_r(ARM::tBRIND, &ARM::GPRRegClass, Op0, Op0IsKill);
1735
0
  }
1736
0
  if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
1737
0
    return fastEmitInst_r(ARM::MOVPCRX, &ARM::GPRRegClass, Op0, Op0IsKill);
1738
0
  }
1739
0
  if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
1740
0
    return fastEmitInst_r(ARM::BX, &ARM::GPRRegClass, Op0, Op0IsKill);
1741
0
  }
1742
0
  return 0;
1743
0
}
1744
1745
unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1746
  switch (VT.SimpleTy) {
1747
  case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
1748
  default: return 0;
1749
  }
1750
}
1751
1752
// FastEmit functions for ISD::BSWAP.
1753
1754
0
unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1755
0
  if (RetVT.SimpleTy != MVT::i32)
1756
0
    return 0;
1757
0
  if ((Subtarget->isThumb2())) {
1758
0
    return fastEmitInst_r(ARM::t2REV, &ARM::rGPRRegClass, Op0, Op0IsKill);
1759
0
  }
1760
0
  if ((Subtarget->hasV6Ops()) && (Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
1761
0
    return fastEmitInst_r(ARM::tREV, &ARM::tGPRRegClass, Op0, Op0IsKill);
1762
0
  }
1763
0
  if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
1764
0
    return fastEmitInst_r(ARM::REV, &ARM::GPRRegClass, Op0, Op0IsKill);
1765
0
  }
1766
0
  return 0;
1767
0
}
1768
1769
unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1770
  switch (VT.SimpleTy) {
1771
  case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0, Op0IsKill);
1772
  default: return 0;
1773
  }
1774
}
1775
1776
// FastEmit functions for ISD::CTLZ.
1777
1778
0
unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1779
0
  if (RetVT.SimpleTy != MVT::i32)
1780
0
    return 0;
1781
0
  if ((Subtarget->isThumb2())) {
1782
0
    return fastEmitInst_r(ARM::t2CLZ, &ARM::rGPRRegClass, Op0, Op0IsKill);
1783
0
  }
1784
0
  if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
1785
0
    return fastEmitInst_r(ARM::CLZ, &ARM::GPRRegClass, Op0, Op0IsKill);
1786
0
  }
1787
0
  return 0;
1788
0
}
1789
1790
0
unsigned fastEmit_ISD_CTLZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1791
0
  if (RetVT.SimpleTy != MVT::v8i8)
1792
0
    return 0;
1793
0
  if ((Subtarget->hasNEON())) {
1794
0
    return fastEmitInst_r(ARM::VCLZv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
1795
0
  }
1796
0
  return 0;
1797
0
}
1798
1799
0
unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1800
0
  if (RetVT.SimpleTy != MVT::v16i8)
1801
0
    return 0;
1802
0
  if ((Subtarget->hasNEON())) {
1803
0
    return fastEmitInst_r(ARM::VCLZv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
1804
0
  }
1805
0
  return 0;
1806
0
}
1807
1808
0
unsigned fastEmit_ISD_CTLZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1809
0
  if (RetVT.SimpleTy != MVT::v4i16)
1810
0
    return 0;
1811
0
  if ((Subtarget->hasNEON())) {
1812
0
    return fastEmitInst_r(ARM::VCLZv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
1813
0
  }
1814
0
  return 0;
1815
0
}
1816
1817
0
unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1818
0
  if (RetVT.SimpleTy != MVT::v8i16)
1819
0
    return 0;
1820
0
  if ((Subtarget->hasNEON())) {
1821
0
    return fastEmitInst_r(ARM::VCLZv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
1822
0
  }
1823
0
  return 0;
1824
0
}
1825
1826
0
unsigned fastEmit_ISD_CTLZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1827
0
  if (RetVT.SimpleTy != MVT::v2i32)
1828
0
    return 0;
1829
0
  if ((Subtarget->hasNEON())) {
1830
0
    return fastEmitInst_r(ARM::VCLZv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
1831
0
  }
1832
0
  return 0;
1833
0
}
1834
1835
0
unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1836
0
  if (RetVT.SimpleTy != MVT::v4i32)
1837
0
    return 0;
1838
0
  if ((Subtarget->hasNEON())) {
1839
0
    return fastEmitInst_r(ARM::VCLZv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
1840
0
  }
1841
0
  return 0;
1842
0
}
1843
1844
unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1845
  switch (VT.SimpleTy) {
1846
  case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
1847
  case MVT::v8i8: return fastEmit_ISD_CTLZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1848
  case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1849
  case MVT::v4i16: return fastEmit_ISD_CTLZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1850
  case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1851
  case MVT::v2i32: return fastEmit_ISD_CTLZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1852
  case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1853
  default: return 0;
1854
  }
1855
}
1856
1857
// FastEmit functions for ISD::CTPOP.
1858
1859
0
unsigned fastEmit_ISD_CTPOP_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1860
0
  if (RetVT.SimpleTy != MVT::v8i8)
1861
0
    return 0;
1862
0
  if ((Subtarget->hasNEON())) {
1863
0
    return fastEmitInst_r(ARM::VCNTd, &ARM::DPRRegClass, Op0, Op0IsKill);
1864
0
  }
1865
0
  return 0;
1866
0
}
1867
1868
0
unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1869
0
  if (RetVT.SimpleTy != MVT::v16i8)
1870
0
    return 0;
1871
0
  if ((Subtarget->hasNEON())) {
1872
0
    return fastEmitInst_r(ARM::VCNTq, &ARM::QPRRegClass, Op0, Op0IsKill);
1873
0
  }
1874
0
  return 0;
1875
0
}
1876
1877
unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1878
  switch (VT.SimpleTy) {
1879
  case MVT::v8i8: return fastEmit_ISD_CTPOP_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1880
  case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1881
  default: return 0;
1882
  }
1883
}
1884
1885
// FastEmit functions for ISD::FABS.
1886
1887
0
unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1888
0
  if (RetVT.SimpleTy != MVT::f32)
1889
0
    return 0;
1890
0
  if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
1891
0
    return fastEmitInst_r(ARM::VABSS, &ARM::SPRRegClass, Op0, Op0IsKill);
1892
0
  }
1893
0
  return 0;
1894
0
}
1895
1896
0
unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1897
0
  if (RetVT.SimpleTy != MVT::f64)
1898
0
    return 0;
1899
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
1900
0
    return fastEmitInst_r(ARM::VABSD, &ARM::DPRRegClass, Op0, Op0IsKill);
1901
0
  }
1902
0
  return 0;
1903
0
}
1904
1905
0
unsigned fastEmit_ISD_FABS_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1906
0
  if (RetVT.SimpleTy != MVT::v4f16)
1907
0
    return 0;
1908
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
1909
0
    return fastEmitInst_r(ARM::VABShd, &ARM::DPRRegClass, Op0, Op0IsKill);
1910
0
  }
1911
0
  return 0;
1912
0
}
1913
1914
0
unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1915
0
  if (RetVT.SimpleTy != MVT::v8f16)
1916
0
    return 0;
1917
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
1918
0
    return fastEmitInst_r(ARM::VABShq, &ARM::QPRRegClass, Op0, Op0IsKill);
1919
0
  }
1920
0
  return 0;
1921
0
}
1922
1923
0
unsigned fastEmit_ISD_FABS_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1924
0
  if (RetVT.SimpleTy != MVT::v2f32)
1925
0
    return 0;
1926
0
  if ((Subtarget->hasNEON())) {
1927
0
    return fastEmitInst_r(ARM::VABSfd, &ARM::DPRRegClass, Op0, Op0IsKill);
1928
0
  }
1929
0
  return 0;
1930
0
}
1931
1932
0
unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1933
0
  if (RetVT.SimpleTy != MVT::v4f32)
1934
0
    return 0;
1935
0
  if ((Subtarget->hasNEON())) {
1936
0
    return fastEmitInst_r(ARM::VABSfq, &ARM::QPRRegClass, Op0, Op0IsKill);
1937
0
  }
1938
0
  return 0;
1939
0
}
1940
1941
unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1942
  switch (VT.SimpleTy) {
1943
  case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
1944
  case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
1945
  case MVT::v4f16: return fastEmit_ISD_FABS_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
1946
  case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
1947
  case MVT::v2f32: return fastEmit_ISD_FABS_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
1948
  case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
1949
  default: return 0;
1950
  }
1951
}
1952
1953
// FastEmit functions for ISD::FCEIL.
1954
1955
0
unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1956
0
  if (RetVT.SimpleTy != MVT::f32)
1957
0
    return 0;
1958
0
  if ((Subtarget->hasFPARMv8())) {
1959
0
    return fastEmitInst_r(ARM::VRINTPS, &ARM::SPRRegClass, Op0, Op0IsKill);
1960
0
  }
1961
0
  return 0;
1962
0
}
1963
1964
0
unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1965
0
  if (RetVT.SimpleTy != MVT::f64)
1966
0
    return 0;
1967
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
1968
0
    return fastEmitInst_r(ARM::VRINTPD, &ARM::DPRRegClass, Op0, Op0IsKill);
1969
0
  }
1970
0
  return 0;
1971
0
}
1972
1973
unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1974
  switch (VT.SimpleTy) {
1975
  case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
1976
  case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
1977
  default: return 0;
1978
  }
1979
}
1980
1981
// FastEmit functions for ISD::FFLOOR.
1982
1983
0
unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1984
0
  if (RetVT.SimpleTy != MVT::f32)
1985
0
    return 0;
1986
0
  if ((Subtarget->hasFPARMv8())) {
1987
0
    return fastEmitInst_r(ARM::VRINTMS, &ARM::SPRRegClass, Op0, Op0IsKill);
1988
0
  }
1989
0
  return 0;
1990
0
}
1991
1992
0
unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1993
0
  if (RetVT.SimpleTy != MVT::f64)
1994
0
    return 0;
1995
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
1996
0
    return fastEmitInst_r(ARM::VRINTMD, &ARM::DPRRegClass, Op0, Op0IsKill);
1997
0
  }
1998
0
  return 0;
1999
0
}
2000
2001
unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2002
  switch (VT.SimpleTy) {
2003
  case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
2004
  case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
2005
  default: return 0;
2006
  }
2007
}
2008
2009
// FastEmit functions for ISD::FNEARBYINT.
2010
2011
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2012
0
  if (RetVT.SimpleTy != MVT::f32)
2013
0
    return 0;
2014
0
  if ((Subtarget->hasFPARMv8())) {
2015
0
    return fastEmitInst_r(ARM::VRINTRS, &ARM::SPRRegClass, Op0, Op0IsKill);
2016
0
  }
2017
0
  return 0;
2018
0
}
2019
2020
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2021
0
  if (RetVT.SimpleTy != MVT::f64)
2022
0
    return 0;
2023
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2024
0
    return fastEmitInst_r(ARM::VRINTRD, &ARM::DPRRegClass, Op0, Op0IsKill);
2025
0
  }
2026
0
  return 0;
2027
0
}
2028
2029
unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2030
  switch (VT.SimpleTy) {
2031
  case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
2032
  case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
2033
  default: return 0;
2034
  }
2035
}
2036
2037
// FastEmit functions for ISD::FNEG.
2038
2039
0
unsigned fastEmit_ISD_FNEG_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2040
0
  if (RetVT.SimpleTy != MVT::f16)
2041
0
    return 0;
2042
0
  if ((Subtarget->hasFullFP16())) {
2043
0
    return fastEmitInst_r(ARM::VNEGH, &ARM::HPRRegClass, Op0, Op0IsKill);
2044
0
  }
2045
0
  return 0;
2046
0
}
2047
2048
0
unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2049
0
  if (RetVT.SimpleTy != MVT::f32)
2050
0
    return 0;
2051
0
  if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
2052
0
    return fastEmitInst_r(ARM::VNEGS, &ARM::SPRRegClass, Op0, Op0IsKill);
2053
0
  }
2054
0
  return 0;
2055
0
}
2056
2057
0
unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2058
0
  if (RetVT.SimpleTy != MVT::f64)
2059
0
    return 0;
2060
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2061
0
    return fastEmitInst_r(ARM::VNEGD, &ARM::DPRRegClass, Op0, Op0IsKill);
2062
0
  }
2063
0
  return 0;
2064
0
}
2065
2066
0
unsigned fastEmit_ISD_FNEG_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2067
0
  if (RetVT.SimpleTy != MVT::v4f16)
2068
0
    return 0;
2069
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2070
0
    return fastEmitInst_r(ARM::VNEGhd, &ARM::DPRRegClass, Op0, Op0IsKill);
2071
0
  }
2072
0
  return 0;
2073
0
}
2074
2075
0
unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2076
0
  if (RetVT.SimpleTy != MVT::v8f16)
2077
0
    return 0;
2078
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2079
0
    return fastEmitInst_r(ARM::VNEGhq, &ARM::QPRRegClass, Op0, Op0IsKill);
2080
0
  }
2081
0
  return 0;
2082
0
}
2083
2084
0
unsigned fastEmit_ISD_FNEG_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2085
0
  if (RetVT.SimpleTy != MVT::v2f32)
2086
0
    return 0;
2087
0
  if ((Subtarget->hasNEON())) {
2088
0
    return fastEmitInst_r(ARM::VNEGfd, &ARM::DPRRegClass, Op0, Op0IsKill);
2089
0
  }
2090
0
  return 0;
2091
0
}
2092
2093
0
unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2094
0
  if (RetVT.SimpleTy != MVT::v4f32)
2095
0
    return 0;
2096
0
  if ((Subtarget->hasNEON())) {
2097
0
    return fastEmitInst_r(ARM::VNEGf32q, &ARM::QPRRegClass, Op0, Op0IsKill);
2098
0
  }
2099
0
  return 0;
2100
0
}
2101
2102
unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2103
  switch (VT.SimpleTy) {
2104
  case MVT::f16: return fastEmit_ISD_FNEG_MVT_f16_r(RetVT, Op0, Op0IsKill);
2105
  case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
2106
  case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
2107
  case MVT::v4f16: return fastEmit_ISD_FNEG_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
2108
  case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
2109
  case MVT::v2f32: return fastEmit_ISD_FNEG_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
2110
  case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
2111
  default: return 0;
2112
  }
2113
}
2114
2115
// FastEmit functions for ISD::FP_EXTEND.
2116
2117
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2118
0
  if (RetVT.SimpleTy != MVT::f64)
2119
0
    return 0;
2120
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2121
0
    return fastEmitInst_r(ARM::VCVTDS, &ARM::DPRRegClass, Op0, Op0IsKill);
2122
0
  }
2123
0
  return 0;
2124
0
}
2125
2126
unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2127
  switch (VT.SimpleTy) {
2128
  case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
2129
  default: return 0;
2130
  }
2131
}
2132
2133
// FastEmit functions for ISD::FP_ROUND.
2134
2135
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2136
0
  if (RetVT.SimpleTy != MVT::f32)
2137
0
    return 0;
2138
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2139
0
    return fastEmitInst_r(ARM::VCVTSD, &ARM::SPRRegClass, Op0, Op0IsKill);
2140
0
  }
2141
0
  return 0;
2142
0
}
2143
2144
unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2145
  switch (VT.SimpleTy) {
2146
  case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
2147
  default: return 0;
2148
  }
2149
}
2150
2151
// FastEmit functions for ISD::FP_TO_SINT.
2152
2153
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2154
0
  if (RetVT.SimpleTy != MVT::v4i16)
2155
0
    return 0;
2156
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2157
0
    return fastEmitInst_r(ARM::VCVTh2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
2158
0
  }
2159
0
  return 0;
2160
0
}
2161
2162
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2163
0
  if (RetVT.SimpleTy != MVT::v8i16)
2164
0
    return 0;
2165
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2166
0
    return fastEmitInst_r(ARM::VCVTh2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
2167
0
  }
2168
0
  return 0;
2169
0
}
2170
2171
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2172
0
  if (RetVT.SimpleTy != MVT::v2i32)
2173
0
    return 0;
2174
0
  if ((Subtarget->hasNEON())) {
2175
0
    return fastEmitInst_r(ARM::VCVTf2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
2176
0
  }
2177
0
  return 0;
2178
0
}
2179
2180
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2181
0
  if (RetVT.SimpleTy != MVT::v4i32)
2182
0
    return 0;
2183
0
  if ((Subtarget->hasNEON())) {
2184
0
    return fastEmitInst_r(ARM::VCVTf2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
2185
0
  }
2186
0
  return 0;
2187
0
}
2188
2189
6
unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2190
6
  switch (VT.SimpleTy) {
2191
6
  
case MVT::v4f16: return fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill)0
;
2192
6
  
case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill)0
;
2193
6
  
case MVT::v2f32: return fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill)0
;
2194
6
  
case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill)0
;
2195
6
  default: return 0;
2196
6
  }
2197
6
}
2198
2199
// FastEmit functions for ISD::FP_TO_UINT.
2200
2201
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2202
0
  if (RetVT.SimpleTy != MVT::v4i16)
2203
0
    return 0;
2204
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2205
0
    return fastEmitInst_r(ARM::VCVTh2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
2206
0
  }
2207
0
  return 0;
2208
0
}
2209
2210
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2211
0
  if (RetVT.SimpleTy != MVT::v8i16)
2212
0
    return 0;
2213
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2214
0
    return fastEmitInst_r(ARM::VCVTh2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
2215
0
  }
2216
0
  return 0;
2217
0
}
2218
2219
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2220
0
  if (RetVT.SimpleTy != MVT::v2i32)
2221
0
    return 0;
2222
0
  if ((Subtarget->hasNEON())) {
2223
0
    return fastEmitInst_r(ARM::VCVTf2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
2224
0
  }
2225
0
  return 0;
2226
0
}
2227
2228
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2229
0
  if (RetVT.SimpleTy != MVT::v4i32)
2230
0
    return 0;
2231
0
  if ((Subtarget->hasNEON())) {
2232
0
    return fastEmitInst_r(ARM::VCVTf2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
2233
0
  }
2234
0
  return 0;
2235
0
}
2236
2237
unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2238
  switch (VT.SimpleTy) {
2239
  case MVT::v4f16: return fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
2240
  case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
2241
  case MVT::v2f32: return fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
2242
  case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
2243
  default: return 0;
2244
  }
2245
}
2246
2247
// FastEmit functions for ISD::FRINT.
2248
2249
0
unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2250
0
  if (RetVT.SimpleTy != MVT::f32)
2251
0
    return 0;
2252
0
  if ((Subtarget->hasFPARMv8())) {
2253
0
    return fastEmitInst_r(ARM::VRINTXS, &ARM::SPRRegClass, Op0, Op0IsKill);
2254
0
  }
2255
0
  return 0;
2256
0
}
2257
2258
0
unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2259
0
  if (RetVT.SimpleTy != MVT::f64)
2260
0
    return 0;
2261
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2262
0
    return fastEmitInst_r(ARM::VRINTXD, &ARM::DPRRegClass, Op0, Op0IsKill);
2263
0
  }
2264
0
  return 0;
2265
0
}
2266
2267
unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2268
  switch (VT.SimpleTy) {
2269
  case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
2270
  case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
2271
  default: return 0;
2272
  }
2273
}
2274
2275
// FastEmit functions for ISD::FROUND.
2276
2277
0
unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2278
0
  if (RetVT.SimpleTy != MVT::f32)
2279
0
    return 0;
2280
0
  if ((Subtarget->hasFPARMv8())) {
2281
0
    return fastEmitInst_r(ARM::VRINTAS, &ARM::SPRRegClass, Op0, Op0IsKill);
2282
0
  }
2283
0
  return 0;
2284
0
}
2285
2286
0
unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2287
0
  if (RetVT.SimpleTy != MVT::f64)
2288
0
    return 0;
2289
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2290
0
    return fastEmitInst_r(ARM::VRINTAD, &ARM::DPRRegClass, Op0, Op0IsKill);
2291
0
  }
2292
0
  return 0;
2293
0
}
2294
2295
unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2296
  switch (VT.SimpleTy) {
2297
  case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
2298
  case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
2299
  default: return 0;
2300
  }
2301
}
2302
2303
// FastEmit functions for ISD::FSQRT.
2304
2305
0
unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2306
0
  if (RetVT.SimpleTy != MVT::f32)
2307
0
    return 0;
2308
0
  if ((Subtarget->hasVFP2())) {
2309
0
    return fastEmitInst_r(ARM::VSQRTS, &ARM::SPRRegClass, Op0, Op0IsKill);
2310
0
  }
2311
0
  return 0;
2312
0
}
2313
2314
0
unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2315
0
  if (RetVT.SimpleTy != MVT::f64)
2316
0
    return 0;
2317
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2318
0
    return fastEmitInst_r(ARM::VSQRTD, &ARM::DPRRegClass, Op0, Op0IsKill);
2319
0
  }
2320
0
  return 0;
2321
0
}
2322
2323
unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2324
  switch (VT.SimpleTy) {
2325
  case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
2326
  case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
2327
  default: return 0;
2328
  }
2329
}
2330
2331
// FastEmit functions for ISD::FTRUNC.
2332
2333
0
unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2334
0
  if (RetVT.SimpleTy != MVT::f32)
2335
0
    return 0;
2336
0
  if ((Subtarget->hasFPARMv8())) {
2337
0
    return fastEmitInst_r(ARM::VRINTZS, &ARM::SPRRegClass, Op0, Op0IsKill);
2338
0
  }
2339
0
  return 0;
2340
0
}
2341
2342
0
unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2343
0
  if (RetVT.SimpleTy != MVT::f64)
2344
0
    return 0;
2345
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2346
0
    return fastEmitInst_r(ARM::VRINTZD, &ARM::DPRRegClass, Op0, Op0IsKill);
2347
0
  }
2348
0
  return 0;
2349
0
}
2350
2351
unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2352
  switch (VT.SimpleTy) {
2353
  case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
2354
  case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
2355
  default: return 0;
2356
  }
2357
}
2358
2359
// FastEmit functions for ISD::SIGN_EXTEND.
2360
2361
0
unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2362
0
  if (RetVT.SimpleTy != MVT::v8i16)
2363
0
    return 0;
2364
0
  if ((Subtarget->hasNEON())) {
2365
0
    return fastEmitInst_r(ARM::VMOVLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
2366
0
  }
2367
0
  return 0;
2368
0
}
2369
2370
0
unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2371
0
  if (RetVT.SimpleTy != MVT::v4i32)
2372
0
    return 0;
2373
0
  if ((Subtarget->hasNEON())) {
2374
0
    return fastEmitInst_r(ARM::VMOVLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
2375
0
  }
2376
0
  return 0;
2377
0
}
2378
2379
0
unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2380
0
  if (RetVT.SimpleTy != MVT::v2i64)
2381
0
    return 0;
2382
0
  if ((Subtarget->hasNEON())) {
2383
0
    return fastEmitInst_r(ARM::VMOVLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
2384
0
  }
2385
0
  return 0;
2386
0
}
2387
2388
1
unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2389
1
  switch (VT.SimpleTy) {
2390
1
  
case MVT::v8i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill)0
;
2391
1
  
case MVT::v4i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill)0
;
2392
1
  
case MVT::v2i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill)0
;
2393
1
  default: return 0;
2394
1
  }
2395
1
}
2396
2397
// FastEmit functions for ISD::SINT_TO_FP.
2398
2399
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2400
0
  if (RetVT.SimpleTy != MVT::v4f16)
2401
0
    return 0;
2402
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2403
0
    return fastEmitInst_r(ARM::VCVTs2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
2404
0
  }
2405
0
  return 0;
2406
0
}
2407
2408
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2409
0
  if (RetVT.SimpleTy != MVT::v8f16)
2410
0
    return 0;
2411
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2412
0
    return fastEmitInst_r(ARM::VCVTs2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
2413
0
  }
2414
0
  return 0;
2415
0
}
2416
2417
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2418
0
  if (RetVT.SimpleTy != MVT::v2f32)
2419
0
    return 0;
2420
0
  if ((Subtarget->hasNEON())) {
2421
0
    return fastEmitInst_r(ARM::VCVTs2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
2422
0
  }
2423
0
  return 0;
2424
0
}
2425
2426
2
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2427
2
  if (RetVT.SimpleTy != MVT::v4f32)
2428
0
    return 0;
2429
2
  if ((Subtarget->hasNEON())) {
2430
2
    return fastEmitInst_r(ARM::VCVTs2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
2431
2
  }
2432
0
  return 0;
2433
0
}
2434
2435
9
unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2436
9
  switch (VT.SimpleTy) {
2437
9
  
case MVT::v4i16: return fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill)0
;
2438
9
  
case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill)0
;
2439
9
  
case MVT::v2i32: return fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill)0
;
2440
9
  
case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill)2
;
2441
9
  
default: return 07
;
2442
9
  }
2443
9
}
2444
2445
// FastEmit functions for ISD::TRUNCATE.
2446
2447
0
unsigned fastEmit_ISD_TRUNCATE_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2448
0
  if (RetVT.SimpleTy != MVT::v8i8)
2449
0
    return 0;
2450
0
  if ((Subtarget->hasNEON())) {
2451
0
    return fastEmitInst_r(ARM::VMOVNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
2452
0
  }
2453
0
  return 0;
2454
0
}
2455
2456
0
unsigned fastEmit_ISD_TRUNCATE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2457
0
  if (RetVT.SimpleTy != MVT::v4i16)
2458
0
    return 0;
2459
0
  if ((Subtarget->hasNEON())) {
2460
0
    return fastEmitInst_r(ARM::VMOVNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
2461
0
  }
2462
0
  return 0;
2463
0
}
2464
2465
0
unsigned fastEmit_ISD_TRUNCATE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2466
0
  if (RetVT.SimpleTy != MVT::v2i32)
2467
0
    return 0;
2468
0
  if ((Subtarget->hasNEON())) {
2469
0
    return fastEmitInst_r(ARM::VMOVNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
2470
0
  }
2471
0
  return 0;
2472
0
}
2473
2474
unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2475
  switch (VT.SimpleTy) {
2476
  case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
2477
  case MVT::v4i32: return fastEmit_ISD_TRUNCATE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
2478
  case MVT::v2i64: return fastEmit_ISD_TRUNCATE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
2479
  default: return 0;
2480
  }
2481
}
2482
2483
// FastEmit functions for ISD::UINT_TO_FP.
2484
2485
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2486
0
  if (RetVT.SimpleTy != MVT::v4f16)
2487
0
    return 0;
2488
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2489
0
    return fastEmitInst_r(ARM::VCVTu2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
2490
0
  }
2491
0
  return 0;
2492
0
}
2493
2494
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2495
0
  if (RetVT.SimpleTy != MVT::v8f16)
2496
0
    return 0;
2497
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2498
0
    return fastEmitInst_r(ARM::VCVTu2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
2499
0
  }
2500
0
  return 0;
2501
0
}
2502
2503
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2504
0
  if (RetVT.SimpleTy != MVT::v2f32)
2505
0
    return 0;
2506
0
  if ((Subtarget->hasNEON())) {
2507
0
    return fastEmitInst_r(ARM::VCVTu2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
2508
0
  }
2509
0
  return 0;
2510
0
}
2511
2512
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2513
0
  if (RetVT.SimpleTy != MVT::v4f32)
2514
0
    return 0;
2515
0
  if ((Subtarget->hasNEON())) {
2516
0
    return fastEmitInst_r(ARM::VCVTu2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
2517
0
  }
2518
0
  return 0;
2519
0
}
2520
2521
unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2522
  switch (VT.SimpleTy) {
2523
  case MVT::v4i16: return fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
2524
  case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
2525
  case MVT::v2i32: return fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
2526
  case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
2527
  default: return 0;
2528
  }
2529
}
2530
2531
// FastEmit functions for ISD::ZERO_EXTEND.
2532
2533
0
unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2534
0
  if (RetVT.SimpleTy != MVT::v8i16)
2535
0
    return 0;
2536
0
  if ((Subtarget->hasNEON())) {
2537
0
    return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
2538
0
  }
2539
0
  return 0;
2540
0
}
2541
2542
0
unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2543
0
  if (RetVT.SimpleTy != MVT::v4i32)
2544
0
    return 0;
2545
0
  if ((Subtarget->hasNEON())) {
2546
0
    return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
2547
0
  }
2548
0
  return 0;
2549
0
}
2550
2551
0
unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2552
0
  if (RetVT.SimpleTy != MVT::v2i64)
2553
0
    return 0;
2554
0
  if ((Subtarget->hasNEON())) {
2555
0
    return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
2556
0
  }
2557
0
  return 0;
2558
0
}
2559
2560
unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2561
  switch (VT.SimpleTy) {
2562
  case MVT::v8i8: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
2563
  case MVT::v4i16: return fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
2564
  case MVT::v2i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
2565
  default: return 0;
2566
  }
2567
}
2568
2569
// Top-level FastEmit function.
2570
2571
99
unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
2572
99
  switch (Opcode) {
2573
99
  
case ARMISD::CALL: return fastEmit_ARMISD_CALL_r(VT, RetVT, Op0, Op0IsKill)0
;
2574
99
  
case ARMISD::CALL_NOLINK: return fastEmit_ARMISD_CALL_NOLINK_r(VT, RetVT, Op0, Op0IsKill)0
;
2575
99
  
case ARMISD::CALL_PRED: return fastEmit_ARMISD_CALL_PRED_r(VT, RetVT, Op0, Op0IsKill)0
;
2576
99
  
case ARMISD::RRX: return fastEmit_ARMISD_RRX_r(VT, RetVT, Op0, Op0IsKill)0
;
2577
99
  
case ARMISD::SRA_FLAG: return fastEmit_ARMISD_SRA_FLAG_r(VT, RetVT, Op0, Op0IsKill)0
;
2578
99
  
case ARMISD::SRL_FLAG: return fastEmit_ARMISD_SRL_FLAG_r(VT, RetVT, Op0, Op0IsKill)0
;
2579
99
  
case ARMISD::TC_RETURN: return fastEmit_ARMISD_TC_RETURN_r(VT, RetVT, Op0, Op0IsKill)0
;
2580
99
  
case ARMISD::VCEQZ: return fastEmit_ARMISD_VCEQZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2581
99
  
case ARMISD::VCGEZ: return fastEmit_ARMISD_VCGEZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2582
99
  
case ARMISD::VCGTZ: return fastEmit_ARMISD_VCGTZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2583
99
  
case ARMISD::VCLEZ: return fastEmit_ARMISD_VCLEZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2584
99
  
case ARMISD::VCLTZ: return fastEmit_ARMISD_VCLTZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2585
99
  
case ARMISD::VDUP: return fastEmit_ARMISD_VDUP_r(VT, RetVT, Op0, Op0IsKill)0
;
2586
99
  
case ARMISD::VMOVSR: return fastEmit_ARMISD_VMOVSR_r(VT, RetVT, Op0, Op0IsKill)0
;
2587
99
  
case ARMISD::VMOVhr: return fastEmit_ARMISD_VMOVhr_r(VT, RetVT, Op0, Op0IsKill)0
;
2588
99
  
case ARMISD::VMOVrh: return fastEmit_ARMISD_VMOVrh_r(VT, RetVT, Op0, Op0IsKill)0
;
2589
99
  
case ARMISD::VREV16: return fastEmit_ARMISD_VREV16_r(VT, RetVT, Op0, Op0IsKill)0
;
2590
99
  
case ARMISD::VREV32: return fastEmit_ARMISD_VREV32_r(VT, RetVT, Op0, Op0IsKill)0
;
2591
99
  
case ARMISD::VREV64: return fastEmit_ARMISD_VREV64_r(VT, RetVT, Op0, Op0IsKill)0
;
2592
99
  
case ARMISD::WIN__DBZCHK: return fastEmit_ARMISD_WIN__DBZCHK_r(VT, RetVT, Op0, Op0IsKill)0
;
2593
99
  
case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0, Op0IsKill)0
;
2594
99
  
case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
2595
99
  
case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill)83
;
2596
99
  
case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill)0
;
2597
99
  
case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill)0
;
2598
99
  
case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill)0
;
2599
99
  
case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill)0
;
2600
99
  
case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill)0
;
2601
99
  
case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill)0
;
2602
99
  
case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill)0
;
2603
99
  
case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill)0
;
2604
99
  
case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill)0
;
2605
99
  
case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill)0
;
2606
99
  
case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
2607
99
  
case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill)0
;
2608
99
  
case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill)6
;
2609
99
  
case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill)0
;
2610
99
  
case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill)0
;
2611
99
  
case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill)0
;
2612
99
  
case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill)0
;
2613
99
  
case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill)0
;
2614
99
  
case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill)1
;
2615
99
  
case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)9
;
2616
99
  
case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill)0
;
2617
99
  
case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)0
;
2618
99
  
case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
2619
99
  
default: return 00
;
2620
99
  }
2621
99
}
2622
2623
// FastEmit functions for ARMISD::CMP.
2624
2625
0
unsigned fastEmit_ARMISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2626
0
  if (RetVT.SimpleTy != MVT::isVoid)
2627
0
    return 0;
2628
0
  if ((Subtarget->isThumb2())) {
2629
0
    return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2630
0
  }
2631
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
2632
0
    return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2633
0
  }
2634
0
  if ((!Subtarget->isThumb())) {
2635
0
    return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2636
0
  }
2637
0
  return 0;
2638
0
}
2639
2640
unsigned fastEmit_ARMISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2641
  switch (VT.SimpleTy) {
2642
  case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2643
  default: return 0;
2644
  }
2645
}
2646
2647
// FastEmit functions for ARMISD::CMPZ.
2648
2649
0
unsigned fastEmit_ARMISD_CMPZ_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2650
0
  if (RetVT.SimpleTy != MVT::isVoid)
2651
0
    return 0;
2652
0
  if ((Subtarget->isThumb2())) {
2653
0
    return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2654
0
  }
2655
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
2656
0
    return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2657
0
  }
2658
0
  if ((!Subtarget->isThumb())) {
2659
0
    return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2660
0
  }
2661
0
  return 0;
2662
0
}
2663
2664
unsigned fastEmit_ARMISD_CMPZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2665
  switch (VT.SimpleTy) {
2666
  case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2667
  default: return 0;
2668
  }
2669
}
2670
2671
// FastEmit functions for ARMISD::EH_SJLJ_LONGJMP.
2672
2673
0
unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2674
0
  if (RetVT.SimpleTy != MVT::isVoid)
2675
0
    return 0;
2676
0
  if ((Subtarget->isThumb()) && (Subtarget->isTargetWindows())) {
2677
0
    return fastEmitInst_rr(ARM::tInt_WIN_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2678
0
  }
2679
0
  if ((!Subtarget->isTargetWindows()) && (Subtarget->isThumb())) {
2680
0
    return fastEmitInst_rr(ARM::tInt_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2681
0
  }
2682
0
  if ((!Subtarget->isThumb())) {
2683
0
    return fastEmitInst_rr(ARM::Int_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2684
0
  }
2685
0
  return 0;
2686
0
}
2687
2688
unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2689
  switch (VT.SimpleTy) {
2690
  case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2691
  default: return 0;
2692
  }
2693
}
2694
2695
// FastEmit functions for ARMISD::EH_SJLJ_SETJMP.
2696
2697
0
unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2698
0
  if (RetVT.SimpleTy != MVT::i32)
2699
0
    return 0;
2700
0
  if ((Subtarget->isThumb2()) && (!Subtarget->hasVFP2())) {
2701
0
    return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp_nofp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2702
0
  }
2703
0
  if ((Subtarget->hasVFP2()) && (Subtarget->isThumb2())) {
2704
0
    return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2705
0
  }
2706
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
2707
0
    return fastEmitInst_rr(ARM::tInt_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2708
0
  }
2709
0
  if ((!Subtarget->isThumb()) && (!Subtarget->hasVFP2())) {
2710
0
    return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp_nofp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2711
0
  }
2712
0
  if ((Subtarget->hasVFP2()) && (!Subtarget->isThumb())) {
2713
0
    return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2714
0
  }
2715
0
  return 0;
2716
0
}
2717
2718
unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2719
  switch (VT.SimpleTy) {
2720
  case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2721
  default: return 0;
2722
  }
2723
}
2724
2725
// FastEmit functions for ARMISD::SMULWB.
2726
2727
0
unsigned fastEmit_ARMISD_SMULWB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2728
0
  if (RetVT.SimpleTy != MVT::i32)
2729
0
    return 0;
2730
0
  if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
2731
0
    return fastEmitInst_rr(ARM::t2SMULWB, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2732
0
  }
2733
0
  if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
2734
0
    return fastEmitInst_rr(ARM::SMULWB, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2735
0
  }
2736
0
  return 0;
2737
0
}
2738
2739
unsigned fastEmit_ARMISD_SMULWB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2740
  switch (VT.SimpleTy) {
2741
  case MVT::i32: return fastEmit_ARMISD_SMULWB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2742
  default: return 0;
2743
  }
2744
}
2745
2746
// FastEmit functions for ARMISD::SMULWT.
2747
2748
0
unsigned fastEmit_ARMISD_SMULWT_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2749
0
  if (RetVT.SimpleTy != MVT::i32)
2750
0
    return 0;
2751
0
  if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
2752
0
    return fastEmitInst_rr(ARM::t2SMULWT, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2753
0
  }
2754
0
  if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
2755
0
    return fastEmitInst_rr(ARM::SMULWT, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2756
0
  }
2757
0
  return 0;
2758
0
}
2759
2760
unsigned fastEmit_ARMISD_SMULWT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2761
  switch (VT.SimpleTy) {
2762
  case MVT::i32: return fastEmit_ARMISD_SMULWT_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2763
  default: return 0;
2764
  }
2765
}
2766
2767
// FastEmit functions for ARMISD::VCEQ.
2768
2769
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2770
0
  if (RetVT.SimpleTy != MVT::v8i8)
2771
0
    return 0;
2772
0
  if ((Subtarget->hasNEON())) {
2773
0
    return fastEmitInst_rr(ARM::VCEQv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2774
0
  }
2775
0
  return 0;
2776
0
}
2777
2778
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2779
0
  if (RetVT.SimpleTy != MVT::v16i8)
2780
0
    return 0;
2781
0
  if ((Subtarget->hasNEON())) {
2782
0
    return fastEmitInst_rr(ARM::VCEQv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2783
0
  }
2784
0
  return 0;
2785
0
}
2786
2787
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2788
0
  if (RetVT.SimpleTy != MVT::v4i16)
2789
0
    return 0;
2790
0
  if ((Subtarget->hasNEON())) {
2791
0
    return fastEmitInst_rr(ARM::VCEQv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2792
0
  }
2793
0
  return 0;
2794
0
}
2795
2796
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2797
0
  if (RetVT.SimpleTy != MVT::v8i16)
2798
0
    return 0;
2799
0
  if ((Subtarget->hasNEON())) {
2800
0
    return fastEmitInst_rr(ARM::VCEQv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2801
0
  }
2802
0
  return 0;
2803
0
}
2804
2805
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2806
0
  if (RetVT.SimpleTy != MVT::v2i32)
2807
0
    return 0;
2808
0
  if ((Subtarget->hasNEON())) {
2809
0
    return fastEmitInst_rr(ARM::VCEQv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2810
0
  }
2811
0
  return 0;
2812
0
}
2813
2814
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2815
0
  if (RetVT.SimpleTy != MVT::v4i32)
2816
0
    return 0;
2817
0
  if ((Subtarget->hasNEON())) {
2818
0
    return fastEmitInst_rr(ARM::VCEQv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2819
0
  }
2820
0
  return 0;
2821
0
}
2822
2823
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2824
0
  if (RetVT.SimpleTy != MVT::v4i16)
2825
0
    return 0;
2826
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2827
0
    return fastEmitInst_rr(ARM::VCEQhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2828
0
  }
2829
0
  return 0;
2830
0
}
2831
2832
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2833
0
  if (RetVT.SimpleTy != MVT::v8i16)
2834
0
    return 0;
2835
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2836
0
    return fastEmitInst_rr(ARM::VCEQhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2837
0
  }
2838
0
  return 0;
2839
0
}
2840
2841
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2842
0
  if (RetVT.SimpleTy != MVT::v2i32)
2843
0
    return 0;
2844
0
  if ((Subtarget->hasNEON())) {
2845
0
    return fastEmitInst_rr(ARM::VCEQfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2846
0
  }
2847
0
  return 0;
2848
0
}
2849
2850
0
unsigned fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2851
0
  if (RetVT.SimpleTy != MVT::v4i32)
2852
0
    return 0;
2853
0
  if ((Subtarget->hasNEON())) {
2854
0
    return fastEmitInst_rr(ARM::VCEQfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2855
0
  }
2856
0
  return 0;
2857
0
}
2858
2859
unsigned fastEmit_ARMISD_VCEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2860
  switch (VT.SimpleTy) {
2861
  case MVT::v8i8: return fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2862
  case MVT::v16i8: return fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2863
  case MVT::v4i16: return fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2864
  case MVT::v8i16: return fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2865
  case MVT::v2i32: return fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2866
  case MVT::v4i32: return fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2867
  case MVT::v4f16: return fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2868
  case MVT::v8f16: return fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2869
  case MVT::v2f32: return fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2870
  case MVT::v4f32: return fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2871
  default: return 0;
2872
  }
2873
}
2874
2875
// FastEmit functions for ARMISD::VCGE.
2876
2877
0
unsigned fastEmit_ARMISD_VCGE_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2878
0
  if (RetVT.SimpleTy != MVT::v8i8)
2879
0
    return 0;
2880
0
  if ((Subtarget->hasNEON())) {
2881
0
    return fastEmitInst_rr(ARM::VCGEsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2882
0
  }
2883
0
  return 0;
2884
0
}
2885
2886
0
unsigned fastEmit_ARMISD_VCGE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2887
0
  if (RetVT.SimpleTy != MVT::v16i8)
2888
0
    return 0;
2889
0
  if ((Subtarget->hasNEON())) {
2890
0
    return fastEmitInst_rr(ARM::VCGEsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2891
0
  }
2892
0
  return 0;
2893
0
}
2894
2895
0
unsigned fastEmit_ARMISD_VCGE_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2896
0
  if (RetVT.SimpleTy != MVT::v4i16)
2897
0
    return 0;
2898
0
  if ((Subtarget->hasNEON())) {
2899
0
    return fastEmitInst_rr(ARM::VCGEsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2900
0
  }
2901
0
  return 0;
2902
0
}
2903
2904
0
unsigned fastEmit_ARMISD_VCGE_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2905
0
  if (RetVT.SimpleTy != MVT::v8i16)
2906
0
    return 0;
2907
0
  if ((Subtarget->hasNEON())) {
2908
0
    return fastEmitInst_rr(ARM::VCGEsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2909
0
  }
2910
0
  return 0;
2911
0
}
2912
2913
0
unsigned fastEmit_ARMISD_VCGE_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2914
0
  if (RetVT.SimpleTy != MVT::v2i32)
2915
0
    return 0;
2916
0
  if ((Subtarget->hasNEON())) {
2917
0
    return fastEmitInst_rr(ARM::VCGEsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2918
0
  }
2919
0
  return 0;
2920
0
}
2921
2922
0
unsigned fastEmit_ARMISD_VCGE_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2923
0
  if (RetVT.SimpleTy != MVT::v4i32)
2924
0
    return 0;
2925
0
  if ((Subtarget->hasNEON())) {
2926
0
    return fastEmitInst_rr(ARM::VCGEsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2927
0
  }
2928
0
  return 0;
2929
0
}
2930
2931
0
unsigned fastEmit_ARMISD_VCGE_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2932
0
  if (RetVT.SimpleTy != MVT::v4i16)
2933
0
    return 0;
2934
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2935
0
    return fastEmitInst_rr(ARM::VCGEhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2936
0
  }
2937
0
  return 0;
2938
0
}
2939
2940
0
unsigned fastEmit_ARMISD_VCGE_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2941
0
  if (RetVT.SimpleTy != MVT::v8i16)
2942
0
    return 0;
2943
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2944
0
    return fastEmitInst_rr(ARM::VCGEhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2945
0
  }
2946
0
  return 0;
2947
0
}
2948
2949
0
unsigned fastEmit_ARMISD_VCGE_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2950
0
  if (RetVT.SimpleTy != MVT::v2i32)
2951
0
    return 0;
2952
0
  if ((Subtarget->hasNEON())) {
2953
0
    return fastEmitInst_rr(ARM::VCGEfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2954
0
  }
2955
0
  return 0;
2956
0
}
2957
2958
0
unsigned fastEmit_ARMISD_VCGE_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2959
0
  if (RetVT.SimpleTy != MVT::v4i32)
2960
0
    return 0;
2961
0
  if ((Subtarget->hasNEON())) {
2962
0
    return fastEmitInst_rr(ARM::VCGEfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2963
0
  }
2964
0
  return 0;
2965
0
}
2966
2967
unsigned fastEmit_ARMISD_VCGE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2968
  switch (VT.SimpleTy) {
2969
  case MVT::v8i8: return fastEmit_ARMISD_VCGE_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2970
  case MVT::v16i8: return fastEmit_ARMISD_VCGE_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2971
  case MVT::v4i16: return fastEmit_ARMISD_VCGE_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2972
  case MVT::v8i16: return fastEmit_ARMISD_VCGE_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2973
  case MVT::v2i32: return fastEmit_ARMISD_VCGE_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2974
  case MVT::v4i32: return fastEmit_ARMISD_VCGE_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2975
  case MVT::v4f16: return fastEmit_ARMISD_VCGE_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2976
  case MVT::v8f16: return fastEmit_ARMISD_VCGE_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2977
  case MVT::v2f32: return fastEmit_ARMISD_VCGE_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2978
  case MVT::v4f32: return fastEmit_ARMISD_VCGE_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2979
  default: return 0;
2980
  }
2981
}
2982
2983
// FastEmit functions for ARMISD::VCGEU.
2984
2985
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2986
0
  if (RetVT.SimpleTy != MVT::v8i8)
2987
0
    return 0;
2988
0
  if ((Subtarget->hasNEON())) {
2989
0
    return fastEmitInst_rr(ARM::VCGEuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2990
0
  }
2991
0
  return 0;
2992
0
}
2993
2994
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2995
0
  if (RetVT.SimpleTy != MVT::v16i8)
2996
0
    return 0;
2997
0
  if ((Subtarget->hasNEON())) {
2998
0
    return fastEmitInst_rr(ARM::VCGEuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2999
0
  }
3000
0
  return 0;
3001
0
}
3002
3003
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3004
0
  if (RetVT.SimpleTy != MVT::v4i16)
3005
0
    return 0;
3006
0
  if ((Subtarget->hasNEON())) {
3007
0
    return fastEmitInst_rr(ARM::VCGEuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3008
0
  }
3009
0
  return 0;
3010
0
}
3011
3012
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3013
0
  if (RetVT.SimpleTy != MVT::v8i16)
3014
0
    return 0;
3015
0
  if ((Subtarget->hasNEON())) {
3016
0
    return fastEmitInst_rr(ARM::VCGEuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3017
0
  }
3018
0
  return 0;
3019
0
}
3020
3021
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3022
0
  if (RetVT.SimpleTy != MVT::v2i32)
3023
0
    return 0;
3024
0
  if ((Subtarget->hasNEON())) {
3025
0
    return fastEmitInst_rr(ARM::VCGEuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3026
0
  }
3027
0
  return 0;
3028
0
}
3029
3030
0
unsigned fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3031
0
  if (RetVT.SimpleTy != MVT::v4i32)
3032
0
    return 0;
3033
0
  if ((Subtarget->hasNEON())) {
3034
0
    return fastEmitInst_rr(ARM::VCGEuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3035
0
  }
3036
0
  return 0;
3037
0
}
3038
3039
unsigned fastEmit_ARMISD_VCGEU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3040
  switch (VT.SimpleTy) {
3041
  case MVT::v8i8: return fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3042
  case MVT::v16i8: return fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3043
  case MVT::v4i16: return fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3044
  case MVT::v8i16: return fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3045
  case MVT::v2i32: return fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3046
  case MVT::v4i32: return fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3047
  default: return 0;
3048
  }
3049
}
3050
3051
// FastEmit functions for ARMISD::VCGT.
3052
3053
0
unsigned fastEmit_ARMISD_VCGT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3054
0
  if (RetVT.SimpleTy != MVT::v8i8)
3055
0
    return 0;
3056
0
  if ((Subtarget->hasNEON())) {
3057
0
    return fastEmitInst_rr(ARM::VCGTsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3058
0
  }
3059
0
  return 0;
3060
0
}
3061
3062
0
unsigned fastEmit_ARMISD_VCGT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3063
0
  if (RetVT.SimpleTy != MVT::v16i8)
3064
0
    return 0;
3065
0
  if ((Subtarget->hasNEON())) {
3066
0
    return fastEmitInst_rr(ARM::VCGTsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3067
0
  }
3068
0
  return 0;
3069
0
}
3070
3071
0
unsigned fastEmit_ARMISD_VCGT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3072
0
  if (RetVT.SimpleTy != MVT::v4i16)
3073
0
    return 0;
3074
0
  if ((Subtarget->hasNEON())) {
3075
0
    return fastEmitInst_rr(ARM::VCGTsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3076
0
  }
3077
0
  return 0;
3078
0
}
3079
3080
0
unsigned fastEmit_ARMISD_VCGT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3081
0
  if (RetVT.SimpleTy != MVT::v8i16)
3082
0
    return 0;
3083
0
  if ((Subtarget->hasNEON())) {
3084
0
    return fastEmitInst_rr(ARM::VCGTsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3085
0
  }
3086
0
  return 0;
3087
0
}
3088
3089
0
unsigned fastEmit_ARMISD_VCGT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3090
0
  if (RetVT.SimpleTy != MVT::v2i32)
3091
0
    return 0;
3092
0
  if ((Subtarget->hasNEON())) {
3093
0
    return fastEmitInst_rr(ARM::VCGTsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3094
0
  }
3095
0
  return 0;
3096
0
}
3097
3098
0
unsigned fastEmit_ARMISD_VCGT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3099
0
  if (RetVT.SimpleTy != MVT::v4i32)
3100
0
    return 0;
3101
0
  if ((Subtarget->hasNEON())) {
3102
0
    return fastEmitInst_rr(ARM::VCGTsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3103
0
  }
3104
0
  return 0;
3105
0
}
3106
3107
0
unsigned fastEmit_ARMISD_VCGT_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3108
0
  if (RetVT.SimpleTy != MVT::v4i16)
3109
0
    return 0;
3110
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3111
0
    return fastEmitInst_rr(ARM::VCGThd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3112
0
  }
3113
0
  return 0;
3114
0
}
3115
3116
0
unsigned fastEmit_ARMISD_VCGT_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3117
0
  if (RetVT.SimpleTy != MVT::v8i16)
3118
0
    return 0;
3119
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3120
0
    return fastEmitInst_rr(ARM::VCGThq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3121
0
  }
3122
0
  return 0;
3123
0
}
3124
3125
0
unsigned fastEmit_ARMISD_VCGT_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3126
0
  if (RetVT.SimpleTy != MVT::v2i32)
3127
0
    return 0;
3128
0
  if ((Subtarget->hasNEON())) {
3129
0
    return fastEmitInst_rr(ARM::VCGTfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3130
0
  }
3131
0
  return 0;
3132
0
}
3133
3134
0
unsigned fastEmit_ARMISD_VCGT_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3135
0
  if (RetVT.SimpleTy != MVT::v4i32)
3136
0
    return 0;
3137
0
  if ((Subtarget->hasNEON())) {
3138
0
    return fastEmitInst_rr(ARM::VCGTfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3139
0
  }
3140
0
  return 0;
3141
0
}
3142
3143
unsigned fastEmit_ARMISD_VCGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3144
  switch (VT.SimpleTy) {
3145
  case MVT::v8i8: return fastEmit_ARMISD_VCGT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3146
  case MVT::v16i8: return fastEmit_ARMISD_VCGT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3147
  case MVT::v4i16: return fastEmit_ARMISD_VCGT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3148
  case MVT::v8i16: return fastEmit_ARMISD_VCGT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3149
  case MVT::v2i32: return fastEmit_ARMISD_VCGT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3150
  case MVT::v4i32: return fastEmit_ARMISD_VCGT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3151
  case MVT::v4f16: return fastEmit_ARMISD_VCGT_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3152
  case MVT::v8f16: return fastEmit_ARMISD_VCGT_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3153
  case MVT::v2f32: return fastEmit_ARMISD_VCGT_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3154
  case MVT::v4f32: return fastEmit_ARMISD_VCGT_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3155
  default: return 0;
3156
  }
3157
}
3158
3159
// FastEmit functions for ARMISD::VCGTU.
3160
3161
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3162
0
  if (RetVT.SimpleTy != MVT::v8i8)
3163
0
    return 0;
3164
0
  if ((Subtarget->hasNEON())) {
3165
0
    return fastEmitInst_rr(ARM::VCGTuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3166
0
  }
3167
0
  return 0;
3168
0
}
3169
3170
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3171
0
  if (RetVT.SimpleTy != MVT::v16i8)
3172
0
    return 0;
3173
0
  if ((Subtarget->hasNEON())) {
3174
0
    return fastEmitInst_rr(ARM::VCGTuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3175
0
  }
3176
0
  return 0;
3177
0
}
3178
3179
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3180
0
  if (RetVT.SimpleTy != MVT::v4i16)
3181
0
    return 0;
3182
0
  if ((Subtarget->hasNEON())) {
3183
0
    return fastEmitInst_rr(ARM::VCGTuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3184
0
  }
3185
0
  return 0;
3186
0
}
3187
3188
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3189
0
  if (RetVT.SimpleTy != MVT::v8i16)
3190
0
    return 0;
3191
0
  if ((Subtarget->hasNEON())) {
3192
0
    return fastEmitInst_rr(ARM::VCGTuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3193
0
  }
3194
0
  return 0;
3195
0
}
3196
3197
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3198
0
  if (RetVT.SimpleTy != MVT::v2i32)
3199
0
    return 0;
3200
0
  if ((Subtarget->hasNEON())) {
3201
0
    return fastEmitInst_rr(ARM::VCGTuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3202
0
  }
3203
0
  return 0;
3204
0
}
3205
3206
0
unsigned fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3207
0
  if (RetVT.SimpleTy != MVT::v4i32)
3208
0
    return 0;
3209
0
  if ((Subtarget->hasNEON())) {
3210
0
    return fastEmitInst_rr(ARM::VCGTuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3211
0
  }
3212
0
  return 0;
3213
0
}
3214
3215
unsigned fastEmit_ARMISD_VCGTU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3216
  switch (VT.SimpleTy) {
3217
  case MVT::v8i8: return fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3218
  case MVT::v16i8: return fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3219
  case MVT::v4i16: return fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3220
  case MVT::v8i16: return fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3221
  case MVT::v2i32: return fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3222
  case MVT::v4i32: return fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3223
  default: return 0;
3224
  }
3225
}
3226
3227
// FastEmit functions for ARMISD::VMOVDRR.
3228
3229
0
unsigned fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3230
0
  if (RetVT.SimpleTy != MVT::f64)
3231
0
    return 0;
3232
0
  if ((Subtarget->hasVFP2())) {
3233
0
    return fastEmitInst_rr(ARM::VMOVDRR, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3234
0
  }
3235
0
  return 0;
3236
0
}
3237
3238
unsigned fastEmit_ARMISD_VMOVDRR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3239
  switch (VT.SimpleTy) {
3240
  case MVT::i32: return fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3241
  default: return 0;
3242
  }
3243
}
3244
3245
// FastEmit functions for ARMISD::VMULLs.
3246
3247
0
unsigned fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3248
0
  if (RetVT.SimpleTy != MVT::v8i16)
3249
0
    return 0;
3250
0
  if ((Subtarget->hasNEON())) {
3251
0
    return fastEmitInst_rr(ARM::VMULLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3252
0
  }
3253
0
  return 0;
3254
0
}
3255
3256
0
unsigned fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3257
0
  if (RetVT.SimpleTy != MVT::v4i32)
3258
0
    return 0;
3259
0
  if ((Subtarget->hasNEON())) {
3260
0
    return fastEmitInst_rr(ARM::VMULLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3261
0
  }
3262
0
  return 0;
3263
0
}
3264
3265
0
unsigned fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3266
0
  if (RetVT.SimpleTy != MVT::v2i64)
3267
0
    return 0;
3268
0
  if ((Subtarget->hasNEON())) {
3269
0
    return fastEmitInst_rr(ARM::VMULLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3270
0
  }
3271
0
  return 0;
3272
0
}
3273
3274
unsigned fastEmit_ARMISD_VMULLs_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3275
  switch (VT.SimpleTy) {
3276
  case MVT::v8i8: return fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3277
  case MVT::v4i16: return fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3278
  case MVT::v2i32: return fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3279
  default: return 0;
3280
  }
3281
}
3282
3283
// FastEmit functions for ARMISD::VMULLu.
3284
3285
0
unsigned fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3286
0
  if (RetVT.SimpleTy != MVT::v8i16)
3287
0
    return 0;
3288
0
  if ((Subtarget->hasNEON())) {
3289
0
    return fastEmitInst_rr(ARM::VMULLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3290
0
  }
3291
0
  return 0;
3292
0
}
3293
3294
0
unsigned fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3295
0
  if (RetVT.SimpleTy != MVT::v4i32)
3296
0
    return 0;
3297
0
  if ((Subtarget->hasNEON())) {
3298
0
    return fastEmitInst_rr(ARM::VMULLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3299
0
  }
3300
0
  return 0;
3301
0
}
3302
3303
0
unsigned fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3304
0
  if (RetVT.SimpleTy != MVT::v2i64)
3305
0
    return 0;
3306
0
  if ((Subtarget->hasNEON())) {
3307
0
    return fastEmitInst_rr(ARM::VMULLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3308
0
  }
3309
0
  return 0;
3310
0
}
3311
3312
unsigned fastEmit_ARMISD_VMULLu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3313
  switch (VT.SimpleTy) {
3314
  case MVT::v8i8: return fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3315
  case MVT::v4i16: return fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3316
  case MVT::v2i32: return fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3317
  default: return 0;
3318
  }
3319
}
3320
3321
// FastEmit functions for ARMISD::VTBL1.
3322
3323
0
unsigned fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3324
0
  if (RetVT.SimpleTy != MVT::v8i8)
3325
0
    return 0;
3326
0
  if ((Subtarget->hasNEON())) {
3327
0
    return fastEmitInst_rr(ARM::VTBL1, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3328
0
  }
3329
0
  return 0;
3330
0
}
3331
3332
unsigned fastEmit_ARMISD_VTBL1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3333
  switch (VT.SimpleTy) {
3334
  case MVT::v8i8: return fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3335
  default: return 0;
3336
  }
3337
}
3338
3339
// FastEmit functions for ARMISD::VTST.
3340
3341
0
unsigned fastEmit_ARMISD_VTST_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3342
0
  if (RetVT.SimpleTy != MVT::v8i8)
3343
0
    return 0;
3344
0
  if ((Subtarget->hasNEON())) {
3345
0
    return fastEmitInst_rr(ARM::VTSTv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3346
0
  }
3347
0
  return 0;
3348
0
}
3349
3350
0
unsigned fastEmit_ARMISD_VTST_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3351
0
  if (RetVT.SimpleTy != MVT::v16i8)
3352
0
    return 0;
3353
0
  if ((Subtarget->hasNEON())) {
3354
0
    return fastEmitInst_rr(ARM::VTSTv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3355
0
  }
3356
0
  return 0;
3357
0
}
3358
3359
0
unsigned fastEmit_ARMISD_VTST_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3360
0
  if (RetVT.SimpleTy != MVT::v4i16)
3361
0
    return 0;
3362
0
  if ((Subtarget->hasNEON())) {
3363
0
    return fastEmitInst_rr(ARM::VTSTv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3364
0
  }
3365
0
  return 0;
3366
0
}
3367
3368
0
unsigned fastEmit_ARMISD_VTST_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3369
0
  if (RetVT.SimpleTy != MVT::v8i16)
3370
0
    return 0;
3371
0
  if ((Subtarget->hasNEON())) {
3372
0
    return fastEmitInst_rr(ARM::VTSTv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3373
0
  }
3374
0
  return 0;
3375
0
}
3376
3377
0
unsigned fastEmit_ARMISD_VTST_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3378
0
  if (RetVT.SimpleTy != MVT::v2i32)
3379
0
    return 0;
3380
0
  if ((Subtarget->hasNEON())) {
3381
0
    return fastEmitInst_rr(ARM::VTSTv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3382
0
  }
3383
0
  return 0;
3384
0
}
3385
3386
0
unsigned fastEmit_ARMISD_VTST_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3387
0
  if (RetVT.SimpleTy != MVT::v4i32)
3388
0
    return 0;
3389
0
  if ((Subtarget->hasNEON())) {
3390
0
    return fastEmitInst_rr(ARM::VTSTv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3391
0
  }
3392
0
  return 0;
3393
0
}
3394
3395
unsigned fastEmit_ARMISD_VTST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3396
  switch (VT.SimpleTy) {
3397
  case MVT::v8i8: return fastEmit_ARMISD_VTST_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3398
  case MVT::v16i8: return fastEmit_ARMISD_VTST_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3399
  case MVT::v4i16: return fastEmit_ARMISD_VTST_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3400
  case MVT::v8i16: return fastEmit_ARMISD_VTST_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3401
  case MVT::v2i32: return fastEmit_ARMISD_VTST_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3402
  case MVT::v4i32: return fastEmit_ARMISD_VTST_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3403
  default: return 0;
3404
  }
3405
}
3406
3407
// FastEmit functions for ISD::ADD.
3408
3409
94
unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3410
94
  if (RetVT.SimpleTy != MVT::i32)
3411
0
    return 0;
3412
94
  if ((Subtarget->isThumb2())) {
3413
20
    return fastEmitInst_rr(ARM::t2ADDrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3414
20
  }
3415
74
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
3416
0
    return fastEmitInst_rr(ARM::tADDrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3417
0
  }
3418
74
  if ((!Subtarget->isThumb())) {
3419
74
    return fastEmitInst_rr(ARM::ADDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3420
74
  }
3421
0
  return 0;
3422
0
}
3423
3424
0
unsigned fastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3425
0
  if (RetVT.SimpleTy != MVT::v8i8)
3426
0
    return 0;
3427
0
  if ((Subtarget->hasNEON())) {
3428
0
    return fastEmitInst_rr(ARM::VADDv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3429
0
  }
3430
0
  return 0;
3431
0
}
3432
3433
0
unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3434
0
  if (RetVT.SimpleTy != MVT::v16i8)
3435
0
    return 0;
3436
0
  if ((Subtarget->hasNEON())) {
3437
0
    return fastEmitInst_rr(ARM::VADDv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3438
0
  }
3439
0
  return 0;
3440
0
}
3441
3442
0
unsigned fastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3443
0
  if (RetVT.SimpleTy != MVT::v4i16)
3444
0
    return 0;
3445
0
  if ((Subtarget->hasNEON())) {
3446
0
    return fastEmitInst_rr(ARM::VADDv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3447
0
  }
3448
0
  return 0;
3449
0
}
3450
3451
0
unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3452
0
  if (RetVT.SimpleTy != MVT::v8i16)
3453
0
    return 0;
3454
0
  if ((Subtarget->hasNEON())) {
3455
0
    return fastEmitInst_rr(ARM::VADDv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3456
0
  }
3457
0
  return 0;
3458
0
}
3459
3460
0
unsigned fastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3461
0
  if (RetVT.SimpleTy != MVT::v2i32)
3462
0
    return 0;
3463
0
  if ((Subtarget->hasNEON())) {
3464
0
    return fastEmitInst_rr(ARM::VADDv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3465
0
  }
3466
0
  return 0;
3467
0
}
3468
3469
0
unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3470
0
  if (RetVT.SimpleTy != MVT::v4i32)
3471
0
    return 0;
3472
0
  if ((Subtarget->hasNEON())) {
3473
0
    return fastEmitInst_rr(ARM::VADDv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3474
0
  }
3475
0
  return 0;
3476
0
}
3477
3478
0
unsigned fastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3479
0
  if (RetVT.SimpleTy != MVT::v1i64)
3480
0
    return 0;
3481
0
  if ((Subtarget->hasNEON())) {
3482
0
    return fastEmitInst_rr(ARM::VADDv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3483
0
  }
3484
0
  return 0;
3485
0
}
3486
3487
0
unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3488
0
  if (RetVT.SimpleTy != MVT::v2i64)
3489
0
    return 0;
3490
0
  if ((Subtarget->hasNEON())) {
3491
0
    return fastEmitInst_rr(ARM::VADDv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3492
0
  }
3493
0
  return 0;
3494
0
}
3495
3496
94
unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3497
94
  switch (VT.SimpleTy) {
3498
94
  case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3499
94
  
case MVT::v8i8: return fastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3500
94
  
case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3501
94
  
case MVT::v4i16: return fastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3502
94
  
case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3503
94
  
case MVT::v2i32: return fastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3504
94
  
case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3505
94
  
case MVT::v1i64: return fastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3506
94
  
case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3507
94
  
default: return 00
;
3508
94
  }
3509
94
}
3510
3511
// FastEmit functions for ISD::AND.
3512
3513
0
unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3514
0
  if (RetVT.SimpleTy != MVT::i32)
3515
0
    return 0;
3516
0
  if ((Subtarget->isThumb2())) {
3517
0
    return fastEmitInst_rr(ARM::t2ANDrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3518
0
  }
3519
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
3520
0
    return fastEmitInst_rr(ARM::tAND, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3521
0
  }
3522
0
  if ((!Subtarget->isThumb())) {
3523
0
    return fastEmitInst_rr(ARM::ANDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3524
0
  }
3525
0
  return 0;
3526
0
}
3527
3528
0
unsigned fastEmit_ISD_AND_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3529
0
  if (RetVT.SimpleTy != MVT::v2i32)
3530
0
    return 0;
3531
0
  if ((Subtarget->hasNEON())) {
3532
0
    return fastEmitInst_rr(ARM::VANDd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3533
0
  }
3534
0
  return 0;
3535
0
}
3536
3537
0
unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3538
0
  if (RetVT.SimpleTy != MVT::v4i32)
3539
0
    return 0;
3540
0
  if ((Subtarget->hasNEON())) {
3541
0
    return fastEmitInst_rr(ARM::VANDq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3542
0
  }
3543
0
  return 0;
3544
0
}
3545
3546
unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3547
  switch (VT.SimpleTy) {
3548
  case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3549
  case MVT::v2i32: return fastEmit_ISD_AND_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3550
  case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3551
  default: return 0;
3552
  }
3553
}
3554
3555
// FastEmit functions for ISD::FADD.
3556
3557
0
unsigned fastEmit_ISD_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3558
0
  if (RetVT.SimpleTy != MVT::f16)
3559
0
    return 0;
3560
0
  if ((Subtarget->hasFullFP16())) {
3561
0
    return fastEmitInst_rr(ARM::VADDH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3562
0
  }
3563
0
  return 0;
3564
0
}
3565
3566
17
unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3567
17
  if (RetVT.SimpleTy != MVT::f32)
3568
0
    return 0;
3569
17
  if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
3570
17
    return fastEmitInst_rr(ARM::VADDS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3571
17
  }
3572
0
  return 0;
3573
0
}
3574
3575
15
unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3576
15
  if (RetVT.SimpleTy != MVT::f64)
3577
0
    return 0;
3578
15
  if ((!Subtarget->isFPOnlySP()) && 
(Subtarget->hasVFP2())14
) {
3579
14
    return fastEmitInst_rr(ARM::VADDD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3580
14
  }
3581
1
  return 0;
3582
1
}
3583
3584
0
unsigned fastEmit_ISD_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3585
0
  if (RetVT.SimpleTy != MVT::v4f16)
3586
0
    return 0;
3587
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3588
0
    return fastEmitInst_rr(ARM::VADDhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3589
0
  }
3590
0
  return 0;
3591
0
}
3592
3593
0
unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3594
0
  if (RetVT.SimpleTy != MVT::v8f16)
3595
0
    return 0;
3596
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3597
0
    return fastEmitInst_rr(ARM::VADDhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3598
0
  }
3599
0
  return 0;
3600
0
}
3601
3602
0
unsigned fastEmit_ISD_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3603
0
  if (RetVT.SimpleTy != MVT::v2f32)
3604
0
    return 0;
3605
0
  if ((Subtarget->hasNEON())) {
3606
0
    return fastEmitInst_rr(ARM::VADDfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3607
0
  }
3608
0
  return 0;
3609
0
}
3610
3611
0
unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3612
0
  if (RetVT.SimpleTy != MVT::v4f32)
3613
0
    return 0;
3614
0
  if ((Subtarget->hasNEON())) {
3615
0
    return fastEmitInst_rr(ARM::VADDfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3616
0
  }
3617
0
  return 0;
3618
0
}
3619
3620
33
unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3621
33
  switch (VT.SimpleTy) {
3622
33
  
case MVT::f16: return fastEmit_ISD_FADD_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3623
33
  
case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)17
;
3624
33
  
case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)15
;
3625
33
  
case MVT::v4f16: return fastEmit_ISD_FADD_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3626
33
  
case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3627
33
  
case MVT::v2f32: return fastEmit_ISD_FADD_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3628
33
  
case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3629
33
  
default: return 01
;
3630
33
  }
3631
33
}
3632
3633
// FastEmit functions for ISD::FDIV.
3634
3635
0
unsigned fastEmit_ISD_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3636
0
  if (RetVT.SimpleTy != MVT::f16)
3637
0
    return 0;
3638
0
  if ((Subtarget->hasFullFP16())) {
3639
0
    return fastEmitInst_rr(ARM::VDIVH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3640
0
  }
3641
0
  return 0;
3642
0
}
3643
3644
0
unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3645
0
  if (RetVT.SimpleTy != MVT::f32)
3646
0
    return 0;
3647
0
  if ((Subtarget->hasVFP2())) {
3648
0
    return fastEmitInst_rr(ARM::VDIVS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3649
0
  }
3650
0
  return 0;
3651
0
}
3652
3653
0
unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3654
0
  if (RetVT.SimpleTy != MVT::f64)
3655
0
    return 0;
3656
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
3657
0
    return fastEmitInst_rr(ARM::VDIVD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3658
0
  }
3659
0
  return 0;
3660
0
}
3661
3662
unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3663
  switch (VT.SimpleTy) {
3664
  case MVT::f16: return fastEmit_ISD_FDIV_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3665
  case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3666
  case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3667
  default: return 0;
3668
  }
3669
}
3670
3671
// FastEmit functions for ISD::FMAXNAN.
3672
3673
0
unsigned fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3674
0
  if (RetVT.SimpleTy != MVT::v4f16)
3675
0
    return 0;
3676
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3677
0
    return fastEmitInst_rr(ARM::VMAXhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3678
0
  }
3679
0
  return 0;
3680
0
}
3681
3682
0
unsigned fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3683
0
  if (RetVT.SimpleTy != MVT::v8f16)
3684
0
    return 0;
3685
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3686
0
    return fastEmitInst_rr(ARM::VMAXhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3687
0
  }
3688
0
  return 0;
3689
0
}
3690
3691
0
unsigned fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3692
0
  if (RetVT.SimpleTy != MVT::v2f32)
3693
0
    return 0;
3694
0
  if ((Subtarget->hasNEON())) {
3695
0
    return fastEmitInst_rr(ARM::VMAXfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3696
0
  }
3697
0
  return 0;
3698
0
}
3699
3700
0
unsigned fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3701
0
  if (RetVT.SimpleTy != MVT::v4f32)
3702
0
    return 0;
3703
0
  if ((Subtarget->hasNEON())) {
3704
0
    return fastEmitInst_rr(ARM::VMAXfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3705
0
  }
3706
0
  return 0;
3707
0
}
3708
3709
unsigned fastEmit_ISD_FMAXNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3710
  switch (VT.SimpleTy) {
3711
  case MVT::v4f16: return fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3712
  case MVT::v8f16: return fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3713
  case MVT::v2f32: return fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3714
  case MVT::v4f32: return fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3715
  default: return 0;
3716
  }
3717
}
3718
3719
// FastEmit functions for ISD::FMAXNUM.
3720
3721
0
unsigned fastEmit_ISD_FMAXNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3722
0
  if (RetVT.SimpleTy != MVT::f16)
3723
0
    return 0;
3724
0
  if ((Subtarget->hasFullFP16())) {
3725
0
    return fastEmitInst_rr(ARM::VMAXNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3726
0
  }
3727
0
  return 0;
3728
0
}
3729
3730
0
unsigned fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3731
0
  if (RetVT.SimpleTy != MVT::f32)
3732
0
    return 0;
3733
0
  if ((Subtarget->hasFPARMv8())) {
3734
0
    return fastEmitInst_rr(ARM::VMAXNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3735
0
  }
3736
0
  return 0;
3737
0
}
3738
3739
0
unsigned fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3740
0
  if (RetVT.SimpleTy != MVT::f64)
3741
0
    return 0;
3742
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
3743
0
    return fastEmitInst_rr(ARM::VMAXNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3744
0
  }
3745
0
  return 0;
3746
0
}
3747
3748
0
unsigned fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3749
0
  if (RetVT.SimpleTy != MVT::v4f16)
3750
0
    return 0;
3751
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3752
0
    return fastEmitInst_rr(ARM::VMAXNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3753
0
  }
3754
0
  return 0;
3755
0
}
3756
3757
0
unsigned fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3758
0
  if (RetVT.SimpleTy != MVT::v8f16)
3759
0
    return 0;
3760
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3761
0
    return fastEmitInst_rr(ARM::VMAXNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3762
0
  }
3763
0
  return 0;
3764
0
}
3765
3766
0
unsigned fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3767
0
  if (RetVT.SimpleTy != MVT::v2f32)
3768
0
    return 0;
3769
0
  if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3770
0
    return fastEmitInst_rr(ARM::VMAXNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3771
0
  }
3772
0
  return 0;
3773
0
}
3774
3775
0
unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3776
0
  if (RetVT.SimpleTy != MVT::v4f32)
3777
0
    return 0;
3778
0
  if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3779
0
    return fastEmitInst_rr(ARM::VMAXNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3780
0
  }
3781
0
  return 0;
3782
0
}
3783
3784
unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3785
  switch (VT.SimpleTy) {
3786
  case MVT::f16: return fastEmit_ISD_FMAXNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3787
  case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3788
  case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3789
  case MVT::v4f16: return fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3790
  case MVT::v8f16: return fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3791
  case MVT::v2f32: return fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3792
  case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3793
  default: return 0;
3794
  }
3795
}
3796
3797
// FastEmit functions for ISD::FMINNAN.
3798
3799
0
unsigned fastEmit_ISD_FMINNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3800
0
  if (RetVT.SimpleTy != MVT::v4f16)
3801
0
    return 0;
3802
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3803
0
    return fastEmitInst_rr(ARM::VMINhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3804
0
  }
3805
0
  return 0;
3806
0
}
3807
3808
0
unsigned fastEmit_ISD_FMINNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3809
0
  if (RetVT.SimpleTy != MVT::v8f16)
3810
0
    return 0;
3811
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3812
0
    return fastEmitInst_rr(ARM::VMINhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3813
0
  }
3814
0
  return 0;
3815
0
}
3816
3817
0
unsigned fastEmit_ISD_FMINNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3818
0
  if (RetVT.SimpleTy != MVT::v2f32)
3819
0
    return 0;
3820
0
  if ((Subtarget->hasNEON())) {
3821
0
    return fastEmitInst_rr(ARM::VMINfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3822
0
  }
3823
0
  return 0;
3824
0
}
3825
3826
0
unsigned fastEmit_ISD_FMINNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3827
0
  if (RetVT.SimpleTy != MVT::v4f32)
3828
0
    return 0;
3829
0
  if ((Subtarget->hasNEON())) {
3830
0
    return fastEmitInst_rr(ARM::VMINfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3831
0
  }
3832
0
  return 0;
3833
0
}
3834
3835
unsigned fastEmit_ISD_FMINNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3836
  switch (VT.SimpleTy) {
3837
  case MVT::v4f16: return fastEmit_ISD_FMINNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3838
  case MVT::v8f16: return fastEmit_ISD_FMINNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3839
  case MVT::v2f32: return fastEmit_ISD_FMINNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3840
  case MVT::v4f32: return fastEmit_ISD_FMINNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3841
  default: return 0;
3842
  }
3843
}
3844
3845
// FastEmit functions for ISD::FMINNUM.
3846
3847
0
unsigned fastEmit_ISD_FMINNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3848
0
  if (RetVT.SimpleTy != MVT::f16)
3849
0
    return 0;
3850
0
  if ((Subtarget->hasFullFP16())) {
3851
0
    return fastEmitInst_rr(ARM::VMINNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3852
0
  }
3853
0
  return 0;
3854
0
}
3855
3856
0
unsigned fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3857
0
  if (RetVT.SimpleTy != MVT::f32)
3858
0
    return 0;
3859
0
  if ((Subtarget->hasFPARMv8())) {
3860
0
    return fastEmitInst_rr(ARM::VMINNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3861
0
  }
3862
0
  return 0;
3863
0
}
3864
3865
0
unsigned fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3866
0
  if (RetVT.SimpleTy != MVT::f64)
3867
0
    return 0;
3868
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
3869
0
    return fastEmitInst_rr(ARM::VMINNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3870
0
  }
3871
0
  return 0;
3872
0
}
3873
3874
0
unsigned fastEmit_ISD_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3875
0
  if (RetVT.SimpleTy != MVT::v4f16)
3876
0
    return 0;
3877
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3878
0
    return fastEmitInst_rr(ARM::VMINNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3879
0
  }
3880
0
  return 0;
3881
0
}
3882
3883
0
unsigned fastEmit_ISD_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3884
0
  if (RetVT.SimpleTy != MVT::v8f16)
3885
0
    return 0;
3886
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3887
0
    return fastEmitInst_rr(ARM::VMINNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3888
0
  }
3889
0
  return 0;
3890
0
}
3891
3892
0
unsigned fastEmit_ISD_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3893
0
  if (RetVT.SimpleTy != MVT::v2f32)
3894
0
    return 0;
3895
0
  if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3896
0
    return fastEmitInst_rr(ARM::VMINNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3897
0
  }
3898
0
  return 0;
3899
0
}
3900
3901
0
unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3902
0
  if (RetVT.SimpleTy != MVT::v4f32)
3903
0
    return 0;
3904
0
  if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3905
0
    return fastEmitInst_rr(ARM::VMINNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3906
0
  }
3907
0
  return 0;
3908
0
}
3909
3910
unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3911
  switch (VT.SimpleTy) {
3912
  case MVT::f16: return fastEmit_ISD_FMINNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3913
  case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3914
  case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3915
  case MVT::v4f16: return fastEmit_ISD_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3916
  case MVT::v8f16: return fastEmit_ISD_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3917
  case MVT::v2f32: return fastEmit_ISD_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3918
  case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3919
  default: return 0;
3920
  }
3921
}
3922
3923
// FastEmit functions for ISD::FMUL.
3924
3925
0
unsigned fastEmit_ISD_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3926
0
  if (RetVT.SimpleTy != MVT::f16)
3927
0
    return 0;
3928
0
  if ((Subtarget->hasFullFP16())) {
3929
0
    return fastEmitInst_rr(ARM::VMULH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3930
0
  }
3931
0
  return 0;
3932
0
}
3933
3934
1
unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3935
1
  if (RetVT.SimpleTy != MVT::f32)
3936
0
    return 0;
3937
1
  if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
3938
1
    return fastEmitInst_rr(ARM::VMULS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3939
1
  }
3940
0
  return 0;
3941
0
}
3942
3943
0
unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3944
0
  if (RetVT.SimpleTy != MVT::f64)
3945
0
    return 0;
3946
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
3947
0
    return fastEmitInst_rr(ARM::VMULD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3948
0
  }
3949
0
  return 0;
3950
0
}
3951
3952
0
unsigned fastEmit_ISD_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3953
0
  if (RetVT.SimpleTy != MVT::v4f16)
3954
0
    return 0;
3955
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3956
0
    return fastEmitInst_rr(ARM::VMULhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3957
0
  }
3958
0
  return 0;
3959
0
}
3960
3961
0
unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3962
0
  if (RetVT.SimpleTy != MVT::v8f16)
3963
0
    return 0;
3964
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3965
0
    return fastEmitInst_rr(ARM::VMULhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3966
0
  }
3967
0
  return 0;
3968
0
}
3969
3970
0
unsigned fastEmit_ISD_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3971
0
  if (RetVT.SimpleTy != MVT::v2f32)
3972
0
    return 0;
3973
0
  if ((Subtarget->hasNEON())) {
3974
0
    return fastEmitInst_rr(ARM::VMULfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3975
0
  }
3976
0
  return 0;
3977
0
}
3978
3979
0
unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3980
0
  if (RetVT.SimpleTy != MVT::v4f32)
3981
0
    return 0;
3982
0
  if ((Subtarget->hasNEON())) {
3983
0
    return fastEmitInst_rr(ARM::VMULfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3984
0
  }
3985
0
  return 0;
3986
0
}
3987
3988
1
unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3989
1
  switch (VT.SimpleTy) {
3990
1
  
case MVT::f16: return fastEmit_ISD_FMUL_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3991
1
  case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3992
1
  
case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3993
1
  
case MVT::v4f16: return fastEmit_ISD_FMUL_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3994
1
  
case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3995
1
  
case MVT::v2f32: return fastEmit_ISD_FMUL_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3996
1
  
case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3997
1
  
default: return 00
;
3998
1
  }
3999
1
}
4000
4001
// FastEmit functions for ISD::FSUB.
4002
4003
0
unsigned fastEmit_ISD_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4004
0
  if (RetVT.SimpleTy != MVT::f16)
4005
0
    return 0;
4006
0
  if ((Subtarget->hasFullFP16())) {
4007
0
    return fastEmitInst_rr(ARM::VSUBH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4008
0
  }
4009
0
  return 0;
4010
0
}
4011
4012
0
unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4013
0
  if (RetVT.SimpleTy != MVT::f32)
4014
0
    return 0;
4015
0
  if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
4016
0
    return fastEmitInst_rr(ARM::VSUBS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4017
0
  }
4018
0
  return 0;
4019
0
}
4020
4021
0
unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4022
0
  if (RetVT.SimpleTy != MVT::f64)
4023
0
    return 0;
4024
0
  if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
4025
0
    return fastEmitInst_rr(ARM::VSUBD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4026
0
  }
4027
0
  return 0;
4028
0
}
4029
4030
0
unsigned fastEmit_ISD_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4031
0
  if (RetVT.SimpleTy != MVT::v4f16)
4032
0
    return 0;
4033
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
4034
0
    return fastEmitInst_rr(ARM::VSUBhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4035
0
  }
4036
0
  return 0;
4037
0
}
4038
4039
0
unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4040
0
  if (RetVT.SimpleTy != MVT::v8f16)
4041
0
    return 0;
4042
0
  if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
4043
0
    return fastEmitInst_rr(ARM::VSUBhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4044
0
  }
4045
0
  return 0;
4046
0
}
4047
4048
0
unsigned fastEmit_ISD_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4049
0
  if (RetVT.SimpleTy != MVT::v2f32)
4050
0
    return 0;
4051
0
  if ((Subtarget->hasNEON())) {
4052
0
    return fastEmitInst_rr(ARM::VSUBfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4053
0
  }
4054
0
  return 0;
4055
0
}
4056
4057
0
unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4058
0
  if (RetVT.SimpleTy != MVT::v4f32)
4059
0
    return 0;
4060
0
  if ((Subtarget->hasNEON())) {
4061
0
    return fastEmitInst_rr(ARM::VSUBfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4062
0
  }
4063
0
  return 0;
4064
0
}
4065
4066
unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4067
  switch (VT.SimpleTy) {
4068
  case MVT::f16: return fastEmit_ISD_FSUB_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4069
  case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4070
  case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4071
  case MVT::v4f16: return fastEmit_ISD_FSUB_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4072
  case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4073
  case MVT::v2f32: return fastEmit_ISD_FSUB_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4074
  case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4075
  default: return 0;
4076
  }
4077
}
4078
4079
// FastEmit functions for ISD::MUL.
4080
4081
3
unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4082
3
  if (RetVT.SimpleTy != MVT::i32)
4083
0
    return 0;
4084
3
  if ((Subtarget->isThumb2())) {
4085
3
    return fastEmitInst_rr(ARM::t2MUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4086
3
  }
4087
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4088
0
    return fastEmitInst_rr(ARM::tMUL, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4089
0
  }
4090
0
  if ((!Subtarget->isThumb()) && (!Subtarget->hasV6Ops()) && (Subtarget->useMulOps())) {
4091
0
    return fastEmitInst_rr(ARM::MULv5, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4092
0
  }
4093
0
  if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
4094
0
    return fastEmitInst_rr(ARM::MUL, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4095
0
  }
4096
0
  return 0;
4097
0
}
4098
4099
0
unsigned fastEmit_ISD_MUL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4100
0
  if (RetVT.SimpleTy != MVT::v8i8)
4101
0
    return 0;
4102
0
  if ((Subtarget->hasNEON())) {
4103
0
    return fastEmitInst_rr(ARM::VMULv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4104
0
  }
4105
0
  return 0;
4106
0
}
4107
4108
0
unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4109
0
  if (RetVT.SimpleTy != MVT::v16i8)
4110
0
    return 0;
4111
0
  if ((Subtarget->hasNEON())) {
4112
0
    return fastEmitInst_rr(ARM::VMULv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4113
0
  }
4114
0
  return 0;
4115
0
}
4116
4117
0
unsigned fastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4118
0
  if (RetVT.SimpleTy != MVT::v4i16)
4119
0
    return 0;
4120
0
  if ((Subtarget->hasNEON())) {
4121
0
    return fastEmitInst_rr(ARM::VMULv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4122
0
  }
4123
0
  return 0;
4124
0
}
4125
4126
0
unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4127
0
  if (RetVT.SimpleTy != MVT::v8i16)
4128
0
    return 0;
4129
0
  if ((Subtarget->hasNEON())) {
4130
0
    return fastEmitInst_rr(ARM::VMULv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4131
0
  }
4132
0
  return 0;
4133
0
}
4134
4135
0
unsigned fastEmit_ISD_MUL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4136
0
  if (RetVT.SimpleTy != MVT::v2i32)
4137
0
    return 0;
4138
0
  if ((Subtarget->hasNEON())) {
4139
0
    return fastEmitInst_rr(ARM::VMULv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4140
0
  }
4141
0
  return 0;
4142
0
}
4143
4144
0
unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4145
0
  if (RetVT.SimpleTy != MVT::v4i32)
4146
0
    return 0;
4147
0
  if ((Subtarget->hasNEON())) {
4148
0
    return fastEmitInst_rr(ARM::VMULv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4149
0
  }
4150
0
  return 0;
4151
0
}
4152
4153
3
unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4154
3
  switch (VT.SimpleTy) {
4155
3
  case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4156
3
  
case MVT::v8i8: return fastEmit_ISD_MUL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4157
3
  
case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4158
3
  
case MVT::v4i16: return fastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4159
3
  
case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4160
3
  
case MVT::v2i32: return fastEmit_ISD_MUL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4161
3
  
case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4162
3
  
default: return 00
;
4163
3
  }
4164
3
}
4165
4166
// FastEmit functions for ISD::MULHS.
4167
4168
0
unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4169
0
  if (RetVT.SimpleTy != MVT::i32)
4170
0
    return 0;
4171
0
  if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
4172
0
    return fastEmitInst_rr(ARM::t2SMMUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4173
0
  }
4174
0
  if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
4175
0
    return fastEmitInst_rr(ARM::SMMUL, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4176
0
  }
4177
0
  return 0;
4178
0
}
4179
4180
unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4181
  switch (VT.SimpleTy) {
4182
  case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4183
  default: return 0;
4184
  }
4185
}
4186
4187
// FastEmit functions for ISD::OR.
4188
4189
3
unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4190
3
  if (RetVT.SimpleTy != MVT::i32)
4191
0
    return 0;
4192
3
  if ((Subtarget->isThumb2())) {
4193
1
    return fastEmitInst_rr(ARM::t2ORRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4194
1
  }
4195
2
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
4196
0
    return fastEmitInst_rr(ARM::tORR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4197
0
  }
4198
2
  if ((!Subtarget->isThumb())) {
4199
2
    return fastEmitInst_rr(ARM::ORRrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4200
2
  }
4201
0
  return 0;
4202
0
}
4203
4204
0
unsigned fastEmit_ISD_OR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4205
0
  if (RetVT.SimpleTy != MVT::v2i32)
4206
0
    return 0;
4207
0
  if ((Subtarget->hasNEON())) {
4208
0
    return fastEmitInst_rr(ARM::VORRd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4209
0
  }
4210
0
  return 0;
4211
0
}
4212
4213
0
unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4214
0
  if (RetVT.SimpleTy != MVT::v4i32)
4215
0
    return 0;
4216
0
  if ((Subtarget->hasNEON())) {
4217
0
    return fastEmitInst_rr(ARM::VORRq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4218
0
  }
4219
0
  return 0;
4220
0
}
4221
4222
3
unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4223
3
  switch (VT.SimpleTy) {
4224
3
  case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4225
3
  
case MVT::v2i32: return fastEmit_ISD_OR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4226
3
  
case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
4227
3
  
default: return 00
;
4228
3
  }
4229
3
}
4230
4231
// FastEmit functions for ISD::ROTR.
4232
4233
0
unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4234
0
  if (RetVT.SimpleTy != MVT::i32)
4235
0
    return 0;
4236
0
  if ((Subtarget->isThumb2())) {
4237
0
    return fastEmitInst_rr(ARM::t2RORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4238
0
  }
4239
0
  if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4240
0
    return fastEmitInst_rr(ARM::tROR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4241
0
  }
4242
0
  return 0;
4243
0
}
4244
4245
unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4246
  switch (VT.SimpleTy) {
4247
  case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4248
  default: return 0;
4249
  }
4250
}
4251
4252
// FastEmit functions for ISD::SDIV.
4253
4254
4
unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4255
4
  if (RetVT.SimpleTy != MVT::i32)
4256
0
    return 0;
4257
4
  if ((Subtarget->hasDivideInThumbMode()) && 
(Subtarget->hasV8MBaselineOps())0
&&
(Subtarget->isThumb())0
) {
4258
0
    return fastEmitInst_rr(ARM::t2SDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4259
0
  }
4260
4
  if ((Subtarget->hasDivideInARMMode()) && 
(!Subtarget->isThumb())0
) {
4261
0
    return fastEmitInst_rr(ARM::SDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4262
0
  }
4263
4
  return 0;
4264
4
}
4265
4266
4
unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4267
4
  switch (VT.SimpleTy) {
4268
4
  case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4269
4
  
default: return 00
;
4270
4
  }
4271
4
}
4272
4273
// FastEmit functions for ISD::SHL.
4274
4275
5
unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4276
5
  if (RetVT.SimpleTy != MVT::i32)
4277
0
    return 0;
4278
5
  if ((Subtarget->isThumb2())) {
4279
0
    return fastEmitInst_rr(ARM::t2LSLrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4280
0
  }
4281
5
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
4282
0
    return fastEmitInst_rr(ARM::tLSLrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4283
0
  }
4284
5
  return 0;
4285
5
}
4286
4287
5
unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4288
5
  switch (VT.SimpleTy) {
4289
5
  case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4290
5
  
default: return 00
;
4291
5
  }
4292
5
}
4293
4294
// FastEmit functions for ISD::SMAX.
4295
4296
0
unsigned fastEmit_ISD_SMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4297
0
  if (RetVT.SimpleTy != MVT::v8i8)
4298
0
    return 0;
4299
0
  if ((Subtarget->hasNEON())) {
4300
0
    return fastEmitInst_rr(ARM::VMAXsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4301
0
  }
4302
0
  return 0;
4303
0
}
4304
4305
0
unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4306
0
  if (RetVT.SimpleTy != MVT::v16i8)
4307
0
    return 0;
4308
0
  if ((Subtarget->hasNEON())) {
4309
0
    return fastEmitInst_rr(ARM::VMAXsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4310
0
  }
4311
0
  return 0;
4312
0
}
4313
4314
0
unsigned fastEmit_ISD_SMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4315
0
  if (RetVT.SimpleTy != MVT::v4i16)
4316
0
    return 0;
4317
0
  if ((Subtarget->hasNEON())) {
4318
0
    return fastEmitInst_rr(ARM::VMAXsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4319
0
  }
4320
0
  return 0;
4321
0
}
4322
4323
0
unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4324
0
  if (RetVT.SimpleTy != MVT::v8i16)
4325
0
    return 0;
4326
0
  if ((Subtarget->hasNEON())) {
4327
0
    return fastEmitInst_rr(ARM::VMAXsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4328
0
  }
4329
0
  return 0;
4330
0
}
4331
4332
0
unsigned fastEmit_ISD_SMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4333
0
  if (RetVT.SimpleTy != MVT::v2i32)
4334
0
    return 0;
4335
0
  if ((Subtarget->hasNEON())) {
4336
0
    return fastEmitInst_rr(ARM::VMAXsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4337
0
  }
4338
0
  return 0;
4339
0
}
4340
4341
0
unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4342
0
  if (RetVT.SimpleTy != MVT::v4i32)
4343
0
    return 0;
4344
0
  if ((Subtarget->hasNEON())) {
4345
0
    return fastEmitInst_rr(ARM::VMAXsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4346
0
  }
4347
0
  return 0;
4348
0
}
4349
4350
unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4351
  switch (VT.SimpleTy) {
4352
  case MVT::v8i8: return fastEmit_ISD_SMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4353
  case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4354
  case MVT::v4i16: return fastEmit_ISD_SMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4355
  case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4356
  case MVT::v2i32: return fastEmit_ISD_SMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4357
  case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4358
  default: return 0;
4359
  }
4360
}
4361
4362
// FastEmit functions for ISD::SMIN.
4363
4364
0
unsigned fastEmit_ISD_SMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4365
0
  if (RetVT.SimpleTy != MVT::v8i8)
4366
0
    return 0;
4367
0
  if ((Subtarget->hasNEON())) {
4368
0
    return fastEmitInst_rr(ARM::VMINsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4369
0
  }
4370
0
  return 0;
4371
0
}
4372
4373
0
unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4374
0
  if (RetVT.SimpleTy != MVT::v16i8)
4375
0
    return 0;
4376
0
  if ((Subtarget->hasNEON())) {
4377
0
    return fastEmitInst_rr(ARM::VMINsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4378
0
  }
4379
0
  return 0;
4380
0
}
4381
4382
0
unsigned fastEmit_ISD_SMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4383
0
  if (RetVT.SimpleTy != MVT::v4i16)
4384
0
    return 0;
4385
0
  if ((Subtarget->hasNEON())) {
4386
0
    return fastEmitInst_rr(ARM::VMINsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4387
0
  }
4388
0
  return 0;
4389
0
}
4390
4391
0
unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4392
0
  if (RetVT.SimpleTy != MVT::v8i16)
4393
0
    return 0;
4394
0
  if ((Subtarget->hasNEON())) {
4395
0
    return fastEmitInst_rr(ARM::VMINsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4396
0
  }
4397
0
  return 0;
4398
0
}
4399
4400
0
unsigned fastEmit_ISD_SMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4401
0
  if (RetVT.SimpleTy != MVT::v2i32)
4402
0
    return 0;
4403
0
  if ((Subtarget->hasNEON())) {
4404
0
    return fastEmitInst_rr(ARM::VMINsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4405
0
  }
4406
0
  return 0;
4407
0
}
4408
4409
0
unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4410
0
  if (RetVT.SimpleTy != MVT::v4i32)
4411
0
    return 0;
4412
0
  if ((Subtarget->hasNEON())) {
4413
0
    return fastEmitInst_rr(ARM::VMINsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4414
0
  }
4415
0
  return 0;
4416
0
}
4417
4418
unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4419
  switch (VT.SimpleTy) {
4420
  case MVT::v8i8: return fastEmit_ISD_SMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4421
  case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4422
  case MVT::v4i16: return fastEmit_ISD_SMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4423
  case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4424
  case MVT::v2i32: return fastEmit_ISD_SMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4425
  case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4426
  default: return 0;
4427
  }
4428
}
4429
4430
// FastEmit functions for ISD::SRA.
4431
4432
4
unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4433
4
  if (RetVT.SimpleTy != MVT::i32)
4434
0
    return 0;
4435
4
  if ((Subtarget->isThumb2())) {
4436
0
    return fastEmitInst_rr(ARM::t2ASRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4437
0
  }
4438
4
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
4439
0
    return fastEmitInst_rr(ARM::tASRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4440
0
  }
4441
4
  return 0;
4442
4
}
4443
4444
4
unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4445
4
  switch (VT.SimpleTy) {
4446
4
  case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4447
4
  
default: return 00
;
4448
4
  }
4449
4
}
4450
4451
// FastEmit functions for ISD::SRL.
4452
4453
6
unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4454
6
  if (RetVT.SimpleTy != MVT::i32)
4455
0
    return 0;
4456
6
  if ((Subtarget->isThumb2())) {
4457
2
    return fastEmitInst_rr(ARM::t2LSRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4458
2
  }
4459
4
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
4460
0
    return fastEmitInst_rr(ARM::tLSRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4461
0
  }
4462
4
  return 0;
4463
4
}
4464
4465
6
unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4466
6
  switch (VT.SimpleTy) {
4467
6
  case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4468
6
  
default: return 00
;
4469
6
  }
4470
6
}
4471
4472
// FastEmit functions for ISD::SUB.
4473
4474
3
unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4475
3
  if (RetVT.SimpleTy != MVT::i32)
4476
0
    return 0;
4477
3
  if ((Subtarget->isThumb2())) {
4478
1
    return fastEmitInst_rr(ARM::t2SUBrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4479
1
  }
4480
2
  if ((Subtarget->isThumb()) && 
(Subtarget->isThumb1Only())0
) {
4481
0
    return fastEmitInst_rr(ARM::tSUBrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4482
0
  }
4483
2
  if ((!Subtarget->isThumb())) {
4484
2
    return fastEmitInst_rr(ARM::SUBrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4485
2
  }
4486
0
  return 0;
4487
0
}
4488
4489
0
unsigned fastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4490
0
  if (RetVT.SimpleTy != MVT::v8i8)
4491
0
    return 0;
4492
0
  if ((Subtarget->hasNEON())) {
4493
0
    return fastEmitInst_rr(ARM::VSUBv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4494
0
  }
4495
0
  return 0;
4496
0
}
4497
4498
0
unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4499
0
  if (RetVT.SimpleTy != MVT::v16i8)
4500
0
    return 0;
4501
0
  if ((Subtarget->hasNEON())) {
4502
0
    return fastEmitInst_rr(ARM::VSUBv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4503
0
  }
4504
0
  return 0;
4505
0
}
4506
4507
0
unsigned fastEmit_ISD_SUB_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4508
0
  if (RetVT.SimpleTy != MVT::v4i16)
4509
0
    return 0;
4510
0
  if ((Subtarget->hasNEON())) {
4511
0
    return fastEmitInst_rr(ARM::VSUBv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4512
0
  }
4513
0
  return 0;
4514
0
}
4515
4516
0
unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4517
0
  if (RetVT.SimpleTy != MVT::v8i16)
4518
0
    return 0;
4519
0
  if ((Subtarget->hasNEON())) {
4520
0
    return fastEmitInst_rr(ARM::VSUBv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4521
0
  }
4522
0
  return 0;
4523
0
}
4524
4525
0
unsigned fastEmit_ISD_SUB_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4526
0
  if (RetVT.SimpleTy != MVT::v2i32)
4527
0
    return 0;
4528
0
  if ((Subtarget->hasNEON())) {
4529
0
    return fastEmitInst_rr(ARM::VSUBv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4530
0
  }
4531
0
  return 0;
4532
0
}
4533
4534
0
unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4535
0
  if (RetVT.SimpleTy != MVT::v4i32)
4536
0
    return 0;
4537
0
  if ((Subtarget->hasNEON())) {
4538
0
    return fastEmitInst_rr(ARM::VSUBv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4539
0
  }
4540
0
  return 0;
4541
0
}
4542
4543
0
unsigned fastEmit_ISD_SUB_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)