Coverage Report

Created: 2019-03-22 08:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenGlobalISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the ARM target                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 64;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(0),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_NoHonorSignDependentRoundingBit = 57,
37
  Feature_HasV4TBit = 6,
38
  Feature_NoV4TBit = 7,
39
  Feature_HasV5TBit = 8,
40
  Feature_NoV5TBit = 54,
41
  Feature_HasV5TEBit = 12,
42
  Feature_HasV6Bit = 0,
43
  Feature_NoV6Bit = 10,
44
  Feature_HasV6MBit = 29,
45
  Feature_HasV8MBaselineBit = 33,
46
  Feature_HasV6T2Bit = 9,
47
  Feature_HasV6KBit = 19,
48
  Feature_HasV7Bit = 3,
49
  Feature_HasV8Bit = 15,
50
  Feature_PreV8Bit = 20,
51
  Feature_HasV8_1aBit = 59,
52
  Feature_NoVFPBit = 23,
53
  Feature_HasVFP2Bit = 22,
54
  Feature_HasVFP3Bit = 46,
55
  Feature_HasVFP4Bit = 44,
56
  Feature_HasDPVFPBit = 39,
57
  Feature_HasFPARMv8Bit = 41,
58
  Feature_HasNEONBit = 47,
59
  Feature_HasCryptoBit = 48,
60
  Feature_HasDotProdBit = 49,
61
  Feature_HasCRCBit = 14,
62
  Feature_HasFP16Bit = 53,
63
  Feature_HasFullFP16Bit = 38,
64
  Feature_HasDivideInThumbBit = 35,
65
  Feature_HasDivideInARMBit = 13,
66
  Feature_HasDSPBit = 34,
67
  Feature_HasDBBit = 16,
68
  Feature_HasV7ClrexBit = 18,
69
  Feature_HasAcquireReleaseBit = 17,
70
  Feature_HasMPBit = 2,
71
  Feature_HasZCZBit = 50,
72
  Feature_UseNEONForFPBit = 62,
73
  Feature_DontUseNEONForFPBit = 40,
74
  Feature_IsThumbBit = 27,
75
  Feature_IsThumb1OnlyBit = 28,
76
  Feature_IsThumb2Bit = 32,
77
  Feature_IsNotMClassBit = 36,
78
  Feature_IsARMBit = 1,
79
  Feature_IsWindowsBit = 30,
80
  Feature_IsNotWindowsBit = 31,
81
  Feature_IsReadTPHardBit = 55,
82
  Feature_IsReadTPSoftBit = 21,
83
  Feature_UseNaClTrapBit = 4,
84
  Feature_DontUseNaClTrapBit = 5,
85
  Feature_UseMovtBit = 37,
86
  Feature_DontUseMovtBit = 24,
87
  Feature_UseMovtInPicBit = 25,
88
  Feature_DontUseMovtInPicBit = 26,
89
  Feature_UseFPVMLxBit = 43,
90
  Feature_UseMulOpsBit = 11,
91
  Feature_UseFusedMACBit = 45,
92
  Feature_HasFastVGETLNi32Bit = 51,
93
  Feature_HasSlowVGETLNi32Bit = 60,
94
  Feature_HasFastVDUP32Bit = 52,
95
  Feature_HasSlowVDUP32Bit = 61,
96
  Feature_UseVMOVSRBit = 42,
97
  Feature_DontUseVMOVSRBit = 63,
98
  Feature_IsLEBit = 56,
99
  Feature_IsBEBit = 58,
100
};
101
102
PredicateBitset ARMInstructionSelector::
103
7.09k
computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
104
7.09k
  PredicateBitset Features;
105
7.09k
  if (!TM.Options.HonorSignDependentRoundingFPMath())
106
7.02k
    Features[Feature_NoHonorSignDependentRoundingBit] = 1;
107
7.09k
  if (Subtarget->hasV4TOps())
108
6.02k
    Features[Feature_HasV4TBit] = 1;
109
7.09k
  if (!Subtarget->hasV4TOps())
110
1.07k
    Features[Feature_NoV4TBit] = 1;
111
7.09k
  if (Subtarget->hasV5TOps())
112
5.77k
    Features[Feature_HasV5TBit] = 1;
113
7.09k
  if (!Subtarget->hasV5TOps())
114
1.32k
    Features[Feature_NoV5TBit] = 1;
115
7.09k
  if (Subtarget->hasV5TEOps())
116
5.72k
    Features[Feature_HasV5TEBit] = 1;
117
7.09k
  if (Subtarget->hasV6Ops())
118
5.69k
    Features[Feature_HasV6Bit] = 1;
119
7.09k
  if (!Subtarget->hasV6Ops())
120
1.40k
    Features[Feature_NoV6Bit] = 1;
121
7.09k
  if (Subtarget->hasV6MOps())
122
5.42k
    Features[Feature_HasV6MBit] = 1;
123
7.09k
  if (Subtarget->hasV8MBaselineOps())
124
5.03k
    Features[Feature_HasV8MBaselineBit] = 1;
125
7.09k
  if (Subtarget->hasV6T2Ops())
126
4.95k
    Features[Feature_HasV6T2Bit] = 1;
127
7.09k
  if (Subtarget->hasV6KOps())
128
4.98k
    Features[Feature_HasV6KBit] = 1;
129
7.09k
  if (Subtarget->hasV7Ops())
130
4.67k
    Features[Feature_HasV7Bit] = 1;
131
7.09k
  if (Subtarget->hasV8Ops())
132
364
    Features[Feature_HasV8Bit] = 1;
133
7.09k
  if (!Subtarget->hasV8Ops())
134
6.73k
    Features[Feature_PreV8Bit] = 1;
135
7.09k
  if (Subtarget->hasV8_1aOps())
136
46
    Features[Feature_HasV8_1aBit] = 1;
137
7.09k
  if (!Subtarget->hasVFP2())
138
2.79k
    Features[Feature_NoVFPBit] = 1;
139
7.09k
  if (Subtarget->hasVFP2())
140
4.30k
    Features[Feature_HasVFP2Bit] = 1;
141
7.09k
  if (Subtarget->hasVFP3())
142
4.13k
    Features[Feature_HasVFP3Bit] = 1;
143
7.09k
  if (Subtarget->hasVFP4())
144
1.64k
    Features[Feature_HasVFP4Bit] = 1;
145
7.09k
  if (!Subtarget->isFPOnlySP())
146
6.76k
    Features[Feature_HasDPVFPBit] = 1;
147
7.09k
  if (Subtarget->hasFPARMv8())
148
528
    Features[Feature_HasFPARMv8Bit] = 1;
149
7.09k
  if (Subtarget->hasNEON())
150
3.65k
    Features[Feature_HasNEONBit] = 1;
151
7.09k
  if (Subtarget->hasCrypto())
152
319
    Features[Feature_HasCryptoBit] = 1;
153
7.09k
  if (Subtarget->hasDotProd())
154
12
    Features[Feature_HasDotProdBit] = 1;
155
7.09k
  if (Subtarget->hasCRC())
156
345
    Features[Feature_HasCRCBit] = 1;
157
7.09k
  if (Subtarget->hasFP16())
158
1.80k
    Features[Feature_HasFP16Bit] = 1;
159
7.09k
  if (Subtarget->hasFullFP16())
160
70
    Features[Feature_HasFullFP16Bit] = 1;
161
7.09k
  if (Subtarget->hasDivideInThumbMode())
162
2.26k
    Features[Feature_HasDivideInThumbBit] = 1;
163
7.09k
  if (Subtarget->hasDivideInARMMode())
164
1.25k
    Features[Feature_HasDivideInARMBit] = 1;
165
7.09k
  if (Subtarget->hasDSP())
166
4.63k
    Features[Feature_HasDSPBit] = 1;
167
7.09k
  if (Subtarget->hasDataBarrier())
168
5.07k
    Features[Feature_HasDBBit] = 1;
169
7.09k
  if (Subtarget->hasV7Clrex())
170
4.73k
    Features[Feature_HasV7ClrexBit] = 1;
171
7.09k
  if (Subtarget->hasAcquireRelease())
172
589
    Features[Feature_HasAcquireReleaseBit] = 1;
173
7.09k
  if (Subtarget->hasMPExtension())
174
1.34k
    Features[Feature_HasMPBit] = 1;
175
7.09k
  if (Subtarget->hasZeroCycleZeroing())
176
43
    Features[Feature_HasZCZBit] = 1;
177
7.09k
  if (Subtarget->useNEONForSinglePrecisionFP())
178
519
    Features[Feature_UseNEONForFPBit] = 1;
179
7.09k
  if (!Subtarget->useNEONForSinglePrecisionFP())
180
6.57k
    Features[Feature_DontUseNEONForFPBit] = 1;
181
7.09k
  if (Subtarget->isThumb())
182
4.04k
    Features[Feature_IsThumbBit] = 1;
183
7.09k
  if (Subtarget->isThumb1Only())
184
718
    Features[Feature_IsThumb1OnlyBit] = 1;
185
7.09k
  if (Subtarget->isThumb2())
186
3.32k
    Features[Feature_IsThumb2Bit] = 1;
187
7.09k
  if (!Subtarget->isMClass())
188
5.68k
    Features[Feature_IsNotMClassBit] = 1;
189
7.09k
  if (!Subtarget->isThumb())
190
3.05k
    Features[Feature_IsARMBit] = 1;
191
7.09k
  if (Subtarget->isTargetWindows())
192
84
    Features[Feature_IsWindowsBit] = 1;
193
7.09k
  if (!Subtarget->isTargetWindows())
194
7.01k
    Features[Feature_IsNotWindowsBit] = 1;
195
7.09k
  if (Subtarget->isReadTPHard())
196
2
    Features[Feature_IsReadTPHardBit] = 1;
197
7.09k
  if (!Subtarget->isReadTPHard())
198
7.09k
    Features[Feature_IsReadTPSoftBit] = 1;
199
7.09k
  if (Subtarget->useNaClTrap())
200
14
    Features[Feature_UseNaClTrapBit] = 1;
201
7.09k
  if (!Subtarget->useNaClTrap())
202
7.08k
    Features[Feature_DontUseNaClTrapBit] = 1;
203
7.09k
  if (Subtarget->useMulOps())
204
7.09k
    Features[Feature_UseMulOpsBit] = 1;
205
7.09k
  if ((TM.Options.AllowFPOpFusion == FPOpFusion::Fast &&  
Subtarget->hasVFP4()102
) &&
!Subtarget->isTargetDarwin()54
&&
Subtarget->useFPVMLx()54
)
206
30
    Features[Feature_UseFusedMACBit] = 1;
207
7.09k
  if (!Subtarget->hasSlowVGETLNi32())
208
6.70k
    Features[Feature_HasFastVGETLNi32Bit] = 1;
209
7.09k
  if (Subtarget->hasSlowVGETLNi32())
210
389
    Features[Feature_HasSlowVGETLNi32Bit] = 1;
211
7.09k
  if (!Subtarget->hasSlowVDUP32())
212
6.70k
    Features[Feature_HasFastVDUP32Bit] = 1;
213
7.09k
  if (Subtarget->hasSlowVDUP32())
214
389
    Features[Feature_HasSlowVDUP32Bit] = 1;
215
7.09k
  if (Subtarget->preferVMOVSR() ||
!Subtarget->useNEONForSinglePrecisionFP()6.98k
)
216
6.58k
    Features[Feature_UseVMOVSRBit] = 1;
217
7.09k
  if (!Subtarget->preferVMOVSR() &&
Subtarget->useNEONForSinglePrecisionFP()6.98k
)
218
511
    Features[Feature_DontUseVMOVSRBit] = 1;
219
7.09k
  return Features;
220
7.09k
}
221
222
PredicateBitset ARMInstructionSelector::
223
1.01k
computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
224
1.01k
  PredicateBitset Features;
225
1.01k
  if (Subtarget->useMovt())
226
490
    Features[Feature_UseMovtBit] = 1;
227
1.01k
  if (!Subtarget->useMovt())
228
527
    Features[Feature_DontUseMovtBit] = 1;
229
1.01k
  if (Subtarget->useMovt() && 
Subtarget->allowPositionIndependentMovt()490
)
230
112
    Features[Feature_UseMovtInPicBit] = 1;
231
1.01k
  if (!Subtarget->useMovt() || 
!Subtarget->allowPositionIndependentMovt()490
)
232
905
    Features[Feature_DontUseMovtInPicBit] = 1;
233
1.01k
  if (((Subtarget->useFPVMLx() &&  TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||
Subtarget->optForMinSize()0
))
234
1.01k
    Features[Feature_UseFPVMLxBit] = 1;
235
1.01k
  if (MF->getDataLayout().isLittleEndian())
236
1.01k
    Features[Feature_IsLEBit] = 1;
237
1.01k
  if (MF->getDataLayout().isBigEndian())
238
0
    Features[Feature_IsBEBit] = 1;
239
1.01k
  return Features;
240
1.01k
}
241
242
// LLT Objects.
243
enum {
244
  GILLT_s16,
245
  GILLT_s32,
246
  GILLT_s64,
247
  GILLT_v2s32,
248
  GILLT_v2s64,
249
  GILLT_v4s16,
250
  GILLT_v4s32,
251
  GILLT_v8s8,
252
  GILLT_v8s16,
253
  GILLT_v16s8,
254
};
255
const static size_t NumTypeObjects = 10;
256
const static LLT TypeObjects[] = {
257
  LLT::scalar(16),
258
  LLT::scalar(32),
259
  LLT::scalar(64),
260
  LLT::vector(2, 32),
261
  LLT::vector(2, 64),
262
  LLT::vector(4, 16),
263
  LLT::vector(4, 32),
264
  LLT::vector(8, 8),
265
  LLT::vector(8, 16),
266
  LLT::vector(16, 8),
267
};
268
269
// Feature bitsets.
270
enum {
271
  GIFBS_Invalid,
272
  GIFBS_HasDotProd,
273
  GIFBS_HasFPARMv8,
274
  GIFBS_HasFullFP16,
275
  GIFBS_HasNEON,
276
  GIFBS_HasVFP2,
277
  GIFBS_HasVFP4,
278
  GIFBS_IsARM,
279
  GIFBS_IsBE,
280
  GIFBS_IsLE,
281
  GIFBS_IsThumb,
282
  GIFBS_IsThumb2,
283
  GIFBS_NoHonorSignDependentRounding,
284
  GIFBS_DontUseNEONForFP_HasVFP2,
285
  GIFBS_HasCrypto_HasV8,
286
  GIFBS_HasDB_IsARM,
287
  GIFBS_HasDB_IsThumb,
288
  GIFBS_HasDPVFP_HasFPARMv8,
289
  GIFBS_HasDPVFP_HasVFP2,
290
  GIFBS_HasDPVFP_HasVFP4,
291
  GIFBS_HasDPVFP_NoHonorSignDependentRounding,
292
  GIFBS_HasDSP_IsThumb2,
293
  GIFBS_HasDivideInARM_IsARM,
294
  GIFBS_HasFP16_HasNEON,
295
  GIFBS_HasFullFP16_HasNEON,
296
  GIFBS_HasNEON_HasV8,
297
  GIFBS_HasNEON_HasV8_1a,
298
  GIFBS_HasV5T_IsARM,
299
  GIFBS_HasV5TE_IsARM,
300
  GIFBS_HasV6_IsARM,
301
  GIFBS_HasV6K_IsARM,
302
  GIFBS_HasV6M_IsThumb,
303
  GIFBS_HasV6T2_IsARM,
304
  GIFBS_HasV6T2_IsThumb2,
305
  GIFBS_HasV7_IsARM,
306
  GIFBS_HasV7Clrex_IsThumb,
307
  GIFBS_HasV8MBaseline_IsThumb,
308
  GIFBS_HasVFP2_UseVMOVSR,
309
  GIFBS_IsARM_NoV6,
310
  GIFBS_IsARM_PreV8,
311
  GIFBS_IsThumb_IsThumb1Only,
312
  GIFBS_IsThumb_IsWindows,
313
  GIFBS_IsThumb_UseMovt,
314
  GIFBS_IsThumb2_PreV8,
315
  GIFBS_IsThumb2_UseMulOps,
316
  GIFBS_HasCRC_HasV8_IsARM,
317
  GIFBS_HasCRC_HasV8_IsThumb2,
318
  GIFBS_HasDSP_IsThumb2_UseMulOps,
319
  GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
320
  GIFBS_HasFullFP16_HasNEON_HasV8,
321
  GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
322
  GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
323
  GIFBS_HasV5TE_IsARM_UseMulOps,
324
  GIFBS_HasV6_IsARM_UseMulOps,
325
  GIFBS_HasV6_IsThumb_IsThumb1Only,
326
  GIFBS_HasV6T2_IsARM_UseMulOps,
327
  GIFBS_IsARM_NoV6_UseMulOps,
328
};
329
const static PredicateBitset FeatureBitsets[] {
330
  {}, // GIFBS_Invalid
331
  {Feature_HasDotProdBit, },
332
  {Feature_HasFPARMv8Bit, },
333
  {Feature_HasFullFP16Bit, },
334
  {Feature_HasNEONBit, },
335
  {Feature_HasVFP2Bit, },
336
  {Feature_HasVFP4Bit, },
337
  {Feature_IsARMBit, },
338
  {Feature_IsBEBit, },
339
  {Feature_IsLEBit, },
340
  {Feature_IsThumbBit, },
341
  {Feature_IsThumb2Bit, },
342
  {Feature_NoHonorSignDependentRoundingBit, },
343
  {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
344
  {Feature_HasCryptoBit, Feature_HasV8Bit, },
345
  {Feature_HasDBBit, Feature_IsARMBit, },
346
  {Feature_HasDBBit, Feature_IsThumbBit, },
347
  {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
348
  {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
349
  {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
350
  {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
351
  {Feature_HasDSPBit, Feature_IsThumb2Bit, },
352
  {Feature_HasDivideInARMBit, Feature_IsARMBit, },
353
  {Feature_HasFP16Bit, Feature_HasNEONBit, },
354
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
355
  {Feature_HasNEONBit, Feature_HasV8Bit, },
356
  {Feature_HasNEONBit, Feature_HasV8_1aBit, },
357
  {Feature_HasV5TBit, Feature_IsARMBit, },
358
  {Feature_HasV5TEBit, Feature_IsARMBit, },
359
  {Feature_HasV6Bit, Feature_IsARMBit, },
360
  {Feature_HasV6KBit, Feature_IsARMBit, },
361
  {Feature_HasV6MBit, Feature_IsThumbBit, },
362
  {Feature_HasV6T2Bit, Feature_IsARMBit, },
363
  {Feature_HasV6T2Bit, Feature_IsThumb2Bit, },
364
  {Feature_HasV7Bit, Feature_IsARMBit, },
365
  {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
366
  {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
367
  {Feature_HasVFP2Bit, Feature_UseVMOVSRBit, },
368
  {Feature_IsARMBit, Feature_NoV6Bit, },
369
  {Feature_IsARMBit, Feature_PreV8Bit, },
370
  {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
371
  {Feature_IsThumbBit, Feature_IsWindowsBit, },
372
  {Feature_IsThumbBit, Feature_UseMovtBit, },
373
  {Feature_IsThumb2Bit, Feature_PreV8Bit, },
374
  {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
375
  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsARMBit, },
376
  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsThumb2Bit, },
377
  {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
378
  {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
379
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
380
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
381
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
382
  {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
383
  {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
384
  {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
385
  {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
386
  {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
387
};
388
389
// ComplexPattern predicates.
390
enum {
391
  GICP_Invalid,
392
};
393
// See constructor for table contents
394
395
// PatFrag predicates.
396
enum {
397
  GIPFP_I64_Predicate_VectorIndex16 = GIPFP_I64_Invalid + 1,
398
  GIPFP_I64_Predicate_VectorIndex32,
399
  GIPFP_I64_Predicate_VectorIndex64,
400
  GIPFP_I64_Predicate_VectorIndex8,
401
  GIPFP_I64_Predicate_imm0_15,
402
  GIPFP_I64_Predicate_imm0_239,
403
  GIPFP_I64_Predicate_imm0_255,
404
  GIPFP_I64_Predicate_imm0_31,
405
  GIPFP_I64_Predicate_imm0_32,
406
  GIPFP_I64_Predicate_imm0_4095,
407
  GIPFP_I64_Predicate_imm0_63,
408
  GIPFP_I64_Predicate_imm0_65535,
409
  GIPFP_I64_Predicate_imm0_65535_neg,
410
  GIPFP_I64_Predicate_imm0_7,
411
  GIPFP_I64_Predicate_imm16,
412
  GIPFP_I64_Predicate_imm16_31,
413
  GIPFP_I64_Predicate_imm1_15,
414
  GIPFP_I64_Predicate_imm1_16,
415
  GIPFP_I64_Predicate_imm1_31,
416
  GIPFP_I64_Predicate_imm1_7,
417
  GIPFP_I64_Predicate_imm24b,
418
  GIPFP_I64_Predicate_imm256_510,
419
  GIPFP_I64_Predicate_imm32,
420
  GIPFP_I64_Predicate_imm8,
421
  GIPFP_I64_Predicate_imm8_255,
422
  GIPFP_I64_Predicate_imm8_or_16,
423
  GIPFP_I64_Predicate_mod_imm,
424
  GIPFP_I64_Predicate_pkh_asr_amt,
425
  GIPFP_I64_Predicate_pkh_lsl_amt,
426
  GIPFP_I64_Predicate_shr_imm16,
427
  GIPFP_I64_Predicate_shr_imm32,
428
  GIPFP_I64_Predicate_shr_imm64,
429
  GIPFP_I64_Predicate_shr_imm8,
430
  GIPFP_I64_Predicate_t2_so_imm,
431
  GIPFP_I64_Predicate_t2_so_imm_neg,
432
};
433
81
bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
434
81
  switch (PredicateID) {
435
81
  case GIPFP_I64_Predicate_VectorIndex16: {
436
0
    
437
0
  return ((uint64_t)Imm) < 4;
438
81
439
81
    
llvm_unreachable0
("ImmediateCode should have returned");
440
81
    
return false0
;
441
81
  }
442
81
  case GIPFP_I64_Predicate_VectorIndex32: {
443
0
    
444
0
  return ((uint64_t)Imm) < 2;
445
81
446
81
    
llvm_unreachable0
("ImmediateCode should have returned");
447
81
    
return false0
;
448
81
  }
449
81
  case GIPFP_I64_Predicate_VectorIndex64: {
450
0
    
451
0
  return ((uint64_t)Imm) < 1;
452
81
453
81
    
llvm_unreachable0
("ImmediateCode should have returned");
454
81
    
return false0
;
455
81
  }
456
81
  case GIPFP_I64_Predicate_VectorIndex8: {
457
0
    
458
0
  return ((uint64_t)Imm) < 8;
459
81
460
81
    
llvm_unreachable0
("ImmediateCode should have returned");
461
81
    
return false0
;
462
81
  }
463
81
  case GIPFP_I64_Predicate_imm0_15: {
464
0
    
465
0
  return Imm >= 0 && Imm < 16;
466
81
467
81
    
llvm_unreachable0
("ImmediateCode should have returned");
468
81
    
return false0
;
469
81
  }
470
81
  case GIPFP_I64_Predicate_imm0_239: {
471
0
     return Imm >= 0 && Imm < 240; 
472
81
    
llvm_unreachable0
("ImmediateCode should have returned");
473
81
    
return false0
;
474
81
  }
475
81
  case GIPFP_I64_Predicate_imm0_255: {
476
0
     return Imm >= 0 && Imm < 256; 
477
81
    
llvm_unreachable0
("ImmediateCode should have returned");
478
81
    
return false0
;
479
81
  }
480
81
  case GIPFP_I64_Predicate_imm0_31: {
481
0
    
482
0
  return Imm >= 0 && Imm < 32;
483
81
484
81
    
llvm_unreachable0
("ImmediateCode should have returned");
485
81
    
return false0
;
486
81
  }
487
81
  case GIPFP_I64_Predicate_imm0_32: {
488
0
    
489
0
  return Imm >= 0 && Imm < 33;
490
81
491
81
    
llvm_unreachable0
("ImmediateCode should have returned");
492
81
    
return false0
;
493
81
  }
494
81
  case GIPFP_I64_Predicate_imm0_4095: {
495
2
    
496
2
  return Imm >= 0 && Imm < 4096;
497
81
498
81
    
llvm_unreachable0
("ImmediateCode should have returned");
499
81
    
return false0
;
500
81
  }
501
81
  case GIPFP_I64_Predicate_imm0_63: {
502
0
    
503
0
  return Imm >= 0 && Imm < 64;
504
81
505
81
    
llvm_unreachable0
("ImmediateCode should have returned");
506
81
    
return false0
;
507
81
  }
508
81
  case GIPFP_I64_Predicate_imm0_65535: {
509
5
    
510
5
  return Imm >= 0 && Imm < 65536;
511
81
512
81
    
llvm_unreachable0
("ImmediateCode should have returned");
513
81
    
return false0
;
514
81
  }
515
81
  case GIPFP_I64_Predicate_imm0_65535_neg: {
516
0
    
517
0
  return -Imm >= 0 && -Imm < 65536;
518
81
519
81
    
llvm_unreachable0
("ImmediateCode should have returned");
520
81
    
return false0
;
521
81
  }
522
81
  case GIPFP_I64_Predicate_imm0_7: {
523
0
    
524
0
  return Imm >= 0 && Imm < 8;
525
81
526
81
    
llvm_unreachable0
("ImmediateCode should have returned");
527
81
    
return false0
;
528
81
  }
529
81
  case GIPFP_I64_Predicate_imm16: {
530
2
     return Imm == 16; 
531
81
    
llvm_unreachable0
("ImmediateCode should have returned");
532
81
    
return false0
;
533
81
  }
534
81
  case GIPFP_I64_Predicate_imm16_31: {
535
3
    
536
3
  return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
537
81
538
81
    
llvm_unreachable0
("ImmediateCode should have returned");
539
81
    
return false0
;
540
81
  }
541
81
  case GIPFP_I64_Predicate_imm1_15: {
542
2
     return Imm > 0 && Imm < 16; 
543
81
    
llvm_unreachable0
("ImmediateCode should have returned");
544
81
    
return false0
;
545
81
  }
546
81
  case GIPFP_I64_Predicate_imm1_16: {
547
0
    
548
0
    return Imm > 0 && Imm <= 16;
549
81
  
550
81
    
llvm_unreachable0
("ImmediateCode should have returned");
551
81
    
return false0
;
552
81
  }
553
81
  case GIPFP_I64_Predicate_imm1_31: {
554
3
     return Imm > 0 && Imm < 32; 
555
81
    
llvm_unreachable0
("ImmediateCode should have returned");
556
81
    
return false0
;
557
81
  }
558
81
  case GIPFP_I64_Predicate_imm1_7: {
559
0
     return Imm > 0 && Imm < 8; 
560
81
    
llvm_unreachable0
("ImmediateCode should have returned");
561
81
    
return false0
;
562
81
  }
563
81
  case GIPFP_I64_Predicate_imm24b: {
564
0
    
565
0
  return Imm >= 0 && Imm <= 0xffffff;
566
81
567
81
    
llvm_unreachable0
("ImmediateCode should have returned");
568
81
    
return false0
;
569
81
  }
570
81
  case GIPFP_I64_Predicate_imm256_510: {
571
0
    
572
0
  return Imm >= 256 && Imm < 511;
573
81
574
81
    
llvm_unreachable0
("ImmediateCode should have returned");
575
81
    
return false0
;
576
81
  }
577
81
  case GIPFP_I64_Predicate_imm32: {
578
0
     return Imm == 32; 
579
81
    
llvm_unreachable0
("ImmediateCode should have returned");
580
81
    
return false0
;
581
81
  }
582
81
  case GIPFP_I64_Predicate_imm8: {
583
0
     return Imm == 8; 
584
81
    
llvm_unreachable0
("ImmediateCode should have returned");
585
81
    
return false0
;
586
81
  }
587
81
  case GIPFP_I64_Predicate_imm8_255: {
588
0
    
589
0
  return Imm >= 8 && Imm < 256;
590
81
591
81
    
llvm_unreachable0
("ImmediateCode should have returned");
592
81
    
return false0
;
593
81
  }
594
81
  case GIPFP_I64_Predicate_imm8_or_16: {
595
0
     return Imm == 8 || Imm == 16;
596
81
    
llvm_unreachable0
("ImmediateCode should have returned");
597
81
    
return false0
;
598
81
  }
599
81
  case GIPFP_I64_Predicate_mod_imm: {
600
44
    
601
44
    return ARM_AM::getSOImmVal(Imm) != -1;
602
81
  
603
81
    
llvm_unreachable0
("ImmediateCode should have returned");
604
81
    
return false0
;
605
81
  }
606
81
  case GIPFP_I64_Predicate_pkh_asr_amt: {
607
0
     return Imm > 0 && Imm <= 32; 
608
81
    
llvm_unreachable0
("ImmediateCode should have returned");
609
81
    
return false0
;
610
81
  }
611
81
  case GIPFP_I64_Predicate_pkh_lsl_amt: {
612
5
     return Imm >= 0 && Imm < 32; 
613
81
    
llvm_unreachable0
("ImmediateCode should have returned");
614
81
    
return false0
;
615
81
  }
616
81
  case GIPFP_I64_Predicate_shr_imm16: {
617
0
     return Imm > 0 && Imm <= 16; 
618
81
    
llvm_unreachable0
("ImmediateCode should have returned");
619
81
    
return false0
;
620
81
  }
621
81
  case GIPFP_I64_Predicate_shr_imm32: {
622
0
     return Imm > 0 && Imm <= 32; 
623
81
    
llvm_unreachable0
("ImmediateCode should have returned");
624
81
    
return false0
;
625
81
  }
626
81
  case GIPFP_I64_Predicate_shr_imm64: {
627
0
     return Imm > 0 && Imm <= 64; 
628
81
    
llvm_unreachable0
("ImmediateCode should have returned");
629
81
    
return false0
;
630
81
  }
631
81
  case GIPFP_I64_Predicate_shr_imm8: {
632
0
     return Imm > 0 && Imm <= 8; 
633
81
    
llvm_unreachable0
("ImmediateCode should have returned");
634
81
    
return false0
;
635
81
  }
636
81
  case GIPFP_I64_Predicate_t2_so_imm: {
637
15
    
638
15
    return ARM_AM::getT2SOImmVal(Imm) != -1;
639
81
  
640
81
    
llvm_unreachable0
("ImmediateCode should have returned");
641
81
    
return false0
;
642
81
  }
643
81
  case GIPFP_I64_Predicate_t2_so_imm_neg: {
644
0
    
645
0
  return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
646
81
647
81
    
llvm_unreachable0
("ImmediateCode should have returned");
648
81
    
return false0
;
649
0
  }
650
0
  }
651
0
  llvm_unreachable("Unknown predicate");
652
0
  return false;
653
0
}
654
0
bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
655
0
  llvm_unreachable("Unknown predicate");
656
0
  return false;
657
0
}
658
// PatFrag predicates.
659
enum {
660
  GIPFP_APInt_Predicate_arm_i32imm = GIPFP_APInt_Invalid + 1,
661
};
662
1
bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
663
1
  switch (PredicateID) {
664
1
  case GIPFP_APInt_Predicate_arm_i32imm: {
665
1
    
666
1
  if (Subtarget->useMovt())
667
1
    return true;
668
0
  return ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue());
669
0
670
0
    llvm_unreachable("ImmediateCode should have returned");
671
0
    return false;
672
0
  }
673
0
  }
674
0
  llvm_unreachable("Unknown predicate");
675
0
  return false;
676
0
}
677
// PatFrag predicates.
678
enum {
679
  GIPFP_MI_Predicate_bf_inv_mask_imm = GIPFP_MI_Invalid + 1,
680
};
681
2
bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
682
2
  const MachineFunction &MF = *MI.getParent()->getParent();
683
2
  const MachineRegisterInfo &MRI = MF.getRegInfo();
684
2
  (void)MRI;
685
2
  switch (PredicateID) {
686
2
  case GIPFP_MI_Predicate_bf_inv_mask_imm: {
687
2
    
688
2
    // There's better methods of implementing this check. IntImmLeaf<> would be
689
2
    // equivalent and have less boilerplate but we need a test for C++
690
2
    // predicates and this one causes new rules to be imported into GlobalISel
691
2
    // without requiring additional features first.
692
2
    const auto &MO = MI.getOperand(1);
693
2
    if (!MO.isCImm())
694
0
      return false;
695
2
    return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
696
2
  
697
2
    
llvm_unreachable0
("GISelPredicateCode should have returned");
698
2
    
return false0
;
699
0
  }
700
0
  }
701
0
  llvm_unreachable("Unknown predicate");
702
0
  return false;
703
0
}
704
705
ARMInstructionSelector::ComplexMatcherMemFn
706
ARMInstructionSelector::ComplexPredicateFns[] = {
707
  nullptr, // GICP_Invalid
708
};
709
710
// Custom renderers.
711
enum {
712
  GICR_Invalid,
713
};
714
ARMInstructionSelector::CustomRendererFn
715
ARMInstructionSelector::CustomRenderers[] = {
716
  nullptr, // GICP_Invalid
717
};
718
719
1.01k
bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
720
1.01k
  MachineFunction &MF = *I.getParent()->getParent();
721
1.01k
  MachineRegisterInfo &MRI = MF.getRegInfo();
722
1.01k
  // FIXME: This should be computed on a per-function basis rather than per-insn.
723
1.01k
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
724
1.01k
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
725
1.01k
  NewMIVector OutMIs;
726
1.01k
  State.MIs.clear();
727
1.01k
  State.MIs.push_back(&I);
728
1.01k
729
1.01k
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
730
283
    return true;
731
283
  }
732
734
733
734
  return false;
734
734
}
735
736
1.01k
const int64_t *ARMInstructionSelector::getMatchTable() const {
737
1.01k
  constexpr static int64_t MatchTable0[] = {
738
1.01k
    GIM_SwitchOpcode, /*MI*/0, /*[*/35, 146, /*)*//*default:*//*Label 39*/ 62830,
739
1.01k
    /*TargetOpcode::G_ADD*//*Label 0*/ 116,
740
1.01k
    /*TargetOpcode::G_SUB*//*Label 1*/ 6667,
741
1.01k
    /*TargetOpcode::G_MUL*//*Label 2*/ 8657,
742
1.01k
    /*TargetOpcode::G_SDIV*//*Label 3*/ 9291,
743
1.01k
    /*TargetOpcode::G_UDIV*//*Label 4*/ 9391, 0, 0,
744
1.01k
    /*TargetOpcode::G_AND*//*Label 5*/ 9491,
745
1.01k
    /*TargetOpcode::G_OR*//*Label 6*/ 11204,
746
1.01k
    /*TargetOpcode::G_XOR*//*Label 7*/ 15387, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
747
1.01k
    /*TargetOpcode::G_BITCAST*//*Label 8*/ 15886, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
748
1.01k
    /*TargetOpcode::G_INTRINSIC*//*Label 9*/ 20274,
749
1.01k
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 10*/ 49645,
750
1.01k
    /*TargetOpcode::G_ANYEXT*//*Label 11*/ 53974,
751
1.01k
    /*TargetOpcode::G_TRUNC*//*Label 12*/ 54097,
752
1.01k
    /*TargetOpcode::G_CONSTANT*//*Label 13*/ 54226, 0, 0, 0,
753
1.01k
    /*TargetOpcode::G_SEXT*//*Label 14*/ 54417,
754
1.01k
    /*TargetOpcode::G_ZEXT*//*Label 15*/ 54546,
755
1.01k
    /*TargetOpcode::G_SHL*//*Label 16*/ 55056,
756
1.01k
    /*TargetOpcode::G_LSHR*//*Label 17*/ 55161,
757
1.01k
    /*TargetOpcode::G_ASHR*//*Label 18*/ 55219, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
758
1.01k
    /*TargetOpcode::G_FADD*//*Label 19*/ 55432,
759
1.01k
    /*TargetOpcode::G_FSUB*//*Label 20*/ 56063,
760
1.01k
    /*TargetOpcode::G_FMUL*//*Label 21*/ 56678,
761
1.01k
    /*TargetOpcode::G_FMA*//*Label 22*/ 57261,
762
1.01k
    /*TargetOpcode::G_FDIV*//*Label 23*/ 58282, 0, 0, 0, 0, 0, 0, 0,
763
1.01k
    /*TargetOpcode::G_FNEG*//*Label 24*/ 58445,
764
1.01k
    /*TargetOpcode::G_FPEXT*//*Label 25*/ 59362,
765
1.01k
    /*TargetOpcode::G_FPTRUNC*//*Label 26*/ 59519,
766
1.01k
    /*TargetOpcode::G_FPTOSI*//*Label 27*/ 59680,
767
1.01k
    /*TargetOpcode::G_FPTOUI*//*Label 28*/ 60398,
768
1.01k
    /*TargetOpcode::G_SITOFP*//*Label 29*/ 61116,
769
1.01k
    /*TargetOpcode::G_UITOFP*//*Label 30*/ 61453,
770
1.01k
    /*TargetOpcode::G_FABS*//*Label 31*/ 61790, 0, 0, 0,
771
1.01k
    /*TargetOpcode::G_BR*//*Label 32*/ 62039, 0, 0, 0, 0, 0,
772
1.01k
    /*TargetOpcode::G_CTLZ*//*Label 33*/ 62101, 0,
773
1.01k
    /*TargetOpcode::G_CTPOP*//*Label 34*/ 62427,
774
1.01k
    /*TargetOpcode::G_BSWAP*//*Label 35*/ 62515,
775
1.01k
    /*TargetOpcode::G_FCEIL*//*Label 36*/ 62629, 0, 0,
776
1.01k
    /*TargetOpcode::G_FSQRT*//*Label 37*/ 62686,
777
1.01k
    /*TargetOpcode::G_FFLOOR*//*Label 38*/ 62773,
778
1.01k
    // Label 0: @116
779
1.01k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 49*/ 6666,
780
1.01k
    /*GILLT_s32*//*Label 40*/ 131,
781
1.01k
    /*GILLT_s64*//*Label 41*/ 1809,
782
1.01k
    /*GILLT_v2s32*//*Label 42*/ 1860,
783
1.01k
    /*GILLT_v2s64*//*Label 43*/ 2320,
784
1.01k
    /*GILLT_v4s16*//*Label 44*/ 3038,
785
1.01k
    /*GILLT_v4s32*//*Label 45*/ 3498,
786
1.01k
    /*GILLT_v8s8*//*Label 46*/ 4622,
787
1.01k
    /*GILLT_v8s16*//*Label 47*/ 5082,
788
1.01k
    /*GILLT_v16s8*//*Label 48*/ 6206,
789
1.01k
    // Label 40: @131
790
1.01k
    GIM_Try, /*On fail goto*//*Label 50*/ 1808,
791
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
792
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
793
1.01k
      GIM_Try, /*On fail goto*//*Label 51*/ 207, // Rule ID 2782 //
794
1.01k
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
795
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
796
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
797
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
798
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
799
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
800
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
801
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
802
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
803
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
804
1.01k
        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
805
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
806
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
807
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
808
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
809
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
810
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
811
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
812
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
813
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
814
1.01k
        // GIR_Coverage, 2782,
815
1.01k
        GIR_Done,
816
1.01k
      // Label 51: @207
817
1.01k
      GIM_Try, /*On fail goto*//*Label 52*/ 273, // Rule ID 2783 //
818
1.01k
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
819
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
820
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
821
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
822
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
823
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
824
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
825
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
826
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
827
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
828
1.01k
        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
829
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
830
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
831
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
832
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
833
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
834
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
835
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
836
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
837
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
838
1.01k
        // GIR_Coverage, 2783,
839
1.01k
        GIR_Done,
840
1.01k
      // Label 52: @273
841
1.01k
      GIM_Try, /*On fail goto*//*Label 53*/ 339, // Rule ID 2816 //
842
1.01k
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
843
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
844
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
845
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
846
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
847
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
848
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
849
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
850
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
851
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
852
1.01k
        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
853
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
854
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
855
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
856
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
857
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
858
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
859
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
860
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
861
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
862
1.01k
        // GIR_Coverage, 2816,
863
1.01k
        GIR_Done,
864
1.01k
      // Label 53: @339
865
1.01k
      GIM_Try, /*On fail goto*//*Label 54*/ 405, // Rule ID 2817 //
866
1.01k
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
867
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
868
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
869
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
870
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
871
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
872
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
873
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
874
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
875
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
876
1.01k
        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
877
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
878
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
879
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
880
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
881
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
882
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
883
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
884
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
885
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
886
1.01k
        // GIR_Coverage, 2817,
887
1.01k
        GIR_Done,
888
1.01k
      // Label 54: @405
889
1.01k
      GIM_Try, /*On fail goto*//*Label 55*/ 471, // Rule ID 1826 //
890
1.01k
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
891
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
892
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
893
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
894
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
895
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
896
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
897
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
898
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
899
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
900
1.01k
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
901
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
902
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
903
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
904
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
905
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
906
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
907
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
908
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
909
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
910
1.01k
        // GIR_Coverage, 1826,
911
1.01k
        GIR_Done,
912
1.01k
      // Label 55: @471
913
1.01k
      GIM_Try, /*On fail goto*//*Label 56*/ 537, // Rule ID 1827 //
914
1.01k
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
915
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
916
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
917
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
918
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
919
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
920
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
921
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
922
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
923
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
924
1.01k
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
925
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
926
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
927
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
928
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
929
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
930
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
931
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
932
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
933
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
934
1.01k
        // GIR_Coverage, 1827,
935
1.01k
        GIR_Done,
936
1.01k
      // Label 56: @537
937
1.01k
      GIM_Try, /*On fail goto*//*Label 57*/ 603, // Rule ID 2026 //
938
1.01k
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
939
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
940
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
941
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
942
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
943
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
944
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
945
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
946
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
947
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
948
1.01k
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
949
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
950
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
951
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
952
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
953
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
954
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
955
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
956
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
957
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
958
1.01k
        // GIR_Coverage, 2026,
959
1.01k
        GIR_Done,
960
1.01k
      // Label 57: @603
961
1.01k
      GIM_Try, /*On fail goto*//*Label 58*/ 669, // Rule ID 2027 //
962
1.01k
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
963
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
964
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
965
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
966
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
967
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
968
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
969
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
970
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
971
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
972
1.01k
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
973
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
974
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
975
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
976
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
977
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
978
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
979
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
980
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
981
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
982
1.01k
        // GIR_Coverage, 2027,
983
1.01k
        GIR_Done,
984
1.01k
      // Label 58: @669
985
1.01k
      GIM_Try, /*On fail goto*//*Label 59*/ 778, // Rule ID 2563 //
986
1.01k
        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
987
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
988
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
989
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
990
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
991
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
992
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
993
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
994
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
995
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
996
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
997
1.01k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
998
1.01k
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
999
1.01k
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1000
1.01k
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1001
1.01k
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1002
1.01k
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1003
1.01k
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1004
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1005
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1006
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1007
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1008
1.01k
        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra)  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1009
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1010
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1011
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1012
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1013
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1014
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1015
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1016
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1017
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1018
1.01k
        // GIR_Coverage, 2563,
1019
1.01k
        GIR_Done,
1020
1.01k
      // Label 59: @778
1021
1.01k
      GIM_Try, /*On fail goto*//*Label 60*/ 887, // Rule ID 2600 //
1022
1.01k
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1023
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1024
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1025
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1026
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1027
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1028
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1029
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1030
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1031
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1032
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1033
1.01k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1034
1.01k
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1035
1.01k
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1036
1.01k
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1037
1.01k
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1038
1.01k
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1039
1.01k
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1040
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1041
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1042
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1043
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1044
1.01k
        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1045
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1046
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1047
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1048
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1049
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1050
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1051
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1052
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1053
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1054
1.01k
        // GIR_Coverage, 2600,
1055
1.01k
        GIR_Done,
1056
1.01k
      // Label 60: @887
1057
1.01k
      GIM_Try, /*On fail goto*//*Label 61*/ 996, // Rule ID 194 //
1058
1.01k
        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
1059
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1060
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1061
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1062
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1063
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1064
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1065
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1066
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1067
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1068
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1069
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1070
1.01k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1071
1.01k
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1072
1.01k
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1073
1.01k
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1074
1.01k
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1075
1.01k
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1076
1.01k
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1077
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1078
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1079
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1080
1.01k
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1081
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1082
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1083
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1084
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1085
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1086
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1087
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1088
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1089
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1090
1.01k
        // GIR_Coverage, 194,
1091
1.01k
        GIR_Done,
1092
1.01k
      // Label 61: @996
1093
1.01k
      GIM_Try, /*On fail goto*//*Label 62*/ 1105, // Rule ID 526 //
1094
1.01k
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1095
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1096
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1097
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1098
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1099
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1100
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1101
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1102
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1103
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1104
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1105
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1106
1.01k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1107
1.01k
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1108
1.01k
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1109
1.01k
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1110
1.01k
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1111
1.01k
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1112
1.01k
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1113
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1114
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1115
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1116
1.01k
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1117
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1118
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1119
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1120
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1121
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1122
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1123
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1124
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1125
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1126
1.01k
        // GIR_Coverage, 526,
1127
1.01k
        GIR_Done,
1128
1.01k
      // Label 62: @1105
1129
1.01k
      GIM_Try, /*On fail goto*//*Label 63*/ 1157, // Rule ID 74 //
1130
1.01k
        GIM_CheckFeatures, GIFBS_IsARM,
1131
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1132
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1133
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1134
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1135
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
1136
1.01k
        // MIs[1] Operand 1
1137
1.01k
        // No operand predicates
1138
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1139
1.01k
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1140
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDri,
1141
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1142
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1143
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1144
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1145
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1146
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1147
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1148
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1149
1.01k
        // GIR_Coverage, 74,
1150
1.01k
        GIR_Done,
1151
1.01k
      // Label 63: @1157
1152
1.01k
      GIM_Try, /*On fail goto*//*Label 64*/ 1209, // Rule ID 412 //
1153
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
1154
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1155
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1156
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1157
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1158
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
1159
1.01k
        // MIs[1] Operand 1
1160
1.01k
        // No operand predicates
1161
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1162
1.01k
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1163
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri,
1164
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1165
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1166
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1167
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1168
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1169
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1170
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1171
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1172
1.01k
        // GIR_Coverage, 412,
1173
1.01k
        GIR_Done,
1174
1.01k
      // Label 64: @1209
1175
1.01k
      GIM_Try, /*On fail goto*//*Label 65*/ 1258, // Rule ID 413 //
1176
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
1177
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1178
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1179
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1180
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1181
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
1182
1.01k
        // MIs[1] Operand 1
1183
1.01k
        // No operand predicates
1184
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1185
1.01k
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1186
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri12,
1187
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1188
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1189
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1190
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1191
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1192
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1193
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1194
1.01k
        // GIR_Coverage, 413,
1195
1.01k
        GIR_Done,
1196
1.01k
      // Label 65: @1258
1197
1.01k
      GIM_Try, /*On fail goto*//*Label 66*/ 1328, // Rule ID 173 //
1198
1.01k
        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1199
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1200
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1201
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1202
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1203
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1204
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1205
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1206
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1207
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1208
1.01k
        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1209
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1210
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1211
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1212
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1213
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1214
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1215
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1216
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1217
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1218
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1219
1.01k
        // GIR_Coverage, 173,
1220
1.01k
        GIR_Done,
1221
1.01k
      // Label 66: @1328
1222
1.01k
      GIM_Try, /*On fail goto*//*Label 67*/ 1398, // Rule ID 174 //
1223
1.01k
        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1224
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1225
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1226
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1227
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1228
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1229
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1230
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1231
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1232
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1233
1.01k
        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1234
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1235
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1236
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1237
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1238
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1239
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1240
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1241
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1242
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1243
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1244
1.01k
        // GIR_Coverage, 174,
1245
1.01k
        GIR_Done,
1246
1.01k
      // Label 67: @1398
1247
1.01k
      GIM_Try, /*On fail goto*//*Label 68*/ 1465, // Rule ID 508 //
1248
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1249
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1250
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1251
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1252
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1253
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1254
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1255
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1256
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1257
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1258
1.01k
        // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra)  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1259
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1260
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1261
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1262
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1263
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1264
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1265
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1266
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1267
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1268
1.01k
        // GIR_Coverage, 508,
1269
1.01k
        GIR_Done,
1270
1.01k
      // Label 68: @1465
1271
1.01k
      GIM_Try, /*On fail goto*//*Label 69*/ 1535, // Rule ID 2557 //
1272
1.01k
        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1273
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1274
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1275
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1276
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1277
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1278
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1279
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1280
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1281
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1282
1.01k
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1283
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1284
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1285
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1286
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1287
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1288
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1289
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1290
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1291
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1292
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1293
1.01k
        // GIR_Coverage, 2557,
1294
1.01k
        GIR_Done,
1295
1.01k
      // Label 69: @1535
1296
1.01k
      GIM_Try, /*On fail goto*//*Label 70*/ 1605, // Rule ID 2558 //
1297
1.01k
        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1298
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1299
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1300
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1301
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1302
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1303
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1304
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1305
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1306
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1307
1.01k
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1308
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1309
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1310
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1311
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1312
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1313
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1314
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1315
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1316
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1317
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1318
1.01k
        // GIR_Coverage, 2558,
1319
1.01k
        GIR_Done,
1320
1.01k
      // Label 70: @1605
1321
1.01k
      GIM_Try, /*On fail goto*//*Label 71*/ 1672, // Rule ID 2595 //
1322
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1323
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1324
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1325
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1326
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1327
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1328
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1329
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1330
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1331
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1332
1.01k
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1333
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1334
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1335
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1336
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1337
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1338
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1339
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1340
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1341
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1342
1.01k
        // GIR_Coverage, 2595,
1343
1.01k
        GIR_Done,
1344
1.01k
      // Label 71: @1672
1345
1.01k
      GIM_Try, /*On fail goto*//*Label 72*/ 1717, // Rule ID 75 //
1346
1.01k
        GIM_CheckFeatures, GIFBS_IsARM,
1347
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1348
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1349
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1350
1.01k
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
1351
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDrr,
1352
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1353
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1354
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1355
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1356
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1357
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1358
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1359
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1360
1.01k
        // GIR_Coverage, 75,
1361
1.01k
        GIR_Done,
1362
1.01k
      // Label 72: @1717
1363
1.01k
      GIM_Try, /*On fail goto*//*Label 73*/ 1762, // Rule ID 414 //
1364
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
1365
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1366
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1367
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1368
1.01k
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1369
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1370
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1371
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1372
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1373
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1374
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1375
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1376
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1377
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1378
1.01k
        // GIR_Coverage, 414,
1379
1.01k
        GIR_Done,
1380
1.01k
      // Label 73: @1762
1381
1.01k
      GIM_Try, /*On fail goto*//*Label 74*/ 1807, // Rule ID 2577 //
1382
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
1383
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1384
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1385
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1386
1.01k
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1387
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1388
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1389
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1390
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
1391
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1392
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1393
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1394
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1395
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1396
1.01k
        // GIR_Coverage, 2577,
1397
1.01k
        GIR_Done,
1398
1.01k
      // Label 74: @1807
1399
1.01k
      GIM_Reject,
1400
1.01k
    // Label 50: @1808
1401
1.01k
    GIM_Reject,
1402
1.01k
    // Label 41: @1809
1403
1.01k
    GIM_Try, /*On fail goto*//*Label 75*/ 1859, // Rule ID 761 //
1404
1.01k
      GIM_CheckFeatures, GIFBS_HasNEON,
1405
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1406
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1407
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1408
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1409
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1410
1.01k
      // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1411
1.01k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv1i64,
1412
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1413
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1414
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1415
1.01k
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1416
1.01k
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1417
1.01k
      GIR_EraseFromParent, /*InsnID*/0,
1418
1.01k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1419
1.01k
      // GIR_Coverage, 761,
1420
1.01k
      GIR_Done,
1421
1.01k
    // Label 75: @1859
1422
1.01k
    GIM_Reject,
1423
1.01k
    // Label 42: @1860
1424
1.01k
    GIM_Try, /*On fail goto*//*Label 76*/ 2319,
1425
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1426
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1427
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1428
1.01k
      GIM_Try, /*On fail goto*//*Label 77*/ 1944, // Rule ID 2715 //
1429
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1430
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1431
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1432
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1433
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1434
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1435
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1436
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1437
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1438
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1439
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1440
1.01k
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1110:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1441
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1442
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1443
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1444
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1445
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1446
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1447
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1448
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1449
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1450
1.01k
        // GIR_Coverage, 2715,
1451
1.01k
        GIR_Done,
1452
1.01k
      // Label 77: @1944
1453
1.01k
      GIM_Try, /*On fail goto*//*Label 78*/ 2014, // Rule ID 2721 //
1454
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1455
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1456
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1457
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1458
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1459
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1460
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1461
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1462
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1463
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1464
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1465
1.01k
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1111:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1466
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1467
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1468
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1469
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1470
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1471
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1472
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1473
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1474
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1475
1.01k
        // GIR_Coverage, 2721,
1476
1.01k
        GIR_Done,
1477
1.01k
      // Label 78: @2014
1478
1.01k
      GIM_Try, /*On fail goto*//*Label 79*/ 2084, // Rule ID 1153 //
1479
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1480
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1481
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1482
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1483
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1484
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1485
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1486
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1487
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1488
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1489
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1490
1.01k
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1110:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1491
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1492
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1493
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1494
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1495
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1496
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1497
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1498
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1499
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1500
1.01k
        // GIR_Coverage, 1153,
1501
1.01k
        GIR_Done,
1502
1.01k
      // Label 79: @2084
1503
1.01k
      GIM_Try, /*On fail goto*//*Label 80*/ 2154, // Rule ID 1159 //
1504
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1505
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1506
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1507
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1508
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1509
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1510
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1511
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1512
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1513
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1514
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1515
1.01k
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1111:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1516
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1517
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1518
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1519
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1520
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1521
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1522
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1523
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1524
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1525
1.01k
        // GIR_Coverage, 1159,
1526
1.01k
        GIR_Done,
1527
1.01k
      // Label 80: @2154
1528
1.01k
      GIM_Try, /*On fail goto*//*Label 81*/ 2217, // Rule ID 2645 //
1529
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1530
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1531
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1532
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1533
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1534
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1535
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1536
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1537
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1538
1.01k
        // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1539
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1540
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1541
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1542
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1543
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1544
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1545
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1546
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1547
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1548
1.01k
        // GIR_Coverage, 2645,
1549
1.01k
        GIR_Done,
1550
1.01k
      // Label 81: @2217
1551
1.01k
      GIM_Try, /*On fail goto*//*Label 82*/ 2280, // Rule ID 876 //
1552
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1553
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1554
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1555
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1556
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1557
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1558
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1559
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1560
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1561
1.01k
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1562
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1563
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1564
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1565
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1566
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1567
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1568
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1569
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1570
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1571
1.01k
        // GIR_Coverage, 876,
1572
1.01k
        GIR_Done,
1573
1.01k
      // Label 82: @2280
1574
1.01k
      GIM_Try, /*On fail goto*//*Label 83*/ 2318, // Rule ID 757 //
1575
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1576
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1577
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1578
1.01k
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1579
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i32,
1580
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1581
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1582
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1583
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1584
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1585
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1586
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1587
1.01k
        // GIR_Coverage, 757,
1588
1.01k
        GIR_Done,
1589
1.01k
      // Label 83: @2318
1590
1.01k
      GIM_Reject,
1591
1.01k
    // Label 76: @2319
1592
1.01k
    GIM_Reject,
1593
1.01k
    // Label 43: @2320
1594
1.01k
    GIM_Try, /*On fail goto*//*Label 84*/ 3037,
1595
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1596
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1597
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
1598
1.01k
      GIM_Try, /*On fail goto*//*Label 85*/ 2417, // Rule ID 2727 //
1599
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1600
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1601
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1602
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1603
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1604
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1605
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1606
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1607
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1608
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1609
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1610
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1611
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1612
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1613
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1614
1.01k
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1110:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1615
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1616
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1617
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1618
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1619
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1620
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1621
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1622
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1623
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1624
1.01k
        // GIR_Coverage, 2727,
1625
1.01k
        GIR_Done,
1626
1.01k
      // Label 85: @2417
1627
1.01k
      GIM_Try, /*On fail goto*//*Label 86*/ 2500, // Rule ID 2730 //
1628
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1629
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1630
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1631
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1632
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1633
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1634
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1635
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1636
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1637
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1638
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1639
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1640
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1641
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1642
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1643
1.01k
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1111:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1644
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1645
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1646
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1647
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1648
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1649
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1650
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1651
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1652
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1653
1.01k
        // GIR_Coverage, 2730,
1654
1.01k
        GIR_Done,
1655
1.01k
      // Label 86: @2500
1656
1.01k
      GIM_Try, /*On fail goto*//*Label 87*/ 2583, // Rule ID 1165 //
1657
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1658
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1659
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1660
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1661
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1662
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1663
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1664
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1665
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1666
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1667
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1668
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1669
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1670
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1671
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1672
1.01k
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1110:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1673
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1674
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1675
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1676
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1677
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1678
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1679
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1680
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1681
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1682
1.01k
        // GIR_Coverage, 1165,
1683
1.01k
        GIR_Done,
1684
1.01k
      // Label 87: @2583
1685
1.01k
      GIM_Try, /*On fail goto*//*Label 88*/ 2666, // Rule ID 1168 //
1686
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1687
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1688
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1689
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1690
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1691
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1692
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1693
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1694
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1695
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1696
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1697
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1698
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1699
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1700
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1701
1.01k
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1111:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1702
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1703
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1704
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1705
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1706
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1707
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1708
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1709
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1710
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1711
1.01k
        // GIR_Coverage, 1168,
1712
1.01k
        GIR_Done,
1713
1.01k
      // Label 88: @2666
1714
1.01k
      GIM_Try, /*On fail goto*//*Label 89*/ 2730, // Rule ID 769 //
1715
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1716
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1717
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1718
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1719
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1720
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1721
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1722
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1723
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1724
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1725
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1726
1.01k
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1727
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv2i64,
1728
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1729
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1730
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
1731
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1732
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1733
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1734
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1735
1.01k
        // GIR_Coverage, 769,
1736
1.01k
        GIR_Done,
1737
1.01k
      // Label 89: @2730
1738
1.01k
      GIM_Try, /*On fail goto*//*Label 90*/ 2794, // Rule ID 772 //
1739
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1740
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1741
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1742
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1743
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1744
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1745
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1746
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1747
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1748
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1749
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1750
1.01k
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1751
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
1752
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1753
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1754
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
1755
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1756
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1757
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1758
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1759
1.01k
        // GIR_Coverage, 772,
1760
1.01k
        GIR_Done,
1761
1.01k
      // Label 90: @2794
1762
1.01k
      GIM_Try, /*On fail goto*//*Label 91*/ 2845, // Rule ID 2621 //
1763
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1764
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1765
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1766
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1767
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1768
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1769
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1770
1.01k
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1771
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
1772
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1773
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
1774
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1775
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1776
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1777
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1778
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1779
1.01k
        // GIR_Coverage, 2621,
1780
1.01k
        GIR_Done,
1781
1.01k
      // Label 91: @2845
1782
1.01k
      GIM_Try, /*On fail goto*//*Label 92*/ 2896, // Rule ID 2624 //
1783
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1784
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1785
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1786
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1787
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1788
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1789
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1790
1.01k
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1791
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
1792
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1793
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
1794
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1795
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1796
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1797
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1798
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1799
1.01k
        // GIR_Coverage, 2624,
1800
1.01k
        GIR_Done,
1801
1.01k
      // Label 92: @2896
1802
1.01k
      GIM_Try, /*On fail goto*//*Label 93*/ 2947, // Rule ID 775 //
1803
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1804
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1805
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1806
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1807
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1808
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1809
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1810
1.01k
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1811
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
1812
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1813
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1814
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1815
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1816
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1817
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1818
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1819
1.01k
        // GIR_Coverage, 775,
1820
1.01k
        GIR_Done,
1821
1.01k
      // Label 93: @2947
1822
1.01k
      GIM_Try, /*On fail goto*//*Label 94*/ 2998, // Rule ID 778 //
1823
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1824
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1825
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1826
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1827
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1828
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1829
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1830
1.01k
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1831
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
1832
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1833
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1834
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1835
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1836
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1837
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1838
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1839
1.01k
        // GIR_Coverage, 778,
1840
1.01k
        GIR_Done,
1841
1.01k
      // Label 94: @2998
1842
1.01k
      GIM_Try, /*On fail goto*//*Label 95*/ 3036, // Rule ID 762 //
1843
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1844
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1845
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1846
1.01k
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
1847
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i64,
1848
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1849
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1850
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1851
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1852
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1853
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1854
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1855
1.01k
        // GIR_Coverage, 762,
1856
1.01k
        GIR_Done,
1857
1.01k
      // Label 95: @3036
1858
1.01k
      GIM_Reject,
1859
1.01k
    // Label 84: @3037
1860
1.01k
    GIM_Reject,
1861
1.01k
    // Label 44: @3038
1862
1.01k
    GIM_Try, /*On fail goto*//*Label 96*/ 3497,
1863
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1864
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
1865
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1866
1.01k
      GIM_Try, /*On fail goto*//*Label 97*/ 3122, // Rule ID 2714 //
1867
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1868
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1869
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1870
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1871
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1872
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1873
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1874
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1875
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1876
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1877
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1878
1.01k
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1110:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1879
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
1880
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1881
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1882
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1883
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1884
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1885
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1886
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1887
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1888
1.01k
        // GIR_Coverage, 2714,
1889
1.01k
        GIR_Done,
1890
1.01k
      // Label 97: @3122
1891
1.01k
      GIM_Try, /*On fail goto*//*Label 98*/ 3192, // Rule ID 2720 //
1892
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1893
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1894
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1895
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1896
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1897
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1898
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1899
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1900
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1901
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1902
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1903
1.01k
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1111:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1904
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
1905
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1906
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1907
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1908
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1909
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1910
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1911
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1912
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1913
1.01k
        // GIR_Coverage, 2720,
1914
1.01k
        GIR_Done,
1915
1.01k
      // Label 98: @3192
1916
1.01k
      GIM_Try, /*On fail goto*//*Label 99*/ 3262, // Rule ID 1152 //
1917
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1918
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1919
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1920
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1921
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1922
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1923
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1924
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1925
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1926
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1927
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1928
1.01k
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1110:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1929
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
1930
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1931
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1932
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1933
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1934
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1935
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1936
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1937
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1938
1.01k
        // GIR_Coverage, 1152,
1939
1.01k
        GIR_Done,
1940
1.01k
      // Label 99: @3262
1941
1.01k
      GIM_Try, /*On fail goto*//*Label 100*/ 3332, // Rule ID 1158 //
1942
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1943
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1944
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1945
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1946
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1947
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1948
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1949
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1950
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1951
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1952
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1953
1.01k
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1111:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1954
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
1955
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1956
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1957
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1958
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1959
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1960
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1961
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1962
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1963
1.01k
        // GIR_Coverage, 1158,
1964
1.01k
        GIR_Done,
1965
1.01k
      // Label 100: @3332
1966
1.01k
      GIM_Try, /*On fail goto*//*Label 101*/ 3395, // Rule ID 2644 //
1967
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1968
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1969
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1970
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
1971
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1972
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1973
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1974
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1975
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1976
1.01k
        // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1977
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
1978
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1979
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1980
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1981
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1982
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1983
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1984
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
1985
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1986
1.01k
        // GIR_Coverage, 2644,
1987
1.01k
        GIR_Done,
1988
1.01k
      // Label 101: @3395
1989
1.01k
      GIM_Try, /*On fail goto*//*Label 102*/ 3458, // Rule ID 875 //
1990
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
1991
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1992
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1993
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1994
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
1995
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1996
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1997
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1998
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1999
1.01k
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2000
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
2001
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2002
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2003
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2004
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2005
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2006
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2007
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2008
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2009
1.01k
        // GIR_Coverage, 875,
2010
1.01k
        GIR_Done,
2011
1.01k
      // Label 102: @3458
2012
1.01k
      GIM_Try, /*On fail goto*//*Label 103*/ 3496, // Rule ID 756 //
2013
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2014
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2015
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2016
1.01k
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2017
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i16,
2018
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2019
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2020
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2021
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2022
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2023
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2024
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2025
1.01k
        // GIR_Coverage, 756,
2026
1.01k
        GIR_Done,
2027
1.01k
      // Label 103: @3496
2028
1.01k
      GIM_Reject,
2029
1.01k
    // Label 96: @3497
2030
1.01k
    GIM_Reject,
2031
1.01k
    // Label 45: @3498
2032
1.01k
    GIM_Try, /*On fail goto*//*Label 104*/ 4621,
2033
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2034
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2035
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2036
1.01k
      GIM_Try, /*On fail goto*//*Label 105*/ 3595, // Rule ID 2726 //
2037
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2038
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2039
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2040
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2041
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2042
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2043
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2044
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2045
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2046
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2047
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2048
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2049
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2050
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2051
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2052
1.01k
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1110:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2053
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2054
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2055
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2056
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2057
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2058
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2059
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2060
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2061
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2062
1.01k
        // GIR_Coverage, 2726,
2063
1.01k
        GIR_Done,
2064
1.01k
      // Label 105: @3595
2065
1.01k
      GIM_Try, /*On fail goto*//*Label 106*/ 3678, // Rule ID 2729 //
2066
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2067
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2068
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2069
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2070
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2071
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2072
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2073
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2074
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2075
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2076
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2077
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2078
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2079
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2080
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2081
1.01k
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1111:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2082
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2083
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2084
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2085
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2086
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2087
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2088
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2089
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2090
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2091
1.01k
        // GIR_Coverage, 2729,
2092
1.01k
        GIR_Done,
2093
1.01k
      // Label 106: @3678
2094
1.01k
      GIM_Try, /*On fail goto*//*Label 107*/ 3761, // Rule ID 1164 //
2095
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2096
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2097
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2098
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2099
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2100
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2101
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2102
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2103
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2104
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2105
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2106
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2107
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2108
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2109
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2110
1.01k
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1110:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2111
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2112
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2113
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2114
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2115
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2116
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2117
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2118
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2119
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2120
1.01k
        // GIR_Coverage, 1164,
2121
1.01k
        GIR_Done,
2122
1.01k
      // Label 107: @3761
2123
1.01k
      GIM_Try, /*On fail goto*//*Label 108*/ 3844, // Rule ID 1167 //
2124
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2125
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2126
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2127
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2128
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2129
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2130
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2131
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2132
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2133
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2134
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2135
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2136
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2137
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2138
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2139
1.01k
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1111:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2140
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2141
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2142
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2143
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2144
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2145
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2146
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2147
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2148
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2149
1.01k
        // GIR_Coverage, 1167,
2150
1.01k
        GIR_Done,
2151
1.01k
      // Label 108: @3844
2152
1.01k
      GIM_Try, /*On fail goto*//*Label 109*/ 3914, // Rule ID 2718 //
2153
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2154
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2155
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2156
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2157
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2158
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2159
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2160
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2161
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2162
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2163
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2164
1.01k
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1110:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2165
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2166
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2167
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2168
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2169
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2170
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2171
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2172
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2173
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2174
1.01k
        // GIR_Coverage, 2718,
2175
1.01k
        GIR_Done,
2176
1.01k
      // Label 109: @3914
2177
1.01k
      GIM_Try, /*On fail goto*//*Label 110*/ 3984, // Rule ID 2724 //
2178
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2179
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2180
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2181
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2182
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2183
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2184
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2185
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2186
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2187
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2188
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2189
1.01k
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1111:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2190
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2191
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2192
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2193
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2194
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2195
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2196
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2197
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2198
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2199
1.01k
        // GIR_Coverage, 2724,
2200
1.01k
        GIR_Done,
2201
1.01k
      // Label 110: @3984
2202
1.01k
      GIM_Try, /*On fail goto*//*Label 111*/ 4054, // Rule ID 1156 //
2203
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2204
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2205
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2206
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2207
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2208
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2209
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2210
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2211
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2212
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2213
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2214
1.01k
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1110:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2215
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2216
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2217
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2218
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2219
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2220
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2221
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2222
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2223
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2224
1.01k
        // GIR_Coverage, 1156,
2225
1.01k
        GIR_Done,
2226
1.01k
      // Label 111: @4054
2227
1.01k
      GIM_Try, /*On fail goto*//*Label 112*/ 4124, // Rule ID 1162 //
2228
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2229
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2230
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2231
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2232
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2233
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2234
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2235
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2236
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2237
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2238
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2239
1.01k
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1111:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2240
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2241
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2242
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2243
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2244
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2245
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2246
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2247
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2248
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2249
1.01k
        // GIR_Coverage, 1162,
2250
1.01k
        GIR_Done,
2251
1.01k
      // Label 112: @4124
2252
1.01k
      GIM_Try, /*On fail goto*//*Label 113*/ 4188, // Rule ID 768 //
2253
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2254
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2255
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2256
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2257
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2258
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2259
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2260
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2261
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2262
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2263
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2264
1.01k
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2265
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv4i32,
2266
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2267
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2268
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2269
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2270
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2271
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2272
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2273
1.01k
        // GIR_Coverage, 768,
2274
1.01k
        GIR_Done,
2275
1.01k
      // Label 113: @4188
2276
1.01k
      GIM_Try, /*On fail goto*//*Label 114*/ 4252, // Rule ID 771 //
2277
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2278
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2279
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2280
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2281
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2282
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2283
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2284
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2285
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2286
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2287
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2288
1.01k
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2289
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2290
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2291
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2292
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2293
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2294
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2295
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2296
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2297
1.01k
        // GIR_Coverage, 771,
2298
1.01k
        GIR_Done,
2299
1.01k
      // Label 114: @4252
2300
1.01k
      GIM_Try, /*On fail goto*//*Label 115*/ 4315, // Rule ID 2648 //
2301
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2302
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2303
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2304
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2305
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2306
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2307
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2308
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2309
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2310
1.01k
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2311
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2312
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2313
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2314
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2315
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2316
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2317
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2318
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2319
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2320
1.01k
        // GIR_Coverage, 2648,
2321
1.01k
        GIR_Done,
2322
1.01k
      // Label 115: @4315
2323
1.01k
      GIM_Try, /*On fail goto*//*Label 116*/ 4366, // Rule ID 2620 //
2324
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2325
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2326
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2327
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2328
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2329
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2330
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2331
1.01k
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2332
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2333
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2334
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2335
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2336
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2337
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2338
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2339
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2340
1.01k
        // GIR_Coverage, 2620,
2341
1.01k
        GIR_Done,
2342
1.01k
      // Label 116: @4366
2343
1.01k
      GIM_Try, /*On fail goto*//*Label 117*/ 4417, // Rule ID 2623 //
2344
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2345
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2346
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2347
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2348
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2349
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2350
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2351
1.01k
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2352
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2353
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2354
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2355
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2356
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2357
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2358
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2359
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2360
1.01k
        // GIR_Coverage, 2623,
2361
1.01k
        GIR_Done,
2362
1.01k
      // Label 117: @4417
2363
1.01k
      GIM_Try, /*On fail goto*//*Label 118*/ 4480, // Rule ID 879 //
2364
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2365
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2366
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2367
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2368
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2369
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2370
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2371
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2372
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2373
1.01k
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2374
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2375
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2376
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2377
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2378
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2379
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2380
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2381
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2382
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2383
1.01k
        // GIR_Coverage, 879,
2384
1.01k
        GIR_Done,
2385
1.01k
      // Label 118: @4480
2386
1.01k
      GIM_Try, /*On fail goto*//*Label 119*/ 4531, // Rule ID 774 //
2387
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2388
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2389
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2390
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2391
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2392
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2393
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2394
1.01k
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2395
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2396
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2397
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2398
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2399
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2400
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2401
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2402
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2403
1.01k
        // GIR_Coverage, 774,
2404
1.01k
        GIR_Done,
2405
1.01k
      // Label 119: @4531
2406
1.01k
      GIM_Try, /*On fail goto*//*Label 120*/ 4582, // Rule ID 777 //
2407
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2408
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2409
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2410
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2411
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2412
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2413
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2414
1.01k
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2415
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2416
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2417
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2418
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2419
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2420
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2421
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2422
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2423
1.01k
        // GIR_Coverage, 777,
2424
1.01k
        GIR_Done,
2425
1.01k
      // Label 120: @4582
2426
1.01k
      GIM_Try, /*On fail goto*//*Label 121*/ 4620, // Rule ID 760 //
2427
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2428
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2429
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2430
1.01k
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2431
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i32,
2432
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2433
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2434
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2435
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2436
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2437
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2438
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2439
1.01k
        // GIR_Coverage, 760,
2440
1.01k
        GIR_Done,
2441
1.01k
      // Label 121: @4620
2442
1.01k
      GIM_Reject,
2443
1.01k
    // Label 104: @4621
2444
1.01k
    GIM_Reject,
2445
1.01k
    // Label 46: @4622
2446
1.01k
    GIM_Try, /*On fail goto*//*Label 122*/ 5081,
2447
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
2448
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
2449
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
2450
1.01k
      GIM_Try, /*On fail goto*//*Label 123*/ 4706, // Rule ID 2713 //
2451
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2452
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2453
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2454
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2455
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2456
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2457
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2458
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2459
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2460
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2461
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2462
1.01k
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1110:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2463
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2464
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2465
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2466
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2467
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2468
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2469
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2470
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2471
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2472
1.01k
        // GIR_Coverage, 2713,
2473
1.01k
        GIR_Done,
2474
1.01k
      // Label 123: @4706
2475
1.01k
      GIM_Try, /*On fail goto*//*Label 124*/ 4776, // Rule ID 2719 //
2476
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2477
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2478
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2479
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2480
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2481
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2482
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2483
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2484
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2485
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2486
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2487
1.01k
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1111:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2488
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2489
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2490
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2491
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2492
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2493
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2494
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2495
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2496
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2497
1.01k
        // GIR_Coverage, 2719,
2498
1.01k
        GIR_Done,
2499
1.01k
      // Label 124: @4776
2500
1.01k
      GIM_Try, /*On fail goto*//*Label 125*/ 4846, // Rule ID 1151 //
2501
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2502
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2503
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2504
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2505
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2506
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2507
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2508
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2509
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2510
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2511
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2512
1.01k
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1110:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2513
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2514
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2515
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2516
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2517
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2518
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2519
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2520
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2521
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2522
1.01k
        // GIR_Coverage, 1151,
2523
1.01k
        GIR_Done,
2524
1.01k
      // Label 125: @4846
2525
1.01k
      GIM_Try, /*On fail goto*//*Label 126*/ 4916, // Rule ID 1157 //
2526
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2527
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2528
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2529
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2530
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2531
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2532
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2533
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2534
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2535
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2536
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2537
1.01k
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1111:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2538
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2539
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2540
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2541
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2542
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2543
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2544
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2545
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2546
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2547
1.01k
        // GIR_Coverage, 1157,
2548
1.01k
        GIR_Done,
2549
1.01k
      // Label 126: @4916
2550
1.01k
      GIM_Try, /*On fail goto*//*Label 127*/ 4979, // Rule ID 2643 //
2551
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2552
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2553
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2554
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2555
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2556
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2557
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2558
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2559
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2560
1.01k
        // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2561
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2562
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2563
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2564
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2565
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2566
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2567
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2568
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2569
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2570
1.01k
        // GIR_Coverage, 2643,
2571
1.01k
        GIR_Done,
2572
1.01k
      // Label 127: @4979
2573
1.01k
      GIM_Try, /*On fail goto*//*Label 128*/ 5042, // Rule ID 874 //
2574
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2575
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2576
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2577
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2578
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2579
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2580
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2581
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2582
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2583
1.01k
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2584
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2585
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2586
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2587
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2588
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2589
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2590
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2591
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2592
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2593
1.01k
        // GIR_Coverage, 874,
2594
1.01k
        GIR_Done,
2595
1.01k
      // Label 128: @5042
2596
1.01k
      GIM_Try, /*On fail goto*//*Label 129*/ 5080, // Rule ID 755 //
2597
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2598
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2599
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2600
1.01k
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2601
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i8,
2602
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2603
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2604
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2605
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2606
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2607
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2608
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2609
1.01k
        // GIR_Coverage, 755,
2610
1.01k
        GIR_Done,
2611
1.01k
      // Label 129: @5080
2612
1.01k
      GIM_Reject,
2613
1.01k
    // Label 122: @5081
2614
1.01k
    GIM_Reject,
2615
1.01k
    // Label 47: @5082
2616
1.01k
    GIM_Try, /*On fail goto*//*Label 130*/ 6205,
2617
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2618
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2619
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2620
1.01k
      GIM_Try, /*On fail goto*//*Label 131*/ 5179, // Rule ID 2725 //
2621
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2622
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2623
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2624
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2625
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2626
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2627
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2628
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2629
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2630
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2631
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2632
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2633
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2634
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2635
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2636
1.01k
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1110:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2637
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2638
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2639
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2640
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2641
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2642
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2643
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2644
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2645
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2646
1.01k
        // GIR_Coverage, 2725,
2647
1.01k
        GIR_Done,
2648
1.01k
      // Label 131: @5179
2649
1.01k
      GIM_Try, /*On fail goto*//*Label 132*/ 5262, // Rule ID 2728 //
2650
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2651
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2652
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2653
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2654
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2655
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2656
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2657
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2658
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2659
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2660
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2661
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2662
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2663
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2664
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2665
1.01k
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1111:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2666
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2667
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2668
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2669
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2670
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2671
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2672
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2673
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2674
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2675
1.01k
        // GIR_Coverage, 2728,
2676
1.01k
        GIR_Done,
2677
1.01k
      // Label 132: @5262
2678
1.01k
      GIM_Try, /*On fail goto*//*Label 133*/ 5345, // Rule ID 1163 //
2679
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2680
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2681
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2682
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2683
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2684
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2685
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2686
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2687
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2688
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2689
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2690
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2691
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2692
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2693
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2694
1.01k
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1110:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2695
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2696
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2697
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2698
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2699
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2700
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2701
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2702
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2703
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2704
1.01k
        // GIR_Coverage, 1163,
2705
1.01k
        GIR_Done,
2706
1.01k
      // Label 133: @5345
2707
1.01k
      GIM_Try, /*On fail goto*//*Label 134*/ 5428, // Rule ID 1166 //
2708
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2709
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2710
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2711
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2712
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2713
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2714
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2715
1.01k
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2716
1.01k
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2717
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2718
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2719
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2720
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2721
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2722
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2723
1.01k
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1111:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2724
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2725
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2726
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2727
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2728
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2729
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2730
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2731
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2732
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2733
1.01k
        // GIR_Coverage, 1166,
2734
1.01k
        GIR_Done,
2735
1.01k
      // Label 134: @5428
2736
1.01k
      GIM_Try, /*On fail goto*//*Label 135*/ 5498, // Rule ID 2717 //
2737
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2738
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2739
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2740
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2741
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2742
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2743
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2744
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2745
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2746
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2747
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2748
1.01k
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1110:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2749
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
2750
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2751
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2752
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2753
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2754
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2755
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2756
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2757
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2758
1.01k
        // GIR_Coverage, 2717,
2759
1.01k
        GIR_Done,
2760
1.01k
      // Label 135: @5498
2761
1.01k
      GIM_Try, /*On fail goto*//*Label 136*/ 5568, // Rule ID 2723 //
2762
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2763
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2764
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2765
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2766
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2767
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2768
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2769
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2770
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2771
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2772
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2773
1.01k
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1111:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2774
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
2775
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2776
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2777
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2778
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2779
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2780
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2781
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2782
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2783
1.01k
        // GIR_Coverage, 2723,
2784
1.01k
        GIR_Done,
2785
1.01k
      // Label 136: @5568
2786
1.01k
      GIM_Try, /*On fail goto*//*Label 137*/ 5638, // Rule ID 1155 //
2787
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2788
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2789
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2790
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2791
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2792
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2793
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2794
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2795
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2796
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2797
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2798
1.01k
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1110:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2799
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
2800
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2801
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2802
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2803
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2804
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2805
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2806
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2807
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2808
1.01k
        // GIR_Coverage, 1155,
2809
1.01k
        GIR_Done,
2810
1.01k
      // Label 137: @5638
2811
1.01k
      GIM_Try, /*On fail goto*//*Label 138*/ 5708, // Rule ID 1161 //
2812
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2813
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2814
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2815
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2816
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2817
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2818
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2819
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2820
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2821
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2822
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2823
1.01k
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1111:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2824
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
2825
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2826
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2827
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2828
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2829
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2830
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2831
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2832
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2833
1.01k
        // GIR_Coverage, 1161,
2834
1.01k
        GIR_Done,
2835
1.01k
      // Label 138: @5708
2836
1.01k
      GIM_Try, /*On fail goto*//*Label 139*/ 5772, // Rule ID 767 //
2837
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2838
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2839
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2840
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2841
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2842
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2843
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2844
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
2845
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2846
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2847
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2848
1.01k
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2849
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv8i16,
2850
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2851
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2852
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2853
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2854
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2855
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2856
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2857
1.01k
        // GIR_Coverage, 767,
2858
1.01k
        GIR_Done,
2859
1.01k
      // Label 139: @5772
2860
1.01k
      GIM_Try, /*On fail goto*//*Label 140*/ 5836, // Rule ID 770 //
2861
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2862
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2863
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2864
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2865
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2866
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2867
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2868
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
2869
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2870
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2871
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2872
1.01k
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2873
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
2874
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2875
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2876
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2877
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2878
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2879
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2880
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2881
1.01k
        // GIR_Coverage, 770,
2882
1.01k
        GIR_Done,
2883
1.01k
      // Label 140: @5836
2884
1.01k
      GIM_Try, /*On fail goto*//*Label 141*/ 5899, // Rule ID 2647 //
2885
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2886
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2887
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2888
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2889
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2890
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2891
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2892
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2893
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2894
1.01k
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2895
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
2896
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2897
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2898
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2899
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2900
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2901
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2902
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2903
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2904
1.01k
        // GIR_Coverage, 2647,
2905
1.01k
        GIR_Done,
2906
1.01k
      // Label 141: @5899
2907
1.01k
      GIM_Try, /*On fail goto*//*Label 142*/ 5950, // Rule ID 2619 //
2908
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2909
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2910
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2911
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2912
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2913
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2914
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2915
1.01k
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2916
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
2917
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2918
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2919
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2920
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2921
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2922
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2923
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2924
1.01k
        // GIR_Coverage, 2619,
2925
1.01k
        GIR_Done,
2926
1.01k
      // Label 142: @5950
2927
1.01k
      GIM_Try, /*On fail goto*//*Label 143*/ 6001, // Rule ID 2622 //
2928
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2929
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2930
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2931
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2932
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2933
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2934
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2935
1.01k
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2936
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
2937
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2938
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2939
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2940
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2941
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2942
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2943
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2944
1.01k
        // GIR_Coverage, 2622,
2945
1.01k
        GIR_Done,
2946
1.01k
      // Label 143: @6001
2947
1.01k
      GIM_Try, /*On fail goto*//*Label 144*/ 6064, // Rule ID 878 //
2948
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2949
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2950
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2951
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2952
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2953
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2954
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2955
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2956
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2957
1.01k
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2958
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
2959
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2960
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2961
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2962
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2963
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2964
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2965
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2966
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2967
1.01k
        // GIR_Coverage, 878,
2968
1.01k
        GIR_Done,
2969
1.01k
      // Label 144: @6064
2970
1.01k
      GIM_Try, /*On fail goto*//*Label 145*/ 6115, // Rule ID 773 //
2971
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2972
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2973
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2974
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2975
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2976
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2977
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2978
1.01k
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2979
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
2980
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2981
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2982
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2983
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2984
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2985
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
2986
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2987
1.01k
        // GIR_Coverage, 773,
2988
1.01k
        GIR_Done,
2989
1.01k
      // Label 145: @6115
2990
1.01k
      GIM_Try, /*On fail goto*//*Label 146*/ 6166, // Rule ID 776 //
2991
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
2992
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2993
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2994
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2995
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2996
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2997
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2998
1.01k
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2999
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3000
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3001
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3002
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3003
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3004
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3005
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3006
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3007
1.01k
        // GIR_Coverage, 776,
3008
1.01k
        GIR_Done,
3009
1.01k
      // Label 146: @6166
3010
1.01k
      GIM_Try, /*On fail goto*//*Label 147*/ 6204, // Rule ID 759 //
3011
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3012
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3013
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3014
1.01k
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3015
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i16,
3016
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3017
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3018
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3019
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3020
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3021
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3022
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3023
1.01k
        // GIR_Coverage, 759,
3024
1.01k
        GIR_Done,
3025
1.01k
      // Label 147: @6204
3026
1.01k
      GIM_Reject,
3027
1.01k
    // Label 130: @6205
3028
1.01k
    GIM_Reject,
3029
1.01k
    // Label 48: @6206
3030
1.01k
    GIM_Try, /*On fail goto*//*Label 148*/ 6665,
3031
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3032
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3033
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3034
1.01k
      GIM_Try, /*On fail goto*//*Label 149*/ 6290, // Rule ID 2716 //
3035
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3036
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3037
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3038
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3039
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3040
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3041
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3042
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3043
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3044
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3045
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3046
1.01k
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1110:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3047
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3048
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3049
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3050
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3051
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3052
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3053
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3054
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3055
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3056
1.01k
        // GIR_Coverage, 2716,
3057
1.01k
        GIR_Done,
3058
1.01k
      // Label 149: @6290
3059
1.01k
      GIM_Try, /*On fail goto*//*Label 150*/ 6360, // Rule ID 2722 //
3060
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3061
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3062
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3063
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3064
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3065
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3066
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3067
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3068
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3069
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3070
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3071
1.01k
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1111:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3072
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3073
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3074
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3075
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3076
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3077
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3078
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3079
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3080
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3081
1.01k
        // GIR_Coverage, 2722,
3082
1.01k
        GIR_Done,
3083
1.01k
      // Label 150: @6360
3084
1.01k
      GIM_Try, /*On fail goto*//*Label 151*/ 6430, // Rule ID 1154 //
3085
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3086
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3087
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3088
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3089
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3090
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3091
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3092
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3093
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3094
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3095
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3096
1.01k
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1110:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3097
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3098
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3099
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3100
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3101
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3102
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3103
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3104
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3105
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3106
1.01k
        // GIR_Coverage, 1154,
3107
1.01k
        GIR_Done,
3108
1.01k
      // Label 151: @6430
3109
1.01k
      GIM_Try, /*On fail goto*//*Label 152*/ 6500, // Rule ID 1160 //
3110
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3111
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3112
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3113
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3114
1.01k
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3115
1.01k
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3116
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3117
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3118
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3119
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3120
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3121
1.01k
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1111:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3122
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3123
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3124
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3125
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3126
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3127
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3128
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3129
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3130
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3131
1.01k
        // GIR_Coverage, 1160,
3132
1.01k
        GIR_Done,
3133
1.01k
      // Label 152: @6500
3134
1.01k
      GIM_Try, /*On fail goto*//*Label 153*/ 6563, // Rule ID 2646 //
3135
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3136
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3137
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3138
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3139
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3140
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3141
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3142
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3143
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3144
1.01k
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3145
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3146
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3147
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3148
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3149
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3150
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3151
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3152
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3153
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3154
1.01k
        // GIR_Coverage, 2646,
3155
1.01k
        GIR_Done,
3156
1.01k
      // Label 153: @6563
3157
1.01k
      GIM_Try, /*On fail goto*//*Label 154*/ 6626, // Rule ID 877 //
3158
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3159
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3160
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3161
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3162
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3163
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3164
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3165
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3166
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3167
1.01k
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3168
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3169
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3170
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3171
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3172
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3173
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3174
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3175
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3176
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3177
1.01k
        // GIR_Coverage, 877,
3178
1.01k
        GIR_Done,
3179
1.01k
      // Label 154: @6626
3180
1.01k
      GIM_Try, /*On fail goto*//*Label 155*/ 6664, // Rule ID 758 //
3181
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3182
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3183
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3184
1.01k
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3185
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv16i8,
3186
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3187
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3188
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3189
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3190
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3191
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3192
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3193
1.01k
        // GIR_Coverage, 758,
3194
1.01k
        GIR_Done,
3195
1.01k
      // Label 155: @6664
3196
1.01k
      GIM_Reject,
3197
1.01k
    // Label 148: @6665
3198
1.01k
    GIM_Reject,
3199
1.01k
    // Label 49: @6666
3200
1.01k
    GIM_Reject,
3201
1.01k
    // Label 1: @6667
3202
1.01k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 165*/ 8656,
3203
1.01k
    /*GILLT_s32*//*Label 156*/ 6682,
3204
1.01k
    /*GILLT_s64*//*Label 157*/ 7175,
3205
1.01k
    /*GILLT_v2s32*//*Label 158*/ 7226,
3206
1.01k
    /*GILLT_v2s64*//*Label 159*/ 7339,
3207
1.01k
    /*GILLT_v4s16*//*Label 160*/ 7623,
3208
1.01k
    /*GILLT_v4s32*//*Label 161*/ 7736,
3209
1.01k
    /*GILLT_v8s8*//*Label 162*/ 8083,
3210
1.01k
    /*GILLT_v8s16*//*Label 163*/ 8196,
3211
1.01k
    /*GILLT_v16s8*//*Label 164*/ 8543,
3212
1.01k
    // Label 156: @6682
3213
1.01k
    GIM_Try, /*On fail goto*//*Label 166*/ 7174,
3214
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3215
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3216
1.01k
      GIM_Try, /*On fail goto*//*Label 167*/ 6744, // Rule ID 98 //
3217
1.01k
        GIM_CheckFeatures, GIFBS_IsARM,
3218
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3219
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3220
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3221
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3222
1.01k
        // MIs[1] Operand 1
3223
1.01k
        // No operand predicates
3224
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3225
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3226
1.01k
        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn)  =>  (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3227
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RSBri,
3228
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3229
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3230
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3231
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3232
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3233
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3234
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3235
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3236
1.01k
        // GIR_Coverage, 98,
3237
1.01k
        GIR_Done,
3238
1.01k
      // Label 167: @6744
3239
1.01k
      GIM_Try, /*On fail goto*//*Label 168*/ 6796, // Rule ID 432 //
3240
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
3241
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3242
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3243
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3244
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
3245
1.01k
        // MIs[1] Operand 1
3246
1.01k
        // No operand predicates
3247
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3248
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3249
1.01k
        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn)  =>  (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3250
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RSBri,
3251
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3252
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3253
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3254
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3255
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3256
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3257
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3258
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3259
1.01k
        // GIR_Coverage, 432,
3260
1.01k
        GIR_Done,
3261
1.01k
      // Label 168: @6796
3262
1.01k
      GIM_Try, /*On fail goto*//*Label 169*/ 6848, // Rule ID 78 //
3263
1.01k
        GIM_CheckFeatures, GIFBS_IsARM,
3264
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3265
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3266
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3267
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3268
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3269
1.01k
        // MIs[1] Operand 1
3270
1.01k
        // No operand predicates
3271
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3272
1.01k
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3273
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBri,
3274
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3275
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3276
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3277
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3278
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3279
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3280
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3281
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3282
1.01k
        // GIR_Coverage, 78,
3283
1.01k
        GIR_Done,
3284
1.01k
      // Label 169: @6848
3285
1.01k
      GIM_Try, /*On fail goto*//*Label 170*/ 6900, // Rule ID 416 //
3286
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
3287
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3288
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
3289
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3290
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3291
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
3292
1.01k
        // MIs[1] Operand 1
3293
1.01k
        // No operand predicates
3294
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3295
1.01k
        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3296
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri,
3297
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3298
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3299
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3300
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3301
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3302
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3303
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3304
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3305
1.01k
        // GIR_Coverage, 416,
3306
1.01k
        GIR_Done,
3307
1.01k
      // Label 170: @6900
3308
1.01k
      GIM_Try, /*On fail goto*//*Label 171*/ 6949, // Rule ID 417 //
3309
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
3310
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3311
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3312
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3313
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3314
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
3315
1.01k
        // MIs[1] Operand 1
3316
1.01k
        // No operand predicates
3317
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3318
1.01k
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3319
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri12,
3320
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3321
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3322
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3323
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3324
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3325
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3326
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3327
1.01k
        // GIR_Coverage, 417,
3328
1.01k
        GIR_Done,
3329
1.01k
      // Label 171: @6949
3330
1.01k
      GIM_Try, /*On fail goto*//*Label 172*/ 7016, // Rule ID 175 //
3331
1.01k
        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM_UseMulOps,
3332
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3333
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3334
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3335
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3336
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3337
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3338
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3339
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3340
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3341
1.01k
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm))  =>  (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
3342
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLS,
3343
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3344
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3345
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3346
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3347
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3348
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3349
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3350
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3351
1.01k
        // GIR_Coverage, 175,
3352
1.01k
        GIR_Done,
3353
1.01k
      // Label 172: @7016
3354
1.01k
      GIM_Try, /*On fail goto*//*Label 173*/ 7083, // Rule ID 509 //
3355
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
3356
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3357
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3358
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3359
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3360
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3361
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3362
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3363
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3364
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3365
1.01k
        // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
3366
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLS,
3367
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3368
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3369
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3370
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3371
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3372
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3373
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3374
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3375
1.01k
        // GIR_Coverage, 509,
3376
1.01k
        GIR_Done,
3377
1.01k
      // Label 173: @7083
3378
1.01k
      GIM_Try, /*On fail goto*//*Label 174*/ 7128, // Rule ID 79 //
3379
1.01k
        GIM_CheckFeatures, GIFBS_IsARM,
3380
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3381
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3382
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3383
1.01k
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
3384
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBrr,
3385
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3386
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3387
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
3388
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3389
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3390
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3391
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3392
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3393
1.01k
        // GIR_Coverage, 79,
3394
1.01k
        GIR_Done,
3395
1.01k
      // Label 174: @7128
3396
1.01k
      GIM_Try, /*On fail goto*//*Label 175*/ 7173, // Rule ID 418 //
3397
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
3398
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3399
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
3400
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3401
1.01k
        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
3402
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBrr,
3403
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3404
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3405
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
3406
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3407
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3408
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3409
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3410
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3411
1.01k
        // GIR_Coverage, 418,
3412
1.01k
        GIR_Done,
3413
1.01k
      // Label 175: @7173
3414
1.01k
      GIM_Reject,
3415
1.01k
    // Label 166: @7174
3416
1.01k
    GIM_Reject,
3417
1.01k
    // Label 157: @7175
3418
1.01k
    GIM_Try, /*On fail goto*//*Label 176*/ 7225, // Rule ID 948 //
3419
1.01k
      GIM_CheckFeatures, GIFBS_HasNEON,
3420
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3421
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3422
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3423
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3424
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3425
1.01k
      // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
3426
1.01k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv1i64,
3427
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3428
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3429
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3430
1.01k
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3431
1.01k
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3432
1.01k
      GIR_EraseFromParent, /*InsnID*/0,
3433
1.01k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3434
1.01k
      // GIR_Coverage, 948,
3435
1.01k
      GIR_Done,
3436
1.01k
    // Label 176: @7225
3437
1.01k
    GIM_Reject,
3438
1.01k
    // Label 158: @7226
3439
1.01k
    GIM_Try, /*On fail goto*//*Label 177*/ 7338,
3440
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
3441
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
3442
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3443
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3444
1.01k
      GIM_Try, /*On fail goto*//*Label 178*/ 7303, // Rule ID 904 //
3445
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3446
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3447
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3448
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3449
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3450
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3451
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3452
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3453
1.01k
        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3454
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv2i32,
3455
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3456
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3457
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3458
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3459
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3460
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3461
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3462
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3463
1.01k
        // GIR_Coverage, 904,
3464
1.01k
        GIR_Done,
3465
1.01k
      // Label 178: @7303
3466
1.01k
      GIM_Try, /*On fail goto*//*Label 179*/ 7337, // Rule ID 944 //
3467
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3468
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3469
1.01k
        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3470
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i32,
3471
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3472
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3473
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3474
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3475
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3476
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3477
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3478
1.01k
        // GIR_Coverage, 944,
3479
1.01k
        GIR_Done,
3480
1.01k
      // Label 179: @7337
3481
1.01k
      GIM_Reject,
3482
1.01k
    // Label 177: @7338
3483
1.01k
    GIM_Reject,
3484
1.01k
    // Label 159: @7339
3485
1.01k
    GIM_Try, /*On fail goto*//*Label 180*/ 7622,
3486
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3487
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
3488
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3489
1.01k
      GIM_Try, /*On fail goto*//*Label 181*/ 7417, // Rule ID 956 //
3490
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3491
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3492
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3493
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3494
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3495
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3496
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3497
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3498
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3499
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3500
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3501
1.01k
        // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3502
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv2i64,
3503
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3504
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3505
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3506
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3507
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3508
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3509
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3510
1.01k
        // GIR_Coverage, 956,
3511
1.01k
        GIR_Done,
3512
1.01k
      // Label 181: @7417
3513
1.01k
      GIM_Try, /*On fail goto*//*Label 182*/ 7481, // Rule ID 959 //
3514
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3515
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3516
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3517
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3518
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3519
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3520
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3521
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3522
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3523
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3524
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3525
1.01k
        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3526
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
3527
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3528
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3529
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3530
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3531
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3532
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3533
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3534
1.01k
        // GIR_Coverage, 959,
3535
1.01k
        GIR_Done,
3536
1.01k
      // Label 182: @7481
3537
1.01k
      GIM_Try, /*On fail goto*//*Label 183*/ 7532, // Rule ID 962 //
3538
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3539
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3540
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3541
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3542
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3543
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3544
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3545
1.01k
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3546
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv2i64,
3547
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3548
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3549
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3550
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3551
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3552
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3553
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3554
1.01k
        // GIR_Coverage, 962,
3555
1.01k
        GIR_Done,
3556
1.01k
      // Label 183: @7532
3557
1.01k
      GIM_Try, /*On fail goto*//*Label 184*/ 7583, // Rule ID 965 //
3558
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3559
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3560
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3561
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3562
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3563
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3564
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3565
1.01k
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3566
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv2i64,
3567
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3568
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3569
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3570
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3571
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3572
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3573
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3574
1.01k
        // GIR_Coverage, 965,
3575
1.01k
        GIR_Done,
3576
1.01k
      // Label 184: @7583
3577
1.01k
      GIM_Try, /*On fail goto*//*Label 185*/ 7621, // Rule ID 949 //
3578
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3579
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3580
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3581
1.01k
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
3582
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i64,
3583
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3584
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3585
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3586
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3587
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3588
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3589
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3590
1.01k
        // GIR_Coverage, 949,
3591
1.01k
        GIR_Done,
3592
1.01k
      // Label 185: @7621
3593
1.01k
      GIM_Reject,
3594
1.01k
    // Label 180: @7622
3595
1.01k
    GIM_Reject,
3596
1.01k
    // Label 160: @7623
3597
1.01k
    GIM_Try, /*On fail goto*//*Label 186*/ 7735,
3598
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
3599
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
3600
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3601
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3602
1.01k
      GIM_Try, /*On fail goto*//*Label 187*/ 7700, // Rule ID 903 //
3603
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3604
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3605
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3606
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3607
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3608
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3609
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3610
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3611
1.01k
        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3612
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i16,
3613
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3614
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3615
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3616
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3617
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3618
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3619
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3620
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3621
1.01k
        // GIR_Coverage, 903,
3622
1.01k
        GIR_Done,
3623
1.01k
      // Label 187: @7700
3624
1.01k
      GIM_Try, /*On fail goto*//*Label 188*/ 7734, // Rule ID 943 //
3625
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3626
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3627
1.01k
        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3628
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i16,
3629
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3630
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3631
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3632
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3633
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3634
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3635
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3636
1.01k
        // GIR_Coverage, 943,
3637
1.01k
        GIR_Done,
3638
1.01k
      // Label 188: @7734
3639
1.01k
      GIM_Reject,
3640
1.01k
    // Label 186: @7735
3641
1.01k
    GIM_Reject,
3642
1.01k
    // Label 161: @7736
3643
1.01k
    GIM_Try, /*On fail goto*//*Label 189*/ 8082,
3644
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3645
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
3646
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3647
1.01k
      GIM_Try, /*On fail goto*//*Label 190*/ 7814, // Rule ID 955 //
3648
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3649
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3650
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3651
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3652
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3653
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3654
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3655
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3656
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3657
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3658
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3659
1.01k
        // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3660
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv4i32,
3661
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3662
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3663
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3664
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3665
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3666
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3667
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3668
1.01k
        // GIR_Coverage, 955,
3669
1.01k
        GIR_Done,
3670
1.01k
      // Label 190: @7814
3671
1.01k
      GIM_Try, /*On fail goto*//*Label 191*/ 7878, // Rule ID 958 //
3672
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3673
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3674
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3675
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3676
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3677
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3678
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3679
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3680
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3681
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3682
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3683
1.01k
        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3684
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
3685
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3686
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3687
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3688
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3689
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3690
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3691
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3692
1.01k
        // GIR_Coverage, 958,
3693
1.01k
        GIR_Done,
3694
1.01k
      // Label 191: @7878
3695
1.01k
      GIM_Try, /*On fail goto*//*Label 192*/ 7941, // Rule ID 907 //
3696
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3697
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3698
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3699
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3700
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3701
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3702
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3703
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3704
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3705
1.01k
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3706
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i32,
3707
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3708
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3709
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3710
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3711
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3712
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3713
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3714
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3715
1.01k
        // GIR_Coverage, 907,
3716
1.01k
        GIR_Done,
3717
1.01k
      // Label 192: @7941
3718
1.01k
      GIM_Try, /*On fail goto*//*Label 193*/ 7992, // Rule ID 961 //
3719
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3720
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3721
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3722
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3723
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3724
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3725
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3726
1.01k
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3727
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv4i32,
3728
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3729
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3730
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3731
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3732
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3733
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3734
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3735
1.01k
        // GIR_Coverage, 961,
3736
1.01k
        GIR_Done,
3737
1.01k
      // Label 193: @7992
3738
1.01k
      GIM_Try, /*On fail goto*//*Label 194*/ 8043, // Rule ID 964 //
3739
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3740
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3741
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3742
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3743
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3744
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3745
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3746
1.01k
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3747
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv4i32,
3748
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3749
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3750
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3751
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3752
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3753
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3754
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3755
1.01k
        // GIR_Coverage, 964,
3756
1.01k
        GIR_Done,
3757
1.01k
      // Label 194: @8043
3758
1.01k
      GIM_Try, /*On fail goto*//*Label 195*/ 8081, // Rule ID 947 //
3759
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3760
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3761
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3762
1.01k
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3763
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i32,
3764
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3765
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3766
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3767
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3768
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3769
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3770
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3771
1.01k
        // GIR_Coverage, 947,
3772
1.01k
        GIR_Done,
3773
1.01k
      // Label 195: @8081
3774
1.01k
      GIM_Reject,
3775
1.01k
    // Label 189: @8082
3776
1.01k
    GIM_Reject,
3777
1.01k
    // Label 162: @8083
3778
1.01k
    GIM_Try, /*On fail goto*//*Label 196*/ 8195,
3779
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
3780
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
3781
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3782
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3783
1.01k
      GIM_Try, /*On fail goto*//*Label 197*/ 8160, // Rule ID 902 //
3784
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3785
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3786
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3787
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3788
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3789
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3790
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3791
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3792
1.01k
        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3793
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i8,
3794
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3795
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3796
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3797
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3798
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3799
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3800
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3801
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3802
1.01k
        // GIR_Coverage, 902,
3803
1.01k
        GIR_Done,
3804
1.01k
      // Label 197: @8160
3805
1.01k
      GIM_Try, /*On fail goto*//*Label 198*/ 8194, // Rule ID 942 //
3806
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3807
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3808
1.01k
        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3809
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i8,
3810
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3811
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3812
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3813
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3814
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3815
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3816
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3817
1.01k
        // GIR_Coverage, 942,
3818
1.01k
        GIR_Done,
3819
1.01k
      // Label 198: @8194
3820
1.01k
      GIM_Reject,
3821
1.01k
    // Label 196: @8195
3822
1.01k
    GIM_Reject,
3823
1.01k
    // Label 163: @8196
3824
1.01k
    GIM_Try, /*On fail goto*//*Label 199*/ 8542,
3825
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3826
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
3827
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3828
1.01k
      GIM_Try, /*On fail goto*//*Label 200*/ 8274, // Rule ID 954 //
3829
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3830
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3831
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3832
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3833
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3834
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3835
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3836
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3837
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3838
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3839
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3840
1.01k
        // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3841
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv8i16,
3842
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3843
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3844
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3845
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3846
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3847
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3848
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3849
1.01k
        // GIR_Coverage, 954,
3850
1.01k
        GIR_Done,
3851
1.01k
      // Label 200: @8274
3852
1.01k
      GIM_Try, /*On fail goto*//*Label 201*/ 8338, // Rule ID 957 //
3853
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3854
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3855
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3856
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3857
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3858
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3859
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3860
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3861
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3862
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3863
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3864
1.01k
        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3865
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
3866
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3867
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3868
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3869
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3870
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3871
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3872
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3873
1.01k
        // GIR_Coverage, 957,
3874
1.01k
        GIR_Done,
3875
1.01k
      // Label 201: @8338
3876
1.01k
      GIM_Try, /*On fail goto*//*Label 202*/ 8401, // Rule ID 906 //
3877
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3878
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3879
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3880
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3881
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3882
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3883
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3884
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3885
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3886
1.01k
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3887
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i16,
3888
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3889
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3890
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3891
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3892
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3893
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3894
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3895
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3896
1.01k
        // GIR_Coverage, 906,
3897
1.01k
        GIR_Done,
3898
1.01k
      // Label 202: @8401
3899
1.01k
      GIM_Try, /*On fail goto*//*Label 203*/ 8452, // Rule ID 960 //
3900
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3901
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3902
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3903
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3904
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3905
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3906
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3907
1.01k
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3908
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv8i16,
3909
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3910
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3911
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3912
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3913
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3914
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3915
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3916
1.01k
        // GIR_Coverage, 960,
3917
1.01k
        GIR_Done,
3918
1.01k
      // Label 203: @8452
3919
1.01k
      GIM_Try, /*On fail goto*//*Label 204*/ 8503, // Rule ID 963 //
3920
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3921
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3922
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3923
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3924
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3925
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3926
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3927
1.01k
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3928
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv8i16,
3929
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3930
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3931
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3932
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3933
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3934
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3935
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3936
1.01k
        // GIR_Coverage, 963,
3937
1.01k
        GIR_Done,
3938
1.01k
      // Label 204: @8503
3939
1.01k
      GIM_Try, /*On fail goto*//*Label 205*/ 8541, // Rule ID 946 //
3940
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3941
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3942
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3943
1.01k
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3944
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i16,
3945
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3946
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3947
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3948
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3949
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3950
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3951
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3952
1.01k
        // GIR_Coverage, 946,
3953
1.01k
        GIR_Done,
3954
1.01k
      // Label 205: @8541
3955
1.01k
      GIM_Reject,
3956
1.01k
    // Label 199: @8542
3957
1.01k
    GIM_Reject,
3958
1.01k
    // Label 164: @8543
3959
1.01k
    GIM_Try, /*On fail goto*//*Label 206*/ 8655,
3960
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3961
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3962
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3963
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3964
1.01k
      GIM_Try, /*On fail goto*//*Label 207*/ 8620, // Rule ID 905 //
3965
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3966
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3967
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3968
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3969
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3970
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3971
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3972
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3973
1.01k
        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3974
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv16i8,
3975
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3976
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3977
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3978
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3979
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3980
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3981
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3982
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3983
1.01k
        // GIR_Coverage, 905,
3984
1.01k
        GIR_Done,
3985
1.01k
      // Label 207: @8620
3986
1.01k
      GIM_Try, /*On fail goto*//*Label 208*/ 8654, // Rule ID 945 //
3987
1.01k
        GIM_CheckFeatures, GIFBS_HasNEON,
3988
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3989
1.01k
        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3990
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv16i8,
3991
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3992
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3993
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3994
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3995
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3996
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
3997
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3998
1.01k
        // GIR_Coverage, 945,
3999
1.01k
        GIR_Done,
4000
1.01k
      // Label 208: @8654
4001
1.01k
      GIM_Reject,
4002
1.01k
    // Label 206: @8655
4003
1.01k
    GIM_Reject,
4004
1.01k
    // Label 165: @8656
4005
1.01k
    GIM_Reject,
4006
1.01k
    // Label 2: @8657
4007
1.01k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 216*/ 9290,
4008
1.01k
    /*GILLT_s32*//*Label 209*/ 8672, 0,
4009
1.01k
    /*GILLT_v2s32*//*Label 210*/ 8984, 0,
4010
1.01k
    /*GILLT_v4s16*//*Label 211*/ 9035,
4011
1.01k
    /*GILLT_v4s32*//*Label 212*/ 9086,
4012
1.01k
    /*GILLT_v8s8*//*Label 213*/ 9137,
4013
1.01k
    /*GILLT_v8s16*//*Label 214*/ 9188,
4014
1.01k
    /*GILLT_v16s8*//*Label 215*/ 9239,
4015
1.01k
    // Label 209: @8672
4016
1.01k
    GIM_Try, /*On fail goto*//*Label 217*/ 8983,
4017
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4018
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4019
1.01k
      GIM_Try, /*On fail goto*//*Label 218*/ 8766, // Rule ID 188 //
4020
1.01k
        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
4021
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4022
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4023
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4024
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4025
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4026
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4027
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
4028
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4029
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
4030
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
4031
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4032
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4033
1.01k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
4034
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4035
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4036
1.01k
        // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4037
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
4038
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4039
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4040
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4041
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4042
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4043
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4044
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4045
1.01k
        // GIR_Coverage, 188,
4046
1.01k
        GIR_Done,
4047
1.01k
      // Label 218: @8766
4048
1.01k
      GIM_Try, /*On fail goto*//*Label 219*/ 8850, // Rule ID 520 //
4049
1.01k
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4050
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4051
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4052
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4053
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4054
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4055
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4056
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
4057
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4058
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
4059
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
4060
1.01k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4061
1.01k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4062
1.01k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
4063
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4064
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4065
1.01k
        // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4066
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
4067
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4068
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4069
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4070
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4071
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4072
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4073
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4074
1.01k
        // GIR_Coverage, 520,
4075
1.01k
        GIR_Done,
4076
1.01k
      // Label 219: @8850
4077
1.01k
      GIM_Try, /*On fail goto*//*Label 220*/ 8895, // Rule ID 171 //
4078
1.01k
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4079
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4080
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4081
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4082
1.01k
        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
4083
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MUL,
4084
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4085
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4086
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4087
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4088
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4089
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4090
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4091
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4092
1.01k
        // GIR_Coverage, 171,
4093
1.01k
        GIR_Done,
4094
1.01k
      // Label 220: @8895
4095
1.01k
      GIM_Try, /*On fail goto*//*Label 221*/ 8940, // Rule ID 172 //
4096
1.01k
        GIM_CheckFeatures, GIFBS_IsARM_NoV6_UseMulOps,
4097
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4098
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4099
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4100
1.01k
        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
4101
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MULv5,
4102
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4103
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4104
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4105
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4106
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4107
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4108
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4109
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4110
1.01k
        // GIR_Coverage, 172,
4111
1.01k
        GIR_Done,
4112
1.01k
      // Label 221: @8940
4113
1.01k
      GIM_Try, /*On fail goto*//*Label 222*/ 8982, // Rule ID 507 //
4114
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
4115
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4116
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4117
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4118
1.01k
        // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4119
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MUL,
4120
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4121
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4122
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4123
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4124
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4125
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4126
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4127
1.01k
        // GIR_Coverage, 507,
4128
1.01k
        GIR_Done,
4129
1.01k
      // Label 222: @8982
4130
1.01k
      GIM_Reject,
4131
1.01k
    // Label 217: @8983
4132
1.01k
    GIM_Reject,
4133
1.01k
    // Label 210: @8984
4134
1.01k
    GIM_Try, /*On fail goto*//*Label 223*/ 9034, // Rule ID 824 //
4135
1.01k
      GIM_CheckFeatures, GIFBS_HasNEON,
4136
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
4137
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
4138
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4139
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4140
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4141
1.01k
      // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4142
1.01k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv2i32,
4143
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4144
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4145
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4146
1.01k
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4147
1.01k
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4148
1.01k
      GIR_EraseFromParent, /*InsnID*/0,
4149
1.01k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4150
1.01k
      // GIR_Coverage, 824,
4151
1.01k
      GIR_Done,
4152
1.01k
    // Label 223: @9034
4153
1.01k
    GIM_Reject,
4154
1.01k
    // Label 211: @9035
4155
1.01k
    GIM_Try, /*On fail goto*//*Label 224*/ 9085, // Rule ID 823 //
4156
1.01k
      GIM_CheckFeatures, GIFBS_HasNEON,
4157
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4158
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4159
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4160
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4161
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4162
1.01k
      // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4163
1.01k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i16,
4164
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4165
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4166
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4167
1.01k
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4168
1.01k
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4169
1.01k
      GIR_EraseFromParent, /*InsnID*/0,
4170
1.01k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4171
1.01k
      // GIR_Coverage, 823,
4172
1.01k
      GIR_Done,
4173
1.01k
    // Label 224: @9085
4174
1.01k
    GIM_Reject,
4175
1.01k
    // Label 212: @9086
4176
1.01k
    GIM_Try, /*On fail goto*//*Label 225*/ 9136, // Rule ID 827 //
4177
1.01k
      GIM_CheckFeatures, GIFBS_HasNEON,
4178
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4179
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4180
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4181
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4182
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4183
1.01k
      // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4184
1.01k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i32,
4185
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4186
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4187
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4188
1.01k
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4189
1.01k
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4190
1.01k
      GIR_EraseFromParent, /*InsnID*/0,
4191
1.01k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4192
1.01k
      // GIR_Coverage, 827,
4193
1.01k
      GIR_Done,
4194
1.01k
    // Label 225: @9136
4195
1.01k
    GIM_Reject,
4196
1.01k
    // Label 213: @9137
4197
1.01k
    GIM_Try, /*On fail goto*//*Label 226*/ 9187, // Rule ID 822 //
4198
1.01k
      GIM_CheckFeatures, GIFBS_HasNEON,
4199
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4200
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4201
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4202
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4203
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4204
1.01k
      // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4205
1.01k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i8,
4206
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4207
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4208
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4209
1.01k
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4210
1.01k
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4211
1.01k
      GIR_EraseFromParent, /*InsnID*/0,
4212
1.01k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4213
1.01k
      // GIR_Coverage, 822,
4214
1.01k
      GIR_Done,
4215
1.01k
    // Label 226: @9187
4216
1.01k
    GIM_Reject,
4217
1.01k
    // Label 214: @9188
4218
1.01k
    GIM_Try, /*On fail goto*//*Label 227*/ 9238, // Rule ID 826 //
4219
1.01k
      GIM_CheckFeatures, GIFBS_HasNEON,
4220
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4221
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4222
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4223
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4224
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4225
1.01k
      // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4226
1.01k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i16,
4227
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4228
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4229
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4230
1.01k
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4231
1.01k
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4232
1.01k
      GIR_EraseFromParent, /*InsnID*/0,
4233
1.01k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4234
1.01k
      // GIR_Coverage, 826,
4235
1.01k
      GIR_Done,
4236
1.01k
    // Label 227: @9238
4237
1.01k
    GIM_Reject,
4238
1.01k
    // Label 215: @9239
4239
1.01k
    GIM_Try, /*On fail goto*//*Label 228*/ 9289, // Rule ID 825 //
4240
1.01k
      GIM_CheckFeatures, GIFBS_HasNEON,
4241
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4242
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
4243
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4244
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4245
1.01k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4246
1.01k
      // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4247
1.01k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv16i8,
4248
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4249
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4250
1.01k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4251
1.01k
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4252
1.01k
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4253
1.01k
      GIR_EraseFromParent, /*InsnID*/0,
4254
1.01k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4255
1.01k
      // GIR_Coverage, 825,
4256
1.01k
      GIR_Done,
4257
1.01k
    // Label 228: @9289
4258
1.01k
    GIM_Reject,
4259
1.01k
    // Label 216: @9290
4260
1.01k
    GIM_Reject,
4261
1.01k
    // Label 3: @9291
4262
1.01k
    GIM_Try, /*On fail goto*//*Label 229*/ 9390,
4263
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4264
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4265
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4266
1.01k
      GIM_Try, /*On fail goto*//*Label 230*/ 9347, // Rule ID 197 //
4267
1.01k
        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
4268
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4269
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4270
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4271
1.01k
        // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4272
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SDIV,
4273
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4274
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4275
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4276
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4277
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4278
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4279
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4280
1.01k
        // GIR_Coverage, 197,
4281
1.01k
        GIR_Done,
4282
1.01k
      // Label 230: @9347
4283
1.01k
      GIM_Try, /*On fail goto*//*Label 231*/ 9389, // Rule ID 537 //
4284
1.01k
        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
4285
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4286
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4287
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4288
1.01k
        // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4289
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SDIV,
4290
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4291
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4292
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4293
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4294
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4295
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4296
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4297
1.01k
        // GIR_Coverage, 537,
4298
1.01k
        GIR_Done,
4299
1.01k
      // Label 231: @9389
4300
1.01k
      GIM_Reject,
4301
1.01k
    // Label 229: @9390
4302
1.01k
    GIM_Reject,
4303
1.01k
    // Label 4: @9391
4304
1.01k
    GIM_Try, /*On fail goto*//*Label 232*/ 9490,
4305
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4306
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4307
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4308
1.01k
      GIM_Try, /*On fail goto*//*Label 233*/ 9447, // Rule ID 198 //
4309
1.01k
        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
4310
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4311
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4312
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4313
1.01k
        // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4314
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDIV,
4315
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4316
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4317
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4318
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4319
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4320
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4321
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4322
1.01k
        // GIR_Coverage, 198,
4323
1.01k
        GIR_Done,
4324
1.01k
      // Label 233: @9447
4325
1.01k
      GIM_Try, /*On fail goto*//*Label 234*/ 9489, // Rule ID 538 //
4326
1.01k
        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
4327
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4328
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4329
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4330
1.01k
        // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4331
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDIV,
4332
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4333
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4334
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4335
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4336
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4337
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4338
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4339
1.01k
        // GIR_Coverage, 538,
4340
1.01k
        GIR_Done,
4341
1.01k
      // Label 234: @9489
4342
1.01k
      GIM_Reject,
4343
1.01k
    // Label 232: @9490
4344
1.01k
    GIM_Reject,
4345
1.01k
    // Label 5: @9491
4346
1.01k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 238*/ 11203,
4347
1.01k
    /*GILLT_s32*//*Label 235*/ 9503, 0,
4348
1.01k
    /*GILLT_v2s32*//*Label 236*/ 11101, 0, 0,
4349
1.01k
    /*GILLT_v4s32*//*Label 237*/ 11152,
4350
1.01k
    // Label 235: @9503
4351
1.01k
    GIM_Try, /*On fail goto*//*Label 239*/ 11100,
4352
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4353
1.01k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4354
1.01k
      GIM_Try, /*On fail goto*//*Label 240*/ 9575, // Rule ID 1712 //
4355
1.01k
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4356
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4357
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4358
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
4359
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4360
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4361
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4362
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
4363
1.01k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4364
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4365
1.01k
        // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
4366
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4367
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4368
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
4369
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
4370
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4371
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4372
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4373
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4374
1.01k
        // GIR_Coverage, 1712,
4375
1.01k
        GIR_Done,
4376
1.01k
      // Label 240: @9575
4377
1.01k
      GIM_Try, /*On fail goto*//*Label 241*/ 9637, // Rule ID 1930 //
4378
1.01k
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4379
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4380
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4381
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
4382
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4383
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4384
1.01k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4385
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
4386
1.01k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4387
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4388
1.01k
        // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
4389
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4390
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4391
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
4392
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
4393
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4394
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4395
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4396
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4397
1.01k
        // GIR_Coverage, 1930,
4398
1.01k
        GIR_Done,
4399
1.01k
      // Label 241: @9637
4400
1.01k
      GIM_Try, /*On fail goto*//*Label 242*/ 9678, // Rule ID 1823 //
4401
1.01k
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4402
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4403
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4404
1.01k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
4405
1.01k
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] })  =>  (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4406
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB,
4407
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4408
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4409
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4410
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4411
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4412
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4413
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4414
1.01k
        // GIR_Coverage, 1823,
4415
1.01k
        GIR_Done,
4416
1.01k
      // Label 242: @9678
4417
1.01k
      GIM_Try, /*On fail goto*//*Label 243*/ 9719, // Rule ID 1824 //
4418
1.01k
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4419
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4420
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4421
1.01k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
4422
1.01k
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] })  =>  (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4423
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTH,
4424
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4425
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4426
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4427
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4428
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4429
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4430
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4431
1.01k
        // GIR_Coverage, 1824,
4432
1.01k
        GIR_Done,
4433
1.01k
      // Label 243: @9719
4434
1.01k
      GIM_Try, /*On fail goto*//*Label 244*/ 9760, // Rule ID 1825 //
4435
1.01k
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4436
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4437
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4438
1.01k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4439
1.01k
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4440
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4441
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4442
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4443
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4444
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4445
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4446
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4447
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4448
1.01k
        // GIR_Coverage, 1825,
4449
1.01k
        GIR_Done,
4450
1.01k
      // Label 244: @9760
4451
1.01k
      GIM_Try, /*On fail goto*//*Label 245*/ 9801, // Rule ID 2023 //
4452
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
4453
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4454
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4455
1.01k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
4456
1.01k
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })  =>  (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4457
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB,
4458
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4459
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4460
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4461
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4462
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4463
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4464
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4465
1.01k
        // GIR_Coverage, 2023,
4466
1.01k
        GIR_Done,
4467
1.01k
      // Label 245: @9801
4468
1.01k
      GIM_Try, /*On fail goto*//*Label 246*/ 9842, // Rule ID 2024 //
4469
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
4470
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4471
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4472
1.01k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
4473
1.01k
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })  =>  (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4474
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTH,
4475
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4476
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4477
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4478
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4479
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4480
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4481
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4482
1.01k
        // GIR_Coverage, 2024,
4483
1.01k
        GIR_Done,
4484
1.01k
      // Label 246: @9842
4485
1.01k
      GIM_Try, /*On fail goto*//*Label 247*/ 9883, // Rule ID 2025 //
4486
1.01k
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4487
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4488
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4489
1.01k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4490
1.01k
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4491
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4492
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4493
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4494
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4495
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4496
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4497
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4498
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4499
1.01k
        // GIR_Coverage, 2025,
4500
1.01k
        GIR_Done,
4501
1.01k
      // Label 247: @9883
4502
1.01k
      GIM_Try, /*On fail goto*//*Label 248*/ 9956, // Rule ID 2553 //
4503
1.01k
        GIM_CheckFeatures, GIFBS_IsARM,
4504
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4505
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4506
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4507
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4508
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4509
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4510
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4511
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4512
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4513
1.01k
        // MIs[2] Operand 1
4514
1.01k
        // No operand predicates
4515
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4516
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4517
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4518
1.01k
        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4519
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4520
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4521
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4522
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4523
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4524
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4525
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4526
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4527
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4528
1.01k
        // GIR_Coverage, 2553,
4529
1.01k
        GIR_Done,
4530
1.01k
      // Label 248: @9956
4531
1.01k
      GIM_Try, /*On fail goto*//*Label 249*/ 10029, // Rule ID 2586 //
4532
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
4533
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4534
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4535
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4536
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4537
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4538
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4539
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4540
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4541
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4542
1.01k
        // MIs[2] Operand 1
4543
1.01k
        // No operand predicates
4544
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4545
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4546
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4547
1.01k
        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4548
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4549
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4550
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4551
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4552
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4553
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4554
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4555
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4556
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4557
1.01k
        // GIR_Coverage, 2586,
4558
1.01k
        GIR_Done,
4559
1.01k
      // Label 249: @10029
4560
1.01k
      GIM_Try, /*On fail goto*//*Label 250*/ 10102, // Rule ID 2552 //
4561
1.01k
        GIM_CheckFeatures, GIFBS_IsARM,
4562
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4563
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4564
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4565
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4566
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4567
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4568
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4569
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4570
1.01k
        // MIs[2] Operand 1
4571
1.01k
        // No operand predicates
4572
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4573
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4574
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4575
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4576
1.01k
        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4577
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4578
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4579
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4580
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4581
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4582
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4583
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4584
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4585
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4586
1.01k
        // GIR_Coverage, 2552,
4587
1.01k
        GIR_Done,
4588
1.01k
      // Label 250: @10102
4589
1.01k
      GIM_Try, /*On fail goto*//*Label 251*/ 10175, // Rule ID 2585 //
4590
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
4591
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4592
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4593
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4594
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4595
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4596
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4597
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4598
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4599
1.01k
        // MIs[2] Operand 1
4600
1.01k
        // No operand predicates
4601
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4602
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4603
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4604
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4605
1.01k
        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4606
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4607
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4608
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4609
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4610
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4611
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4612
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4613
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4614
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4615
1.01k
        // GIR_Coverage, 2585,
4616
1.01k
        GIR_Done,
4617
1.01k
      // Label 251: @10175
4618
1.01k
      GIM_Try, /*On fail goto*//*Label 252*/ 10248, // Rule ID 2551 //
4619
1.01k
        GIM_CheckFeatures, GIFBS_IsARM,
4620
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4621
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4622
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4623
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4624
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4625
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4626
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4627
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4628
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4629
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4630
1.01k
        // MIs[2] Operand 1
4631
1.01k
        // No operand predicates
4632
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4633
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4634
1.01k
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4635
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4636
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4637
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4638
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4639
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4640
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4641
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4642
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4643
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4644
1.01k
        // GIR_Coverage, 2551,
4645
1.01k
        GIR_Done,
4646
1.01k
      // Label 252: @10248
4647
1.01k
      GIM_Try, /*On fail goto*//*Label 253*/ 10321, // Rule ID 2584 //
4648
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
4649
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4650
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4651
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4652
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4653
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4654
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4655
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4656
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4657
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4658
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4659
1.01k
        // MIs[2] Operand 1
4660
1.01k
        // No operand predicates
4661
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4662
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4663
1.01k
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4664
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4665
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4666
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4667
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4668
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4669
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4670
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4671
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4672
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4673
1.01k
        // GIR_Coverage, 2584,
4674
1.01k
        GIR_Done,
4675
1.01k
      // Label 253: @10321
4676
1.01k
      GIM_Try, /*On fail goto*//*Label 254*/ 10394, // Rule ID 161 //
4677
1.01k
        GIM_CheckFeatures, GIFBS_IsARM,
4678
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4679
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4680
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4681
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4682
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4683
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4684
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4685
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4686
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4687
1.01k
        // MIs[2] Operand 1
4688
1.01k
        // No operand predicates
4689
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4690
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4691
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4692
1.01k
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4693
1.01k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4694
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4695
1.01k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4696
1.01k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4697
1.01k
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4698
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4699
1.01k
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4700
1.01k
        GIR_EraseFromParent, /*InsnID*/0,
4701
1.01k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4702
1.01k
        // GIR_Coverage, 161,
4703
1.01k
        GIR_Done,
4704
1.01k
      // Label 254: @10394
4705
1.01k
      GIM_Try, /*On fail goto*//*Label 255*/ 10467, // Rule ID 495 //
4706
1.01k
        GIM_CheckFeatures, GIFBS_IsThumb2,
4707
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4708
1.01k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4709
1.01k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4710
1.01k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4711
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4712
1.01k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4713
1.01k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4714
1.01k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4715
1.01k
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4716
1.01k
        // MIs[2] Operand 1
4717
1.01k
        // No operand predicates
4718
1.01k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4719
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4720
1.01k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4721
1.01k
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$