Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenGlobalISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the ARM target                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 64;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(0),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_NoHonorSignDependentRoundingBit = 57,
37
  Feature_HasV4TBit = 6,
38
  Feature_NoV4TBit = 7,
39
  Feature_HasV5TBit = 8,
40
  Feature_HasV5TEBit = 12,
41
  Feature_HasV6Bit = 0,
42
  Feature_NoV6Bit = 10,
43
  Feature_HasV6MBit = 29,
44
  Feature_HasV8MBaselineBit = 33,
45
  Feature_HasV6T2Bit = 9,
46
  Feature_HasV6KBit = 19,
47
  Feature_HasV7Bit = 3,
48
  Feature_HasV8Bit = 15,
49
  Feature_PreV8Bit = 20,
50
  Feature_HasV8_1aBit = 59,
51
  Feature_NoVFPBit = 23,
52
  Feature_HasVFP2Bit = 22,
53
  Feature_HasVFP3Bit = 47,
54
  Feature_HasVFP4Bit = 45,
55
  Feature_HasDPVFPBit = 39,
56
  Feature_HasFPARMv8Bit = 41,
57
  Feature_HasNEONBit = 48,
58
  Feature_HasCryptoBit = 49,
59
  Feature_HasDotProdBit = 50,
60
  Feature_HasCRCBit = 14,
61
  Feature_HasFP16Bit = 54,
62
  Feature_HasFullFP16Bit = 38,
63
  Feature_HasDivideInThumbBit = 35,
64
  Feature_HasDivideInARMBit = 13,
65
  Feature_HasDSPBit = 34,
66
  Feature_HasDBBit = 16,
67
  Feature_HasV7ClrexBit = 18,
68
  Feature_HasAcquireReleaseBit = 17,
69
  Feature_HasMPBit = 2,
70
  Feature_HasZCZBit = 51,
71
  Feature_UseNEONForFPBit = 62,
72
  Feature_DontUseNEONForFPBit = 40,
73
  Feature_IsThumbBit = 27,
74
  Feature_IsThumb1OnlyBit = 28,
75
  Feature_IsThumb2Bit = 32,
76
  Feature_IsNotMClassBit = 36,
77
  Feature_IsARMBit = 1,
78
  Feature_IsWindowsBit = 30,
79
  Feature_IsNotWindowsBit = 31,
80
  Feature_IsReadTPHardBit = 55,
81
  Feature_IsReadTPSoftBit = 21,
82
  Feature_UseNaClTrapBit = 4,
83
  Feature_DontUseNaClTrapBit = 5,
84
  Feature_UseMovtBit = 37,
85
  Feature_DontUseMovtBit = 24,
86
  Feature_UseMovtInPicBit = 25,
87
  Feature_DontUseMovtInPicBit = 26,
88
  Feature_UseFPVMLxBit = 44,
89
  Feature_UseMulOpsBit = 11,
90
  Feature_UseFusedMACBit = 46,
91
  Feature_DontUseFusedMACBit = 43,
92
  Feature_HasFastVGETLNi32Bit = 52,
93
  Feature_HasSlowVGETLNi32Bit = 60,
94
  Feature_HasFastVDUP32Bit = 53,
95
  Feature_HasSlowVDUP32Bit = 61,
96
  Feature_UseVMOVSRBit = 42,
97
  Feature_DontUseVMOVSRBit = 63,
98
  Feature_IsLEBit = 56,
99
  Feature_IsBEBit = 58,
100
};
101
102
PredicateBitset ARMInstructionSelector::
103
6.58k
computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
104
6.58k
  PredicateBitset Features;
105
6.58k
  if (!TM.Options.HonorSignDependentRoundingFPMath())
106
6.51k
    Features[Feature_NoHonorSignDependentRoundingBit] = 1;
107
6.58k
  if (Subtarget->hasV4TOps())
108
5.54k
    Features[Feature_HasV4TBit] = 1;
109
6.58k
  if (!Subtarget->hasV4TOps())
110
1.03k
    Features[Feature_NoV4TBit] = 1;
111
6.58k
  if (Subtarget->hasV5TOps())
112
5.31k
    Features[Feature_HasV5TBit] = 1;
113
6.58k
  if (Subtarget->hasV5TEOps())
114
5.27k
    Features[Feature_HasV5TEBit] = 1;
115
6.58k
  if (Subtarget->hasV6Ops())
116
5.24k
    Features[Feature_HasV6Bit] = 1;
117
6.58k
  if (!Subtarget->hasV6Ops())
118
1.33k
    Features[Feature_NoV6Bit] = 1;
119
6.58k
  if (Subtarget->hasV6MOps())
120
4.99k
    Features[Feature_HasV6MBit] = 1;
121
6.58k
  if (Subtarget->hasV8MBaselineOps())
122
4.63k
    Features[Feature_HasV8MBaselineBit] = 1;
123
6.58k
  if (Subtarget->hasV6T2Ops())
124
4.58k
    Features[Feature_HasV6T2Bit] = 1;
125
6.58k
  if (Subtarget->hasV6KOps())
126
4.61k
    Features[Feature_HasV6KBit] = 1;
127
6.58k
  if (Subtarget->hasV7Ops())
128
4.35k
    Features[Feature_HasV7Bit] = 1;
129
6.58k
  if (Subtarget->hasV8Ops())
130
299
    Features[Feature_HasV8Bit] = 1;
131
6.58k
  if (!Subtarget->hasV8Ops())
132
6.28k
    Features[Feature_PreV8Bit] = 1;
133
6.58k
  if (Subtarget->hasV8_1aOps())
134
28
    Features[Feature_HasV8_1aBit] = 1;
135
6.58k
  if (!Subtarget->hasVFP2())
136
2.54k
    Features[Feature_NoVFPBit] = 1;
137
6.58k
  if (Subtarget->hasVFP2())
138
4.03k
    Features[Feature_HasVFP2Bit] = 1;
139
6.58k
  if (Subtarget->hasVFP3())
140
3.87k
    Features[Feature_HasVFP3Bit] = 1;
141
6.58k
  if (Subtarget->hasVFP4())
142
1.48k
    Features[Feature_HasVFP4Bit] = 1;
143
6.58k
  if (!Subtarget->isFPOnlySP())
144
6.32k
    Features[Feature_HasDPVFPBit] = 1;
145
6.58k
  if (Subtarget->hasFPARMv8())
146
393
    Features[Feature_HasFPARMv8Bit] = 1;
147
6.58k
  if (Subtarget->hasNEON())
148
3.47k
    Features[Feature_HasNEONBit] = 1;
149
6.58k
  if (Subtarget->hasCrypto())
150
268
    Features[Feature_HasCryptoBit] = 1;
151
6.58k
  if (Subtarget->hasDotProd())
152
2
    Features[Feature_HasDotProdBit] = 1;
153
6.58k
  if (Subtarget->hasCRC())
154
286
    Features[Feature_HasCRCBit] = 1;
155
6.58k
  if (Subtarget->hasFP16())
156
1.64k
    Features[Feature_HasFP16Bit] = 1;
157
6.58k
  if (Subtarget->hasFullFP16())
158
40
    Features[Feature_HasFullFP16Bit] = 1;
159
6.58k
  if (Subtarget->hasDivideInThumbMode())
160
2.02k
    Features[Feature_HasDivideInThumbBit] = 1;
161
6.58k
  if (Subtarget->hasDivideInARMMode())
162
1.18k
    Features[Feature_HasDivideInARMBit] = 1;
163
6.58k
  if (Subtarget->hasDSP())
164
4.35k
    Features[Feature_HasDSPBit] = 1;
165
6.58k
  if (Subtarget->hasDataBarrier())
166
4.69k
    Features[Feature_HasDBBit] = 1;
167
6.58k
  if (Subtarget->hasV7Clrex())
168
4.39k
    Features[Feature_HasV7ClrexBit] = 1;
169
6.58k
  if (Subtarget->hasAcquireRelease())
170
418
    Features[Feature_HasAcquireReleaseBit] = 1;
171
6.58k
  if (Subtarget->hasMPExtension())
172
1.27k
    Features[Feature_HasMPBit] = 1;
173
6.58k
  if (Subtarget->hasZeroCycleZeroing())
174
3
    Features[Feature_HasZCZBit] = 1;
175
6.58k
  if (Subtarget->useNEONForSinglePrecisionFP())
176
508
    Features[Feature_UseNEONForFPBit] = 1;
177
6.58k
  if (!Subtarget->useNEONForSinglePrecisionFP())
178
6.07k
    Features[Feature_DontUseNEONForFPBit] = 1;
179
6.58k
  if (Subtarget->isThumb())
180
3.67k
    Features[Feature_IsThumbBit] = 1;
181
6.58k
  if (Subtarget->isThumb1Only())
182
640
    Features[Feature_IsThumb1OnlyBit] = 1;
183
6.58k
  if (Subtarget->isThumb2())
184
3.03k
    Features[Feature_IsThumb2Bit] = 1;
185
6.58k
  if (!Subtarget->isMClass())
186
5.37k
    Features[Feature_IsNotMClassBit] = 1;
187
6.58k
  if (!Subtarget->isThumb())
188
2.91k
    Features[Feature_IsARMBit] = 1;
189
6.58k
  if (Subtarget->isTargetWindows())
190
81
    Features[Feature_IsWindowsBit] = 1;
191
6.58k
  if (!Subtarget->isTargetWindows())
192
6.50k
    Features[Feature_IsNotWindowsBit] = 1;
193
6.58k
  if (Subtarget->isReadTPHard())
194
2
    Features[Feature_IsReadTPHardBit] = 1;
195
6.58k
  if (!Subtarget->isReadTPHard())
196
6.57k
    Features[Feature_IsReadTPSoftBit] = 1;
197
6.58k
  if (Subtarget->useNaClTrap())
198
14
    Features[Feature_UseNaClTrapBit] = 1;
199
6.58k
  if (!Subtarget->useNaClTrap())
200
6.56k
    Features[Feature_DontUseNaClTrapBit] = 1;
201
6.58k
  if (Subtarget->useFPVMLx())
202
5.40k
    Features[Feature_UseFPVMLxBit] = 1;
203
6.58k
  if (Subtarget->useMulOps())
204
6.57k
    Features[Feature_UseMulOpsBit] = 1;
205
6.58k
  if ((TM.Options.AllowFPOpFusion == FPOpFusion::Fast &&  
Subtarget->hasVFP4()96
) &&
!Subtarget->isTargetDarwin()48
)
206
48
    Features[Feature_UseFusedMACBit] = 1;
207
6.58k
  if (!(TM.Options.AllowFPOpFusion == FPOpFusion::Fast && 
Subtarget->hasVFP4()96
) ||
Subtarget->isTargetDarwin()48
)
208
6.53k
    Features[Feature_DontUseFusedMACBit] = 1;
209
6.58k
  if (!Subtarget->hasSlowVGETLNi32())
210
6.23k
    Features[Feature_HasFastVGETLNi32Bit] = 1;
211
6.58k
  if (Subtarget->hasSlowVGETLNi32())
212
344
    Features[Feature_HasSlowVGETLNi32Bit] = 1;
213
6.58k
  if (!Subtarget->hasSlowVDUP32())
214
6.23k
    Features[Feature_HasFastVDUP32Bit] = 1;
215
6.58k
  if (Subtarget->hasSlowVDUP32())
216
344
    Features[Feature_HasSlowVDUP32Bit] = 1;
217
6.58k
  if (Subtarget->preferVMOVSR() ||
!Subtarget->useNEONForSinglePrecisionFP()6.47k
)
218
6.08k
    Features[Feature_UseVMOVSRBit] = 1;
219
6.58k
  if (!Subtarget->preferVMOVSR() &&
Subtarget->useNEONForSinglePrecisionFP()6.47k
)
220
500
    Features[Feature_DontUseVMOVSRBit] = 1;
221
6.58k
  return Features;
222
6.58k
}
223
224
PredicateBitset ARMInstructionSelector::
225
706
computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
226
706
  PredicateBitset Features;
227
706
  if (Subtarget->useMovt(*MF))
228
266
    Features[Feature_UseMovtBit] = 1;
229
706
  if (!Subtarget->useMovt(*MF))
230
440
    Features[Feature_DontUseMovtBit] = 1;
231
706
  if (Subtarget->useMovt(*MF) && 
Subtarget->allowPositionIndependentMovt()266
)
232
56
    Features[Feature_UseMovtInPicBit] = 1;
233
706
  if (!Subtarget->useMovt(*MF) || 
!Subtarget->allowPositionIndependentMovt()266
)
234
650
    Features[Feature_DontUseMovtInPicBit] = 1;
235
706
  if (MF->getDataLayout().isLittleEndian())
236
706
    Features[Feature_IsLEBit] = 1;
237
706
  if (MF->getDataLayout().isBigEndian())
238
0
    Features[Feature_IsBEBit] = 1;
239
706
  return Features;
240
706
}
241
242
// LLT Objects.
243
enum {
244
  GILLT_s16,
245
  GILLT_s32,
246
  GILLT_s64,
247
  GILLT_v2s32,
248
  GILLT_v2s64,
249
  GILLT_v4s16,
250
  GILLT_v4s32,
251
  GILLT_v8s8,
252
  GILLT_v8s16,
253
  GILLT_v16s8,
254
};
255
const static size_t NumTypeObjects = 10;
256
const static LLT TypeObjects[] = {
257
  LLT::scalar(16),
258
  LLT::scalar(32),
259
  LLT::scalar(64),
260
  LLT::vector(2, 32),
261
  LLT::vector(2, 64),
262
  LLT::vector(4, 16),
263
  LLT::vector(4, 32),
264
  LLT::vector(8, 8),
265
  LLT::vector(8, 16),
266
  LLT::vector(16, 8),
267
};
268
269
// Feature bitsets.
270
enum {
271
  GIFBS_Invalid,
272
  GIFBS_HasDotProd,
273
  GIFBS_HasFPARMv8,
274
  GIFBS_HasFullFP16,
275
  GIFBS_HasNEON,
276
  GIFBS_HasVFP2,
277
  GIFBS_HasVFP4,
278
  GIFBS_IsARM,
279
  GIFBS_IsBE,
280
  GIFBS_IsLE,
281
  GIFBS_IsThumb,
282
  GIFBS_IsThumb2,
283
  GIFBS_NoHonorSignDependentRounding,
284
  GIFBS_DontUseNEONForFP_HasVFP2,
285
  GIFBS_HasCrypto_HasV8,
286
  GIFBS_HasDB_IsARM,
287
  GIFBS_HasDB_IsThumb,
288
  GIFBS_HasDPVFP_HasFPARMv8,
289
  GIFBS_HasDPVFP_HasVFP2,
290
  GIFBS_HasDPVFP_HasVFP4,
291
  GIFBS_HasDPVFP_NoHonorSignDependentRounding,
292
  GIFBS_HasDSP_IsThumb2,
293
  GIFBS_HasDivideInARM_IsARM,
294
  GIFBS_HasFP16_HasNEON,
295
  GIFBS_HasFullFP16_HasNEON,
296
  GIFBS_HasNEON_HasV8,
297
  GIFBS_HasNEON_HasV8_1a,
298
  GIFBS_HasV5T_IsARM,
299
  GIFBS_HasV5TE_IsARM,
300
  GIFBS_HasV6_IsARM,
301
  GIFBS_HasV6K_IsARM,
302
  GIFBS_HasV6M_IsThumb,
303
  GIFBS_HasV6T2_IsARM,
304
  GIFBS_HasV6T2_IsThumb2,
305
  GIFBS_HasV7_IsARM,
306
  GIFBS_HasV7Clrex_IsThumb,
307
  GIFBS_HasV8MBaseline_IsThumb,
308
  GIFBS_HasVFP2_UseVMOVSR,
309
  GIFBS_IsARM_NoV6,
310
  GIFBS_IsARM_PreV8,
311
  GIFBS_IsThumb_IsThumb1Only,
312
  GIFBS_IsThumb_IsWindows,
313
  GIFBS_IsThumb_UseMovt,
314
  GIFBS_IsThumb2_PreV8,
315
  GIFBS_IsThumb2_UseMulOps,
316
  GIFBS_HasCRC_HasV8_IsARM,
317
  GIFBS_HasCRC_HasV8_IsThumb2,
318
  GIFBS_HasDSP_IsThumb2_UseMulOps,
319
  GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
320
  GIFBS_HasFullFP16_HasNEON_HasV8,
321
  GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
322
  GIFBS_HasV5TE_IsARM_UseMulOps,
323
  GIFBS_HasV6_IsARM_UseMulOps,
324
  GIFBS_HasV6_IsThumb_IsThumb1Only,
325
  GIFBS_HasV6T2_IsARM_UseMulOps,
326
  GIFBS_IsARM_NoV6_UseMulOps,
327
  GIFBS_DontUseFusedMAC_HasFullFP16_HasNEON_UseFPVMLx,
328
};
329
const static PredicateBitset FeatureBitsets[] {
330
  {}, // GIFBS_Invalid
331
  {Feature_HasDotProdBit, },
332
  {Feature_HasFPARMv8Bit, },
333
  {Feature_HasFullFP16Bit, },
334
  {Feature_HasNEONBit, },
335
  {Feature_HasVFP2Bit, },
336
  {Feature_HasVFP4Bit, },
337
  {Feature_IsARMBit, },
338
  {Feature_IsBEBit, },
339
  {Feature_IsLEBit, },
340
  {Feature_IsThumbBit, },
341
  {Feature_IsThumb2Bit, },
342
  {Feature_NoHonorSignDependentRoundingBit, },
343
  {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
344
  {Feature_HasCryptoBit, Feature_HasV8Bit, },
345
  {Feature_HasDBBit, Feature_IsARMBit, },
346
  {Feature_HasDBBit, Feature_IsThumbBit, },
347
  {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
348
  {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
349
  {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
350
  {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
351
  {Feature_HasDSPBit, Feature_IsThumb2Bit, },
352
  {Feature_HasDivideInARMBit, Feature_IsARMBit, },
353
  {Feature_HasFP16Bit, Feature_HasNEONBit, },
354
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
355
  {Feature_HasNEONBit, Feature_HasV8Bit, },
356
  {Feature_HasNEONBit, Feature_HasV8_1aBit, },
357
  {Feature_HasV5TBit, Feature_IsARMBit, },
358
  {Feature_HasV5TEBit, Feature_IsARMBit, },
359
  {Feature_HasV6Bit, Feature_IsARMBit, },
360
  {Feature_HasV6KBit, Feature_IsARMBit, },
361
  {Feature_HasV6MBit, Feature_IsThumbBit, },
362
  {Feature_HasV6T2Bit, Feature_IsARMBit, },
363
  {Feature_HasV6T2Bit, Feature_IsThumb2Bit, },
364
  {Feature_HasV7Bit, Feature_IsARMBit, },
365
  {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
366
  {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
367
  {Feature_HasVFP2Bit, Feature_UseVMOVSRBit, },
368
  {Feature_IsARMBit, Feature_NoV6Bit, },
369
  {Feature_IsARMBit, Feature_PreV8Bit, },
370
  {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
371
  {Feature_IsThumbBit, Feature_IsWindowsBit, },
372
  {Feature_IsThumbBit, Feature_UseMovtBit, },
373
  {Feature_IsThumb2Bit, Feature_PreV8Bit, },
374
  {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
375
  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsARMBit, },
376
  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsThumb2Bit, },
377
  {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
378
  {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
379
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
380
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
381
  {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
382
  {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
383
  {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
384
  {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
385
  {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
386
  {Feature_DontUseFusedMACBit, Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
387
};
388
389
// ComplexPattern predicates.
390
enum {
391
  GICP_Invalid,
392
};
393
// See constructor for table contents
394
395
// PatFrag predicates.
396
enum {
397
  GIPFP_I64_Predicate_VectorIndex16 = GIPFP_I64_Invalid + 1,
398
  GIPFP_I64_Predicate_VectorIndex32,
399
  GIPFP_I64_Predicate_VectorIndex64,
400
  GIPFP_I64_Predicate_VectorIndex8,
401
  GIPFP_I64_Predicate_imm0_15,
402
  GIPFP_I64_Predicate_imm0_239,
403
  GIPFP_I64_Predicate_imm0_255,
404
  GIPFP_I64_Predicate_imm0_31,
405
  GIPFP_I64_Predicate_imm0_32,
406
  GIPFP_I64_Predicate_imm0_4095,
407
  GIPFP_I64_Predicate_imm0_63,
408
  GIPFP_I64_Predicate_imm0_65535,
409
  GIPFP_I64_Predicate_imm0_65535_neg,
410
  GIPFP_I64_Predicate_imm0_7,
411
  GIPFP_I64_Predicate_imm16,
412
  GIPFP_I64_Predicate_imm16_31,
413
  GIPFP_I64_Predicate_imm1_15,
414
  GIPFP_I64_Predicate_imm1_16,
415
  GIPFP_I64_Predicate_imm1_31,
416
  GIPFP_I64_Predicate_imm1_7,
417
  GIPFP_I64_Predicate_imm24b,
418
  GIPFP_I64_Predicate_imm256_510,
419
  GIPFP_I64_Predicate_imm32,
420
  GIPFP_I64_Predicate_imm8,
421
  GIPFP_I64_Predicate_imm8_255,
422
  GIPFP_I64_Predicate_imm8_or_16,
423
  GIPFP_I64_Predicate_mod_imm,
424
  GIPFP_I64_Predicate_pkh_asr_amt,
425
  GIPFP_I64_Predicate_pkh_lsl_amt,
426
  GIPFP_I64_Predicate_shr_imm16,
427
  GIPFP_I64_Predicate_shr_imm32,
428
  GIPFP_I64_Predicate_shr_imm64,
429
  GIPFP_I64_Predicate_shr_imm8,
430
  GIPFP_I64_Predicate_t2_so_imm,
431
  GIPFP_I64_Predicate_t2_so_imm_neg,
432
};
433
71
bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
434
71
  switch (PredicateID) {
435
71
  case GIPFP_I64_Predicate_VectorIndex16: {
436
0
    
437
0
  return ((uint64_t)Imm) < 4;
438
71
439
71
    
llvm_unreachable0
("ImmediateCode should have returned");
440
71
    
return false0
;
441
71
  }
442
71
  case GIPFP_I64_Predicate_VectorIndex32: {
443
0
    
444
0
  return ((uint64_t)Imm) < 2;
445
71
446
71
    
llvm_unreachable0
("ImmediateCode should have returned");
447
71
    
return false0
;
448
71
  }
449
71
  case GIPFP_I64_Predicate_VectorIndex64: {
450
0
    
451
0
  return ((uint64_t)Imm) < 1;
452
71
453
71
    
llvm_unreachable0
("ImmediateCode should have returned");
454
71
    
return false0
;
455
71
  }
456
71
  case GIPFP_I64_Predicate_VectorIndex8: {
457
0
    
458
0
  return ((uint64_t)Imm) < 8;
459
71
460
71
    
llvm_unreachable0
("ImmediateCode should have returned");
461
71
    
return false0
;
462
71
  }
463
71
  case GIPFP_I64_Predicate_imm0_15: {
464
0
    
465
0
  return Imm >= 0 && Imm < 16;
466
71
467
71
    
llvm_unreachable0
("ImmediateCode should have returned");
468
71
    
return false0
;
469
71
  }
470
71
  case GIPFP_I64_Predicate_imm0_239: {
471
0
     return Imm >= 0 && Imm < 240; 
472
71
    
llvm_unreachable0
("ImmediateCode should have returned");
473
71
    
return false0
;
474
71
  }
475
71
  case GIPFP_I64_Predicate_imm0_255: {
476
0
     return Imm >= 0 && Imm < 256; 
477
71
    
llvm_unreachable0
("ImmediateCode should have returned");
478
71
    
return false0
;
479
71
  }
480
71
  case GIPFP_I64_Predicate_imm0_31: {
481
0
    
482
0
  return Imm >= 0 && Imm < 32;
483
71
484
71
    
llvm_unreachable0
("ImmediateCode should have returned");
485
71
    
return false0
;
486
71
  }
487
71
  case GIPFP_I64_Predicate_imm0_32: {
488
0
    
489
0
  return Imm >= 0 && Imm < 33;
490
71
491
71
    
llvm_unreachable0
("ImmediateCode should have returned");
492
71
    
return false0
;
493
71
  }
494
71
  case GIPFP_I64_Predicate_imm0_4095: {
495
0
    
496
0
  return Imm >= 0 && Imm < 4096;
497
71
498
71
    
llvm_unreachable0
("ImmediateCode should have returned");
499
71
    
return false0
;
500
71
  }
501
71
  case GIPFP_I64_Predicate_imm0_63: {
502
0
    
503
0
  return Imm >= 0 && Imm < 64;
504
71
505
71
    
llvm_unreachable0
("ImmediateCode should have returned");
506
71
    
return false0
;
507
71
  }
508
71
  case GIPFP_I64_Predicate_imm0_65535: {
509
1
    
510
1
  return Imm >= 0 && Imm < 65536;
511
71
512
71
    
llvm_unreachable0
("ImmediateCode should have returned");
513
71
    
return false0
;
514
71
  }
515
71
  case GIPFP_I64_Predicate_imm0_65535_neg: {
516
0
    
517
0
  return -Imm >= 0 && -Imm < 65536;
518
71
519
71
    
llvm_unreachable0
("ImmediateCode should have returned");
520
71
    
return false0
;
521
71
  }
522
71
  case GIPFP_I64_Predicate_imm0_7: {
523
0
    
524
0
  return Imm >= 0 && Imm < 8;
525
71
526
71
    
llvm_unreachable0
("ImmediateCode should have returned");
527
71
    
return false0
;
528
71
  }
529
71
  case GIPFP_I64_Predicate_imm16: {
530
1
     return Imm == 16; 
531
71
    
llvm_unreachable0
("ImmediateCode should have returned");
532
71
    
return false0
;
533
71
  }
534
71
  case GIPFP_I64_Predicate_imm16_31: {
535
2
    
536
2
  return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
537
71
538
71
    
llvm_unreachable0
("ImmediateCode should have returned");
539
71
    
return false0
;
540
71
  }
541
71
  case GIPFP_I64_Predicate_imm1_15: {
542
1
     return Imm > 0 && Imm < 16; 
543
71
    
llvm_unreachable0
("ImmediateCode should have returned");
544
71
    
return false0
;
545
71
  }
546
71
  case GIPFP_I64_Predicate_imm1_16: {
547
0
    
548
0
    return Imm > 0 && Imm <= 16;
549
71
  
550
71
    
llvm_unreachable0
("ImmediateCode should have returned");
551
71
    
return false0
;
552
71
  }
553
71
  case GIPFP_I64_Predicate_imm1_31: {
554
0
     return Imm > 0 && Imm < 32; 
555
71
    
llvm_unreachable0
("ImmediateCode should have returned");
556
71
    
return false0
;
557
71
  }
558
71
  case GIPFP_I64_Predicate_imm1_7: {
559
0
     return Imm > 0 && Imm < 8; 
560
71
    
llvm_unreachable0
("ImmediateCode should have returned");
561
71
    
return false0
;
562
71
  }
563
71
  case GIPFP_I64_Predicate_imm24b: {
564
0
    
565
0
  return Imm >= 0 && Imm <= 0xffffff;
566
71
567
71
    
llvm_unreachable0
("ImmediateCode should have returned");
568
71
    
return false0
;
569
71
  }
570
71
  case GIPFP_I64_Predicate_imm256_510: {
571
0
    
572
0
  return Imm >= 256 && Imm < 511;
573
71
574
71
    
llvm_unreachable0
("ImmediateCode should have returned");
575
71
    
return false0
;
576
71
  }
577
71
  case GIPFP_I64_Predicate_imm32: {
578
0
     return Imm == 32; 
579
71
    
llvm_unreachable0
("ImmediateCode should have returned");
580
71
    
return false0
;
581
71
  }
582
71
  case GIPFP_I64_Predicate_imm8: {
583
0
     return Imm == 8; 
584
71
    
llvm_unreachable0
("ImmediateCode should have returned");
585
71
    
return false0
;
586
71
  }
587
71
  case GIPFP_I64_Predicate_imm8_255: {
588
0
    
589
0
  return Imm >= 8 && Imm < 256;
590
71
591
71
    
llvm_unreachable0
("ImmediateCode should have returned");
592
71
    
return false0
;
593
71
  }
594
71
  case GIPFP_I64_Predicate_imm8_or_16: {
595
0
     return Imm == 8 || Imm == 16;
596
71
    
llvm_unreachable0
("ImmediateCode should have returned");
597
71
    
return false0
;
598
71
  }
599
71
  case GIPFP_I64_Predicate_mod_imm: {
600
63
    
601
63
    return ARM_AM::getSOImmVal(Imm) != -1;
602
71
  
603
71
    
llvm_unreachable0
("ImmediateCode should have returned");
604
71
    
return false0
;
605
71
  }
606
71
  case GIPFP_I64_Predicate_pkh_asr_amt: {
607
0
     return Imm > 0 && Imm <= 32; 
608
71
    
llvm_unreachable0
("ImmediateCode should have returned");
609
71
    
return false0
;
610
71
  }
611
71
  case GIPFP_I64_Predicate_pkh_lsl_amt: {
612
3
     return Imm >= 0 && Imm < 32; 
613
71
    
llvm_unreachable0
("ImmediateCode should have returned");
614
71
    
return false0
;
615
71
  }
616
71
  case GIPFP_I64_Predicate_shr_imm16: {
617
0
     return Imm > 0 && Imm <= 16; 
618
71
    
llvm_unreachable0
("ImmediateCode should have returned");
619
71
    
return false0
;
620
71
  }
621
71
  case GIPFP_I64_Predicate_shr_imm32: {
622
0
     return Imm > 0 && Imm <= 32; 
623
71
    
llvm_unreachable0
("ImmediateCode should have returned");
624
71
    
return false0
;
625
71
  }
626
71
  case GIPFP_I64_Predicate_shr_imm64: {
627
0
     return Imm > 0 && Imm <= 64; 
628
71
    
llvm_unreachable0
("ImmediateCode should have returned");
629
71
    
return false0
;
630
71
  }
631
71
  case GIPFP_I64_Predicate_shr_imm8: {
632
0
     return Imm > 0 && Imm <= 8; 
633
71
    
llvm_unreachable0
("ImmediateCode should have returned");
634
71
    
return false0
;
635
71
  }
636
71
  case GIPFP_I64_Predicate_t2_so_imm: {
637
0
    
638
0
    return ARM_AM::getT2SOImmVal(Imm) != -1;
639
71
  
640
71
    
llvm_unreachable0
("ImmediateCode should have returned");
641
71
    
return false0
;
642
71
  }
643
71
  case GIPFP_I64_Predicate_t2_so_imm_neg: {
644
0
    
645
0
  return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
646
71
647
71
    
llvm_unreachable0
("ImmediateCode should have returned");
648
71
    
return false0
;
649
0
  }
650
0
  }
651
0
  llvm_unreachable("Unknown predicate");
652
0
  return false;
653
0
}
654
0
bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
655
0
  llvm_unreachable("Unknown predicate");
656
0
  return false;
657
0
}
658
0
bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
659
0
  llvm_unreachable("Unknown predicate");
660
0
  return false;
661
0
}
662
// PatFrag predicates.
663
enum {
664
  GIPFP_MI_Predicate_bf_inv_mask_imm = GIPFP_MI_Invalid + 1,
665
};
666
0
bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
667
0
  const MachineFunction &MF = *MI.getParent()->getParent();
668
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
669
0
  (void)MRI;
670
0
  switch (PredicateID) {
671
0
  case GIPFP_MI_Predicate_bf_inv_mask_imm: {
672
0
    
673
0
    // There's better methods of implementing this check. IntImmLeaf<> would be
674
0
    // equivalent and have less boilerplate but we need a test for C++
675
0
    // predicates and this one causes new rules to be imported into GlobalISel
676
0
    // without requiring additional features first.
677
0
    const auto &MO = MI.getOperand(1);
678
0
    if (!MO.isCImm())
679
0
      return false;
680
0
    return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
681
0
  
682
0
    llvm_unreachable("GISelPredicateCode should have returned");
683
0
    return false;
684
0
  }
685
0
  }
686
0
  llvm_unreachable("Unknown predicate");
687
0
  return false;
688
0
}
689
690
ARMInstructionSelector::ComplexMatcherMemFn
691
ARMInstructionSelector::ComplexPredicateFns[] = {
692
  nullptr, // GICP_Invalid
693
};
694
695
// Custom renderers.
696
enum {
697
  GICR_Invalid,
698
};
699
ARMInstructionSelector::CustomRendererFn
700
ARMInstructionSelector::CustomRenderers[] = {
701
  nullptr, // GICP_Invalid
702
};
703
704
706
bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
705
706
  MachineFunction &MF = *I.getParent()->getParent();
706
706
  MachineRegisterInfo &MRI = MF.getRegInfo();
707
706
  // FIXME: This should be computed on a per-function basis rather than per-insn.
708
706
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
709
706
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
710
706
  NewMIVector OutMIs;
711
706
  State.MIs.clear();
712
706
  State.MIs.push_back(&I);
713
706
714
706
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
715
233
    return true;
716
233
  }
717
473
718
473
  return false;
719
473
}
720
721
706
const int64_t *ARMInstructionSelector::getMatchTable() const {
722
706
  constexpr static int64_t MatchTable0[] = {
723
706
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 124, /*)*//*default:*//*Label 33*/ 61035,
724
706
    /*TargetOpcode::G_ADD*//*Label 0*/ 95,
725
706
    /*TargetOpcode::G_SUB*//*Label 1*/ 6646,
726
706
    /*TargetOpcode::G_MUL*//*Label 2*/ 8636,
727
706
    /*TargetOpcode::G_SDIV*//*Label 3*/ 9270,
728
706
    /*TargetOpcode::G_UDIV*//*Label 4*/ 9370, 0, 0,
729
706
    /*TargetOpcode::G_AND*//*Label 5*/ 9470,
730
706
    /*TargetOpcode::G_OR*//*Label 6*/ 11183,
731
706
    /*TargetOpcode::G_XOR*//*Label 7*/ 15366, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
732
706
    /*TargetOpcode::G_BITCAST*//*Label 8*/ 15865, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
733
706
    /*TargetOpcode::G_INTRINSIC*//*Label 9*/ 20253,
734
706
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 10*/ 49624,
735
706
    /*TargetOpcode::G_ANYEXT*//*Label 11*/ 53953,
736
706
    /*TargetOpcode::G_TRUNC*//*Label 12*/ 54076,
737
706
    /*TargetOpcode::G_CONSTANT*//*Label 13*/ 54205, 0, 0, 0,
738
706
    /*TargetOpcode::G_SEXT*//*Label 14*/ 54370,
739
706
    /*TargetOpcode::G_ZEXT*//*Label 15*/ 54499,
740
706
    /*TargetOpcode::G_SHL*//*Label 16*/ 55009,
741
706
    /*TargetOpcode::G_LSHR*//*Label 17*/ 55114,
742
706
    /*TargetOpcode::G_ASHR*//*Label 18*/ 55172, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
743
706
    /*TargetOpcode::G_FADD*//*Label 19*/ 55385,
744
706
    /*TargetOpcode::G_FSUB*//*Label 20*/ 56016,
745
706
    /*TargetOpcode::G_FMUL*//*Label 21*/ 56631,
746
706
    /*TargetOpcode::G_FMA*//*Label 22*/ 57214,
747
706
    /*TargetOpcode::G_FDIV*//*Label 23*/ 58107, 0, 0, 0, 0, 0, 0,
748
706
    /*TargetOpcode::G_FNEG*//*Label 24*/ 58270,
749
706
    /*TargetOpcode::G_FPEXT*//*Label 25*/ 59187,
750
706
    /*TargetOpcode::G_FPTRUNC*//*Label 26*/ 59344,
751
706
    /*TargetOpcode::G_FPTOSI*//*Label 27*/ 59505,
752
706
    /*TargetOpcode::G_FPTOUI*//*Label 28*/ 59845,
753
706
    /*TargetOpcode::G_SITOFP*//*Label 29*/ 60185,
754
706
    /*TargetOpcode::G_UITOFP*//*Label 30*/ 60522, 0, 0, 0,
755
706
    /*TargetOpcode::G_BR*//*Label 31*/ 60859, 0, 0, 0,
756
706
    /*TargetOpcode::G_BSWAP*//*Label 32*/ 60921,
757
706
    // Label 0: @95
758
706
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 43*/ 6645,
759
706
    /*GILLT_s32*//*Label 34*/ 110,
760
706
    /*GILLT_s64*//*Label 35*/ 1788,
761
706
    /*GILLT_v2s32*//*Label 36*/ 1839,
762
706
    /*GILLT_v2s64*//*Label 37*/ 2299,
763
706
    /*GILLT_v4s16*//*Label 38*/ 3017,
764
706
    /*GILLT_v4s32*//*Label 39*/ 3477,
765
706
    /*GILLT_v8s8*//*Label 40*/ 4601,
766
706
    /*GILLT_v8s16*//*Label 41*/ 5061,
767
706
    /*GILLT_v16s8*//*Label 42*/ 6185,
768
706
    // Label 34: @110
769
706
    GIM_Try, /*On fail goto*//*Label 44*/ 1787,
770
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
771
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
772
706
      GIM_Try, /*On fail goto*//*Label 45*/ 186, // Rule ID 2738 //
773
706
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
774
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
775
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
776
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
777
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
778
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
779
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
780
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
781
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
782
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
783
706
        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
784
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
785
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
786
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
787
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
788
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
789
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
790
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
791
706
        GIR_EraseFromParent, /*InsnID*/0,
792
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
793
706
        // GIR_Coverage, 2738,
794
706
        GIR_Done,
795
706
      // Label 45: @186
796
706
      GIM_Try, /*On fail goto*//*Label 46*/ 252, // Rule ID 2739 //
797
706
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
798
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
799
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
800
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
801
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
802
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
803
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
804
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
805
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
806
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
807
706
        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
808
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
809
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
810
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
811
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
812
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
813
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
814
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
815
706
        GIR_EraseFromParent, /*InsnID*/0,
816
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
817
706
        // GIR_Coverage, 2739,
818
706
        GIR_Done,
819
706
      // Label 46: @252
820
706
      GIM_Try, /*On fail goto*//*Label 47*/ 318, // Rule ID 2768 //
821
706
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
822
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
823
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
824
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
825
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
826
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
827
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
828
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
829
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
830
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
831
706
        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
832
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
833
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
834
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
835
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
836
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
837
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
838
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
839
706
        GIR_EraseFromParent, /*InsnID*/0,
840
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
841
706
        // GIR_Coverage, 2768,
842
706
        GIR_Done,
843
706
      // Label 47: @318
844
706
      GIM_Try, /*On fail goto*//*Label 48*/ 384, // Rule ID 2769 //
845
706
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
846
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
847
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
848
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
849
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
850
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
851
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
852
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
853
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
854
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
855
706
        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
856
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
857
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
858
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
859
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
860
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
861
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
862
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
863
706
        GIR_EraseFromParent, /*InsnID*/0,
864
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
865
706
        // GIR_Coverage, 2769,
866
706
        GIR_Done,
867
706
      // Label 48: @384
868
706
      GIM_Try, /*On fail goto*//*Label 49*/ 450, // Rule ID 1813 //
869
706
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
870
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
871
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
872
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
873
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
874
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
875
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
876
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
877
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
878
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
879
706
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
880
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
881
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
882
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
883
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
884
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
885
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
886
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
887
706
        GIR_EraseFromParent, /*InsnID*/0,
888
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
889
706
        // GIR_Coverage, 1813,
890
706
        GIR_Done,
891
706
      // Label 49: @450
892
706
      GIM_Try, /*On fail goto*//*Label 50*/ 516, // Rule ID 1814 //
893
706
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
894
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
895
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
896
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
897
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
898
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
899
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
900
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
901
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
902
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
903
706
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
904
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
905
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
906
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
907
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
908
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
909
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
910
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
911
706
        GIR_EraseFromParent, /*InsnID*/0,
912
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
913
706
        // GIR_Coverage, 1814,
914
706
        GIR_Done,
915
706
      // Label 50: @516
916
706
      GIM_Try, /*On fail goto*//*Label 51*/ 582, // Rule ID 1999 //
917
706
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
918
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
919
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
920
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
921
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
922
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
923
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
924
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
925
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
926
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
927
706
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
928
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
929
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
930
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
931
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
932
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
933
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
934
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
935
706
        GIR_EraseFromParent, /*InsnID*/0,
936
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
937
706
        // GIR_Coverage, 1999,
938
706
        GIR_Done,
939
706
      // Label 51: @582
940
706
      GIM_Try, /*On fail goto*//*Label 52*/ 648, // Rule ID 2000 //
941
706
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
942
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
943
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
944
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
945
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
946
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
947
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
948
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
949
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
950
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
951
706
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
952
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
953
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
954
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
955
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
956
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
957
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
958
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
959
706
        GIR_EraseFromParent, /*InsnID*/0,
960
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
961
706
        // GIR_Coverage, 2000,
962
706
        GIR_Done,
963
706
      // Label 52: @648
964
706
      GIM_Try, /*On fail goto*//*Label 53*/ 757, // Rule ID 2523 //
965
706
        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
966
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
967
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
968
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
969
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
970
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
971
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
972
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
973
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
974
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
975
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
976
706
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
977
706
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
978
706
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
979
706
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
980
706
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
981
706
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
982
706
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
983
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
984
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
985
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
986
706
        GIM_CheckIsSafeToFold, /*InsnID*/3,
987
706
        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra)  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
988
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
989
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
990
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
991
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
992
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
993
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
994
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
995
706
        GIR_EraseFromParent, /*InsnID*/0,
996
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
997
706
        // GIR_Coverage, 2523,
998
706
        GIR_Done,
999
706
      // Label 53: @757
1000
706
      GIM_Try, /*On fail goto*//*Label 54*/ 866, // Rule ID 2560 //
1001
706
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1002
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1003
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1004
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1005
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1006
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1007
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1008
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1009
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1010
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1011
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1012
706
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1013
706
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1014
706
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1015
706
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1016
706
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1017
706
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1018
706
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1019
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1020
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1021
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1022
706
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1023
706
        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1024
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1025
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1026
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1027
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1028
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1029
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1030
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1031
706
        GIR_EraseFromParent, /*InsnID*/0,
1032
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1033
706
        // GIR_Coverage, 2560,
1034
706
        GIR_Done,
1035
706
      // Label 54: @866
1036
706
      GIM_Try, /*On fail goto*//*Label 55*/ 975, // Rule ID 194 //
1037
706
        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
1038
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1039
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1040
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1041
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1042
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1043
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1044
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1045
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1046
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1047
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1048
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1049
706
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1050
706
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1051
706
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1052
706
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1053
706
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1054
706
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1055
706
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1056
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1057
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1058
706
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1059
706
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1060
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1061
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1062
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1063
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1064
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1065
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1066
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1067
706
        GIR_EraseFromParent, /*InsnID*/0,
1068
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1069
706
        // GIR_Coverage, 194,
1070
706
        GIR_Done,
1071
706
      // Label 55: @975
1072
706
      GIM_Try, /*On fail goto*//*Label 56*/ 1084, // Rule ID 525 //
1073
706
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1074
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1075
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1076
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1077
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1078
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1079
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1080
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1081
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1082
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1083
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1084
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1085
706
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1086
706
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1087
706
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1088
706
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1089
706
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1090
706
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1091
706
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1092
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1093
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1094
706
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1095
706
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1096
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1097
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1098
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1099
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1100
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1101
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1102
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1103
706
        GIR_EraseFromParent, /*InsnID*/0,
1104
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1105
706
        // GIR_Coverage, 525,
1106
706
        GIR_Done,
1107
706
      // Label 56: @1084
1108
706
      GIM_Try, /*On fail goto*//*Label 57*/ 1136, // Rule ID 74 //
1109
706
        GIM_CheckFeatures, GIFBS_IsARM,
1110
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1111
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1112
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1113
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1114
706
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
1115
706
        // MIs[1] Operand 1
1116
706
        // No operand predicates
1117
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1118
706
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1119
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDri,
1120
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1121
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1122
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1123
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1124
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1125
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1126
706
        GIR_EraseFromParent, /*InsnID*/0,
1127
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1128
706
        // GIR_Coverage, 74,
1129
706
        GIR_Done,
1130
706
      // Label 57: @1136
1131
706
      GIM_Try, /*On fail goto*//*Label 58*/ 1188, // Rule ID 411 //
1132
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
1133
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1134
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1135
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1136
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1137
706
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
1138
706
        // MIs[1] Operand 1
1139
706
        // No operand predicates
1140
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1141
706
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1142
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri,
1143
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1144
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1145
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1146
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1147
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1148
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1149
706
        GIR_EraseFromParent, /*InsnID*/0,
1150
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1151
706
        // GIR_Coverage, 411,
1152
706
        GIR_Done,
1153
706
      // Label 58: @1188
1154
706
      GIM_Try, /*On fail goto*//*Label 59*/ 1237, // Rule ID 412 //
1155
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
1156
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1157
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1158
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1159
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1160
706
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
1161
706
        // MIs[1] Operand 1
1162
706
        // No operand predicates
1163
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1164
706
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1165
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri12,
1166
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1167
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1168
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1169
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1170
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1171
706
        GIR_EraseFromParent, /*InsnID*/0,
1172
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1173
706
        // GIR_Coverage, 412,
1174
706
        GIR_Done,
1175
706
      // Label 59: @1237
1176
706
      GIM_Try, /*On fail goto*//*Label 60*/ 1307, // Rule ID 173 //
1177
706
        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1178
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1179
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1180
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1181
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1182
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1183
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1184
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1185
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1186
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1187
706
        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1188
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1189
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1190
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1191
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1192
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1193
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1194
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1195
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1196
706
        GIR_EraseFromParent, /*InsnID*/0,
1197
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1198
706
        // GIR_Coverage, 173,
1199
706
        GIR_Done,
1200
706
      // Label 60: @1307
1201
706
      GIM_Try, /*On fail goto*//*Label 61*/ 1377, // Rule ID 174 //
1202
706
        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1203
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1204
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1205
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1206
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1207
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1208
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1209
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1210
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1211
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1212
706
        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1213
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1214
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1215
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1216
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1217
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1218
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1219
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1220
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1221
706
        GIR_EraseFromParent, /*InsnID*/0,
1222
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1223
706
        // GIR_Coverage, 174,
1224
706
        GIR_Done,
1225
706
      // Label 61: @1377
1226
706
      GIM_Try, /*On fail goto*//*Label 62*/ 1444, // Rule ID 507 //
1227
706
        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1228
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1229
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1230
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1231
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1232
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1233
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1234
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1235
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1236
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1237
706
        // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra)  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1238
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1239
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1240
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1241
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1242
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1243
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1244
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1245
706
        GIR_EraseFromParent, /*InsnID*/0,
1246
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1247
706
        // GIR_Coverage, 507,
1248
706
        GIR_Done,
1249
706
      // Label 62: @1444
1250
706
      GIM_Try, /*On fail goto*//*Label 63*/ 1514, // Rule ID 2517 //
1251
706
        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1252
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1253
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1254
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1255
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1256
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1257
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1258
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1259
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1260
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1261
706
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1262
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1263
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1264
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1265
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1266
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1267
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1268
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1269
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1270
706
        GIR_EraseFromParent, /*InsnID*/0,
1271
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1272
706
        // GIR_Coverage, 2517,
1273
706
        GIR_Done,
1274
706
      // Label 63: @1514
1275
706
      GIM_Try, /*On fail goto*//*Label 64*/ 1584, // Rule ID 2518 //
1276
706
        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1277
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1278
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1279
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1280
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1281
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1282
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1283
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1284
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1285
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1286
706
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1287
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1288
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1289
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1290
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1291
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1292
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1293
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1294
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1295
706
        GIR_EraseFromParent, /*InsnID*/0,
1296
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1297
706
        // GIR_Coverage, 2518,
1298
706
        GIR_Done,
1299
706
      // Label 64: @1584
1300
706
      GIM_Try, /*On fail goto*//*Label 65*/ 1651, // Rule ID 2555 //
1301
706
        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1302
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1303
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1304
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1305
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1306
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1307
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1308
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1309
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1310
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1311
706
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1312
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1313
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1314
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1315
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1316
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1317
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1318
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1319
706
        GIR_EraseFromParent, /*InsnID*/0,
1320
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1321
706
        // GIR_Coverage, 2555,
1322
706
        GIR_Done,
1323
706
      // Label 65: @1651
1324
706
      GIM_Try, /*On fail goto*//*Label 66*/ 1696, // Rule ID 75 //
1325
706
        GIM_CheckFeatures, GIFBS_IsARM,
1326
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1327
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1328
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1329
706
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
1330
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDrr,
1331
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1332
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1333
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1334
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1335
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1336
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1337
706
        GIR_EraseFromParent, /*InsnID*/0,
1338
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1339
706
        // GIR_Coverage, 75,
1340
706
        GIR_Done,
1341
706
      // Label 66: @1696
1342
706
      GIM_Try, /*On fail goto*//*Label 67*/ 1741, // Rule ID 413 //
1343
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
1344
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1345
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1346
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1347
706
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1348
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1349
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1350
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1351
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1352
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1353
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1354
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1355
706
        GIR_EraseFromParent, /*InsnID*/0,
1356
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1357
706
        // GIR_Coverage, 413,
1358
706
        GIR_Done,
1359
706
      // Label 67: @1741
1360
706
      GIM_Try, /*On fail goto*//*Label 68*/ 1786, // Rule ID 2537 //
1361
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
1362
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1363
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1364
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1365
706
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1366
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1367
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1368
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1369
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
1370
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1371
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1372
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1373
706
        GIR_EraseFromParent, /*InsnID*/0,
1374
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1375
706
        // GIR_Coverage, 2537,
1376
706
        GIR_Done,
1377
706
      // Label 68: @1786
1378
706
      GIM_Reject,
1379
706
    // Label 44: @1787
1380
706
    GIM_Reject,
1381
706
    // Label 35: @1788
1382
706
    GIM_Try, /*On fail goto*//*Label 69*/ 1838, // Rule ID 760 //
1383
706
      GIM_CheckFeatures, GIFBS_HasNEON,
1384
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1385
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1386
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1387
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1388
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1389
706
      // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1390
706
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv1i64,
1391
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1392
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1393
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1394
706
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1395
706
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1396
706
      GIR_EraseFromParent, /*InsnID*/0,
1397
706
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1398
706
      // GIR_Coverage, 760,
1399
706
      GIR_Done,
1400
706
    // Label 69: @1838
1401
706
    GIM_Reject,
1402
706
    // Label 36: @1839
1403
706
    GIM_Try, /*On fail goto*//*Label 70*/ 2298,
1404
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1405
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1406
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1407
706
      GIM_Try, /*On fail goto*//*Label 71*/ 1923, // Rule ID 2675 //
1408
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1409
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1410
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1411
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1412
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1413
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1414
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1415
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1416
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1417
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1418
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1419
706
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1014:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1420
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1421
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1422
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1423
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1424
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1425
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1426
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1427
706
        GIR_EraseFromParent, /*InsnID*/0,
1428
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1429
706
        // GIR_Coverage, 2675,
1430
706
        GIR_Done,
1431
706
      // Label 71: @1923
1432
706
      GIM_Try, /*On fail goto*//*Label 72*/ 1993, // Rule ID 2681 //
1433
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1434
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1435
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1436
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1437
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1438
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1439
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1440
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1441
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1442
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1443
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1444
706
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1015:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1445
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1446
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1447
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1448
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1449
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1450
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1451
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1452
706
        GIR_EraseFromParent, /*InsnID*/0,
1453
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1454
706
        // GIR_Coverage, 2681,
1455
706
        GIR_Done,
1456
706
      // Label 72: @1993
1457
706
      GIM_Try, /*On fail goto*//*Label 73*/ 2063, // Rule ID 1152 //
1458
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1459
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1460
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1461
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1462
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1463
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1464
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1465
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1466
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1467
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1468
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1469
706
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1014:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1470
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1471
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1472
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1473
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1474
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1475
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1476
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1477
706
        GIR_EraseFromParent, /*InsnID*/0,
1478
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1479
706
        // GIR_Coverage, 1152,
1480
706
        GIR_Done,
1481
706
      // Label 73: @2063
1482
706
      GIM_Try, /*On fail goto*//*Label 74*/ 2133, // Rule ID 1158 //
1483
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1484
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1485
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1486
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1487
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1488
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1489
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1490
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1491
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1492
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1493
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1494
706
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1015:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1495
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1496
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1497
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1498
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1499
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1500
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1501
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1502
706
        GIR_EraseFromParent, /*InsnID*/0,
1503
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1504
706
        // GIR_Coverage, 1158,
1505
706
        GIR_Done,
1506
706
      // Label 74: @2133
1507
706
      GIM_Try, /*On fail goto*//*Label 75*/ 2196, // Rule ID 2605 //
1508
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1509
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1510
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1511
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1512
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1513
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1514
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1515
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1516
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1517
706
        // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1518
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1519
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1520
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1521
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1522
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1523
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1524
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1525
706
        GIR_EraseFromParent, /*InsnID*/0,
1526
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1527
706
        // GIR_Coverage, 2605,
1528
706
        GIR_Done,
1529
706
      // Label 75: @2196
1530
706
      GIM_Try, /*On fail goto*//*Label 76*/ 2259, // Rule ID 875 //
1531
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1532
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1533
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1534
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1535
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1536
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1537
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1538
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1539
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1540
706
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1541
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1542
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1543
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1544
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1545
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1546
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1547
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1548
706
        GIR_EraseFromParent, /*InsnID*/0,
1549
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1550
706
        // GIR_Coverage, 875,
1551
706
        GIR_Done,
1552
706
      // Label 76: @2259
1553
706
      GIM_Try, /*On fail goto*//*Label 77*/ 2297, // Rule ID 756 //
1554
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1555
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1556
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1557
706
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1558
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i32,
1559
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1560
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1561
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1562
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1563
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1564
706
        GIR_EraseFromParent, /*InsnID*/0,
1565
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1566
706
        // GIR_Coverage, 756,
1567
706
        GIR_Done,
1568
706
      // Label 77: @2297
1569
706
      GIM_Reject,
1570
706
    // Label 70: @2298
1571
706
    GIM_Reject,
1572
706
    // Label 37: @2299
1573
706
    GIM_Try, /*On fail goto*//*Label 78*/ 3016,
1574
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1575
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1576
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
1577
706
      GIM_Try, /*On fail goto*//*Label 79*/ 2396, // Rule ID 2687 //
1578
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1579
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1580
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1581
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1582
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1583
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1584
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1585
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1586
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1587
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1588
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1589
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1590
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1591
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1592
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1593
706
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1014:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1594
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1595
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1596
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1597
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1598
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1599
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1600
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1601
706
        GIR_EraseFromParent, /*InsnID*/0,
1602
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1603
706
        // GIR_Coverage, 2687,
1604
706
        GIR_Done,
1605
706
      // Label 79: @2396
1606
706
      GIM_Try, /*On fail goto*//*Label 80*/ 2479, // Rule ID 2690 //
1607
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1608
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1609
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1610
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1611
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1612
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1613
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1614
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1615
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1616
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1617
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1618
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1619
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1620
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1621
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1622
706
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1015:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1623
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1624
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1625
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1626
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1627
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1628
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1629
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1630
706
        GIR_EraseFromParent, /*InsnID*/0,
1631
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1632
706
        // GIR_Coverage, 2690,
1633
706
        GIR_Done,
1634
706
      // Label 80: @2479
1635
706
      GIM_Try, /*On fail goto*//*Label 81*/ 2562, // Rule ID 1164 //
1636
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1637
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1638
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1639
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1640
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1641
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1642
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1643
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1644
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1645
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1646
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1647
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1648
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1649
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1650
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1651
706
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1014:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1652
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1653
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1654
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1655
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1656
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1657
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1658
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1659
706
        GIR_EraseFromParent, /*InsnID*/0,
1660
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1661
706
        // GIR_Coverage, 1164,
1662
706
        GIR_Done,
1663
706
      // Label 81: @2562
1664
706
      GIM_Try, /*On fail goto*//*Label 82*/ 2645, // Rule ID 1167 //
1665
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1666
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1667
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1668
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1669
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1670
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1671
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1672
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1673
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1674
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1675
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1676
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1677
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1678
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1679
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1680
706
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1015:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1681
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1682
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1683
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1684
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1685
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1686
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1687
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1688
706
        GIR_EraseFromParent, /*InsnID*/0,
1689
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1690
706
        // GIR_Coverage, 1167,
1691
706
        GIR_Done,
1692
706
      // Label 82: @2645
1693
706
      GIM_Try, /*On fail goto*//*Label 83*/ 2709, // Rule ID 768 //
1694
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1695
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1696
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1697
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1698
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1699
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1700
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1701
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1702
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1703
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1704
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1705
706
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1706
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv2i64,
1707
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1708
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1709
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
1710
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1711
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1712
706
        GIR_EraseFromParent, /*InsnID*/0,
1713
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1714
706
        // GIR_Coverage, 768,
1715
706
        GIR_Done,
1716
706
      // Label 83: @2709
1717
706
      GIM_Try, /*On fail goto*//*Label 84*/ 2773, // Rule ID 771 //
1718
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1719
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1720
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1721
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1722
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1723
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1724
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1725
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1726
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1727
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1728
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1729
706
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1730
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
1731
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1732
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1733
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
1734
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1735
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1736
706
        GIR_EraseFromParent, /*InsnID*/0,
1737
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1738
706
        // GIR_Coverage, 771,
1739
706
        GIR_Done,
1740
706
      // Label 84: @2773
1741
706
      GIM_Try, /*On fail goto*//*Label 85*/ 2824, // Rule ID 2581 //
1742
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1743
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1744
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1745
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1746
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1747
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1748
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1749
706
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1750
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
1751
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1752
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
1753
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1754
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1755
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1756
706
        GIR_EraseFromParent, /*InsnID*/0,
1757
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1758
706
        // GIR_Coverage, 2581,
1759
706
        GIR_Done,
1760
706
      // Label 85: @2824
1761
706
      GIM_Try, /*On fail goto*//*Label 86*/ 2875, // Rule ID 2584 //
1762
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1763
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1764
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1765
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1766
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1767
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1768
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1769
706
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1770
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
1771
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1772
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
1773
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1774
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1775
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1776
706
        GIR_EraseFromParent, /*InsnID*/0,
1777
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1778
706
        // GIR_Coverage, 2584,
1779
706
        GIR_Done,
1780
706
      // Label 86: @2875
1781
706
      GIM_Try, /*On fail goto*//*Label 87*/ 2926, // Rule ID 774 //
1782
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1783
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1784
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1785
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1786
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1787
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1788
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1789
706
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1790
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
1791
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1792
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1793
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1794
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1795
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1796
706
        GIR_EraseFromParent, /*InsnID*/0,
1797
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1798
706
        // GIR_Coverage, 774,
1799
706
        GIR_Done,
1800
706
      // Label 87: @2926
1801
706
      GIM_Try, /*On fail goto*//*Label 88*/ 2977, // Rule ID 777 //
1802
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1803
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1804
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1805
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1806
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1807
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1808
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1809
706
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1810
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
1811
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1812
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1813
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1814
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1815
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1816
706
        GIR_EraseFromParent, /*InsnID*/0,
1817
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1818
706
        // GIR_Coverage, 777,
1819
706
        GIR_Done,
1820
706
      // Label 88: @2977
1821
706
      GIM_Try, /*On fail goto*//*Label 89*/ 3015, // Rule ID 761 //
1822
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1823
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1824
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1825
706
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
1826
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i64,
1827
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1828
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1829
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1830
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1831
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1832
706
        GIR_EraseFromParent, /*InsnID*/0,
1833
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1834
706
        // GIR_Coverage, 761,
1835
706
        GIR_Done,
1836
706
      // Label 89: @3015
1837
706
      GIM_Reject,
1838
706
    // Label 78: @3016
1839
706
    GIM_Reject,
1840
706
    // Label 38: @3017
1841
706
    GIM_Try, /*On fail goto*//*Label 90*/ 3476,
1842
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1843
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
1844
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1845
706
      GIM_Try, /*On fail goto*//*Label 91*/ 3101, // Rule ID 2674 //
1846
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1847
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1848
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1849
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1850
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1851
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1852
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1853
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1854
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1855
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1856
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1857
706
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1014:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1858
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
1859
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1860
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1861
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1862
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1863
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1864
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1865
706
        GIR_EraseFromParent, /*InsnID*/0,
1866
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1867
706
        // GIR_Coverage, 2674,
1868
706
        GIR_Done,
1869
706
      // Label 91: @3101
1870
706
      GIM_Try, /*On fail goto*//*Label 92*/ 3171, // Rule ID 2680 //
1871
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1872
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1873
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1874
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1875
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1876
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1877
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1878
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1879
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1880
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1881
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1882
706
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1015:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1883
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
1884
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1885
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1886
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1887
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1888
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1889
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1890
706
        GIR_EraseFromParent, /*InsnID*/0,
1891
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1892
706
        // GIR_Coverage, 2680,
1893
706
        GIR_Done,
1894
706
      // Label 92: @3171
1895
706
      GIM_Try, /*On fail goto*//*Label 93*/ 3241, // Rule ID 1151 //
1896
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1897
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1898
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1899
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1900
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1901
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1902
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1903
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1904
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1905
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1906
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1907
706
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1014:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1908
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
1909
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1910
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1911
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1912
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1913
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1914
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1915
706
        GIR_EraseFromParent, /*InsnID*/0,
1916
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1917
706
        // GIR_Coverage, 1151,
1918
706
        GIR_Done,
1919
706
      // Label 93: @3241
1920
706
      GIM_Try, /*On fail goto*//*Label 94*/ 3311, // Rule ID 1157 //
1921
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1922
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1923
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1924
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1925
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1926
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1927
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1928
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1929
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1930
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1931
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1932
706
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1015:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1933
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
1934
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1935
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1936
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1937
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1938
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1939
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1940
706
        GIR_EraseFromParent, /*InsnID*/0,
1941
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1942
706
        // GIR_Coverage, 1157,
1943
706
        GIR_Done,
1944
706
      // Label 94: @3311
1945
706
      GIM_Try, /*On fail goto*//*Label 95*/ 3374, // Rule ID 2604 //
1946
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1947
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1948
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1949
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
1950
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1951
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1952
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1953
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1954
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1955
706
        // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1956
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
1957
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1958
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1959
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1960
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1961
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1962
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1963
706
        GIR_EraseFromParent, /*InsnID*/0,
1964
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1965
706
        // GIR_Coverage, 2604,
1966
706
        GIR_Done,
1967
706
      // Label 95: @3374
1968
706
      GIM_Try, /*On fail goto*//*Label 96*/ 3437, // Rule ID 874 //
1969
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1970
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1971
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1972
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1973
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
1974
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1975
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1976
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1977
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1978
706
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1979
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
1980
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1981
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1982
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1983
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1984
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1985
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1986
706
        GIR_EraseFromParent, /*InsnID*/0,
1987
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1988
706
        // GIR_Coverage, 874,
1989
706
        GIR_Done,
1990
706
      // Label 96: @3437
1991
706
      GIM_Try, /*On fail goto*//*Label 97*/ 3475, // Rule ID 755 //
1992
706
        GIM_CheckFeatures, GIFBS_HasNEON,
1993
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1994
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1995
706
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1996
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i16,
1997
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1998
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1999
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2000
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2001
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2002
706
        GIR_EraseFromParent, /*InsnID*/0,
2003
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2004
706
        // GIR_Coverage, 755,
2005
706
        GIR_Done,
2006
706
      // Label 97: @3475
2007
706
      GIM_Reject,
2008
706
    // Label 90: @3476
2009
706
    GIM_Reject,
2010
706
    // Label 39: @3477
2011
706
    GIM_Try, /*On fail goto*//*Label 98*/ 4600,
2012
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2013
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2014
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2015
706
      GIM_Try, /*On fail goto*//*Label 99*/ 3574, // Rule ID 2686 //
2016
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2017
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2018
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2019
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2020
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2021
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2022
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2023
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2024
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2025
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2026
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2027
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2028
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2029
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2030
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2031
706
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1014:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2032
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2033
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2034
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2035
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2036
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2037
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2038
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2039
706
        GIR_EraseFromParent, /*InsnID*/0,
2040
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2041
706
        // GIR_Coverage, 2686,
2042
706
        GIR_Done,
2043
706
      // Label 99: @3574
2044
706
      GIM_Try, /*On fail goto*//*Label 100*/ 3657, // Rule ID 2689 //
2045
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2046
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2047
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2048
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2049
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2050
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2051
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2052
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2053
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2054
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2055
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2056
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2057
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2058
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2059
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2060
706
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1015:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2061
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2062
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2063
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2064
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2065
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2066
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2067
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2068
706
        GIR_EraseFromParent, /*InsnID*/0,
2069
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2070
706
        // GIR_Coverage, 2689,
2071
706
        GIR_Done,
2072
706
      // Label 100: @3657
2073
706
      GIM_Try, /*On fail goto*//*Label 101*/ 3740, // Rule ID 1163 //
2074
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2075
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2076
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2077
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2078
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2079
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2080
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2081
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2082
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2083
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2084
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2085
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2086
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2087
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2088
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2089
706
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1014:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2090
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2091
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2092
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2093
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2094
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2095
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2096
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2097
706
        GIR_EraseFromParent, /*InsnID*/0,
2098
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2099
706
        // GIR_Coverage, 1163,
2100
706
        GIR_Done,
2101
706
      // Label 101: @3740
2102
706
      GIM_Try, /*On fail goto*//*Label 102*/ 3823, // Rule ID 1166 //
2103
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2104
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2105
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2106
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2107
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2108
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2109
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2110
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2111
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2112
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2113
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2114
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2115
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2116
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2117
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2118
706
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1015:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2119
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2120
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2121
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2122
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2123
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2124
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2125
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2126
706
        GIR_EraseFromParent, /*InsnID*/0,
2127
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2128
706
        // GIR_Coverage, 1166,
2129
706
        GIR_Done,
2130
706
      // Label 102: @3823
2131
706
      GIM_Try, /*On fail goto*//*Label 103*/ 3893, // Rule ID 2678 //
2132
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2133
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2134
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2135
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2136
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2137
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2138
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2139
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2140
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2141
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2142
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2143
706
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1014:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2144
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2145
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2146
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2147
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2148
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2149
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2150
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2151
706
        GIR_EraseFromParent, /*InsnID*/0,
2152
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2153
706
        // GIR_Coverage, 2678,
2154
706
        GIR_Done,
2155
706
      // Label 103: @3893
2156
706
      GIM_Try, /*On fail goto*//*Label 104*/ 3963, // Rule ID 2684 //
2157
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2158
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2159
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2160
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2161
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2162
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2163
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2164
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2165
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2166
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2167
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2168
706
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1015:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2169
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2170
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2171
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2172
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2173
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2174
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2175
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2176
706
        GIR_EraseFromParent, /*InsnID*/0,
2177
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2178
706
        // GIR_Coverage, 2684,
2179
706
        GIR_Done,
2180
706
      // Label 104: @3963
2181
706
      GIM_Try, /*On fail goto*//*Label 105*/ 4033, // Rule ID 1155 //
2182
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2183
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2184
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2185
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2186
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2187
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2188
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2189
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2190
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2191
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2192
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2193
706
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1014:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2194
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2195
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2196
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2197
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2198
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2199
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2200
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2201
706
        GIR_EraseFromParent, /*InsnID*/0,
2202
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2203
706
        // GIR_Coverage, 1155,
2204
706
        GIR_Done,
2205
706
      // Label 105: @4033
2206
706
      GIM_Try, /*On fail goto*//*Label 106*/ 4103, // Rule ID 1161 //
2207
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2208
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2209
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2210
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2211
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2212
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2213
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2214
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2215
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2216
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2217
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2218
706
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1015:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2219
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2220
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2221
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2222
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2223
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2224
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2225
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2226
706
        GIR_EraseFromParent, /*InsnID*/0,
2227
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2228
706
        // GIR_Coverage, 1161,
2229
706
        GIR_Done,
2230
706
      // Label 106: @4103
2231
706
      GIM_Try, /*On fail goto*//*Label 107*/ 4167, // Rule ID 767 //
2232
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2233
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2234
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2235
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2236
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2237
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2238
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2239
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2240
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2241
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2242
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2243
706
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2244
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv4i32,
2245
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2246
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2247
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2248
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2249
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2250
706
        GIR_EraseFromParent, /*InsnID*/0,
2251
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2252
706
        // GIR_Coverage, 767,
2253
706
        GIR_Done,
2254
706
      // Label 107: @4167
2255
706
      GIM_Try, /*On fail goto*//*Label 108*/ 4231, // Rule ID 770 //
2256
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2257
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2258
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2259
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2260
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2261
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2262
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2263
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2264
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2265
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2266
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2267
706
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2268
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2269
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2270
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2271
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2272
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2273
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2274
706
        GIR_EraseFromParent, /*InsnID*/0,
2275
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2276
706
        // GIR_Coverage, 770,
2277
706
        GIR_Done,
2278
706
      // Label 108: @4231
2279
706
      GIM_Try, /*On fail goto*//*Label 109*/ 4294, // Rule ID 2608 //
2280
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2281
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2282
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2283
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2284
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2285
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2286
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2287
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2288
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2289
706
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2290
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2291
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2292
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2293
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2294
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2295
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2296
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2297
706
        GIR_EraseFromParent, /*InsnID*/0,
2298
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2299
706
        // GIR_Coverage, 2608,
2300
706
        GIR_Done,
2301
706
      // Label 109: @4294
2302
706
      GIM_Try, /*On fail goto*//*Label 110*/ 4345, // Rule ID 2580 //
2303
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2304
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2305
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2306
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2307
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2308
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2309
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2310
706
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2311
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2312
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2313
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2314
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2315
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2316
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2317
706
        GIR_EraseFromParent, /*InsnID*/0,
2318
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2319
706
        // GIR_Coverage, 2580,
2320
706
        GIR_Done,
2321
706
      // Label 110: @4345
2322
706
      GIM_Try, /*On fail goto*//*Label 111*/ 4396, // Rule ID 2583 //
2323
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2324
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2325
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2326
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2327
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2328
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2329
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2330
706
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2331
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2332
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2333
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2334
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2335
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2336
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2337
706
        GIR_EraseFromParent, /*InsnID*/0,
2338
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2339
706
        // GIR_Coverage, 2583,
2340
706
        GIR_Done,
2341
706
      // Label 111: @4396
2342
706
      GIM_Try, /*On fail goto*//*Label 112*/ 4459, // Rule ID 878 //
2343
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2344
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2345
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2346
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2347
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2348
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2349
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2350
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2351
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2352
706
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2353
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2354
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2355
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2356
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2357
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2358
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2359
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2360
706
        GIR_EraseFromParent, /*InsnID*/0,
2361
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2362
706
        // GIR_Coverage, 878,
2363
706
        GIR_Done,
2364
706
      // Label 112: @4459
2365
706
      GIM_Try, /*On fail goto*//*Label 113*/ 4510, // Rule ID 773 //
2366
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2367
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2368
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2369
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2370
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2371
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2372
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2373
706
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2374
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2375
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2376
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2377
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2378
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2379
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2380
706
        GIR_EraseFromParent, /*InsnID*/0,
2381
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2382
706
        // GIR_Coverage, 773,
2383
706
        GIR_Done,
2384
706
      // Label 113: @4510
2385
706
      GIM_Try, /*On fail goto*//*Label 114*/ 4561, // Rule ID 776 //
2386
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2387
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2388
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2389
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2390
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2391
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2392
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2393
706
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2394
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2395
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2396
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2397
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2398
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2399
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2400
706
        GIR_EraseFromParent, /*InsnID*/0,
2401
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2402
706
        // GIR_Coverage, 776,
2403
706
        GIR_Done,
2404
706
      // Label 114: @4561
2405
706
      GIM_Try, /*On fail goto*//*Label 115*/ 4599, // Rule ID 759 //
2406
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2407
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2408
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2409
706
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2410
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i32,
2411
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2412
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2413
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2414
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2415
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2416
706
        GIR_EraseFromParent, /*InsnID*/0,
2417
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2418
706
        // GIR_Coverage, 759,
2419
706
        GIR_Done,
2420
706
      // Label 115: @4599
2421
706
      GIM_Reject,
2422
706
    // Label 98: @4600
2423
706
    GIM_Reject,
2424
706
    // Label 40: @4601
2425
706
    GIM_Try, /*On fail goto*//*Label 116*/ 5060,
2426
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
2427
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
2428
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
2429
706
      GIM_Try, /*On fail goto*//*Label 117*/ 4685, // Rule ID 2673 //
2430
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2431
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2432
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2433
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2434
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2435
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2436
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2437
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2438
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2439
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2440
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2441
706
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1014:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2442
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2443
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2444
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2445
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2446
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2447
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2448
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2449
706
        GIR_EraseFromParent, /*InsnID*/0,
2450
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2451
706
        // GIR_Coverage, 2673,
2452
706
        GIR_Done,
2453
706
      // Label 117: @4685
2454
706
      GIM_Try, /*On fail goto*//*Label 118*/ 4755, // Rule ID 2679 //
2455
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2456
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2457
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2458
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2459
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2460
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2461
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2462
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2463
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2464
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2465
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2466
706
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1015:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2467
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2468
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2469
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2470
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2471
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2472
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2473
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2474
706
        GIR_EraseFromParent, /*InsnID*/0,
2475
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2476
706
        // GIR_Coverage, 2679,
2477
706
        GIR_Done,
2478
706
      // Label 118: @4755
2479
706
      GIM_Try, /*On fail goto*//*Label 119*/ 4825, // Rule ID 1150 //
2480
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2481
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2482
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2483
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2484
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2485
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2486
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2487
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2488
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2489
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2490
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2491
706
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1014:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2492
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2493
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2494
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2495
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2496
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2497
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2498
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2499
706
        GIR_EraseFromParent, /*InsnID*/0,
2500
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2501
706
        // GIR_Coverage, 1150,
2502
706
        GIR_Done,
2503
706
      // Label 119: @4825
2504
706
      GIM_Try, /*On fail goto*//*Label 120*/ 4895, // Rule ID 1156 //
2505
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2506
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2507
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2508
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2509
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2510
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2511
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2512
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2513
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2514
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2515
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2516
706
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1015:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2517
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2518
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2519
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2520
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2521
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2522
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2523
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2524
706
        GIR_EraseFromParent, /*InsnID*/0,
2525
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2526
706
        // GIR_Coverage, 1156,
2527
706
        GIR_Done,
2528
706
      // Label 120: @4895
2529
706
      GIM_Try, /*On fail goto*//*Label 121*/ 4958, // Rule ID 2603 //
2530
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2531
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2532
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2533
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2534
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2535
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2536
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2537
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2538
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2539
706
        // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2540
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2541
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2542
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2543
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2544
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2545
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2546
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2547
706
        GIR_EraseFromParent, /*InsnID*/0,
2548
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2549
706
        // GIR_Coverage, 2603,
2550
706
        GIR_Done,
2551
706
      // Label 121: @4958
2552
706
      GIM_Try, /*On fail goto*//*Label 122*/ 5021, // Rule ID 873 //
2553
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2554
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2555
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2556
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2557
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2558
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2559
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2560
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2561
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2562
706
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2563
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2564
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2565
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2566
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2567
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2568
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2569
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2570
706
        GIR_EraseFromParent, /*InsnID*/0,
2571
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2572
706
        // GIR_Coverage, 873,
2573
706
        GIR_Done,
2574
706
      // Label 122: @5021
2575
706
      GIM_Try, /*On fail goto*//*Label 123*/ 5059, // Rule ID 754 //
2576
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2577
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2578
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2579
706
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2580
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i8,
2581
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2582
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2583
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2584
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2585
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2586
706
        GIR_EraseFromParent, /*InsnID*/0,
2587
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2588
706
        // GIR_Coverage, 754,
2589
706
        GIR_Done,
2590
706
      // Label 123: @5059
2591
706
      GIM_Reject,
2592
706
    // Label 116: @5060
2593
706
    GIM_Reject,
2594
706
    // Label 41: @5061
2595
706
    GIM_Try, /*On fail goto*//*Label 124*/ 6184,
2596
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2597
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2598
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2599
706
      GIM_Try, /*On fail goto*//*Label 125*/ 5158, // Rule ID 2685 //
2600
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2601
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2602
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2603
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2604
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2605
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2606
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2607
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2608
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2609
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2610
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2611
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2612
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2613
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2614
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2615
706
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1014:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2616
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2617
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2618
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2619
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2620
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2621
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2622
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2623
706
        GIR_EraseFromParent, /*InsnID*/0,
2624
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2625
706
        // GIR_Coverage, 2685,
2626
706
        GIR_Done,
2627
706
      // Label 125: @5158
2628
706
      GIM_Try, /*On fail goto*//*Label 126*/ 5241, // Rule ID 2688 //
2629
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2630
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2631
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2632
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2633
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2634
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2635
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2636
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2637
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2638
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2639
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2640
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2641
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2642
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2643
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2644
706
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1015:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2645
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2646
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2647
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2648
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2649
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2650
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2651
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2652
706
        GIR_EraseFromParent, /*InsnID*/0,
2653
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2654
706
        // GIR_Coverage, 2688,
2655
706
        GIR_Done,
2656
706
      // Label 126: @5241
2657
706
      GIM_Try, /*On fail goto*//*Label 127*/ 5324, // Rule ID 1162 //
2658
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2659
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2660
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2661
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2662
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2663
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2664
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2665
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2666
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2667
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2668
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2669
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2670
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2671
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2672
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2673
706
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1014:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2674
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2675
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2676
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2677
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2678
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2679
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2680
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2681
706
        GIR_EraseFromParent, /*InsnID*/0,
2682
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2683
706
        // GIR_Coverage, 1162,
2684
706
        GIR_Done,
2685
706
      // Label 127: @5324
2686
706
      GIM_Try, /*On fail goto*//*Label 128*/ 5407, // Rule ID 1165 //
2687
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2688
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2689
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2690
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2691
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2692
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2693
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2694
706
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2695
706
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2696
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2697
706
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2698
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2699
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2700
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2701
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2702
706
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1015:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2703
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2704
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2705
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2706
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2707
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2708
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2709
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2710
706
        GIR_EraseFromParent, /*InsnID*/0,
2711
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2712
706
        // GIR_Coverage, 1165,
2713
706
        GIR_Done,
2714
706
      // Label 128: @5407
2715
706
      GIM_Try, /*On fail goto*//*Label 129*/ 5477, // Rule ID 2677 //
2716
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2717
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2718
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2719
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2720
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2721
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2722
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2723
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2724
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2725
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2726
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2727
706
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1014:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2728
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
2729
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2730
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2731
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2732
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2733
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2734
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2735
706
        GIR_EraseFromParent, /*InsnID*/0,
2736
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2737
706
        // GIR_Coverage, 2677,
2738
706
        GIR_Done,
2739
706
      // Label 129: @5477
2740
706
      GIM_Try, /*On fail goto*//*Label 130*/ 5547, // Rule ID 2683 //
2741
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2742
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2743
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2744
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2745
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2746
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2747
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2748
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2749
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2750
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2751
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2752
706
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1015:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2753
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
2754
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2755
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2756
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2757
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2758
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2759
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2760
706
        GIR_EraseFromParent, /*InsnID*/0,
2761
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2762
706
        // GIR_Coverage, 2683,
2763
706
        GIR_Done,
2764
706
      // Label 130: @5547
2765
706
      GIM_Try, /*On fail goto*//*Label 131*/ 5617, // Rule ID 1154 //
2766
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2767
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2768
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2769
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2770
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2771
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2772
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2773
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2774
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2775
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2776
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2777
706
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1014:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2778
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
2779
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2780
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2781
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2782
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2783
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2784
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2785
706
        GIR_EraseFromParent, /*InsnID*/0,
2786
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2787
706
        // GIR_Coverage, 1154,
2788
706
        GIR_Done,
2789
706
      // Label 131: @5617
2790
706
      GIM_Try, /*On fail goto*//*Label 132*/ 5687, // Rule ID 1160 //
2791
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2792
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2793
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2794
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2795
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2796
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2797
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2798
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2799
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2800
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2801
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2802
706
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1015:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2803
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
2804
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2805
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2806
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2807
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2808
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2809
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2810
706
        GIR_EraseFromParent, /*InsnID*/0,
2811
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2812
706
        // GIR_Coverage, 1160,
2813
706
        GIR_Done,
2814
706
      // Label 132: @5687
2815
706
      GIM_Try, /*On fail goto*//*Label 133*/ 5751, // Rule ID 766 //
2816
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2817
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2818
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2819
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2820
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2821
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2822
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2823
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
2824
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2825
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2826
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2827
706
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2828
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv8i16,
2829
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2830
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2831
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2832
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2833
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2834
706
        GIR_EraseFromParent, /*InsnID*/0,
2835
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2836
706
        // GIR_Coverage, 766,
2837
706
        GIR_Done,
2838
706
      // Label 133: @5751
2839
706
      GIM_Try, /*On fail goto*//*Label 134*/ 5815, // Rule ID 769 //
2840
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2841
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2842
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2843
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2844
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2845
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2846
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2847
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
2848
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2849
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2850
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2851
706
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2852
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
2853
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2854
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2855
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2856
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2857
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2858
706
        GIR_EraseFromParent, /*InsnID*/0,
2859
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2860
706
        // GIR_Coverage, 769,
2861
706
        GIR_Done,
2862
706
      // Label 134: @5815
2863
706
      GIM_Try, /*On fail goto*//*Label 135*/ 5878, // Rule ID 2607 //
2864
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2865
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2866
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2867
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2868
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2869
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2870
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2871
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2872
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2873
706
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2874
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
2875
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2876
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2877
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2878
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2879
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2880
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2881
706
        GIR_EraseFromParent, /*InsnID*/0,
2882
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2883
706
        // GIR_Coverage, 2607,
2884
706
        GIR_Done,
2885
706
      // Label 135: @5878
2886
706
      GIM_Try, /*On fail goto*//*Label 136*/ 5929, // Rule ID 2579 //
2887
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2888
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2889
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2890
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2891
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2892
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2893
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2894
706
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2895
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
2896
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2897
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2898
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2899
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2900
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2901
706
        GIR_EraseFromParent, /*InsnID*/0,
2902
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2903
706
        // GIR_Coverage, 2579,
2904
706
        GIR_Done,
2905
706
      // Label 136: @5929
2906
706
      GIM_Try, /*On fail goto*//*Label 137*/ 5980, // Rule ID 2582 //
2907
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2908
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2909
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2910
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2911
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2912
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2913
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2914
706
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2915
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
2916
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2917
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2918
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2919
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2920
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2921
706
        GIR_EraseFromParent, /*InsnID*/0,
2922
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2923
706
        // GIR_Coverage, 2582,
2924
706
        GIR_Done,
2925
706
      // Label 137: @5980
2926
706
      GIM_Try, /*On fail goto*//*Label 138*/ 6043, // Rule ID 877 //
2927
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2928
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2929
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2930
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2931
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2932
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2933
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2934
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2935
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2936
706
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2937
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
2938
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2939
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2940
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2941
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2942
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2943
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2944
706
        GIR_EraseFromParent, /*InsnID*/0,
2945
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2946
706
        // GIR_Coverage, 877,
2947
706
        GIR_Done,
2948
706
      // Label 138: @6043
2949
706
      GIM_Try, /*On fail goto*//*Label 139*/ 6094, // Rule ID 772 //
2950
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2951
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2952
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2953
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2954
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2955
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2956
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2957
706
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2958
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
2959
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2960
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2961
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2962
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2963
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2964
706
        GIR_EraseFromParent, /*InsnID*/0,
2965
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2966
706
        // GIR_Coverage, 772,
2967
706
        GIR_Done,
2968
706
      // Label 139: @6094
2969
706
      GIM_Try, /*On fail goto*//*Label 140*/ 6145, // Rule ID 775 //
2970
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2971
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2972
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2973
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2974
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2975
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2976
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2977
706
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2978
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
2979
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2980
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2981
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2982
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2983
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2984
706
        GIR_EraseFromParent, /*InsnID*/0,
2985
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2986
706
        // GIR_Coverage, 775,
2987
706
        GIR_Done,
2988
706
      // Label 140: @6145
2989
706
      GIM_Try, /*On fail goto*//*Label 141*/ 6183, // Rule ID 758 //
2990
706
        GIM_CheckFeatures, GIFBS_HasNEON,
2991
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2992
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2993
706
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2994
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i16,
2995
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2996
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2997
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2998
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2999
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3000
706
        GIR_EraseFromParent, /*InsnID*/0,
3001
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3002
706
        // GIR_Coverage, 758,
3003
706
        GIR_Done,
3004
706
      // Label 141: @6183
3005
706
      GIM_Reject,
3006
706
    // Label 124: @6184
3007
706
    GIM_Reject,
3008
706
    // Label 42: @6185
3009
706
    GIM_Try, /*On fail goto*//*Label 142*/ 6644,
3010
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3011
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3012
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3013
706
      GIM_Try, /*On fail goto*//*Label 143*/ 6269, // Rule ID 2676 //
3014
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3015
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3016
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3017
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3018
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3019
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3020
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3021
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3022
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3023
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3024
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3025
706
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1014:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3026
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3027
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3028
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3029
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3030
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3031
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3032
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3033
706
        GIR_EraseFromParent, /*InsnID*/0,
3034
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3035
706
        // GIR_Coverage, 2676,
3036
706
        GIR_Done,
3037
706
      // Label 143: @6269
3038
706
      GIM_Try, /*On fail goto*//*Label 144*/ 6339, // Rule ID 2682 //
3039
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3040
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3041
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3042
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3043
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3044
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3045
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3046
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3047
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3048
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3049
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3050
706
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1015:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3051
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3052
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3053
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3054
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3055
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3056
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3057
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3058
706
        GIR_EraseFromParent, /*InsnID*/0,
3059
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3060
706
        // GIR_Coverage, 2682,
3061
706
        GIR_Done,
3062
706
      // Label 144: @6339
3063
706
      GIM_Try, /*On fail goto*//*Label 145*/ 6409, // Rule ID 1153 //
3064
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3065
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3066
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3067
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3068
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3069
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3070
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3071
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3072
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3073
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3074
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3075
706
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1014:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3076
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3077
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3078
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3079
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3080
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3081
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3082
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3083
706
        GIR_EraseFromParent, /*InsnID*/0,
3084
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3085
706
        // GIR_Coverage, 1153,
3086
706
        GIR_Done,
3087
706
      // Label 145: @6409
3088
706
      GIM_Try, /*On fail goto*//*Label 146*/ 6479, // Rule ID 1159 //
3089
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3090
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3091
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3092
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3093
706
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3094
706
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3095
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3096
706
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3097
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3098
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3099
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3100
706
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1015:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3101
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3102
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3103
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3104
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3105
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3106
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3107
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3108
706
        GIR_EraseFromParent, /*InsnID*/0,
3109
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3110
706
        // GIR_Coverage, 1159,
3111
706
        GIR_Done,
3112
706
      // Label 146: @6479
3113
706
      GIM_Try, /*On fail goto*//*Label 147*/ 6542, // Rule ID 2606 //
3114
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3115
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3116
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3117
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3118
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3119
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3120
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3121
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3122
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3123
706
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3124
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3125
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3126
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3127
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3128
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3129
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3130
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3131
706
        GIR_EraseFromParent, /*InsnID*/0,
3132
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3133
706
        // GIR_Coverage, 2606,
3134
706
        GIR_Done,
3135
706
      // Label 147: @6542
3136
706
      GIM_Try, /*On fail goto*//*Label 148*/ 6605, // Rule ID 876 //
3137
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3138
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3139
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3140
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3141
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3142
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3143
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3144
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3145
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3146
706
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3147
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3148
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3149
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3150
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3151
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3152
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3153
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3154
706
        GIR_EraseFromParent, /*InsnID*/0,
3155
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3156
706
        // GIR_Coverage, 876,
3157
706
        GIR_Done,
3158
706
      // Label 148: @6605
3159
706
      GIM_Try, /*On fail goto*//*Label 149*/ 6643, // Rule ID 757 //
3160
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3161
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3162
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3163
706
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3164
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv16i8,
3165
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3166
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3167
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3168
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3169
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3170
706
        GIR_EraseFromParent, /*InsnID*/0,
3171
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3172
706
        // GIR_Coverage, 757,
3173
706
        GIR_Done,
3174
706
      // Label 149: @6643
3175
706
      GIM_Reject,
3176
706
    // Label 142: @6644
3177
706
    GIM_Reject,
3178
706
    // Label 43: @6645
3179
706
    GIM_Reject,
3180
706
    // Label 1: @6646
3181
706
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 159*/ 8635,
3182
706
    /*GILLT_s32*//*Label 150*/ 6661,
3183
706
    /*GILLT_s64*//*Label 151*/ 7154,
3184
706
    /*GILLT_v2s32*//*Label 152*/ 7205,
3185
706
    /*GILLT_v2s64*//*Label 153*/ 7318,
3186
706
    /*GILLT_v4s16*//*Label 154*/ 7602,
3187
706
    /*GILLT_v4s32*//*Label 155*/ 7715,
3188
706
    /*GILLT_v8s8*//*Label 156*/ 8062,
3189
706
    /*GILLT_v8s16*//*Label 157*/ 8175,
3190
706
    /*GILLT_v16s8*//*Label 158*/ 8522,
3191
706
    // Label 150: @6661
3192
706
    GIM_Try, /*On fail goto*//*Label 160*/ 7153,
3193
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3194
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3195
706
      GIM_Try, /*On fail goto*//*Label 161*/ 6723, // Rule ID 98 //
3196
706
        GIM_CheckFeatures, GIFBS_IsARM,
3197
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3198
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3199
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3200
706
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3201
706
        // MIs[1] Operand 1
3202
706
        // No operand predicates
3203
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3204
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3205
706
        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn)  =>  (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3206
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RSBri,
3207
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3208
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3209
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3210
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3211
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3212
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3213
706
        GIR_EraseFromParent, /*InsnID*/0,
3214
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3215
706
        // GIR_Coverage, 98,
3216
706
        GIR_Done,
3217
706
      // Label 161: @6723
3218
706
      GIM_Try, /*On fail goto*//*Label 162*/ 6775, // Rule ID 431 //
3219
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
3220
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3221
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3222
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3223
706
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
3224
706
        // MIs[1] Operand 1
3225
706
        // No operand predicates
3226
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3227
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3228
706
        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn)  =>  (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3229
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RSBri,
3230
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3231
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3232
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3233
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3234
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3235
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3236
706
        GIR_EraseFromParent, /*InsnID*/0,
3237
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3238
706
        // GIR_Coverage, 431,
3239
706
        GIR_Done,
3240
706
      // Label 162: @6775
3241
706
      GIM_Try, /*On fail goto*//*Label 163*/ 6827, // Rule ID 78 //
3242
706
        GIM_CheckFeatures, GIFBS_IsARM,
3243
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3244
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3245
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3246
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3247
706
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3248
706
        // MIs[1] Operand 1
3249
706
        // No operand predicates
3250
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3251
706
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3252
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBri,
3253
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3254
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3255
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3256
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3257
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3258
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3259
706
        GIR_EraseFromParent, /*InsnID*/0,
3260
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3261
706
        // GIR_Coverage, 78,
3262
706
        GIR_Done,
3263
706
      // Label 163: @6827
3264
706
      GIM_Try, /*On fail goto*//*Label 164*/ 6879, // Rule ID 415 //
3265
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
3266
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3267
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
3268
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3269
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3270
706
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
3271
706
        // MIs[1] Operand 1
3272
706
        // No operand predicates
3273
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3274
706
        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3275
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri,
3276
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3277
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3278
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3279
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3280
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3281
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3282
706
        GIR_EraseFromParent, /*InsnID*/0,
3283
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3284
706
        // GIR_Coverage, 415,
3285
706
        GIR_Done,
3286
706
      // Label 164: @6879
3287
706
      GIM_Try, /*On fail goto*//*Label 165*/ 6928, // Rule ID 416 //
3288
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
3289
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3290
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3291
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3292
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3293
706
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
3294
706
        // MIs[1] Operand 1
3295
706
        // No operand predicates
3296
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3297
706
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3298
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri12,
3299
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3300
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3301
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3302
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3303
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3304
706
        GIR_EraseFromParent, /*InsnID*/0,
3305
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3306
706
        // GIR_Coverage, 416,
3307
706
        GIR_Done,
3308
706
      // Label 165: @6928
3309
706
      GIM_Try, /*On fail goto*//*Label 166*/ 6995, // Rule ID 175 //
3310
706
        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM_UseMulOps,
3311
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3312
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3313
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3314
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3315
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3316
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3317
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3318
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3319
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3320
706
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm))  =>  (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
3321
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLS,
3322
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3323
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3324
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3325
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3326
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3327
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3328
706
        GIR_EraseFromParent, /*InsnID*/0,
3329
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3330
706
        // GIR_Coverage, 175,
3331
706
        GIR_Done,
3332
706
      // Label 166: @6995
3333
706
      GIM_Try, /*On fail goto*//*Label 167*/ 7062, // Rule ID 508 //
3334
706
        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
3335
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3336
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3337
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3338
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3339
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3340
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3341
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3342
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3343
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3344
706
        // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
3345
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLS,
3346
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3347
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3348
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3349
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3350
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3351
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3352
706
        GIR_EraseFromParent, /*InsnID*/0,
3353
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3354
706
        // GIR_Coverage, 508,
3355
706
        GIR_Done,
3356
706
      // Label 167: @7062
3357
706
      GIM_Try, /*On fail goto*//*Label 168*/ 7107, // Rule ID 79 //
3358
706
        GIM_CheckFeatures, GIFBS_IsARM,
3359
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3360
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3361
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3362
706
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
3363
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBrr,
3364
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3365
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3366
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
3367
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3368
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3369
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3370
706
        GIR_EraseFromParent, /*InsnID*/0,
3371
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3372
706
        // GIR_Coverage, 79,
3373
706
        GIR_Done,
3374
706
      // Label 168: @7107
3375
706
      GIM_Try, /*On fail goto*//*Label 169*/ 7152, // Rule ID 417 //
3376
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
3377
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3378
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
3379
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3380
706
        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
3381
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBrr,
3382
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3383
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3384
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
3385
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3386
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3387
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3388
706
        GIR_EraseFromParent, /*InsnID*/0,
3389
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3390
706
        // GIR_Coverage, 417,
3391
706
        GIR_Done,
3392
706
      // Label 169: @7152
3393
706
      GIM_Reject,
3394
706
    // Label 160: @7153
3395
706
    GIM_Reject,
3396
706
    // Label 151: @7154
3397
706
    GIM_Try, /*On fail goto*//*Label 170*/ 7204, // Rule ID 947 //
3398
706
      GIM_CheckFeatures, GIFBS_HasNEON,
3399
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3400
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3401
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3402
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3403
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3404
706
      // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
3405
706
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv1i64,
3406
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3407
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3408
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3409
706
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3410
706
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3411
706
      GIR_EraseFromParent, /*InsnID*/0,
3412
706
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3413
706
      // GIR_Coverage, 947,
3414
706
      GIR_Done,
3415
706
    // Label 170: @7204
3416
706
    GIM_Reject,
3417
706
    // Label 152: @7205
3418
706
    GIM_Try, /*On fail goto*//*Label 171*/ 7317,
3419
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
3420
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
3421
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3422
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3423
706
      GIM_Try, /*On fail goto*//*Label 172*/ 7282, // Rule ID 903 //
3424
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3425
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3426
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3427
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3428
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3429
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3430
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3431
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3432
706
        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3433
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv2i32,
3434
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3435
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3436
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3437
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3438
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3439
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3440
706
        GIR_EraseFromParent, /*InsnID*/0,
3441
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3442
706
        // GIR_Coverage, 903,
3443
706
        GIR_Done,
3444
706
      // Label 172: @7282
3445
706
      GIM_Try, /*On fail goto*//*Label 173*/ 7316, // Rule ID 943 //
3446
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3447
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3448
706
        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3449
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i32,
3450
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3451
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3452
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3453
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3454
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3455
706
        GIR_EraseFromParent, /*InsnID*/0,
3456
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3457
706
        // GIR_Coverage, 943,
3458
706
        GIR_Done,
3459
706
      // Label 173: @7316
3460
706
      GIM_Reject,
3461
706
    // Label 171: @7317
3462
706
    GIM_Reject,
3463
706
    // Label 153: @7318
3464
706
    GIM_Try, /*On fail goto*//*Label 174*/ 7601,
3465
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3466
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
3467
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3468
706
      GIM_Try, /*On fail goto*//*Label 175*/ 7396, // Rule ID 955 //
3469
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3470
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3471
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3472
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3473
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3474
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3475
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3476
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3477
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3478
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3479
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3480
706
        // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3481
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv2i64,
3482
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3483
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3484
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3485
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3486
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3487
706
        GIR_EraseFromParent, /*InsnID*/0,
3488
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3489
706
        // GIR_Coverage, 955,
3490
706
        GIR_Done,
3491
706
      // Label 175: @7396
3492
706
      GIM_Try, /*On fail goto*//*Label 176*/ 7460, // Rule ID 958 //
3493
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3494
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3495
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3496
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3497
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3498
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3499
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3500
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3501
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3502
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3503
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3504
706
        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3505
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
3506
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3507
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3508
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3509
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3510
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3511
706
        GIR_EraseFromParent, /*InsnID*/0,
3512
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3513
706
        // GIR_Coverage, 958,
3514
706
        GIR_Done,
3515
706
      // Label 176: @7460
3516
706
      GIM_Try, /*On fail goto*//*Label 177*/ 7511, // Rule ID 961 //
3517
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3518
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3519
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3520
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3521
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3522
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3523
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3524
706
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3525
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv2i64,
3526
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3527
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3528
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3529
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3530
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3531
706
        GIR_EraseFromParent, /*InsnID*/0,
3532
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3533
706
        // GIR_Coverage, 961,
3534
706
        GIR_Done,
3535
706
      // Label 177: @7511
3536
706
      GIM_Try, /*On fail goto*//*Label 178*/ 7562, // Rule ID 964 //
3537
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3538
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3539
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3540
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3541
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3542
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3543
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3544
706
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3545
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv2i64,
3546
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3547
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3548
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3549
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3550
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3551
706
        GIR_EraseFromParent, /*InsnID*/0,
3552
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3553
706
        // GIR_Coverage, 964,
3554
706
        GIR_Done,
3555
706
      // Label 178: @7562
3556
706
      GIM_Try, /*On fail goto*//*Label 179*/ 7600, // Rule ID 948 //
3557
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3558
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3559
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3560
706
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
3561
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i64,
3562
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3563
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3564
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3565
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3566
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3567
706
        GIR_EraseFromParent, /*InsnID*/0,
3568
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3569
706
        // GIR_Coverage, 948,
3570
706
        GIR_Done,
3571
706
      // Label 179: @7600
3572
706
      GIM_Reject,
3573
706
    // Label 174: @7601
3574
706
    GIM_Reject,
3575
706
    // Label 154: @7602
3576
706
    GIM_Try, /*On fail goto*//*Label 180*/ 7714,
3577
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
3578
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
3579
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3580
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3581
706
      GIM_Try, /*On fail goto*//*Label 181*/ 7679, // Rule ID 902 //
3582
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3583
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3584
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3585
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3586
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3587
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3588
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3589
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3590
706
        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3591
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i16,
3592
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3593
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3594
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3595
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3596
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3597
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3598
706
        GIR_EraseFromParent, /*InsnID*/0,
3599
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3600
706
        // GIR_Coverage, 902,
3601
706
        GIR_Done,
3602
706
      // Label 181: @7679
3603
706
      GIM_Try, /*On fail goto*//*Label 182*/ 7713, // Rule ID 942 //
3604
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3605
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3606
706
        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3607
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i16,
3608
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3609
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3610
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3611
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3612
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3613
706
        GIR_EraseFromParent, /*InsnID*/0,
3614
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3615
706
        // GIR_Coverage, 942,
3616
706
        GIR_Done,
3617
706
      // Label 182: @7713
3618
706
      GIM_Reject,
3619
706
    // Label 180: @7714
3620
706
    GIM_Reject,
3621
706
    // Label 155: @7715
3622
706
    GIM_Try, /*On fail goto*//*Label 183*/ 8061,
3623
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3624
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
3625
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3626
706
      GIM_Try, /*On fail goto*//*Label 184*/ 7793, // Rule ID 954 //
3627
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3628
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3629
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3630
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3631
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3632
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3633
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3634
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3635
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3636
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3637
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3638
706
        // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3639
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv4i32,
3640
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3641
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3642
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3643
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3644
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3645
706
        GIR_EraseFromParent, /*InsnID*/0,
3646
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3647
706
        // GIR_Coverage, 954,
3648
706
        GIR_Done,
3649
706
      // Label 184: @7793
3650
706
      GIM_Try, /*On fail goto*//*Label 185*/ 7857, // Rule ID 957 //
3651
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3652
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3653
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3654
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3655
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3656
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3657
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3658
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3659
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3660
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3661
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3662
706
        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3663
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
3664
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3665
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3666
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3667
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3668
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3669
706
        GIR_EraseFromParent, /*InsnID*/0,
3670
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3671
706
        // GIR_Coverage, 957,
3672
706
        GIR_Done,
3673
706
      // Label 185: @7857
3674
706
      GIM_Try, /*On fail goto*//*Label 186*/ 7920, // Rule ID 906 //
3675
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3676
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3677
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3678
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3679
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3680
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3681
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3682
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3683
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3684
706
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3685
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i32,
3686
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3687
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3688
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3689
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3690
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3691
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3692
706
        GIR_EraseFromParent, /*InsnID*/0,
3693
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3694
706
        // GIR_Coverage, 906,
3695
706
        GIR_Done,
3696
706
      // Label 186: @7920
3697
706
      GIM_Try, /*On fail goto*//*Label 187*/ 7971, // Rule ID 960 //
3698
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3699
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3700
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3701
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3702
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3703
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3704
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3705
706
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3706
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv4i32,
3707
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3708
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3709
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3710
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3711
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3712
706
        GIR_EraseFromParent, /*InsnID*/0,
3713
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3714
706
        // GIR_Coverage, 960,
3715
706
        GIR_Done,
3716
706
      // Label 187: @7971
3717
706
      GIM_Try, /*On fail goto*//*Label 188*/ 8022, // Rule ID 963 //
3718
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3719
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3720
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3721
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3722
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3723
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3724
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3725
706
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3726
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv4i32,
3727
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3728
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3729
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3730
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3731
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3732
706
        GIR_EraseFromParent, /*InsnID*/0,
3733
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3734
706
        // GIR_Coverage, 963,
3735
706
        GIR_Done,
3736
706
      // Label 188: @8022
3737
706
      GIM_Try, /*On fail goto*//*Label 189*/ 8060, // Rule ID 946 //
3738
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3739
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3740
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3741
706
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3742
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i32,
3743
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3744
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3745
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3746
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3747
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3748
706
        GIR_EraseFromParent, /*InsnID*/0,
3749
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3750
706
        // GIR_Coverage, 946,
3751
706
        GIR_Done,
3752
706
      // Label 189: @8060
3753
706
      GIM_Reject,
3754
706
    // Label 183: @8061
3755
706
    GIM_Reject,
3756
706
    // Label 156: @8062
3757
706
    GIM_Try, /*On fail goto*//*Label 190*/ 8174,
3758
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
3759
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
3760
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3761
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3762
706
      GIM_Try, /*On fail goto*//*Label 191*/ 8139, // Rule ID 901 //
3763
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3764
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3765
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3766
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3767
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3768
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3769
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3770
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3771
706
        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3772
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i8,
3773
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3774
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3775
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3776
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3777
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3778
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3779
706
        GIR_EraseFromParent, /*InsnID*/0,
3780
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3781
706
        // GIR_Coverage, 901,
3782
706
        GIR_Done,
3783
706
      // Label 191: @8139
3784
706
      GIM_Try, /*On fail goto*//*Label 192*/ 8173, // Rule ID 941 //
3785
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3786
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3787
706
        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3788
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i8,
3789
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3790
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3791
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3792
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3793
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3794
706
        GIR_EraseFromParent, /*InsnID*/0,
3795
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3796
706
        // GIR_Coverage, 941,
3797
706
        GIR_Done,
3798
706
      // Label 192: @8173
3799
706
      GIM_Reject,
3800
706
    // Label 190: @8174
3801
706
    GIM_Reject,
3802
706
    // Label 157: @8175
3803
706
    GIM_Try, /*On fail goto*//*Label 193*/ 8521,
3804
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3805
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
3806
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3807
706
      GIM_Try, /*On fail goto*//*Label 194*/ 8253, // Rule ID 953 //
3808
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3809
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3810
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3811
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3812
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3813
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3814
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3815
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3816
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3817
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3818
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3819
706
        // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3820
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv8i16,
3821
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3822
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3823
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3824
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3825
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3826
706
        GIR_EraseFromParent, /*InsnID*/0,
3827
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3828
706
        // GIR_Coverage, 953,
3829
706
        GIR_Done,
3830
706
      // Label 194: @8253
3831
706
      GIM_Try, /*On fail goto*//*Label 195*/ 8317, // Rule ID 956 //
3832
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3833
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3834
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3835
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3836
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3837
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3838
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3839
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3840
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3841
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3842
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3843
706
        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3844
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
3845
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3846
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3847
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3848
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3849
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3850
706
        GIR_EraseFromParent, /*InsnID*/0,
3851
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3852
706
        // GIR_Coverage, 956,
3853
706
        GIR_Done,
3854
706
      // Label 195: @8317
3855
706
      GIM_Try, /*On fail goto*//*Label 196*/ 8380, // Rule ID 905 //
3856
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3857
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3858
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3859
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3860
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3861
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3862
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3863
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3864
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3865
706
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3866
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i16,
3867
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3868
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3869
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3870
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3871
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3872
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3873
706
        GIR_EraseFromParent, /*InsnID*/0,
3874
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3875
706
        // GIR_Coverage, 905,
3876
706
        GIR_Done,
3877
706
      // Label 196: @8380
3878
706
      GIM_Try, /*On fail goto*//*Label 197*/ 8431, // Rule ID 959 //
3879
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3880
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3881
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3882
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3883
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3884
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3885
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3886
706
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3887
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv8i16,
3888
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3889
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3890
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3891
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3892
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3893
706
        GIR_EraseFromParent, /*InsnID*/0,
3894
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3895
706
        // GIR_Coverage, 959,
3896
706
        GIR_Done,
3897
706
      // Label 197: @8431
3898
706
      GIM_Try, /*On fail goto*//*Label 198*/ 8482, // Rule ID 962 //
3899
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3900
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3901
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3902
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3903
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3904
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3905
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3906
706
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3907
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv8i16,
3908
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3909
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3910
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3911
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3912
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3913
706
        GIR_EraseFromParent, /*InsnID*/0,
3914
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3915
706
        // GIR_Coverage, 962,
3916
706
        GIR_Done,
3917
706
      // Label 198: @8482
3918
706
      GIM_Try, /*On fail goto*//*Label 199*/ 8520, // Rule ID 945 //
3919
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3920
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3921
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3922
706
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3923
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i16,
3924
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3925
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3926
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3927
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3928
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3929
706
        GIR_EraseFromParent, /*InsnID*/0,
3930
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3931
706
        // GIR_Coverage, 945,
3932
706
        GIR_Done,
3933
706
      // Label 199: @8520
3934
706
      GIM_Reject,
3935
706
    // Label 193: @8521
3936
706
    GIM_Reject,
3937
706
    // Label 158: @8522
3938
706
    GIM_Try, /*On fail goto*//*Label 200*/ 8634,
3939
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3940
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3941
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3942
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3943
706
      GIM_Try, /*On fail goto*//*Label 201*/ 8599, // Rule ID 904 //
3944
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3945
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3946
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3947
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3948
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3949
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3950
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3951
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3952
706
        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3953
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv16i8,
3954
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3955
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3956
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3957
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3958
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3959
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3960
706
        GIR_EraseFromParent, /*InsnID*/0,
3961
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3962
706
        // GIR_Coverage, 904,
3963
706
        GIR_Done,
3964
706
      // Label 201: @8599
3965
706
      GIM_Try, /*On fail goto*//*Label 202*/ 8633, // Rule ID 944 //
3966
706
        GIM_CheckFeatures, GIFBS_HasNEON,
3967
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3968
706
        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3969
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv16i8,
3970
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3971
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3972
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3973
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3974
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3975
706
        GIR_EraseFromParent, /*InsnID*/0,
3976
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3977
706
        // GIR_Coverage, 944,
3978
706
        GIR_Done,
3979
706
      // Label 202: @8633
3980
706
      GIM_Reject,
3981
706
    // Label 200: @8634
3982
706
    GIM_Reject,
3983
706
    // Label 159: @8635
3984
706
    GIM_Reject,
3985
706
    // Label 2: @8636
3986
706
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 210*/ 9269,
3987
706
    /*GILLT_s32*//*Label 203*/ 8651, 0,
3988
706
    /*GILLT_v2s32*//*Label 204*/ 8963, 0,
3989
706
    /*GILLT_v4s16*//*Label 205*/ 9014,
3990
706
    /*GILLT_v4s32*//*Label 206*/ 9065,
3991
706
    /*GILLT_v8s8*//*Label 207*/ 9116,
3992
706
    /*GILLT_v8s16*//*Label 208*/ 9167,
3993
706
    /*GILLT_v16s8*//*Label 209*/ 9218,
3994
706
    // Label 203: @8651
3995
706
    GIM_Try, /*On fail goto*//*Label 211*/ 8962,
3996
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3997
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3998
706
      GIM_Try, /*On fail goto*//*Label 212*/ 8745, // Rule ID 188 //
3999
706
        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
4000
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4001
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4002
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4003
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4004
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4005
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4006
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
4007
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4008
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
4009
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
4010
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4011
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4012
706
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
4013
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4014
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4015
706
        // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4016
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
4017
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4018
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4019
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4020
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4021
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4022
706
        GIR_EraseFromParent, /*InsnID*/0,
4023
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4024
706
        // GIR_Coverage, 188,
4025
706
        GIR_Done,
4026
706
      // Label 212: @8745
4027
706
      GIM_Try, /*On fail goto*//*Label 213*/ 8829, // Rule ID 519 //
4028
706
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4029
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4030
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4031
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4032
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4033
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4034
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4035
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
4036
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4037
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
4038
706
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
4039
706
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4040
706
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4041
706
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
4042
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4043
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4044
706
        // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4045
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
4046
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4047
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4048
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4049
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4050
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4051
706
        GIR_EraseFromParent, /*InsnID*/0,
4052
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4053
706
        // GIR_Coverage, 519,
4054
706
        GIR_Done,
4055
706
      // Label 213: @8829
4056
706
      GIM_Try, /*On fail goto*//*Label 214*/ 8874, // Rule ID 171 //
4057
706
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4058
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4059
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4060
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4061
706
        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
4062
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MUL,
4063
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4064
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4065
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4066
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4067
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4068
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4069
706
        GIR_EraseFromParent, /*InsnID*/0,
4070
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4071
706
        // GIR_Coverage, 171,
4072
706
        GIR_Done,
4073
706
      // Label 214: @8874
4074
706
      GIM_Try, /*On fail goto*//*Label 215*/ 8919, // Rule ID 172 //
4075
706
        GIM_CheckFeatures, GIFBS_IsARM_NoV6_UseMulOps,
4076
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4077
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4078
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4079
706
        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
4080
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MULv5,
4081
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4082
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4083
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4084
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4085
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4086
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4087
706
        GIR_EraseFromParent, /*InsnID*/0,
4088
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4089
706
        // GIR_Coverage, 172,
4090
706
        GIR_Done,
4091
706
      // Label 215: @8919
4092
706
      GIM_Try, /*On fail goto*//*Label 216*/ 8961, // Rule ID 506 //
4093
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
4094
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4095
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4096
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4097
706
        // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4098
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MUL,
4099
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4100
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4101
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4102
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4103
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4104
706
        GIR_EraseFromParent, /*InsnID*/0,
4105
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4106
706
        // GIR_Coverage, 506,
4107
706
        GIR_Done,
4108
706
      // Label 216: @8961
4109
706
      GIM_Reject,
4110
706
    // Label 211: @8962
4111
706
    GIM_Reject,
4112
706
    // Label 204: @8963
4113
706
    GIM_Try, /*On fail goto*//*Label 217*/ 9013, // Rule ID 823 //
4114
706
      GIM_CheckFeatures, GIFBS_HasNEON,
4115
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
4116
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
4117
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4118
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4119
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4120
706
      // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4121
706
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv2i32,
4122
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4123
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4124
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4125
706
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4126
706
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4127
706
      GIR_EraseFromParent, /*InsnID*/0,
4128
706
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4129
706
      // GIR_Coverage, 823,
4130
706
      GIR_Done,
4131
706
    // Label 217: @9013
4132
706
    GIM_Reject,
4133
706
    // Label 205: @9014
4134
706
    GIM_Try, /*On fail goto*//*Label 218*/ 9064, // Rule ID 822 //
4135
706
      GIM_CheckFeatures, GIFBS_HasNEON,
4136
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4137
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4138
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4139
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4140
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4141
706
      // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4142
706
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i16,
4143
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4144
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4145
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4146
706
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4147
706
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4148
706
      GIR_EraseFromParent, /*InsnID*/0,
4149
706
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4150
706
      // GIR_Coverage, 822,
4151
706
      GIR_Done,
4152
706
    // Label 218: @9064
4153
706
    GIM_Reject,
4154
706
    // Label 206: @9065
4155
706
    GIM_Try, /*On fail goto*//*Label 219*/ 9115, // Rule ID 826 //
4156
706
      GIM_CheckFeatures, GIFBS_HasNEON,
4157
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4158
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4159
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4160
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4161
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4162
706
      // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4163
706
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i32,
4164
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4165
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4166
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4167
706
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4168
706
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4169
706
      GIR_EraseFromParent, /*InsnID*/0,
4170
706
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4171
706
      // GIR_Coverage, 826,
4172
706
      GIR_Done,
4173
706
    // Label 219: @9115
4174
706
    GIM_Reject,
4175
706
    // Label 207: @9116
4176
706
    GIM_Try, /*On fail goto*//*Label 220*/ 9166, // Rule ID 821 //
4177
706
      GIM_CheckFeatures, GIFBS_HasNEON,
4178
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4179
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4180
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4181
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4182
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4183
706
      // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4184
706
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i8,
4185
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4186
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4187
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4188
706
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4189
706
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4190
706
      GIR_EraseFromParent, /*InsnID*/0,
4191
706
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4192
706
      // GIR_Coverage, 821,
4193
706
      GIR_Done,
4194
706
    // Label 220: @9166
4195
706
    GIM_Reject,
4196
706
    // Label 208: @9167
4197
706
    GIM_Try, /*On fail goto*//*Label 221*/ 9217, // Rule ID 825 //
4198
706
      GIM_CheckFeatures, GIFBS_HasNEON,
4199
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4200
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4201
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4202
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4203
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4204
706
      // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4205
706
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i16,
4206
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4207
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4208
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4209
706
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4210
706
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4211
706
      GIR_EraseFromParent, /*InsnID*/0,
4212
706
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4213
706
      // GIR_Coverage, 825,
4214
706
      GIR_Done,
4215
706
    // Label 221: @9217
4216
706
    GIM_Reject,
4217
706
    // Label 209: @9218
4218
706
    GIM_Try, /*On fail goto*//*Label 222*/ 9268, // Rule ID 824 //
4219
706
      GIM_CheckFeatures, GIFBS_HasNEON,
4220
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4221
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
4222
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4223
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4224
706
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4225
706
      // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4226
706
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv16i8,
4227
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4228
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4229
706
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4230
706
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4231
706
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4232
706
      GIR_EraseFromParent, /*InsnID*/0,
4233
706
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4234
706
      // GIR_Coverage, 824,
4235
706
      GIR_Done,
4236
706
    // Label 222: @9268
4237
706
    GIM_Reject,
4238
706
    // Label 210: @9269
4239
706
    GIM_Reject,
4240
706
    // Label 3: @9270
4241
706
    GIM_Try, /*On fail goto*//*Label 223*/ 9369,
4242
706
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4243
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4244
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4245
706
      GIM_Try, /*On fail goto*//*Label 224*/ 9326, // Rule ID 197 //
4246
706
        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
4247
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4248
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4249
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4250
706
        // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4251
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SDIV,
4252
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4253
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4254
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4255
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4256
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4257
706
        GIR_EraseFromParent, /*InsnID*/0,
4258
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4259
706
        // GIR_Coverage, 197,
4260
706
        GIR_Done,
4261
706
      // Label 224: @9326
4262
706
      GIM_Try, /*On fail goto*//*Label 225*/ 9368, // Rule ID 536 //
4263
706
        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
4264
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4265
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4266
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4267
706
        // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4268
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SDIV,
4269
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4270
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4271
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4272
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4273
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4274
706
        GIR_EraseFromParent, /*InsnID*/0,
4275
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4276
706
        // GIR_Coverage, 536,
4277
706
        GIR_Done,
4278
706
      // Label 225: @9368
4279
706
      GIM_Reject,
4280
706
    // Label 223: @9369
4281
706
    GIM_Reject,
4282
706
    // Label 4: @9370
4283
706
    GIM_Try, /*On fail goto*//*Label 226*/ 9469,
4284
706
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4285
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4286
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4287
706
      GIM_Try, /*On fail goto*//*Label 227*/ 9426, // Rule ID 198 //
4288
706
        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
4289
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4290
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4291
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4292
706
        // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4293
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDIV,
4294
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4295
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4296
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4297
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4298
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4299
706
        GIR_EraseFromParent, /*InsnID*/0,
4300
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4301
706
        // GIR_Coverage, 198,
4302
706
        GIR_Done,
4303
706
      // Label 227: @9426
4304
706
      GIM_Try, /*On fail goto*//*Label 228*/ 9468, // Rule ID 537 //
4305
706
        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
4306
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4307
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4308
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4309
706
        // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4310
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDIV,
4311
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4312
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4313
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4314
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4315
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4316
706
        GIR_EraseFromParent, /*InsnID*/0,
4317
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4318
706
        // GIR_Coverage, 537,
4319
706
        GIR_Done,
4320
706
      // Label 228: @9468
4321
706
      GIM_Reject,
4322
706
    // Label 226: @9469
4323
706
    GIM_Reject,
4324
706
    // Label 5: @9470
4325
706
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 232*/ 11182,
4326
706
    /*GILLT_s32*//*Label 229*/ 9482, 0,
4327
706
    /*GILLT_v2s32*//*Label 230*/ 11080, 0, 0,
4328
706
    /*GILLT_v4s32*//*Label 231*/ 11131,
4329
706
    // Label 229: @9482
4330
706
    GIM_Try, /*On fail goto*//*Label 233*/ 11079,
4331
706
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4332
706
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4333
706
      GIM_Try, /*On fail goto*//*Label 234*/ 9554, // Rule ID 1707 //
4334
706
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4335
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4336
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4337
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
4338
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4339
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4340
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4341
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
4342
706
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4343
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4344
706
        // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
4345
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4346
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4347
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
4348
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
4349
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4350
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4351
706
        GIR_EraseFromParent, /*InsnID*/0,
4352
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4353
706
        // GIR_Coverage, 1707,
4354
706
        GIR_Done,
4355
706
      // Label 234: @9554
4356
706
      GIM_Try, /*On fail goto*//*Label 235*/ 9616, // Rule ID 1909 //
4357
706
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4358
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4359
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4360
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
4361
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4362
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4363
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4364
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
4365
706
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4366
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4367
706
        // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
4368
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4369
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4370
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
4371
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
4372
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4373
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4374
706
        GIR_EraseFromParent, /*InsnID*/0,
4375
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4376
706
        // GIR_Coverage, 1909,
4377
706
        GIR_Done,
4378
706
      // Label 235: @9616
4379
706
      GIM_Try, /*On fail goto*//*Label 236*/ 9657, // Rule ID 1810 //
4380
706
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4381
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4382
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4383
706
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
4384
706
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] })  =>  (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4385
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB,
4386
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4387
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4388
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4389
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4390
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4391
706
        GIR_EraseFromParent, /*InsnID*/0,
4392
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4393
706
        // GIR_Coverage, 1810,
4394
706
        GIR_Done,
4395
706
      // Label 236: @9657
4396
706
      GIM_Try, /*On fail goto*//*Label 237*/ 9698, // Rule ID 1811 //
4397
706
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4398
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4399
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4400
706
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
4401
706
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] })  =>  (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4402
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTH,
4403
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4404
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4405
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4406
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4407
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4408
706
        GIR_EraseFromParent, /*InsnID*/0,
4409
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4410
706
        // GIR_Coverage, 1811,
4411
706
        GIR_Done,
4412
706
      // Label 237: @9698
4413
706
      GIM_Try, /*On fail goto*//*Label 238*/ 9739, // Rule ID 1812 //
4414
706
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4415
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4416
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4417
706
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4418
706
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4419
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4420
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4421
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4422
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4423
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4424
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4425
706
        GIR_EraseFromParent, /*InsnID*/0,
4426
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4427
706
        // GIR_Coverage, 1812,
4428
706
        GIR_Done,
4429
706
      // Label 238: @9739
4430
706
      GIM_Try, /*On fail goto*//*Label 239*/ 9780, // Rule ID 1996 //
4431
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
4432
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4433
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4434
706
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
4435
706
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })  =>  (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4436
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB,
4437
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4438
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4439
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4440
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4441
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4442
706
        GIR_EraseFromParent, /*InsnID*/0,
4443
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4444
706
        // GIR_Coverage, 1996,
4445
706
        GIR_Done,
4446
706
      // Label 239: @9780
4447
706
      GIM_Try, /*On fail goto*//*Label 240*/ 9821, // Rule ID 1997 //
4448
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
4449
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4450
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4451
706
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
4452
706
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })  =>  (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4453
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTH,
4454
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4455
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4456
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4457
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4458
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4459
706
        GIR_EraseFromParent, /*InsnID*/0,
4460
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4461
706
        // GIR_Coverage, 1997,
4462
706
        GIR_Done,
4463
706
      // Label 240: @9821
4464
706
      GIM_Try, /*On fail goto*//*Label 241*/ 9862, // Rule ID 1998 //
4465
706
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4466
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4467
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4468
706
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4469
706
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4470
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4471
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4472
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4473
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4474
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4475
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4476
706
        GIR_EraseFromParent, /*InsnID*/0,
4477
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4478
706
        // GIR_Coverage, 1998,
4479
706
        GIR_Done,
4480
706
      // Label 241: @9862
4481
706
      GIM_Try, /*On fail goto*//*Label 242*/ 9935, // Rule ID 2513 //
4482
706
        GIM_CheckFeatures, GIFBS_IsARM,
4483
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4484
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4485
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4486
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4487
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4488
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4489
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4490
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4491
706
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4492
706
        // MIs[2] Operand 1
4493
706
        // No operand predicates
4494
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4495
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4496
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4497
706
        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4498
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4499
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4500
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4501
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4502
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4503
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4504
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4505
706
        GIR_EraseFromParent, /*InsnID*/0,
4506
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4507
706
        // GIR_Coverage, 2513,
4508
706
        GIR_Done,
4509
706
      // Label 242: @9935
4510
706
      GIM_Try, /*On fail goto*//*Label 243*/ 10008, // Rule ID 2546 //
4511
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
4512
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4513
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4514
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4515
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4516
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4517
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4518
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4519
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4520
706
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4521
706
        // MIs[2] Operand 1
4522
706
        // No operand predicates
4523
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4524
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4525
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4526
706
        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4527
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4528
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4529
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4530
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4531
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4532
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4533
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4534
706
        GIR_EraseFromParent, /*InsnID*/0,
4535
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4536
706
        // GIR_Coverage, 2546,
4537
706
        GIR_Done,
4538
706
      // Label 243: @10008
4539
706
      GIM_Try, /*On fail goto*//*Label 244*/ 10081, // Rule ID 2512 //
4540
706
        GIM_CheckFeatures, GIFBS_IsARM,
4541
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4542
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4543
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4544
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4545
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4546
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4547
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4548
706
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4549
706
        // MIs[2] Operand 1
4550
706
        // No operand predicates
4551
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4552
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4553
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4554
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4555
706
        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4556
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4557
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4558
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4559
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4560
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4561
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4562
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4563
706
        GIR_EraseFromParent, /*InsnID*/0,
4564
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4565
706
        // GIR_Coverage, 2512,
4566
706
        GIR_Done,
4567
706
      // Label 244: @10081
4568
706
      GIM_Try, /*On fail goto*//*Label 245*/ 10154, // Rule ID 2545 //
4569
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
4570
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4571
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4572
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4573
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4574
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4575
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4576
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4577
706
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4578
706
        // MIs[2] Operand 1
4579
706
        // No operand predicates
4580
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4581
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4582
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4583
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4584
706
        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4585
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4586
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4587
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4588
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4589
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4590
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4591
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4592
706
        GIR_EraseFromParent, /*InsnID*/0,
4593
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4594
706
        // GIR_Coverage, 2545,
4595
706
        GIR_Done,
4596
706
      // Label 245: @10154
4597
706
      GIM_Try, /*On fail goto*//*Label 246*/ 10227, // Rule ID 2511 //
4598
706
        GIM_CheckFeatures, GIFBS_IsARM,
4599
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4600
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4601
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4602
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4603
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4604
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4605
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4606
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4607
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4608
706
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4609
706
        // MIs[2] Operand 1
4610
706
        // No operand predicates
4611
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4612
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4613
706
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4614
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4615
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4616
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4617
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4618
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4619
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4620
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4621
706
        GIR_EraseFromParent, /*InsnID*/0,
4622
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4623
706
        // GIR_Coverage, 2511,
4624
706
        GIR_Done,
4625
706
      // Label 246: @10227
4626
706
      GIM_Try, /*On fail goto*//*Label 247*/ 10300, // Rule ID 2544 //
4627
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
4628
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4629
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4630
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4631
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4632
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4633
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4634
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4635
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4636
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4637
706
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4638
706
        // MIs[2] Operand 1
4639
706
        // No operand predicates
4640
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4641
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4642
706
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4643
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4644
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4645
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4646
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4647
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4648
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4649
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4650
706
        GIR_EraseFromParent, /*InsnID*/0,
4651
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4652
706
        // GIR_Coverage, 2544,
4653
706
        GIR_Done,
4654
706
      // Label 247: @10300
4655
706
      GIM_Try, /*On fail goto*//*Label 248*/ 10373, // Rule ID 161 //
4656
706
        GIM_CheckFeatures, GIFBS_IsARM,
4657
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4658
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4659
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4660
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4661
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4662
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4663
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4664
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4665
706
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4666
706
        // MIs[2] Operand 1
4667
706
        // No operand predicates
4668
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4669
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4670
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4671
706
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4672
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4673
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4674
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4675
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4676
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4677
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4678
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4679
706
        GIR_EraseFromParent, /*InsnID*/0,
4680
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4681
706
        // GIR_Coverage, 161,
4682
706
        GIR_Done,
4683
706
      // Label 248: @10373
4684
706
      GIM_Try, /*On fail goto*//*Label 249*/ 10446, // Rule ID 494 //
4685
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
4686
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4687
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4688
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4689
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4690
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4691
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4692
706
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4693
706
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4694
706
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4695
706
        // MIs[2] Operand 1
4696
706
        // No operand predicates
4697
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4698
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4699
706
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4700
706
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4701
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4702
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4703
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4704
706
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4705
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4706
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4707
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4708
706
        GIR_EraseFromParent, /*InsnID*/0,
4709
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4710
706
        // GIR_Coverage, 494,
4711
706
        GIR_Done,
4712
706
      // Label 249: @10446
4713
706
      GIM_Try, /*On fail goto*//*Label 250*/ 10512, // Rule ID 2514 //
4714
706
        GIM_CheckFeatures, GIFBS_IsARM,
4715
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4716
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4717
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4718
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4719
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4720
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4721
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4722
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4723
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4724
706
        // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4725
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
4726
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4727
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4728
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4729
706
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4730
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4731
706
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4732
706
        GIR_EraseFromParent, /*InsnID*/0,
4733
706
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4734
706
        // GIR_Coverage, 2514,
4735
706
        GIR_Done,
4736
706
      // Label 250: @10512
4737
706
      GIM_Try, /*On fail goto*//*Label 251*/ 10578, // Rule ID 2547 //
4738
706
        GIM_CheckFeatures, GIFBS_IsThumb2,
4739
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4740
706
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4741
706
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4742
706
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4743
706
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4744
706
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4745
706
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4746
706
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4747
706
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4748
706
        // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4749
706
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
4750
706
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd