Coverage Report

Created: 2018-12-14 11:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenGlobalISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the ARM target                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 64;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(0),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_NoHonorSignDependentRoundingBit = 57,
37
  Feature_HasV4TBit = 6,
38
  Feature_NoV4TBit = 7,
39
  Feature_HasV5TBit = 8,
40
  Feature_NoV5TBit = 54,
41
  Feature_HasV5TEBit = 12,
42
  Feature_HasV6Bit = 0,
43
  Feature_NoV6Bit = 10,
44
  Feature_HasV6MBit = 29,
45
  Feature_HasV8MBaselineBit = 33,
46
  Feature_HasV6T2Bit = 9,
47
  Feature_HasV6KBit = 19,
48
  Feature_HasV7Bit = 3,
49
  Feature_HasV8Bit = 15,
50
  Feature_PreV8Bit = 20,
51
  Feature_HasV8_1aBit = 59,
52
  Feature_NoVFPBit = 23,
53
  Feature_HasVFP2Bit = 22,
54
  Feature_HasVFP3Bit = 46,
55
  Feature_HasVFP4Bit = 44,
56
  Feature_HasDPVFPBit = 39,
57
  Feature_HasFPARMv8Bit = 41,
58
  Feature_HasNEONBit = 47,
59
  Feature_HasCryptoBit = 48,
60
  Feature_HasDotProdBit = 49,
61
  Feature_HasCRCBit = 14,
62
  Feature_HasFP16Bit = 53,
63
  Feature_HasFullFP16Bit = 38,
64
  Feature_HasDivideInThumbBit = 35,
65
  Feature_HasDivideInARMBit = 13,
66
  Feature_HasDSPBit = 34,
67
  Feature_HasDBBit = 16,
68
  Feature_HasV7ClrexBit = 18,
69
  Feature_HasAcquireReleaseBit = 17,
70
  Feature_HasMPBit = 2,
71
  Feature_HasZCZBit = 50,
72
  Feature_UseNEONForFPBit = 62,
73
  Feature_DontUseNEONForFPBit = 40,
74
  Feature_IsThumbBit = 27,
75
  Feature_IsThumb1OnlyBit = 28,
76
  Feature_IsThumb2Bit = 32,
77
  Feature_IsNotMClassBit = 36,
78
  Feature_IsARMBit = 1,
79
  Feature_IsWindowsBit = 30,
80
  Feature_IsNotWindowsBit = 31,
81
  Feature_IsReadTPHardBit = 55,
82
  Feature_IsReadTPSoftBit = 21,
83
  Feature_UseNaClTrapBit = 4,
84
  Feature_DontUseNaClTrapBit = 5,
85
  Feature_UseMovtBit = 37,
86
  Feature_DontUseMovtBit = 24,
87
  Feature_UseMovtInPicBit = 25,
88
  Feature_DontUseMovtInPicBit = 26,
89
  Feature_UseFPVMLxBit = 43,
90
  Feature_UseMulOpsBit = 11,
91
  Feature_UseFusedMACBit = 45,
92
  Feature_HasFastVGETLNi32Bit = 51,
93
  Feature_HasSlowVGETLNi32Bit = 60,
94
  Feature_HasFastVDUP32Bit = 52,
95
  Feature_HasSlowVDUP32Bit = 61,
96
  Feature_UseVMOVSRBit = 42,
97
  Feature_DontUseVMOVSRBit = 63,
98
  Feature_IsLEBit = 56,
99
  Feature_IsBEBit = 58,
100
};
101
102
PredicateBitset ARMInstructionSelector::
103
6.86k
computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
104
6.86k
  PredicateBitset Features;
105
6.86k
  if (!TM.Options.HonorSignDependentRoundingFPMath())
106
6.79k
    Features[Feature_NoHonorSignDependentRoundingBit] = 1;
107
6.86k
  if (Subtarget->hasV4TOps())
108
5.79k
    Features[Feature_HasV4TBit] = 1;
109
6.86k
  if (!Subtarget->hasV4TOps())
110
1.06k
    Features[Feature_NoV4TBit] = 1;
111
6.86k
  if (Subtarget->hasV5TOps())
112
5.55k
    Features[Feature_HasV5TBit] = 1;
113
6.86k
  if (!Subtarget->hasV5TOps())
114
1.30k
    Features[Feature_NoV5TBit] = 1;
115
6.86k
  if (Subtarget->hasV5TEOps())
116
5.50k
    Features[Feature_HasV5TEBit] = 1;
117
6.86k
  if (Subtarget->hasV6Ops())
118
5.47k
    Features[Feature_HasV6Bit] = 1;
119
6.86k
  if (!Subtarget->hasV6Ops())
120
1.38k
    Features[Feature_NoV6Bit] = 1;
121
6.86k
  if (Subtarget->hasV6MOps())
122
5.21k
    Features[Feature_HasV6MBit] = 1;
123
6.86k
  if (Subtarget->hasV8MBaselineOps())
124
4.83k
    Features[Feature_HasV8MBaselineBit] = 1;
125
6.86k
  if (Subtarget->hasV6T2Ops())
126
4.77k
    Features[Feature_HasV6T2Bit] = 1;
127
6.86k
  if (Subtarget->hasV6KOps())
128
4.79k
    Features[Feature_HasV6KBit] = 1;
129
6.86k
  if (Subtarget->hasV7Ops())
130
4.52k
    Features[Feature_HasV7Bit] = 1;
131
6.86k
  if (Subtarget->hasV8Ops())
132
344
    Features[Feature_HasV8Bit] = 1;
133
6.86k
  if (!Subtarget->hasV8Ops())
134
6.51k
    Features[Feature_PreV8Bit] = 1;
135
6.86k
  if (Subtarget->hasV8_1aOps())
136
36
    Features[Feature_HasV8_1aBit] = 1;
137
6.86k
  if (!Subtarget->hasVFP2())
138
2.68k
    Features[Feature_NoVFPBit] = 1;
139
6.86k
  if (Subtarget->hasVFP2())
140
4.17k
    Features[Feature_HasVFP2Bit] = 1;
141
6.86k
  if (Subtarget->hasVFP3())
142
4.01k
    Features[Feature_HasVFP3Bit] = 1;
143
6.86k
  if (Subtarget->hasVFP4())
144
1.57k
    Features[Feature_HasVFP4Bit] = 1;
145
6.86k
  if (!Subtarget->isFPOnlySP())
146
6.55k
    Features[Feature_HasDPVFPBit] = 1;
147
6.86k
  if (Subtarget->hasFPARMv8())
148
472
    Features[Feature_HasFPARMv8Bit] = 1;
149
6.86k
  if (Subtarget->hasNEON())
150
3.57k
    Features[Feature_HasNEONBit] = 1;
151
6.86k
  if (Subtarget->hasCrypto())
152
299
    Features[Feature_HasCryptoBit] = 1;
153
6.86k
  if (Subtarget->hasDotProd())
154
2
    Features[Feature_HasDotProdBit] = 1;
155
6.86k
  if (Subtarget->hasCRC())
156
325
    Features[Feature_HasCRCBit] = 1;
157
6.86k
  if (Subtarget->hasFP16())
158
1.73k
    Features[Feature_HasFP16Bit] = 1;
159
6.86k
  if (Subtarget->hasFullFP16())
160
48
    Features[Feature_HasFullFP16Bit] = 1;
161
6.86k
  if (Subtarget->hasDivideInThumbMode())
162
2.16k
    Features[Feature_HasDivideInThumbBit] = 1;
163
6.86k
  if (Subtarget->hasDivideInARMMode())
164
1.22k
    Features[Feature_HasDivideInARMBit] = 1;
165
6.86k
  if (Subtarget->hasDSP())
166
4.51k
    Features[Feature_HasDSPBit] = 1;
167
6.86k
  if (Subtarget->hasDataBarrier())
168
4.89k
    Features[Feature_HasDBBit] = 1;
169
6.86k
  if (Subtarget->hasV7Clrex())
170
4.58k
    Features[Feature_HasV7ClrexBit] = 1;
171
6.86k
  if (Subtarget->hasAcquireRelease())
172
514
    Features[Feature_HasAcquireReleaseBit] = 1;
173
6.86k
  if (Subtarget->hasMPExtension())
174
1.31k
    Features[Feature_HasMPBit] = 1;
175
6.86k
  if (Subtarget->hasZeroCycleZeroing())
176
43
    Features[Feature_HasZCZBit] = 1;
177
6.86k
  if (Subtarget->useNEONForSinglePrecisionFP())
178
508
    Features[Feature_UseNEONForFPBit] = 1;
179
6.86k
  if (!Subtarget->useNEONForSinglePrecisionFP())
180
6.35k
    Features[Feature_DontUseNEONForFPBit] = 1;
181
6.86k
  if (Subtarget->isThumb())
182
3.85k
    Features[Feature_IsThumbBit] = 1;
183
6.86k
  if (Subtarget->isThumb1Only())
184
688
    Features[Feature_IsThumb1OnlyBit] = 1;
185
6.86k
  if (Subtarget->isThumb2())
186
3.16k
    Features[Feature_IsThumb2Bit] = 1;
187
6.86k
  if (!Subtarget->isMClass())
188
5.54k
    Features[Feature_IsNotMClassBit] = 1;
189
6.86k
  if (!Subtarget->isThumb())
190
3.00k
    Features[Feature_IsARMBit] = 1;
191
6.86k
  if (Subtarget->isTargetWindows())
192
84
    Features[Feature_IsWindowsBit] = 1;
193
6.86k
  if (!Subtarget->isTargetWindows())
194
6.77k
    Features[Feature_IsNotWindowsBit] = 1;
195
6.86k
  if (Subtarget->isReadTPHard())
196
2
    Features[Feature_IsReadTPHardBit] = 1;
197
6.86k
  if (!Subtarget->isReadTPHard())
198
6.85k
    Features[Feature_IsReadTPSoftBit] = 1;
199
6.86k
  if (Subtarget->useNaClTrap())
200
14
    Features[Feature_UseNaClTrapBit] = 1;
201
6.86k
  if (!Subtarget->useNaClTrap())
202
6.84k
    Features[Feature_DontUseNaClTrapBit] = 1;
203
6.86k
  if (Subtarget->useMulOps())
204
6.85k
    Features[Feature_UseMulOpsBit] = 1;
205
6.86k
  if ((TM.Options.AllowFPOpFusion == FPOpFusion::Fast &&  
Subtarget->hasVFP4()102
) &&
!Subtarget->isTargetDarwin()54
&&
Subtarget->useFPVMLx()54
)
206
30
    Features[Feature_UseFusedMACBit] = 1;
207
6.86k
  if (!Subtarget->hasSlowVGETLNi32())
208
6.47k
    Features[Feature_HasFastVGETLNi32Bit] = 1;
209
6.86k
  if (Subtarget->hasSlowVGETLNi32())
210
384
    Features[Feature_HasSlowVGETLNi32Bit] = 1;
211
6.86k
  if (!Subtarget->hasSlowVDUP32())
212
6.47k
    Features[Feature_HasFastVDUP32Bit] = 1;
213
6.86k
  if (Subtarget->hasSlowVDUP32())
214
384
    Features[Feature_HasSlowVDUP32Bit] = 1;
215
6.86k
  if (Subtarget->preferVMOVSR() ||
!Subtarget->useNEONForSinglePrecisionFP()6.75k
)
216
6.36k
    Features[Feature_UseVMOVSRBit] = 1;
217
6.86k
  if (!Subtarget->preferVMOVSR() &&
Subtarget->useNEONForSinglePrecisionFP()6.75k
)
218
500
    Features[Feature_DontUseVMOVSRBit] = 1;
219
6.86k
  return Features;
220
6.86k
}
221
222
PredicateBitset ARMInstructionSelector::
223
736
computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
224
736
  PredicateBitset Features;
225
736
  if (Subtarget->useMovt(*MF))
226
296
    Features[Feature_UseMovtBit] = 1;
227
736
  if (!Subtarget->useMovt(*MF))
228
440
    Features[Feature_DontUseMovtBit] = 1;
229
736
  if (Subtarget->useMovt(*MF) && 
Subtarget->allowPositionIndependentMovt()296
)
230
56
    Features[Feature_UseMovtInPicBit] = 1;
231
736
  if (!Subtarget->useMovt(*MF) || 
!Subtarget->allowPositionIndependentMovt()296
)
232
680
    Features[Feature_DontUseMovtInPicBit] = 1;
233
736
  if (((Subtarget->useFPVMLx() &&  TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||
MF->getFunction().optForMinSize()0
))
234
736
    Features[Feature_UseFPVMLxBit] = 1;
235
736
  if (MF->getDataLayout().isLittleEndian())
236
736
    Features[Feature_IsLEBit] = 1;
237
736
  if (MF->getDataLayout().isBigEndian())
238
0
    Features[Feature_IsBEBit] = 1;
239
736
  return Features;
240
736
}
241
242
// LLT Objects.
243
enum {
244
  GILLT_s16,
245
  GILLT_s32,
246
  GILLT_s64,
247
  GILLT_v2s32,
248
  GILLT_v2s64,
249
  GILLT_v4s16,
250
  GILLT_v4s32,
251
  GILLT_v8s8,
252
  GILLT_v8s16,
253
  GILLT_v16s8,
254
};
255
const static size_t NumTypeObjects = 10;
256
const static LLT TypeObjects[] = {
257
  LLT::scalar(16),
258
  LLT::scalar(32),
259
  LLT::scalar(64),
260
  LLT::vector(2, 32),
261
  LLT::vector(2, 64),
262
  LLT::vector(4, 16),
263
  LLT::vector(4, 32),
264
  LLT::vector(8, 8),
265
  LLT::vector(8, 16),
266
  LLT::vector(16, 8),
267
};
268
269
// Feature bitsets.
270
enum {
271
  GIFBS_Invalid,
272
  GIFBS_HasDotProd,
273
  GIFBS_HasFPARMv8,
274
  GIFBS_HasFullFP16,
275
  GIFBS_HasNEON,
276
  GIFBS_HasVFP2,
277
  GIFBS_HasVFP4,
278
  GIFBS_IsARM,
279
  GIFBS_IsBE,
280
  GIFBS_IsLE,
281
  GIFBS_IsThumb,
282
  GIFBS_IsThumb2,
283
  GIFBS_NoHonorSignDependentRounding,
284
  GIFBS_DontUseNEONForFP_HasVFP2,
285
  GIFBS_HasCrypto_HasV8,
286
  GIFBS_HasDB_IsARM,
287
  GIFBS_HasDB_IsThumb,
288
  GIFBS_HasDPVFP_HasFPARMv8,
289
  GIFBS_HasDPVFP_HasVFP2,
290
  GIFBS_HasDPVFP_HasVFP4,
291
  GIFBS_HasDPVFP_NoHonorSignDependentRounding,
292
  GIFBS_HasDSP_IsThumb2,
293
  GIFBS_HasDivideInARM_IsARM,
294
  GIFBS_HasFP16_HasNEON,
295
  GIFBS_HasFullFP16_HasNEON,
296
  GIFBS_HasNEON_HasV8,
297
  GIFBS_HasNEON_HasV8_1a,
298
  GIFBS_HasV5T_IsARM,
299
  GIFBS_HasV5TE_IsARM,
300
  GIFBS_HasV6_IsARM,
301
  GIFBS_HasV6K_IsARM,
302
  GIFBS_HasV6M_IsThumb,
303
  GIFBS_HasV6T2_IsARM,
304
  GIFBS_HasV6T2_IsThumb2,
305
  GIFBS_HasV7_IsARM,
306
  GIFBS_HasV7Clrex_IsThumb,
307
  GIFBS_HasV8MBaseline_IsThumb,
308
  GIFBS_HasVFP2_UseVMOVSR,
309
  GIFBS_IsARM_NoV6,
310
  GIFBS_IsARM_PreV8,
311
  GIFBS_IsThumb_IsThumb1Only,
312
  GIFBS_IsThumb_IsWindows,
313
  GIFBS_IsThumb_UseMovt,
314
  GIFBS_IsThumb2_PreV8,
315
  GIFBS_IsThumb2_UseMulOps,
316
  GIFBS_HasCRC_HasV8_IsARM,
317
  GIFBS_HasCRC_HasV8_IsThumb2,
318
  GIFBS_HasDSP_IsThumb2_UseMulOps,
319
  GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
320
  GIFBS_HasFullFP16_HasNEON_HasV8,
321
  GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
322
  GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
323
  GIFBS_HasV5TE_IsARM_UseMulOps,
324
  GIFBS_HasV6_IsARM_UseMulOps,
325
  GIFBS_HasV6_IsThumb_IsThumb1Only,
326
  GIFBS_HasV6T2_IsARM_UseMulOps,
327
  GIFBS_IsARM_NoV6_UseMulOps,
328
};
329
const static PredicateBitset FeatureBitsets[] {
330
  {}, // GIFBS_Invalid
331
  {Feature_HasDotProdBit, },
332
  {Feature_HasFPARMv8Bit, },
333
  {Feature_HasFullFP16Bit, },
334
  {Feature_HasNEONBit, },
335
  {Feature_HasVFP2Bit, },
336
  {Feature_HasVFP4Bit, },
337
  {Feature_IsARMBit, },
338
  {Feature_IsBEBit, },
339
  {Feature_IsLEBit, },
340
  {Feature_IsThumbBit, },
341
  {Feature_IsThumb2Bit, },
342
  {Feature_NoHonorSignDependentRoundingBit, },
343
  {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
344
  {Feature_HasCryptoBit, Feature_HasV8Bit, },
345
  {Feature_HasDBBit, Feature_IsARMBit, },
346
  {Feature_HasDBBit, Feature_IsThumbBit, },
347
  {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
348
  {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
349
  {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
350
  {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
351
  {Feature_HasDSPBit, Feature_IsThumb2Bit, },
352
  {Feature_HasDivideInARMBit, Feature_IsARMBit, },
353
  {Feature_HasFP16Bit, Feature_HasNEONBit, },
354
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
355
  {Feature_HasNEONBit, Feature_HasV8Bit, },
356
  {Feature_HasNEONBit, Feature_HasV8_1aBit, },
357
  {Feature_HasV5TBit, Feature_IsARMBit, },
358
  {Feature_HasV5TEBit, Feature_IsARMBit, },
359
  {Feature_HasV6Bit, Feature_IsARMBit, },
360
  {Feature_HasV6KBit, Feature_IsARMBit, },
361
  {Feature_HasV6MBit, Feature_IsThumbBit, },
362
  {Feature_HasV6T2Bit, Feature_IsARMBit, },
363
  {Feature_HasV6T2Bit, Feature_IsThumb2Bit, },
364
  {Feature_HasV7Bit, Feature_IsARMBit, },
365
  {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
366
  {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
367
  {Feature_HasVFP2Bit, Feature_UseVMOVSRBit, },
368
  {Feature_IsARMBit, Feature_NoV6Bit, },
369
  {Feature_IsARMBit, Feature_PreV8Bit, },
370
  {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
371
  {Feature_IsThumbBit, Feature_IsWindowsBit, },
372
  {Feature_IsThumbBit, Feature_UseMovtBit, },
373
  {Feature_IsThumb2Bit, Feature_PreV8Bit, },
374
  {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
375
  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsARMBit, },
376
  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsThumb2Bit, },
377
  {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
378
  {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
379
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
380
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
381
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
382
  {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
383
  {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
384
  {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
385
  {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
386
  {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
387
};
388
389
// ComplexPattern predicates.
390
enum {
391
  GICP_Invalid,
392
};
393
// See constructor for table contents
394
395
// PatFrag predicates.
396
enum {
397
  GIPFP_I64_Predicate_VectorIndex16 = GIPFP_I64_Invalid + 1,
398
  GIPFP_I64_Predicate_VectorIndex32,
399
  GIPFP_I64_Predicate_VectorIndex64,
400
  GIPFP_I64_Predicate_VectorIndex8,
401
  GIPFP_I64_Predicate_imm0_15,
402
  GIPFP_I64_Predicate_imm0_239,
403
  GIPFP_I64_Predicate_imm0_255,
404
  GIPFP_I64_Predicate_imm0_31,
405
  GIPFP_I64_Predicate_imm0_32,
406
  GIPFP_I64_Predicate_imm0_4095,
407
  GIPFP_I64_Predicate_imm0_63,
408
  GIPFP_I64_Predicate_imm0_65535,
409
  GIPFP_I64_Predicate_imm0_65535_neg,
410
  GIPFP_I64_Predicate_imm0_7,
411
  GIPFP_I64_Predicate_imm16,
412
  GIPFP_I64_Predicate_imm16_31,
413
  GIPFP_I64_Predicate_imm1_15,
414
  GIPFP_I64_Predicate_imm1_16,
415
  GIPFP_I64_Predicate_imm1_31,
416
  GIPFP_I64_Predicate_imm1_7,
417
  GIPFP_I64_Predicate_imm24b,
418
  GIPFP_I64_Predicate_imm256_510,
419
  GIPFP_I64_Predicate_imm32,
420
  GIPFP_I64_Predicate_imm8,
421
  GIPFP_I64_Predicate_imm8_255,
422
  GIPFP_I64_Predicate_imm8_or_16,
423
  GIPFP_I64_Predicate_mod_imm,
424
  GIPFP_I64_Predicate_pkh_asr_amt,
425
  GIPFP_I64_Predicate_pkh_lsl_amt,
426
  GIPFP_I64_Predicate_shr_imm16,
427
  GIPFP_I64_Predicate_shr_imm32,
428
  GIPFP_I64_Predicate_shr_imm64,
429
  GIPFP_I64_Predicate_shr_imm8,
430
  GIPFP_I64_Predicate_t2_so_imm,
431
  GIPFP_I64_Predicate_t2_so_imm_neg,
432
};
433
73
bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
434
73
  switch (PredicateID) {
435
73
  case GIPFP_I64_Predicate_VectorIndex16: {
436
0
    
437
0
  return ((uint64_t)Imm) < 4;
438
73
439
73
    
llvm_unreachable0
("ImmediateCode should have returned");
440
73
    
return false0
;
441
73
  }
442
73
  case GIPFP_I64_Predicate_VectorIndex32: {
443
0
    
444
0
  return ((uint64_t)Imm) < 2;
445
73
446
73
    
llvm_unreachable0
("ImmediateCode should have returned");
447
73
    
return false0
;
448
73
  }
449
73
  case GIPFP_I64_Predicate_VectorIndex64: {
450
0
    
451
0
  return ((uint64_t)Imm) < 1;
452
73
453
73
    
llvm_unreachable0
("ImmediateCode should have returned");
454
73
    
return false0
;
455
73
  }
456
73
  case GIPFP_I64_Predicate_VectorIndex8: {
457
0
    
458
0
  return ((uint64_t)Imm) < 8;
459
73
460
73
    
llvm_unreachable0
("ImmediateCode should have returned");
461
73
    
return false0
;
462
73
  }
463
73
  case GIPFP_I64_Predicate_imm0_15: {
464
0
    
465
0
  return Imm >= 0 && Imm < 16;
466
73
467
73
    
llvm_unreachable0
("ImmediateCode should have returned");
468
73
    
return false0
;
469
73
  }
470
73
  case GIPFP_I64_Predicate_imm0_239: {
471
0
     return Imm >= 0 && Imm < 240; 
472
73
    
llvm_unreachable0
("ImmediateCode should have returned");
473
73
    
return false0
;
474
73
  }
475
73
  case GIPFP_I64_Predicate_imm0_255: {
476
0
     return Imm >= 0 && Imm < 256; 
477
73
    
llvm_unreachable0
("ImmediateCode should have returned");
478
73
    
return false0
;
479
73
  }
480
73
  case GIPFP_I64_Predicate_imm0_31: {
481
0
    
482
0
  return Imm >= 0 && Imm < 32;
483
73
484
73
    
llvm_unreachable0
("ImmediateCode should have returned");
485
73
    
return false0
;
486
73
  }
487
73
  case GIPFP_I64_Predicate_imm0_32: {
488
0
    
489
0
  return Imm >= 0 && Imm < 33;
490
73
491
73
    
llvm_unreachable0
("ImmediateCode should have returned");
492
73
    
return false0
;
493
73
  }
494
73
  case GIPFP_I64_Predicate_imm0_4095: {
495
0
    
496
0
  return Imm >= 0 && Imm < 4096;
497
73
498
73
    
llvm_unreachable0
("ImmediateCode should have returned");
499
73
    
return false0
;
500
73
  }
501
73
  case GIPFP_I64_Predicate_imm0_63: {
502
0
    
503
0
  return Imm >= 0 && Imm < 64;
504
73
505
73
    
llvm_unreachable0
("ImmediateCode should have returned");
506
73
    
return false0
;
507
73
  }
508
73
  case GIPFP_I64_Predicate_imm0_65535: {
509
1
    
510
1
  return Imm >= 0 && Imm < 65536;
511
73
512
73
    
llvm_unreachable0
("ImmediateCode should have returned");
513
73
    
return false0
;
514
73
  }
515
73
  case GIPFP_I64_Predicate_imm0_65535_neg: {
516
0
    
517
0
  return -Imm >= 0 && -Imm < 65536;
518
73
519
73
    
llvm_unreachable0
("ImmediateCode should have returned");
520
73
    
return false0
;
521
73
  }
522
73
  case GIPFP_I64_Predicate_imm0_7: {
523
0
    
524
0
  return Imm >= 0 && Imm < 8;
525
73
526
73
    
llvm_unreachable0
("ImmediateCode should have returned");
527
73
    
return false0
;
528
73
  }
529
73
  case GIPFP_I64_Predicate_imm16: {
530
1
     return Imm == 16; 
531
73
    
llvm_unreachable0
("ImmediateCode should have returned");
532
73
    
return false0
;
533
73
  }
534
73
  case GIPFP_I64_Predicate_imm16_31: {
535
2
    
536
2
  return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
537
73
538
73
    
llvm_unreachable0
("ImmediateCode should have returned");
539
73
    
return false0
;
540
73
  }
541
73
  case GIPFP_I64_Predicate_imm1_15: {
542
1
     return Imm > 0 && Imm < 16; 
543
73
    
llvm_unreachable0
("ImmediateCode should have returned");
544
73
    
return false0
;
545
73
  }
546
73
  case GIPFP_I64_Predicate_imm1_16: {
547
0
    
548
0
    return Imm > 0 && Imm <= 16;
549
73
  
550
73
    
llvm_unreachable0
("ImmediateCode should have returned");
551
73
    
return false0
;
552
73
  }
553
73
  case GIPFP_I64_Predicate_imm1_31: {
554
0
     return Imm > 0 && Imm < 32; 
555
73
    
llvm_unreachable0
("ImmediateCode should have returned");
556
73
    
return false0
;
557
73
  }
558
73
  case GIPFP_I64_Predicate_imm1_7: {
559
0
     return Imm > 0 && Imm < 8; 
560
73
    
llvm_unreachable0
("ImmediateCode should have returned");
561
73
    
return false0
;
562
73
  }
563
73
  case GIPFP_I64_Predicate_imm24b: {
564
0
    
565
0
  return Imm >= 0 && Imm <= 0xffffff;
566
73
567
73
    
llvm_unreachable0
("ImmediateCode should have returned");
568
73
    
return false0
;
569
73
  }
570
73
  case GIPFP_I64_Predicate_imm256_510: {
571
0
    
572
0
  return Imm >= 256 && Imm < 511;
573
73
574
73
    
llvm_unreachable0
("ImmediateCode should have returned");
575
73
    
return false0
;
576
73
  }
577
73
  case GIPFP_I64_Predicate_imm32: {
578
0
     return Imm == 32; 
579
73
    
llvm_unreachable0
("ImmediateCode should have returned");
580
73
    
return false0
;
581
73
  }
582
73
  case GIPFP_I64_Predicate_imm8: {
583
0
     return Imm == 8; 
584
73
    
llvm_unreachable0
("ImmediateCode should have returned");
585
73
    
return false0
;
586
73
  }
587
73
  case GIPFP_I64_Predicate_imm8_255: {
588
0
    
589
0
  return Imm >= 8 && Imm < 256;
590
73
591
73
    
llvm_unreachable0
("ImmediateCode should have returned");
592
73
    
return false0
;
593
73
  }
594
73
  case GIPFP_I64_Predicate_imm8_or_16: {
595
0
     return Imm == 8 || Imm == 16;
596
73
    
llvm_unreachable0
("ImmediateCode should have returned");
597
73
    
return false0
;
598
73
  }
599
73
  case GIPFP_I64_Predicate_mod_imm: {
600
65
    
601
65
    return ARM_AM::getSOImmVal(Imm) != -1;
602
73
  
603
73
    
llvm_unreachable0
("ImmediateCode should have returned");
604
73
    
return false0
;
605
73
  }
606
73
  case GIPFP_I64_Predicate_pkh_asr_amt: {
607
0
     return Imm > 0 && Imm <= 32; 
608
73
    
llvm_unreachable0
("ImmediateCode should have returned");
609
73
    
return false0
;
610
73
  }
611
73
  case GIPFP_I64_Predicate_pkh_lsl_amt: {
612
3
     return Imm >= 0 && Imm < 32; 
613
73
    
llvm_unreachable0
("ImmediateCode should have returned");
614
73
    
return false0
;
615
73
  }
616
73
  case GIPFP_I64_Predicate_shr_imm16: {
617
0
     return Imm > 0 && Imm <= 16; 
618
73
    
llvm_unreachable0
("ImmediateCode should have returned");
619
73
    
return false0
;
620
73
  }
621
73
  case GIPFP_I64_Predicate_shr_imm32: {
622
0
     return Imm > 0 && Imm <= 32; 
623
73
    
llvm_unreachable0
("ImmediateCode should have returned");
624
73
    
return false0
;
625
73
  }
626
73
  case GIPFP_I64_Predicate_shr_imm64: {
627
0
     return Imm > 0 && Imm <= 64; 
628
73
    
llvm_unreachable0
("ImmediateCode should have returned");
629
73
    
return false0
;
630
73
  }
631
73
  case GIPFP_I64_Predicate_shr_imm8: {
632
0
     return Imm > 0 && Imm <= 8; 
633
73
    
llvm_unreachable0
("ImmediateCode should have returned");
634
73
    
return false0
;
635
73
  }
636
73
  case GIPFP_I64_Predicate_t2_so_imm: {
637
0
    
638
0
    return ARM_AM::getT2SOImmVal(Imm) != -1;
639
73
  
640
73
    
llvm_unreachable0
("ImmediateCode should have returned");
641
73
    
return false0
;
642
73
  }
643
73
  case GIPFP_I64_Predicate_t2_so_imm_neg: {
644
0
    
645
0
  return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
646
73
647
73
    
llvm_unreachable0
("ImmediateCode should have returned");
648
73
    
return false0
;
649
0
  }
650
0
  }
651
0
  llvm_unreachable("Unknown predicate");
652
0
  return false;
653
0
}
654
0
bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
655
0
  llvm_unreachable("Unknown predicate");
656
0
  return false;
657
0
}
658
0
bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
659
0
  llvm_unreachable("Unknown predicate");
660
0
  return false;
661
0
}
662
// PatFrag predicates.
663
enum {
664
  GIPFP_MI_Predicate_bf_inv_mask_imm = GIPFP_MI_Invalid + 1,
665
};
666
1
bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
667
1
  const MachineFunction &MF = *MI.getParent()->getParent();
668
1
  const MachineRegisterInfo &MRI = MF.getRegInfo();
669
1
  (void)MRI;
670
1
  switch (PredicateID) {
671
1
  case GIPFP_MI_Predicate_bf_inv_mask_imm: {
672
1
    
673
1
    // There's better methods of implementing this check. IntImmLeaf<> would be
674
1
    // equivalent and have less boilerplate but we need a test for C++
675
1
    // predicates and this one causes new rules to be imported into GlobalISel
676
1
    // without requiring additional features first.
677
1
    const auto &MO = MI.getOperand(1);
678
1
    if (!MO.isCImm())
679
0
      return false;
680
1
    return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
681
1
  
682
1
    
llvm_unreachable0
("GISelPredicateCode should have returned");
683
1
    
return false0
;
684
0
  }
685
0
  }
686
0
  llvm_unreachable("Unknown predicate");
687
0
  return false;
688
0
}
689
690
ARMInstructionSelector::ComplexMatcherMemFn
691
ARMInstructionSelector::ComplexPredicateFns[] = {
692
  nullptr, // GICP_Invalid
693
};
694
695
// Custom renderers.
696
enum {
697
  GICR_Invalid,
698
};
699
ARMInstructionSelector::CustomRendererFn
700
ARMInstructionSelector::CustomRenderers[] = {
701
  nullptr, // GICP_Invalid
702
};
703
704
736
bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
705
736
  MachineFunction &MF = *I.getParent()->getParent();
706
736
  MachineRegisterInfo &MRI = MF.getRegInfo();
707
736
  // FIXME: This should be computed on a per-function basis rather than per-insn.
708
736
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
709
736
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
710
736
  NewMIVector OutMIs;
711
736
  State.MIs.clear();
712
736
  State.MIs.push_back(&I);
713
736
714
736
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
715
239
    return true;
716
239
  }
717
497
718
497
  return false;
719
497
}
720
721
736
const int64_t *ARMInstructionSelector::getMatchTable() const {
722
736
  constexpr static int64_t MatchTable0[] = {
723
736
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 139, /*)*//*default:*//*Label 35*/ 61592,
724
736
    /*TargetOpcode::G_ADD*//*Label 0*/ 110,
725
736
    /*TargetOpcode::G_SUB*//*Label 1*/ 6661,
726
736
    /*TargetOpcode::G_MUL*//*Label 2*/ 8651,
727
736
    /*TargetOpcode::G_SDIV*//*Label 3*/ 9285,
728
736
    /*TargetOpcode::G_UDIV*//*Label 4*/ 9385, 0, 0,
729
736
    /*TargetOpcode::G_AND*//*Label 5*/ 9485,
730
736
    /*TargetOpcode::G_OR*//*Label 6*/ 11198,
731
736
    /*TargetOpcode::G_XOR*//*Label 7*/ 15381, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
732
736
    /*TargetOpcode::G_BITCAST*//*Label 8*/ 15880, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
733
736
    /*TargetOpcode::G_INTRINSIC*//*Label 9*/ 20268,
734
736
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 10*/ 49639,
735
736
    /*TargetOpcode::G_ANYEXT*//*Label 11*/ 53968,
736
736
    /*TargetOpcode::G_TRUNC*//*Label 12*/ 54091,
737
736
    /*TargetOpcode::G_CONSTANT*//*Label 13*/ 54220, 0, 0, 0,
738
736
    /*TargetOpcode::G_SEXT*//*Label 14*/ 54385,
739
736
    /*TargetOpcode::G_ZEXT*//*Label 15*/ 54514,
740
736
    /*TargetOpcode::G_SHL*//*Label 16*/ 55024,
741
736
    /*TargetOpcode::G_LSHR*//*Label 17*/ 55129,
742
736
    /*TargetOpcode::G_ASHR*//*Label 18*/ 55187, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
743
736
    /*TargetOpcode::G_FADD*//*Label 19*/ 55400,
744
736
    /*TargetOpcode::G_FSUB*//*Label 20*/ 56031,
745
736
    /*TargetOpcode::G_FMUL*//*Label 21*/ 56646,
746
736
    /*TargetOpcode::G_FMA*//*Label 22*/ 57229,
747
736
    /*TargetOpcode::G_FDIV*//*Label 23*/ 58250, 0, 0, 0, 0, 0, 0, 0,
748
736
    /*TargetOpcode::G_FNEG*//*Label 24*/ 58413,
749
736
    /*TargetOpcode::G_FPEXT*//*Label 25*/ 59330,
750
736
    /*TargetOpcode::G_FPTRUNC*//*Label 26*/ 59487,
751
736
    /*TargetOpcode::G_FPTOSI*//*Label 27*/ 59648,
752
736
    /*TargetOpcode::G_FPTOUI*//*Label 28*/ 59988,
753
736
    /*TargetOpcode::G_SITOFP*//*Label 29*/ 60328,
754
736
    /*TargetOpcode::G_UITOFP*//*Label 30*/ 60665, 0, 0, 0,
755
736
    /*TargetOpcode::G_BR*//*Label 31*/ 61002, 0, 0, 0, 0, 0,
756
736
    /*TargetOpcode::G_CTLZ*//*Label 32*/ 61064, 0,
757
736
    /*TargetOpcode::G_CTPOP*//*Label 33*/ 61390,
758
736
    /*TargetOpcode::G_BSWAP*//*Label 34*/ 61478,
759
736
    // Label 0: @110
760
736
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 45*/ 6660,
761
736
    /*GILLT_s32*//*Label 36*/ 125,
762
736
    /*GILLT_s64*//*Label 37*/ 1803,
763
736
    /*GILLT_v2s32*//*Label 38*/ 1854,
764
736
    /*GILLT_v2s64*//*Label 39*/ 2314,
765
736
    /*GILLT_v4s16*//*Label 40*/ 3032,
766
736
    /*GILLT_v4s32*//*Label 41*/ 3492,
767
736
    /*GILLT_v8s8*//*Label 42*/ 4616,
768
736
    /*GILLT_v8s16*//*Label 43*/ 5076,
769
736
    /*GILLT_v16s8*//*Label 44*/ 6200,
770
736
    // Label 36: @125
771
736
    GIM_Try, /*On fail goto*//*Label 46*/ 1802,
772
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
773
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
774
736
      GIM_Try, /*On fail goto*//*Label 47*/ 201, // Rule ID 2774 //
775
736
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
776
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
777
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
778
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
779
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
780
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
781
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
782
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
783
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
784
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
785
736
        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
786
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
787
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
788
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
789
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
790
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
791
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
792
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
793
736
        GIR_EraseFromParent, /*InsnID*/0,
794
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
795
736
        // GIR_Coverage, 2774,
796
736
        GIR_Done,
797
736
      // Label 47: @201
798
736
      GIM_Try, /*On fail goto*//*Label 48*/ 267, // Rule ID 2775 //
799
736
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
800
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
801
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
802
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
803
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
804
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
805
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
806
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
807
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
808
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
809
736
        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
810
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
811
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
812
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
813
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
814
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
815
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
816
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
817
736
        GIR_EraseFromParent, /*InsnID*/0,
818
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
819
736
        // GIR_Coverage, 2775,
820
736
        GIR_Done,
821
736
      // Label 48: @267
822
736
      GIM_Try, /*On fail goto*//*Label 49*/ 333, // Rule ID 2804 //
823
736
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
824
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
825
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
826
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
827
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
828
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
829
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
830
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
831
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
832
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
833
736
        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
834
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
835
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
836
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
837
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
838
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
839
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
840
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
841
736
        GIR_EraseFromParent, /*InsnID*/0,
842
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
843
736
        // GIR_Coverage, 2804,
844
736
        GIR_Done,
845
736
      // Label 49: @333
846
736
      GIM_Try, /*On fail goto*//*Label 50*/ 399, // Rule ID 2805 //
847
736
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
848
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
849
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
850
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
851
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
852
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
853
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
854
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
855
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
856
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
857
736
        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
858
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
859
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
860
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
861
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
862
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
863
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
864
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
865
736
        GIR_EraseFromParent, /*InsnID*/0,
866
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
867
736
        // GIR_Coverage, 2805,
868
736
        GIR_Done,
869
736
      // Label 50: @399
870
736
      GIM_Try, /*On fail goto*//*Label 51*/ 465, // Rule ID 1824 //
871
736
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
872
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
873
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
874
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
875
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
876
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
877
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
878
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
879
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
880
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
881
736
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
882
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
883
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
884
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
885
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
886
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
887
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
888
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
889
736
        GIR_EraseFromParent, /*InsnID*/0,
890
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
891
736
        // GIR_Coverage, 1824,
892
736
        GIR_Done,
893
736
      // Label 51: @465
894
736
      GIM_Try, /*On fail goto*//*Label 52*/ 531, // Rule ID 1825 //
895
736
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
896
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
897
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
898
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
899
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
900
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
901
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
902
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
903
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
904
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
905
736
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
906
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
907
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
908
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
909
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
910
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
911
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
912
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
913
736
        GIR_EraseFromParent, /*InsnID*/0,
914
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
915
736
        // GIR_Coverage, 1825,
916
736
        GIR_Done,
917
736
      // Label 52: @531
918
736
      GIM_Try, /*On fail goto*//*Label 53*/ 597, // Rule ID 2022 //
919
736
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
920
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
921
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
922
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
923
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
924
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
925
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
926
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
927
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
928
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
929
736
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
930
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
931
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
932
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
933
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
934
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
935
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
936
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
937
736
        GIR_EraseFromParent, /*InsnID*/0,
938
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
939
736
        // GIR_Coverage, 2022,
940
736
        GIR_Done,
941
736
      // Label 53: @597
942
736
      GIM_Try, /*On fail goto*//*Label 54*/ 663, // Rule ID 2023 //
943
736
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
944
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
945
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
946
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
947
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
948
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
949
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
950
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
951
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
952
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
953
736
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
954
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
955
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
956
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
957
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
958
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
959
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
960
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
961
736
        GIR_EraseFromParent, /*InsnID*/0,
962
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
963
736
        // GIR_Coverage, 2023,
964
736
        GIR_Done,
965
736
      // Label 54: @663
966
736
      GIM_Try, /*On fail goto*//*Label 55*/ 772, // Rule ID 2559 //
967
736
        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
968
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
969
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
970
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
971
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
972
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
973
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
974
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
975
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
976
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
977
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
978
736
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
979
736
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
980
736
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
981
736
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
982
736
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
983
736
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
984
736
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
985
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
986
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
987
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
988
736
        GIM_CheckIsSafeToFold, /*InsnID*/3,
989
736
        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra)  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
990
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
991
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
992
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
993
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
994
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
995
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
996
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
997
736
        GIR_EraseFromParent, /*InsnID*/0,
998
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
999
736
        // GIR_Coverage, 2559,
1000
736
        GIR_Done,
1001
736
      // Label 55: @772
1002
736
      GIM_Try, /*On fail goto*//*Label 56*/ 881, // Rule ID 2596 //
1003
736
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1004
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1005
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1006
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1007
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1008
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1009
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1010
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1011
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1012
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1013
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1014
736
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1015
736
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1016
736
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1017
736
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1018
736
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1019
736
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1020
736
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1021
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1022
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1023
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1024
736
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1025
736
        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1026
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1027
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1028
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1029
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1030
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1031
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1032
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1033
736
        GIR_EraseFromParent, /*InsnID*/0,
1034
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1035
736
        // GIR_Coverage, 2596,
1036
736
        GIR_Done,
1037
736
      // Label 56: @881
1038
736
      GIM_Try, /*On fail goto*//*Label 57*/ 990, // Rule ID 194 //
1039
736
        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
1040
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1041
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1042
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1043
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1044
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1045
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1046
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1047
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1048
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1049
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1050
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1051
736
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1052
736
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1053
736
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1054
736
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1055
736
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1056
736
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1057
736
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1058
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1059
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1060
736
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1061
736
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1062
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1063
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1064
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1065
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1066
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1067
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1068
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1069
736
        GIR_EraseFromParent, /*InsnID*/0,
1070
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1071
736
        // GIR_Coverage, 194,
1072
736
        GIR_Done,
1073
736
      // Label 57: @990
1074
736
      GIM_Try, /*On fail goto*//*Label 58*/ 1099, // Rule ID 526 //
1075
736
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1076
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1077
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1078
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1079
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1080
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1081
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1082
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1083
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1084
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1085
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1086
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1087
736
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1088
736
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1089
736
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1090
736
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1091
736
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1092
736
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1093
736
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1094
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1095
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1096
736
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1097
736
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1098
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1099
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1100
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1101
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1102
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1103
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1104
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1105
736
        GIR_EraseFromParent, /*InsnID*/0,
1106
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1107
736
        // GIR_Coverage, 526,
1108
736
        GIR_Done,
1109
736
      // Label 58: @1099
1110
736
      GIM_Try, /*On fail goto*//*Label 59*/ 1151, // Rule ID 74 //
1111
736
        GIM_CheckFeatures, GIFBS_IsARM,
1112
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1113
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1114
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1115
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1116
736
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
1117
736
        // MIs[1] Operand 1
1118
736
        // No operand predicates
1119
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1120
736
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1121
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDri,
1122
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1123
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1124
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1125
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1126
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1127
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1128
736
        GIR_EraseFromParent, /*InsnID*/0,
1129
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1130
736
        // GIR_Coverage, 74,
1131
736
        GIR_Done,
1132
736
      // Label 59: @1151
1133
736
      GIM_Try, /*On fail goto*//*Label 60*/ 1203, // Rule ID 412 //
1134
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
1135
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1136
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1137
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1138
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1139
736
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
1140
736
        // MIs[1] Operand 1
1141
736
        // No operand predicates
1142
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1143
736
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1144
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri,
1145
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1146
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1147
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1148
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1149
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1150
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1151
736
        GIR_EraseFromParent, /*InsnID*/0,
1152
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1153
736
        // GIR_Coverage, 412,
1154
736
        GIR_Done,
1155
736
      // Label 60: @1203
1156
736
      GIM_Try, /*On fail goto*//*Label 61*/ 1252, // Rule ID 413 //
1157
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
1158
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1159
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1160
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1161
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1162
736
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
1163
736
        // MIs[1] Operand 1
1164
736
        // No operand predicates
1165
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1166
736
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1167
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri12,
1168
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1169
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1170
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1171
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1172
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1173
736
        GIR_EraseFromParent, /*InsnID*/0,
1174
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1175
736
        // GIR_Coverage, 413,
1176
736
        GIR_Done,
1177
736
      // Label 61: @1252
1178
736
      GIM_Try, /*On fail goto*//*Label 62*/ 1322, // Rule ID 173 //
1179
736
        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1180
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1181
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1182
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1183
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1184
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1185
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1186
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1187
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1188
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1189
736
        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1190
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1191
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1192
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1193
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1194
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1195
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1196
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1197
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1198
736
        GIR_EraseFromParent, /*InsnID*/0,
1199
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1200
736
        // GIR_Coverage, 173,
1201
736
        GIR_Done,
1202
736
      // Label 62: @1322
1203
736
      GIM_Try, /*On fail goto*//*Label 63*/ 1392, // Rule ID 174 //
1204
736
        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1205
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1206
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1207
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1208
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1209
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1210
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1211
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1212
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1213
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1214
736
        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1215
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1216
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1217
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1218
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1219
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1220
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1221
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1222
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1223
736
        GIR_EraseFromParent, /*InsnID*/0,
1224
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1225
736
        // GIR_Coverage, 174,
1226
736
        GIR_Done,
1227
736
      // Label 63: @1392
1228
736
      GIM_Try, /*On fail goto*//*Label 64*/ 1459, // Rule ID 508 //
1229
736
        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1230
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1231
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1232
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1233
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1234
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1235
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1236
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1237
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1238
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1239
736
        // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra)  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1240
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1241
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1242
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1243
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1244
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1245
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1246
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1247
736
        GIR_EraseFromParent, /*InsnID*/0,
1248
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1249
736
        // GIR_Coverage, 508,
1250
736
        GIR_Done,
1251
736
      // Label 64: @1459
1252
736
      GIM_Try, /*On fail goto*//*Label 65*/ 1529, // Rule ID 2553 //
1253
736
        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1254
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1255
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1256
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1257
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1258
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1259
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1260
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1261
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1262
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1263
736
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1264
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1265
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1266
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1267
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1268
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1269
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1270
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1271
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1272
736
        GIR_EraseFromParent, /*InsnID*/0,
1273
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1274
736
        // GIR_Coverage, 2553,
1275
736
        GIR_Done,
1276
736
      // Label 65: @1529
1277
736
      GIM_Try, /*On fail goto*//*Label 66*/ 1599, // Rule ID 2554 //
1278
736
        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1279
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1280
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1281
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1282
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1283
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1284
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1285
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1286
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1287
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1288
736
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1289
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1290
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1291
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1292
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1293
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1294
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1295
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1296
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1297
736
        GIR_EraseFromParent, /*InsnID*/0,
1298
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1299
736
        // GIR_Coverage, 2554,
1300
736
        GIR_Done,
1301
736
      // Label 66: @1599
1302
736
      GIM_Try, /*On fail goto*//*Label 67*/ 1666, // Rule ID 2591 //
1303
736
        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1304
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1305
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1306
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1307
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1308
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1309
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1310
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1311
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1312
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1313
736
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1314
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1315
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1316
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1317
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1318
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1319
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1320
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1321
736
        GIR_EraseFromParent, /*InsnID*/0,
1322
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1323
736
        // GIR_Coverage, 2591,
1324
736
        GIR_Done,
1325
736
      // Label 67: @1666
1326
736
      GIM_Try, /*On fail goto*//*Label 68*/ 1711, // Rule ID 75 //
1327
736
        GIM_CheckFeatures, GIFBS_IsARM,
1328
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1329
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1330
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1331
736
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
1332
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDrr,
1333
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1334
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1335
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1336
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1337
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1338
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1339
736
        GIR_EraseFromParent, /*InsnID*/0,
1340
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1341
736
        // GIR_Coverage, 75,
1342
736
        GIR_Done,
1343
736
      // Label 68: @1711
1344
736
      GIM_Try, /*On fail goto*//*Label 69*/ 1756, // Rule ID 414 //
1345
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
1346
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1347
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1348
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1349
736
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1350
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1351
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1352
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1353
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1354
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1355
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1356
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1357
736
        GIR_EraseFromParent, /*InsnID*/0,
1358
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1359
736
        // GIR_Coverage, 414,
1360
736
        GIR_Done,
1361
736
      // Label 69: @1756
1362
736
      GIM_Try, /*On fail goto*//*Label 70*/ 1801, // Rule ID 2573 //
1363
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
1364
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1365
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1366
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1367
736
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1368
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1369
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1370
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1371
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
1372
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1373
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1374
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1375
736
        GIR_EraseFromParent, /*InsnID*/0,
1376
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1377
736
        // GIR_Coverage, 2573,
1378
736
        GIR_Done,
1379
736
      // Label 70: @1801
1380
736
      GIM_Reject,
1381
736
    // Label 46: @1802
1382
736
    GIM_Reject,
1383
736
    // Label 37: @1803
1384
736
    GIM_Try, /*On fail goto*//*Label 71*/ 1853, // Rule ID 761 //
1385
736
      GIM_CheckFeatures, GIFBS_HasNEON,
1386
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1387
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1388
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1389
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1390
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1391
736
      // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1392
736
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv1i64,
1393
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1394
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1395
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1396
736
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1397
736
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1398
736
      GIR_EraseFromParent, /*InsnID*/0,
1399
736
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1400
736
      // GIR_Coverage, 761,
1401
736
      GIR_Done,
1402
736
    // Label 71: @1853
1403
736
    GIM_Reject,
1404
736
    // Label 38: @1854
1405
736
    GIM_Try, /*On fail goto*//*Label 72*/ 2313,
1406
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1407
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1408
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1409
736
      GIM_Try, /*On fail goto*//*Label 73*/ 1938, // Rule ID 2711 //
1410
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1411
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1412
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1413
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1414
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1415
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1416
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1417
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1418
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1419
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1420
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1421
736
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1100:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1422
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1423
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1424
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1425
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1426
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1427
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1428
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1429
736
        GIR_EraseFromParent, /*InsnID*/0,
1430
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1431
736
        // GIR_Coverage, 2711,
1432
736
        GIR_Done,
1433
736
      // Label 73: @1938
1434
736
      GIM_Try, /*On fail goto*//*Label 74*/ 2008, // Rule ID 2717 //
1435
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1436
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1437
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1438
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1439
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1440
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1441
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1442
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1443
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1444
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1445
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1446
736
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1101:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1447
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1448
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1449
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1450
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1451
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1452
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1453
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1454
736
        GIR_EraseFromParent, /*InsnID*/0,
1455
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1456
736
        // GIR_Coverage, 2717,
1457
736
        GIR_Done,
1458
736
      // Label 74: @2008
1459
736
      GIM_Try, /*On fail goto*//*Label 75*/ 2078, // Rule ID 1153 //
1460
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1461
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1462
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1463
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1464
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1465
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1466
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1467
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1468
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1469
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1470
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1471
736
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1100:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1472
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1473
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1474
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1475
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1476
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1477
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1478
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1479
736
        GIR_EraseFromParent, /*InsnID*/0,
1480
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1481
736
        // GIR_Coverage, 1153,
1482
736
        GIR_Done,
1483
736
      // Label 75: @2078
1484
736
      GIM_Try, /*On fail goto*//*Label 76*/ 2148, // Rule ID 1159 //
1485
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1486
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1487
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1488
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1489
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1490
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1491
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1492
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1493
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1494
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1495
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1496
736
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1101:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1497
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1498
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1499
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1500
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1501
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1502
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1503
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1504
736
        GIR_EraseFromParent, /*InsnID*/0,
1505
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1506
736
        // GIR_Coverage, 1159,
1507
736
        GIR_Done,
1508
736
      // Label 76: @2148
1509
736
      GIM_Try, /*On fail goto*//*Label 77*/ 2211, // Rule ID 2641 //
1510
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1511
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1512
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1513
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1514
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1515
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1516
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1517
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1518
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1519
736
        // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1520
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1521
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1522
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1523
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1524
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1525
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1526
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1527
736
        GIR_EraseFromParent, /*InsnID*/0,
1528
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1529
736
        // GIR_Coverage, 2641,
1530
736
        GIR_Done,
1531
736
      // Label 77: @2211
1532
736
      GIM_Try, /*On fail goto*//*Label 78*/ 2274, // Rule ID 876 //
1533
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1534
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1535
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1536
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1537
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1538
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1539
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1540
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1541
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1542
736
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1543
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1544
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1545
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1546
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1547
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1548
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1549
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1550
736
        GIR_EraseFromParent, /*InsnID*/0,
1551
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1552
736
        // GIR_Coverage, 876,
1553
736
        GIR_Done,
1554
736
      // Label 78: @2274
1555
736
      GIM_Try, /*On fail goto*//*Label 79*/ 2312, // Rule ID 757 //
1556
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1557
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1558
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1559
736
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1560
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i32,
1561
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1562
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1563
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1564
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1565
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1566
736
        GIR_EraseFromParent, /*InsnID*/0,
1567
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1568
736
        // GIR_Coverage, 757,
1569
736
        GIR_Done,
1570
736
      // Label 79: @2312
1571
736
      GIM_Reject,
1572
736
    // Label 72: @2313
1573
736
    GIM_Reject,
1574
736
    // Label 39: @2314
1575
736
    GIM_Try, /*On fail goto*//*Label 80*/ 3031,
1576
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1577
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1578
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
1579
736
      GIM_Try, /*On fail goto*//*Label 81*/ 2411, // Rule ID 2723 //
1580
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1581
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1582
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1583
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1584
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1585
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1586
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1587
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1588
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1589
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1590
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1591
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1592
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1593
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1594
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1595
736
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1100:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1596
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1597
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1598
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1599
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1600
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1601
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1602
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1603
736
        GIR_EraseFromParent, /*InsnID*/0,
1604
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1605
736
        // GIR_Coverage, 2723,
1606
736
        GIR_Done,
1607
736
      // Label 81: @2411
1608
736
      GIM_Try, /*On fail goto*//*Label 82*/ 2494, // Rule ID 2726 //
1609
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1610
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1611
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1612
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1613
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1614
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1615
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1616
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1617
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1618
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1619
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1620
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1621
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1622
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1623
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1624
736
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1101:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1625
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1626
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1627
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1628
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1629
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1630
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1631
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1632
736
        GIR_EraseFromParent, /*InsnID*/0,
1633
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1634
736
        // GIR_Coverage, 2726,
1635
736
        GIR_Done,
1636
736
      // Label 82: @2494
1637
736
      GIM_Try, /*On fail goto*//*Label 83*/ 2577, // Rule ID 1165 //
1638
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1639
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1640
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1641
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1642
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1643
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1644
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1645
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1646
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1647
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1648
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1649
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1650
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1651
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1652
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1653
736
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1100:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1654
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1655
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1656
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1657
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1658
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1659
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1660
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1661
736
        GIR_EraseFromParent, /*InsnID*/0,
1662
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1663
736
        // GIR_Coverage, 1165,
1664
736
        GIR_Done,
1665
736
      // Label 83: @2577
1666
736
      GIM_Try, /*On fail goto*//*Label 84*/ 2660, // Rule ID 1168 //
1667
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1668
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1669
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1670
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1671
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1672
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1673
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1674
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1675
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1676
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1677
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1678
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1679
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1680
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1681
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1682
736
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1101:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1683
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1684
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1685
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1686
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1687
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1688
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1689
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1690
736
        GIR_EraseFromParent, /*InsnID*/0,
1691
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1692
736
        // GIR_Coverage, 1168,
1693
736
        GIR_Done,
1694
736
      // Label 84: @2660
1695
736
      GIM_Try, /*On fail goto*//*Label 85*/ 2724, // Rule ID 769 //
1696
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1697
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1698
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1699
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1700
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1701
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1702
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1703
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1704
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1705
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1706
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1707
736
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1708
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv2i64,
1709
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1710
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1711
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
1712
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1713
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1714
736
        GIR_EraseFromParent, /*InsnID*/0,
1715
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1716
736
        // GIR_Coverage, 769,
1717
736
        GIR_Done,
1718
736
      // Label 85: @2724
1719
736
      GIM_Try, /*On fail goto*//*Label 86*/ 2788, // Rule ID 772 //
1720
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1721
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1722
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1723
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1724
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1725
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1726
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1727
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1728
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1729
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1730
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1731
736
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1732
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
1733
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1734
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1735
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
1736
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1737
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1738
736
        GIR_EraseFromParent, /*InsnID*/0,
1739
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1740
736
        // GIR_Coverage, 772,
1741
736
        GIR_Done,
1742
736
      // Label 86: @2788
1743
736
      GIM_Try, /*On fail goto*//*Label 87*/ 2839, // Rule ID 2617 //
1744
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1745
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1746
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1747
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1748
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1749
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1750
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1751
736
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1752
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
1753
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1754
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
1755
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1756
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1757
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1758
736
        GIR_EraseFromParent, /*InsnID*/0,
1759
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1760
736
        // GIR_Coverage, 2617,
1761
736
        GIR_Done,
1762
736
      // Label 87: @2839
1763
736
      GIM_Try, /*On fail goto*//*Label 88*/ 2890, // Rule ID 2620 //
1764
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1765
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1766
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1767
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1768
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1769
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1770
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1771
736
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1772
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
1773
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1774
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
1775
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1776
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1777
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1778
736
        GIR_EraseFromParent, /*InsnID*/0,
1779
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1780
736
        // GIR_Coverage, 2620,
1781
736
        GIR_Done,
1782
736
      // Label 88: @2890
1783
736
      GIM_Try, /*On fail goto*//*Label 89*/ 2941, // Rule ID 775 //
1784
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1785
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1786
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1787
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1788
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1789
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1790
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1791
736
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1792
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
1793
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1794
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1795
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1796
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1797
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1798
736
        GIR_EraseFromParent, /*InsnID*/0,
1799
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1800
736
        // GIR_Coverage, 775,
1801
736
        GIR_Done,
1802
736
      // Label 89: @2941
1803
736
      GIM_Try, /*On fail goto*//*Label 90*/ 2992, // Rule ID 778 //
1804
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1805
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1806
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1807
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1808
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1809
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1810
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1811
736
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1812
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
1813
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1814
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1815
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1816
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1817
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1818
736
        GIR_EraseFromParent, /*InsnID*/0,
1819
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1820
736
        // GIR_Coverage, 778,
1821
736
        GIR_Done,
1822
736
      // Label 90: @2992
1823
736
      GIM_Try, /*On fail goto*//*Label 91*/ 3030, // Rule ID 762 //
1824
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1825
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1826
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1827
736
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
1828
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i64,
1829
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1830
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1831
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1832
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1833
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1834
736
        GIR_EraseFromParent, /*InsnID*/0,
1835
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1836
736
        // GIR_Coverage, 762,
1837
736
        GIR_Done,
1838
736
      // Label 91: @3030
1839
736
      GIM_Reject,
1840
736
    // Label 80: @3031
1841
736
    GIM_Reject,
1842
736
    // Label 40: @3032
1843
736
    GIM_Try, /*On fail goto*//*Label 92*/ 3491,
1844
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1845
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
1846
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1847
736
      GIM_Try, /*On fail goto*//*Label 93*/ 3116, // Rule ID 2710 //
1848
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1849
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1850
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1851
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1852
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1853
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1854
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1855
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1856
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1857
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1858
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1859
736
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1100:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1860
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
1861
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1862
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1863
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1864
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1865
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1866
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1867
736
        GIR_EraseFromParent, /*InsnID*/0,
1868
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1869
736
        // GIR_Coverage, 2710,
1870
736
        GIR_Done,
1871
736
      // Label 93: @3116
1872
736
      GIM_Try, /*On fail goto*//*Label 94*/ 3186, // Rule ID 2716 //
1873
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1874
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1875
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1876
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1877
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1878
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1879
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1880
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1881
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1882
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1883
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1884
736
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1101:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1885
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
1886
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1887
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1888
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1889
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1890
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1891
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1892
736
        GIR_EraseFromParent, /*InsnID*/0,
1893
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1894
736
        // GIR_Coverage, 2716,
1895
736
        GIR_Done,
1896
736
      // Label 94: @3186
1897
736
      GIM_Try, /*On fail goto*//*Label 95*/ 3256, // Rule ID 1152 //
1898
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1899
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1900
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1901
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1902
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1903
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1904
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1905
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1906
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1907
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1908
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1909
736
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1100:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1910
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
1911
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1912
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1913
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1914
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1915
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1916
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1917
736
        GIR_EraseFromParent, /*InsnID*/0,
1918
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1919
736
        // GIR_Coverage, 1152,
1920
736
        GIR_Done,
1921
736
      // Label 95: @3256
1922
736
      GIM_Try, /*On fail goto*//*Label 96*/ 3326, // Rule ID 1158 //
1923
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1924
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1925
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1926
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1927
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1928
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1929
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1930
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1931
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1932
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1933
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1934
736
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1101:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1935
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
1936
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1937
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1938
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1939
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1940
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1941
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1942
736
        GIR_EraseFromParent, /*InsnID*/0,
1943
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1944
736
        // GIR_Coverage, 1158,
1945
736
        GIR_Done,
1946
736
      // Label 96: @3326
1947
736
      GIM_Try, /*On fail goto*//*Label 97*/ 3389, // Rule ID 2640 //
1948
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1949
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1950
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1951
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
1952
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1953
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1954
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1955
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1956
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1957
736
        // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1958
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
1959
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1960
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1961
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1962
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1963
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1964
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1965
736
        GIR_EraseFromParent, /*InsnID*/0,
1966
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1967
736
        // GIR_Coverage, 2640,
1968
736
        GIR_Done,
1969
736
      // Label 97: @3389
1970
736
      GIM_Try, /*On fail goto*//*Label 98*/ 3452, // Rule ID 875 //
1971
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1972
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1973
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1974
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1975
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
1976
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1977
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1978
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1979
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1980
736
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1981
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
1982
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1983
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1984
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1985
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1986
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1987
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1988
736
        GIR_EraseFromParent, /*InsnID*/0,
1989
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1990
736
        // GIR_Coverage, 875,
1991
736
        GIR_Done,
1992
736
      // Label 98: @3452
1993
736
      GIM_Try, /*On fail goto*//*Label 99*/ 3490, // Rule ID 756 //
1994
736
        GIM_CheckFeatures, GIFBS_HasNEON,
1995
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1996
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1997
736
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1998
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i16,
1999
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2000
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2001
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2002
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2003
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2004
736
        GIR_EraseFromParent, /*InsnID*/0,
2005
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2006
736
        // GIR_Coverage, 756,
2007
736
        GIR_Done,
2008
736
      // Label 99: @3490
2009
736
      GIM_Reject,
2010
736
    // Label 92: @3491
2011
736
    GIM_Reject,
2012
736
    // Label 41: @3492
2013
736
    GIM_Try, /*On fail goto*//*Label 100*/ 4615,
2014
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2015
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2016
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2017
736
      GIM_Try, /*On fail goto*//*Label 101*/ 3589, // Rule ID 2722 //
2018
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2019
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2020
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2021
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2022
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2023
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2024
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2025
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2026
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2027
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2028
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2029
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2030
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2031
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2032
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2033
736
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1100:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2034
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2035
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2036
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2037
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2038
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2039
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2040
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2041
736
        GIR_EraseFromParent, /*InsnID*/0,
2042
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2043
736
        // GIR_Coverage, 2722,
2044
736
        GIR_Done,
2045
736
      // Label 101: @3589
2046
736
      GIM_Try, /*On fail goto*//*Label 102*/ 3672, // Rule ID 2725 //
2047
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2048
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2049
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2050
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2051
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2052
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2053
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2054
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2055
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2056
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2057
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2058
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2059
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2060
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2061
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2062
736
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1101:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2063
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2064
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2065
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2066
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2067
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2068
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2069
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2070
736
        GIR_EraseFromParent, /*InsnID*/0,
2071
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2072
736
        // GIR_Coverage, 2725,
2073
736
        GIR_Done,
2074
736
      // Label 102: @3672
2075
736
      GIM_Try, /*On fail goto*//*Label 103*/ 3755, // Rule ID 1164 //
2076
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2077
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2078
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2079
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2080
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2081
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2082
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2083
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2084
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2085
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2086
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2087
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2088
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2089
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2090
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2091
736
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1100:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2092
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2093
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2094
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2095
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2096
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2097
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2098
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2099
736
        GIR_EraseFromParent, /*InsnID*/0,
2100
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2101
736
        // GIR_Coverage, 1164,
2102
736
        GIR_Done,
2103
736
      // Label 103: @3755
2104
736
      GIM_Try, /*On fail goto*//*Label 104*/ 3838, // Rule ID 1167 //
2105
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2106
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2107
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2108
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2109
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2110
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2111
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2112
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2113
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2114
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2115
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2116
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2117
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2118
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2119
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2120
736
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1101:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2121
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2122
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2123
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2124
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2125
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2126
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2127
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2128
736
        GIR_EraseFromParent, /*InsnID*/0,
2129
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2130
736
        // GIR_Coverage, 1167,
2131
736
        GIR_Done,
2132
736
      // Label 104: @3838
2133
736
      GIM_Try, /*On fail goto*//*Label 105*/ 3908, // Rule ID 2714 //
2134
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2135
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2136
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2137
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2138
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2139
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2140
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2141
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2142
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2143
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2144
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2145
736
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1100:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2146
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2147
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2148
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2149
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2150
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2151
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2152
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2153
736
        GIR_EraseFromParent, /*InsnID*/0,
2154
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2155
736
        // GIR_Coverage, 2714,
2156
736
        GIR_Done,
2157
736
      // Label 105: @3908
2158
736
      GIM_Try, /*On fail goto*//*Label 106*/ 3978, // Rule ID 2720 //
2159
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2160
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2161
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2162
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2163
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2164
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2165
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2166
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2167
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2168
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2169
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2170
736
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1101:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2171
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2172
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2173
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2174
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2175
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2176
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2177
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2178
736
        GIR_EraseFromParent, /*InsnID*/0,
2179
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2180
736
        // GIR_Coverage, 2720,
2181
736
        GIR_Done,
2182
736
      // Label 106: @3978
2183
736
      GIM_Try, /*On fail goto*//*Label 107*/ 4048, // Rule ID 1156 //
2184
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2185
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2186
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2187
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2188
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2189
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2190
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2191
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2192
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2193
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2194
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2195
736
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1100:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2196
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2197
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2198
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2199
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2200
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2201
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2202
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2203
736
        GIR_EraseFromParent, /*InsnID*/0,
2204
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2205
736
        // GIR_Coverage, 1156,
2206
736
        GIR_Done,
2207
736
      // Label 107: @4048
2208
736
      GIM_Try, /*On fail goto*//*Label 108*/ 4118, // Rule ID 1162 //
2209
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2210
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2211
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2212
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2213
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2214
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2215
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2216
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2217
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2218
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2219
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2220
736
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1101:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2221
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2222
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2223
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2224
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2225
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2226
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2227
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2228
736
        GIR_EraseFromParent, /*InsnID*/0,
2229
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2230
736
        // GIR_Coverage, 1162,
2231
736
        GIR_Done,
2232
736
      // Label 108: @4118
2233
736
      GIM_Try, /*On fail goto*//*Label 109*/ 4182, // Rule ID 768 //
2234
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2235
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2236
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2237
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2238
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2239
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2240
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2241
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2242
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2243
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2244
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2245
736
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2246
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv4i32,
2247
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2248
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2249
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2250
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2251
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2252
736
        GIR_EraseFromParent, /*InsnID*/0,
2253
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2254
736
        // GIR_Coverage, 768,
2255
736
        GIR_Done,
2256
736
      // Label 109: @4182
2257
736
      GIM_Try, /*On fail goto*//*Label 110*/ 4246, // Rule ID 771 //
2258
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2259
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2260
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2261
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2262
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2263
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2264
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2265
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2266
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2267
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2268
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2269
736
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2270
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2271
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2272
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2273
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2274
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2275
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2276
736
        GIR_EraseFromParent, /*InsnID*/0,
2277
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2278
736
        // GIR_Coverage, 771,
2279
736
        GIR_Done,
2280
736
      // Label 110: @4246
2281
736
      GIM_Try, /*On fail goto*//*Label 111*/ 4309, // Rule ID 2644 //
2282
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2283
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2284
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2285
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2286
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2287
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2288
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2289
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2290
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2291
736
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2292
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2293
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2294
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2295
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2296
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2297
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2298
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2299
736
        GIR_EraseFromParent, /*InsnID*/0,
2300
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2301
736
        // GIR_Coverage, 2644,
2302
736
        GIR_Done,
2303
736
      // Label 111: @4309
2304
736
      GIM_Try, /*On fail goto*//*Label 112*/ 4360, // Rule ID 2616 //
2305
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2306
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2307
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2308
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2309
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2310
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2311
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2312
736
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2313
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2314
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2315
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2316
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2317
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2318
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2319
736
        GIR_EraseFromParent, /*InsnID*/0,
2320
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2321
736
        // GIR_Coverage, 2616,
2322
736
        GIR_Done,
2323
736
      // Label 112: @4360
2324
736
      GIM_Try, /*On fail goto*//*Label 113*/ 4411, // Rule ID 2619 //
2325
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2326
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2327
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2328
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2329
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2330
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2331
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2332
736
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2333
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2334
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2335
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2336
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2337
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2338
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2339
736
        GIR_EraseFromParent, /*InsnID*/0,
2340
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2341
736
        // GIR_Coverage, 2619,
2342
736
        GIR_Done,
2343
736
      // Label 113: @4411
2344
736
      GIM_Try, /*On fail goto*//*Label 114*/ 4474, // Rule ID 879 //
2345
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2346
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2347
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2348
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2349
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2350
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2351
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2352
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2353
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2354
736
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2355
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2356
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2357
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2358
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2359
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2360
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2361
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2362
736
        GIR_EraseFromParent, /*InsnID*/0,
2363
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2364
736
        // GIR_Coverage, 879,
2365
736
        GIR_Done,
2366
736
      // Label 114: @4474
2367
736
      GIM_Try, /*On fail goto*//*Label 115*/ 4525, // Rule ID 774 //
2368
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2369
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2370
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2371
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2372
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2373
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2374
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2375
736
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2376
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2377
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2378
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2379
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2380
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2381
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2382
736
        GIR_EraseFromParent, /*InsnID*/0,
2383
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2384
736
        // GIR_Coverage, 774,
2385
736
        GIR_Done,
2386
736
      // Label 115: @4525
2387
736
      GIM_Try, /*On fail goto*//*Label 116*/ 4576, // Rule ID 777 //
2388
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2389
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2390
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2391
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2392
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2393
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2394
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2395
736
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2396
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2397
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2398
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2399
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2400
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2401
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2402
736
        GIR_EraseFromParent, /*InsnID*/0,
2403
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2404
736
        // GIR_Coverage, 777,
2405
736
        GIR_Done,
2406
736
      // Label 116: @4576
2407
736
      GIM_Try, /*On fail goto*//*Label 117*/ 4614, // Rule ID 760 //
2408
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2409
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2410
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2411
736
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2412
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i32,
2413
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2414
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2415
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2416
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2417
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2418
736
        GIR_EraseFromParent, /*InsnID*/0,
2419
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2420
736
        // GIR_Coverage, 760,
2421
736
        GIR_Done,
2422
736
      // Label 117: @4614
2423
736
      GIM_Reject,
2424
736
    // Label 100: @4615
2425
736
    GIM_Reject,
2426
736
    // Label 42: @4616
2427
736
    GIM_Try, /*On fail goto*//*Label 118*/ 5075,
2428
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
2429
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
2430
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
2431
736
      GIM_Try, /*On fail goto*//*Label 119*/ 4700, // Rule ID 2709 //
2432
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2433
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2434
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2435
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2436
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2437
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2438
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2439
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2440
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2441
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2442
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2443
736
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1100:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2444
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2445
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2446
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2447
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2448
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2449
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2450
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2451
736
        GIR_EraseFromParent, /*InsnID*/0,
2452
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2453
736
        // GIR_Coverage, 2709,
2454
736
        GIR_Done,
2455
736
      // Label 119: @4700
2456
736
      GIM_Try, /*On fail goto*//*Label 120*/ 4770, // Rule ID 2715 //
2457
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2458
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2459
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2460
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2461
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2462
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2463
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2464
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2465
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2466
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2467
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2468
736
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1101:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2469
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2470
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2471
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2472
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2473
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2474
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2475
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2476
736
        GIR_EraseFromParent, /*InsnID*/0,
2477
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2478
736
        // GIR_Coverage, 2715,
2479
736
        GIR_Done,
2480
736
      // Label 120: @4770
2481
736
      GIM_Try, /*On fail goto*//*Label 121*/ 4840, // Rule ID 1151 //
2482
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2483
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2484
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2485
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2486
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2487
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2488
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2489
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2490
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2491
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2492
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2493
736
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1100:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2494
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2495
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2496
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2497
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2498
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2499
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2500
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2501
736
        GIR_EraseFromParent, /*InsnID*/0,
2502
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2503
736
        // GIR_Coverage, 1151,
2504
736
        GIR_Done,
2505
736
      // Label 121: @4840
2506
736
      GIM_Try, /*On fail goto*//*Label 122*/ 4910, // Rule ID 1157 //
2507
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2508
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2509
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2510
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2511
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2512
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2513
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2514
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2515
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2516
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2517
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2518
736
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1101:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2519
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2520
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2521
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2522
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2523
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2524
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2525
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2526
736
        GIR_EraseFromParent, /*InsnID*/0,
2527
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2528
736
        // GIR_Coverage, 1157,
2529
736
        GIR_Done,
2530
736
      // Label 122: @4910
2531
736
      GIM_Try, /*On fail goto*//*Label 123*/ 4973, // Rule ID 2639 //
2532
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2533
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2534
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2535
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2536
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2537
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2538
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2539
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2540
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2541
736
        // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2542
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2543
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2544
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2545
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2546
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2547
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2548
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2549
736
        GIR_EraseFromParent, /*InsnID*/0,
2550
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2551
736
        // GIR_Coverage, 2639,
2552
736
        GIR_Done,
2553
736
      // Label 123: @4973
2554
736
      GIM_Try, /*On fail goto*//*Label 124*/ 5036, // Rule ID 874 //
2555
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2556
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2557
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2558
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2559
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2560
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2561
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2562
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2563
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2564
736
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2565
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2566
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2567
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2568
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2569
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2570
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2571
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2572
736
        GIR_EraseFromParent, /*InsnID*/0,
2573
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2574
736
        // GIR_Coverage, 874,
2575
736
        GIR_Done,
2576
736
      // Label 124: @5036
2577
736
      GIM_Try, /*On fail goto*//*Label 125*/ 5074, // Rule ID 755 //
2578
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2579
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2580
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2581
736
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2582
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i8,
2583
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2584
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2585
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2586
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2587
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2588
736
        GIR_EraseFromParent, /*InsnID*/0,
2589
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2590
736
        // GIR_Coverage, 755,
2591
736
        GIR_Done,
2592
736
      // Label 125: @5074
2593
736
      GIM_Reject,
2594
736
    // Label 118: @5075
2595
736
    GIM_Reject,
2596
736
    // Label 43: @5076
2597
736
    GIM_Try, /*On fail goto*//*Label 126*/ 6199,
2598
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2599
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2600
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2601
736
      GIM_Try, /*On fail goto*//*Label 127*/ 5173, // Rule ID 2721 //
2602
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2603
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2604
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2605
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2606
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2607
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2608
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2609
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2610
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2611
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2612
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2613
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2614
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2615
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2616
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2617
736
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1100:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2618
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2619
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2620
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2621
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2622
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2623
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2624
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2625
736
        GIR_EraseFromParent, /*InsnID*/0,
2626
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2627
736
        // GIR_Coverage, 2721,
2628
736
        GIR_Done,
2629
736
      // Label 127: @5173
2630
736
      GIM_Try, /*On fail goto*//*Label 128*/ 5256, // Rule ID 2724 //
2631
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2632
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2633
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2634
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2635
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2636
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2637
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2638
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2639
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2640
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2641
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2642
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2643
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2644
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2645
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2646
736
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1101:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2647
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2648
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2649
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2650
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2651
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2652
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2653
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2654
736
        GIR_EraseFromParent, /*InsnID*/0,
2655
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2656
736
        // GIR_Coverage, 2724,
2657
736
        GIR_Done,
2658
736
      // Label 128: @5256
2659
736
      GIM_Try, /*On fail goto*//*Label 129*/ 5339, // Rule ID 1163 //
2660
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2661
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2662
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2663
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2664
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2665
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2666
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2667
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2668
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2669
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2670
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2671
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2672
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2673
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2674
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2675
736
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1100:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2676
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2677
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2678
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2679
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2680
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2681
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2682
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2683
736
        GIR_EraseFromParent, /*InsnID*/0,
2684
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2685
736
        // GIR_Coverage, 1163,
2686
736
        GIR_Done,
2687
736
      // Label 129: @5339
2688
736
      GIM_Try, /*On fail goto*//*Label 130*/ 5422, // Rule ID 1166 //
2689
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2690
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2691
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2692
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2693
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2694
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2695
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2696
736
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2697
736
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2698
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2699
736
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2700
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2701
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2702
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2703
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2704
736
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1101:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2705
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2706
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2707
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2708
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2709
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2710
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2711
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2712
736
        GIR_EraseFromParent, /*InsnID*/0,
2713
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2714
736
        // GIR_Coverage, 1166,
2715
736
        GIR_Done,
2716
736
      // Label 130: @5422
2717
736
      GIM_Try, /*On fail goto*//*Label 131*/ 5492, // Rule ID 2713 //
2718
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2719
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2720
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2721
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2722
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2723
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2724
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2725
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2726
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2727
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2728
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2729
736
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1100:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2730
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
2731
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2732
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2733
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2734
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2735
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2736
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2737
736
        GIR_EraseFromParent, /*InsnID*/0,
2738
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2739
736
        // GIR_Coverage, 2713,
2740
736
        GIR_Done,
2741
736
      // Label 131: @5492
2742
736
      GIM_Try, /*On fail goto*//*Label 132*/ 5562, // Rule ID 2719 //
2743
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2744
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2745
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2746
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2747
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2748
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2749
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2750
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2751
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2752
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2753
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2754
736
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1101:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2755
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
2756
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2757
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2758
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2759
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2760
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2761
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2762
736
        GIR_EraseFromParent, /*InsnID*/0,
2763
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2764
736
        // GIR_Coverage, 2719,
2765
736
        GIR_Done,
2766
736
      // Label 132: @5562
2767
736
      GIM_Try, /*On fail goto*//*Label 133*/ 5632, // Rule ID 1155 //
2768
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2769
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2770
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2771
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2772
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2773
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2774
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2775
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2776
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2777
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2778
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2779
736
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1100:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2780
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
2781
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2782
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2783
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2784
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2785
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2786
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2787
736
        GIR_EraseFromParent, /*InsnID*/0,
2788
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2789
736
        // GIR_Coverage, 1155,
2790
736
        GIR_Done,
2791
736
      // Label 133: @5632
2792
736
      GIM_Try, /*On fail goto*//*Label 134*/ 5702, // Rule ID 1161 //
2793
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2794
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2795
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2796
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2797
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2798
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2799
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2800
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2801
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2802
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2803
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2804
736
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1101:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2805
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
2806
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2807
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2808
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2809
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2810
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2811
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2812
736
        GIR_EraseFromParent, /*InsnID*/0,
2813
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2814
736
        // GIR_Coverage, 1161,
2815
736
        GIR_Done,
2816
736
      // Label 134: @5702
2817
736
      GIM_Try, /*On fail goto*//*Label 135*/ 5766, // Rule ID 767 //
2818
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2819
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2820
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2821
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2822
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2823
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2824
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2825
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
2826
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2827
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2828
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2829
736
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2830
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv8i16,
2831
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2832
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2833
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2834
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2835
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2836
736
        GIR_EraseFromParent, /*InsnID*/0,
2837
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2838
736
        // GIR_Coverage, 767,
2839
736
        GIR_Done,
2840
736
      // Label 135: @5766
2841
736
      GIM_Try, /*On fail goto*//*Label 136*/ 5830, // Rule ID 770 //
2842
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2843
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2844
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2845
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2846
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2847
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2848
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2849
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
2850
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2851
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2852
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2853
736
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2854
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
2855
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2856
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2857
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2858
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2859
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2860
736
        GIR_EraseFromParent, /*InsnID*/0,
2861
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2862
736
        // GIR_Coverage, 770,
2863
736
        GIR_Done,
2864
736
      // Label 136: @5830
2865
736
      GIM_Try, /*On fail goto*//*Label 137*/ 5893, // Rule ID 2643 //
2866
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2867
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2868
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2869
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2870
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2871
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2872
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2873
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2874
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2875
736
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2876
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
2877
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2878
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2879
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2880
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2881
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2882
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2883
736
        GIR_EraseFromParent, /*InsnID*/0,
2884
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2885
736
        // GIR_Coverage, 2643,
2886
736
        GIR_Done,
2887
736
      // Label 137: @5893
2888
736
      GIM_Try, /*On fail goto*//*Label 138*/ 5944, // Rule ID 2615 //
2889
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2890
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2891
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2892
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2893
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2894
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2895
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2896
736
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2897
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
2898
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2899
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2900
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2901
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2902
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2903
736
        GIR_EraseFromParent, /*InsnID*/0,
2904
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2905
736
        // GIR_Coverage, 2615,
2906
736
        GIR_Done,
2907
736
      // Label 138: @5944
2908
736
      GIM_Try, /*On fail goto*//*Label 139*/ 5995, // Rule ID 2618 //
2909
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2910
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2911
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2912
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2913
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2914
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2915
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2916
736
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2917
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
2918
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2919
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2920
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2921
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2922
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2923
736
        GIR_EraseFromParent, /*InsnID*/0,
2924
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2925
736
        // GIR_Coverage, 2618,
2926
736
        GIR_Done,
2927
736
      // Label 139: @5995
2928
736
      GIM_Try, /*On fail goto*//*Label 140*/ 6058, // Rule ID 878 //
2929
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2930
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2931
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2932
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2933
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2934
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2935
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2936
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2937
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2938
736
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2939
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
2940
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2941
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2942
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2943
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2944
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2945
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2946
736
        GIR_EraseFromParent, /*InsnID*/0,
2947
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2948
736
        // GIR_Coverage, 878,
2949
736
        GIR_Done,
2950
736
      // Label 140: @6058
2951
736
      GIM_Try, /*On fail goto*//*Label 141*/ 6109, // Rule ID 773 //
2952
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2953
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2954
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2955
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2956
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2957
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2958
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2959
736
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2960
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
2961
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2962
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2963
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2964
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2965
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2966
736
        GIR_EraseFromParent, /*InsnID*/0,
2967
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2968
736
        // GIR_Coverage, 773,
2969
736
        GIR_Done,
2970
736
      // Label 141: @6109
2971
736
      GIM_Try, /*On fail goto*//*Label 142*/ 6160, // Rule ID 776 //
2972
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2973
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2974
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2975
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2976
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2977
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2978
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2979
736
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2980
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
2981
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2982
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2983
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2984
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2985
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2986
736
        GIR_EraseFromParent, /*InsnID*/0,
2987
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2988
736
        // GIR_Coverage, 776,
2989
736
        GIR_Done,
2990
736
      // Label 142: @6160
2991
736
      GIM_Try, /*On fail goto*//*Label 143*/ 6198, // Rule ID 759 //
2992
736
        GIM_CheckFeatures, GIFBS_HasNEON,
2993
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2994
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2995
736
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2996
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i16,
2997
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2998
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2999
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3000
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3001
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3002
736
        GIR_EraseFromParent, /*InsnID*/0,
3003
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3004
736
        // GIR_Coverage, 759,
3005
736
        GIR_Done,
3006
736
      // Label 143: @6198
3007
736
      GIM_Reject,
3008
736
    // Label 126: @6199
3009
736
    GIM_Reject,
3010
736
    // Label 44: @6200
3011
736
    GIM_Try, /*On fail goto*//*Label 144*/ 6659,
3012
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3013
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3014
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3015
736
      GIM_Try, /*On fail goto*//*Label 145*/ 6284, // Rule ID 2712 //
3016
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3017
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3018
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3019
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3020
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3021
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3022
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3023
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3024
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3025
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3026
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3027
736
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1100:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3028
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3029
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3030
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3031
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3032
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3033
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3034
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3035
736
        GIR_EraseFromParent, /*InsnID*/0,
3036
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3037
736
        // GIR_Coverage, 2712,
3038
736
        GIR_Done,
3039
736
      // Label 145: @6284
3040
736
      GIM_Try, /*On fail goto*//*Label 146*/ 6354, // Rule ID 2718 //
3041
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3042
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3043
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3044
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3045
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3046
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3047
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3048
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3049
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3050
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3051
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3052
736
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1101:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3053
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3054
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3055
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3056
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3057
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3058
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3059
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3060
736
        GIR_EraseFromParent, /*InsnID*/0,
3061
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3062
736
        // GIR_Coverage, 2718,
3063
736
        GIR_Done,
3064
736
      // Label 146: @6354
3065
736
      GIM_Try, /*On fail goto*//*Label 147*/ 6424, // Rule ID 1154 //
3066
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3067
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3068
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3069
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3070
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3071
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3072
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3073
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3074
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3075
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3076
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3077
736
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1100:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3078
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3079
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3080
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3081
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3082
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3083
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3084
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3085
736
        GIR_EraseFromParent, /*InsnID*/0,
3086
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3087
736
        // GIR_Coverage, 1154,
3088
736
        GIR_Done,
3089
736
      // Label 147: @6424
3090
736
      GIM_Try, /*On fail goto*//*Label 148*/ 6494, // Rule ID 1160 //
3091
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3092
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3093
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3094
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3095
736
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3096
736
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3097
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3098
736
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3099
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3100
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3101
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3102
736
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1101:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3103
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3104
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3105
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3106
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3107
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3108
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3109
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3110
736
        GIR_EraseFromParent, /*InsnID*/0,
3111
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3112
736
        // GIR_Coverage, 1160,
3113
736
        GIR_Done,
3114
736
      // Label 148: @6494
3115
736
      GIM_Try, /*On fail goto*//*Label 149*/ 6557, // Rule ID 2642 //
3116
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3117
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3118
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3119
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3120
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3121
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3122
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3123
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3124
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3125
736
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3126
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3127
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3128
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3129
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3130
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3131
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3132
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3133
736
        GIR_EraseFromParent, /*InsnID*/0,
3134
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3135
736
        // GIR_Coverage, 2642,
3136
736
        GIR_Done,
3137
736
      // Label 149: @6557
3138
736
      GIM_Try, /*On fail goto*//*Label 150*/ 6620, // Rule ID 877 //
3139
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3140
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3141
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3142
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3143
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3144
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3145
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3146
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3147
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3148
736
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3149
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3150
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3151
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3152
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3153
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3154
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3155
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3156
736
        GIR_EraseFromParent, /*InsnID*/0,
3157
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3158
736
        // GIR_Coverage, 877,
3159
736
        GIR_Done,
3160
736
      // Label 150: @6620
3161
736
      GIM_Try, /*On fail goto*//*Label 151*/ 6658, // Rule ID 758 //
3162
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3163
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3164
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3165
736
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3166
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv16i8,
3167
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3168
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3169
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3170
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3171
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3172
736
        GIR_EraseFromParent, /*InsnID*/0,
3173
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3174
736
        // GIR_Coverage, 758,
3175
736
        GIR_Done,
3176
736
      // Label 151: @6658
3177
736
      GIM_Reject,
3178
736
    // Label 144: @6659
3179
736
    GIM_Reject,
3180
736
    // Label 45: @6660
3181
736
    GIM_Reject,
3182
736
    // Label 1: @6661
3183
736
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 161*/ 8650,
3184
736
    /*GILLT_s32*//*Label 152*/ 6676,
3185
736
    /*GILLT_s64*//*Label 153*/ 7169,
3186
736
    /*GILLT_v2s32*//*Label 154*/ 7220,
3187
736
    /*GILLT_v2s64*//*Label 155*/ 7333,
3188
736
    /*GILLT_v4s16*//*Label 156*/ 7617,
3189
736
    /*GILLT_v4s32*//*Label 157*/ 7730,
3190
736
    /*GILLT_v8s8*//*Label 158*/ 8077,
3191
736
    /*GILLT_v8s16*//*Label 159*/ 8190,
3192
736
    /*GILLT_v16s8*//*Label 160*/ 8537,
3193
736
    // Label 152: @6676
3194
736
    GIM_Try, /*On fail goto*//*Label 162*/ 7168,
3195
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3196
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3197
736
      GIM_Try, /*On fail goto*//*Label 163*/ 6738, // Rule ID 98 //
3198
736
        GIM_CheckFeatures, GIFBS_IsARM,
3199
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3200
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3201
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3202
736
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3203
736
        // MIs[1] Operand 1
3204
736
        // No operand predicates
3205
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3206
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3207
736
        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn)  =>  (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3208
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RSBri,
3209
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3210
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3211
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3212
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3213
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3214
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3215
736
        GIR_EraseFromParent, /*InsnID*/0,
3216
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3217
736
        // GIR_Coverage, 98,
3218
736
        GIR_Done,
3219
736
      // Label 163: @6738
3220
736
      GIM_Try, /*On fail goto*//*Label 164*/ 6790, // Rule ID 432 //
3221
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
3222
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3223
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3224
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3225
736
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
3226
736
        // MIs[1] Operand 1
3227
736
        // No operand predicates
3228
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3229
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3230
736
        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn)  =>  (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3231
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RSBri,
3232
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3233
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3234
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3235
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3236
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3237
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3238
736
        GIR_EraseFromParent, /*InsnID*/0,
3239
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3240
736
        // GIR_Coverage, 432,
3241
736
        GIR_Done,
3242
736
      // Label 164: @6790
3243
736
      GIM_Try, /*On fail goto*//*Label 165*/ 6842, // Rule ID 78 //
3244
736
        GIM_CheckFeatures, GIFBS_IsARM,
3245
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3246
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3247
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3248
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3249
736
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3250
736
        // MIs[1] Operand 1
3251
736
        // No operand predicates
3252
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3253
736
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3254
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBri,
3255
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3256
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3257
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3258
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3259
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3260
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3261
736
        GIR_EraseFromParent, /*InsnID*/0,
3262
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3263
736
        // GIR_Coverage, 78,
3264
736
        GIR_Done,
3265
736
      // Label 165: @6842
3266
736
      GIM_Try, /*On fail goto*//*Label 166*/ 6894, // Rule ID 416 //
3267
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
3268
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3269
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
3270
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3271
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3272
736
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
3273
736
        // MIs[1] Operand 1
3274
736
        // No operand predicates
3275
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3276
736
        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3277
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri,
3278
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3279
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3280
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3281
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3282
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3283
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3284
736
        GIR_EraseFromParent, /*InsnID*/0,
3285
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3286
736
        // GIR_Coverage, 416,
3287
736
        GIR_Done,
3288
736
      // Label 166: @6894
3289
736
      GIM_Try, /*On fail goto*//*Label 167*/ 6943, // Rule ID 417 //
3290
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
3291
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3292
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3293
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3294
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3295
736
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
3296
736
        // MIs[1] Operand 1
3297
736
        // No operand predicates
3298
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3299
736
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3300
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri12,
3301
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3302
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3303
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3304
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3305
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3306
736
        GIR_EraseFromParent, /*InsnID*/0,
3307
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3308
736
        // GIR_Coverage, 417,
3309
736
        GIR_Done,
3310
736
      // Label 167: @6943
3311
736
      GIM_Try, /*On fail goto*//*Label 168*/ 7010, // Rule ID 175 //
3312
736
        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM_UseMulOps,
3313
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3314
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3315
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3316
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3317
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3318
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3319
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3320
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3321
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3322
736
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm))  =>  (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
3323
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLS,
3324
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3325
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3326
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3327
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3328
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3329
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3330
736
        GIR_EraseFromParent, /*InsnID*/0,
3331
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3332
736
        // GIR_Coverage, 175,
3333
736
        GIR_Done,
3334
736
      // Label 168: @7010
3335
736
      GIM_Try, /*On fail goto*//*Label 169*/ 7077, // Rule ID 509 //
3336
736
        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
3337
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3338
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3339
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3340
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3341
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3342
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3343
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3344
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3345
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3346
736
        // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
3347
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLS,
3348
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3349
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3350
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3351
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3352
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3353
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3354
736
        GIR_EraseFromParent, /*InsnID*/0,
3355
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3356
736
        // GIR_Coverage, 509,
3357
736
        GIR_Done,
3358
736
      // Label 169: @7077
3359
736
      GIM_Try, /*On fail goto*//*Label 170*/ 7122, // Rule ID 79 //
3360
736
        GIM_CheckFeatures, GIFBS_IsARM,
3361
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3362
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3363
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3364
736
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
3365
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBrr,
3366
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3367
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3368
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
3369
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3370
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3371
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3372
736
        GIR_EraseFromParent, /*InsnID*/0,
3373
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3374
736
        // GIR_Coverage, 79,
3375
736
        GIR_Done,
3376
736
      // Label 170: @7122
3377
736
      GIM_Try, /*On fail goto*//*Label 171*/ 7167, // Rule ID 418 //
3378
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
3379
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3380
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
3381
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3382
736
        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
3383
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBrr,
3384
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3385
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3386
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
3387
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3388
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3389
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3390
736
        GIR_EraseFromParent, /*InsnID*/0,
3391
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3392
736
        // GIR_Coverage, 418,
3393
736
        GIR_Done,
3394
736
      // Label 171: @7167
3395
736
      GIM_Reject,
3396
736
    // Label 162: @7168
3397
736
    GIM_Reject,
3398
736
    // Label 153: @7169
3399
736
    GIM_Try, /*On fail goto*//*Label 172*/ 7219, // Rule ID 948 //
3400
736
      GIM_CheckFeatures, GIFBS_HasNEON,
3401
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3402
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3403
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3404
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3405
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3406
736
      // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
3407
736
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv1i64,
3408
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3409
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3410
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3411
736
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3412
736
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3413
736
      GIR_EraseFromParent, /*InsnID*/0,
3414
736
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3415
736
      // GIR_Coverage, 948,
3416
736
      GIR_Done,
3417
736
    // Label 172: @7219
3418
736
    GIM_Reject,
3419
736
    // Label 154: @7220
3420
736
    GIM_Try, /*On fail goto*//*Label 173*/ 7332,
3421
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
3422
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
3423
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3424
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3425
736
      GIM_Try, /*On fail goto*//*Label 174*/ 7297, // Rule ID 904 //
3426
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3427
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3428
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3429
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3430
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3431
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3432
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3433
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3434
736
        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3435
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv2i32,
3436
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3437
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3438
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3439
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3440
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3441
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3442
736
        GIR_EraseFromParent, /*InsnID*/0,
3443
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3444
736
        // GIR_Coverage, 904,
3445
736
        GIR_Done,
3446
736
      // Label 174: @7297
3447
736
      GIM_Try, /*On fail goto*//*Label 175*/ 7331, // Rule ID 944 //
3448
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3449
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3450
736
        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3451
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i32,
3452
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3453
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3454
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3455
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3456
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3457
736
        GIR_EraseFromParent, /*InsnID*/0,
3458
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3459
736
        // GIR_Coverage, 944,
3460
736
        GIR_Done,
3461
736
      // Label 175: @7331
3462
736
      GIM_Reject,
3463
736
    // Label 173: @7332
3464
736
    GIM_Reject,
3465
736
    // Label 155: @7333
3466
736
    GIM_Try, /*On fail goto*//*Label 176*/ 7616,
3467
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3468
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
3469
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3470
736
      GIM_Try, /*On fail goto*//*Label 177*/ 7411, // Rule ID 956 //
3471
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3472
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3473
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3474
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3475
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3476
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3477
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3478
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3479
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3480
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3481
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3482
736
        // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3483
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv2i64,
3484
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3485
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3486
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3487
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3488
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3489
736
        GIR_EraseFromParent, /*InsnID*/0,
3490
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3491
736
        // GIR_Coverage, 956,
3492
736
        GIR_Done,
3493
736
      // Label 177: @7411
3494
736
      GIM_Try, /*On fail goto*//*Label 178*/ 7475, // Rule ID 959 //
3495
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3496
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3497
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3498
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3499
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3500
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3501
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3502
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3503
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3504
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3505
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3506
736
        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3507
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
3508
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3509
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3510
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3511
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3512
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3513
736
        GIR_EraseFromParent, /*InsnID*/0,
3514
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3515
736
        // GIR_Coverage, 959,
3516
736
        GIR_Done,
3517
736
      // Label 178: @7475
3518
736
      GIM_Try, /*On fail goto*//*Label 179*/ 7526, // Rule ID 962 //
3519
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3520
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3521
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3522
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3523
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3524
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3525
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3526
736
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3527
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv2i64,
3528
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3529
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3530
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3531
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3532
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3533
736
        GIR_EraseFromParent, /*InsnID*/0,
3534
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3535
736
        // GIR_Coverage, 962,
3536
736
        GIR_Done,
3537
736
      // Label 179: @7526
3538
736
      GIM_Try, /*On fail goto*//*Label 180*/ 7577, // Rule ID 965 //
3539
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3540
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3541
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3542
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3543
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3544
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3545
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3546
736
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3547
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv2i64,
3548
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3549
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3550
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3551
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3552
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3553
736
        GIR_EraseFromParent, /*InsnID*/0,
3554
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3555
736
        // GIR_Coverage, 965,
3556
736
        GIR_Done,
3557
736
      // Label 180: @7577
3558
736
      GIM_Try, /*On fail goto*//*Label 181*/ 7615, // Rule ID 949 //
3559
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3560
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3561
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3562
736
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
3563
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i64,
3564
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3565
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3566
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3567
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3568
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3569
736
        GIR_EraseFromParent, /*InsnID*/0,
3570
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3571
736
        // GIR_Coverage, 949,
3572
736
        GIR_Done,
3573
736
      // Label 181: @7615
3574
736
      GIM_Reject,
3575
736
    // Label 176: @7616
3576
736
    GIM_Reject,
3577
736
    // Label 156: @7617
3578
736
    GIM_Try, /*On fail goto*//*Label 182*/ 7729,
3579
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
3580
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
3581
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3582
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3583
736
      GIM_Try, /*On fail goto*//*Label 183*/ 7694, // Rule ID 903 //
3584
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3585
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3586
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3587
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3588
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3589
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3590
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3591
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3592
736
        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3593
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i16,
3594
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3595
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3596
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3597
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3598
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3599
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3600
736
        GIR_EraseFromParent, /*InsnID*/0,
3601
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3602
736
        // GIR_Coverage, 903,
3603
736
        GIR_Done,
3604
736
      // Label 183: @7694
3605
736
      GIM_Try, /*On fail goto*//*Label 184*/ 7728, // Rule ID 943 //
3606
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3607
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3608
736
        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3609
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i16,
3610
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3611
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3612
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3613
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3614
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3615
736
        GIR_EraseFromParent, /*InsnID*/0,
3616
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3617
736
        // GIR_Coverage, 943,
3618
736
        GIR_Done,
3619
736
      // Label 184: @7728
3620
736
      GIM_Reject,
3621
736
    // Label 182: @7729
3622
736
    GIM_Reject,
3623
736
    // Label 157: @7730
3624
736
    GIM_Try, /*On fail goto*//*Label 185*/ 8076,
3625
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3626
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
3627
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3628
736
      GIM_Try, /*On fail goto*//*Label 186*/ 7808, // Rule ID 955 //
3629
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3630
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3631
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3632
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3633
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3634
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3635
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3636
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3637
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3638
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3639
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3640
736
        // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3641
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv4i32,
3642
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3643
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3644
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3645
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3646
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3647
736
        GIR_EraseFromParent, /*InsnID*/0,
3648
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3649
736
        // GIR_Coverage, 955,
3650
736
        GIR_Done,
3651
736
      // Label 186: @7808
3652
736
      GIM_Try, /*On fail goto*//*Label 187*/ 7872, // Rule ID 958 //
3653
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3654
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3655
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3656
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3657
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3658
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3659
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3660
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3661
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3662
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3663
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3664
736
        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3665
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
3666
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3667
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3668
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3669
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3670
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3671
736
        GIR_EraseFromParent, /*InsnID*/0,
3672
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3673
736
        // GIR_Coverage, 958,
3674
736
        GIR_Done,
3675
736
      // Label 187: @7872
3676
736
      GIM_Try, /*On fail goto*//*Label 188*/ 7935, // Rule ID 907 //
3677
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3678
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3679
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3680
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3681
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3682
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3683
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3684
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3685
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3686
736
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3687
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i32,
3688
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3689
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3690
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3691
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3692
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3693
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3694
736
        GIR_EraseFromParent, /*InsnID*/0,
3695
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3696
736
        // GIR_Coverage, 907,
3697
736
        GIR_Done,
3698
736
      // Label 188: @7935
3699
736
      GIM_Try, /*On fail goto*//*Label 189*/ 7986, // Rule ID 961 //
3700
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3701
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3702
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3703
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3704
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3705
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3706
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3707
736
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3708
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv4i32,
3709
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3710
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3711
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3712
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3713
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3714
736
        GIR_EraseFromParent, /*InsnID*/0,
3715
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3716
736
        // GIR_Coverage, 961,
3717
736
        GIR_Done,
3718
736
      // Label 189: @7986
3719
736
      GIM_Try, /*On fail goto*//*Label 190*/ 8037, // Rule ID 964 //
3720
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3721
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3722
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3723
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3724
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3725
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3726
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3727
736
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3728
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv4i32,
3729
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3730
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3731
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3732
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3733
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3734
736
        GIR_EraseFromParent, /*InsnID*/0,
3735
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3736
736
        // GIR_Coverage, 964,
3737
736
        GIR_Done,
3738
736
      // Label 190: @8037
3739
736
      GIM_Try, /*On fail goto*//*Label 191*/ 8075, // Rule ID 947 //
3740
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3741
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3742
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3743
736
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3744
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i32,
3745
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3746
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3747
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3748
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3749
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3750
736
        GIR_EraseFromParent, /*InsnID*/0,
3751
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3752
736
        // GIR_Coverage, 947,
3753
736
        GIR_Done,
3754
736
      // Label 191: @8075
3755
736
      GIM_Reject,
3756
736
    // Label 185: @8076
3757
736
    GIM_Reject,
3758
736
    // Label 158: @8077
3759
736
    GIM_Try, /*On fail goto*//*Label 192*/ 8189,
3760
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
3761
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
3762
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3763
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3764
736
      GIM_Try, /*On fail goto*//*Label 193*/ 8154, // Rule ID 902 //
3765
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3766
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3767
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3768
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3769
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3770
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3771
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3772
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3773
736
        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3774
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i8,
3775
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3776
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3777
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3778
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3779
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3780
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3781
736
        GIR_EraseFromParent, /*InsnID*/0,
3782
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3783
736
        // GIR_Coverage, 902,
3784
736
        GIR_Done,
3785
736
      // Label 193: @8154
3786
736
      GIM_Try, /*On fail goto*//*Label 194*/ 8188, // Rule ID 942 //
3787
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3788
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3789
736
        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3790
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i8,
3791
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3792
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3793
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3794
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3795
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3796
736
        GIR_EraseFromParent, /*InsnID*/0,
3797
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3798
736
        // GIR_Coverage, 942,
3799
736
        GIR_Done,
3800
736
      // Label 194: @8188
3801
736
      GIM_Reject,
3802
736
    // Label 192: @8189
3803
736
    GIM_Reject,
3804
736
    // Label 159: @8190
3805
736
    GIM_Try, /*On fail goto*//*Label 195*/ 8536,
3806
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3807
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
3808
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3809
736
      GIM_Try, /*On fail goto*//*Label 196*/ 8268, // Rule ID 954 //
3810
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3811
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3812
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3813
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3814
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3815
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3816
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3817
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3818
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3819
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3820
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3821
736
        // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3822
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv8i16,
3823
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3824
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3825
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3826
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3827
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3828
736
        GIR_EraseFromParent, /*InsnID*/0,
3829
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3830
736
        // GIR_Coverage, 954,
3831
736
        GIR_Done,
3832
736
      // Label 196: @8268
3833
736
      GIM_Try, /*On fail goto*//*Label 197*/ 8332, // Rule ID 957 //
3834
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3835
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3836
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3837
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3838
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3839
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3840
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3841
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3842
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3843
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3844
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3845
736
        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3846
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
3847
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3848
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3849
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3850
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3851
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3852
736
        GIR_EraseFromParent, /*InsnID*/0,
3853
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3854
736
        // GIR_Coverage, 957,
3855
736
        GIR_Done,
3856
736
      // Label 197: @8332
3857
736
      GIM_Try, /*On fail goto*//*Label 198*/ 8395, // Rule ID 906 //
3858
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3859
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3860
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3861
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3862
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3863
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3864
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3865
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3866
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3867
736
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3868
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i16,
3869
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3870
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3871
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3872
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3873
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3874
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3875
736
        GIR_EraseFromParent, /*InsnID*/0,
3876
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3877
736
        // GIR_Coverage, 906,
3878
736
        GIR_Done,
3879
736
      // Label 198: @8395
3880
736
      GIM_Try, /*On fail goto*//*Label 199*/ 8446, // Rule ID 960 //
3881
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3882
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3883
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3884
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3885
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3886
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3887
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3888
736
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3889
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv8i16,
3890
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3891
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3892
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3893
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3894
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3895
736
        GIR_EraseFromParent, /*InsnID*/0,
3896
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3897
736
        // GIR_Coverage, 960,
3898
736
        GIR_Done,
3899
736
      // Label 199: @8446
3900
736
      GIM_Try, /*On fail goto*//*Label 200*/ 8497, // Rule ID 963 //
3901
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3902
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3903
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3904
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3905
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3906
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3907
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3908
736
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3909
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv8i16,
3910
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3911
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3912
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3913
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3914
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3915
736
        GIR_EraseFromParent, /*InsnID*/0,
3916
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3917
736
        // GIR_Coverage, 963,
3918
736
        GIR_Done,
3919
736
      // Label 200: @8497
3920
736
      GIM_Try, /*On fail goto*//*Label 201*/ 8535, // Rule ID 946 //
3921
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3922
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3923
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3924
736
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3925
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i16,
3926
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3927
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3928
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3929
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3930
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3931
736
        GIR_EraseFromParent, /*InsnID*/0,
3932
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3933
736
        // GIR_Coverage, 946,
3934
736
        GIR_Done,
3935
736
      // Label 201: @8535
3936
736
      GIM_Reject,
3937
736
    // Label 195: @8536
3938
736
    GIM_Reject,
3939
736
    // Label 160: @8537
3940
736
    GIM_Try, /*On fail goto*//*Label 202*/ 8649,
3941
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3942
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3943
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3944
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3945
736
      GIM_Try, /*On fail goto*//*Label 203*/ 8614, // Rule ID 905 //
3946
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3947
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3948
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3949
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3950
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3951
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3952
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3953
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3954
736
        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3955
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv16i8,
3956
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3957
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3958
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3959
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3960
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3961
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3962
736
        GIR_EraseFromParent, /*InsnID*/0,
3963
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3964
736
        // GIR_Coverage, 905,
3965
736
        GIR_Done,
3966
736
      // Label 203: @8614
3967
736
      GIM_Try, /*On fail goto*//*Label 204*/ 8648, // Rule ID 945 //
3968
736
        GIM_CheckFeatures, GIFBS_HasNEON,
3969
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3970
736
        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3971
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv16i8,
3972
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3973
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3974
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3975
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3976
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3977
736
        GIR_EraseFromParent, /*InsnID*/0,
3978
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3979
736
        // GIR_Coverage, 945,
3980
736
        GIR_Done,
3981
736
      // Label 204: @8648
3982
736
      GIM_Reject,
3983
736
    // Label 202: @8649
3984
736
    GIM_Reject,
3985
736
    // Label 161: @8650
3986
736
    GIM_Reject,
3987
736
    // Label 2: @8651
3988
736
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 212*/ 9284,
3989
736
    /*GILLT_s32*//*Label 205*/ 8666, 0,
3990
736
    /*GILLT_v2s32*//*Label 206*/ 8978, 0,
3991
736
    /*GILLT_v4s16*//*Label 207*/ 9029,
3992
736
    /*GILLT_v4s32*//*Label 208*/ 9080,
3993
736
    /*GILLT_v8s8*//*Label 209*/ 9131,
3994
736
    /*GILLT_v8s16*//*Label 210*/ 9182,
3995
736
    /*GILLT_v16s8*//*Label 211*/ 9233,
3996
736
    // Label 205: @8666
3997
736
    GIM_Try, /*On fail goto*//*Label 213*/ 8977,
3998
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3999
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4000
736
      GIM_Try, /*On fail goto*//*Label 214*/ 8760, // Rule ID 188 //
4001
736
        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
4002
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4003
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4004
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4005
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4006
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4007
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4008
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
4009
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4010
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
4011
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
4012
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4013
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4014
736
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
4015
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4016
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4017
736
        // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4018
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
4019
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4020
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4021
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4022
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4023
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4024
736
        GIR_EraseFromParent, /*InsnID*/0,
4025
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4026
736
        // GIR_Coverage, 188,
4027
736
        GIR_Done,
4028
736
      // Label 214: @8760
4029
736
      GIM_Try, /*On fail goto*//*Label 215*/ 8844, // Rule ID 520 //
4030
736
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4031
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4032
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4033
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4034
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4035
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4036
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4037
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
4038
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4039
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
4040
736
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
4041
736
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4042
736
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4043
736
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
4044
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4045
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4046
736
        // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4047
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
4048
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4049
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4050
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4051
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4052
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4053
736
        GIR_EraseFromParent, /*InsnID*/0,
4054
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4055
736
        // GIR_Coverage, 520,
4056
736
        GIR_Done,
4057
736
      // Label 215: @8844
4058
736
      GIM_Try, /*On fail goto*//*Label 216*/ 8889, // Rule ID 171 //
4059
736
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4060
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4061
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4062
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4063
736
        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
4064
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MUL,
4065
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4066
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4067
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4068
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4069
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4070
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4071
736
        GIR_EraseFromParent, /*InsnID*/0,
4072
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4073
736
        // GIR_Coverage, 171,
4074
736
        GIR_Done,
4075
736
      // Label 216: @8889
4076
736
      GIM_Try, /*On fail goto*//*Label 217*/ 8934, // Rule ID 172 //
4077
736
        GIM_CheckFeatures, GIFBS_IsARM_NoV6_UseMulOps,
4078
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4079
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4080
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4081
736
        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
4082
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MULv5,
4083
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4084
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4085
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4086
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4087
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4088
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4089
736
        GIR_EraseFromParent, /*InsnID*/0,
4090
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4091
736
        // GIR_Coverage, 172,
4092
736
        GIR_Done,
4093
736
      // Label 217: @8934
4094
736
      GIM_Try, /*On fail goto*//*Label 218*/ 8976, // Rule ID 507 //
4095
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
4096
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4097
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4098
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4099
736
        // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4100
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MUL,
4101
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4102
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4103
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4104
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4105
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4106
736
        GIR_EraseFromParent, /*InsnID*/0,
4107
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4108
736
        // GIR_Coverage, 507,
4109
736
        GIR_Done,
4110
736
      // Label 218: @8976
4111
736
      GIM_Reject,
4112
736
    // Label 213: @8977
4113
736
    GIM_Reject,
4114
736
    // Label 206: @8978
4115
736
    GIM_Try, /*On fail goto*//*Label 219*/ 9028, // Rule ID 824 //
4116
736
      GIM_CheckFeatures, GIFBS_HasNEON,
4117
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
4118
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
4119
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4120
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4121
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4122
736
      // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4123
736
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv2i32,
4124
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4125
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4126
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4127
736
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4128
736
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4129
736
      GIR_EraseFromParent, /*InsnID*/0,
4130
736
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4131
736
      // GIR_Coverage, 824,
4132
736
      GIR_Done,
4133
736
    // Label 219: @9028
4134
736
    GIM_Reject,
4135
736
    // Label 207: @9029
4136
736
    GIM_Try, /*On fail goto*//*Label 220*/ 9079, // Rule ID 823 //
4137
736
      GIM_CheckFeatures, GIFBS_HasNEON,
4138
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4139
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4140
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4141
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4142
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4143
736
      // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4144
736
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i16,
4145
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4146
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4147
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4148
736
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4149
736
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4150
736
      GIR_EraseFromParent, /*InsnID*/0,
4151
736
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4152
736
      // GIR_Coverage, 823,
4153
736
      GIR_Done,
4154
736
    // Label 220: @9079
4155
736
    GIM_Reject,
4156
736
    // Label 208: @9080
4157
736
    GIM_Try, /*On fail goto*//*Label 221*/ 9130, // Rule ID 827 //
4158
736
      GIM_CheckFeatures, GIFBS_HasNEON,
4159
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4160
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4161
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4162
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4163
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4164
736
      // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4165
736
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i32,
4166
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4167
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4168
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4169
736
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4170
736
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4171
736
      GIR_EraseFromParent, /*InsnID*/0,
4172
736
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4173
736
      // GIR_Coverage, 827,
4174
736
      GIR_Done,
4175
736
    // Label 221: @9130
4176
736
    GIM_Reject,
4177
736
    // Label 209: @9131
4178
736
    GIM_Try, /*On fail goto*//*Label 222*/ 9181, // Rule ID 822 //
4179
736
      GIM_CheckFeatures, GIFBS_HasNEON,
4180
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4181
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4182
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4183
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4184
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4185
736
      // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4186
736
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i8,
4187
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4188
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4189
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4190
736
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4191
736
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4192
736
      GIR_EraseFromParent, /*InsnID*/0,
4193
736
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4194
736
      // GIR_Coverage, 822,
4195
736
      GIR_Done,
4196
736
    // Label 222: @9181
4197
736
    GIM_Reject,
4198
736
    // Label 210: @9182
4199
736
    GIM_Try, /*On fail goto*//*Label 223*/ 9232, // Rule ID 826 //
4200
736
      GIM_CheckFeatures, GIFBS_HasNEON,
4201
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4202
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4203
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4204
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4205
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4206
736
      // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4207
736
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i16,
4208
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4209
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4210
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4211
736
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4212
736
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4213
736
      GIR_EraseFromParent, /*InsnID*/0,
4214
736
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4215
736
      // GIR_Coverage, 826,
4216
736
      GIR_Done,
4217
736
    // Label 223: @9232
4218
736
    GIM_Reject,
4219
736
    // Label 211: @9233
4220
736
    GIM_Try, /*On fail goto*//*Label 224*/ 9283, // Rule ID 825 //
4221
736
      GIM_CheckFeatures, GIFBS_HasNEON,
4222
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4223
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
4224
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4225
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4226
736
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4227
736
      // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4228
736
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv16i8,
4229
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4230
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4231
736
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4232
736
      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4233
736
      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4234
736
      GIR_EraseFromParent, /*InsnID*/0,
4235
736
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4236
736
      // GIR_Coverage, 825,
4237
736
      GIR_Done,
4238
736
    // Label 224: @9283
4239
736
    GIM_Reject,
4240
736
    // Label 212: @9284
4241
736
    GIM_Reject,
4242
736
    // Label 3: @9285
4243
736
    GIM_Try, /*On fail goto*//*Label 225*/ 9384,
4244
736
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4245
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4246
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4247
736
      GIM_Try, /*On fail goto*//*Label 226*/ 9341, // Rule ID 197 //
4248
736
        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
4249
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4250
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4251
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4252
736
        // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4253
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SDIV,
4254
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4255
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4256
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4257
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4258
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4259
736
        GIR_EraseFromParent, /*InsnID*/0,
4260
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4261
736
        // GIR_Coverage, 197,
4262
736
        GIR_Done,
4263
736
      // Label 226: @9341
4264
736
      GIM_Try, /*On fail goto*//*Label 227*/ 9383, // Rule ID 537 //
4265
736
        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
4266
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4267
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4268
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4269
736
        // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4270
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SDIV,
4271
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4272
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4273
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4274
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4275
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4276
736
        GIR_EraseFromParent, /*InsnID*/0,
4277
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4278
736
        // GIR_Coverage, 537,
4279
736
        GIR_Done,
4280
736
      // Label 227: @9383
4281
736
      GIM_Reject,
4282
736
    // Label 225: @9384
4283
736
    GIM_Reject,
4284
736
    // Label 4: @9385
4285
736
    GIM_Try, /*On fail goto*//*Label 228*/ 9484,
4286
736
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4287
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4288
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4289
736
      GIM_Try, /*On fail goto*//*Label 229*/ 9441, // Rule ID 198 //
4290
736
        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
4291
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4292
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4293
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4294
736
        // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4295
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDIV,
4296
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4297
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4298
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4299
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4300
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4301
736
        GIR_EraseFromParent, /*InsnID*/0,
4302
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4303
736
        // GIR_Coverage, 198,
4304
736
        GIR_Done,
4305
736
      // Label 229: @9441
4306
736
      GIM_Try, /*On fail goto*//*Label 230*/ 9483, // Rule ID 538 //
4307
736
        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
4308
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4309
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4310
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4311
736
        // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4312
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDIV,
4313
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4314
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4315
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4316
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4317
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4318
736
        GIR_EraseFromParent, /*InsnID*/0,
4319
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4320
736
        // GIR_Coverage, 538,
4321
736
        GIR_Done,
4322
736
      // Label 230: @9483
4323
736
      GIM_Reject,
4324
736
    // Label 228: @9484
4325
736
    GIM_Reject,
4326
736
    // Label 5: @9485
4327
736
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 234*/ 11197,
4328
736
    /*GILLT_s32*//*Label 231*/ 9497, 0,
4329
736
    /*GILLT_v2s32*//*Label 232*/ 11095, 0, 0,
4330
736
    /*GILLT_v4s32*//*Label 233*/ 11146,
4331
736
    // Label 231: @9497
4332
736
    GIM_Try, /*On fail goto*//*Label 235*/ 11094,
4333
736
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4334
736
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4335
736
      GIM_Try, /*On fail goto*//*Label 236*/ 9569, // Rule ID 1712 //
4336
736
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4337
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4338
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4339
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
4340
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4341
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4342
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4343
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
4344
736
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4345
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4346
736
        // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
4347
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4348
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4349
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
4350
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
4351
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4352
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4353
736
        GIR_EraseFromParent, /*InsnID*/0,
4354
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4355
736
        // GIR_Coverage, 1712,
4356
736
        GIR_Done,
4357
736
      // Label 236: @9569
4358
736
      GIM_Try, /*On fail goto*//*Label 237*/ 9631, // Rule ID 1928 //
4359
736
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4360
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4361
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4362
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
4363
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4364
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4365
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4366
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
4367
736
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4368
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4369
736
        // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
4370
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4371
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4372
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
4373
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
4374
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4375
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4376
736
        GIR_EraseFromParent, /*InsnID*/0,
4377
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4378
736
        // GIR_Coverage, 1928,
4379
736
        GIR_Done,
4380
736
      // Label 237: @9631
4381
736
      GIM_Try, /*On fail goto*//*Label 238*/ 9672, // Rule ID 1821 //
4382
736
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4383
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4384
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4385
736
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
4386
736
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] })  =>  (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4387
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB,
4388
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4389
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4390
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4391
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4392
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4393
736
        GIR_EraseFromParent, /*InsnID*/0,
4394
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4395
736
        // GIR_Coverage, 1821,
4396
736
        GIR_Done,
4397
736
      // Label 238: @9672
4398
736
      GIM_Try, /*On fail goto*//*Label 239*/ 9713, // Rule ID 1822 //
4399
736
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4400
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4401
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4402
736
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
4403
736
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] })  =>  (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4404
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTH,
4405
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4406
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4407
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4408
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4409
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4410
736
        GIR_EraseFromParent, /*InsnID*/0,
4411
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4412
736
        // GIR_Coverage, 1822,
4413
736
        GIR_Done,
4414
736
      // Label 239: @9713
4415
736
      GIM_Try, /*On fail goto*//*Label 240*/ 9754, // Rule ID 1823 //
4416
736
        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4417
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4418
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4419
736
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4420
736
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4421
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4422
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4423
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4424
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4425
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4426
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4427
736
        GIR_EraseFromParent, /*InsnID*/0,
4428
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4429
736
        // GIR_Coverage, 1823,
4430
736
        GIR_Done,
4431
736
      // Label 240: @9754
4432
736
      GIM_Try, /*On fail goto*//*Label 241*/ 9795, // Rule ID 2019 //
4433
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
4434
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4435
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4436
736
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
4437
736
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })  =>  (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4438
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB,
4439
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4440
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4441
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4442
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4443
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4444
736
        GIR_EraseFromParent, /*InsnID*/0,
4445
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4446
736
        // GIR_Coverage, 2019,
4447
736
        GIR_Done,
4448
736
      // Label 241: @9795
4449
736
      GIM_Try, /*On fail goto*//*Label 242*/ 9836, // Rule ID 2020 //
4450
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
4451
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4452
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4453
736
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
4454
736
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })  =>  (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4455
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTH,
4456
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4457
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4458
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4459
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4460
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4461
736
        GIR_EraseFromParent, /*InsnID*/0,
4462
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4463
736
        // GIR_Coverage, 2020,
4464
736
        GIR_Done,
4465
736
      // Label 242: @9836
4466
736
      GIM_Try, /*On fail goto*//*Label 243*/ 9877, // Rule ID 2021 //
4467
736
        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4468
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4469
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4470
736
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4471
736
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4472
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4473
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4474
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4475
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4476
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4477
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4478
736
        GIR_EraseFromParent, /*InsnID*/0,
4479
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4480
736
        // GIR_Coverage, 2021,
4481
736
        GIR_Done,
4482
736
      // Label 243: @9877
4483
736
      GIM_Try, /*On fail goto*//*Label 244*/ 9950, // Rule ID 2549 //
4484
736
        GIM_CheckFeatures, GIFBS_IsARM,
4485
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4486
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4487
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4488
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4489
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4490
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4491
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4492
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4493
736
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4494
736
        // MIs[2] Operand 1
4495
736
        // No operand predicates
4496
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4497
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4498
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4499
736
        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4500
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4501
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4502
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4503
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4504
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4505
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4506
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4507
736
        GIR_EraseFromParent, /*InsnID*/0,
4508
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4509
736
        // GIR_Coverage, 2549,
4510
736
        GIR_Done,
4511
736
      // Label 244: @9950
4512
736
      GIM_Try, /*On fail goto*//*Label 245*/ 10023, // Rule ID 2582 //
4513
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
4514
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4515
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4516
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4517
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4518
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4519
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4520
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4521
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4522
736
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4523
736
        // MIs[2] Operand 1
4524
736
        // No operand predicates
4525
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4526
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4527
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4528
736
        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4529
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4530
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4531
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4532
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4533
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4534
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4535
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4536
736
        GIR_EraseFromParent, /*InsnID*/0,
4537
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4538
736
        // GIR_Coverage, 2582,
4539
736
        GIR_Done,
4540
736
      // Label 245: @10023
4541
736
      GIM_Try, /*On fail goto*//*Label 246*/ 10096, // Rule ID 2548 //
4542
736
        GIM_CheckFeatures, GIFBS_IsARM,
4543
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4544
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4545
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4546
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4547
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4548
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4549
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4550
736
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4551
736
        // MIs[2] Operand 1
4552
736
        // No operand predicates
4553
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4554
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4555
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4556
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4557
736
        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4558
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4559
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4560
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4561
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4562
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4563
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4564
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4565
736
        GIR_EraseFromParent, /*InsnID*/0,
4566
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4567
736
        // GIR_Coverage, 2548,
4568
736
        GIR_Done,
4569
736
      // Label 246: @10096
4570
736
      GIM_Try, /*On fail goto*//*Label 247*/ 10169, // Rule ID 2581 //
4571
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
4572
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4573
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4574
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4575
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4576
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4577
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4578
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4579
736
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4580
736
        // MIs[2] Operand 1
4581
736
        // No operand predicates
4582
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4583
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4584
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4585
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4586
736
        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4587
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4588
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4589
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4590
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4591
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4592
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4593
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4594
736
        GIR_EraseFromParent, /*InsnID*/0,
4595
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4596
736
        // GIR_Coverage, 2581,
4597
736
        GIR_Done,
4598
736
      // Label 247: @10169
4599
736
      GIM_Try, /*On fail goto*//*Label 248*/ 10242, // Rule ID 2547 //
4600
736
        GIM_CheckFeatures, GIFBS_IsARM,
4601
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4602
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4603
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4604
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4605
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4606
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4607
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4608
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4609
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4610
736
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4611
736
        // MIs[2] Operand 1
4612
736
        // No operand predicates
4613
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4614
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4615
736
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4616
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4617
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4618
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4619
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4620
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4621
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4622
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4623
736
        GIR_EraseFromParent, /*InsnID*/0,
4624
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4625
736
        // GIR_Coverage, 2547,
4626
736
        GIR_Done,
4627
736
      // Label 248: @10242
4628
736
      GIM_Try, /*On fail goto*//*Label 249*/ 10315, // Rule ID 2580 //
4629
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
4630
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4631
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4632
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4633
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4634
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4635
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4636
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4637
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4638
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4639
736
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4640
736
        // MIs[2] Operand 1
4641
736
        // No operand predicates
4642
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4643
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4644
736
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4645
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4646
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4647
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4648
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4649
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4650
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4651
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4652
736
        GIR_EraseFromParent, /*InsnID*/0,
4653
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4654
736
        // GIR_Coverage, 2580,
4655
736
        GIR_Done,
4656
736
      // Label 249: @10315
4657
736
      GIM_Try, /*On fail goto*//*Label 250*/ 10388, // Rule ID 161 //
4658
736
        GIM_CheckFeatures, GIFBS_IsARM,
4659
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4660
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4661
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4662
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4663
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4664
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4665
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4666
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4667
736
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4668
736
        // MIs[2] Operand 1
4669
736
        // No operand predicates
4670
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4671
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4672
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4673
736
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4674
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4675
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4676
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4677
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4678
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4679
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4680
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4681
736
        GIR_EraseFromParent, /*InsnID*/0,
4682
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4683
736
        // GIR_Coverage, 161,
4684
736
        GIR_Done,
4685
736
      // Label 250: @10388
4686
736
      GIM_Try, /*On fail goto*//*Label 251*/ 10461, // Rule ID 495 //
4687
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
4688
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4689
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4690
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4691
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4692
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4693
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4694
736
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4695
736
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4696
736
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4697
736
        // MIs[2] Operand 1
4698
736
        // No operand predicates
4699
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4700
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4701
736
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4702
736
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4703
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4704
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4705
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4706
736
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4707
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4708
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4709
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4710
736
        GIR_EraseFromParent, /*InsnID*/0,
4711
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4712
736
        // GIR_Coverage, 495,
4713
736
        GIR_Done,
4714
736
      // Label 251: @10461
4715
736
      GIM_Try, /*On fail goto*//*Label 252*/ 10527, // Rule ID 2550 //
4716
736
        GIM_CheckFeatures, GIFBS_IsARM,
4717
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4718
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4719
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4720
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4721
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4722
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4723
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4724
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4725
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4726
736
        // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4727
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
4728
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4729
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4730
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4731
736
        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4732
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4733
736
        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4734
736
        GIR_EraseFromParent, /*InsnID*/0,
4735
736
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4736
736
        // GIR_Coverage, 2550,
4737
736
        GIR_Done,
4738
736
      // Label 252: @10527
4739
736
      GIM_Try, /*On fail goto*//*Label 253*/ 10593, // Rule ID 2583 //
4740
736
        GIM_CheckFeatures, GIFBS_IsThumb2,
4741
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4742
736
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4743
736
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4744
736
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4745
736
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4746
736
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4747
736
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4748
736
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4749
736
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4750
736
        // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4751
736
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
4752
736
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd