Coverage Report

Created: 2018-09-19 20:53

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenInstrInfo.inc
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace ARM {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    CFI_INSTRUCTION = 2,
18
    EH_LABEL  = 3,
19
    GC_LABEL  = 4,
20
    ANNOTATION_LABEL  = 5,
21
    KILL  = 6,
22
    EXTRACT_SUBREG  = 7,
23
    INSERT_SUBREG = 8,
24
    IMPLICIT_DEF  = 9,
25
    SUBREG_TO_REG = 10,
26
    COPY_TO_REGCLASS  = 11,
27
    DBG_VALUE = 12,
28
    DBG_LABEL = 13,
29
    REG_SEQUENCE  = 14,
30
    COPY  = 15,
31
    BUNDLE  = 16,
32
    LIFETIME_START  = 17,
33
    LIFETIME_END  = 18,
34
    STACKMAP  = 19,
35
    FENTRY_CALL = 20,
36
    PATCHPOINT  = 21,
37
    LOAD_STACK_GUARD  = 22,
38
    STATEPOINT  = 23,
39
    LOCAL_ESCAPE  = 24,
40
    FAULTING_OP = 25,
41
    PATCHABLE_OP  = 26,
42
    PATCHABLE_FUNCTION_ENTER  = 27,
43
    PATCHABLE_RET = 28,
44
    PATCHABLE_FUNCTION_EXIT = 29,
45
    PATCHABLE_TAIL_CALL = 30,
46
    PATCHABLE_EVENT_CALL  = 31,
47
    PATCHABLE_TYPED_EVENT_CALL  = 32,
48
    ICALL_BRANCH_FUNNEL = 33,
49
    G_ADD = 34,
50
    G_SUB = 35,
51
    G_MUL = 36,
52
    G_SDIV  = 37,
53
    G_UDIV  = 38,
54
    G_SREM  = 39,
55
    G_UREM  = 40,
56
    G_AND = 41,
57
    G_OR  = 42,
58
    G_XOR = 43,
59
    G_IMPLICIT_DEF  = 44,
60
    G_PHI = 45,
61
    G_FRAME_INDEX = 46,
62
    G_GLOBAL_VALUE  = 47,
63
    G_EXTRACT = 48,
64
    G_UNMERGE_VALUES  = 49,
65
    G_INSERT  = 50,
66
    G_MERGE_VALUES  = 51,
67
    G_PTRTOINT  = 52,
68
    G_INTTOPTR  = 53,
69
    G_BITCAST = 54,
70
    G_INTRINSIC_TRUNC = 55,
71
    G_INTRINSIC_ROUND = 56,
72
    G_LOAD  = 57,
73
    G_SEXTLOAD  = 58,
74
    G_ZEXTLOAD  = 59,
75
    G_STORE = 60,
76
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 61,
77
    G_ATOMIC_CMPXCHG  = 62,
78
    G_ATOMICRMW_XCHG  = 63,
79
    G_ATOMICRMW_ADD = 64,
80
    G_ATOMICRMW_SUB = 65,
81
    G_ATOMICRMW_AND = 66,
82
    G_ATOMICRMW_NAND  = 67,
83
    G_ATOMICRMW_OR  = 68,
84
    G_ATOMICRMW_XOR = 69,
85
    G_ATOMICRMW_MAX = 70,
86
    G_ATOMICRMW_MIN = 71,
87
    G_ATOMICRMW_UMAX  = 72,
88
    G_ATOMICRMW_UMIN  = 73,
89
    G_BRCOND  = 74,
90
    G_BRINDIRECT  = 75,
91
    G_INTRINSIC = 76,
92
    G_INTRINSIC_W_SIDE_EFFECTS  = 77,
93
    G_ANYEXT  = 78,
94
    G_TRUNC = 79,
95
    G_CONSTANT  = 80,
96
    G_FCONSTANT = 81,
97
    G_VASTART = 82,
98
    G_VAARG = 83,
99
    G_SEXT  = 84,
100
    G_ZEXT  = 85,
101
    G_SHL = 86,
102
    G_LSHR  = 87,
103
    G_ASHR  = 88,
104
    G_ICMP  = 89,
105
    G_FCMP  = 90,
106
    G_SELECT  = 91,
107
    G_UADDO = 92,
108
    G_UADDE = 93,
109
    G_USUBO = 94,
110
    G_USUBE = 95,
111
    G_SADDO = 96,
112
    G_SADDE = 97,
113
    G_SSUBO = 98,
114
    G_SSUBE = 99,
115
    G_UMULO = 100,
116
    G_SMULO = 101,
117
    G_UMULH = 102,
118
    G_SMULH = 103,
119
    G_FADD  = 104,
120
    G_FSUB  = 105,
121
    G_FMUL  = 106,
122
    G_FMA = 107,
123
    G_FDIV  = 108,
124
    G_FREM  = 109,
125
    G_FPOW  = 110,
126
    G_FEXP  = 111,
127
    G_FEXP2 = 112,
128
    G_FLOG  = 113,
129
    G_FLOG2 = 114,
130
    G_FNEG  = 115,
131
    G_FPEXT = 116,
132
    G_FPTRUNC = 117,
133
    G_FPTOSI  = 118,
134
    G_FPTOUI  = 119,
135
    G_SITOFP  = 120,
136
    G_UITOFP  = 121,
137
    G_FABS  = 122,
138
    G_GEP = 123,
139
    G_PTR_MASK  = 124,
140
    G_BR  = 125,
141
    G_INSERT_VECTOR_ELT = 126,
142
    G_EXTRACT_VECTOR_ELT  = 127,
143
    G_SHUFFLE_VECTOR  = 128,
144
    G_CTTZ  = 129,
145
    G_CTTZ_ZERO_UNDEF = 130,
146
    G_CTLZ  = 131,
147
    G_CTLZ_ZERO_UNDEF = 132,
148
    G_CTPOP = 133,
149
    G_BSWAP = 134,
150
    G_ADDRSPACE_CAST  = 135,
151
    G_BLOCK_ADDR  = 136,
152
    ABS = 137,
153
    ADDSri  = 138,
154
    ADDSrr  = 139,
155
    ADDSrsi = 140,
156
    ADDSrsr = 141,
157
    ADJCALLSTACKDOWN  = 142,
158
    ADJCALLSTACKUP  = 143,
159
    ASRi  = 144,
160
    ASRr  = 145,
161
    B = 146,
162
    BCCZi64 = 147,
163
    BCCi64  = 148,
164
    BMOVPCB_CALL  = 149,
165
    BMOVPCRX_CALL = 150,
166
    BR_JTadd  = 151,
167
    BR_JTm_i12  = 152,
168
    BR_JTm_rs = 153,
169
    BR_JTr  = 154,
170
    BX_CALL = 155,
171
    CMP_SWAP_16 = 156,
172
    CMP_SWAP_32 = 157,
173
    CMP_SWAP_64 = 158,
174
    CMP_SWAP_8  = 159,
175
    CONSTPOOL_ENTRY = 160,
176
    COPY_STRUCT_BYVAL_I32 = 161,
177
    CompilerBarrier = 162,
178
    ITasm = 163,
179
    Int_eh_sjlj_dispatchsetup = 164,
180
    Int_eh_sjlj_longjmp = 165,
181
    Int_eh_sjlj_setjmp  = 166,
182
    Int_eh_sjlj_setjmp_nofp = 167,
183
    Int_eh_sjlj_setup_dispatch  = 168,
184
    JUMPTABLE_ADDRS = 169,
185
    JUMPTABLE_INSTS = 170,
186
    JUMPTABLE_TBB = 171,
187
    JUMPTABLE_TBH = 172,
188
    LDMIA_RET = 173,
189
    LDRBT_POST  = 174,
190
    LDRConstPool  = 175,
191
    LDRLIT_ga_abs = 176,
192
    LDRLIT_ga_pcrel = 177,
193
    LDRLIT_ga_pcrel_ldr = 178,
194
    LDRT_POST = 179,
195
    LEApcrel  = 180,
196
    LEApcrelJT  = 181,
197
    LSLi  = 182,
198
    LSLr  = 183,
199
    LSRi  = 184,
200
    LSRr  = 185,
201
    MEMCPY  = 186,
202
    MLAv5 = 187,
203
    MOVCCi  = 188,
204
    MOVCCi16  = 189,
205
    MOVCCi32imm = 190,
206
    MOVCCr  = 191,
207
    MOVCCsi = 192,
208
    MOVCCsr = 193,
209
    MOVPCRX = 194,
210
    MOVTi16_ga_pcrel  = 195,
211
    MOV_ga_pcrel  = 196,
212
    MOV_ga_pcrel_ldr  = 197,
213
    MOVi16_ga_pcrel = 198,
214
    MOVi32imm = 199,
215
    MOVsra_flag = 200,
216
    MOVsrl_flag = 201,
217
    MULv5 = 202,
218
    MVNCCi  = 203,
219
    PICADD  = 204,
220
    PICLDR  = 205,
221
    PICLDRB = 206,
222
    PICLDRH = 207,
223
    PICLDRSB  = 208,
224
    PICLDRSH  = 209,
225
    PICSTR  = 210,
226
    PICSTRB = 211,
227
    PICSTRH = 212,
228
    RORi  = 213,
229
    RORr  = 214,
230
    RRX = 215,
231
    RRXi  = 216,
232
    RSBSri  = 217,
233
    RSBSrsi = 218,
234
    RSBSrsr = 219,
235
    SMLALv5 = 220,
236
    SMULLv5 = 221,
237
    SPACE = 222,
238
    STRBT_POST  = 223,
239
    STRBi_preidx  = 224,
240
    STRBr_preidx  = 225,
241
    STRH_preidx = 226,
242
    STRT_POST = 227,
243
    STRi_preidx = 228,
244
    STRr_preidx = 229,
245
    SUBS_PC_LR  = 230,
246
    SUBSri  = 231,
247
    SUBSrr  = 232,
248
    SUBSrsi = 233,
249
    SUBSrsr = 234,
250
    TAILJMPd  = 235,
251
    TAILJMPr  = 236,
252
    TAILJMPr4 = 237,
253
    TCRETURNdi  = 238,
254
    TCRETURNri  = 239,
255
    TPsoft  = 240,
256
    UMLALv5 = 241,
257
    UMULLv5 = 242,
258
    VLD1LNdAsm_16 = 243,
259
    VLD1LNdAsm_32 = 244,
260
    VLD1LNdAsm_8  = 245,
261
    VLD1LNdWB_fixed_Asm_16  = 246,
262
    VLD1LNdWB_fixed_Asm_32  = 247,
263
    VLD1LNdWB_fixed_Asm_8 = 248,
264
    VLD1LNdWB_register_Asm_16 = 249,
265
    VLD1LNdWB_register_Asm_32 = 250,
266
    VLD1LNdWB_register_Asm_8  = 251,
267
    VLD2LNdAsm_16 = 252,
268
    VLD2LNdAsm_32 = 253,
269
    VLD2LNdAsm_8  = 254,
270
    VLD2LNdWB_fixed_Asm_16  = 255,
271
    VLD2LNdWB_fixed_Asm_32  = 256,
272
    VLD2LNdWB_fixed_Asm_8 = 257,
273
    VLD2LNdWB_register_Asm_16 = 258,
274
    VLD2LNdWB_register_Asm_32 = 259,
275
    VLD2LNdWB_register_Asm_8  = 260,
276
    VLD2LNqAsm_16 = 261,
277
    VLD2LNqAsm_32 = 262,
278
    VLD2LNqWB_fixed_Asm_16  = 263,
279
    VLD2LNqWB_fixed_Asm_32  = 264,
280
    VLD2LNqWB_register_Asm_16 = 265,
281
    VLD2LNqWB_register_Asm_32 = 266,
282
    VLD3DUPdAsm_16  = 267,
283
    VLD3DUPdAsm_32  = 268,
284
    VLD3DUPdAsm_8 = 269,
285
    VLD3DUPdWB_fixed_Asm_16 = 270,
286
    VLD3DUPdWB_fixed_Asm_32 = 271,
287
    VLD3DUPdWB_fixed_Asm_8  = 272,
288
    VLD3DUPdWB_register_Asm_16  = 273,
289
    VLD3DUPdWB_register_Asm_32  = 274,
290
    VLD3DUPdWB_register_Asm_8 = 275,
291
    VLD3DUPqAsm_16  = 276,
292
    VLD3DUPqAsm_32  = 277,
293
    VLD3DUPqAsm_8 = 278,
294
    VLD3DUPqWB_fixed_Asm_16 = 279,
295
    VLD3DUPqWB_fixed_Asm_32 = 280,
296
    VLD3DUPqWB_fixed_Asm_8  = 281,
297
    VLD3DUPqWB_register_Asm_16  = 282,
298
    VLD3DUPqWB_register_Asm_32  = 283,
299
    VLD3DUPqWB_register_Asm_8 = 284,
300
    VLD3LNdAsm_16 = 285,
301
    VLD3LNdAsm_32 = 286,
302
    VLD3LNdAsm_8  = 287,
303
    VLD3LNdWB_fixed_Asm_16  = 288,
304
    VLD3LNdWB_fixed_Asm_32  = 289,
305
    VLD3LNdWB_fixed_Asm_8 = 290,
306
    VLD3LNdWB_register_Asm_16 = 291,
307
    VLD3LNdWB_register_Asm_32 = 292,
308
    VLD3LNdWB_register_Asm_8  = 293,
309
    VLD3LNqAsm_16 = 294,
310
    VLD3LNqAsm_32 = 295,
311
    VLD3LNqWB_fixed_Asm_16  = 296,
312
    VLD3LNqWB_fixed_Asm_32  = 297,
313
    VLD3LNqWB_register_Asm_16 = 298,
314
    VLD3LNqWB_register_Asm_32 = 299,
315
    VLD3dAsm_16 = 300,
316
    VLD3dAsm_32 = 301,
317
    VLD3dAsm_8  = 302,
318
    VLD3dWB_fixed_Asm_16  = 303,
319
    VLD3dWB_fixed_Asm_32  = 304,
320
    VLD3dWB_fixed_Asm_8 = 305,
321
    VLD3dWB_register_Asm_16 = 306,
322
    VLD3dWB_register_Asm_32 = 307,
323
    VLD3dWB_register_Asm_8  = 308,
324
    VLD3qAsm_16 = 309,
325
    VLD3qAsm_32 = 310,
326
    VLD3qAsm_8  = 311,
327
    VLD3qWB_fixed_Asm_16  = 312,
328
    VLD3qWB_fixed_Asm_32  = 313,
329
    VLD3qWB_fixed_Asm_8 = 314,
330
    VLD3qWB_register_Asm_16 = 315,
331
    VLD3qWB_register_Asm_32 = 316,
332
    VLD3qWB_register_Asm_8  = 317,
333
    VLD4DUPdAsm_16  = 318,
334
    VLD4DUPdAsm_32  = 319,
335
    VLD4DUPdAsm_8 = 320,
336
    VLD4DUPdWB_fixed_Asm_16 = 321,
337
    VLD4DUPdWB_fixed_Asm_32 = 322,
338
    VLD4DUPdWB_fixed_Asm_8  = 323,
339
    VLD4DUPdWB_register_Asm_16  = 324,
340
    VLD4DUPdWB_register_Asm_32  = 325,
341
    VLD4DUPdWB_register_Asm_8 = 326,
342
    VLD4DUPqAsm_16  = 327,
343
    VLD4DUPqAsm_32  = 328,
344
    VLD4DUPqAsm_8 = 329,
345
    VLD4DUPqWB_fixed_Asm_16 = 330,
346
    VLD4DUPqWB_fixed_Asm_32 = 331,
347
    VLD4DUPqWB_fixed_Asm_8  = 332,
348
    VLD4DUPqWB_register_Asm_16  = 333,
349
    VLD4DUPqWB_register_Asm_32  = 334,
350
    VLD4DUPqWB_register_Asm_8 = 335,
351
    VLD4LNdAsm_16 = 336,
352
    VLD4LNdAsm_32 = 337,
353
    VLD4LNdAsm_8  = 338,
354
    VLD4LNdWB_fixed_Asm_16  = 339,
355
    VLD4LNdWB_fixed_Asm_32  = 340,
356
    VLD4LNdWB_fixed_Asm_8 = 341,
357
    VLD4LNdWB_register_Asm_16 = 342,
358
    VLD4LNdWB_register_Asm_32 = 343,
359
    VLD4LNdWB_register_Asm_8  = 344,
360
    VLD4LNqAsm_16 = 345,
361
    VLD4LNqAsm_32 = 346,
362
    VLD4LNqWB_fixed_Asm_16  = 347,
363
    VLD4LNqWB_fixed_Asm_32  = 348,
364
    VLD4LNqWB_register_Asm_16 = 349,
365
    VLD4LNqWB_register_Asm_32 = 350,
366
    VLD4dAsm_16 = 351,
367
    VLD4dAsm_32 = 352,
368
    VLD4dAsm_8  = 353,
369
    VLD4dWB_fixed_Asm_16  = 354,
370
    VLD4dWB_fixed_Asm_32  = 355,
371
    VLD4dWB_fixed_Asm_8 = 356,
372
    VLD4dWB_register_Asm_16 = 357,
373
    VLD4dWB_register_Asm_32 = 358,
374
    VLD4dWB_register_Asm_8  = 359,
375
    VLD4qAsm_16 = 360,
376
    VLD4qAsm_32 = 361,
377
    VLD4qAsm_8  = 362,
378
    VLD4qWB_fixed_Asm_16  = 363,
379
    VLD4qWB_fixed_Asm_32  = 364,
380
    VLD4qWB_fixed_Asm_8 = 365,
381
    VLD4qWB_register_Asm_16 = 366,
382
    VLD4qWB_register_Asm_32 = 367,
383
    VLD4qWB_register_Asm_8  = 368,
384
    VMOVD0  = 369,
385
    VMOVDcc = 370,
386
    VMOVQ0  = 371,
387
    VMOVScc = 372,
388
    VST1LNdAsm_16 = 373,
389
    VST1LNdAsm_32 = 374,
390
    VST1LNdAsm_8  = 375,
391
    VST1LNdWB_fixed_Asm_16  = 376,
392
    VST1LNdWB_fixed_Asm_32  = 377,
393
    VST1LNdWB_fixed_Asm_8 = 378,
394
    VST1LNdWB_register_Asm_16 = 379,
395
    VST1LNdWB_register_Asm_32 = 380,
396
    VST1LNdWB_register_Asm_8  = 381,
397
    VST2LNdAsm_16 = 382,
398
    VST2LNdAsm_32 = 383,
399
    VST2LNdAsm_8  = 384,
400
    VST2LNdWB_fixed_Asm_16  = 385,
401
    VST2LNdWB_fixed_Asm_32  = 386,
402
    VST2LNdWB_fixed_Asm_8 = 387,
403
    VST2LNdWB_register_Asm_16 = 388,
404
    VST2LNdWB_register_Asm_32 = 389,
405
    VST2LNdWB_register_Asm_8  = 390,
406
    VST2LNqAsm_16 = 391,
407
    VST2LNqAsm_32 = 392,
408
    VST2LNqWB_fixed_Asm_16  = 393,
409
    VST2LNqWB_fixed_Asm_32  = 394,
410
    VST2LNqWB_register_Asm_16 = 395,
411
    VST2LNqWB_register_Asm_32 = 396,
412
    VST3LNdAsm_16 = 397,
413
    VST3LNdAsm_32 = 398,
414
    VST3LNdAsm_8  = 399,
415
    VST3LNdWB_fixed_Asm_16  = 400,
416
    VST3LNdWB_fixed_Asm_32  = 401,
417
    VST3LNdWB_fixed_Asm_8 = 402,
418
    VST3LNdWB_register_Asm_16 = 403,
419
    VST3LNdWB_register_Asm_32 = 404,
420
    VST3LNdWB_register_Asm_8  = 405,
421
    VST3LNqAsm_16 = 406,
422
    VST3LNqAsm_32 = 407,
423
    VST3LNqWB_fixed_Asm_16  = 408,
424
    VST3LNqWB_fixed_Asm_32  = 409,
425
    VST3LNqWB_register_Asm_16 = 410,
426
    VST3LNqWB_register_Asm_32 = 411,
427
    VST3dAsm_16 = 412,
428
    VST3dAsm_32 = 413,
429
    VST3dAsm_8  = 414,
430
    VST3dWB_fixed_Asm_16  = 415,
431
    VST3dWB_fixed_Asm_32  = 416,
432
    VST3dWB_fixed_Asm_8 = 417,
433
    VST3dWB_register_Asm_16 = 418,
434
    VST3dWB_register_Asm_32 = 419,
435
    VST3dWB_register_Asm_8  = 420,
436
    VST3qAsm_16 = 421,
437
    VST3qAsm_32 = 422,
438
    VST3qAsm_8  = 423,
439
    VST3qWB_fixed_Asm_16  = 424,
440
    VST3qWB_fixed_Asm_32  = 425,
441
    VST3qWB_fixed_Asm_8 = 426,
442
    VST3qWB_register_Asm_16 = 427,
443
    VST3qWB_register_Asm_32 = 428,
444
    VST3qWB_register_Asm_8  = 429,
445
    VST4LNdAsm_16 = 430,
446
    VST4LNdAsm_32 = 431,
447
    VST4LNdAsm_8  = 432,
448
    VST4LNdWB_fixed_Asm_16  = 433,
449
    VST4LNdWB_fixed_Asm_32  = 434,
450
    VST4LNdWB_fixed_Asm_8 = 435,
451
    VST4LNdWB_register_Asm_16 = 436,
452
    VST4LNdWB_register_Asm_32 = 437,
453
    VST4LNdWB_register_Asm_8  = 438,
454
    VST4LNqAsm_16 = 439,
455
    VST4LNqAsm_32 = 440,
456
    VST4LNqWB_fixed_Asm_16  = 441,
457
    VST4LNqWB_fixed_Asm_32  = 442,
458
    VST4LNqWB_register_Asm_16 = 443,
459
    VST4LNqWB_register_Asm_32 = 444,
460
    VST4dAsm_16 = 445,
461
    VST4dAsm_32 = 446,
462
    VST4dAsm_8  = 447,
463
    VST4dWB_fixed_Asm_16  = 448,
464
    VST4dWB_fixed_Asm_32  = 449,
465
    VST4dWB_fixed_Asm_8 = 450,
466
    VST4dWB_register_Asm_16 = 451,
467
    VST4dWB_register_Asm_32 = 452,
468
    VST4dWB_register_Asm_8  = 453,
469
    VST4qAsm_16 = 454,
470
    VST4qAsm_32 = 455,
471
    VST4qAsm_8  = 456,
472
    VST4qWB_fixed_Asm_16  = 457,
473
    VST4qWB_fixed_Asm_32  = 458,
474
    VST4qWB_fixed_Asm_8 = 459,
475
    VST4qWB_register_Asm_16 = 460,
476
    VST4qWB_register_Asm_32 = 461,
477
    VST4qWB_register_Asm_8  = 462,
478
    WIN__CHKSTK = 463,
479
    WIN__DBZCHK = 464,
480
    t2ABS = 465,
481
    t2ADDSri  = 466,
482
    t2ADDSrr  = 467,
483
    t2ADDSrs  = 468,
484
    t2BR_JT = 469,
485
    t2LDMIA_RET = 470,
486
    t2LDRBpcrel = 471,
487
    t2LDRConstPool  = 472,
488
    t2LDRHpcrel = 473,
489
    t2LDRSBpcrel  = 474,
490
    t2LDRSHpcrel  = 475,
491
    t2LDRpci_pic  = 476,
492
    t2LDRpcrel  = 477,
493
    t2LEApcrel  = 478,
494
    t2LEApcrelJT  = 479,
495
    t2MOVCCasr  = 480,
496
    t2MOVCCi  = 481,
497
    t2MOVCCi16  = 482,
498
    t2MOVCCi32imm = 483,
499
    t2MOVCClsl  = 484,
500
    t2MOVCClsr  = 485,
501
    t2MOVCCr  = 486,
502
    t2MOVCCror  = 487,
503
    t2MOVSsi  = 488,
504
    t2MOVSsr  = 489,
505
    t2MOVTi16_ga_pcrel  = 490,
506
    t2MOV_ga_pcrel  = 491,
507
    t2MOVi16_ga_pcrel = 492,
508
    t2MOVi32imm = 493,
509
    t2MOVsi = 494,
510
    t2MOVsr = 495,
511
    t2MVNCCi  = 496,
512
    t2RSBSri  = 497,
513
    t2RSBSrs  = 498,
514
    t2STRB_preidx = 499,
515
    t2STRH_preidx = 500,
516
    t2STR_preidx  = 501,
517
    t2SUBSri  = 502,
518
    t2SUBSrr  = 503,
519
    t2SUBSrs  = 504,
520
    t2TBB_JT  = 505,
521
    t2TBH_JT  = 506,
522
    tADCS = 507,
523
    tADDSi3 = 508,
524
    tADDSi8 = 509,
525
    tADDSrr = 510,
526
    tADDframe = 511,
527
    tADJCALLSTACKDOWN = 512,
528
    tADJCALLSTACKUP = 513,
529
    tBRIND  = 514,
530
    tBR_JTr = 515,
531
    tBX_CALL  = 516,
532
    tBX_RET = 517,
533
    tBX_RET_vararg  = 518,
534
    tBfar = 519,
535
    tLDMIA_UPD  = 520,
536
    tLDRConstPool = 521,
537
    tLDRLIT_ga_abs  = 522,
538
    tLDRLIT_ga_pcrel  = 523,
539
    tLDR_postidx  = 524,
540
    tLDRpci_pic = 525,
541
    tLEApcrel = 526,
542
    tLEApcrelJT = 527,
543
    tMOVCCr_pseudo  = 528,
544
    tPOP_RET  = 529,
545
    tSBCS = 530,
546
    tSUBSi3 = 531,
547
    tSUBSi8 = 532,
548
    tSUBSrr = 533,
549
    tTAILJMPd = 534,
550
    tTAILJMPdND = 535,
551
    tTAILJMPr = 536,
552
    tTBB_JT = 537,
553
    tTBH_JT = 538,
554
    tTPsoft = 539,
555
    ADCri = 540,
556
    ADCrr = 541,
557
    ADCrsi  = 542,
558
    ADCrsr  = 543,
559
    ADDri = 544,
560
    ADDrr = 545,
561
    ADDrsi  = 546,
562
    ADDrsr  = 547,
563
    ADR = 548,
564
    AESD  = 549,
565
    AESE  = 550,
566
    AESIMC  = 551,
567
    AESMC = 552,
568
    ANDri = 553,
569
    ANDrr = 554,
570
    ANDrsi  = 555,
571
    ANDrsr  = 556,
572
    BFC = 557,
573
    BFI = 558,
574
    BICri = 559,
575
    BICrr = 560,
576
    BICrsi  = 561,
577
    BICrsr  = 562,
578
    BKPT  = 563,
579
    BL  = 564,
580
    BLX = 565,
581
    BLX_pred  = 566,
582
    BLXi  = 567,
583
    BL_pred = 568,
584
    BX  = 569,
585
    BXJ = 570,
586
    BX_RET  = 571,
587
    BX_pred = 572,
588
    Bcc = 573,
589
    CDP = 574,
590
    CDP2  = 575,
591
    CLREX = 576,
592
    CLZ = 577,
593
    CMNri = 578,
594
    CMNzrr  = 579,
595
    CMNzrsi = 580,
596
    CMNzrsr = 581,
597
    CMPri = 582,
598
    CMPrr = 583,
599
    CMPrsi  = 584,
600
    CMPrsr  = 585,
601
    CPS1p = 586,
602
    CPS2p = 587,
603
    CPS3p = 588,
604
    CRC32B  = 589,
605
    CRC32CB = 590,
606
    CRC32CH = 591,
607
    CRC32CW = 592,
608
    CRC32H  = 593,
609
    CRC32W  = 594,
610
    DBG = 595,
611
    DMB = 596,
612
    DSB = 597,
613
    EORri = 598,
614
    EORrr = 599,
615
    EORrsi  = 600,
616
    EORrsr  = 601,
617
    ERET  = 602,
618
    FCONSTD = 603,
619
    FCONSTH = 604,
620
    FCONSTS = 605,
621
    FLDMXDB_UPD = 606,
622
    FLDMXIA = 607,
623
    FLDMXIA_UPD = 608,
624
    FMSTAT  = 609,
625
    FSTMXDB_UPD = 610,
626
    FSTMXIA = 611,
627
    FSTMXIA_UPD = 612,
628
    HINT  = 613,
629
    HLT = 614,
630
    HVC = 615,
631
    ISB = 616,
632
    LDA = 617,
633
    LDAB  = 618,
634
    LDAEX = 619,
635
    LDAEXB  = 620,
636
    LDAEXD  = 621,
637
    LDAEXH  = 622,
638
    LDAH  = 623,
639
    LDC2L_OFFSET  = 624,
640
    LDC2L_OPTION  = 625,
641
    LDC2L_POST  = 626,
642
    LDC2L_PRE = 627,
643
    LDC2_OFFSET = 628,
644
    LDC2_OPTION = 629,
645
    LDC2_POST = 630,
646
    LDC2_PRE  = 631,
647
    LDCL_OFFSET = 632,
648
    LDCL_OPTION = 633,
649
    LDCL_POST = 634,
650
    LDCL_PRE  = 635,
651
    LDC_OFFSET  = 636,
652
    LDC_OPTION  = 637,
653
    LDC_POST  = 638,
654
    LDC_PRE = 639,
655
    LDMDA = 640,
656
    LDMDA_UPD = 641,
657
    LDMDB = 642,
658
    LDMDB_UPD = 643,
659
    LDMIA = 644,
660
    LDMIA_UPD = 645,
661
    LDMIB = 646,
662
    LDMIB_UPD = 647,
663
    LDRBT_POST_IMM  = 648,
664
    LDRBT_POST_REG  = 649,
665
    LDRB_POST_IMM = 650,
666
    LDRB_POST_REG = 651,
667
    LDRB_PRE_IMM  = 652,
668
    LDRB_PRE_REG  = 653,
669
    LDRBi12 = 654,
670
    LDRBrs  = 655,
671
    LDRD  = 656,
672
    LDRD_POST = 657,
673
    LDRD_PRE  = 658,
674
    LDREX = 659,
675
    LDREXB  = 660,
676
    LDREXD  = 661,
677
    LDREXH  = 662,
678
    LDRH  = 663,
679
    LDRHTi  = 664,
680
    LDRHTr  = 665,
681
    LDRH_POST = 666,
682
    LDRH_PRE  = 667,
683
    LDRSB = 668,
684
    LDRSBTi = 669,
685
    LDRSBTr = 670,
686
    LDRSB_POST  = 671,
687
    LDRSB_PRE = 672,
688
    LDRSH = 673,
689
    LDRSHTi = 674,
690
    LDRSHTr = 675,
691
    LDRSH_POST  = 676,
692
    LDRSH_PRE = 677,
693
    LDRT_POST_IMM = 678,
694
    LDRT_POST_REG = 679,
695
    LDR_POST_IMM  = 680,
696
    LDR_POST_REG  = 681,
697
    LDR_PRE_IMM = 682,
698
    LDR_PRE_REG = 683,
699
    LDRcp = 684,
700
    LDRi12  = 685,
701
    LDRrs = 686,
702
    MCR = 687,
703
    MCR2  = 688,
704
    MCRR  = 689,
705
    MCRR2 = 690,
706
    MLA = 691,
707
    MLS = 692,
708
    MOVPCLR = 693,
709
    MOVTi16 = 694,
710
    MOVi  = 695,
711
    MOVi16  = 696,
712
    MOVr  = 697,
713
    MOVr_TC = 698,
714
    MOVsi = 699,
715
    MOVsr = 700,
716
    MRC = 701,
717
    MRC2  = 702,
718
    MRRC  = 703,
719
    MRRC2 = 704,
720
    MRS = 705,
721
    MRSbanked = 706,
722
    MRSsys  = 707,
723
    MSR = 708,
724
    MSRbanked = 709,
725
    MSRi  = 710,
726
    MUL = 711,
727
    MVNi  = 712,
728
    MVNr  = 713,
729
    MVNsi = 714,
730
    MVNsr = 715,
731
    ORRri = 716,
732
    ORRrr = 717,
733
    ORRrsi  = 718,
734
    ORRrsr  = 719,
735
    PKHBT = 720,
736
    PKHTB = 721,
737
    PLDWi12 = 722,
738
    PLDWrs  = 723,
739
    PLDi12  = 724,
740
    PLDrs = 725,
741
    PLIi12  = 726,
742
    PLIrs = 727,
743
    QADD  = 728,
744
    QADD16  = 729,
745
    QADD8 = 730,
746
    QASX  = 731,
747
    QDADD = 732,
748
    QDSUB = 733,
749
    QSAX  = 734,
750
    QSUB  = 735,
751
    QSUB16  = 736,
752
    QSUB8 = 737,
753
    RBIT  = 738,
754
    REV = 739,
755
    REV16 = 740,
756
    REVSH = 741,
757
    RFEDA = 742,
758
    RFEDA_UPD = 743,
759
    RFEDB = 744,
760
    RFEDB_UPD = 745,
761
    RFEIA = 746,
762
    RFEIA_UPD = 747,
763
    RFEIB = 748,
764
    RFEIB_UPD = 749,
765
    RSBri = 750,
766
    RSBrr = 751,
767
    RSBrsi  = 752,
768
    RSBrsr  = 753,
769
    RSCri = 754,
770
    RSCrr = 755,
771
    RSCrsi  = 756,
772
    RSCrsr  = 757,
773
    SADD16  = 758,
774
    SADD8 = 759,
775
    SASX  = 760,
776
    SBCri = 761,
777
    SBCrr = 762,
778
    SBCrsi  = 763,
779
    SBCrsr  = 764,
780
    SBFX  = 765,
781
    SDIV  = 766,
782
    SEL = 767,
783
    SETEND  = 768,
784
    SETPAN  = 769,
785
    SHA1C = 770,
786
    SHA1H = 771,
787
    SHA1M = 772,
788
    SHA1P = 773,
789
    SHA1SU0 = 774,
790
    SHA1SU1 = 775,
791
    SHA256H = 776,
792
    SHA256H2  = 777,
793
    SHA256SU0 = 778,
794
    SHA256SU1 = 779,
795
    SHADD16 = 780,
796
    SHADD8  = 781,
797
    SHASX = 782,
798
    SHSAX = 783,
799
    SHSUB16 = 784,
800
    SHSUB8  = 785,
801
    SMC = 786,
802
    SMLABB  = 787,
803
    SMLABT  = 788,
804
    SMLAD = 789,
805
    SMLADX  = 790,
806
    SMLAL = 791,
807
    SMLALBB = 792,
808
    SMLALBT = 793,
809
    SMLALD  = 794,
810
    SMLALDX = 795,
811
    SMLALTB = 796,
812
    SMLALTT = 797,
813
    SMLATB  = 798,
814
    SMLATT  = 799,
815
    SMLAWB  = 800,
816
    SMLAWT  = 801,
817
    SMLSD = 802,
818
    SMLSDX  = 803,
819
    SMLSLD  = 804,
820
    SMLSLDX = 805,
821
    SMMLA = 806,
822
    SMMLAR  = 807,
823
    SMMLS = 808,
824
    SMMLSR  = 809,
825
    SMMUL = 810,
826
    SMMULR  = 811,
827
    SMUAD = 812,
828
    SMUADX  = 813,
829
    SMULBB  = 814,
830
    SMULBT  = 815,
831
    SMULL = 816,
832
    SMULTB  = 817,
833
    SMULTT  = 818,
834
    SMULWB  = 819,
835
    SMULWT  = 820,
836
    SMUSD = 821,
837
    SMUSDX  = 822,
838
    SRSDA = 823,
839
    SRSDA_UPD = 824,
840
    SRSDB = 825,
841
    SRSDB_UPD = 826,
842
    SRSIA = 827,
843
    SRSIA_UPD = 828,
844
    SRSIB = 829,
845
    SRSIB_UPD = 830,
846
    SSAT  = 831,
847
    SSAT16  = 832,
848
    SSAX  = 833,
849
    SSUB16  = 834,
850
    SSUB8 = 835,
851
    STC2L_OFFSET  = 836,
852
    STC2L_OPTION  = 837,
853
    STC2L_POST  = 838,
854
    STC2L_PRE = 839,
855
    STC2_OFFSET = 840,
856
    STC2_OPTION = 841,
857
    STC2_POST = 842,
858
    STC2_PRE  = 843,
859
    STCL_OFFSET = 844,
860
    STCL_OPTION = 845,
861
    STCL_POST = 846,
862
    STCL_PRE  = 847,
863
    STC_OFFSET  = 848,
864
    STC_OPTION  = 849,
865
    STC_POST  = 850,
866
    STC_PRE = 851,
867
    STL = 852,
868
    STLB  = 853,
869
    STLEX = 854,
870
    STLEXB  = 855,
871
    STLEXD  = 856,
872
    STLEXH  = 857,
873
    STLH  = 858,
874
    STMDA = 859,
875
    STMDA_UPD = 860,
876
    STMDB = 861,
877
    STMDB_UPD = 862,
878
    STMIA = 863,
879
    STMIA_UPD = 864,
880
    STMIB = 865,
881
    STMIB_UPD = 866,
882
    STRBT_POST_IMM  = 867,
883
    STRBT_POST_REG  = 868,
884
    STRB_POST_IMM = 869,
885
    STRB_POST_REG = 870,
886
    STRB_PRE_IMM  = 871,
887
    STRB_PRE_REG  = 872,
888
    STRBi12 = 873,
889
    STRBrs  = 874,
890
    STRD  = 875,
891
    STRD_POST = 876,
892
    STRD_PRE  = 877,
893
    STREX = 878,
894
    STREXB  = 879,
895
    STREXD  = 880,
896
    STREXH  = 881,
897
    STRH  = 882,
898
    STRHTi  = 883,
899
    STRHTr  = 884,
900
    STRH_POST = 885,
901
    STRH_PRE  = 886,
902
    STRT_POST_IMM = 887,
903
    STRT_POST_REG = 888,
904
    STR_POST_IMM  = 889,
905
    STR_POST_REG  = 890,
906
    STR_PRE_IMM = 891,
907
    STR_PRE_REG = 892,
908
    STRi12  = 893,
909
    STRrs = 894,
910
    SUBri = 895,
911
    SUBrr = 896,
912
    SUBrsi  = 897,
913
    SUBrsr  = 898,
914
    SVC = 899,
915
    SWP = 900,
916
    SWPB  = 901,
917
    SXTAB = 902,
918
    SXTAB16 = 903,
919
    SXTAH = 904,
920
    SXTB  = 905,
921
    SXTB16  = 906,
922
    SXTH  = 907,
923
    TEQri = 908,
924
    TEQrr = 909,
925
    TEQrsi  = 910,
926
    TEQrsr  = 911,
927
    TRAP  = 912,
928
    TRAPNaCl  = 913,
929
    TSB = 914,
930
    TSTri = 915,
931
    TSTrr = 916,
932
    TSTrsi  = 917,
933
    TSTrsr  = 918,
934
    UADD16  = 919,
935
    UADD8 = 920,
936
    UASX  = 921,
937
    UBFX  = 922,
938
    UDF = 923,
939
    UDIV  = 924,
940
    UHADD16 = 925,
941
    UHADD8  = 926,
942
    UHASX = 927,
943
    UHSAX = 928,
944
    UHSUB16 = 929,
945
    UHSUB8  = 930,
946
    UMAAL = 931,
947
    UMLAL = 932,
948
    UMULL = 933,
949
    UQADD16 = 934,
950
    UQADD8  = 935,
951
    UQASX = 936,
952
    UQSAX = 937,
953
    UQSUB16 = 938,
954
    UQSUB8  = 939,
955
    USAD8 = 940,
956
    USADA8  = 941,
957
    USAT  = 942,
958
    USAT16  = 943,
959
    USAX  = 944,
960
    USUB16  = 945,
961
    USUB8 = 946,
962
    UXTAB = 947,
963
    UXTAB16 = 948,
964
    UXTAH = 949,
965
    UXTB  = 950,
966
    UXTB16  = 951,
967
    UXTH  = 952,
968
    VABALsv2i64 = 953,
969
    VABALsv4i32 = 954,
970
    VABALsv8i16 = 955,
971
    VABALuv2i64 = 956,
972
    VABALuv4i32 = 957,
973
    VABALuv8i16 = 958,
974
    VABAsv16i8  = 959,
975
    VABAsv2i32  = 960,
976
    VABAsv4i16  = 961,
977
    VABAsv4i32  = 962,
978
    VABAsv8i16  = 963,
979
    VABAsv8i8 = 964,
980
    VABAuv16i8  = 965,
981
    VABAuv2i32  = 966,
982
    VABAuv4i16  = 967,
983
    VABAuv4i32  = 968,
984
    VABAuv8i16  = 969,
985
    VABAuv8i8 = 970,
986
    VABDLsv2i64 = 971,
987
    VABDLsv4i32 = 972,
988
    VABDLsv8i16 = 973,
989
    VABDLuv2i64 = 974,
990
    VABDLuv4i32 = 975,
991
    VABDLuv8i16 = 976,
992
    VABDfd  = 977,
993
    VABDfq  = 978,
994
    VABDhd  = 979,
995
    VABDhq  = 980,
996
    VABDsv16i8  = 981,
997
    VABDsv2i32  = 982,
998
    VABDsv4i16  = 983,
999
    VABDsv4i32  = 984,
1000
    VABDsv8i16  = 985,
1001
    VABDsv8i8 = 986,
1002
    VABDuv16i8  = 987,
1003
    VABDuv2i32  = 988,
1004
    VABDuv4i16  = 989,
1005
    VABDuv4i32  = 990,
1006
    VABDuv8i16  = 991,
1007
    VABDuv8i8 = 992,
1008
    VABSD = 993,
1009
    VABSH = 994,
1010
    VABSS = 995,
1011
    VABSfd  = 996,
1012
    VABSfq  = 997,
1013
    VABShd  = 998,
1014
    VABShq  = 999,
1015
    VABSv16i8 = 1000,
1016
    VABSv2i32 = 1001,
1017
    VABSv4i16 = 1002,
1018
    VABSv4i32 = 1003,
1019
    VABSv8i16 = 1004,
1020
    VABSv8i8  = 1005,
1021
    VACGEfd = 1006,
1022
    VACGEfq = 1007,
1023
    VACGEhd = 1008,
1024
    VACGEhq = 1009,
1025
    VACGTfd = 1010,
1026
    VACGTfq = 1011,
1027
    VACGThd = 1012,
1028
    VACGThq = 1013,
1029
    VADDD = 1014,
1030
    VADDH = 1015,
1031
    VADDHNv2i32 = 1016,
1032
    VADDHNv4i16 = 1017,
1033
    VADDHNv8i8  = 1018,
1034
    VADDLsv2i64 = 1019,
1035
    VADDLsv4i32 = 1020,
1036
    VADDLsv8i16 = 1021,
1037
    VADDLuv2i64 = 1022,
1038
    VADDLuv4i32 = 1023,
1039
    VADDLuv8i16 = 1024,
1040
    VADDS = 1025,
1041
    VADDWsv2i64 = 1026,
1042
    VADDWsv4i32 = 1027,
1043
    VADDWsv8i16 = 1028,
1044
    VADDWuv2i64 = 1029,
1045
    VADDWuv4i32 = 1030,
1046
    VADDWuv8i16 = 1031,
1047
    VADDfd  = 1032,
1048
    VADDfq  = 1033,
1049
    VADDhd  = 1034,
1050
    VADDhq  = 1035,
1051
    VADDv16i8 = 1036,
1052
    VADDv1i64 = 1037,
1053
    VADDv2i32 = 1038,
1054
    VADDv2i64 = 1039,
1055
    VADDv4i16 = 1040,
1056
    VADDv4i32 = 1041,
1057
    VADDv8i16 = 1042,
1058
    VADDv8i8  = 1043,
1059
    VANDd = 1044,
1060
    VANDq = 1045,
1061
    VBICd = 1046,
1062
    VBICiv2i32  = 1047,
1063
    VBICiv4i16  = 1048,
1064
    VBICiv4i32  = 1049,
1065
    VBICiv8i16  = 1050,
1066
    VBICq = 1051,
1067
    VBIFd = 1052,
1068
    VBIFq = 1053,
1069
    VBITd = 1054,
1070
    VBITq = 1055,
1071
    VBSLd = 1056,
1072
    VBSLq = 1057,
1073
    VCADDv2f32  = 1058,
1074
    VCADDv4f16  = 1059,
1075
    VCADDv4f32  = 1060,
1076
    VCADDv8f16  = 1061,
1077
    VCEQfd  = 1062,
1078
    VCEQfq  = 1063,
1079
    VCEQhd  = 1064,
1080
    VCEQhq  = 1065,
1081
    VCEQv16i8 = 1066,
1082
    VCEQv2i32 = 1067,
1083
    VCEQv4i16 = 1068,
1084
    VCEQv4i32 = 1069,
1085
    VCEQv8i16 = 1070,
1086
    VCEQv8i8  = 1071,
1087
    VCEQzv16i8  = 1072,
1088
    VCEQzv2f32  = 1073,
1089
    VCEQzv2i32  = 1074,
1090
    VCEQzv4f16  = 1075,
1091
    VCEQzv4f32  = 1076,
1092
    VCEQzv4i16  = 1077,
1093
    VCEQzv4i32  = 1078,
1094
    VCEQzv8f16  = 1079,
1095
    VCEQzv8i16  = 1080,
1096
    VCEQzv8i8 = 1081,
1097
    VCGEfd  = 1082,
1098
    VCGEfq  = 1083,
1099
    VCGEhd  = 1084,
1100
    VCGEhq  = 1085,
1101
    VCGEsv16i8  = 1086,
1102
    VCGEsv2i32  = 1087,
1103
    VCGEsv4i16  = 1088,
1104
    VCGEsv4i32  = 1089,
1105
    VCGEsv8i16  = 1090,
1106
    VCGEsv8i8 = 1091,
1107
    VCGEuv16i8  = 1092,
1108
    VCGEuv2i32  = 1093,
1109
    VCGEuv4i16  = 1094,
1110
    VCGEuv4i32  = 1095,
1111
    VCGEuv8i16  = 1096,
1112
    VCGEuv8i8 = 1097,
1113
    VCGEzv16i8  = 1098,
1114
    VCGEzv2f32  = 1099,
1115
    VCGEzv2i32  = 1100,
1116
    VCGEzv4f16  = 1101,
1117
    VCGEzv4f32  = 1102,
1118
    VCGEzv4i16  = 1103,
1119
    VCGEzv4i32  = 1104,
1120
    VCGEzv8f16  = 1105,
1121
    VCGEzv8i16  = 1106,
1122
    VCGEzv8i8 = 1107,
1123
    VCGTfd  = 1108,
1124
    VCGTfq  = 1109,
1125
    VCGThd  = 1110,
1126
    VCGThq  = 1111,
1127
    VCGTsv16i8  = 1112,
1128
    VCGTsv2i32  = 1113,
1129
    VCGTsv4i16  = 1114,
1130
    VCGTsv4i32  = 1115,
1131
    VCGTsv8i16  = 1116,
1132
    VCGTsv8i8 = 1117,
1133
    VCGTuv16i8  = 1118,
1134
    VCGTuv2i32  = 1119,
1135
    VCGTuv4i16  = 1120,
1136
    VCGTuv4i32  = 1121,
1137
    VCGTuv8i16  = 1122,
1138
    VCGTuv8i8 = 1123,
1139
    VCGTzv16i8  = 1124,
1140
    VCGTzv2f32  = 1125,
1141
    VCGTzv2i32  = 1126,
1142
    VCGTzv4f16  = 1127,
1143
    VCGTzv4f32  = 1128,
1144
    VCGTzv4i16  = 1129,
1145
    VCGTzv4i32  = 1130,
1146
    VCGTzv8f16  = 1131,
1147
    VCGTzv8i16  = 1132,
1148
    VCGTzv8i8 = 1133,
1149
    VCLEzv16i8  = 1134,
1150
    VCLEzv2f32  = 1135,
1151
    VCLEzv2i32  = 1136,
1152
    VCLEzv4f16  = 1137,
1153
    VCLEzv4f32  = 1138,
1154
    VCLEzv4i16  = 1139,
1155
    VCLEzv4i32  = 1140,
1156
    VCLEzv8f16  = 1141,
1157
    VCLEzv8i16  = 1142,
1158
    VCLEzv8i8 = 1143,
1159
    VCLSv16i8 = 1144,
1160
    VCLSv2i32 = 1145,
1161
    VCLSv4i16 = 1146,
1162
    VCLSv4i32 = 1147,
1163
    VCLSv8i16 = 1148,
1164
    VCLSv8i8  = 1149,
1165
    VCLTzv16i8  = 1150,
1166
    VCLTzv2f32  = 1151,
1167
    VCLTzv2i32  = 1152,
1168
    VCLTzv4f16  = 1153,
1169
    VCLTzv4f32  = 1154,
1170
    VCLTzv4i16  = 1155,
1171
    VCLTzv4i32  = 1156,
1172
    VCLTzv8f16  = 1157,
1173
    VCLTzv8i16  = 1158,
1174
    VCLTzv8i8 = 1159,
1175
    VCLZv16i8 = 1160,
1176
    VCLZv2i32 = 1161,
1177
    VCLZv4i16 = 1162,
1178
    VCLZv4i32 = 1163,
1179
    VCLZv8i16 = 1164,
1180
    VCLZv8i8  = 1165,
1181
    VCMLAv2f32  = 1166,
1182
    VCMLAv2f32_indexed  = 1167,
1183
    VCMLAv4f16  = 1168,
1184
    VCMLAv4f16_indexed  = 1169,
1185
    VCMLAv4f32  = 1170,
1186
    VCMLAv4f32_indexed  = 1171,
1187
    VCMLAv8f16  = 1172,
1188
    VCMLAv8f16_indexed  = 1173,
1189
    VCMPD = 1174,
1190
    VCMPED  = 1175,
1191
    VCMPEH  = 1176,
1192
    VCMPES  = 1177,
1193
    VCMPEZD = 1178,
1194
    VCMPEZH = 1179,
1195
    VCMPEZS = 1180,
1196
    VCMPH = 1181,
1197
    VCMPS = 1182,
1198
    VCMPZD  = 1183,
1199
    VCMPZH  = 1184,
1200
    VCMPZS  = 1185,
1201
    VCNTd = 1186,
1202
    VCNTq = 1187,
1203
    VCVTANSDf = 1188,
1204
    VCVTANSDh = 1189,
1205
    VCVTANSQf = 1190,
1206
    VCVTANSQh = 1191,
1207
    VCVTANUDf = 1192,
1208
    VCVTANUDh = 1193,
1209
    VCVTANUQf = 1194,
1210
    VCVTANUQh = 1195,
1211
    VCVTASD = 1196,
1212
    VCVTASH = 1197,
1213
    VCVTASS = 1198,
1214
    VCVTAUD = 1199,
1215
    VCVTAUH = 1200,
1216
    VCVTAUS = 1201,
1217
    VCVTBDH = 1202,
1218
    VCVTBHD = 1203,
1219
    VCVTBHS = 1204,
1220
    VCVTBSH = 1205,
1221
    VCVTDS  = 1206,
1222
    VCVTMNSDf = 1207,
1223
    VCVTMNSDh = 1208,
1224
    VCVTMNSQf = 1209,
1225
    VCVTMNSQh = 1210,
1226
    VCVTMNUDf = 1211,
1227
    VCVTMNUDh = 1212,
1228
    VCVTMNUQf = 1213,
1229
    VCVTMNUQh = 1214,
1230
    VCVTMSD = 1215,
1231
    VCVTMSH = 1216,
1232
    VCVTMSS = 1217,
1233
    VCVTMUD = 1218,
1234
    VCVTMUH = 1219,
1235
    VCVTMUS = 1220,
1236
    VCVTNNSDf = 1221,
1237
    VCVTNNSDh = 1222,
1238
    VCVTNNSQf = 1223,
1239
    VCVTNNSQh = 1224,
1240
    VCVTNNUDf = 1225,
1241
    VCVTNNUDh = 1226,
1242
    VCVTNNUQf = 1227,
1243
    VCVTNNUQh = 1228,
1244
    VCVTNSD = 1229,
1245
    VCVTNSH = 1230,
1246
    VCVTNSS = 1231,
1247
    VCVTNUD = 1232,
1248
    VCVTNUH = 1233,
1249
    VCVTNUS = 1234,
1250
    VCVTPNSDf = 1235,
1251
    VCVTPNSDh = 1236,
1252
    VCVTPNSQf = 1237,
1253
    VCVTPNSQh = 1238,
1254
    VCVTPNUDf = 1239,
1255
    VCVTPNUDh = 1240,
1256
    VCVTPNUQf = 1241,
1257
    VCVTPNUQh = 1242,
1258
    VCVTPSD = 1243,
1259
    VCVTPSH = 1244,
1260
    VCVTPSS = 1245,
1261
    VCVTPUD = 1246,
1262
    VCVTPUH = 1247,
1263
    VCVTPUS = 1248,
1264
    VCVTSD  = 1249,
1265
    VCVTTDH = 1250,
1266
    VCVTTHD = 1251,
1267
    VCVTTHS = 1252,
1268
    VCVTTSH = 1253,
1269
    VCVTf2h = 1254,
1270
    VCVTf2sd  = 1255,
1271
    VCVTf2sq  = 1256,
1272
    VCVTf2ud  = 1257,
1273
    VCVTf2uq  = 1258,
1274
    VCVTf2xsd = 1259,
1275
    VCVTf2xsq = 1260,
1276
    VCVTf2xud = 1261,
1277
    VCVTf2xuq = 1262,
1278
    VCVTh2f = 1263,
1279
    VCVTh2sd  = 1264,
1280
    VCVTh2sq  = 1265,
1281
    VCVTh2ud  = 1266,
1282
    VCVTh2uq  = 1267,
1283
    VCVTh2xsd = 1268,
1284
    VCVTh2xsq = 1269,
1285
    VCVTh2xud = 1270,
1286
    VCVTh2xuq = 1271,
1287
    VCVTs2fd  = 1272,
1288
    VCVTs2fq  = 1273,
1289
    VCVTs2hd  = 1274,
1290
    VCVTs2hq  = 1275,
1291
    VCVTu2fd  = 1276,
1292
    VCVTu2fq  = 1277,
1293
    VCVTu2hd  = 1278,
1294
    VCVTu2hq  = 1279,
1295
    VCVTxs2fd = 1280,
1296
    VCVTxs2fq = 1281,
1297
    VCVTxs2hd = 1282,
1298
    VCVTxs2hq = 1283,
1299
    VCVTxu2fd = 1284,
1300
    VCVTxu2fq = 1285,
1301
    VCVTxu2hd = 1286,
1302
    VCVTxu2hq = 1287,
1303
    VDIVD = 1288,
1304
    VDIVH = 1289,
1305
    VDIVS = 1290,
1306
    VDUP16d = 1291,
1307
    VDUP16q = 1292,
1308
    VDUP32d = 1293,
1309
    VDUP32q = 1294,
1310
    VDUP8d  = 1295,
1311
    VDUP8q  = 1296,
1312
    VDUPLN16d = 1297,
1313
    VDUPLN16q = 1298,
1314
    VDUPLN32d = 1299,
1315
    VDUPLN32q = 1300,
1316
    VDUPLN8d  = 1301,
1317
    VDUPLN8q  = 1302,
1318
    VEORd = 1303,
1319
    VEORq = 1304,
1320
    VEXTd16 = 1305,
1321
    VEXTd32 = 1306,
1322
    VEXTd8  = 1307,
1323
    VEXTq16 = 1308,
1324
    VEXTq32 = 1309,
1325
    VEXTq64 = 1310,
1326
    VEXTq8  = 1311,
1327
    VFMAD = 1312,
1328
    VFMAH = 1313,
1329
    VFMALD  = 1314,
1330
    VFMALDI = 1315,
1331
    VFMALQ  = 1316,
1332
    VFMALQI = 1317,
1333
    VFMAS = 1318,
1334
    VFMAfd  = 1319,
1335
    VFMAfq  = 1320,
1336
    VFMAhd  = 1321,
1337
    VFMAhq  = 1322,
1338
    VFMSD = 1323,
1339
    VFMSH = 1324,
1340
    VFMSLD  = 1325,
1341
    VFMSLDI = 1326,
1342
    VFMSLQ  = 1327,
1343
    VFMSLQI = 1328,
1344
    VFMSS = 1329,
1345
    VFMSfd  = 1330,
1346
    VFMSfq  = 1331,
1347
    VFMShd  = 1332,
1348
    VFMShq  = 1333,
1349
    VFNMAD  = 1334,
1350
    VFNMAH  = 1335,
1351
    VFNMAS  = 1336,
1352
    VFNMSD  = 1337,
1353
    VFNMSH  = 1338,
1354
    VFNMSS  = 1339,
1355
    VGETLNi32 = 1340,
1356
    VGETLNs16 = 1341,
1357
    VGETLNs8  = 1342,
1358
    VGETLNu16 = 1343,
1359
    VGETLNu8  = 1344,
1360
    VHADDsv16i8 = 1345,
1361
    VHADDsv2i32 = 1346,
1362
    VHADDsv4i16 = 1347,
1363
    VHADDsv4i32 = 1348,
1364
    VHADDsv8i16 = 1349,
1365
    VHADDsv8i8  = 1350,
1366
    VHADDuv16i8 = 1351,
1367
    VHADDuv2i32 = 1352,
1368
    VHADDuv4i16 = 1353,
1369
    VHADDuv4i32 = 1354,
1370
    VHADDuv8i16 = 1355,
1371
    VHADDuv8i8  = 1356,
1372
    VHSUBsv16i8 = 1357,
1373
    VHSUBsv2i32 = 1358,
1374
    VHSUBsv4i16 = 1359,
1375
    VHSUBsv4i32 = 1360,
1376
    VHSUBsv8i16 = 1361,
1377
    VHSUBsv8i8  = 1362,
1378
    VHSUBuv16i8 = 1363,
1379
    VHSUBuv2i32 = 1364,
1380
    VHSUBuv4i16 = 1365,
1381
    VHSUBuv4i32 = 1366,
1382
    VHSUBuv8i16 = 1367,
1383
    VHSUBuv8i8  = 1368,
1384
    VINSH = 1369,
1385
    VJCVT = 1370,
1386
    VLD1DUPd16  = 1371,
1387
    VLD1DUPd16wb_fixed  = 1372,
1388
    VLD1DUPd16wb_register = 1373,
1389
    VLD1DUPd32  = 1374,
1390
    VLD1DUPd32wb_fixed  = 1375,
1391
    VLD1DUPd32wb_register = 1376,
1392
    VLD1DUPd8 = 1377,
1393
    VLD1DUPd8wb_fixed = 1378,
1394
    VLD1DUPd8wb_register  = 1379,
1395
    VLD1DUPq16  = 1380,
1396
    VLD1DUPq16wb_fixed  = 1381,
1397
    VLD1DUPq16wb_register = 1382,
1398
    VLD1DUPq32  = 1383,
1399
    VLD1DUPq32wb_fixed  = 1384,
1400
    VLD1DUPq32wb_register = 1385,
1401
    VLD1DUPq8 = 1386,
1402
    VLD1DUPq8wb_fixed = 1387,
1403
    VLD1DUPq8wb_register  = 1388,
1404
    VLD1LNd16 = 1389,
1405
    VLD1LNd16_UPD = 1390,
1406
    VLD1LNd32 = 1391,
1407
    VLD1LNd32_UPD = 1392,
1408
    VLD1LNd8  = 1393,
1409
    VLD1LNd8_UPD  = 1394,
1410
    VLD1LNq16Pseudo = 1395,
1411
    VLD1LNq16Pseudo_UPD = 1396,
1412
    VLD1LNq32Pseudo = 1397,
1413
    VLD1LNq32Pseudo_UPD = 1398,
1414
    VLD1LNq8Pseudo  = 1399,
1415
    VLD1LNq8Pseudo_UPD  = 1400,
1416
    VLD1d16 = 1401,
1417
    VLD1d16Q  = 1402,
1418
    VLD1d16QPseudo  = 1403,
1419
    VLD1d16Qwb_fixed  = 1404,
1420
    VLD1d16Qwb_register = 1405,
1421
    VLD1d16T  = 1406,
1422
    VLD1d16TPseudo  = 1407,
1423
    VLD1d16Twb_fixed  = 1408,
1424
    VLD1d16Twb_register = 1409,
1425
    VLD1d16wb_fixed = 1410,
1426
    VLD1d16wb_register  = 1411,
1427
    VLD1d32 = 1412,
1428
    VLD1d32Q  = 1413,
1429
    VLD1d32QPseudo  = 1414,
1430
    VLD1d32Qwb_fixed  = 1415,
1431
    VLD1d32Qwb_register = 1416,
1432
    VLD1d32T  = 1417,
1433
    VLD1d32TPseudo  = 1418,
1434
    VLD1d32Twb_fixed  = 1419,
1435
    VLD1d32Twb_register = 1420,
1436
    VLD1d32wb_fixed = 1421,
1437
    VLD1d32wb_register  = 1422,
1438
    VLD1d64 = 1423,
1439
    VLD1d64Q  = 1424,
1440
    VLD1d64QPseudo  = 1425,
1441
    VLD1d64QPseudoWB_fixed  = 1426,
1442
    VLD1d64QPseudoWB_register = 1427,
1443
    VLD1d64Qwb_fixed  = 1428,
1444
    VLD1d64Qwb_register = 1429,
1445
    VLD1d64T  = 1430,
1446
    VLD1d64TPseudo  = 1431,
1447
    VLD1d64TPseudoWB_fixed  = 1432,
1448
    VLD1d64TPseudoWB_register = 1433,
1449
    VLD1d64Twb_fixed  = 1434,
1450
    VLD1d64Twb_register = 1435,
1451
    VLD1d64wb_fixed = 1436,
1452
    VLD1d64wb_register  = 1437,
1453
    VLD1d8  = 1438,
1454
    VLD1d8Q = 1439,
1455
    VLD1d8QPseudo = 1440,
1456
    VLD1d8Qwb_fixed = 1441,
1457
    VLD1d8Qwb_register  = 1442,
1458
    VLD1d8T = 1443,
1459
    VLD1d8TPseudo = 1444,
1460
    VLD1d8Twb_fixed = 1445,
1461
    VLD1d8Twb_register  = 1446,
1462
    VLD1d8wb_fixed  = 1447,
1463
    VLD1d8wb_register = 1448,
1464
    VLD1q16 = 1449,
1465
    VLD1q16HighQPseudo  = 1450,
1466
    VLD1q16HighTPseudo  = 1451,
1467
    VLD1q16LowQPseudo_UPD = 1452,
1468
    VLD1q16LowTPseudo_UPD = 1453,
1469
    VLD1q16wb_fixed = 1454,
1470
    VLD1q16wb_register  = 1455,
1471
    VLD1q32 = 1456,
1472
    VLD1q32HighQPseudo  = 1457,
1473
    VLD1q32HighTPseudo  = 1458,
1474
    VLD1q32LowQPseudo_UPD = 1459,
1475
    VLD1q32LowTPseudo_UPD = 1460,
1476
    VLD1q32wb_fixed = 1461,
1477
    VLD1q32wb_register  = 1462,
1478
    VLD1q64 = 1463,
1479
    VLD1q64HighQPseudo  = 1464,
1480
    VLD1q64HighTPseudo  = 1465,
1481
    VLD1q64LowQPseudo_UPD = 1466,
1482
    VLD1q64LowTPseudo_UPD = 1467,
1483
    VLD1q64wb_fixed = 1468,
1484
    VLD1q64wb_register  = 1469,
1485
    VLD1q8  = 1470,
1486
    VLD1q8HighQPseudo = 1471,
1487
    VLD1q8HighTPseudo = 1472,
1488
    VLD1q8LowQPseudo_UPD  = 1473,
1489
    VLD1q8LowTPseudo_UPD  = 1474,
1490
    VLD1q8wb_fixed  = 1475,
1491
    VLD1q8wb_register = 1476,
1492
    VLD2DUPd16  = 1477,
1493
    VLD2DUPd16wb_fixed  = 1478,
1494
    VLD2DUPd16wb_register = 1479,
1495
    VLD2DUPd16x2  = 1480,
1496
    VLD2DUPd16x2wb_fixed  = 1481,
1497
    VLD2DUPd16x2wb_register = 1482,
1498
    VLD2DUPd32  = 1483,
1499
    VLD2DUPd32wb_fixed  = 1484,
1500
    VLD2DUPd32wb_register = 1485,
1501
    VLD2DUPd32x2  = 1486,
1502
    VLD2DUPd32x2wb_fixed  = 1487,
1503
    VLD2DUPd32x2wb_register = 1488,
1504
    VLD2DUPd8 = 1489,
1505
    VLD2DUPd8wb_fixed = 1490,
1506
    VLD2DUPd8wb_register  = 1491,
1507
    VLD2DUPd8x2 = 1492,
1508
    VLD2DUPd8x2wb_fixed = 1493,
1509
    VLD2DUPd8x2wb_register  = 1494,
1510
    VLD2DUPq16EvenPseudo  = 1495,
1511
    VLD2DUPq16OddPseudo = 1496,
1512
    VLD2DUPq32EvenPseudo  = 1497,
1513
    VLD2DUPq32OddPseudo = 1498,
1514
    VLD2DUPq8EvenPseudo = 1499,
1515
    VLD2DUPq8OddPseudo  = 1500,
1516
    VLD2LNd16 = 1501,
1517
    VLD2LNd16Pseudo = 1502,
1518
    VLD2LNd16Pseudo_UPD = 1503,
1519
    VLD2LNd16_UPD = 1504,
1520
    VLD2LNd32 = 1505,
1521
    VLD2LNd32Pseudo = 1506,
1522
    VLD2LNd32Pseudo_UPD = 1507,
1523
    VLD2LNd32_UPD = 1508,
1524
    VLD2LNd8  = 1509,
1525
    VLD2LNd8Pseudo  = 1510,
1526
    VLD2LNd8Pseudo_UPD  = 1511,
1527
    VLD2LNd8_UPD  = 1512,
1528
    VLD2LNq16 = 1513,
1529
    VLD2LNq16Pseudo = 1514,
1530
    VLD2LNq16Pseudo_UPD = 1515,
1531
    VLD2LNq16_UPD = 1516,
1532
    VLD2LNq32 = 1517,
1533
    VLD2LNq32Pseudo = 1518,
1534
    VLD2LNq32Pseudo_UPD = 1519,
1535
    VLD2LNq32_UPD = 1520,
1536
    VLD2b16 = 1521,
1537
    VLD2b16wb_fixed = 1522,
1538
    VLD2b16wb_register  = 1523,
1539
    VLD2b32 = 1524,
1540
    VLD2b32wb_fixed = 1525,
1541
    VLD2b32wb_register  = 1526,
1542
    VLD2b8  = 1527,
1543
    VLD2b8wb_fixed  = 1528,
1544
    VLD2b8wb_register = 1529,
1545
    VLD2d16 = 1530,
1546
    VLD2d16wb_fixed = 1531,
1547
    VLD2d16wb_register  = 1532,
1548
    VLD2d32 = 1533,
1549
    VLD2d32wb_fixed = 1534,
1550
    VLD2d32wb_register  = 1535,
1551
    VLD2d8  = 1536,
1552
    VLD2d8wb_fixed  = 1537,
1553
    VLD2d8wb_register = 1538,
1554
    VLD2q16 = 1539,
1555
    VLD2q16Pseudo = 1540,
1556
    VLD2q16PseudoWB_fixed = 1541,
1557
    VLD2q16PseudoWB_register  = 1542,
1558
    VLD2q16wb_fixed = 1543,
1559
    VLD2q16wb_register  = 1544,
1560
    VLD2q32 = 1545,
1561
    VLD2q32Pseudo = 1546,
1562
    VLD2q32PseudoWB_fixed = 1547,
1563
    VLD2q32PseudoWB_register  = 1548,
1564
    VLD2q32wb_fixed = 1549,
1565
    VLD2q32wb_register  = 1550,
1566
    VLD2q8  = 1551,
1567
    VLD2q8Pseudo  = 1552,
1568
    VLD2q8PseudoWB_fixed  = 1553,
1569
    VLD2q8PseudoWB_register = 1554,
1570
    VLD2q8wb_fixed  = 1555,
1571
    VLD2q8wb_register = 1556,
1572
    VLD3DUPd16  = 1557,
1573
    VLD3DUPd16Pseudo  = 1558,
1574
    VLD3DUPd16Pseudo_UPD  = 1559,
1575
    VLD3DUPd16_UPD  = 1560,
1576
    VLD3DUPd32  = 1561,
1577
    VLD3DUPd32Pseudo  = 1562,
1578
    VLD3DUPd32Pseudo_UPD  = 1563,
1579
    VLD3DUPd32_UPD  = 1564,
1580
    VLD3DUPd8 = 1565,
1581
    VLD3DUPd8Pseudo = 1566,
1582
    VLD3DUPd8Pseudo_UPD = 1567,
1583
    VLD3DUPd8_UPD = 1568,
1584
    VLD3DUPq16  = 1569,
1585
    VLD3DUPq16EvenPseudo  = 1570,
1586
    VLD3DUPq16OddPseudo = 1571,
1587
    VLD3DUPq16_UPD  = 1572,
1588
    VLD3DUPq32  = 1573,
1589
    VLD3DUPq32EvenPseudo  = 1574,
1590
    VLD3DUPq32OddPseudo = 1575,
1591
    VLD3DUPq32_UPD  = 1576,
1592
    VLD3DUPq8 = 1577,
1593
    VLD3DUPq8EvenPseudo = 1578,
1594
    VLD3DUPq8OddPseudo  = 1579,
1595
    VLD3DUPq8_UPD = 1580,
1596
    VLD3LNd16 = 1581,
1597
    VLD3LNd16Pseudo = 1582,
1598
    VLD3LNd16Pseudo_UPD = 1583,
1599
    VLD3LNd16_UPD = 1584,
1600
    VLD3LNd32 = 1585,
1601
    VLD3LNd32Pseudo = 1586,
1602
    VLD3LNd32Pseudo_UPD = 1587,
1603
    VLD3LNd32_UPD = 1588,
1604
    VLD3LNd8  = 1589,
1605
    VLD3LNd8Pseudo  = 1590,
1606
    VLD3LNd8Pseudo_UPD  = 1591,
1607
    VLD3LNd8_UPD  = 1592,
1608
    VLD3LNq16 = 1593,
1609
    VLD3LNq16Pseudo = 1594,
1610
    VLD3LNq16Pseudo_UPD = 1595,
1611
    VLD3LNq16_UPD = 1596,
1612
    VLD3LNq32 = 1597,
1613
    VLD3LNq32Pseudo = 1598,
1614
    VLD3LNq32Pseudo_UPD = 1599,
1615
    VLD3LNq32_UPD = 1600,
1616
    VLD3d16 = 1601,
1617
    VLD3d16Pseudo = 1602,
1618
    VLD3d16Pseudo_UPD = 1603,
1619
    VLD3d16_UPD = 1604,
1620
    VLD3d32 = 1605,
1621
    VLD3d32Pseudo = 1606,
1622
    VLD3d32Pseudo_UPD = 1607,
1623
    VLD3d32_UPD = 1608,
1624
    VLD3d8  = 1609,
1625
    VLD3d8Pseudo  = 1610,
1626
    VLD3d8Pseudo_UPD  = 1611,
1627
    VLD3d8_UPD  = 1612,
1628
    VLD3q16 = 1613,
1629
    VLD3q16Pseudo_UPD = 1614,
1630
    VLD3q16_UPD = 1615,
1631
    VLD3q16oddPseudo  = 1616,
1632
    VLD3q16oddPseudo_UPD  = 1617,
1633
    VLD3q32 = 1618,
1634
    VLD3q32Pseudo_UPD = 1619,
1635
    VLD3q32_UPD = 1620,
1636
    VLD3q32oddPseudo  = 1621,
1637
    VLD3q32oddPseudo_UPD  = 1622,
1638
    VLD3q8  = 1623,
1639
    VLD3q8Pseudo_UPD  = 1624,
1640
    VLD3q8_UPD  = 1625,
1641
    VLD3q8oddPseudo = 1626,
1642
    VLD3q8oddPseudo_UPD = 1627,
1643
    VLD4DUPd16  = 1628,
1644
    VLD4DUPd16Pseudo  = 1629,
1645
    VLD4DUPd16Pseudo_UPD  = 1630,
1646
    VLD4DUPd16_UPD  = 1631,
1647
    VLD4DUPd32  = 1632,
1648
    VLD4DUPd32Pseudo  = 1633,
1649
    VLD4DUPd32Pseudo_UPD  = 1634,
1650
    VLD4DUPd32_UPD  = 1635,
1651
    VLD4DUPd8 = 1636,
1652
    VLD4DUPd8Pseudo = 1637,
1653
    VLD4DUPd8Pseudo_UPD = 1638,
1654
    VLD4DUPd8_UPD = 1639,
1655
    VLD4DUPq16  = 1640,
1656
    VLD4DUPq16EvenPseudo  = 1641,
1657
    VLD4DUPq16OddPseudo = 1642,
1658
    VLD4DUPq16_UPD  = 1643,
1659
    VLD4DUPq32  = 1644,
1660
    VLD4DUPq32EvenPseudo  = 1645,
1661
    VLD4DUPq32OddPseudo = 1646,
1662
    VLD4DUPq32_UPD  = 1647,
1663
    VLD4DUPq8 = 1648,
1664
    VLD4DUPq8EvenPseudo = 1649,
1665
    VLD4DUPq8OddPseudo  = 1650,
1666
    VLD4DUPq8_UPD = 1651,
1667
    VLD4LNd16 = 1652,
1668
    VLD4LNd16Pseudo = 1653,
1669
    VLD4LNd16Pseudo_UPD = 1654,
1670
    VLD4LNd16_UPD = 1655,
1671
    VLD4LNd32 = 1656,
1672
    VLD4LNd32Pseudo = 1657,
1673
    VLD4LNd32Pseudo_UPD = 1658,
1674
    VLD4LNd32_UPD = 1659,
1675
    VLD4LNd8  = 1660,
1676
    VLD4LNd8Pseudo  = 1661,
1677
    VLD4LNd8Pseudo_UPD  = 1662,
1678
    VLD4LNd8_UPD  = 1663,
1679
    VLD4LNq16 = 1664,
1680
    VLD4LNq16Pseudo = 1665,
1681
    VLD4LNq16Pseudo_UPD = 1666,
1682
    VLD4LNq16_UPD = 1667,
1683
    VLD4LNq32 = 1668,
1684
    VLD4LNq32Pseudo = 1669,
1685
    VLD4LNq32Pseudo_UPD = 1670,
1686
    VLD4LNq32_UPD = 1671,
1687
    VLD4d16 = 1672,
1688
    VLD4d16Pseudo = 1673,
1689
    VLD4d16Pseudo_UPD = 1674,
1690
    VLD4d16_UPD = 1675,
1691
    VLD4d32 = 1676,
1692
    VLD4d32Pseudo = 1677,
1693
    VLD4d32Pseudo_UPD = 1678,
1694
    VLD4d32_UPD = 1679,
1695
    VLD4d8  = 1680,
1696
    VLD4d8Pseudo  = 1681,
1697
    VLD4d8Pseudo_UPD  = 1682,
1698
    VLD4d8_UPD  = 1683,
1699
    VLD4q16 = 1684,
1700
    VLD4q16Pseudo_UPD = 1685,
1701
    VLD4q16_UPD = 1686,
1702
    VLD4q16oddPseudo  = 1687,
1703
    VLD4q16oddPseudo_UPD  = 1688,
1704
    VLD4q32 = 1689,
1705
    VLD4q32Pseudo_UPD = 1690,
1706
    VLD4q32_UPD = 1691,
1707
    VLD4q32oddPseudo  = 1692,
1708
    VLD4q32oddPseudo_UPD  = 1693,
1709
    VLD4q8  = 1694,
1710
    VLD4q8Pseudo_UPD  = 1695,
1711
    VLD4q8_UPD  = 1696,
1712
    VLD4q8oddPseudo = 1697,
1713
    VLD4q8oddPseudo_UPD = 1698,
1714
    VLDMDDB_UPD = 1699,
1715
    VLDMDIA = 1700,
1716
    VLDMDIA_UPD = 1701,
1717
    VLDMQIA = 1702,
1718
    VLDMSDB_UPD = 1703,
1719
    VLDMSIA = 1704,
1720
    VLDMSIA_UPD = 1705,
1721
    VLDRD = 1706,
1722
    VLDRH = 1707,
1723
    VLDRS = 1708,
1724
    VLLDM = 1709,
1725
    VLSTM = 1710,
1726
    VMAXNMD = 1711,
1727
    VMAXNMH = 1712,
1728
    VMAXNMNDf = 1713,
1729
    VMAXNMNDh = 1714,
1730
    VMAXNMNQf = 1715,
1731
    VMAXNMNQh = 1716,
1732
    VMAXNMS = 1717,
1733
    VMAXfd  = 1718,
1734
    VMAXfq  = 1719,
1735
    VMAXhd  = 1720,
1736
    VMAXhq  = 1721,
1737
    VMAXsv16i8  = 1722,
1738
    VMAXsv2i32  = 1723,
1739
    VMAXsv4i16  = 1724,
1740
    VMAXsv4i32  = 1725,
1741
    VMAXsv8i16  = 1726,
1742
    VMAXsv8i8 = 1727,
1743
    VMAXuv16i8  = 1728,
1744
    VMAXuv2i32  = 1729,
1745
    VMAXuv4i16  = 1730,
1746
    VMAXuv4i32  = 1731,
1747
    VMAXuv8i16  = 1732,
1748
    VMAXuv8i8 = 1733,
1749
    VMINNMD = 1734,
1750
    VMINNMH = 1735,
1751
    VMINNMNDf = 1736,
1752
    VMINNMNDh = 1737,
1753
    VMINNMNQf = 1738,
1754
    VMINNMNQh = 1739,
1755
    VMINNMS = 1740,
1756
    VMINfd  = 1741,
1757
    VMINfq  = 1742,
1758
    VMINhd  = 1743,
1759
    VMINhq  = 1744,
1760
    VMINsv16i8  = 1745,
1761
    VMINsv2i32  = 1746,
1762
    VMINsv4i16  = 1747,
1763
    VMINsv4i32  = 1748,
1764
    VMINsv8i16  = 1749,
1765
    VMINsv8i8 = 1750,
1766
    VMINuv16i8  = 1751,
1767
    VMINuv2i32  = 1752,
1768
    VMINuv4i16  = 1753,
1769
    VMINuv4i32  = 1754,
1770
    VMINuv8i16  = 1755,
1771
    VMINuv8i8 = 1756,
1772
    VMLAD = 1757,
1773
    VMLAH = 1758,
1774
    VMLALslsv2i32 = 1759,
1775
    VMLALslsv4i16 = 1760,
1776
    VMLALsluv2i32 = 1761,
1777
    VMLALsluv4i16 = 1762,
1778
    VMLALsv2i64 = 1763,
1779
    VMLALsv4i32 = 1764,
1780
    VMLALsv8i16 = 1765,
1781
    VMLALuv2i64 = 1766,
1782
    VMLALuv4i32 = 1767,
1783
    VMLALuv8i16 = 1768,
1784
    VMLAS = 1769,
1785
    VMLAfd  = 1770,
1786
    VMLAfq  = 1771,
1787
    VMLAhd  = 1772,
1788
    VMLAhq  = 1773,
1789
    VMLAslfd  = 1774,
1790
    VMLAslfq  = 1775,
1791
    VMLAslhd  = 1776,
1792
    VMLAslhq  = 1777,
1793
    VMLAslv2i32 = 1778,
1794
    VMLAslv4i16 = 1779,
1795
    VMLAslv4i32 = 1780,
1796
    VMLAslv8i16 = 1781,
1797
    VMLAv16i8 = 1782,
1798
    VMLAv2i32 = 1783,
1799
    VMLAv4i16 = 1784,
1800
    VMLAv4i32 = 1785,
1801
    VMLAv8i16 = 1786,
1802
    VMLAv8i8  = 1787,
1803
    VMLSD = 1788,
1804
    VMLSH = 1789,
1805
    VMLSLslsv2i32 = 1790,
1806
    VMLSLslsv4i16 = 1791,
1807
    VMLSLsluv2i32 = 1792,
1808
    VMLSLsluv4i16 = 1793,
1809
    VMLSLsv2i64 = 1794,
1810
    VMLSLsv4i32 = 1795,
1811
    VMLSLsv8i16 = 1796,
1812
    VMLSLuv2i64 = 1797,
1813
    VMLSLuv4i32 = 1798,
1814
    VMLSLuv8i16 = 1799,
1815
    VMLSS = 1800,
1816
    VMLSfd  = 1801,
1817
    VMLSfq  = 1802,
1818
    VMLShd  = 1803,
1819
    VMLShq  = 1804,
1820
    VMLSslfd  = 1805,
1821
    VMLSslfq  = 1806,
1822
    VMLSslhd  = 1807,
1823
    VMLSslhq  = 1808,
1824
    VMLSslv2i32 = 1809,
1825
    VMLSslv4i16 = 1810,
1826
    VMLSslv4i32 = 1811,
1827
    VMLSslv8i16 = 1812,
1828
    VMLSv16i8 = 1813,
1829
    VMLSv2i32 = 1814,
1830
    VMLSv4i16 = 1815,
1831
    VMLSv4i32 = 1816,
1832
    VMLSv8i16 = 1817,
1833
    VMLSv8i8  = 1818,
1834
    VMOVD = 1819,
1835
    VMOVDRR = 1820,
1836
    VMOVH = 1821,
1837
    VMOVHR  = 1822,
1838
    VMOVLsv2i64 = 1823,
1839
    VMOVLsv4i32 = 1824,
1840
    VMOVLsv8i16 = 1825,
1841
    VMOVLuv2i64 = 1826,
1842
    VMOVLuv4i32 = 1827,
1843
    VMOVLuv8i16 = 1828,
1844
    VMOVNv2i32  = 1829,
1845
    VMOVNv4i16  = 1830,
1846
    VMOVNv8i8 = 1831,
1847
    VMOVRH  = 1832,
1848
    VMOVRRD = 1833,
1849
    VMOVRRS = 1834,
1850
    VMOVRS  = 1835,
1851
    VMOVS = 1836,
1852
    VMOVSR  = 1837,
1853
    VMOVSRR = 1838,
1854
    VMOVv16i8 = 1839,
1855
    VMOVv1i64 = 1840,
1856
    VMOVv2f32 = 1841,
1857
    VMOVv2i32 = 1842,
1858
    VMOVv2i64 = 1843,
1859
    VMOVv4f32 = 1844,
1860
    VMOVv4i16 = 1845,
1861
    VMOVv4i32 = 1846,
1862
    VMOVv8i16 = 1847,
1863
    VMOVv8i8  = 1848,
1864
    VMRS  = 1849,
1865
    VMRS_FPEXC  = 1850,
1866
    VMRS_FPINST = 1851,
1867
    VMRS_FPINST2  = 1852,
1868
    VMRS_FPSID  = 1853,
1869
    VMRS_MVFR0  = 1854,
1870
    VMRS_MVFR1  = 1855,
1871
    VMRS_MVFR2  = 1856,
1872
    VMSR  = 1857,
1873
    VMSR_FPEXC  = 1858,
1874
    VMSR_FPINST = 1859,
1875
    VMSR_FPINST2  = 1860,
1876
    VMSR_FPSID  = 1861,
1877
    VMULD = 1862,
1878
    VMULH = 1863,
1879
    VMULLp64  = 1864,
1880
    VMULLp8 = 1865,
1881
    VMULLslsv2i32 = 1866,
1882
    VMULLslsv4i16 = 1867,
1883
    VMULLsluv2i32 = 1868,
1884
    VMULLsluv4i16 = 1869,
1885
    VMULLsv2i64 = 1870,
1886
    VMULLsv4i32 = 1871,
1887
    VMULLsv8i16 = 1872,
1888
    VMULLuv2i64 = 1873,
1889
    VMULLuv4i32 = 1874,
1890
    VMULLuv8i16 = 1875,
1891
    VMULS = 1876,
1892
    VMULfd  = 1877,
1893
    VMULfq  = 1878,
1894
    VMULhd  = 1879,
1895
    VMULhq  = 1880,
1896
    VMULpd  = 1881,
1897
    VMULpq  = 1882,
1898
    VMULslfd  = 1883,
1899
    VMULslfq  = 1884,
1900
    VMULslhd  = 1885,
1901
    VMULslhq  = 1886,
1902
    VMULslv2i32 = 1887,
1903
    VMULslv4i16 = 1888,
1904
    VMULslv4i32 = 1889,
1905
    VMULslv8i16 = 1890,
1906
    VMULv16i8 = 1891,
1907
    VMULv2i32 = 1892,
1908
    VMULv4i16 = 1893,
1909
    VMULv4i32 = 1894,
1910
    VMULv8i16 = 1895,
1911
    VMULv8i8  = 1896,
1912
    VMVNd = 1897,
1913
    VMVNq = 1898,
1914
    VMVNv2i32 = 1899,
1915
    VMVNv4i16 = 1900,
1916
    VMVNv4i32 = 1901,
1917
    VMVNv8i16 = 1902,
1918
    VNEGD = 1903,
1919
    VNEGH = 1904,
1920
    VNEGS = 1905,
1921
    VNEGf32q  = 1906,
1922
    VNEGfd  = 1907,
1923
    VNEGhd  = 1908,
1924
    VNEGhq  = 1909,
1925
    VNEGs16d  = 1910,
1926
    VNEGs16q  = 1911,
1927
    VNEGs32d  = 1912,
1928
    VNEGs32q  = 1913,
1929
    VNEGs8d = 1914,
1930
    VNEGs8q = 1915,
1931
    VNMLAD  = 1916,
1932
    VNMLAH  = 1917,
1933
    VNMLAS  = 1918,
1934
    VNMLSD  = 1919,
1935
    VNMLSH  = 1920,
1936
    VNMLSS  = 1921,
1937
    VNMULD  = 1922,
1938
    VNMULH  = 1923,
1939
    VNMULS  = 1924,
1940
    VORNd = 1925,
1941
    VORNq = 1926,
1942
    VORRd = 1927,
1943
    VORRiv2i32  = 1928,
1944
    VORRiv4i16  = 1929,
1945
    VORRiv4i32  = 1930,
1946
    VORRiv8i16  = 1931,
1947
    VORRq = 1932,
1948
    VPADALsv16i8  = 1933,
1949
    VPADALsv2i32  = 1934,
1950
    VPADALsv4i16  = 1935,
1951
    VPADALsv4i32  = 1936,
1952
    VPADALsv8i16  = 1937,
1953
    VPADALsv8i8 = 1938,
1954
    VPADALuv16i8  = 1939,
1955
    VPADALuv2i32  = 1940,
1956
    VPADALuv4i16  = 1941,
1957
    VPADALuv4i32  = 1942,
1958
    VPADALuv8i16  = 1943,
1959
    VPADALuv8i8 = 1944,
1960
    VPADDLsv16i8  = 1945,
1961
    VPADDLsv2i32  = 1946,
1962
    VPADDLsv4i16  = 1947,
1963
    VPADDLsv4i32  = 1948,
1964
    VPADDLsv8i16  = 1949,
1965
    VPADDLsv8i8 = 1950,
1966
    VPADDLuv16i8  = 1951,
1967
    VPADDLuv2i32  = 1952,
1968
    VPADDLuv4i16  = 1953,
1969
    VPADDLuv4i32  = 1954,
1970
    VPADDLuv8i16  = 1955,
1971
    VPADDLuv8i8 = 1956,
1972
    VPADDf  = 1957,
1973
    VPADDh  = 1958,
1974
    VPADDi16  = 1959,
1975
    VPADDi32  = 1960,
1976
    VPADDi8 = 1961,
1977
    VPMAXf  = 1962,
1978
    VPMAXh  = 1963,
1979
    VPMAXs16  = 1964,
1980
    VPMAXs32  = 1965,
1981
    VPMAXs8 = 1966,
1982
    VPMAXu16  = 1967,
1983
    VPMAXu32  = 1968,
1984
    VPMAXu8 = 1969,
1985
    VPMINf  = 1970,
1986
    VPMINh  = 1971,
1987
    VPMINs16  = 1972,
1988
    VPMINs32  = 1973,
1989
    VPMINs8 = 1974,
1990
    VPMINu16  = 1975,
1991
    VPMINu32  = 1976,
1992
    VPMINu8 = 1977,
1993
    VQABSv16i8  = 1978,
1994
    VQABSv2i32  = 1979,
1995
    VQABSv4i16  = 1980,
1996
    VQABSv4i32  = 1981,
1997
    VQABSv8i16  = 1982,
1998
    VQABSv8i8 = 1983,
1999
    VQADDsv16i8 = 1984,
2000
    VQADDsv1i64 = 1985,
2001
    VQADDsv2i32 = 1986,
2002
    VQADDsv2i64 = 1987,
2003
    VQADDsv4i16 = 1988,
2004
    VQADDsv4i32 = 1989,
2005
    VQADDsv8i16 = 1990,
2006
    VQADDsv8i8  = 1991,
2007
    VQADDuv16i8 = 1992,
2008
    VQADDuv1i64 = 1993,
2009
    VQADDuv2i32 = 1994,
2010
    VQADDuv2i64 = 1995,
2011
    VQADDuv4i16 = 1996,
2012
    VQADDuv4i32 = 1997,
2013
    VQADDuv8i16 = 1998,
2014
    VQADDuv8i8  = 1999,
2015
    VQDMLALslv2i32  = 2000,
2016
    VQDMLALslv4i16  = 2001,
2017
    VQDMLALv2i64  = 2002,
2018
    VQDMLALv4i32  = 2003,
2019
    VQDMLSLslv2i32  = 2004,
2020
    VQDMLSLslv4i16  = 2005,
2021
    VQDMLSLv2i64  = 2006,
2022
    VQDMLSLv4i32  = 2007,
2023
    VQDMULHslv2i32  = 2008,
2024
    VQDMULHslv4i16  = 2009,
2025
    VQDMULHslv4i32  = 2010,
2026
    VQDMULHslv8i16  = 2011,
2027
    VQDMULHv2i32  = 2012,
2028
    VQDMULHv4i16  = 2013,
2029
    VQDMULHv4i32  = 2014,
2030
    VQDMULHv8i16  = 2015,
2031
    VQDMULLslv2i32  = 2016,
2032
    VQDMULLslv4i16  = 2017,
2033
    VQDMULLv2i64  = 2018,
2034
    VQDMULLv4i32  = 2019,
2035
    VQMOVNsuv2i32 = 2020,
2036
    VQMOVNsuv4i16 = 2021,
2037
    VQMOVNsuv8i8  = 2022,
2038
    VQMOVNsv2i32  = 2023,
2039
    VQMOVNsv4i16  = 2024,
2040
    VQMOVNsv8i8 = 2025,
2041
    VQMOVNuv2i32  = 2026,
2042
    VQMOVNuv4i16  = 2027,
2043
    VQMOVNuv8i8 = 2028,
2044
    VQNEGv16i8  = 2029,
2045
    VQNEGv2i32  = 2030,
2046
    VQNEGv4i16  = 2031,
2047
    VQNEGv4i32  = 2032,
2048
    VQNEGv8i16  = 2033,
2049
    VQNEGv8i8 = 2034,
2050
    VQRDMLAHslv2i32 = 2035,
2051
    VQRDMLAHslv4i16 = 2036,
2052
    VQRDMLAHslv4i32 = 2037,
2053
    VQRDMLAHslv8i16 = 2038,
2054
    VQRDMLAHv2i32 = 2039,
2055
    VQRDMLAHv4i16 = 2040,
2056
    VQRDMLAHv4i32 = 2041,
2057
    VQRDMLAHv8i16 = 2042,
2058
    VQRDMLSHslv2i32 = 2043,
2059
    VQRDMLSHslv4i16 = 2044,
2060
    VQRDMLSHslv4i32 = 2045,
2061
    VQRDMLSHslv8i16 = 2046,
2062
    VQRDMLSHv2i32 = 2047,
2063
    VQRDMLSHv4i16 = 2048,
2064
    VQRDMLSHv4i32 = 2049,
2065
    VQRDMLSHv8i16 = 2050,
2066
    VQRDMULHslv2i32 = 2051,
2067
    VQRDMULHslv4i16 = 2052,
2068
    VQRDMULHslv4i32 = 2053,
2069
    VQRDMULHslv8i16 = 2054,
2070
    VQRDMULHv2i32 = 2055,
2071
    VQRDMULHv4i16 = 2056,
2072
    VQRDMULHv4i32 = 2057,
2073
    VQRDMULHv8i16 = 2058,
2074
    VQRSHLsv16i8  = 2059,
2075
    VQRSHLsv1i64  = 2060,
2076
    VQRSHLsv2i32  = 2061,
2077
    VQRSHLsv2i64  = 2062,
2078
    VQRSHLsv4i16  = 2063,
2079
    VQRSHLsv4i32  = 2064,
2080
    VQRSHLsv8i16  = 2065,
2081
    VQRSHLsv8i8 = 2066,
2082
    VQRSHLuv16i8  = 2067,
2083
    VQRSHLuv1i64  = 2068,
2084
    VQRSHLuv2i32  = 2069,
2085
    VQRSHLuv2i64  = 2070,
2086
    VQRSHLuv4i16  = 2071,
2087
    VQRSHLuv4i32  = 2072,
2088
    VQRSHLuv8i16  = 2073,
2089
    VQRSHLuv8i8 = 2074,
2090
    VQRSHRNsv2i32 = 2075,
2091
    VQRSHRNsv4i16 = 2076,
2092
    VQRSHRNsv8i8  = 2077,
2093
    VQRSHRNuv2i32 = 2078,
2094
    VQRSHRNuv4i16 = 2079,
2095
    VQRSHRNuv8i8  = 2080,
2096
    VQRSHRUNv2i32 = 2081,
2097
    VQRSHRUNv4i16 = 2082,
2098
    VQRSHRUNv8i8  = 2083,
2099
    VQSHLsiv16i8  = 2084,
2100
    VQSHLsiv1i64  = 2085,
2101
    VQSHLsiv2i32  = 2086,
2102
    VQSHLsiv2i64  = 2087,
2103
    VQSHLsiv4i16  = 2088,
2104
    VQSHLsiv4i32  = 2089,
2105
    VQSHLsiv8i16  = 2090,
2106
    VQSHLsiv8i8 = 2091,
2107
    VQSHLsuv16i8  = 2092,
2108
    VQSHLsuv1i64  = 2093,
2109
    VQSHLsuv2i32  = 2094,
2110
    VQSHLsuv2i64  = 2095,
2111
    VQSHLsuv4i16  = 2096,
2112
    VQSHLsuv4i32  = 2097,
2113
    VQSHLsuv8i16  = 2098,
2114
    VQSHLsuv8i8 = 2099,
2115
    VQSHLsv16i8 = 2100,
2116
    VQSHLsv1i64 = 2101,
2117
    VQSHLsv2i32 = 2102,
2118
    VQSHLsv2i64 = 2103,
2119
    VQSHLsv4i16 = 2104,
2120
    VQSHLsv4i32 = 2105,
2121
    VQSHLsv8i16 = 2106,
2122
    VQSHLsv8i8  = 2107,
2123
    VQSHLuiv16i8  = 2108,
2124
    VQSHLuiv1i64  = 2109,
2125
    VQSHLuiv2i32  = 2110,
2126
    VQSHLuiv2i64  = 2111,
2127
    VQSHLuiv4i16  = 2112,
2128
    VQSHLuiv4i32  = 2113,
2129
    VQSHLuiv8i16  = 2114,
2130
    VQSHLuiv8i8 = 2115,
2131
    VQSHLuv16i8 = 2116,
2132
    VQSHLuv1i64 = 2117,
2133
    VQSHLuv2i32 = 2118,
2134
    VQSHLuv2i64 = 2119,
2135
    VQSHLuv4i16 = 2120,
2136
    VQSHLuv4i32 = 2121,
2137
    VQSHLuv8i16 = 2122,
2138
    VQSHLuv8i8  = 2123,
2139
    VQSHRNsv2i32  = 2124,
2140
    VQSHRNsv4i16  = 2125,
2141
    VQSHRNsv8i8 = 2126,
2142
    VQSHRNuv2i32  = 2127,
2143
    VQSHRNuv4i16  = 2128,
2144
    VQSHRNuv8i8 = 2129,
2145
    VQSHRUNv2i32  = 2130,
2146
    VQSHRUNv4i16  = 2131,
2147
    VQSHRUNv8i8 = 2132,
2148
    VQSUBsv16i8 = 2133,
2149
    VQSUBsv1i64 = 2134,
2150
    VQSUBsv2i32 = 2135,
2151
    VQSUBsv2i64 = 2136,
2152
    VQSUBsv4i16 = 2137,
2153
    VQSUBsv4i32 = 2138,
2154
    VQSUBsv8i16 = 2139,
2155
    VQSUBsv8i8  = 2140,
2156
    VQSUBuv16i8 = 2141,
2157
    VQSUBuv1i64 = 2142,
2158
    VQSUBuv2i32 = 2143,
2159
    VQSUBuv2i64 = 2144,
2160
    VQSUBuv4i16 = 2145,
2161
    VQSUBuv4i32 = 2146,
2162
    VQSUBuv8i16 = 2147,
2163
    VQSUBuv8i8  = 2148,
2164
    VRADDHNv2i32  = 2149,
2165
    VRADDHNv4i16  = 2150,
2166
    VRADDHNv8i8 = 2151,
2167
    VRECPEd = 2152,
2168
    VRECPEfd  = 2153,
2169
    VRECPEfq  = 2154,
2170
    VRECPEhd  = 2155,
2171
    VRECPEhq  = 2156,
2172
    VRECPEq = 2157,
2173
    VRECPSfd  = 2158,
2174
    VRECPSfq  = 2159,
2175
    VRECPShd  = 2160,
2176
    VRECPShq  = 2161,
2177
    VREV16d8  = 2162,
2178
    VREV16q8  = 2163,
2179
    VREV32d16 = 2164,
2180
    VREV32d8  = 2165,
2181
    VREV32q16 = 2166,
2182
    VREV32q8  = 2167,
2183
    VREV64d16 = 2168,
2184
    VREV64d32 = 2169,
2185
    VREV64d8  = 2170,
2186
    VREV64q16 = 2171,
2187
    VREV64q32 = 2172,
2188
    VREV64q8  = 2173,
2189
    VRHADDsv16i8  = 2174,
2190
    VRHADDsv2i32  = 2175,
2191
    VRHADDsv4i16  = 2176,
2192
    VRHADDsv4i32  = 2177,
2193
    VRHADDsv8i16  = 2178,
2194
    VRHADDsv8i8 = 2179,
2195
    VRHADDuv16i8  = 2180,
2196
    VRHADDuv2i32  = 2181,
2197
    VRHADDuv4i16  = 2182,
2198
    VRHADDuv4i32  = 2183,
2199
    VRHADDuv8i16  = 2184,
2200
    VRHADDuv8i8 = 2185,
2201
    VRINTAD = 2186,
2202
    VRINTAH = 2187,
2203
    VRINTANDf = 2188,
2204
    VRINTANDh = 2189,
2205
    VRINTANQf = 2190,
2206
    VRINTANQh = 2191,
2207
    VRINTAS = 2192,
2208
    VRINTMD = 2193,
2209
    VRINTMH = 2194,
2210
    VRINTMNDf = 2195,
2211
    VRINTMNDh = 2196,
2212
    VRINTMNQf = 2197,
2213
    VRINTMNQh = 2198,
2214
    VRINTMS = 2199,
2215
    VRINTND = 2200,
2216
    VRINTNH = 2201,
2217
    VRINTNNDf = 2202,
2218
    VRINTNNDh = 2203,
2219
    VRINTNNQf = 2204,
2220
    VRINTNNQh = 2205,
2221
    VRINTNS = 2206,
2222
    VRINTPD = 2207,
2223
    VRINTPH = 2208,
2224
    VRINTPNDf = 2209,
2225
    VRINTPNDh = 2210,
2226
    VRINTPNQf = 2211,
2227
    VRINTPNQh = 2212,
2228
    VRINTPS = 2213,
2229
    VRINTRD = 2214,
2230
    VRINTRH = 2215,
2231
    VRINTRS = 2216,
2232
    VRINTXD = 2217,
2233
    VRINTXH = 2218,
2234
    VRINTXNDf = 2219,
2235
    VRINTXNDh = 2220,
2236
    VRINTXNQf = 2221,
2237
    VRINTXNQh = 2222,
2238
    VRINTXS = 2223,
2239
    VRINTZD = 2224,
2240
    VRINTZH = 2225,
2241
    VRINTZNDf = 2226,
2242
    VRINTZNDh = 2227,
2243
    VRINTZNQf = 2228,
2244
    VRINTZNQh = 2229,
2245
    VRINTZS = 2230,
2246
    VRSHLsv16i8 = 2231,
2247
    VRSHLsv1i64 = 2232,
2248
    VRSHLsv2i32 = 2233,
2249
    VRSHLsv2i64 = 2234,
2250
    VRSHLsv4i16 = 2235,
2251
    VRSHLsv4i32 = 2236,
2252
    VRSHLsv8i16 = 2237,
2253
    VRSHLsv8i8  = 2238,
2254
    VRSHLuv16i8 = 2239,
2255
    VRSHLuv1i64 = 2240,
2256
    VRSHLuv2i32 = 2241,
2257
    VRSHLuv2i64 = 2242,
2258
    VRSHLuv4i16 = 2243,
2259
    VRSHLuv4i32 = 2244,
2260
    VRSHLuv8i16 = 2245,
2261
    VRSHLuv8i8  = 2246,
2262
    VRSHRNv2i32 = 2247,
2263
    VRSHRNv4i16 = 2248,
2264
    VRSHRNv8i8  = 2249,
2265
    VRSHRsv16i8 = 2250,
2266
    VRSHRsv1i64 = 2251,
2267
    VRSHRsv2i32 = 2252,
2268
    VRSHRsv2i64 = 2253,
2269
    VRSHRsv4i16 = 2254,
2270
    VRSHRsv4i32 = 2255,
2271
    VRSHRsv8i16 = 2256,
2272
    VRSHRsv8i8  = 2257,
2273
    VRSHRuv16i8 = 2258,
2274
    VRSHRuv1i64 = 2259,
2275
    VRSHRuv2i32 = 2260,
2276
    VRSHRuv2i64 = 2261,
2277
    VRSHRuv4i16 = 2262,
2278
    VRSHRuv4i32 = 2263,
2279
    VRSHRuv8i16 = 2264,
2280
    VRSHRuv8i8  = 2265,
2281
    VRSQRTEd  = 2266,
2282
    VRSQRTEfd = 2267,
2283
    VRSQRTEfq = 2268,
2284
    VRSQRTEhd = 2269,
2285
    VRSQRTEhq = 2270,
2286
    VRSQRTEq  = 2271,
2287
    VRSQRTSfd = 2272,
2288
    VRSQRTSfq = 2273,
2289
    VRSQRTShd = 2274,
2290
    VRSQRTShq = 2275,
2291
    VRSRAsv16i8 = 2276,
2292
    VRSRAsv1i64 = 2277,
2293
    VRSRAsv2i32 = 2278,
2294
    VRSRAsv2i64 = 2279,
2295
    VRSRAsv4i16 = 2280,
2296
    VRSRAsv4i32 = 2281,
2297
    VRSRAsv8i16 = 2282,
2298
    VRSRAsv8i8  = 2283,
2299
    VRSRAuv16i8 = 2284,
2300
    VRSRAuv1i64 = 2285,
2301
    VRSRAuv2i32 = 2286,
2302
    VRSRAuv2i64 = 2287,
2303
    VRSRAuv4i16 = 2288,
2304
    VRSRAuv4i32 = 2289,
2305
    VRSRAuv8i16 = 2290,
2306
    VRSRAuv8i8  = 2291,
2307
    VRSUBHNv2i32  = 2292,
2308
    VRSUBHNv4i16  = 2293,
2309
    VRSUBHNv8i8 = 2294,
2310
    VSDOTD  = 2295,
2311
    VSDOTDI = 2296,
2312
    VSDOTQ  = 2297,
2313
    VSDOTQI = 2298,
2314
    VSELEQD = 2299,
2315
    VSELEQH = 2300,
2316
    VSELEQS = 2301,
2317
    VSELGED = 2302,
2318
    VSELGEH = 2303,
2319
    VSELGES = 2304,
2320
    VSELGTD = 2305,
2321
    VSELGTH = 2306,
2322
    VSELGTS = 2307,
2323
    VSELVSD = 2308,
2324
    VSELVSH = 2309,
2325
    VSELVSS = 2310,
2326
    VSETLNi16 = 2311,
2327
    VSETLNi32 = 2312,
2328
    VSETLNi8  = 2313,
2329
    VSHLLi16  = 2314,
2330
    VSHLLi32  = 2315,
2331
    VSHLLi8 = 2316,
2332
    VSHLLsv2i64 = 2317,
2333
    VSHLLsv4i32 = 2318,
2334
    VSHLLsv8i16 = 2319,
2335
    VSHLLuv2i64 = 2320,
2336
    VSHLLuv4i32 = 2321,
2337
    VSHLLuv8i16 = 2322,
2338
    VSHLiv16i8  = 2323,
2339
    VSHLiv1i64  = 2324,
2340
    VSHLiv2i32  = 2325,
2341
    VSHLiv2i64  = 2326,
2342
    VSHLiv4i16  = 2327,
2343
    VSHLiv4i32  = 2328,
2344
    VSHLiv8i16  = 2329,
2345
    VSHLiv8i8 = 2330,
2346
    VSHLsv16i8  = 2331,
2347
    VSHLsv1i64  = 2332,
2348
    VSHLsv2i32  = 2333,
2349
    VSHLsv2i64  = 2334,
2350
    VSHLsv4i16  = 2335,
2351
    VSHLsv4i32  = 2336,
2352
    VSHLsv8i16  = 2337,
2353
    VSHLsv8i8 = 2338,
2354
    VSHLuv16i8  = 2339,
2355
    VSHLuv1i64  = 2340,
2356
    VSHLuv2i32  = 2341,
2357
    VSHLuv2i64  = 2342,
2358
    VSHLuv4i16  = 2343,
2359
    VSHLuv4i32  = 2344,
2360
    VSHLuv8i16  = 2345,
2361
    VSHLuv8i8 = 2346,
2362
    VSHRNv2i32  = 2347,
2363
    VSHRNv4i16  = 2348,
2364
    VSHRNv8i8 = 2349,
2365
    VSHRsv16i8  = 2350,
2366
    VSHRsv1i64  = 2351,
2367
    VSHRsv2i32  = 2352,
2368
    VSHRsv2i64  = 2353,
2369
    VSHRsv4i16  = 2354,
2370
    VSHRsv4i32  = 2355,
2371
    VSHRsv8i16  = 2356,
2372
    VSHRsv8i8 = 2357,
2373
    VSHRuv16i8  = 2358,
2374
    VSHRuv1i64  = 2359,
2375
    VSHRuv2i32  = 2360,
2376
    VSHRuv2i64  = 2361,
2377
    VSHRuv4i16  = 2362,
2378
    VSHRuv4i32  = 2363,
2379
    VSHRuv8i16  = 2364,
2380
    VSHRuv8i8 = 2365,
2381
    VSHTOD  = 2366,
2382
    VSHTOH  = 2367,
2383
    VSHTOS  = 2368,
2384
    VSITOD  = 2369,
2385
    VSITOH  = 2370,
2386
    VSITOS  = 2371,
2387
    VSLIv16i8 = 2372,
2388
    VSLIv1i64 = 2373,
2389
    VSLIv2i32 = 2374,
2390
    VSLIv2i64 = 2375,
2391
    VSLIv4i16 = 2376,
2392
    VSLIv4i32 = 2377,
2393
    VSLIv8i16 = 2378,
2394
    VSLIv8i8  = 2379,
2395
    VSLTOD  = 2380,
2396
    VSLTOH  = 2381,
2397
    VSLTOS  = 2382,
2398
    VSQRTD  = 2383,
2399
    VSQRTH  = 2384,
2400
    VSQRTS  = 2385,
2401
    VSRAsv16i8  = 2386,
2402
    VSRAsv1i64  = 2387,
2403
    VSRAsv2i32  = 2388,
2404
    VSRAsv2i64  = 2389,
2405
    VSRAsv4i16  = 2390,
2406
    VSRAsv4i32  = 2391,
2407
    VSRAsv8i16  = 2392,
2408
    VSRAsv8i8 = 2393,
2409
    VSRAuv16i8  = 2394,
2410
    VSRAuv1i64  = 2395,
2411
    VSRAuv2i32  = 2396,
2412
    VSRAuv2i64  = 2397,
2413
    VSRAuv4i16  = 2398,
2414
    VSRAuv4i32  = 2399,
2415
    VSRAuv8i16  = 2400,
2416
    VSRAuv8i8 = 2401,
2417
    VSRIv16i8 = 2402,
2418
    VSRIv1i64 = 2403,
2419
    VSRIv2i32 = 2404,
2420
    VSRIv2i64 = 2405,
2421
    VSRIv4i16 = 2406,
2422
    VSRIv4i32 = 2407,
2423
    VSRIv8i16 = 2408,
2424
    VSRIv8i8  = 2409,
2425
    VST1LNd16 = 2410,
2426
    VST1LNd16_UPD = 2411,
2427
    VST1LNd32 = 2412,
2428
    VST1LNd32_UPD = 2413,
2429
    VST1LNd8  = 2414,
2430
    VST1LNd8_UPD  = 2415,
2431
    VST1LNq16Pseudo = 2416,
2432
    VST1LNq16Pseudo_UPD = 2417,
2433
    VST1LNq32Pseudo = 2418,
2434
    VST1LNq32Pseudo_UPD = 2419,
2435
    VST1LNq8Pseudo  = 2420,
2436
    VST1LNq8Pseudo_UPD  = 2421,
2437
    VST1d16 = 2422,
2438
    VST1d16Q  = 2423,
2439
    VST1d16QPseudo  = 2424,
2440
    VST1d16Qwb_fixed  = 2425,
2441
    VST1d16Qwb_register = 2426,
2442
    VST1d16T  = 2427,
2443
    VST1d16TPseudo  = 2428,
2444
    VST1d16Twb_fixed  = 2429,
2445
    VST1d16Twb_register = 2430,
2446
    VST1d16wb_fixed = 2431,
2447
    VST1d16wb_register  = 2432,
2448
    VST1d32 = 2433,
2449
    VST1d32Q  = 2434,
2450
    VST1d32QPseudo  = 2435,
2451
    VST1d32Qwb_fixed  = 2436,
2452
    VST1d32Qwb_register = 2437,
2453
    VST1d32T  = 2438,
2454
    VST1d32TPseudo  = 2439,
2455
    VST1d32Twb_fixed  = 2440,
2456
    VST1d32Twb_register = 2441,
2457
    VST1d32wb_fixed = 2442,
2458
    VST1d32wb_register  = 2443,
2459
    VST1d64 = 2444,
2460
    VST1d64Q  = 2445,
2461
    VST1d64QPseudo  = 2446,
2462
    VST1d64QPseudoWB_fixed  = 2447,
2463
    VST1d64QPseudoWB_register = 2448,
2464
    VST1d64Qwb_fixed  = 2449,
2465
    VST1d64Qwb_register = 2450,
2466
    VST1d64T  = 2451,
2467
    VST1d64TPseudo  = 2452,
2468
    VST1d64TPseudoWB_fixed  = 2453,
2469
    VST1d64TPseudoWB_register = 2454,
2470
    VST1d64Twb_fixed  = 2455,
2471
    VST1d64Twb_register = 2456,
2472
    VST1d64wb_fixed = 2457,
2473
    VST1d64wb_register  = 2458,
2474
    VST1d8  = 2459,
2475
    VST1d8Q = 2460,
2476
    VST1d8QPseudo = 2461,
2477
    VST1d8Qwb_fixed = 2462,
2478
    VST1d8Qwb_register  = 2463,
2479
    VST1d8T = 2464,
2480
    VST1d8TPseudo = 2465,
2481
    VST1d8Twb_fixed = 2466,
2482
    VST1d8Twb_register  = 2467,
2483
    VST1d8wb_fixed  = 2468,
2484
    VST1d8wb_register = 2469,
2485
    VST1q16 = 2470,
2486
    VST1q16HighQPseudo  = 2471,
2487
    VST1q16HighTPseudo  = 2472,
2488
    VST1q16LowQPseudo_UPD = 2473,
2489
    VST1q16LowTPseudo_UPD = 2474,
2490
    VST1q16wb_fixed = 2475,
2491
    VST1q16wb_register  = 2476,
2492
    VST1q32 = 2477,
2493
    VST1q32HighQPseudo  = 2478,
2494
    VST1q32HighTPseudo  = 2479,
2495
    VST1q32LowQPseudo_UPD = 2480,
2496
    VST1q32LowTPseudo_UPD = 2481,
2497
    VST1q32wb_fixed = 2482,
2498
    VST1q32wb_register  = 2483,
2499
    VST1q64 = 2484,
2500
    VST1q64HighQPseudo  = 2485,
2501
    VST1q64HighTPseudo  = 2486,
2502
    VST1q64LowQPseudo_UPD = 2487,
2503
    VST1q64LowTPseudo_UPD = 2488,
2504
    VST1q64wb_fixed = 2489,
2505
    VST1q64wb_register  = 2490,
2506
    VST1q8  = 2491,
2507
    VST1q8HighQPseudo = 2492,
2508
    VST1q8HighTPseudo = 2493,
2509
    VST1q8LowQPseudo_UPD  = 2494,
2510
    VST1q8LowTPseudo_UPD  = 2495,
2511
    VST1q8wb_fixed  = 2496,
2512
    VST1q8wb_register = 2497,
2513
    VST2LNd16 = 2498,
2514
    VST2LNd16Pseudo = 2499,
2515
    VST2LNd16Pseudo_UPD = 2500,
2516
    VST2LNd16_UPD = 2501,
2517
    VST2LNd32 = 2502,
2518
    VST2LNd32Pseudo = 2503,
2519
    VST2LNd32Pseudo_UPD = 2504,
2520
    VST2LNd32_UPD = 2505,
2521
    VST2LNd8  = 2506,
2522
    VST2LNd8Pseudo  = 2507,
2523
    VST2LNd8Pseudo_UPD  = 2508,
2524
    VST2LNd8_UPD  = 2509,
2525
    VST2LNq16 = 2510,
2526
    VST2LNq16Pseudo = 2511,
2527
    VST2LNq16Pseudo_UPD = 2512,
2528
    VST2LNq16_UPD = 2513,
2529
    VST2LNq32 = 2514,
2530
    VST2LNq32Pseudo = 2515,
2531
    VST2LNq32Pseudo_UPD = 2516,
2532
    VST2LNq32_UPD = 2517,
2533
    VST2b16 = 2518,
2534
    VST2b16wb_fixed = 2519,
2535
    VST2b16wb_register  = 2520,
2536
    VST2b32 = 2521,
2537
    VST2b32wb_fixed = 2522,
2538
    VST2b32wb_register  = 2523,
2539
    VST2b8  = 2524,
2540
    VST2b8wb_fixed  = 2525,
2541
    VST2b8wb_register = 2526,
2542
    VST2d16 = 2527,
2543
    VST2d16wb_fixed = 2528,
2544
    VST2d16wb_register  = 2529,
2545
    VST2d32 = 2530,
2546
    VST2d32wb_fixed = 2531,
2547
    VST2d32wb_register  = 2532,
2548
    VST2d8  = 2533,
2549
    VST2d8wb_fixed  = 2534,
2550
    VST2d8wb_register = 2535,
2551
    VST2q16 = 2536,
2552
    VST2q16Pseudo = 2537,
2553
    VST2q16PseudoWB_fixed = 2538,
2554
    VST2q16PseudoWB_register  = 2539,
2555
    VST2q16wb_fixed = 2540,
2556
    VST2q16wb_register  = 2541,
2557
    VST2q32 = 2542,
2558
    VST2q32Pseudo = 2543,
2559
    VST2q32PseudoWB_fixed = 2544,
2560
    VST2q32PseudoWB_register  = 2545,
2561
    VST2q32wb_fixed = 2546,
2562
    VST2q32wb_register  = 2547,
2563
    VST2q8  = 2548,
2564
    VST2q8Pseudo  = 2549,
2565
    VST2q8PseudoWB_fixed  = 2550,
2566
    VST2q8PseudoWB_register = 2551,
2567
    VST2q8wb_fixed  = 2552,
2568
    VST2q8wb_register = 2553,
2569
    VST3LNd16 = 2554,
2570
    VST3LNd16Pseudo = 2555,
2571
    VST3LNd16Pseudo_UPD = 2556,
2572
    VST3LNd16_UPD = 2557,
2573
    VST3LNd32 = 2558,
2574
    VST3LNd32Pseudo = 2559,
2575
    VST3LNd32Pseudo_UPD = 2560,
2576
    VST3LNd32_UPD = 2561,
2577
    VST3LNd8  = 2562,
2578
    VST3LNd8Pseudo  = 2563,
2579
    VST3LNd8Pseudo_UPD  = 2564,
2580
    VST3LNd8_UPD  = 2565,
2581
    VST3LNq16 = 2566,
2582
    VST3LNq16Pseudo = 2567,
2583
    VST3LNq16Pseudo_UPD = 2568,
2584
    VST3LNq16_UPD = 2569,
2585
    VST3LNq32 = 2570,
2586
    VST3LNq32Pseudo = 2571,
2587
    VST3LNq32Pseudo_UPD = 2572,
2588
    VST3LNq32_UPD = 2573,
2589
    VST3d16 = 2574,
2590
    VST3d16Pseudo = 2575,
2591
    VST3d16Pseudo_UPD = 2576,
2592
    VST3d16_UPD = 2577,
2593
    VST3d32 = 2578,
2594
    VST3d32Pseudo = 2579,
2595
    VST3d32Pseudo_UPD = 2580,
2596
    VST3d32_UPD = 2581,
2597
    VST3d8  = 2582,
2598
    VST3d8Pseudo  = 2583,
2599
    VST3d8Pseudo_UPD  = 2584,
2600
    VST3d8_UPD  = 2585,
2601
    VST3q16 = 2586,
2602
    VST3q16Pseudo_UPD = 2587,
2603
    VST3q16_UPD = 2588,
2604
    VST3q16oddPseudo  = 2589,
2605
    VST3q16oddPseudo_UPD  = 2590,
2606
    VST3q32 = 2591,
2607
    VST3q32Pseudo_UPD = 2592,
2608
    VST3q32_UPD = 2593,
2609
    VST3q32oddPseudo  = 2594,
2610
    VST3q32oddPseudo_UPD  = 2595,
2611
    VST3q8  = 2596,
2612
    VST3q8Pseudo_UPD  = 2597,
2613
    VST3q8_UPD  = 2598,
2614
    VST3q8oddPseudo = 2599,
2615
    VST3q8oddPseudo_UPD = 2600,
2616
    VST4LNd16 = 2601,
2617
    VST4LNd16Pseudo = 2602,
2618
    VST4LNd16Pseudo_UPD = 2603,
2619
    VST4LNd16_UPD = 2604,
2620
    VST4LNd32 = 2605,
2621
    VST4LNd32Pseudo = 2606,
2622
    VST4LNd32Pseudo_UPD = 2607,
2623
    VST4LNd32_UPD = 2608,
2624
    VST4LNd8  = 2609,
2625
    VST4LNd8Pseudo  = 2610,
2626
    VST4LNd8Pseudo_UPD  = 2611,
2627
    VST4LNd8_UPD  = 2612,
2628
    VST4LNq16 = 2613,
2629
    VST4LNq16Pseudo = 2614,
2630
    VST4LNq16Pseudo_UPD = 2615,
2631
    VST4LNq16_UPD = 2616,
2632
    VST4LNq32 = 2617,
2633
    VST4LNq32Pseudo = 2618,
2634
    VST4LNq32Pseudo_UPD = 2619,
2635
    VST4LNq32_UPD = 2620,
2636
    VST4d16 = 2621,
2637
    VST4d16Pseudo = 2622,
2638
    VST4d16Pseudo_UPD = 2623,
2639
    VST4d16_UPD = 2624,
2640
    VST4d32 = 2625,
2641
    VST4d32Pseudo = 2626,
2642
    VST4d32Pseudo_UPD = 2627,
2643
    VST4d32_UPD = 2628,
2644
    VST4d8  = 2629,
2645
    VST4d8Pseudo  = 2630,
2646
    VST4d8Pseudo_UPD  = 2631,
2647
    VST4d8_UPD  = 2632,
2648
    VST4q16 = 2633,
2649
    VST4q16Pseudo_UPD = 2634,
2650
    VST4q16_UPD = 2635,
2651
    VST4q16oddPseudo  = 2636,
2652
    VST4q16oddPseudo_UPD  = 2637,
2653
    VST4q32 = 2638,
2654
    VST4q32Pseudo_UPD = 2639,
2655
    VST4q32_UPD = 2640,
2656
    VST4q32oddPseudo  = 2641,
2657
    VST4q32oddPseudo_UPD  = 2642,
2658
    VST4q8  = 2643,
2659
    VST4q8Pseudo_UPD  = 2644,
2660
    VST4q8_UPD  = 2645,
2661
    VST4q8oddPseudo = 2646,
2662
    VST4q8oddPseudo_UPD = 2647,
2663
    VSTMDDB_UPD = 2648,
2664
    VSTMDIA = 2649,
2665
    VSTMDIA_UPD = 2650,
2666
    VSTMQIA = 2651,
2667
    VSTMSDB_UPD = 2652,
2668
    VSTMSIA = 2653,
2669
    VSTMSIA_UPD = 2654,
2670
    VSTRD = 2655,
2671
    VSTRH = 2656,
2672
    VSTRS = 2657,
2673
    VSUBD = 2658,
2674
    VSUBH = 2659,
2675
    VSUBHNv2i32 = 2660,
2676
    VSUBHNv4i16 = 2661,
2677
    VSUBHNv8i8  = 2662,
2678
    VSUBLsv2i64 = 2663,
2679
    VSUBLsv4i32 = 2664,
2680
    VSUBLsv8i16 = 2665,
2681
    VSUBLuv2i64 = 2666,
2682
    VSUBLuv4i32 = 2667,
2683
    VSUBLuv8i16 = 2668,
2684
    VSUBS = 2669,
2685
    VSUBWsv2i64 = 2670,
2686
    VSUBWsv4i32 = 2671,
2687
    VSUBWsv8i16 = 2672,
2688
    VSUBWuv2i64 = 2673,
2689
    VSUBWuv4i32 = 2674,
2690
    VSUBWuv8i16 = 2675,
2691
    VSUBfd  = 2676,
2692
    VSUBfq  = 2677,
2693
    VSUBhd  = 2678,
2694
    VSUBhq  = 2679,
2695
    VSUBv16i8 = 2680,
2696
    VSUBv1i64 = 2681,
2697
    VSUBv2i32 = 2682,
2698
    VSUBv2i64 = 2683,
2699
    VSUBv4i16 = 2684,
2700
    VSUBv4i32 = 2685,
2701
    VSUBv8i16 = 2686,
2702
    VSUBv8i8  = 2687,
2703
    VSWPd = 2688,
2704
    VSWPq = 2689,
2705
    VTBL1 = 2690,
2706
    VTBL2 = 2691,
2707
    VTBL3 = 2692,
2708
    VTBL3Pseudo = 2693,
2709
    VTBL4 = 2694,
2710
    VTBL4Pseudo = 2695,
2711
    VTBX1 = 2696,
2712
    VTBX2 = 2697,
2713
    VTBX3 = 2698,
2714
    VTBX3Pseudo = 2699,
2715
    VTBX4 = 2700,
2716
    VTBX4Pseudo = 2701,
2717
    VTOSHD  = 2702,
2718
    VTOSHH  = 2703,
2719
    VTOSHS  = 2704,
2720
    VTOSIRD = 2705,
2721
    VTOSIRH = 2706,
2722
    VTOSIRS = 2707,
2723
    VTOSIZD = 2708,
2724
    VTOSIZH = 2709,
2725
    VTOSIZS = 2710,
2726
    VTOSLD  = 2711,
2727
    VTOSLH  = 2712,
2728
    VTOSLS  = 2713,
2729
    VTOUHD  = 2714,
2730
    VTOUHH  = 2715,
2731
    VTOUHS  = 2716,
2732
    VTOUIRD = 2717,
2733
    VTOUIRH = 2718,
2734
    VTOUIRS = 2719,
2735
    VTOUIZD = 2720,
2736
    VTOUIZH = 2721,
2737
    VTOUIZS = 2722,
2738
    VTOULD  = 2723,
2739
    VTOULH  = 2724,
2740
    VTOULS  = 2725,
2741
    VTRNd16 = 2726,
2742
    VTRNd32 = 2727,
2743
    VTRNd8  = 2728,
2744
    VTRNq16 = 2729,
2745
    VTRNq32 = 2730,
2746
    VTRNq8  = 2731,
2747
    VTSTv16i8 = 2732,
2748
    VTSTv2i32 = 2733,
2749
    VTSTv4i16 = 2734,
2750
    VTSTv4i32 = 2735,
2751
    VTSTv8i16 = 2736,
2752
    VTSTv8i8  = 2737,
2753
    VUDOTD  = 2738,
2754
    VUDOTDI = 2739,
2755
    VUDOTQ  = 2740,
2756
    VUDOTQI = 2741,
2757
    VUHTOD  = 2742,
2758
    VUHTOH  = 2743,
2759
    VUHTOS  = 2744,
2760
    VUITOD  = 2745,
2761
    VUITOH  = 2746,
2762
    VUITOS  = 2747,
2763
    VULTOD  = 2748,
2764
    VULTOH  = 2749,
2765
    VULTOS  = 2750,
2766
    VUZPd16 = 2751,
2767
    VUZPd8  = 2752,
2768
    VUZPq16 = 2753,
2769
    VUZPq32 = 2754,
2770
    VUZPq8  = 2755,
2771
    VZIPd16 = 2756,
2772
    VZIPd8  = 2757,
2773
    VZIPq16 = 2758,
2774
    VZIPq32 = 2759,
2775
    VZIPq8  = 2760,
2776
    sysLDMDA  = 2761,
2777
    sysLDMDA_UPD  = 2762,
2778
    sysLDMDB  = 2763,
2779
    sysLDMDB_UPD  = 2764,
2780
    sysLDMIA  = 2765,
2781
    sysLDMIA_UPD  = 2766,
2782
    sysLDMIB  = 2767,
2783
    sysLDMIB_UPD  = 2768,
2784
    sysSTMDA  = 2769,
2785
    sysSTMDA_UPD  = 2770,
2786
    sysSTMDB  = 2771,
2787
    sysSTMDB_UPD  = 2772,
2788
    sysSTMIA  = 2773,
2789
    sysSTMIA_UPD  = 2774,
2790
    sysSTMIB  = 2775,
2791
    sysSTMIB_UPD  = 2776,
2792
    t2ADCri = 2777,
2793
    t2ADCrr = 2778,
2794
    t2ADCrs = 2779,
2795
    t2ADDri = 2780,
2796
    t2ADDri12 = 2781,
2797
    t2ADDrr = 2782,
2798
    t2ADDrs = 2783,
2799
    t2ADR = 2784,
2800
    t2ANDri = 2785,
2801
    t2ANDrr = 2786,
2802
    t2ANDrs = 2787,
2803
    t2ASRri = 2788,
2804
    t2ASRrr = 2789,
2805
    t2B = 2790,
2806
    t2BFC = 2791,
2807
    t2BFI = 2792,
2808
    t2BICri = 2793,
2809
    t2BICrr = 2794,
2810
    t2BICrs = 2795,
2811
    t2BXJ = 2796,
2812
    t2Bcc = 2797,
2813
    t2CDP = 2798,
2814
    t2CDP2  = 2799,
2815
    t2CLREX = 2800,
2816
    t2CLZ = 2801,
2817
    t2CMNri = 2802,
2818
    t2CMNzrr  = 2803,
2819
    t2CMNzrs  = 2804,
2820
    t2CMPri = 2805,
2821
    t2CMPrr = 2806,
2822
    t2CMPrs = 2807,
2823
    t2CPS1p = 2808,
2824
    t2CPS2p = 2809,
2825
    t2CPS3p = 2810,
2826
    t2CRC32B  = 2811,
2827
    t2CRC32CB = 2812,
2828
    t2CRC32CH = 2813,
2829
    t2CRC32CW = 2814,
2830
    t2CRC32H  = 2815,
2831
    t2CRC32W  = 2816,
2832
    t2DBG = 2817,
2833
    t2DCPS1 = 2818,
2834
    t2DCPS2 = 2819,
2835
    t2DCPS3 = 2820,
2836
    t2DMB = 2821,
2837
    t2DSB = 2822,
2838
    t2EORri = 2823,
2839
    t2EORrr = 2824,
2840
    t2EORrs = 2825,
2841
    t2HINT  = 2826,
2842
    t2HVC = 2827,
2843
    t2ISB = 2828,
2844
    t2IT  = 2829,
2845
    t2Int_eh_sjlj_setjmp  = 2830,
2846
    t2Int_eh_sjlj_setjmp_nofp = 2831,
2847
    t2LDA = 2832,
2848
    t2LDAB  = 2833,
2849
    t2LDAEX = 2834,
2850
    t2LDAEXB  = 2835,
2851
    t2LDAEXD  = 2836,
2852
    t2LDAEXH  = 2837,
2853
    t2LDAH  = 2838,
2854
    t2LDC2L_OFFSET  = 2839,
2855
    t2LDC2L_OPTION  = 2840,
2856
    t2LDC2L_POST  = 2841,
2857
    t2LDC2L_PRE = 2842,
2858
    t2LDC2_OFFSET = 2843,
2859
    t2LDC2_OPTION = 2844,
2860
    t2LDC2_POST = 2845,
2861
    t2LDC2_PRE  = 2846,
2862
    t2LDCL_OFFSET = 2847,
2863
    t2LDCL_OPTION = 2848,
2864
    t2LDCL_POST = 2849,
2865
    t2LDCL_PRE  = 2850,
2866
    t2LDC_OFFSET  = 2851,
2867
    t2LDC_OPTION  = 2852,
2868
    t2LDC_POST  = 2853,
2869
    t2LDC_PRE = 2854,
2870
    t2LDMDB = 2855,
2871
    t2LDMDB_UPD = 2856,
2872
    t2LDMIA = 2857,
2873
    t2LDMIA_UPD = 2858,
2874
    t2LDRBT = 2859,
2875
    t2LDRB_POST = 2860,
2876
    t2LDRB_PRE  = 2861,
2877
    t2LDRBi12 = 2862,
2878
    t2LDRBi8  = 2863,
2879
    t2LDRBpci = 2864,
2880
    t2LDRBs = 2865,
2881
    t2LDRD_POST = 2866,
2882
    t2LDRD_PRE  = 2867,
2883
    t2LDRDi8  = 2868,
2884
    t2LDREX = 2869,
2885
    t2LDREXB  = 2870,
2886
    t2LDREXD  = 2871,
2887
    t2LDREXH  = 2872,
2888
    t2LDRHT = 2873,
2889
    t2LDRH_POST = 2874,
2890
    t2LDRH_PRE  = 2875,
2891
    t2LDRHi12 = 2876,
2892
    t2LDRHi8  = 2877,
2893
    t2LDRHpci = 2878,
2894
    t2LDRHs = 2879,
2895
    t2LDRSBT  = 2880,
2896
    t2LDRSB_POST  = 2881,
2897
    t2LDRSB_PRE = 2882,
2898
    t2LDRSBi12  = 2883,
2899
    t2LDRSBi8 = 2884,
2900
    t2LDRSBpci  = 2885,
2901
    t2LDRSBs  = 2886,
2902
    t2LDRSHT  = 2887,
2903
    t2LDRSH_POST  = 2888,
2904
    t2LDRSH_PRE = 2889,
2905
    t2LDRSHi12  = 2890,
2906
    t2LDRSHi8 = 2891,
2907
    t2LDRSHpci  = 2892,
2908
    t2LDRSHs  = 2893,
2909
    t2LDRT  = 2894,
2910
    t2LDR_POST  = 2895,
2911
    t2LDR_PRE = 2896,
2912
    t2LDRi12  = 2897,
2913
    t2LDRi8 = 2898,
2914
    t2LDRpci  = 2899,
2915
    t2LDRs  = 2900,
2916
    t2LSLri = 2901,
2917
    t2LSLrr = 2902,
2918
    t2LSRri = 2903,
2919
    t2LSRrr = 2904,
2920
    t2MCR = 2905,
2921
    t2MCR2  = 2906,
2922
    t2MCRR  = 2907,
2923
    t2MCRR2 = 2908,
2924
    t2MLA = 2909,
2925
    t2MLS = 2910,
2926
    t2MOVTi16 = 2911,
2927
    t2MOVi  = 2912,
2928
    t2MOVi16  = 2913,
2929
    t2MOVr  = 2914,
2930
    t2MOVsra_flag = 2915,
2931
    t2MOVsrl_flag = 2916,
2932
    t2MRC = 2917,
2933
    t2MRC2  = 2918,
2934
    t2MRRC  = 2919,
2935
    t2MRRC2 = 2920,
2936
    t2MRS_AR  = 2921,
2937
    t2MRS_M = 2922,
2938
    t2MRSbanked = 2923,
2939
    t2MRSsys_AR = 2924,
2940
    t2MSR_AR  = 2925,
2941
    t2MSR_M = 2926,
2942
    t2MSRbanked = 2927,
2943
    t2MUL = 2928,
2944
    t2MVNi  = 2929,
2945
    t2MVNr  = 2930,
2946
    t2MVNs  = 2931,
2947
    t2ORNri = 2932,
2948
    t2ORNrr = 2933,
2949
    t2ORNrs = 2934,
2950
    t2ORRri = 2935,
2951
    t2ORRrr = 2936,
2952
    t2ORRrs = 2937,
2953
    t2PKHBT = 2938,
2954
    t2PKHTB = 2939,
2955
    t2PLDWi12 = 2940,
2956
    t2PLDWi8  = 2941,
2957
    t2PLDWs = 2942,
2958
    t2PLDi12  = 2943,
2959
    t2PLDi8 = 2944,
2960
    t2PLDpci  = 2945,
2961
    t2PLDs  = 2946,
2962
    t2PLIi12  = 2947,
2963
    t2PLIi8 = 2948,
2964
    t2PLIpci  = 2949,
2965
    t2PLIs  = 2950,
2966
    t2QADD  = 2951,
2967
    t2QADD16  = 2952,
2968
    t2QADD8 = 2953,
2969
    t2QASX  = 2954,
2970
    t2QDADD = 2955,
2971
    t2QDSUB = 2956,
2972
    t2QSAX  = 2957,
2973
    t2QSUB  = 2958,
2974
    t2QSUB16  = 2959,
2975
    t2QSUB8 = 2960,
2976
    t2RBIT  = 2961,
2977
    t2REV = 2962,
2978
    t2REV16 = 2963,
2979
    t2REVSH = 2964,
2980
    t2RFEDB = 2965,
2981
    t2RFEDBW  = 2966,
2982
    t2RFEIA = 2967,
2983
    t2RFEIAW  = 2968,
2984
    t2RORri = 2969,
2985
    t2RORrr = 2970,
2986
    t2RRX = 2971,
2987
    t2RSBri = 2972,
2988
    t2RSBrr = 2973,
2989
    t2RSBrs = 2974,
2990
    t2SADD16  = 2975,
2991
    t2SADD8 = 2976,
2992
    t2SASX  = 2977,
2993
    t2SBCri = 2978,
2994
    t2SBCrr = 2979,
2995
    t2SBCrs = 2980,
2996
    t2SBFX  = 2981,
2997
    t2SDIV  = 2982,
2998
    t2SEL = 2983,
2999
    t2SETPAN  = 2984,
3000
    t2SG  = 2985,
3001
    t2SHADD16 = 2986,
3002
    t2SHADD8  = 2987,
3003
    t2SHASX = 2988,
3004
    t2SHSAX = 2989,
3005
    t2SHSUB16 = 2990,
3006
    t2SHSUB8  = 2991,
3007
    t2SMC = 2992,
3008
    t2SMLABB  = 2993,
3009
    t2SMLABT  = 2994,
3010
    t2SMLAD = 2995,
3011
    t2SMLADX  = 2996,
3012
    t2SMLAL = 2997,
3013
    t2SMLALBB = 2998,
3014
    t2SMLALBT = 2999,
3015
    t2SMLALD  = 3000,
3016
    t2SMLALDX = 3001,
3017
    t2SMLALTB = 3002,
3018
    t2SMLALTT = 3003,
3019
    t2SMLATB  = 3004,
3020
    t2SMLATT  = 3005,
3021
    t2SMLAWB  = 3006,
3022
    t2SMLAWT  = 3007,
3023
    t2SMLSD = 3008,
3024
    t2SMLSDX  = 3009,
3025
    t2SMLSLD  = 3010,
3026
    t2SMLSLDX = 3011,
3027
    t2SMMLA = 3012,
3028
    t2SMMLAR  = 3013,
3029
    t2SMMLS = 3014,
3030
    t2SMMLSR  = 3015,
3031
    t2SMMUL = 3016,
3032
    t2SMMULR  = 3017,
3033
    t2SMUAD = 3018,
3034
    t2SMUADX  = 3019,
3035
    t2SMULBB  = 3020,
3036
    t2SMULBT  = 3021,
3037
    t2SMULL = 3022,
3038
    t2SMULTB  = 3023,
3039
    t2SMULTT  = 3024,
3040
    t2SMULWB  = 3025,
3041
    t2SMULWT  = 3026,
3042
    t2SMUSD = 3027,
3043
    t2SMUSDX  = 3028,
3044
    t2SRSDB = 3029,
3045
    t2SRSDB_UPD = 3030,
3046
    t2SRSIA = 3031,
3047
    t2SRSIA_UPD = 3032,
3048
    t2SSAT  = 3033,
3049
    t2SSAT16  = 3034,
3050
    t2SSAX  = 3035,
3051
    t2SSUB16  = 3036,
3052
    t2SSUB8 = 3037,
3053
    t2STC2L_OFFSET  = 3038,
3054
    t2STC2L_OPTION  = 3039,
3055
    t2STC2L_POST  = 3040,
3056
    t2STC2L_PRE = 3041,
3057
    t2STC2_OFFSET = 3042,
3058
    t2STC2_OPTION = 3043,
3059
    t2STC2_POST = 3044,
3060
    t2STC2_PRE  = 3045,
3061
    t2STCL_OFFSET = 3046,
3062
    t2STCL_OPTION = 3047,
3063
    t2STCL_POST = 3048,
3064
    t2STCL_PRE  = 3049,
3065
    t2STC_OFFSET  = 3050,
3066
    t2STC_OPTION  = 3051,
3067
    t2STC_POST  = 3052,
3068
    t2STC_PRE = 3053,
3069
    t2STL = 3054,
3070
    t2STLB  = 3055,
3071
    t2STLEX = 3056,
3072
    t2STLEXB  = 3057,
3073
    t2STLEXD  = 3058,
3074
    t2STLEXH  = 3059,
3075
    t2STLH  = 3060,
3076
    t2STMDB = 3061,
3077
    t2STMDB_UPD = 3062,
3078
    t2STMIA = 3063,
3079
    t2STMIA_UPD = 3064,
3080
    t2STRBT = 3065,
3081
    t2STRB_POST = 3066,
3082
    t2STRB_PRE  = 3067,
3083
    t2STRBi12 = 3068,
3084
    t2STRBi8  = 3069,
3085
    t2STRBs = 3070,
3086
    t2STRD_POST = 3071,
3087
    t2STRD_PRE  = 3072,
3088
    t2STRDi8  = 3073,
3089
    t2STREX = 3074,
3090
    t2STREXB  = 3075,
3091
    t2STREXD  = 3076,
3092
    t2STREXH  = 3077,
3093
    t2STRHT = 3078,
3094
    t2STRH_POST = 3079,
3095
    t2STRH_PRE  = 3080,
3096
    t2STRHi12 = 3081,
3097
    t2STRHi8  = 3082,
3098
    t2STRHs = 3083,
3099
    t2STRT  = 3084,
3100
    t2STR_POST  = 3085,
3101
    t2STR_PRE = 3086,
3102
    t2STRi12  = 3087,
3103
    t2STRi8 = 3088,
3104
    t2STRs  = 3089,
3105
    t2SUBS_PC_LR  = 3090,
3106
    t2SUBri = 3091,
3107
    t2SUBri12 = 3092,
3108
    t2SUBrr = 3093,
3109
    t2SUBrs = 3094,
3110
    t2SXTAB = 3095,
3111
    t2SXTAB16 = 3096,
3112
    t2SXTAH = 3097,
3113
    t2SXTB  = 3098,
3114
    t2SXTB16  = 3099,
3115
    t2SXTH  = 3100,
3116
    t2TBB = 3101,
3117
    t2TBH = 3102,
3118
    t2TEQri = 3103,
3119
    t2TEQrr = 3104,
3120
    t2TEQrs = 3105,
3121
    t2TSB = 3106,
3122
    t2TSTri = 3107,
3123
    t2TSTrr = 3108,
3124
    t2TSTrs = 3109,
3125
    t2TT  = 3110,
3126
    t2TTA = 3111,
3127
    t2TTAT  = 3112,
3128
    t2TTT = 3113,
3129
    t2UADD16  = 3114,
3130
    t2UADD8 = 3115,
3131
    t2UASX  = 3116,
3132
    t2UBFX  = 3117,
3133
    t2UDF = 3118,
3134
    t2UDIV  = 3119,
3135
    t2UHADD16 = 3120,
3136
    t2UHADD8  = 3121,
3137
    t2UHASX = 3122,
3138
    t2UHSAX = 3123,
3139
    t2UHSUB16 = 3124,
3140
    t2UHSUB8  = 3125,
3141
    t2UMAAL = 3126,
3142
    t2UMLAL = 3127,
3143
    t2UMULL = 3128,
3144
    t2UQADD16 = 3129,
3145
    t2UQADD8  = 3130,
3146
    t2UQASX = 3131,
3147
    t2UQSAX = 3132,
3148
    t2UQSUB16 = 3133,
3149
    t2UQSUB8  = 3134,
3150
    t2USAD8 = 3135,
3151
    t2USADA8  = 3136,
3152
    t2USAT  = 3137,
3153
    t2USAT16  = 3138,
3154
    t2USAX  = 3139,
3155
    t2USUB16  = 3140,
3156
    t2USUB8 = 3141,
3157
    t2UXTAB = 3142,
3158
    t2UXTAB16 = 3143,
3159
    t2UXTAH = 3144,
3160
    t2UXTB  = 3145,
3161
    t2UXTB16  = 3146,
3162
    t2UXTH  = 3147,
3163
    tADC  = 3148,
3164
    tADDhirr  = 3149,
3165
    tADDi3  = 3150,
3166
    tADDi8  = 3151,
3167
    tADDrSP = 3152,
3168
    tADDrSPi  = 3153,
3169
    tADDrr  = 3154,
3170
    tADDspi = 3155,
3171
    tADDspr = 3156,
3172
    tADR  = 3157,
3173
    tAND  = 3158,
3174
    tASRri  = 3159,
3175
    tASRrr  = 3160,
3176
    tB  = 3161,
3177
    tBIC  = 3162,
3178
    tBKPT = 3163,
3179
    tBL = 3164,
3180
    tBLXNSr = 3165,
3181
    tBLXi = 3166,
3182
    tBLXr = 3167,
3183
    tBX = 3168,
3184
    tBXNS = 3169,
3185
    tBcc  = 3170,
3186
    tCBNZ = 3171,
3187
    tCBZ  = 3172,
3188
    tCMNz = 3173,
3189
    tCMPhir = 3174,
3190
    tCMPi8  = 3175,
3191
    tCMPr = 3176,
3192
    tCPS  = 3177,
3193
    tEOR  = 3178,
3194
    tHINT = 3179,
3195
    tHLT  = 3180,
3196
    tInt_WIN_eh_sjlj_longjmp  = 3181,
3197
    tInt_eh_sjlj_longjmp  = 3182,
3198
    tInt_eh_sjlj_setjmp = 3183,
3199
    tLDMIA  = 3184,
3200
    tLDRBi  = 3185,
3201
    tLDRBr  = 3186,
3202
    tLDRHi  = 3187,
3203
    tLDRHr  = 3188,
3204
    tLDRSB  = 3189,
3205
    tLDRSH  = 3190,
3206
    tLDRi = 3191,
3207
    tLDRpci = 3192,
3208
    tLDRr = 3193,
3209
    tLDRspi = 3194,
3210
    tLSLri  = 3195,
3211
    tLSLrr  = 3196,
3212
    tLSRri  = 3197,
3213
    tLSRrr  = 3198,
3214
    tMOVSr  = 3199,
3215
    tMOVi8  = 3200,
3216
    tMOVr = 3201,
3217
    tMUL  = 3202,
3218
    tMVN  = 3203,
3219
    tORR  = 3204,
3220
    tPICADD = 3205,
3221
    tPOP  = 3206,
3222
    tPUSH = 3207,
3223
    tREV  = 3208,
3224
    tREV16  = 3209,
3225
    tREVSH  = 3210,
3226
    tROR  = 3211,
3227
    tRSB  = 3212,
3228
    tSBC  = 3213,
3229
    tSETEND = 3214,
3230
    tSTMIA_UPD  = 3215,
3231
    tSTRBi  = 3216,
3232
    tSTRBr  = 3217,
3233
    tSTRHi  = 3218,
3234
    tSTRHr  = 3219,
3235
    tSTRi = 3220,
3236
    tSTRr = 3221,
3237
    tSTRspi = 3222,
3238
    tSUBi3  = 3223,
3239
    tSUBi8  = 3224,
3240
    tSUBrr  = 3225,
3241
    tSUBspi = 3226,
3242
    tSVC  = 3227,
3243
    tSXTB = 3228,
3244
    tSXTH = 3229,
3245
    tTRAP = 3230,
3246
    tTST  = 3231,
3247
    tUDF  = 3232,
3248
    tUXTB = 3233,
3249
    tUXTH = 3234,
3250
    t__brkdiv0  = 3235,
3251
    INSTRUCTION_LIST_END = 3236
3252
  };
3253
3254
} // end ARM namespace
3255
} // end llvm namespace
3256
#endif // GET_INSTRINFO_ENUM
3257
3258
#ifdef GET_INSTRINFO_SCHED_ENUM
3259
#undef GET_INSTRINFO_SCHED_ENUM
3260
namespace llvm {
3261
3262
namespace ARM {
3263
namespace Sched {
3264
  enum {
3265
    NoInstrModel  = 0,
3266
    IIC_iALUi_WriteALU_ReadALU  = 1,
3267
    IIC_iALUr_WriteALU_ReadALU_ReadALU  = 2,
3268
    IIC_iALUsr_WriteALUsi_ReadALU = 3,
3269
    IIC_iALUsr_WriteALUSsr_ReadALUsr  = 4,
3270
    IIC_Br_WriteBr  = 5,
3271
    IIC_Br_WriteBrTbl = 6,
3272
    IIC_iLoad_mBr = 7,
3273
    IIC_iLoad_i = 8,
3274
    IIC_iLoadiALU = 9,
3275
    IIC_iMAC32_WriteMAC32_ReadMUL_ReadMUL_ReadMAC = 10,
3276
    IIC_iCMOVi_WriteALU = 11,
3277
    IIC_iMOVi_WriteALU  = 12,
3278
    IIC_iCMOVix2  = 13,
3279
    IIC_iCMOVr_WriteALU = 14,
3280
    IIC_iCMOVsr_WriteALU  = 15,
3281
    IIC_iMOVix2addpc  = 16,
3282
    IIC_iMOVix2ld = 17,
3283
    IIC_iMOVix2 = 18,
3284
    IIC_iMOVsi_WriteALU = 19,
3285
    IIC_iMUL32_WriteMUL32_ReadMUL_ReadMUL = 20,
3286
    IIC_iALUr_WriteALU_ReadALU  = 21,
3287
    IIC_iLoad_r = 22,
3288
    IIC_iLoad_bh_r  = 23,
3289
    IIC_iStore_r  = 24,
3290
    IIC_iStore_bh_r = 25,
3291
    IIC_iMAC64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC  = 26,
3292
    IIC_iMUL64_WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL  = 27,
3293
    IIC_iStore_ru = 28,
3294
    IIC_Br  = 29,
3295
    IIC_VMOVImm = 30,
3296
    IIC_fpUNA64 = 31,
3297
    IIC_fpUNA32 = 32,
3298
    IIC_iALUsi_WriteALUsi_ReadALUsr = 33,
3299
    IIC_iCMOVsi_WriteALU  = 34,
3300
    IIC_iALUsi_WriteALUsi_ReadALU = 35,
3301
    IIC_iStore_ru_WriteST = 36,
3302
    IIC_iALUr_WriteALU  = 37,
3303
    IIC_iALUi_WriteALU  = 38,
3304
    IIC_iLoad_mu  = 39,
3305
    IIC_iPop_Br_WriteBrL  = 40,
3306
    IIC_iALUsr_WriteALUsr_ReadALUsr = 41,
3307
    IIC_iBITi_WriteALU_ReadALU  = 42,
3308
    IIC_iBITr_WriteALU_ReadALU_ReadALU  = 43,
3309
    IIC_iBITsr_WriteALUsi_ReadALU = 44,
3310
    IIC_iBITsr_WriteALUsr_ReadALUsr = 45,
3311
    IIC_iUNAsi  = 46,
3312
    IIC_Br_WriteBrL = 47,
3313
    WriteBrL  = 48,
3314
    WriteBr = 49,
3315
    IIC_iUNAr_WriteALU  = 50,
3316
    IIC_iCMPi_WriteCMP_ReadALU  = 51,
3317
    IIC_iCMPr_WriteCMP_ReadALU_ReadALU  = 52,
3318
    IIC_iCMPsr_WriteCMPsi_ReadALU = 53,
3319
    IIC_iCMPsr_WriteCMPsr_ReadALU = 54,
3320
    IIC_fpUNA16 = 55,
3321
    IIC_fpSTAT  = 56,
3322
    IIC_iLoad_m = 57,
3323
    IIC_iLoad_bh_ru = 58,
3324
    IIC_iLoad_bh_iu = 59,
3325
    IIC_iLoad_bh_si = 60,
3326
    IIC_iLoad_d_r = 61,
3327
    IIC_iLoad_d_ru  = 62,
3328
    IIC_iLoad_ru  = 63,
3329
    IIC_iLoad_iu  = 64,
3330
    IIC_iLoad_si  = 65,
3331
    IIC_iMOVr_WriteALU  = 66,
3332
    IIC_iMOVsr_WriteALU = 67,
3333
    IIC_iMVNi_WriteALU  = 68,
3334
    IIC_iMVNr_WriteALU  = 69,
3335
    IIC_iMVNsr_WriteALU = 70,
3336
    IIC_iBITsi_WriteALUsi_ReadALU = 71,
3337
    IIC_Preload_WritePreLd  = 72,
3338
    IIC_iDIV_WriteDIV = 73,
3339
    IIC_iMAC16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 74,
3340
    WriteMAC32_ReadMUL_ReadMUL_ReadMAC  = 75,
3341
    WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC = 76,
3342
    WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL = 77,
3343
    WriteMUL32_ReadMUL_ReadMUL  = 78,
3344
    IIC_iMUL16_WriteMUL16_ReadMUL_ReadMUL = 79,
3345
    IIC_iStore_m  = 80,
3346
    IIC_iStore_mu = 81,
3347
    IIC_iStore_bh_ru  = 82,
3348
    IIC_iStore_bh_iu  = 83,
3349
    IIC_iStore_bh_si  = 84,
3350
    IIC_iStore_d_r  = 85,
3351
    IIC_iStore_d_ru = 86,
3352
    IIC_iStore_iu = 87,
3353
    IIC_iStore_si = 88,
3354
    IIC_iEXTAr_WriteALUsr = 89,
3355
    IIC_iEXTr_WriteALUsi  = 90,
3356
    IIC_iTSTi_WriteCMP_ReadALU  = 91,
3357
    IIC_iTSTr_WriteCMP_ReadALU_ReadALU  = 92,
3358
    IIC_iTSTsr_WriteCMPsi_ReadALU = 93,
3359
    IIC_iTSTsr_WriteCMPsr_ReadALU = 94,
3360
    IIC_iMUL64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL  = 95,
3361
    WriteALU_ReadALU_ReadALU  = 96,
3362
    IIC_VABAD = 97,
3363
    IIC_VABAQ = 98,
3364
    IIC_VSUBi4Q = 99,
3365
    IIC_VBIND = 100,
3366
    IIC_VBINQ = 101,
3367
    IIC_VSUBi4D = 102,
3368
    IIC_VUNAD = 103,
3369
    IIC_VUNAQ = 104,
3370
    IIC_VUNAiQ  = 105,
3371
    IIC_VUNAiD  = 106,
3372
    IIC_fpALU64_WriteFPALU64  = 107,
3373
    IIC_fpALU16_WriteFPALU32  = 108,
3374
    IIC_VBINi4D = 109,
3375
    IIC_VSHLiD  = 110,
3376
    IIC_fpALU32_WriteFPALU32  = 111,
3377
    IIC_VSUBiD  = 112,
3378
    IIC_VBINiQ  = 113,
3379
    IIC_VBINiD  = 114,
3380
    IIC_VCNTiD  = 115,
3381
    IIC_VCNTiQ  = 116,
3382
    IIC_VMACD = 117,
3383
    IIC_VMACQ = 118,
3384
    IIC_fpCMP64 = 119,
3385
    IIC_fpCMP16 = 120,
3386
    IIC_fpCMP32 = 121,
3387
    WriteFPCVT  = 122,
3388
    IIC_fpCVTSH_WriteFPCVT  = 123,
3389
    IIC_fpCVTHS_WriteFPCVT  = 124,
3390
    IIC_fpCVTDS_WriteFPCVT  = 125,
3391
    IIC_fpCVTSD_WriteFPCVT  = 126,
3392
    IIC_fpDIV64_WriteFPDIV64  = 127,
3393
    IIC_fpDIV16_WriteFPDIV32  = 128,
3394
    IIC_fpDIV32_WriteFPDIV32  = 129,
3395
    IIC_VMOVIS  = 130,
3396
    IIC_VMOVD = 131,
3397
    IIC_VMOVQ = 132,
3398
    IIC_VEXTD = 133,
3399
    IIC_VEXTQ = 134,
3400
    IIC_fpFMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL = 135,
3401
    IIC_fpFMAC16_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 136,
3402
    IIC_fpFMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 137,
3403
    IIC_VFMACD  = 138,
3404
    IIC_VFMACQ  = 139,
3405
    IIC_VMOVSI  = 140,
3406
    IIC_VBINi4Q = 141,
3407
    IIC_fpCVTDI = 142,
3408
    IIC_VLD1dup_WriteVLD2 = 143,
3409
    IIC_VLD1dupu  = 144,
3410
    IIC_VLD1dup = 145,
3411
    IIC_VLD1dupu_WriteVLD1  = 146,
3412
    IIC_VLD1ln  = 147,
3413
    IIC_VLD1lnu_WriteVLD1 = 148,
3414
    IIC_VLD1ln_WriteVLD1  = 149,
3415
    IIC_VLD1_WriteVLD1  = 150,
3416
    IIC_VLD1x4_WriteVLD4  = 151,
3417
    IIC_VLD1x2u_WriteVLD4 = 152,
3418
    IIC_VLD1x3_WriteVLD3  = 153,
3419
    IIC_VLD1x2u_WriteVLD3 = 154,
3420
    IIC_VLD1u_WriteVLD1 = 155,
3421
    IIC_VLD1x2_WriteVLD2  = 156,
3422
    IIC_VLD1x2u_WriteVLD2 = 157,
3423
    IIC_VLD2dup = 158,
3424
    IIC_VLD2dupu_WriteVLD1  = 159,
3425
    IIC_VLD2dup_WriteVLD2 = 160,
3426
    IIC_VLD2ln_WriteVLD1  = 161,
3427
    IIC_VLD2lnu_WriteVLD1 = 162,
3428
    IIC_VLD2lnu = 163,
3429
    IIC_VLD2_WriteVLD2  = 164,
3430
    IIC_VLD2u_WriteVLD2 = 165,
3431
    IIC_VLD2x2_WriteVLD4  = 166,
3432
    IIC_VLD2x2u_WriteVLD4 = 167,
3433
    IIC_VLD3dup_WriteVLD2 = 168,
3434
    IIC_VLD3dupu_WriteVLD2  = 169,
3435
    IIC_VLD3ln_WriteVLD2  = 170,
3436
    IIC_VLD3lnu_WriteVLD2 = 171,
3437
    IIC_VLD3_WriteVLD3  = 172,
3438
    IIC_VLD3u_WriteVLD3 = 173,
3439
    IIC_VLD4dup = 174,
3440
    IIC_VLD4dup_WriteVLD2 = 175,
3441
    IIC_VLD4dupu_WriteVLD2  = 176,
3442
    IIC_VLD4ln_WriteVLD2  = 177,
3443
    IIC_VLD4lnu_WriteVLD2 = 178,
3444
    IIC_VLD4lnu = 179,
3445
    IIC_VLD4_WriteVLD4  = 180,
3446
    IIC_VLD4u_WriteVLD4 = 181,
3447
    IIC_fpLoad_mu = 182,
3448
    IIC_fpLoad_m  = 183,
3449
    IIC_fpLoad64  = 184,
3450
    IIC_fpLoad16  = 185,
3451
    IIC_fpLoad32  = 186,
3452
    IIC_fpStore_m = 187,
3453
    IIC_fpMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL  = 188,
3454
    IIC_fpMAC16 = 189,
3455
    IIC_VMACi32D  = 190,
3456
    IIC_VMACi16D  = 191,
3457
    IIC_fpMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL  = 192,
3458
    IIC_VMACi32Q  = 193,
3459
    IIC_VMACi16Q  = 194,
3460
    IIC_fpMOVID_WriteFPMOV  = 195,
3461
    IIC_fpMOVIS_WriteFPMOV  = 196,
3462
    IIC_VQUNAiD = 197,
3463
    IIC_VMOVN = 198,
3464
    IIC_fpMOVSI_WriteFPMOV  = 199,
3465
    IIC_fpMOVDI_WriteFPMOV  = 200,
3466
    IIC_fpMUL64_WriteFPMUL64_ReadFPMUL_ReadFPMUL  = 201,
3467
    IIC_fpMUL16_WriteFPMUL32_ReadFPMUL_ReadFPMUL  = 202,
3468
    IIC_VMULi16D  = 203,
3469
    IIC_VMULi32D  = 204,
3470
    IIC_fpMUL32_WriteFPMUL32_ReadFPMUL_ReadFPMUL  = 205,
3471
    IIC_VFMULD  = 206,
3472
    IIC_VFMULQ  = 207,
3473
    IIC_VMULi16Q  = 208,
3474
    IIC_VMULi32Q  = 209,
3475
    IIC_VSHLiQ  = 210,
3476
    IIC_VPALiQ  = 211,
3477
    IIC_VPALiD  = 212,
3478
    IIC_VPBIND  = 213,
3479
    IIC_VQUNAiQ = 214,
3480
    IIC_VSHLi4Q = 215,
3481
    IIC_VSHLi4D = 216,
3482
    IIC_VRECSD  = 217,
3483
    IIC_VRECSQ  = 218,
3484
    IIC_VDOTPROD  = 219,
3485
    IIC_VMOVISL = 220,
3486
    IIC_fpCVTID_WriteFPCVT  = 221,
3487
    IIC_fpCVTIH_WriteFPCVT  = 222,
3488
    IIC_fpCVTIS_WriteFPCVT  = 223,
3489
    IIC_fpSQRT64_WriteFPSQRT64  = 224,
3490
    IIC_fpSQRT16  = 225,
3491
    IIC_fpSQRT32_WriteFPSQRT32  = 226,
3492
    IIC_VST1ln_WriteVST1  = 227,
3493
    IIC_VST1lnu_WriteVST1 = 228,
3494
    IIC_VST1_WriteVST1  = 229,
3495
    IIC_VST1x4_WriteVST4  = 230,
3496
    IIC_VLD1x4u_WriteVST4 = 231,
3497
    IIC_VST1x3_WriteVST3  = 232,
3498
    IIC_VLD1x3u_WriteVST3 = 233,
3499
    IIC_VLD1u_WriteVST1 = 234,
3500
    IIC_VST1x4u_WriteVST4 = 235,
3501
    IIC_VST1x3u_WriteVST3 = 236,
3502
    IIC_VST1x2_WriteVST2  = 237,
3503
    IIC_VLD1x2u_WriteVST2 = 238,
3504
    IIC_VST2ln_WriteVST1  = 239,
3505
    IIC_VST2lnu_WriteVST1 = 240,
3506
    IIC_VST2lnu = 241,
3507
    IIC_VST2  = 242,
3508
    IIC_VLD1u_WriteVST2 = 243,
3509
    IIC_VST2_WriteVST2  = 244,
3510
    IIC_VST2x2_WriteVST4  = 245,
3511
    IIC_VST2x2u_WriteVST4 = 246,
3512
    IIC_VLD1u_WriteVST4 = 247,
3513
    IIC_VST3ln_WriteVST2  = 248,
3514
    IIC_VST3lnu_WriteVST2 = 249,
3515
    IIC_VST3lnu = 250,
3516
    IIC_VST3ln  = 251,
3517
    IIC_VST3_WriteVST3  = 252,
3518
    IIC_VST3u_WriteVST3 = 253,
3519
    IIC_VST4ln_WriteVST2  = 254,
3520
    IIC_VST4lnu_WriteVST2 = 255,
3521
    IIC_VST4lnu = 256,
3522
    IIC_VST4_WriteVST4  = 257,
3523
    IIC_VST4u_WriteVST4 = 258,
3524
    IIC_fpStore_mu  = 259,
3525
    IIC_fpStore64 = 260,
3526
    IIC_fpStore16 = 261,
3527
    IIC_fpStore32 = 262,
3528
    IIC_VSUBiQ  = 263,
3529
    IIC_VTB1  = 264,
3530
    IIC_VTB2  = 265,
3531
    IIC_VTB3  = 266,
3532
    IIC_VTB4  = 267,
3533
    IIC_VTBX1 = 268,
3534
    IIC_VTBX2 = 269,
3535
    IIC_VTBX3 = 270,
3536
    IIC_VTBX4 = 271,
3537
    IIC_fpCVTDI_WriteFPCVT  = 272,
3538
    IIC_fpCVTHI_WriteFPCVT  = 273,
3539
    IIC_fpCVTSI_WriteFPCVT  = 274,
3540
    IIC_fpCVTSI = 275,
3541
    IIC_VPERMD  = 276,
3542
    IIC_VPERMQ  = 277,
3543
    IIC_VPERMQ3 = 278,
3544
    IIC_iBITi = 279,
3545
    IIC_iCMPsi_WriteCMPsi_ReadALU_ReadALU = 280,
3546
    IIC_iCMPi_WriteCMP  = 281,
3547
    IIC_iCMPr_WriteCMP  = 282,
3548
    IIC_iCMPsi_WriteCMPsi = 283,
3549
    IIC_iALUx = 284,
3550
    WriteLd = 285,
3551
    IIC_iLoad_bh_i_WriteLd  = 286,
3552
    IIC_iLoad_bh_iu_WriteLd = 287,
3553
    IIC_iLoad_bh_si_WriteLd = 288,
3554
    IIC_iLoad_d_ru_WriteLd  = 289,
3555
    IIC_iLoad_d_i_WriteLd = 290,
3556
    IIC_iLoad_i_WriteLd = 291,
3557
    IIC_iLoad_iu_WriteLd  = 292,
3558
    IIC_iLoad_si_WriteLd  = 293,
3559
    IIC_iMVNsi_WriteALU = 294,
3560
    IIC_iALUsir_WriteALUsi_ReadALU  = 295,
3561
    IIC_iMUL16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 296,
3562
    IIC_iMAC32  = 297,
3563
    WriteST = 298,
3564
    IIC_iStore_bh_i_WriteST = 299,
3565
    IIC_iStore_bh_iu_WriteST  = 300,
3566
    IIC_iStore_bh_si_WriteST  = 301,
3567
    IIC_iStore_d_ru_WriteST = 302,
3568
    IIC_iStore_d_r_WriteST  = 303,
3569
    IIC_iStore_iu_WriteST = 304,
3570
    IIC_iStore_i_WriteST  = 305,
3571
    IIC_iStore_si_WriteST = 306,
3572
    IIC_iEXTAsr_WriteALU_ReadALU  = 307,
3573
    IIC_iEXTr_WriteALU_ReadALU  = 308,
3574
    IIC_iTSTi_WriteCMP  = 309,
3575
    IIC_iTSTr_WriteCMP  = 310,
3576
    IIC_iTSTsi_WriteCMPsi = 311,
3577
    IIC_iBITr_WriteALU  = 312,
3578
    IIC_iLoad_bh_i  = 313,
3579
    IIC_iMUL32  = 314,
3580
    IIC_iPop  = 315,
3581
    IIC_iStore_bh_i = 316,
3582
    IIC_iStore_i  = 317,
3583
    IIC_iTSTr_WriteALU  = 318,
3584
    ANDri_ORRri_EORri_BICri = 319,
3585
    ANDrr_ORRrr_EORrr_BICrr = 320,
3586
    ANDrsi_ORRrsi_EORrsi_BICrsi = 321,
3587
    ANDrsr_ORRrsr_EORrsr_BICrsr = 322,
3588
    MOVsra_flag_MOVsrl_flag = 323,
3589
    MOVsr_MOVsi = 324,
3590
    MVNsr = 325,
3591
    MOVCCsi_MOVCCsr = 326,
3592
    MVNr  = 327,
3593
    MOVCCi32imm = 328,
3594
    MOVi32imm = 329,
3595
    MOV_ga_pcrel  = 330,
3596
    MOV_ga_pcrel_ldr  = 331,
3597
    SEL = 332,
3598
    BFC_BFI_UBFX_SBFX = 333,
3599
    MULv5_MUL_SMMUL_SMMULR  = 334,
3600
    MLAv5_MLA_MLS_SMMLA_SMMLAR_SMMLS_SMMLSR = 335,
3601
    SMULLv5_SMULL_UMULLv5 = 336,
3602
    UMULL = 337,
3603
    SMLAL_UMLALv5_UMLAL_UMAAL_SMLALv5_SMLALBB_SMLALBT_SMLALTB_SMLALTT = 338,
3604
    SMLAD_SMLADX_SMLSD_SMLSDX = 339,
3605
    SMLALD_SMLSLD = 340,
3606
    SMLALDX_SMLSLDX = 341,
3607
    SMUAD_SMUADX_SMUSD_SMUSDX = 342,
3608
    SMULBB_SMULBT_SMULTB_SMULTT_SMULWB_SMULWT = 343,
3609
    SMLABB_SMLABT_SMLATB_SMLATT_SMLAWB_SMLAWT = 344,
3610
    LDRi12_PICLDR = 345,
3611
    LDRrs = 346,
3612
    LDRBi12_PICLDRH_PICLDRB_PICLDRSH_PICLDRSB_LDRH_LDRSH_LDRSB  = 347,
3613
    LDRHTi_LDRHTr_LDRH_POST_LDRH_PRE_LDRSHTi_LDRSHTr_LDRSH_POST_LDRSH_PRE_LDRSBTi_LDRSBTr_LDRSB_POST_LDRSB_PRE  = 348,
3614
    SXTB_SXTB16_SXTH_UXTB_UXTB16_UXTH = 349,
3615
    t2SXTB_t2SXTB16_t2SXTH_t2UXTB_t2UXTB16_t2UXTH = 350,
3616
    t2MOVCCi32imm = 351,
3617
    t2MOVi32imm = 352,
3618
    t2MOV_ga_pcrel  = 353,
3619
    t2MOVi16_ga_pcrel = 354,
3620
    t2SEL = 355,
3621
    t2BFC_t2UBFX_t2SBFX = 356,
3622
    t2BFI = 357,
3623
    QADD_QADD16_QADD8_QSUB_QSUB16_QSUB8_QDADD_QDSUB_QASX_QSAX_UQADD8_UQADD16_UQSUB8_UQSUB16_UQASX_UQSAX = 358,
3624
    SSAT_SSAT16_USAT_USAT16_t2QADD_t2QADD16_t2QADD8_t2QSUB_t2QSUB16_t2QSUB8_t2QDADD_t2QDSUB_t2SSAT_t2SSAT16_t2USAT_t2USAT16_t2QASX_t2QSAX_t2UQADD8_t2UQADD16_t2UQSUB8_t2UQSUB16_t2UQASX_t2UQSAX = 359,
3625
    SADD8_SADD16_SSUB8_SSUB16_SASX_SSAX_UADD8_UADD16_USUB8_USUB16_UASX_USAX = 360,
3626
    t2SADD8_t2SADD16_t2SSUB8_t2SSUB16_t2SASX_t2SSAX_t2UADD8_t2UADD16_t2USUB8_t2USUB16_t2UASX_t2USAX = 361,
3627
    SHADD8_SHADD16_SHSUB8_SHSUB16_SHASX_SHSAX_UHADD8_UHADD16_UHSUB8_UHSUB16_UHASX_UHSAX = 362,
3628
    SXTAB_SXTAB16_SXTAH_UXTAB_UXTAB16_UXTAH = 363,
3629
    t2SHADD8_t2SHADD16_t2SHSUB8_t2SHSUB16_t2SHASX_t2SHSAX_t2UHADD8_t2UHADD16_t2UHSUB8_t2UHSUB16_t2UHASX_t2UHSAX = 364,
3630
    t2SXTAB_t2SXTAB16_t2SXTAH_t2UXTAB_t2UXTAB16_t2UXTAH = 365,
3631
    USAD8 = 366,
3632
    USADA8  = 367,
3633
    SMUSD_SMUSDX  = 368,
3634
    t2MUL_t2SMMUL_t2SMMULR  = 369,
3635
    t2SMULBB_t2SMULBT_t2SMULTB_t2SMULTT_t2SMULWB_t2SMULWT = 370,
3636
    t2SMUSD_t2SMUSDX  = 371,
3637
    t2MLA_t2MLS_t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 372,
3638
    t2SMUAD_t2SMUADX  = 373,
3639
    SMLSD_SMLSDX  = 374,
3640
    t2SMLABB_t2SMLABT_t2SMLATB_t2SMLATT_t2SMLAWB_t2SMLAWT = 375,
3641
    t2SMLSD_t2SMLSDX  = 376,
3642
    t2SMLAD_t2SMLADX  = 377,
3643
    SMULL = 378,
3644
    t2SMULL_t2UMULL = 379,
3645
    t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2UMLAL_t2SMLSLD_t2SMLSLDX_t2UMAAL = 380,
3646
    SDIV_UDIV_t2SDIV_t2UDIV = 381,
3647
    LDRi12  = 382,
3648
    LDRBi12 = 383,
3649
    LDRBrs  = 384,
3650
    t2LDRpci_pic  = 385,
3651
    t2LDRi12_t2LDRi8_t2LDRpci = 386,
3652
    t2LDRs  = 387,
3653
    t2LDRBi12_t2LDRBi8_t2LDRBpci_t2LDRHi12_t2LDRHi8_t2LDRHpci = 388,
3654
    t2LDRBs_t2LDRHs = 389,
3655
    LDREX_LDREXB_LDREXD_LDREXH_tLDRpci_pic  = 390,
3656
    tLDRBi_tLDRHi = 391,
3657
    tLDRBr_tLDRHr = 392,
3658
    tLDRi_tLDRpci_tLDRspi = 393,
3659
    tLDRr = 394,
3660
    LDRH_PICLDRB_PICLDRH  = 395,
3661
    LDRcp = 396,
3662
    t2LDRSBpcrel_t2LDRSHpcrel = 397,
3663
    t2LDRSBi12_t2LDRSBi8_t2LDRSBpci_t2LDRSHi12_t2LDRSHi8_t2LDRSHpci = 398,
3664
    t2LDRSBs_t2LDRSHs = 399,
3665
    tLDRSB_tLDRSH = 400,
3666
    LDRBT_POST_IMM_LDRBT_POST_REG_LDRB_POST_REG_LDRB_PRE_REG  = 401,
3667
    LDRB_POST_IMM_LDRB_PRE_IMM_t2LDRB_POST  = 402,
3668
    LDRT_POST_IMM_LDRT_POST_REG_LDR_POST_REG_LDR_PRE_REG  = 403,
3669
    LDR_POST_IMM_LDR_PRE_IMM  = 404,
3670
    LDRH_POST_LDRH_PRE_LDRHTi_LDRHTr  = 405,
3671
    t2LDRB_PRE_t2LDRH_POST_t2LDRH_PRE = 406,
3672
    t2LDR_POST_t2LDR_PRE  = 407,
3673
    t2LDRBT_t2LDRHT = 408,
3674
    t2LDRT  = 409,
3675
    t2LDRSB_POST_t2LDRSB_PRE_t2LDRSH_POST_t2LDRSH_PRE = 410,
3676
    t2LDRSBT_t2LDRSHT = 411,
3677
    t2LDRDi8  = 412,
3678
    LDRD  = 413,
3679
    LDRD_POST_LDRD_PRE  = 414,
3680
    t2LDRD_POST_t2LDRD_PRE  = 415,
3681
    LDMDA_LDMDB_LDMIA_LDMIB_t2LDMDB_t2LDMIA_sysLDMDA_sysLDMDB_sysLDMIA_sysLDMIB_tLDMIA  = 416,
3682
    LDMDA_UPD_LDMDB_UPD_LDMIA_UPD_LDMIB_UPD_tLDMIA_UPD_sysLDMDA_UPD_sysLDMDB_UPD_sysLDMIA_UPD_sysLDMIB_UPD_t2LDMDB_UPD_t2LDMIA_UPD  = 417,
3683
    LDMIA_RET_t2LDMIA_RET = 418,
3684
    tPOP_RET  = 419,
3685
    tPOP  = 420,
3686
    PICSTR_STRi12_tSTRr = 421,
3687
    PICSTRB_PICSTRH_STRBi12_STRH_tSTRBr_tSTRHr  = 422,
3688
    STRrs = 423,
3689
    STRBrs  = 424,
3690
    STREX_STREXB_STREXD_STREXH  = 425,
3691
    t2STRi12_t2STRi8  = 426,
3692
    t2STRs  = 427,
3693
    t2STRBi12_t2STRBi8_t2STRHi12_t2STRHi8 = 428,
3694
    t2STRBs_t2STRHs = 429,
3695
    tSTRBi_tSTRHi = 430,
3696
    tSTRi_tSTRspi = 431,
3697
    STRBT_POST_IMM_STRBT_POST_REG_STRB_POST_REG_STRB_PRE_REG_STRH_POST_STRH_PRE_STRHTi_STRHTr = 432,
3698
    STRB_POST_IMM_STRB_PRE_IMM  = 433,
3699
    STRT_POST_IMM_STRT_POST_REG_STR_POST_REG_STR_PRE_REG_STRi_preidx_STRr_preidx_STRBi_preidx_STRBr_preidx_STRH_preidx  = 434,
3700
    STR_POST_IMM_STR_PRE_IMM  = 435,
3701
    STRBT_POST_STRT_POST  = 436,
3702
    t2STR_POST_t2STR_PRE_t2STRH_PRE = 437,
3703
    t2STRB_POST_t2STRB_PRE_t2STRH_POST  = 438,
3704
    t2STR_preidx_t2STRB_preidx_t2STRH_preidx  = 439,
3705
    t2STRBT_t2STRHT = 440,
3706
    t2STRT  = 441,
3707
    STRD  = 442,
3708
    t2STRDi8  = 443,
3709
    t2STRD_POST_t2STRD_PRE  = 444,
3710
    STRD_POST_STRD_PRE  = 445,
3711
    STMDA_STMDB_STMIA_STMIB_sysSTMDA_sysSTMDB_sysSTMIA_sysSTMIB_t2STMDB_t2STMIA = 446,
3712
    STMDA_UPD_STMDB_UPD_STMIA_UPD_STMIB_UPD_sysSTMDA_UPD_sysSTMDB_UPD_sysSTMIA_UPD_sysSTMIB_UPD_t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD  = 447,
3713
    tPUSH = 448,
3714
    LDRLIT_ga_abs_tLDRLIT_ga_abs  = 449,
3715
    LDRLIT_ga_pcrel_tLDRLIT_ga_pcrel  = 450,
3716
    LDRLIT_ga_pcrel_ldr = 451,
3717
    t2IT  = 452,
3718
    ITasm = 453,
3719
    VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16_VANDq_VBICq_VEORq_VORNq_VORRq_VBIFq_VBITq = 454,
3720
    VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8_VANDd_VBICd_VEORd_VORNd_VORRd_VBIFd_VBITd  = 455,
3721
    VSUBv16i8_VSUBv2i64_VSUBv4i32_VSUBv8i16 = 456,
3722
    VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8_VADDWsv2i64_VADDWsv4i32_VADDWsv8i16_VADDWuv2i64_VADDWuv4i32_VADDWuv8i16_VSUBWsv2i64_VSUBWsv4i32_VSUBWsv8i16_VSUBWuv2i64_VSUBWuv4i32_VSUBWuv8i16  = 457,
3723
    VNEGf32q  = 458,
3724
    VNEGfd  = 459,
3725
    VNEGs16d_VNEGs32d_VNEGs8d_VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16_VPADDi16_VPADDi32_VPADDi8_VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLsv1i64_VSHLsv2i32_VSHLsv4i16_VSHLsv8i8_VSHLuv1i64_VSHLuv2i32_VSHLuv4i16_VSHLuv8i8_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8_VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8  = 460,
3726
    VNEGs16q_VNEGs32q_VNEGs8q_VSHLsv16i8_VSHLsv2i64_VSHLsv4i32_VSHLsv8i16_VSHLuv16i8_VSHLuv2i64_VSHLuv4i32_VSHLuv8i16_VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 461,
3727
    VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16_VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16_VTSTv16i8_VTSTv4i32_VTSTv8i16 = 462,
3728
    VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8_VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8_VTSTv2i32_VTSTv4i16_VTSTv8i8  = 463,
3729
    VHSUBsv16i8_VHSUBsv4i32_VHSUBsv8i16_VHSUBuv16i8_VHSUBuv4i32_VHSUBuv8i16 = 464,
3730
    VHSUBsv2i32_VHSUBsv4i16_VHSUBsv8i8_VHSUBuv2i32_VHSUBuv4i16_VHSUBuv8i8 = 465,
3731
    VBICiv2i32_VBICiv4i16_VBICiv4i32_VBICiv8i16_VORRiv2i32_VORRiv4i16_VORRiv4i32_VORRiv8i16 = 466,
3732
    VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLsv1i64_VQSHLsv2i32_VQSHLsv4i16_VQSHLsv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8_VQSHLuv1i64_VQSHLuv2i32_VQSHLuv4i16_VQSHLuv8i8  = 467,
3733
    VQSHLsv16i8_VQSHLsv2i64_VQSHLsv4i32_VQSHLsv8i16_VQSHLuv16i8_VQSHLuv2i64_VQSHLuv4i32_VQSHLuv8i16 = 468,
3734
    VBSLd_VCLSv2i32_VCLSv4i16_VCLSv8i8_VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 469,
3735
    VBSLq_VCLSv16i8_VCLSv4i32_VCLSv8i16_VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 470,
3736
    VEXTd16_VEXTd32_VEXTd8  = 471,
3737
    VEXTq16_VEXTq32_VEXTq64_VEXTq8  = 472,
3738
    VREV16d8_VREV32d16_VREV32d8_VREV64d16_VREV64d32_VREV64d8  = 473,
3739
    VREV16q8_VREV32q16_VREV32q8_VREV64q16_VREV64q32_VREV64q8  = 474,
3740
    VABALsv2i64_VABALsv4i32_VABALsv8i16_VABALuv2i64_VABALuv4i32_VABALuv8i16_VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 475,
3741
    VABAsv16i8_VABAsv4i32_VABAsv8i16_VABAuv16i8_VABAuv4i32_VABAuv8i16 = 476,
3742
    VPADALsv16i8_VPADALsv4i32_VPADALsv8i16_VPADALuv16i8_VPADALuv4i32_VPADALuv8i16 = 477,
3743
    VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8_VRSRAsv16i8_VRSRAsv1i64_VRSRAsv2i32_VRSRAsv2i64_VRSRAsv4i16_VRSRAsv4i32_VRSRAsv8i16_VRSRAsv8i8_VRSRAuv16i8_VRSRAuv1i64_VRSRAuv2i32_VRSRAuv2i64_VRSRAuv4i16_VRSRAuv4i32_VRSRAuv8i16_VRSRAuv8i8_VSRAsv16i8_VSRAsv1i64_VSRAsv2i32_VSRAsv2i64_VSRAsv4i16_VSRAsv4i32_VSRAsv8i16_VSRAsv8i8_VSRAuv16i8_VSRAuv1i64_VSRAuv2i32_VSRAuv2i64_VSRAuv4i16_VSRAuv4i32_VSRAuv8i16_VSRAuv8i8 = 478,
3744
    VACGEfd_VACGEhd_VACGTfd_VACGThd_VCEQfd_VCEQhd_VCGEfd_VCGEhd_VCGTfd_VCGThd = 479,
3745
    VACGEfq_VACGEhq_VACGTfq_VACGThq_VCEQfq_VCEQhq_VCGEfq_VCGEhq_VCGTfq_VCGThq = 480,
3746
    VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16_VQSUBsv16i8_VQSUBsv2i64_VQSUBsv4i32_VQSUBsv8i16_VQSUBuv16i8_VQSUBuv2i64_VQSUBuv4i32_VQSUBuv8i16 = 481,
3747
    VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8_VQSUBsv1i64_VQSUBsv2i32_VQSUBsv4i16_VQSUBsv8i8_VQSUBuv1i64_VQSUBuv2i32_VQSUBuv4i16_VQSUBuv8i8  = 482,
3748
    VCEQzv16i8_VCEQzv2f32_VCEQzv2i32_VCEQzv4f16_VCEQzv4f32_VCEQzv4i16_VCEQzv4i32_VCEQzv8f16_VCEQzv8i16_VCEQzv8i8_VCGEzv16i8_VCGEzv2f32_VCGEzv2i32_VCGEzv4f16_VCGEzv4f32_VCGEzv4i16_VCGEzv4i32_VCGEzv8f16_VCGEzv8i16_VCGEzv8i8_VCGTzv16i8_VCGTzv2f32_VCGTzv2i32_VCGTzv4f16_VCGTzv4f32_VCGTzv4i16_VCGTzv4i32_VCGTzv8f16_VCGTzv8i16_VCGTzv8i8_VCLEzv16i8_VCLEzv2f32_VCLEzv2i32_VCLEzv4f16_VCLEzv4f32_VCLEzv4i16_VCLEzv4i32_VCLEzv8f16_VCLEzv8i16_VCLEzv8i8_VCLTzv16i8_VCLTzv2f32_VCLTzv2i32_VCLTzv4f16_VCLTzv4f32_VCLTzv4i16_VCLTzv4i32_VCLTzv8f16_VCLTzv8i16_VCLTzv8i8  = 483,
3749
    VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16_VQRSHLsv16i8_VQRSHLsv2i64_VQRSHLsv4i32_VQRSHLsv8i16_VQRSHLuv16i8_VQRSHLuv2i64_VQRSHLuv4i32_VQRSHLuv8i16 = 484,
3750
    VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VQRSHLsv1i64_VQRSHLsv2i32_VQRSHLsv4i16_VQRSHLsv8i8_VQRSHLuv1i64_VQRSHLuv2i32_VQRSHLuv4i16_VQRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 485,
3751
    VABSfd  = 486,
3752
    VABSfq  = 487,
3753
    VABSv16i8_VABSv4i32_VABSv8i16 = 488,
3754
    VABSv2i32_VABSv4i16_VABSv8i8  = 489,
3755
    VQABSv16i8_VQABSv4i32_VQABSv8i16_VQNEGv16i8_VQNEGv4i32_VQNEGv8i16 = 490,
3756
    VQABSv2i32_VQABSv4i16_VQABSv8i8_VQNEGv2i32_VQNEGv4i16_VQNEGv8i8 = 491,
3757
    VQADDsv16i8_VQADDsv2i64_VQADDsv4i32_VQADDsv8i16_VQADDuv16i8_VQADDuv2i64_VQADDuv4i32_VQADDuv8i16 = 492,
3758
    VQADDsv1i64_VQADDsv2i32_VQADDsv4i16_VQADDsv8i8_VQADDuv1i64_VQADDuv2i32_VQADDuv4i16_VQADDuv8i8 = 493,
3759
    VRECPEd_VRECPEfd_VRECPEhd_VRSQRTEd_VRSQRTEfd_VRSQRTEhd  = 494,
3760
    VRECPEfq_VRECPEhq_VRECPEq_VRSQRTEfq_VRSQRTEhq_VRSQRTEq  = 495,
3761
    VADDHNv2i32_VADDHNv4i16_VADDHNv8i8_VSUBHNv2i32_VSUBHNv4i16_VSUBHNv8i8 = 496,
3762
    VSHRNv2i32_VSHRNv4i16_VSHRNv8i8 = 497,
3763
    VRADDHNv2i32_VRADDHNv4i16_VRADDHNv8i8_VRSUBHNv2i32_VRSUBHNv4i16_VRSUBHNv8i8 = 498,
3764
    VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8_VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8_VQSHRUNv2i32_VQSHRUNv4i16_VQSHRUNv8i8_VQRSHRNsv2i32_VQRSHRNsv4i16_VQRSHRNsv8i8_VQRSHRNuv2i32_VQRSHRNuv4i16_VQRSHRNuv8i8_VQRSHRUNv2i32_VQRSHRUNv4i16_VQRSHRUNv8i8 = 499,
3765
    VTBL1 = 500,
3766
    VTBX1 = 501,
3767
    VTBL2 = 502,
3768
    VTBX2 = 503,
3769
    VTBL3_VTBL3Pseudo = 504,
3770
    VTBX3_VTBX3Pseudo = 505,
3771
    VTBL4_VTBL4Pseudo = 506,
3772
    VTBX4_VTBX4Pseudo = 507,
3773
    VSWPd_VSWPq = 508,
3774
    VTRNd16_VTRNd32_VTRNd8_VUZPd16_VUZPd8_VZIPd16_VZIPd8  = 509,
3775
    VTRNq16_VTRNq32_VTRNq8  = 510,
3776
    VUZPq16_VUZPq32_VUZPq8_VZIPq16_VZIPq32_VZIPq8 = 511,
3777
    VABSD_VNEGD = 512,
3778
    VABSS_VNEGS = 513,
3779
    VCMPD_VCMPZD_VCMPED_VCMPEZD = 514,
3780
    VCMPS_VCMPZS_VCMPES_VCMPEZS = 515,
3781
    VADDS_VSUBS = 516,
3782
    VADDfd_VSUBfd_VABDfd_VABDhd_VMAXfd_VMAXhd_VMINfd_VMINhd = 517,
3783
    VADDfq_VSUBfq_VABDfq_VABDhq_VMAXfq_VMAXhq_VMINfq_VMINhq = 518,
3784
    VABDLsv2i64_VABDLsv4i32_VABDLsv8i16_VABDLuv2i64_VABDLuv4i32_VABDLuv8i16_VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16_VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 519,
3785
    VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8_VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8_VPMAXs16_VPMAXs32_VPMAXs8_VPMAXu16_VPMAXu32_VPMAXu8_VPMINs16_VPMINs32_VPMINs8_VPMINu16_VPMINu32_VPMINu8 = 520,
3786
    VPADDf_VPMAXf_VPMAXh_VPMINf_VPMINh  = 521,
3787
    VMAXNMD_VMAXNMH_VMAXNMNDf_VMAXNMNDh_VMAXNMNQf_VMAXNMNQh_VMAXNMS_VMINNMD_VMINNMH_VMINNMNDf_VMINNMNDh_VMINNMNQf_VMINNMNQh_VMINNMS = 522,
3788
    VADDD_VSUBD = 523,
3789
    VRECPSfd_VRECPShd_VRSQRTSfd_VRSQRTShd = 524,
3790
    VRECPSfq_VRECPShq_VRSQRTSfq_VRSQRTShq = 525,
3791
    VMULS_VNMULS  = 526,
3792
    VMULfd  = 527,
3793
    VMULfq  = 528,
3794
    VMULpd_VMULslhd_VMULslv4i16_VMULv4i16_VMULv8i8_VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16_VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32 = 529,
3795
    VMULpq_VMULslhq_VMULslv8i16_VMULv16i8_VMULv8i16_VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 530,
3796
    VMULslfd  = 531,
3797
    VMULslfq  = 532,
3798
    VMULslv2i32_VMULv2i32_VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32_VMULLsv2i64_VMULLuv2i64_VQDMULLv2i64  = 533,
3799
    VMULslv4i32_VMULv4i32_VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 534,
3800
    VMULLp64  = 535,
3801
    VMLAD_VMLSD_VNMLAD_VNMLSD = 536,
3802
    VMLAH_VMLSH_VNMLAH_VNMLSH = 537,
3803
    VMLALslsv2i32_VMLALsluv2i32_VMLALsv2i64_VMLALuv2i64_VMLAslv2i32_VMLAv2i32_VMLSLslsv2i32_VMLSLsluv2i32_VMLSLsv2i64_VMLSLuv2i64_VMLSslv2i32_VMLSv2i32_VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 538,
3804
    VMLALslsv4i16_VMLALsluv4i16_VMLALsv4i32_VMLALsv8i16_VMLALuv4i32_VMLALuv8i16_VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSLslsv4i16_VMLSLsluv4i16_VMLSLsv4i32_VMLSLsv8i16_VMLSLuv4i32_VMLSLuv8i16_VMLSslv4i16_VMLSv4i16_VMLSv8i8_VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 539,
3805
    VMLAS_VMLSS_VNMLAS_VNMLSS = 540,
3806
    VMLAfd_VMLAhd_VMLAslfd_VMLAslhd_VMLSfd_VMLShd_VMLSslfd_VMLSslhd = 541,
3807
    VMLAfq_VMLAhq_VMLAslfq_VMLAslhq_VMLSfq_VMLShq_VMLSslfq_VMLSslhq = 542,
3808
    VMLAslv4i32_VMLAv4i32_VMLSslv4i32_VMLSv4i32 = 543,
3809
    VMLAslv8i16_VMLAv16i8_VMLAv8i16_VMLSslv8i16_VMLSv16i8_VMLSv8i16 = 544,
3810
    VFMAD_VFMSD_VFNMAD_VFNMSD = 545,
3811
    VFMAS_VFMSS_VFNMAS_VFNMSS = 546,
3812
    VFNMAH_VFNMSH = 547,
3813
    VFMAfd_VFMSfd = 548,
3814
    VFMAfq_VFMSfq = 549,
3815
    VCVTANSDf_VCVTANSDh_VCVTANSQf_VCVTANSQh_VCVTANUDf_VCVTANUDh_VCVTANUQf_VCVTANUQh_VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTBDH_VCVTMNSDf_VCVTMNSDh_VCVTMNSQf_VCVTMNSQh_VCVTMNUDf_VCVTMNUDh_VCVTMNUQf_VCVTMNUQh_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNNSDf_VCVTNNSDh_VCVTNNSQf_VCVTNNSQh_VCVTNNUDf_VCVTNNUDh_VCVTNNUQf_VCVTNNUQh_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPNSDf_VCVTPNSDh_VCVTPNSQf_VCVTPNSQh_VCVTPNUDf_VCVTPNUDh_VCVTPNUQf_VCVTPNUQh_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTTDH_VCVTTHD = 550,
3816
    VCVTBHD = 551,
3817
    VCVTBHS_VCVTTHS = 552,
3818
    VCVTBSH_VCVTTSH = 553,
3819
    VCVTDS  = 554,
3820
    VCVTSD  = 555,
3821
    VCVTf2h_VCVTf2sq_VCVTf2uq_VCVTf2xsq_VCVTf2xuq_VCVTh2f_VCVTh2sq_VCVTh2uq_VCVTh2xsq_VCVTh2xuq_VCVTs2fq_VCVTs2hq_VCVTu2fq_VCVTu2hq_VCVTxs2fq_VCVTxs2hq_VCVTxu2fq_VCVTxu2hq = 556,
3822
    VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTh2sd_VCVTh2ud_VCVTh2xsd_VCVTh2xud_VCVTs2fd_VCVTs2hd_VCVTu2fd_VCVTu2hd_VCVTxs2fd_VCVTxs2hd_VCVTxu2fd_VCVTxu2hd = 557,
3823
    VSITOD_VUITOD = 558,
3824
    VSITOH_VUITOH = 559,
3825
    VSITOS_VUITOS = 560,
3826
    VTOSHD_VTOSIRD_VTOSIZD_VTOSLD_VTOUHD_VTOUIRD_VTOUIZD_VTOULD = 561,
3827
    VTOSHH_VTOSIRH_VTOSIZH_VTOSLH_VTOUHH_VTOUIRH_VTOUIZH_VTOULH = 562,
3828
    VTOSHS_VTOSIRS_VTOSIZS_VTOUIRS_VTOUIZS  = 563,
3829
    VTOSLS_VTOUHS_VTOULS  = 564,
3830
    VMOVv16i8_VMOVv1i64_VMOVv2f32_VMOVv2i32_VMOVv2i64_VMOVv4f32_VMOVv4i16_VMOVv4i32_VMOVv8i16_VMOVv8i8_VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16  = 565,
3831
    VMOVD_VMOVDcc_FCONSTD = 566,
3832
    VMOVS_VMOVScc_FCONSTS = 567,
3833
    VMVNd_VMVNq = 568,
3834
    VMOVNv2i32_VMOVNv4i16_VMOVNv8i8 = 569,
3835
    VMOVLsv2i64_VMOVLsv4i32_VMOVLsv8i16_VMOVLuv2i64_VMOVLuv4i32_VMOVLuv8i16 = 570,
3836
    VQMOVNsuv2i32_VQMOVNsuv4i16_VQMOVNsuv8i8_VQMOVNsv2i32_VQMOVNsv4i16_VQMOVNsv8i8_VQMOVNuv2i32_VQMOVNuv4i16_VQMOVNuv8i8  = 571,
3837
    VDUPLN16d_VDUPLN32d_VDUPLN8d  = 572,
3838
    VDUPLN16q_VDUPLN32q_VDUPLN8q  = 573,
3839
    VDUP16d_VDUP16q_VDUP32d_VDUP32q_VDUP8d_VDUP8q = 574,
3840
    VMOVRS  = 575,
3841
    VMOVSR  = 576,
3842
    VSETLNi16_VSETLNi32_VSETLNi8  = 577,
3843
    VMOVRRD_VMOVRRS = 578,
3844
    VMOVDRR = 579,
3845
    VMOVSRR = 580,
3846
    VGETLNi32_VGETLNu16_VGETLNu8  = 581,
3847
    VGETLNs16_VGETLNs8  = 582,
3848
    VMRS_VMRS_FPEXC_VMRS_FPINST_VMRS_FPINST2_VMRS_FPSID_VMRS_MVFR0_VMRS_MVFR1_VMRS_MVFR2  = 583,
3849
    VMSR_VMSR_FPEXC_VMSR_FPINST_VMSR_FPINST2_VMSR_FPSID = 584,
3850
    FMSTAT  = 585,
3851
    VLDRD = 586,
3852
    VLDRS = 587,
3853
    VSTRD = 588,
3854
    VSTRS = 589,
3855
    VLDMQIA = 590,
3856
    VSTMQIA = 591,
3857
    VLDMDIA_VLDMSIA = 592,
3858
    VLDMDDB_UPD_VLDMDIA_UPD_VLDMSDB_UPD_VLDMSIA_UPD = 593,
3859
    VSTMDIA_VSTMSIA = 594,
3860
    VSTMDDB_UPD_VSTMDIA_UPD_VSTMSDB_UPD_VSTMSIA_UPD = 595,
3861
    VLD1d16_VLD1d32_VLD1d64_VLD1d8  = 596,
3862
    VLD1q16_VLD1q32_VLD1q64_VLD1q8  = 597,
3863
    VLD1d16wb_fixed_VLD1d16wb_register_VLD1d32wb_fixed_VLD1d32wb_register_VLD1d64wb_fixed_VLD1d64wb_register_VLD1d8wb_fixed_VLD1d8wb_register = 598,
3864
    VLD1q16wb_fixed_VLD1q16wb_register_VLD1q32wb_fixed_VLD1q32wb_register_VLD1q64wb_fixed_VLD1q64wb_register_VLD1q8wb_fixed_VLD1q8wb_register = 599,
3865
    VLD1d16T_VLD1d32T_VLD1d64T_VLD1d8T_VLD1d64TPseudo_VLD1d64TPseudoWB_fixed_VLD1d64TPseudoWB_register  = 600,
3866
    VLD1d16Twb_fixed_VLD1d16Twb_register_VLD1d32Twb_fixed_VLD1d32Twb_register_VLD1d64Twb_fixed_VLD1d64Twb_register_VLD1d8Twb_fixed_VLD1d8Twb_register = 601,
3867
    VLD1d16Q_VLD1d32Q_VLD1d64Q_VLD1d8Q_VLD1d64QPseudo_VLD1d64QPseudoWB_fixed_VLD1d64QPseudoWB_register  = 602,
3868
    VLD1d16Qwb_fixed_VLD1d16Qwb_register_VLD1d32Qwb_fixed_VLD1d32Qwb_register_VLD1d64Qwb_fixed_VLD1d64Qwb_register_VLD1d8Qwb_fixed_VLD1d8Qwb_register = 603,
3869
    VLD2b16_VLD2b32_VLD2b8_VLD2d16_VLD2d32_VLD2d8 = 604,
3870
    VLD2q16_VLD2q32_VLD2q8_VLD2q16Pseudo_VLD2q32Pseudo_VLD2q8Pseudo = 605,
3871
    VLD2b16wb_fixed_VLD2b16wb_register_VLD2b32wb_fixed_VLD2b32wb_register_VLD2b8wb_fixed_VLD2b8wb_register_VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 606,
3872
    VLD2q16wb_fixed_VLD2q16wb_register_VLD2q32wb_fixed_VLD2q32wb_register_VLD2q8wb_fixed_VLD2q8wb_register_VLD2q16PseudoWB_fixed_VLD2q16PseudoWB_register_VLD2q32PseudoWB_fixed_VLD2q32PseudoWB_register_VLD2q8PseudoWB_fixed_VLD2q8PseudoWB_register = 607,
3873
    VLD3d16_VLD3d32_VLD3d8_VLD3q16_VLD3q32_VLD3q8 = 608,
3874
    VLD3d16Pseudo_VLD3d32Pseudo_VLD3d8Pseudo_VLD3q16oddPseudo_VLD3q32oddPseudo_VLD3q8oddPseudo  = 609,
3875
    VLD3d16_UPD_VLD3d32_UPD_VLD3d8_UPD_VLD3q16_UPD_VLD3q32_UPD_VLD3q8_UPD = 610,
3876
    VLD3d16Pseudo_UPD_VLD3d32Pseudo_UPD_VLD3d8Pseudo_UPD_VLD3q16Pseudo_UPD_VLD3q16oddPseudo_UPD_VLD3q32Pseudo_UPD_VLD3q32oddPseudo_UPD_VLD3q8Pseudo_UPD_VLD3q8oddPseudo_UPD = 611,
3877
    VLD4d16_VLD4d32_VLD4d8_VLD4q16_VLD4q32_VLD4q8 = 612,
3878
    VLD4d16Pseudo_VLD4d32Pseudo_VLD4d8Pseudo_VLD4q16oddPseudo_VLD4q32oddPseudo_VLD4q8oddPseudo  = 613,
3879
    VLD4d16_UPD_VLD4d32_UPD_VLD4d8_UPD_VLD4q16_UPD_VLD4q32_UPD_VLD4q8_UPD = 614,
3880
    VLD4d16Pseudo_UPD_VLD4d32Pseudo_UPD_VLD4d8Pseudo_UPD_VLD4q16Pseudo_UPD_VLD4q16oddPseudo_UPD_VLD4q32Pseudo_UPD_VLD4q32oddPseudo_UPD_VLD4q8Pseudo_UPD_VLD4q8oddPseudo_UPD = 615,
3881
    VLD1DUPd16_VLD1DUPd32_VLD1DUPd8 = 616,
3882
    VLD1DUPq16_VLD1DUPq32_VLD1DUPq8 = 617,
3883
    VLD1LNd16_VLD1LNd8  = 618,
3884
    VLD1LNd32_VLD1LNq16Pseudo_VLD1LNq32Pseudo_VLD1LNq8Pseudo  = 619,
3885
    VLD1DUPd16wb_fixed_VLD1DUPd16wb_register_VLD1DUPd32wb_fixed_VLD1DUPd32wb_register_VLD1DUPd8wb_fixed_VLD1DUPd8wb_register_VLD1DUPq16wb_register_VLD1DUPq32wb_register_VLD1DUPq8wb_register = 620,
3886
    VLD1DUPq16wb_fixed_VLD1DUPq32wb_fixed_VLD1DUPq8wb_fixed = 621,
3887
    VLD1LNd16_UPD_VLD1LNd32_UPD_VLD1LNd8_UPD_VLD1LNq16Pseudo_UPD_VLD1LNq32Pseudo_UPD_VLD1LNq8Pseudo_UPD = 622,
3888
    VLD2DUPd16_VLD2DUPd16x2_VLD2DUPd32_VLD2DUPd32x2_VLD2DUPd8_VLD2DUPd8x2 = 623,
3889
    VLD2LNd16_VLD2LNd32_VLD2LNd8_VLD2LNq16_VLD2LNq32_VLD2LNd16Pseudo_VLD2LNd32Pseudo_VLD2LNd8Pseudo_VLD2LNq16Pseudo_VLD2LNq32Pseudo = 624,
3890
    VLD2LNd16_UPD_VLD2LNd32_UPD_VLD2LNd8_UPD_VLD2LNq16_UPD_VLD2LNq32_UPD  = 625,
3891
    VLD2DUPd16wb_fixed_VLD2DUPd16wb_register_VLD2DUPd16x2wb_fixed_VLD2DUPd16x2wb_register_VLD2DUPd32wb_fixed_VLD2DUPd32wb_register_VLD2DUPd32x2wb_fixed_VLD2DUPd32x2wb_register_VLD2DUPd8wb_fixed_VLD2DUPd8wb_register_VLD2DUPd8x2wb_fixed_VLD2DUPd8x2wb_register = 626,
3892
    VLD2LNd16Pseudo_UPD_VLD2LNd32Pseudo_UPD_VLD2LNd8Pseudo_UPD_VLD2LNq16Pseudo_UPD_VLD2LNq32Pseudo_UPD  = 627,
3893
    VLD3DUPd16_VLD3DUPd32_VLD3DUPd8_VLD3DUPq16_VLD3DUPq32_VLD3DUPq8_VLD3DUPd16Pseudo_VLD3DUPd32Pseudo_VLD3DUPd8Pseudo = 628,
3894
    VLD3LNd16_VLD3LNd32_VLD3LNd8_VLD3LNq16_VLD3LNq32_VLD3LNd16Pseudo_VLD3LNd32Pseudo_VLD3LNd8Pseudo_VLD3LNq16Pseudo_VLD3LNq32Pseudo = 629,
3895
    VLD3DUPd16_UPD_VLD3DUPd32_UPD_VLD3DUPd8_UPD_VLD3DUPq16_UPD_VLD3DUPq32_UPD_VLD3DUPq8_UPD = 630,
3896
    VLD3LNd16_UPD_VLD3LNd32_UPD_VLD3LNd8_UPD_VLD3LNq16_UPD_VLD3LNq32_UPD  = 631,
3897
    VLD3DUPd16Pseudo_UPD_VLD3DUPd32Pseudo_UPD_VLD3DUPd8Pseudo_UPD = 632,
3898
    VLD3LNd16Pseudo_UPD_VLD3LNd32Pseudo_UPD_VLD3LNd8Pseudo_UPD_VLD3LNq16Pseudo_UPD_VLD3LNq32Pseudo_UPD  = 633,
3899
    VLD4DUPd16_VLD4DUPd32_VLD4DUPd8_VLD4DUPq16_VLD4DUPq32_VLD4DUPq8 = 634,
3900
    VLD4LNd16_VLD4LNd32_VLD4LNd8_VLD4LNq16_VLD4LNq32_VLD4LNd16Pseudo_VLD4LNd32Pseudo_VLD4LNd8Pseudo_VLD4LNq16Pseudo_VLD4LNq32Pseudo = 635,
3901
    VLD4DUPd16Pseudo_VLD4DUPd32Pseudo_VLD4DUPd8Pseudo = 636,
3902
    VLD4DUPd16_UPD_VLD4DUPd32_UPD_VLD4DUPd8_UPD_VLD4DUPq16_UPD_VLD4DUPq32_UPD_VLD4DUPq8_UPD = 637,
3903
    VLD4LNd16_UPD_VLD4LNd32_UPD_VLD4LNd8_UPD_VLD4LNq16_UPD_VLD4LNq32_UPD  = 638,
3904
    VLD4DUPd16Pseudo_UPD_VLD4DUPd32Pseudo_UPD_VLD4DUPd8Pseudo_UPD = 639,
3905
    VLD4LNd16Pseudo_UPD_VLD4LNd32Pseudo_UPD_VLD4LNd8Pseudo_UPD_VLD4LNq16Pseudo_UPD_VLD4LNq32Pseudo_UPD  = 640,
3906
    VST1d16_VST1d32_VST1d64_VST1d8  = 641,
3907
    VST1q16_VST1q32_VST1q64_VST1q8  = 642,
3908
    VST1d16wb_fixed_VST1d16wb_register_VST1d32wb_fixed_VST1d32wb_register_VST1d64wb_fixed_VST1d64wb_register_VST1d8wb_fixed_VST1d8wb_register = 643,
3909
    VST1q16wb_fixed_VST1q16wb_register_VST1q32wb_fixed_VST1q32wb_register_VST1q64wb_fixed_VST1q64wb_register_VST1q8wb_fixed_VST1q8wb_register = 644,
3910
    VST1d16T_VST1d32T_VST1d64T_VST1d8T_VST1d64TPseudo = 645,
3911
    VST1d16Twb_fixed_VST1d16Twb_register_VST1d32Twb_fixed_VST1d32Twb_register_VST1d64Twb_fixed_VST1d64Twb_register_VST1d8Twb_fixed_VST1d8Twb_register = 646,
3912
    VST1d64TPseudoWB_fixed_VST1d64TPseudoWB_register  = 647,
3913
    VST1d16Q_VST1d16QPseudo_VST1d32Q_VST1d32QPseudo_VST1d64Q_VST1d64QPseudo_VST1d8Q_VST1d8QPseudo = 648,
3914
    VST1d16Qwb_fixed_VST1d16Qwb_register_VST1d32Qwb_fixed_VST1d32Qwb_register_VST1d64Qwb_fixed_VST1d64Qwb_register_VST1d8Qwb_fixed_VST1d8Qwb_register = 649,
3915
    VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register  = 650,
3916
    VST2b16_VST2b32_VST2b8  = 651,
3917
    VST2d16_VST2d32_VST2d8  = 652,
3918
    VST2b16wb_fixed_VST2b16wb_register_VST2b32wb_fixed_VST2b32wb_register_VST2b8wb_fixed_VST2b8wb_register_VST2d16wb_fixed_VST2d16wb_register_VST2d32wb_fixed_VST2d32wb_register_VST2d8wb_fixed_VST2d8wb_register = 653,
3919
    VST2q16_VST2q32_VST2q8_VST2q16Pseudo_VST2q32Pseudo_VST2q8Pseudo = 654,
3920
    VST2q16wb_fixed_VST2q16wb_register_VST2q32wb_fixed_VST2q32wb_register_VST2q8wb_fixed_VST2q8wb_register  = 655,
3921
    VST2q16PseudoWB_fixed_VST2q16PseudoWB_register_VST2q32PseudoWB_fixed_VST2q32PseudoWB_register_VST2q8PseudoWB_fixed_VST2q8PseudoWB_register  = 656,
3922
    VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8_VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo_VST3q16oddPseudo_VST3q32oddPseudo_VST3q8oddPseudo  = 657,
3923
    VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD_VST3d16Pseudo_UPD_VST3d32Pseudo_UPD_VST3d8Pseudo_UPD_VST3q16Pseudo_UPD_VST3q16oddPseudo_UPD_VST3q32Pseudo_UPD_VST3q32oddPseudo_UPD_VST3q8Pseudo_UPD_VST3q8oddPseudo_UPD = 658,
3924
    VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8_VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo_VST4q16oddPseudo_VST4q32oddPseudo_VST4q8oddPseudo  = 659,
3925
    VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD_VST4d16Pseudo_UPD_VST4d32Pseudo_UPD_VST4d8Pseudo_UPD_VST4q16Pseudo_UPD_VST4q16oddPseudo_UPD_VST4q32Pseudo_UPD_VST4q32oddPseudo_UPD_VST4q8Pseudo_UPD_VST4q8oddPseudo_UPD = 660,
3926
    VST1LNd16_VST1LNd32_VST1LNd8_VST1LNq16Pseudo_VST1LNq32Pseudo_VST1LNq8Pseudo = 661,
3927
    VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD_VST1LNq16Pseudo_UPD_VST1LNq32Pseudo_UPD_VST1LNq8Pseudo_UPD = 662,
3928
    VST2LNd16_VST2LNd32_VST2LNd8_VST2LNq16_VST2LNq32_VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo_VST2LNq16Pseudo_VST2LNq32Pseudo = 663,
3929
    VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD_VST2LNq16_UPD_VST2LNq32_UPD  = 664,
3930
    VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD_VST2LNq16Pseudo_UPD_VST2LNq32Pseudo_UPD  = 665,
3931
    VST3LNd16_VST3LNd32_VST3LNd8_VST3LNq16_VST3LNq32_VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo = 666,
3932
    VST3LNq16Pseudo_VST3LNq32Pseudo = 667,
3933
    VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD_VST3LNq16_UPD_VST3LNq32_UPD  = 668,
3934
    VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD_VST3LNq16Pseudo_UPD_VST3LNq32Pseudo_UPD  = 669,
3935
    VST4LNd16_VST4LNd32_VST4LNd8_VST4LNq16_VST4LNq32_VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo_VST4LNq16Pseudo_VST4LNq32Pseudo = 670,
3936
    VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD_VST4LNq16_UPD_VST4LNq32_UPD  = 671,
3937
    VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD_VST4LNq16Pseudo_UPD_VST4LNq32Pseudo_UPD  = 672,
3938
    VDIVS = 673,
3939
    VSQRTS  = 674,
3940
    VDIVD = 675,
3941
    VSQRTD  = 676,
3942
    ABS = 677,
3943
    COPY  = 678,
3944
    t2MOVCCi_t2MOVCCi16 = 679,
3945
    t2MOVi_t2MOVi16 = 680,
3946
    t2ABS = 681,
3947
    t2USAD8_t2USADA8  = 682,
3948
    t2SDIV_t2UDIV = 683,
3949
    t2LDREX_t2LDREXB_t2LDREXD_t2LDREXH_LDA_LDAB_LDAEX_LDAEXB_LDAEXD_LDAEXH_LDAH_t2LDAEX_t2LDAEXB_t2LDAEXD_t2LDAEXH  = 684,
3950
    t2LDA_t2LDAB_t2LDAH = 685,
3951
    LDRBT_POST  = 686,
3952
    MOVsr = 687,
3953
    t2MOVSsr_t2MOVsr  = 688,
3954
    t2MOVsra_flag_t2MOVsrl_flag = 689,
3955
    MOVTi16_ga_pcrel_MOVTi16_t2MOVTi16_ga_pcrel_t2MOVTi16 = 690,
3956
    ADDSri_ADCri_ADDri_RSBSri_RSBri_RSCri_SBCri_t2ADDSri_t2ADCri_t2ADDri_t2ADDri12_t2RSBSri_t2RSBri_t2SBCri = 691,
3957
    CLZ_t2CLZ = 692,
3958
    t2ANDri_t2BICri_t2EORri_t2ORRri = 693,
3959
    t2MVNCCi  = 694,
3960
    t2MVNi  = 695,
3961
    t2MVNr  = 696,
3962
    t2MVNs  = 697,
3963
    ADDSrr_ADCrr_ADDrr_RSBrr_RSCrr_SBCrr_t2ADDSrr_t2ADCrr_t2ADDrr_t2SBCrr = 698,
3964
    CRC32B_CRC32CB_CRC32CH_CRC32CW_CRC32H_CRC32W_t2CRC32B_t2CRC32CB_t2CRC32CH_t2CRC32CW_t2CRC32H_t2CRC32W = 699,
3965
    t2ANDrr_t2BICrr_t2EORrr = 700,
3966
    ADDSrsi_ADCrsi_ADDrsi_RSBrsi_RSCrsi_SBCrsi  = 701,
3967
    t2ADDSrs  = 702,
3968
    t2ADCrs_t2ADDrs_t2SBCrs = 703,
3969
    t2ANDrs_t2BICrs_t2EORrs_t2ORRrs = 704,
3970
    t2RSBrs = 705,
3971
    ADDSrsr = 706,
3972
    ADCrsr_ADDrsr_RSBrsr_RSCrsr_SBCrsr  = 707,
3973
    ADR = 708,
3974
    MVNi  = 709,
3975
    MVNsi = 710,
3976
    t2MOVSsi_t2MOVsi  = 711,
3977
    ASRi_RORi = 712,
3978
    ASRr_RORr_LSRi_LSRr_LSLi_LSLr = 713,
3979
    CMPri_CMNri = 714,
3980
    CMPrr_CMNzrr  = 715,
3981
    CMPrsi_CMNzrsi  = 716,
3982
    CMPrsr_CMNzrsr  = 717,
3983
    t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE_RRXi  = 718,
3984
    RBIT_REV_REV16_REVSH  = 719,
3985
    RRX = 720,
3986
    TSTri = 721,
3987
    TSTrr = 722,
3988
    TSTrsi  = 723,
3989
    TSTrsr  = 724,
3990
    MRS_MRSbanked_MRSsys  = 725,
3991
    MSR_MSRbanked_MSRi  = 726,
3992
    SRSDA_SRSDA_UPD_SRSDB_SRSDB_UPD_SRSIA_SRSIA_UPD_SRSIB_SRSIB_UPD_t2SRSDB_t2SRSDB_UPD_t2SRSIA_t2SRSIA_UPD_t2STREX_t2STREXB_t2STREXD_t2STREXH_RFEDA_RFEDA_UPD_RFEDB_RFEDB_UPD_RFEIA_RFEIA_UPD_RFEIB_RFEIB_UPD_t2RFEDB_t2RFEDBW_t2RFEIA_t2RFEIAW  = 727,
3993
    STL_STLB_STLEX_STLEXB_STLEXD_STLEXH_STLH_t2STLEX_t2STLEXB_t2STLEXD_t2STLEXH = 728,
3994
    t2STL_t2STLB_t2STLH = 729,
3995
    VABDfd_VABDhd = 730,
3996
    VABDfq_VABDhq = 731,
3997
    VABSD = 732,
3998
    VABSH = 733,
3999
    VABSS = 734,
4000
    VABShd  = 735,
4001
    VABShq  = 736,
4002
    VACGEfd_VACGEhd_VACGTfd_VACGThd = 737,
4003
    VACGEfq_VACGEhq_VACGTfq_VACGThq = 738,
4004
    VADDH_VSUBH = 739,
4005
    VADDfd_VSUBfd = 740,
4006
    VADDhd_VSUBhd = 741,
4007
    VADDfq_VSUBfq = 742,
4008
    VADDhq_VSUBhq = 743,
4009
    VLDRH = 744,
4010
    VSTRH = 745,
4011
    VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 746,
4012
    VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8 = 747,
4013
    VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16 = 748,
4014
    VABDLsv4i32_VABDLsv8i16_VABDLuv4i32_VABDLuv8i16 = 749,
4015
    VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8  = 750,
4016
    VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8  = 751,
4017
    VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16 = 752,
4018
    VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16 = 753,
4019
    VANDd_VBICd_VEORd = 754,
4020
    VANDq_VBICq_VEORq = 755,
4021
    VBICiv2i32_VBICiv4i16 = 756,
4022
    VBICiv4i32_VBICiv8i16 = 757,
4023
    VBIFd_VBITd = 758,
4024
    VBSLd = 759,
4025
    VBIFq_VBITq = 760,
4026
    VBSLq = 761,
4027
    VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16 = 762,
4028
    VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8  = 763,
4029
    VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 764,
4030
    VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd  = 765,
4031
    VCMPEH_VCMPEZH_VCMPH_VCMPZH = 766,
4032
    VDUP16d_VDUP32d_VDUP8d  = 767,
4033
    VSELEQD_VSELEQH_VSELEQS_VSELGED_VSELGEH_VSELGES_VSELGTD_VSELGTH_VSELGTS_VSELVSD_VSELVSH_VSELVSS = 768,
4034
    VFMAhd_VFMShd = 769,
4035
    VFMAhq_VFMShq = 770,
4036
    VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8 = 771,
4037
    VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16 = 772,
4038
    VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 773,
4039
    VPMAXf_VPMAXh_VPMINf_VPMINh = 774,
4040
    VNEGH = 775,
4041
    VNEGhd  = 776,
4042
    VNEGhq  = 777,
4043
    VNEGs16d_VNEGs32d_VNEGs8d = 778,
4044
    VNEGs16q_VNEGs32q_VNEGs8q = 779,
4045
    VPADDi16_VPADDi32_VPADDi8 = 780,
4046
    VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8 = 781,
4047
    VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8 = 782,
4048
    VQABSv2i32_VQABSv4i16_VQABSv8i8 = 783,
4049
    VQABSv16i8_VQABSv4i32_VQABSv8i16  = 784,
4050
    VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 785,
4051
    VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 786,
4052
    VQDMULHslv2i32_VQDMULHv2i32_VQDMULLv2i64_VQRDMULHslv2i32_VQRDMULHv2i32  = 787,
4053
    VQDMULHslv4i16_VQDMULHv4i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32_VQRDMULHslv4i16_VQRDMULHv4i16  = 788,
4054
    VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 789,
4055
    VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 790,
4056
    VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8 = 791,
4057
    VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16 = 792,
4058
    VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 793,
4059
    VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8  = 794,
4060
    VST1d16T_VST1d32T_VST1d64T_VST1d8T  = 795,
4061
    VST1d16Q_VST1d32Q_VST1d64Q_VST1d8Q  = 796,
4062
    VST1d64QPseudo  = 797,
4063
    VST1LNd16_VST1LNd32_VST1LNd8  = 798,
4064
    VST1LNdAsm_16_VST1LNdAsm_32_VST1LNdAsm_8  = 799,
4065
    VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD  = 800,
4066
    VST1LNdWB_fixed_Asm_16_VST1LNdWB_fixed_Asm_32_VST1LNdWB_fixed_Asm_8_VST1LNdWB_register_Asm_16_VST1LNdWB_register_Asm_32_VST1LNdWB_register_Asm_8  = 801,
4067
    VST2q16_VST2q32_VST2q8  = 802,
4068
    VST2LNd16_VST2LNd32_VST2LNd8  = 803,
4069
    VST2LNdAsm_16_VST2LNdAsm_32_VST2LNdAsm_8  = 804,
4070
    VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo  = 805,
4071
    VST2LNq16_VST2LNq32 = 806,
4072
    VST2LNqAsm_16_VST2LNqAsm_32 = 807,
4073
    VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD  = 808,
4074
    VST2LNdWB_fixed_Asm_16_VST2LNdWB_fixed_Asm_32_VST2LNdWB_fixed_Asm_8_VST2LNdWB_register_Asm_16_VST2LNdWB_register_Asm_32_VST2LNdWB_register_Asm_8  = 809,
4075
    VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD  = 810,
4076
    VST2LNqWB_fixed_Asm_16_VST2LNqWB_fixed_Asm_32_VST2LNqWB_register_Asm_16_VST2LNqWB_register_Asm_32 = 811,
4077
    VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8 = 812,
4078
    VST3dAsm_16_VST3dAsm_32_VST3dAsm_8_VST3qAsm_16_VST3qAsm_32_VST3qAsm_8 = 813,
4079
    VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo  = 814,
4080
    VST3LNd16_VST3LNd32_VST3LNd8  = 815,
4081
    VST3LNdAsm_16_VST3LNdAsm_32_VST3LNdAsm_8  = 816,
4082
    VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo  = 817,
4083
    VST3LNqAsm_16_VST3LNqAsm_32 = 818,
4084
    VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD = 819,
4085
    VST3dWB_fixed_Asm_16_VST3dWB_fixed_Asm_32_VST3dWB_fixed_Asm_8_VST3dWB_register_Asm_16_VST3dWB_register_Asm_32_VST3dWB_register_Asm_8_VST3qWB_fixed_Asm_16_VST3qWB_fixed_Asm_32_VST3qWB_fixed_Asm_8_VST3qWB_register_Asm_16_VST3qWB_register_Asm_32_VST3qWB_register_Asm_8 = 820,
4086
    VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD  = 821,
4087
    VST3LNdWB_fixed_Asm_16_VST3LNdWB_fixed_Asm_32_VST3LNdWB_fixed_Asm_8_VST3LNdWB_register_Asm_16_VST3LNdWB_register_Asm_32_VST3LNdWB_register_Asm_8  = 822,
4088
    VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD  = 823,
4089
    VST3LNqWB_fixed_Asm_16_VST3LNqWB_fixed_Asm_32_VST3LNqWB_register_Asm_16_VST3LNqWB_register_Asm_32 = 824,
4090
    VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8 = 825,
4091
    VST4dAsm_16_VST4dAsm_32_VST4dAsm_8_VST4qAsm_16_VST4qAsm_32_VST4qAsm_8 = 826,
4092
    VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo  = 827,
4093
    VST4LNd16_VST4LNd32_VST4LNd8  = 828,
4094
    VST4LNdAsm_16_VST4LNdAsm_32_VST4LNdAsm_8  = 829,
4095
    VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo  = 830,
4096
    VST4LNq16_VST4LNq32 = 831,
4097
    VST4LNqAsm_16_VST4LNqAsm_32 = 832,
4098
    VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD = 833,
4099
    VST4dWB_fixed_Asm_16_VST4dWB_fixed_Asm_32_VST4dWB_fixed_Asm_8_VST4dWB_register_Asm_16_VST4dWB_register_Asm_32_VST4dWB_register_Asm_8_VST4qWB_fixed_Asm_16_VST4qWB_fixed_Asm_32_VST4qWB_fixed_Asm_8_VST4qWB_register_Asm_16_VST4qWB_register_Asm_32_VST4qWB_register_Asm_8 = 834,
4100
    VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD  = 835,
4101
    VST4LNdWB_fixed_Asm_16_VST4LNdWB_fixed_Asm_32_VST4LNdWB_fixed_Asm_8_VST4LNdWB_register_Asm_16_VST4LNdWB_register_Asm_32_VST4LNdWB_register_Asm_8  = 836,
4102
    VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD  = 837,
4103
    VST4LNqWB_fixed_Asm_16_VST4LNqWB_fixed_Asm_32_VST4LNqWB_register_Asm_16_VST4LNqWB_register_Asm_32 = 838,
4104
    BKPT_tBKPT_CDP_CDP2_t2CDP_t2CDP2_CLREX_t2CLREX_CONSTPOOL_ENTRY_COPY_STRUCT_BYVAL_I32_CPS1p_CPS2p_CPS3p_t2CPS1p_t2CPS2p_t2CPS3p_DBG_t2DBG_DMB_t2DMB_DSB_t2DSB_ERET_HINT_t2HINT_tHINT_HLT_tHLT_HVC_ISB_t2ISB_SETEND_tSETEND_SETPAN_t2SETPAN_SMC_t2SMC_SPACE_SWP_SWPB_TRAP_TRAPNaCl_UDF_t2DCPS1_t2DCPS2_t2DCPS3_t2SG_t2TT_t2TTA_t2TTAT_t2TTT_tCPS_CMP_SWAP_16_CMP_SWAP_32_CMP_SWAP_64_CMP_SWAP_8_CompilerBarrier = 839,
4105
    t2HVC_tTRAP_SVC_tSVC  = 840,
4106
    RFEDA_RFEDA_UPD_RFEDB_RFEDB_UPD_RFEIA_RFEIA_UPD_RFEIB_RFEIB_UPD_t2RFEDB_t2RFEDBW_t2RFEIA_t2RFEIAW_SRSDA_SRSDA_UPD_SRSDB_SRSDB_UPD_SRSIA_SRSIA_UPD_SRSIB_SRSIB_UPD_t2SRSDB_t2SRSDB_UPD_t2SRSIA_t2SRSIA_UPD = 841,
4107
    t2UDF_tUDF_t__brkdiv0 = 842,
4108
    LDC2L_OFFSET_LDC2L_OPTION_LDC2L_POST_LDC2L_PRE_LDC2_OFFSET_LDC2_OPTION_LDC2_POST_LDC2_PRE_LDCL_OFFSET_LDCL_OPTION_LDCL_POST_LDCL_PRE_LDC_OFFSET_LDC_OPTION_LDC_POST_LDC_PRE_STC2L_OFFSET_STC2L_OPTION_STC2L_POST_STC2L_PRE_STC2_OFFSET_STC2_OPTION_STC2_POST_STC2_PRE_STCL_OFFSET_STCL_OPTION_STCL_POST_STCL_PRE_STC_OFFSET_STC_OPTION_STC_POST_STC_PRE_t2STC2L_OFFSET_t2STC2L_OPTION_t2STC2L_POST_t2STC2L_PRE_t2STC2_OFFSET_t2STC2_OPTION_t2STC2_POST_t2STC2_PRE_t2STCL_OFFSET_t2STCL_OPTION_t2STCL_POST_t2STCL_PRE_t2STC_OFFSET_t2STC_OPTION_t2STC_POST_t2STC_PRE_MEMCPY  = 843,
4109
    t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE = 844,
4110
    LDREX_LDREXB_LDREXD_LDREXH  = 845,
4111
    MCR_MCR2_MCRR_MCRR2_t2MCR_t2MCR2_t2MCRR_t2MCRR2_MRC_MRC2_t2MRC_t2MRC2_MRRC_MRRC2_t2MRRC_t2MRRC2_t2MRS_AR_t2MRS_M_t2MRSbanked_t2MRSsys_AR_t2MSR_AR_t2MSR_M_t2MSRbanked = 846,
4112
    FLDMXDB_UPD_FLDMXIA_FLDMXIA_UPD_FSTMXDB_UPD_FSTMXIA_FSTMXIA_UPD = 847,
4113
    ADJCALLSTACKDOWN_tADJCALLSTACKDOWN_ADJCALLSTACKUP_tADJCALLSTACKUP_Int_eh_sjlj_dispatchsetup_Int_eh_sjlj_longjmp_Int_eh_sjlj_setjmp_Int_eh_sjlj_setjmp_nofp_Int_eh_sjlj_setup_dispatch_t2Int_eh_sjlj_setjmp_t2Int_eh_sjlj_setjmp_nofp_tInt_eh_sjlj_longjmp_tInt_eh_sjlj_setjmp_t2SUBS_PC_LR_JUMPTABLE_ADDRS_JUMPTABLE_INSTS_JUMPTABLE_TBB_JUMPTABLE_TBH_tInt_WIN_eh_sjlj_longjmp_VLD1LNdAsm_16_VLD1LNdAsm_32_VLD1LNdAsm_8_VLD1LNdWB_fixed_Asm_16_VLD1LNdWB_fixed_Asm_32_VLD1LNdWB_fixed_Asm_8_VLD1LNdWB_register_Asm_16_VLD1LNdWB_register_Asm_32_VLD1LNdWB_register_Asm_8_VLD2LNdAsm_16_VLD2LNdAsm_32_VLD2LNdAsm_8_VLD2LNdWB_fixed_Asm_16_VLD2LNdWB_fixed_Asm_32_VLD2LNdWB_fixed_Asm_8_VLD2LNdWB_register_Asm_16_VLD2LNdWB_register_Asm_32_VLD2LNdWB_register_Asm_8_VLD2LNqAsm_16_VLD2LNqAsm_32_VLD2LNqWB_fixed_Asm_16_VLD2LNqWB_fixed_Asm_32_VLD2LNqWB_register_Asm_16_VLD2LNqWB_register_Asm_32_VLD3DUPdAsm_16_VLD3DUPdAsm_32_VLD3DUPdAsm_8_VLD3DUPdWB_fixed_Asm_16_VLD3DUPdWB_fixed_Asm_32_VLD3DUPdWB_fixed_Asm_8_VLD3DUPdWB_register_Asm_16_VLD3DUPdWB_register_Asm_32_VLD3DUPdWB_register_Asm_8_VLD3DUPqAsm_16_VLD3DUPqAsm_32_VLD3DUPqAsm_8_VLD3DUPqWB_fixed_Asm_16_VLD3DUPqWB_fixed_Asm_32_VLD3DUPqWB_fixed_Asm_8_VLD3DUPqWB_register_Asm_16_VLD3DUPqWB_register_Asm_32_VLD3DUPqWB_register_Asm_8_VLD3LNdAsm_16_VLD3LNdAsm_32_VLD3LNdAsm_8_VLD3LNdWB_fixed_Asm_16_VLD3LNdWB_fixed_Asm_32_VLD3LNdWB_fixed_Asm_8_VLD3LNdWB_register_Asm_16_VLD3LNdWB_register_Asm_32_VLD3LNdWB_register_Asm_8_VLD3LNqAsm_16_VLD3LNqAsm_32_VLD3LNqWB_fixed_Asm_16_VLD3LNqWB_fixed_Asm_32_VLD3LNqWB_register_Asm_16_VLD3LNqWB_register_Asm_32_VLD3dAsm_16_VLD3dAsm_32_VLD3dAsm_8_VLD3dWB_fixed_Asm_16_VLD3dWB_fixed_Asm_32_VLD3dWB_fixed_Asm_8_VLD3dWB_register_Asm_16_VLD3dWB_register_Asm_32_VLD3dWB_register_Asm_8_VLD3qAsm_16_VLD3qAsm_32_VLD3qAsm_8_VLD3qWB_fixed_Asm_16_VLD3qWB_fixed_Asm_32_VLD3qWB_fixed_Asm_8_VLD3qWB_register_Asm_16_VLD3qWB_register_Asm_32_VLD3qWB_register_Asm_8_VLD4DUPdAsm_16_VLD4DUPdAsm_32_VLD4DUPdAsm_8_VLD4DUPdWB_fixed_Asm_16_VLD4DUPdWB_fixed_Asm_32_VLD4DUPdWB_fixed_Asm_8_VLD4DUPdWB_register_Asm_16_VLD4DUPdWB_register_Asm_32_VLD4DUPdWB_register_Asm_8_VLD4DUPqAsm_16_VLD4DUPqAsm_32_VLD4DUPqAsm_8_VLD4DUPqWB_fixed_Asm_16_VLD4DUPqWB_fixed_Asm_32_VLD4DUPqWB_fixed_Asm_8_VLD4DUPqWB_register_Asm_16_VLD4DUPqWB_register_Asm_32_VLD4DUPqWB_register_Asm_8_VLD4LNdAsm_16_VLD4LNdAsm_32_VLD4LNdAsm_8_VLD4LNdWB_fixed_Asm_16_VLD4LNdWB_fixed_Asm_32_VLD4LNdWB_fixed_Asm_8_VLD4LNdWB_register_Asm_16_VLD4LNdWB_register_Asm_32_VLD4LNdWB_register_Asm_8_VLD4LNqAsm_16_VLD4LNqAsm_32_VLD4LNqWB_fixed_Asm_16_VLD4LNqWB_fixed_Asm_32_VLD4LNqWB_register_Asm_16_VLD4LNqWB_register_Asm_32_VLD4dAsm_16_VLD4dAsm_32_VLD4dAsm_8_VLD4dWB_fixed_Asm_16_VLD4dWB_fixed_Asm_32_VLD4dWB_fixed_Asm_8_VLD4dWB_register_Asm_16_VLD4dWB_register_Asm_32_VLD4dWB_register_Asm_8_VLD4qAsm_16_VLD4qAsm_32_VLD4qAsm_8_VLD4qWB_fixed_Asm_16_VLD4qWB_fixed_Asm_32_VLD4qWB_fixed_Asm_8_VLD4qWB_register_Asm_16_VLD4qWB_register_Asm_32_VLD4qWB_register_Asm_8_WIN__CHKSTK_WIN__DBZCHK = 848,
4114
    SUBS_PC_LR  = 849,
4115
    B_t2B_tB_BX_CALL_tBX_CALL_tBX_RET_tBX_RET_vararg_BX_BX_RET_BX_pred_tBX_tBXNS_Bcc_t2Bcc_tBcc_TAILJMPd_TAILJMPr_TAILJMPr4_tTAILJMPd_tTAILJMPdND_tTAILJMPr_TCRETURNdi_TCRETURNri_tCBNZ_tCBZ  = 850,
4116
    BXJ = 851,
4117
    tBfar = 852,
4118
    BL_tBL_BL_pred_tBLXi  = 853,
4119
    BLXi  = 854,
4120
    TPsoft_tTPsoft  = 855,
4121
    BLX_BLX_pred_tBLXNSr_tBLXr  = 856,
4122
    BCCi64_BCCZi64  = 857,
4123
    BR_JTadd_tBR_JTr_t2TBB_t2TBH  = 858,
4124
    BR_JTr_t2BR_JT_t2TBB_JT_t2TBH_JT_tBRIND = 859,
4125
    t2BXJ = 860,
4126
    BR_JTm_i12_BR_JTm_rs  = 861,
4127
    tADDframe = 862,
4128
    MOVi16_ga_pcrel_MOVi_MOVi16_MOVCCi16_tMOVi8 = 863,
4129
    MOVr_MOVr_TC_tMOVSr_tMOVr = 864,
4130
    MVNCCi_MOVCCi = 865,
4131
    BMOVPCB_CALL_BMOVPCRX_CALL  = 866,
4132
    MOVCCr  = 867,
4133
    tMOVCCr_pseudo  = 868,
4134
    tMVN  = 869,
4135
    MOVCCsi = 870,
4136
    t2ASRri_tASRri_t2LSRri_tLSRri_t2LSLri_tLSLri_t2RORri_t2RRX  = 871,
4137
    LSRi_LSLi = 872,
4138
    t2MOVCCasr_t2MOVCClsl_t2MOVCClsr_t2MOVCCror = 873,
4139
    t2MOVCCr  = 874,
4140
    t2MOVTi16_ga_pcrel_t2MOVTi16  = 875,
4141
    t2MOVr  = 876,
4142
    tROR  = 877,
4143
    t2ASRrr_tASRrr_t2LSRrr_tLSRrr_t2LSLrr_tLSLrr_t2RORrr  = 878,
4144
    MOVPCRX_MOVPCLR = 879,
4145
    tMUL  = 880,
4146
    SADD16_SADD8_SSUB16_SSUB8_UADD16_UADD8_USUB16_USUB8 = 881,
4147
    t2SADD16_t2SADD8_t2SSUB16_t2SSUB8_t2UADD16_t2UADD8_t2USUB16_t2USUB8 = 882,
4148
    SHADD16_SHADD8_SHSUB16_SHSUB8_UHADD16_UHADD8_UHSUB16_UHSUB8 = 883,
4149
    t2SHADD16_t2SHADD8_t2SHSUB16_t2SHSUB8_t2UHADD16_t2UHADD8_t2UHSUB16_t2UHSUB8 = 884,
4150
    QADD16_QADD8_QSUB16_QSUB8_UQADD16_UQADD8_UQSUB16_UQSUB8 = 885,
4151
    t2QADD_t2QADD16_t2QADD8_t2UQADD16_t2UQADD8_t2QSUB_t2QSUB16_t2QSUB8_t2UQSUB16_t2UQSUB8 = 886,
4152
    QASX_QSAX_UQASX_UQSAX = 887,
4153
    t2QASX_t2QSAX_t2UQASX_t2UQSAX = 888,
4154
    SSAT_SSAT16_t2SSAT_t2SSAT16_USAT_USAT16_t2USAT_t2USAT16 = 889,
4155
    QADD_QSUB = 890,
4156
    SBFX_UBFX = 891,
4157
    t2SBFX_t2UBFX = 892,
4158
    SXTB_SXTH_UXTB_UXTH = 893,
4159
    t2SXTB_t2SXTH_t2UXTB_t2UXTH = 894,
4160
    tSXTB_tSXTH_tUXTB_tUXTH = 895,
4161
    SXTAB_SXTAH_UXTAB_UXTAH = 896,
4162
    t2SXTAB_t2SXTAH_t2UXTAB_t2UXTAH = 897,
4163
    LDRConstPool_t2LDRConstPool_tLDRConstPool = 898,
4164
    PICLDRB_PICLDRH = 899,
4165
    PICLDRSB_PICLDRSH = 900,
4166
    tLDR_postidx  = 901,
4167
    t2LDRBpcrel_t2LDRHpcrel_t2LDRpcrel  = 902,
4168
    LDR_PRE_IMM = 903,
4169
    LDRB_PRE_IMM  = 904,
4170
    t2LDRB_PRE  = 905,
4171
    LDR_PRE_REG = 906,
4172
    LDRB_PRE_REG  = 907,
4173
    LDRH_PRE  = 908,
4174
    LDRSB_PRE_LDRSH_PRE = 909,
4175
    t2LDRH_PRE  = 910,
4176
    t2LDRSB_PRE_t2LDRSH_PRE = 911,
4177
    t2LDR_PRE = 912,
4178
    LDRD_PRE  = 913,
4179
    t2LDRD_PRE  = 914,
4180
    LDRT_POST_IMM = 915,
4181
    LDRBT_POST_IMM  = 916,
4182
    LDRHTi  = 917,
4183
    LDRSBTi_LDRSHTi = 918,
4184
    LDRH_POST = 919,
4185
    LDRSB_POST_LDRSH_POST = 920,
4186
    LDR_POST_REG  = 921,
4187
    LDRB_POST_REG = 922,
4188
    LDRT_POST = 923,
4189
    PLDi12_t2PLDi12_PLDWi12_t2PLDWi12_t2PLDWi8_t2PLDWs_t2PLDi8_t2PLDpci_t2PLDs_PLIi12_PLIrs_t2PLIi12_t2PLIi8_t2PLIpci_t2PLIs  = 924,
4190
    PLDrs_PLDWrs  = 925,
4191
    VLLDM = 926,
4192
    STRBi12_PICSTRB_PICSTRH_tSTRBr_tSTRHr = 927,
4193
    t2STRBT = 928,
4194
    STR_PRE_IMM = 929,
4195
    STRB_PRE_IMM  = 930,
4196
    STRBi_preidx_STRBr_preidx_STRi_preidx_STRr_preidx_STRH_preidx = 931,
4197
    STRH_PRE  = 932,
4198
    t2STRH_PRE_t2STR_PRE  = 933,
4199
    t2STRB_PRE  = 934,
4200
    t2STRD_PRE  = 935,
4201
    STR_PRE_REG = 936,
4202
    STRB_PRE_REG  = 937,
4203
    STRD_PRE  = 938,
4204
    STRT_POST_IMM = 939,
4205
    STRBT_POST_IMM  = 940,
4206
    t2STRB_POST = 941,
4207
    STRBT_POST_REG_STRB_POST_REG  = 942,
4208
    VLSTM = 943,
4209
    VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTBDH_VCVTTDH_VCVTTHD = 944,
4210
    VJCVT = 945,
4211
    VRINTAD_VRINTAH_VRINTAS_VRINTMD_VRINTMH_VRINTMS_VRINTND_VRINTNH_VRINTNS_VRINTPD_VRINTPH_VRINTPS_VRINTRD_VRINTRH_VRINTRS_VRINTXD_VRINTXH_VRINTXS_VRINTZD_VRINTZH_VRINTZS = 946,
4212
    VSQRTH  = 947,
4213
    VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8 = 948,
4214
    VUDOTD_VUDOTDI_VSDOTD_VSDOTDI_VUDOTQ_VUDOTQI_VSDOTQ_VSDOTQI = 949,
4215
    FCONSTD = 950,
4216
    FCONSTH = 951,
4217
    FCONSTS = 952,
4218
    VMOVH = 953,
4219
    VINSH = 954,
4220
    VSTMSIA = 955,
4221
    VSTMSDB_UPD_VSTMSIA_UPD = 956,
4222
    VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16 = 957,
4223
    VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8 = 958,
4224
    VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 959,
4225
    VMULpd_VMULv4i16_VMULv8i8_VMULslv4i16 = 960,
4226
    VMULv2i32_VMULslv2i32 = 961,
4227
    VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32 = 962,
4228
    VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16 = 963,
4229
    VMULpq_VMULv16i8_VMULv8i16_VMULslv8i16  = 964,
4230
    VMLAslv2i32_VMLAv2i32_VMLSslv2i32_VMLSv2i32 = 965,
4231
    VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSslv4i16_VMLSv4i16_VMLSv8i8 = 966,
4232
    VQRDMLAHslv2i32_VQRDMLAHv2i32_VQRDMLSHslv2i32_VQRDMLSHv2i32 = 967,
4233
    VQRDMLAHslv4i16_VQRDMLAHv4i16_VQRDMLSHslv4i16_VQRDMLSHv4i16 = 968,
4234
    VQRDMLAHslv4i32_VQRDMLAHv4i32_VQRDMLSHslv4i32_VQRDMLSHv4i32 = 969,
4235
    VQRDMLAHslv8i16_VQRDMLAHv8i16_VQRDMLSHslv8i16_VQRDMLSHv8i16 = 970,
4236
    VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16 = 971,
4237
    VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8  = 972,
4238
    VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8  = 973,
4239
    VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 974,
4240
    VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8 = 975,
4241
    VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 976,
4242
    VPADDh  = 977,
4243
    VCADDv2f32_VCADDv4f16_VCMLAv2f32_VCMLAv2f32_indexed_VCMLAv4f16_VCMLAv4f16_indexed = 978,
4244
    VCADDv4f32_VCADDv8f16_VCMLAv4f32_VCMLAv4f32_indexed_VCMLAv8f16_VCMLAv8f16_indexed = 979,
4245
    VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTs2fd_VCVTu2fd_VCVTxs2fd_VCVTxu2fd = 980,
4246
    VCVTf2sq_VCVTf2uq_VCVTs2fq_VCVTu2fq_VCVTf2xsq_VCVTf2xuq_VCVTxs2fq_VCVTxu2fq = 981,
4247
    VMULhd  = 982,
4248
    VMULhq  = 983,
4249
    VRINTANDf_VRINTANDh_VRINTANQf_VRINTANQh_VRINTMNDf_VRINTMNDh_VRINTMNQf_VRINTMNQh_VRINTNNDf_VRINTNNDh_VRINTNNQf_VRINTNNQh_VRINTPNDf_VRINTPNDh_VRINTPNQf_VRINTPNQh_VRINTXNDf_VRINTXNDh_VRINTXNQf_VRINTXNQh_VRINTZNDf_VRINTZNDh_VRINTZNQf_VRINTZNQh = 984,
4250
    VMOVD0_VMOVQ0 = 985,
4251
    VTRNd16_VTRNd32_VTRNd8  = 986,
4252
    VLD2d16_VLD2d32_VLD2d8  = 987,
4253
    VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register  = 988,
4254
    VLD3LNd32_VLD3LNq32_VLD3LNd32Pseudo_VLD3LNq32Pseudo = 989,
4255
    VLD3LNd32_UPD_VLD3LNq32_UPD = 990,
4256
    VLD3LNd32Pseudo_UPD_VLD3LNq32Pseudo_UPD = 991,
4257
    VLD4LNd32_VLD4LNq32_VLD4LNd32Pseudo_VLD4LNq32Pseudo = 992,
4258
    VLD4LNd32_UPD_VLD4LNq32_UPD = 993,
4259
    VLD4LNd32Pseudo_UPD_VLD4LNq32Pseudo_UPD = 994,
4260
    AESD_AESE_AESIMC_AESMC  = 995,
4261
    SHA1SU0 = 996,
4262
    SHA1H_SHA1SU1 = 997,
4263
    SHA1C_SHA1M_SHA1P = 998,
4264
    SHA256SU0 = 999,
4265
    SHA256H_SHA256H2_SHA256SU1  = 1000,
4266
    SCHED_LIST_END = 1001
4267
  };
4268
} // end Sched namespace
4269
} // end ARM namespace
4270
} // end llvm namespace
4271
#endif // GET_INSTRINFO_SCHED_ENUM
4272
4273
#ifdef GET_INSTRINFO_MC_DESC
4274
#undef GET_INSTRINFO_MC_DESC
4275
namespace llvm {
4276
4277
static const MCPhysReg ImplicitList1[] = { ARM::CPSR, 0 };
4278
static const MCPhysReg ImplicitList2[] = { ARM::SP, 0 };
4279
static const MCPhysReg ImplicitList3[] = { ARM::LR, 0 };
4280
static const MCPhysReg ImplicitList4[] = { ARM::R7, ARM::LR, ARM::SP, 0 };
4281
static const MCPhysReg ImplicitList5[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
4282
static const MCPhysReg ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, 0 };
4283
static const MCPhysReg ImplicitList7[] = { ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, 0 };
4284
static const MCPhysReg ImplicitList8[] = { ARM::R4, 0 };
4285
static const MCPhysReg ImplicitList9[] = { ARM::R4, ARM::SP, 0 };
4286
static const MCPhysReg ImplicitList10[] = { ARM::PC, 0 };
4287
static const MCPhysReg ImplicitList11[] = { ARM::FPSCR_NZCV, 0 };
4288
static const MCPhysReg ImplicitList12[] = { ARM::FPSCR, 0 };
4289
static const MCPhysReg ImplicitList13[] = { ARM::ITSTATE, 0 };
4290
static const MCPhysReg ImplicitList14[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
4291
static const MCPhysReg ImplicitList15[] = { ARM::R11, ARM::LR, ARM::SP, 0 };
4292
static const MCPhysReg ImplicitList16[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR, 0 };
4293
4294
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4295
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4296
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4297
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4298
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4299
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4300
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4301
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4302
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4303
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4304
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4305
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4306
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4307
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4308
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4309
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
4310
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4311
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4312
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4313
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4314
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4315
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
4316
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
4317
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4318
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
4319
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4320
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
4321
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
4322
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
4323
static const MCOperandInfo OperandInfo31[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4324
static const MCOperandInfo OperandInfo32[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4325
static const MCOperandInfo OperandInfo33[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4326
static const MCOperandInfo OperandInfo34[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4327
static const MCOperandInfo OperandInfo35[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4328
static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4329
static const MCOperandInfo OperandInfo37[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4330
static const MCOperandInfo OperandInfo38[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4331
static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
4332
static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
4333
static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
4334
static const MCOperandInfo OperandInfo42[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4335
static const MCOperandInfo OperandInfo43[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4336
static const MCOperandInfo OperandInfo44[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4337
static const MCOperandInfo OperandInfo45[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4338
static const MCOperandInfo OperandInfo46[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4339
static const MCOperandInfo OperandInfo47[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4340
static const MCOperandInfo OperandInfo48[] = { { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4341
static const MCOperandInfo OperandInfo49[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4342
static const MCOperandInfo OperandInfo50[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4343
static const MCOperandInfo OperandInfo51[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4344
static const MCOperandInfo OperandInfo52[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4345
static const MCOperandInfo OperandInfo53[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4346
static const MCOperandInfo OperandInfo54[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4347
static const MCOperandInfo OperandInfo55[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4348
static const MCOperandInfo OperandInfo56[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4349
static const MCOperandInfo OperandInfo57[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4350
static const MCOperandInfo OperandInfo58[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4351
static const MCOperandInfo OperandInfo59[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4352
static const MCOperandInfo OperandInfo60[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4353
static const MCOperandInfo OperandInfo61[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4354
static const MCOperandInfo OperandInfo62[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4355
static const MCOperandInfo OperandInfo63[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4356
static const MCOperandInfo OperandInfo64[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4357
static const MCOperandInfo OperandInfo65[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4358
static const MCOperandInfo OperandInfo66[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4359
static const MCOperandInfo OperandInfo67[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4360
static const MCOperandInfo OperandInfo68[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4361
static const MCOperandInfo OperandInfo69[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4362
static const MCOperandInfo OperandInfo70[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4363
static const MCOperandInfo OperandInfo71[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4364
static const MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4365
static const MCOperandInfo OperandInfo73[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4366
static const MCOperandInfo OperandInfo74[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4367
static const MCOperandInfo OperandInfo75[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4368
static const MCOperandInfo OperandInfo76[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4369
static const MCOperandInfo OperandInfo77[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4370
static const MCOperandInfo OperandInfo78[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4371
static const MCOperandInfo OperandInfo79[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4372
static const MCOperandInfo OperandInfo80[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4373
static const MCOperandInfo OperandInfo81[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4374
static const MCOperandInfo OperandInfo82[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4375
static const MCOperandInfo OperandInfo83[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4376
static const MCOperandInfo OperandInfo84[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4377
static const MCOperandInfo OperandInfo85[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4378
static const MCOperandInfo OperandInfo86[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4379
static const MCOperandInfo OperandInfo87[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4380
static const MCOperandInfo OperandInfo88[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4381
static const MCOperandInfo OperandInfo89[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4382
static const MCOperandInfo OperandInfo90[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4383
static const MCOperandInfo OperandInfo91[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4384
static const MCOperandInfo OperandInfo92[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4385
static const MCOperandInfo OperandInfo93[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4386
static const MCOperandInfo OperandInfo94[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4387
static const MCOperandInfo OperandInfo95[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4388
static const MCOperandInfo OperandInfo96[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4389
static const MCOperandInfo OperandInfo97[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4390
static const MCOperandInfo OperandInfo98[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4391
static const MCOperandInfo OperandInfo99[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4392
static const MCOperandInfo OperandInfo100[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4393
static const MCOperandInfo OperandInfo101[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4394
static const MCOperandInfo OperandInfo102[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4395
static const MCOperandInfo OperandInfo103[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4396
static const MCOperandInfo OperandInfo104[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4397
static const MCOperandInfo OperandInfo105[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4398
static const MCOperandInfo OperandInfo106[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4399
static const MCOperandInfo OperandInfo107[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4400
static const MCOperandInfo OperandInfo108[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4401
static const MCOperandInfo OperandInfo109[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4402
static const MCOperandInfo OperandInfo110[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4403
static const MCOperandInfo OperandInfo111[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4404
static const MCOperandInfo OperandInfo112[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4405
static const MCOperandInfo OperandInfo113[] = { { ARM::tGPRwithpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4406
static const MCOperandInfo OperandInfo114[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4407
static const MCOperandInfo OperandInfo115[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4408
static const MCOperandInfo OperandInfo116[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4409
static const MCOperandInfo OperandInfo117[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4410
static const MCOperandInfo OperandInfo118[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4411
static const MCOperandInfo OperandInfo119[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4412
static const MCOperandInfo OperandInfo120[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4413
static const MCOperandInfo OperandInfo121[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4414
static const MCOperandInfo OperandInfo122[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4415
static const MCOperandInfo OperandInfo123[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4416
static const MCOperandInfo OperandInfo124[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4417
static const MCOperandInfo OperandInfo125[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4418
static const MCOperandInfo OperandInfo126[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4419
static const MCOperandInfo OperandInfo127[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4420
static const MCOperandInfo OperandInfo128[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4421
static const MCOperandInfo OperandInfo129[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4422
static const MCOperandInfo OperandInfo130[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4423
static const MCOperandInfo OperandInfo131[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4424
static const MCOperandInfo OperandInfo132[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4425
static const MCOperandInfo OperandInfo133[] = { { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4426
static const MCOperandInfo OperandInfo134[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4427
static const MCOperandInfo OperandInfo135[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4428
static const MCOperandInfo OperandInfo136[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4429
static const MCOperandInfo OperandInfo137[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4430
static const MCOperandInfo OperandInfo138[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4431
static const MCOperandInfo OperandInfo139[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4432
static const MCOperandInfo OperandInfo140[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4433
static const MCOperandInfo OperandInfo141[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4434
static const MCOperandInfo OperandInfo142[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4435
static const MCOperandInfo OperandInfo143[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4436
static const MCOperandInfo OperandInfo144[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4437
static const MCOperandInfo OperandInfo145[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4438
static const MCOperandInfo OperandInfo146[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4439
static const MCOperandInfo OperandInfo147[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4440
static const MCOperandInfo OperandInfo148[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4441
static const MCOperandInfo OperandInfo149[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4442
static const MCOperandInfo OperandInfo150[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4443
static const MCOperandInfo OperandInfo151[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4444
static const MCOperandInfo OperandInfo152[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4445
static const MCOperandInfo OperandInfo153[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4446
static const MCOperandInfo OperandInfo154[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4447
static const MCOperandInfo OperandInfo155[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4448
static const MCOperandInfo OperandInfo156[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4449
static const MCOperandInfo OperandInfo157[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4450
static const MCOperandInfo OperandInfo158[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4451
static const MCOperandInfo OperandInfo159[] = { { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4452
static const MCOperandInfo OperandInfo160[] = { { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4453
static const MCOperandInfo OperandInfo161[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4454
static const MCOperandInfo OperandInfo162[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4455
static const MCOperandInfo OperandInfo163[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4456
static const MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4457
static const MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4458
static const MCOperandInfo OperandInfo166[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4459
static const MCOperandInfo OperandInfo167[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4460
static const MCOperandInfo OperandInfo168[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4461
static const MCOperandInfo OperandInfo169[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4462
static const MCOperandInfo OperandInfo170[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4463
static const MCOperandInfo OperandInfo171[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4464
static const MCOperandInfo OperandInfo172[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4465
static const MCOperandInfo OperandInfo173[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4466
static const MCOperandInfo OperandInfo174[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4467
static const MCOperandInfo OperandInfo175[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4468
static const MCOperandInfo OperandInfo176[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4469
static const MCOperandInfo OperandInfo177[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4470
static const MCOperandInfo OperandInfo178[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4471
static const MCOperandInfo OperandInfo179[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4472
static const MCOperandInfo OperandInfo180[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4473
static const MCOperandInfo OperandInfo181[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4474
static const MCOperandInfo OperandInfo182[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4475
static const MCOperandInfo OperandInfo183[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4476
static const MCOperandInfo OperandInfo184[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4477
static const MCOperandInfo OperandInfo185[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4478
static const MCOperandInfo OperandInfo186[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4479
static const MCOperandInfo OperandInfo187[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4480
static const MCOperandInfo OperandInfo188[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4481
static const MCOperandInfo OperandInfo189[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4482
static const MCOperandInfo OperandInfo190[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4483
static const MCOperandInfo OperandInfo191[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4484
static const MCOperandInfo OperandInfo192[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4485
static const MCOperandInfo OperandInfo193[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4486
static const MCOperandInfo OperandInfo194[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4487
static const MCOperandInfo OperandInfo195[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4488
static const MCOperandInfo OperandInfo196[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4489
static const MCOperandInfo OperandInfo197[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4490
static const MCOperandInfo OperandInfo198[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4491
static const MCOperandInfo OperandInfo199[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4492
static const MCOperandInfo OperandInfo200[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4493
static const MCOperandInfo OperandInfo201[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4494
static const MCOperandInfo OperandInfo202[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4495
static const MCOperandInfo OperandInfo203[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4496
static const MCOperandInfo OperandInfo204[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4497
static const MCOperandInfo OperandInfo205[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4498
static const MCOperandInfo OperandInfo206[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4499
static const MCOperandInfo OperandInfo207[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4500
static const MCOperandInfo OperandInfo208[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4501
static const MCOperandInfo OperandInfo209[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4502
static const MCOperandInfo OperandInfo210[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4503
static const MCOperandInfo OperandInfo211[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4504
static const MCOperandInfo OperandInfo212[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4505
static const MCOperandInfo OperandInfo213[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4506
static const MCOperandInfo OperandInfo214[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4507
static const MCOperandInfo OperandInfo215[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4508
static const MCOperandInfo OperandInfo216[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4509
static const MCOperandInfo OperandInfo217[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4510
static const MCOperandInfo OperandInfo218[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4511
static const MCOperandInfo OperandInfo219[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4512
static const MCOperandInfo OperandInfo220[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4513
static const MCOperandInfo OperandInfo221[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4514
static const MCOperandInfo OperandInfo222[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4515
static const MCOperandInfo OperandInfo223[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4516
static const MCOperandInfo OperandInfo224[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4517
static const MCOperandInfo OperandInfo225[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4518
static const MCOperandInfo OperandInfo226[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4519
static const MCOperandInfo OperandInfo227[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4520
static const MCOperandInfo OperandInfo228[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4521
static const MCOperandInfo OperandInfo229[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4522
static const MCOperandInfo OperandInfo230[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4523
static const MCOperandInfo OperandInfo231[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4524
static const MCOperandInfo OperandInfo232[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4525
static const MCOperandInfo OperandInfo233[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4526
static const MCOperandInfo OperandInfo234[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4527
static const MCOperandInfo OperandInfo235[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4528
static const MCOperandInfo OperandInfo236[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4529
static const MCOperandInfo OperandInfo237[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4530
static const MCOperandInfo OperandInfo238[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4531
static const MCOperandInfo OperandInfo239[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4532
static const MCOperandInfo OperandInfo240[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4533
static const MCOperandInfo OperandInfo241[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4534
static const MCOperandInfo OperandInfo242[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4535
static const MCOperandInfo OperandInfo243[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4536
static const MCOperandInfo OperandInfo244[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4537
static const MCOperandInfo OperandInfo245[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4538
static const MCOperandInfo OperandInfo246[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4539
static const MCOperandInfo OperandInfo247[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4540
static const MCOperandInfo OperandInfo248[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4541
static const MCOperandInfo OperandInfo249[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4542
static const MCOperandInfo OperandInfo250[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4543
static const MCOperandInfo OperandInfo251[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4544
static const MCOperandInfo OperandInfo252[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4545
static const MCOperandInfo OperandInfo253[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4546
static const MCOperandInfo OperandInfo254[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4547
static const MCOperandInfo OperandInfo255[] = { { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4548
static const MCOperandInfo OperandInfo256[] = { { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4549
static const MCOperandInfo OperandInfo257[] = { { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4550
static const MCOperandInfo OperandInfo258[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4551
static const MCOperandInfo OperandInfo259[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4552
static const MCOperandInfo OperandInfo260[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4553
static const MCOperandInfo OperandInfo261[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4554
static const MCOperandInfo OperandInfo262[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4555
static const MCOperandInfo OperandInfo263[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4556
static const MCOperandInfo OperandInfo264[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4557
static const MCOperandInfo OperandInfo265[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4558
static const MCOperandInfo OperandInfo266[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4559
static const MCOperandInfo OperandInfo267[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4560
static const MCOperandInfo OperandInfo268[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4561
static const MCOperandInfo OperandInfo269[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4562
static const MCOperandInfo OperandInfo270[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((4 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4563
static const MCOperandInfo OperandInfo271[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4564
static const MCOperandInfo OperandInfo272[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((4 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4565
static const MCOperandInfo OperandInfo273[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4566
static const MCOperandInfo OperandInfo274[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4567
static const MCOperandInfo OperandInfo275[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4568
static const MCOperandInfo OperandInfo276[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4569
static const MCOperandInfo OperandInfo277[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4570
static const MCOperandInfo OperandInfo278[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4571
static const MCOperandInfo OperandInfo279[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4572
static const MCOperandInfo OperandInfo280[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4573
static const MCOperandInfo OperandInfo281[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4574
static const MCOperandInfo OperandInfo282[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4575
static const MCOperandInfo OperandInfo283[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4576
static const MCOperandInfo OperandInfo284[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4577
static const MCOperandInfo OperandInfo285[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4578
static const MCOperandInfo OperandInfo286[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4579
static const MCOperandInfo OperandInfo287[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4580
static const MCOperandInfo OperandInfo288[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4581
static const MCOperandInfo OperandInfo289[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4582
static const MCOperandInfo OperandInfo290[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4583
static const MCOperandInfo OperandInfo291[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4584
static const MCOperandInfo OperandInfo292[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4585
static const MCOperandInfo OperandInfo293[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4586
static const MCOperandInfo OperandInfo294[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4587
static const MCOperandInfo OperandInfo295[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4588
static const MCOperandInfo OperandInfo296[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4589
static const MCOperandInfo OperandInfo297[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4590
static const MCOperandInfo OperandInfo298[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4591
static const MCOperandInfo OperandInfo299[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4592
static const MCOperandInfo OperandInfo300[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4593
static const MCOperandInfo OperandInfo301[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4594
static const MCOperandInfo OperandInfo302[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4595
static const MCOperandInfo OperandInfo303[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4596
static const MCOperandInfo OperandInfo304[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4597
static const MCOperandInfo OperandInfo305[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4598
static const MCOperandInfo OperandInfo306[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4599
static const MCOperandInfo OperandInfo307[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4600
static const MCOperandInfo OperandInfo308[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4601
static const MCOperandInfo OperandInfo309[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4602
static const MCOperandInfo OperandInfo310[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4603
static const MCOperandInfo OperandInfo311[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4604
static const MCOperandInfo OperandInfo312[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4605
static const MCOperandInfo OperandInfo313[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4606
static const MCOperandInfo OperandInfo314[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4607
static const MCOperandInfo OperandInfo315[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4608
static const MCOperandInfo OperandInfo316[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4609
static const MCOperandInfo OperandInfo317[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4610
static const MCOperandInfo OperandInfo318[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4611
static const MCOperandInfo OperandInfo319[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4612
static const MCOperandInfo OperandInfo320[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4613
static const MCOperandInfo OperandInfo321[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4614
static const MCOperandInfo OperandInfo322[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4615
static const MCOperandInfo OperandInfo323[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4616
static const MCOperandInfo OperandInfo324[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4617
static const MCOperandInfo OperandInfo325[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4618
static const MCOperandInfo OperandInfo326[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4619
static const MCOperandInfo OperandInfo327[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4620
static const MCOperandInfo OperandInfo328[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4621
static const MCOperandInfo OperandInfo329[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4622
static const MCOperandInfo OperandInfo330[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4623
static const MCOperandInfo OperandInfo331[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4624
static const MCOperandInfo OperandInfo332[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4625
static const MCOperandInfo OperandInfo333[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4626
static const MCOperandInfo OperandInfo334[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4627
static const MCOperandInfo OperandInfo335[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4628
static const MCOperandInfo OperandInfo336[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4629
static const MCOperandInfo OperandInfo337[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4630
static const MCOperandInfo OperandInfo338[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4631
static const MCOperandInfo OperandInfo339[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4632
static const MCOperandInfo OperandInfo340[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4633
static const MCOperandInfo OperandInfo341[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4634
static const MCOperandInfo OperandInfo342[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4635
static const MCOperandInfo OperandInfo343[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4636
static const MCOperandInfo OperandInfo344[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4637
static const MCOperandInfo OperandInfo345[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4638
static const MCOperandInfo OperandInfo346[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4639
static const MCOperandInfo OperandInfo347[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4640
static const MCOperandInfo OperandInfo348[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4641
static const MCOperandInfo OperandInfo349[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4642
static const MCOperandInfo OperandInfo350[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4643
static const MCOperandInfo OperandInfo351[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4644
static const MCOperandInfo OperandInfo352[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4645
static const MCOperandInfo OperandInfo353[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4646
static const MCOperandInfo OperandInfo354[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4647
static const MCOperandInfo OperandInfo355[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4648
static const MCOperandInfo OperandInfo356[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4649
static const MCOperandInfo OperandInfo357[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4650
static const MCOperandInfo OperandInfo358[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4651
static const MCOperandInfo OperandInfo359[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4652
static const MCOperandInfo OperandInfo360[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4653
static const MCOperandInfo OperandInfo361[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4654
static const MCOperandInfo OperandInfo362[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4655
static const MCOperandInfo OperandInfo363[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4656
static const MCOperandInfo OperandInfo364[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4657
static const MCOperandInfo OperandInfo365[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4658
static const MCOperandInfo OperandInfo366[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4659
static const MCOperandInfo OperandInfo367[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4660
static const MCOperandInfo OperandInfo368[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4661
static const MCOperandInfo OperandInfo369[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4662
static const MCOperandInfo OperandInfo370[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4663
static const MCOperandInfo OperandInfo371[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4664
static const MCOperandInfo OperandInfo372[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4665
static const MCOperandInfo OperandInfo373[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4666
static const MCOperandInfo OperandInfo374[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4667
static const MCOperandInfo OperandInfo375[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4668
static const MCOperandInfo OperandInfo376[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4669
static const MCOperandInfo OperandInfo377[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4670
static const MCOperandInfo OperandInfo378[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4671
static const MCOperandInfo OperandInfo379[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4672
static const MCOperandInfo OperandInfo380[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4673
static const MCOperandInfo OperandInfo381[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4674
static const MCOperandInfo OperandInfo382[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4675
static const MCOperandInfo OperandInfo383[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
4676
static const MCOperandInfo OperandInfo384[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4677
static const MCOperandInfo OperandInfo385[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4678
static const MCOperandInfo OperandInfo386[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4679
static const MCOperandInfo OperandInfo387[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4680
static const MCOperandInfo OperandInfo388[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4681
static const MCOperandInfo OperandInfo389[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4682
static const MCOperandInfo OperandInfo390[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4683
static const MCOperandInfo OperandInfo391[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4684
static const MCOperandInfo OperandInfo392[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4685
static const MCOperandInfo OperandInfo393[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4686
static const MCOperandInfo OperandInfo394[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4687
static const MCOperandInfo OperandInfo395[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4688
static const MCOperandInfo OperandInfo396[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4689
static const MCOperandInfo OperandInfo397[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4690
static const MCOperandInfo OperandInfo398[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4691
static const MCOperandInfo OperandInfo399[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4692
static const MCOperandInfo OperandInfo400[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4693
static const MCOperandInfo OperandInfo401[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4694
static const MCOperandInfo OperandInfo402[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4695
static const MCOperandInfo OperandInfo403[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4696
static const MCOperandInfo OperandInfo404[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4697
static const MCOperandInfo OperandInfo405[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4698
static const MCOperandInfo OperandInfo406[] = { { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4699
static const MCOperandInfo OperandInfo407[] = { { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4700
static const MCOperandInfo OperandInfo408[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4701
static const MCOperandInfo OperandInfo409[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
4702
static const MCOperandInfo OperandInfo410[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4703
static const MCOperandInfo OperandInfo411[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4704
static const MCOperandInfo OperandInfo412[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
4705
static const MCOperandInfo OperandInfo413[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4706
static const MCOperandInfo OperandInfo414[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4707
static const MCOperandInfo OperandInfo415[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4708
static const MCOperandInfo OperandInfo416[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4709
static const MCOperandInfo OperandInfo417[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4710
static const MCOperandInfo OperandInfo418[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4711
static const MCOperandInfo OperandInfo419[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4712
static const MCOperandInfo OperandInfo420[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
4713
static const MCOperandInfo OperandInfo421[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4714
static const MCOperandInfo OperandInfo422[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4715
4716
extern const MCInstrDesc ARMInsts[] = {
4717
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
4718
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
4719
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
4720
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
4721
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
4722
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
4723
  { 6,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
4724
  { 7,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
4725
  { 8,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
4726
  { 9,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
4727
  { 10, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
4728
  { 11, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
4729
  { 12, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
4730
  { 13, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
4731
  { 14, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
4732
  { 15, 2,  1,  0,  678,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
4733
  { 16, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
4734
  { 17, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
4735
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
4736
  { 19, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
4737
  { 20, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
4738
  { 21, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
4739
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
4740
  { 23, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
4741
  { 24, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
4742
  { 25, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
4743
  { 26, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
4744
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
4745
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
4746
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
4747
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
4748
  { 31, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
4749
  { 32, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
4750
  { 33, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
4751
  { 34, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
4752
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
4753
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
4754
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
4755
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
4756
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
4757
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
4758
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
4759
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
4760
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
4761
  { 44, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
4762
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
4763
  { 46, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
4764
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
4765
  { 48, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
4766
  { 49, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
4767
  { 50, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
4768
  { 51, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
4769
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
4770
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
4771
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
4772
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #55 = G_INTRINSIC_TRUNC
4773
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #56 = G_INTRINSIC_ROUND
4774
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_LOAD
4775
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_SEXTLOAD
4776
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = G_ZEXTLOAD
4777
  { 60, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #60 = G_STORE
4778
  { 61, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #61 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
4779
  { 62, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMIC_CMPXCHG
4780
  { 63, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_XCHG
4781
  { 64, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_ADD
4782
  { 65, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_SUB
4783
  { 66, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_AND
4784
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_NAND
4785
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_OR
4786
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_XOR
4787
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_MAX
4788
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_MIN
4789
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_UMAX
4790
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_UMIN
4791
  { 74, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #74 = G_BRCOND
4792
  { 75, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #75 = G_BRINDIRECT
4793
  { 76, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #76 = G_INTRINSIC
4794
  { 77, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #77 = G_INTRINSIC_W_SIDE_EFFECTS
4795
  { 78, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #78 = G_ANYEXT
4796
  { 79, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #79 = G_TRUNC
4797
  { 80, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #80 = G_CONSTANT
4798
  { 81, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #81 = G_FCONSTANT
4799
  { 82, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #82 = G_VASTART
4800
  { 83, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #83 = G_VAARG
4801
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #84 = G_SEXT
4802
  { 85, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #85 = G_ZEXT
4803
  { 86, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_SHL
4804
  { 87, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #87 = G_LSHR
4805
  { 88, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #88 = G_ASHR
4806
  { 89, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #89 = G_ICMP
4807
  { 90, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_FCMP
4808
  { 91, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #91 = G_SELECT
4809
  { 92, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #92 = G_UADDO
4810
  { 93, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #93 = G_UADDE
4811
  { 94, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #94 = G_USUBO
4812
  { 95, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #95 = G_USUBE
4813
  { 96, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_SADDO
4814
  { 97, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #97 = G_SADDE
4815
  { 98, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #98 = G_SSUBO
4816
  { 99, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #99 = G_SSUBE
4817
  { 100,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #100 = G_UMULO
4818
  { 101,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #101 = G_SMULO
4819
  { 102,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_UMULH
4820
  { 103,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_SMULH
4821
  { 104,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FADD
4822
  { 105,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #105 = G_FSUB
4823
  { 106,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_FMUL
4824
  { 107,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FMA
4825
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FDIV
4826
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FREM
4827
  { 110,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FPOW
4828
  { 111,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #111 = G_FEXP
4829
  { 112,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #112 = G_FEXP2
4830
  { 113,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #113 = G_FLOG
4831
  { 114,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #114 = G_FLOG2
4832
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FNEG
4833
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #116 = G_FPEXT
4834
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #117 = G_FPTRUNC
4835
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #118 = G_FPTOSI
4836
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #119 = G_FPTOUI
4837
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #120 = G_SITOFP
4838
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_UITOFP
4839
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #122 = G_FABS
4840
  { 123,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #123 = G_GEP
4841
  { 124,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #124 = G_PTR_MASK
4842
  { 125,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #125 = G_BR
4843
  { 126,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #126 = G_INSERT_VECTOR_ELT
4844
  { 127,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #127 = G_EXTRACT_VECTOR_ELT
4845
  { 128,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #128 = G_SHUFFLE_VECTOR
4846
  { 129,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #129 = G_CTTZ
4847
  { 130,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #130 = G_CTTZ_ZERO_UNDEF
4848
  { 131,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #131 = G_CTLZ
4849
  { 132,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #132 = G_CTLZ_ZERO_UNDEF
4850
  { 133,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #133 = G_CTPOP
4851
  { 134,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #134 = G_BSWAP
4852
  { 135,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_ADDRSPACE_CAST
4853
  { 136,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #136 = G_BLOCK_ADDR
4854
  { 137,  2,  1,  8,  677,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #137 = ABS
4855
  { 138,  5,  1,  4,  691,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #138 = ADDSri
4856
  { 139,  5,  1,  4,  698,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #139 = ADDSrr
4857
  { 140,  6,  1,  4,  701,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #140 = ADDSrsi
4858
  { 141,  7,  1,  4,  706,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #141 = ADDSrsr
4859
  { 142,  4,  0,  0,  848,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo36, -1 ,nullptr },  // Inst #142 = ADJCALLSTACKDOWN
4860
  { 143,  4,  0,  0,  848,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo36, -1 ,nullptr },  // Inst #143 = ADJCALLSTACKUP
4861
  { 144,  6,  0,  0,  712,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #144 = ASRi
4862
  { 145,  6,  0,  0,  713,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #145 = ASRr
4863
  { 146,  1,  0,  4,  850,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #146 = B
4864
  { 147,  4,  0,  0,  857,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #147 = BCCZi64
4865
  { 148,  6,  0,  0,  857,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #148 = BCCi64
4866
  { 149,  1,  0,  8,  866,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo39, -1 ,nullptr },  // Inst #149 = BMOVPCB_CALL
4867
  { 150,  1,  0,  8,  866,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo42, -1 ,nullptr },  // Inst #150 = BMOVPCRX_CALL
4868
  { 151,  3,  0,  4,  858,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #151 = BR_JTadd
4869
  { 152,  3,  0,  4,  861,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #152 = BR_JTm_i12
4870
  { 153,  4,  0,  4,  861,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #153 = BR_JTm_rs
4871
  { 154,  2,  0,  4,  859,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #154 = BR_JTr
4872
  { 155,  1,  0,  8,  850,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo42, -1 ,nullptr },  // Inst #155 = BX_CALL
4873
  { 156,  5,  2,  0,  839,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #156 = CMP_SWAP_16
4874
  { 157,  5,  2,  0,  839,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #157 = CMP_SWAP_32
4875
  { 158,  5,  2,  0,  839,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #158 = CMP_SWAP_64
4876
  { 159,  5,  2,  0,  839,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #159 = CMP_SWAP_8
4877
  { 160,  3,  0,  0,  839,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #160 = CONSTPOOL_ENTRY
4878
  { 161,  4,  0,  0,  839,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, Operand