Coverage Report

Created: 2018-07-20 23:04

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenMCPseudoLowering.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Pseudo-instruction MC lowering Source Fragment                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
bool ARMAsmPrinter::
10
emitPseudoExpansionLowering(MCStreamer &OutStreamer,
11
786k
                            const MachineInstr *MI) {
12
786k
  switch (MI->getOpcode()) {
13
786k
    
default: return false764k
;
14
786k
    case ARM::B: {
15
220
      MCInst TmpInst;
16
220
      MCOperand MCOp;
17
220
      TmpInst.setOpcode(ARM::Bcc);
18
220
      // Operand: target
19
220
      lowerOperand(MI->getOperand(0), MCOp);
20
220
      TmpInst.addOperand(MCOp);
21
220
      // Operand: p
22
220
      TmpInst.addOperand(MCOperand::createImm(14));
23
220
      TmpInst.addOperand(MCOperand::createReg(0));
24
220
      EmitToStreamer(OutStreamer, TmpInst);
25
220
      break;
26
786k
    }
27
786k
    case ARM::LDMIA_RET: {
28
1.37k
      MCInst TmpInst;
29
1.37k
      MCOperand MCOp;
30
1.37k
      TmpInst.setOpcode(ARM::LDMIA_UPD);
31
1.37k
      // Operand: wb
32
1.37k
      lowerOperand(MI->getOperand(0), MCOp);
33
1.37k
      TmpInst.addOperand(MCOp);
34
1.37k
      // Operand: Rn
35
1.37k
      lowerOperand(MI->getOperand(1), MCOp);
36
1.37k
      TmpInst.addOperand(MCOp);
37
1.37k
      // Operand: p
38
1.37k
      lowerOperand(MI->getOperand(2), MCOp);
39
1.37k
      TmpInst.addOperand(MCOp);
40
1.37k
      lowerOperand(MI->getOperand(3), MCOp);
41
1.37k
      TmpInst.addOperand(MCOp);
42
1.37k
      // Operand: regs
43
1.37k
      lowerOperand(MI->getOperand(4), MCOp);
44
1.37k
      TmpInst.addOperand(MCOp);
45
1.37k
      // variable_ops
46
5.25k
      for (unsigned i = 5, e = MI->getNumOperands(); i != e; 
++i3.87k
)
47
3.87k
        if (lowerOperand(MI->getOperand(i), MCOp))
48
2.58k
          TmpInst.addOperand(MCOp);
49
1.37k
      EmitToStreamer(OutStreamer, TmpInst);
50
1.37k
      break;
51
786k
    }
52
786k
    case ARM::MLAv5: {
53
26
      MCInst TmpInst;
54
26
      MCOperand MCOp;
55
26
      TmpInst.setOpcode(ARM::MLA);
56
26
      // Operand: Rd
57
26
      lowerOperand(MI->getOperand(0), MCOp);
58
26
      TmpInst.addOperand(MCOp);
59
26
      // Operand: Rn
60
26
      lowerOperand(MI->getOperand(1), MCOp);
61
26
      TmpInst.addOperand(MCOp);
62
26
      // Operand: Rm
63
26
      lowerOperand(MI->getOperand(2), MCOp);
64
26
      TmpInst.addOperand(MCOp);
65
26
      // Operand: Ra
66
26
      lowerOperand(MI->getOperand(3), MCOp);
67
26
      TmpInst.addOperand(MCOp);
68
26
      // Operand: p
69
26
      lowerOperand(MI->getOperand(4), MCOp);
70
26
      TmpInst.addOperand(MCOp);
71
26
      lowerOperand(MI->getOperand(5), MCOp);
72
26
      TmpInst.addOperand(MCOp);
73
26
      // Operand: s
74
26
      lowerOperand(MI->getOperand(6), MCOp);
75
26
      TmpInst.addOperand(MCOp);
76
26
      EmitToStreamer(OutStreamer, TmpInst);
77
26
      break;
78
786k
    }
79
786k
    case ARM::MOVPCRX: {
80
0
      MCInst TmpInst;
81
0
      MCOperand MCOp;
82
0
      TmpInst.setOpcode(ARM::MOVr);
83
0
      // Operand: Rd
84
0
      TmpInst.addOperand(MCOperand::createReg(ARM::PC));
85
0
      // Operand: Rm
86
0
      lowerOperand(MI->getOperand(0), MCOp);
87
0
      TmpInst.addOperand(MCOp);
88
0
      // Operand: p
89
0
      TmpInst.addOperand(MCOperand::createImm(14));
90
0
      TmpInst.addOperand(MCOperand::createReg(0));
91
0
      // Operand: s
92
0
      TmpInst.addOperand(MCOperand::createReg(0));
93
0
      EmitToStreamer(OutStreamer, TmpInst);
94
0
      break;
95
786k
    }
96
786k
    case ARM::MULv5: {
97
51
      MCInst TmpInst;
98
51
      MCOperand MCOp;
99
51
      TmpInst.setOpcode(ARM::MUL);
100
51
      // Operand: Rd
101
51
      lowerOperand(MI->getOperand(0), MCOp);
102
51
      TmpInst.addOperand(MCOp);
103
51
      // Operand: Rn
104
51
      lowerOperand(MI->getOperand(1), MCOp);
105
51
      TmpInst.addOperand(MCOp);
106
51
      // Operand: Rm
107
51
      lowerOperand(MI->getOperand(2), MCOp);
108
51
      TmpInst.addOperand(MCOp);
109
51
      // Operand: p
110
51
      lowerOperand(MI->getOperand(3), MCOp);
111
51
      TmpInst.addOperand(MCOp);
112
51
      lowerOperand(MI->getOperand(4), MCOp);
113
51
      TmpInst.addOperand(MCOp);
114
51
      // Operand: s
115
51
      lowerOperand(MI->getOperand(5), MCOp);
116
51
      TmpInst.addOperand(MCOp);
117
51
      EmitToStreamer(OutStreamer, TmpInst);
118
51
      break;
119
786k
    }
120
786k
    case ARM::SMLALv5: {
121
9
      MCInst TmpInst;
122
9
      MCOperand MCOp;
123
9
      TmpInst.setOpcode(ARM::SMLAL);
124
9
      // Operand: RdLo
125
9
      lowerOperand(MI->getOperand(0), MCOp);
126
9
      TmpInst.addOperand(MCOp);
127
9
      // Operand: RdHi
128
9
      lowerOperand(MI->getOperand(1), MCOp);
129
9
      TmpInst.addOperand(MCOp);
130
9
      // Operand: Rn
131
9
      lowerOperand(MI->getOperand(2), MCOp);
132
9
      TmpInst.addOperand(MCOp);
133
9
      // Operand: Rm
134
9
      lowerOperand(MI->getOperand(3), MCOp);
135
9
      TmpInst.addOperand(MCOp);
136
9
      // Operand: RLo
137
9
      lowerOperand(MI->getOperand(4), MCOp);
138
9
      TmpInst.addOperand(MCOp);
139
9
      // Operand: RHi
140
9
      lowerOperand(MI->getOperand(5), MCOp);
141
9
      TmpInst.addOperand(MCOp);
142
9
      // Operand: p
143
9
      lowerOperand(MI->getOperand(6), MCOp);
144
9
      TmpInst.addOperand(MCOp);
145
9
      lowerOperand(MI->getOperand(7), MCOp);
146
9
      TmpInst.addOperand(MCOp);
147
9
      // Operand: s
148
9
      lowerOperand(MI->getOperand(8), MCOp);
149
9
      TmpInst.addOperand(MCOp);
150
9
      EmitToStreamer(OutStreamer, TmpInst);
151
9
      break;
152
786k
    }
153
786k
    case ARM::SMULLv5: {
154
30
      MCInst TmpInst;
155
30
      MCOperand MCOp;
156
30
      TmpInst.setOpcode(ARM::SMULL);
157
30
      // Operand: RdLo
158
30
      lowerOperand(MI->getOperand(0), MCOp);
159
30
      TmpInst.addOperand(MCOp);
160
30
      // Operand: RdHi
161
30
      lowerOperand(MI->getOperand(1), MCOp);
162
30
      TmpInst.addOperand(MCOp);
163
30
      // Operand: Rn
164
30
      lowerOperand(MI->getOperand(2), MCOp);
165
30
      TmpInst.addOperand(MCOp);
166
30
      // Operand: Rm
167
30
      lowerOperand(MI->getOperand(3), MCOp);
168
30
      TmpInst.addOperand(MCOp);
169
30
      // Operand: p
170
30
      lowerOperand(MI->getOperand(4), MCOp);
171
30
      TmpInst.addOperand(MCOp);
172
30
      lowerOperand(MI->getOperand(5), MCOp);
173
30
      TmpInst.addOperand(MCOp);
174
30
      // Operand: s
175
30
      lowerOperand(MI->getOperand(6), MCOp);
176
30
      TmpInst.addOperand(MCOp);
177
30
      EmitToStreamer(OutStreamer, TmpInst);
178
30
      break;
179
786k
    }
180
786k
    case ARM::TAILJMPd: {
181
188
      MCInst TmpInst;
182
188
      MCOperand MCOp;
183
188
      TmpInst.setOpcode(ARM::Bcc);
184
188
      // Operand: target
185
188
      lowerOperand(MI->getOperand(0), MCOp);
186
188
      TmpInst.addOperand(MCOp);
187
188
      // Operand: p
188
188
      TmpInst.addOperand(MCOperand::createImm(14));
189
188
      TmpInst.addOperand(MCOperand::createReg(0));
190
188
      EmitToStreamer(OutStreamer, TmpInst);
191
188
      break;
192
786k
    }
193
786k
    case ARM::TAILJMPr: {
194
6
      MCInst TmpInst;
195
6
      MCOperand MCOp;
196
6
      TmpInst.setOpcode(ARM::BX);
197
6
      // Operand: dst
198
6
      lowerOperand(MI->getOperand(0), MCOp);
199
6
      TmpInst.addOperand(MCOp);
200
6
      EmitToStreamer(OutStreamer, TmpInst);
201
6
      break;
202
786k
    }
203
786k
    case ARM::TAILJMPr4: {
204
3
      MCInst TmpInst;
205
3
      MCOperand MCOp;
206
3
      TmpInst.setOpcode(ARM::MOVr);
207
3
      // Operand: Rd
208
3
      TmpInst.addOperand(MCOperand::createReg(ARM::PC));
209
3
      // Operand: Rm
210
3
      lowerOperand(MI->getOperand(0), MCOp);
211
3
      TmpInst.addOperand(MCOp);
212
3
      // Operand: p
213
3
      TmpInst.addOperand(MCOperand::createImm(14));
214
3
      TmpInst.addOperand(MCOperand::createReg(0));
215
3
      // Operand: s
216
3
      TmpInst.addOperand(MCOperand::createReg(0));
217
3
      EmitToStreamer(OutStreamer, TmpInst);
218
3
      break;
219
786k
    }
220
786k
    case ARM::UMLALv5: {
221
12
      MCInst TmpInst;
222
12
      MCOperand MCOp;
223
12
      TmpInst.setOpcode(ARM::UMLAL);
224
12
      // Operand: RdLo
225
12
      lowerOperand(MI->getOperand(0), MCOp);
226
12
      TmpInst.addOperand(MCOp);
227
12
      // Operand: RdHi
228
12
      lowerOperand(MI->getOperand(1), MCOp);
229
12
      TmpInst.addOperand(MCOp);
230
12
      // Operand: Rn
231
12
      lowerOperand(MI->getOperand(2), MCOp);
232
12
      TmpInst.addOperand(MCOp);
233
12
      // Operand: Rm
234
12
      lowerOperand(MI->getOperand(3), MCOp);
235
12
      TmpInst.addOperand(MCOp);
236
12
      // Operand: RLo
237
12
      lowerOperand(MI->getOperand(4), MCOp);
238
12
      TmpInst.addOperand(MCOp);
239
12
      // Operand: RHi
240
12
      lowerOperand(MI->getOperand(5), MCOp);
241
12
      TmpInst.addOperand(MCOp);
242
12
      // Operand: p
243
12
      lowerOperand(MI->getOperand(6), MCOp);
244
12
      TmpInst.addOperand(MCOp);
245
12
      lowerOperand(MI->getOperand(7), MCOp);
246
12
      TmpInst.addOperand(MCOp);
247
12
      // Operand: s
248
12
      lowerOperand(MI->getOperand(8), MCOp);
249
12
      TmpInst.addOperand(MCOp);
250
12
      EmitToStreamer(OutStreamer, TmpInst);
251
12
      break;
252
786k
    }
253
786k
    case ARM::UMULLv5: {
254
22
      MCInst TmpInst;
255
22
      MCOperand MCOp;
256
22
      TmpInst.setOpcode(ARM::UMULL);
257
22
      // Operand: RdLo
258
22
      lowerOperand(MI->getOperand(0), MCOp);
259
22
      TmpInst.addOperand(MCOp);
260
22
      // Operand: RdHi
261
22
      lowerOperand(MI->getOperand(1), MCOp);
262
22
      TmpInst.addOperand(MCOp);
263
22
      // Operand: Rn
264
22
      lowerOperand(MI->getOperand(2), MCOp);
265
22
      TmpInst.addOperand(MCOp);
266
22
      // Operand: Rm
267
22
      lowerOperand(MI->getOperand(3), MCOp);
268
22
      TmpInst.addOperand(MCOp);
269
22
      // Operand: p
270
22
      lowerOperand(MI->getOperand(4), MCOp);
271
22
      TmpInst.addOperand(MCOp);
272
22
      lowerOperand(MI->getOperand(5), MCOp);
273
22
      TmpInst.addOperand(MCOp);
274
22
      // Operand: s
275
22
      lowerOperand(MI->getOperand(6), MCOp);
276
22
      TmpInst.addOperand(MCOp);
277
22
      EmitToStreamer(OutStreamer, TmpInst);
278
22
      break;
279
786k
    }
280
786k
    case ARM::VMOVD0: {
281
2
      MCInst TmpInst;
282
2
      MCOperand MCOp;
283
2
      TmpInst.setOpcode(ARM::VMOVv2i32);
284
2
      // Operand: Vd
285
2
      lowerOperand(MI->getOperand(0), MCOp);
286
2
      TmpInst.addOperand(MCOp);
287
2
      // Operand: SIMM
288
2
      TmpInst.addOperand(MCOperand::createImm(0));
289
2
      // Operand: p
290
2
      TmpInst.addOperand(MCOperand::createImm(14));
291
2
      TmpInst.addOperand(MCOperand::createReg(0));
292
2
      EmitToStreamer(OutStreamer, TmpInst);
293
2
      break;
294
786k
    }
295
786k
    case ARM::VMOVQ0: {
296
2
      MCInst TmpInst;
297
2
      MCOperand MCOp;
298
2
      TmpInst.setOpcode(ARM::VMOVv4i32);
299
2
      // Operand: Vd
300
2
      lowerOperand(MI->getOperand(0), MCOp);
301
2
      TmpInst.addOperand(MCOp);
302
2
      // Operand: SIMM
303
2
      TmpInst.addOperand(MCOperand::createImm(0));
304
2
      // Operand: p
305
2
      TmpInst.addOperand(MCOperand::createImm(14));
306
2
      TmpInst.addOperand(MCOperand::createReg(0));
307
2
      EmitToStreamer(OutStreamer, TmpInst);
308
2
      break;
309
786k
    }
310
786k
    case ARM::t2LDMIA_RET: {
311
213
      MCInst TmpInst;
312
213
      MCOperand MCOp;
313
213
      TmpInst.setOpcode(ARM::t2LDMIA_UPD);
314
213
      // Operand: wb
315
213
      lowerOperand(MI->getOperand(0), MCOp);
316
213
      TmpInst.addOperand(MCOp);
317
213
      // Operand: Rn
318
213
      lowerOperand(MI->getOperand(1), MCOp);
319
213
      TmpInst.addOperand(MCOp);
320
213
      // Operand: p
321
213
      lowerOperand(MI->getOperand(2), MCOp);
322
213
      TmpInst.addOperand(MCOp);
323
213
      lowerOperand(MI->getOperand(3), MCOp);
324
213
      TmpInst.addOperand(MCOp);
325
213
      // Operand: regs
326
213
      lowerOperand(MI->getOperand(4), MCOp);
327
213
      TmpInst.addOperand(MCOp);
328
213
      // variable_ops
329
1.55k
      for (unsigned i = 5, e = MI->getNumOperands(); i != e; 
++i1.34k
)
330
1.34k
        if (lowerOperand(MI->getOperand(i), MCOp))
331
1.08k
          TmpInst.addOperand(MCOp);
332
213
      EmitToStreamer(OutStreamer, TmpInst);
333
213
      break;
334
786k
    }
335
786k
    case ARM::tBRIND: {
336
20
      MCInst TmpInst;
337
20
      MCOperand MCOp;
338
20
      TmpInst.setOpcode(ARM::tMOVr);
339
20
      // Operand: Rd
340
20
      TmpInst.addOperand(MCOperand::createReg(ARM::PC));
341
20
      // Operand: Rm
342
20
      lowerOperand(MI->getOperand(0), MCOp);
343
20
      TmpInst.addOperand(MCOp);
344
20
      // Operand: p
345
20
      lowerOperand(MI->getOperand(1), MCOp);
346
20
      TmpInst.addOperand(MCOp);
347
20
      lowerOperand(MI->getOperand(2), MCOp);
348
20
      TmpInst.addOperand(MCOp);
349
20
      EmitToStreamer(OutStreamer, TmpInst);
350
20
      break;
351
786k
    }
352
786k
    case ARM::tBX_RET: {
353
7.44k
      MCInst TmpInst;
354
7.44k
      MCOperand MCOp;
355
7.44k
      TmpInst.setOpcode(ARM::tBX);
356
7.44k
      // Operand: Rm
357
7.44k
      TmpInst.addOperand(MCOperand::createReg(ARM::LR));
358
7.44k
      // Operand: p
359
7.44k
      lowerOperand(MI->getOperand(0), MCOp);
360
7.44k
      TmpInst.addOperand(MCOp);
361
7.44k
      lowerOperand(MI->getOperand(1), MCOp);
362
7.44k
      TmpInst.addOperand(MCOp);
363
7.44k
      EmitToStreamer(OutStreamer, TmpInst);
364
7.44k
      break;
365
786k
    }
366
786k
    case ARM::tBX_RET_vararg: {
367
0
      MCInst TmpInst;
368
0
      MCOperand MCOp;
369
0
      TmpInst.setOpcode(ARM::tBX);
370
0
      // Operand: Rm
371
0
      lowerOperand(MI->getOperand(0), MCOp);
372
0
      TmpInst.addOperand(MCOp);
373
0
      // Operand: p
374
0
      lowerOperand(MI->getOperand(1), MCOp);
375
0
      TmpInst.addOperand(MCOp);
376
0
      lowerOperand(MI->getOperand(2), MCOp);
377
0
      TmpInst.addOperand(MCOp);
378
0
      EmitToStreamer(OutStreamer, TmpInst);
379
0
      break;
380
786k
    }
381
786k
    case ARM::tBfar: {
382
0
      MCInst TmpInst;
383
0
      MCOperand MCOp;
384
0
      TmpInst.setOpcode(ARM::tBL);
385
0
      // Operand: p
386
0
      lowerOperand(MI->getOperand(1), MCOp);
387
0
      TmpInst.addOperand(MCOp);
388
0
      lowerOperand(MI->getOperand(2), MCOp);
389
0
      TmpInst.addOperand(MCOp);
390
0
      // Operand: func
391
0
      lowerOperand(MI->getOperand(0), MCOp);
392
0
      TmpInst.addOperand(MCOp);
393
0
      EmitToStreamer(OutStreamer, TmpInst);
394
0
      break;
395
786k
    }
396
786k
    case ARM::tLDMIA_UPD: {
397
43
      MCInst TmpInst;
398
43
      MCOperand MCOp;
399
43
      TmpInst.setOpcode(ARM::tLDMIA);
400
43
      // Operand: Rn
401
43
      lowerOperand(MI->getOperand(1), MCOp);
402
43
      TmpInst.addOperand(MCOp);
403
43
      // Operand: p
404
43
      lowerOperand(MI->getOperand(2), MCOp);
405
43
      TmpInst.addOperand(MCOp);
406
43
      lowerOperand(MI->getOperand(3), MCOp);
407
43
      TmpInst.addOperand(MCOp);
408
43
      // Operand: regs
409
43
      lowerOperand(MI->getOperand(4), MCOp);
410
43
      TmpInst.addOperand(MCOp);
411
43
      // variable_ops
412
129
      for (unsigned i = 5, e = MI->getNumOperands(); i != e; 
++i86
)
413
86
        if (lowerOperand(MI->getOperand(i), MCOp))
414
86
          TmpInst.addOperand(MCOp);
415
43
      EmitToStreamer(OutStreamer, TmpInst);
416
43
      break;
417
786k
    }
418
786k
    case ARM::tPOP_RET: {
419
9.57k
      MCInst TmpInst;
420
9.57k
      MCOperand MCOp;
421
9.57k
      TmpInst.setOpcode(ARM::tPOP);
422
9.57k
      // Operand: p
423
9.57k
      lowerOperand(MI->getOperand(0), MCOp);
424
9.57k
      TmpInst.addOperand(MCOp);
425
9.57k
      lowerOperand(MI->getOperand(1), MCOp);
426
9.57k
      TmpInst.addOperand(MCOp);
427
9.57k
      // Operand: regs
428
9.57k
      lowerOperand(MI->getOperand(2), MCOp);
429
9.57k
      TmpInst.addOperand(MCOp);
430
9.57k
      // variable_ops
431
48.1k
      for (unsigned i = 3, e = MI->getNumOperands(); i != e; 
++i38.5k
)
432
38.5k
        if (lowerOperand(MI->getOperand(i), MCOp))
433
28.9k
          TmpInst.addOperand(MCOp);
434
9.57k
      EmitToStreamer(OutStreamer, TmpInst);
435
9.57k
      break;
436
786k
    }
437
786k
    case ARM::tTAILJMPd: {
438
2.27k
      MCInst TmpInst;
439
2.27k
      MCOperand MCOp;
440
2.27k
      TmpInst.setOpcode(ARM::t2B);
441
2.27k
      // Operand: target
442
2.27k
      lowerOperand(MI->getOperand(0), MCOp);
443
2.27k
      TmpInst.addOperand(MCOp);
444
2.27k
      // Operand: p
445
2.27k
      lowerOperand(MI->getOperand(1), MCOp);
446
2.27k
      TmpInst.addOperand(MCOp);
447
2.27k
      lowerOperand(MI->getOperand(2), MCOp);
448
2.27k
      TmpInst.addOperand(MCOp);
449
2.27k
      EmitToStreamer(OutStreamer, TmpInst);
450
2.27k
      break;
451
786k
    }
452
786k
    case ARM::tTAILJMPdND: {
453
289
      MCInst TmpInst;
454
289
      MCOperand MCOp;
455
289
      TmpInst.setOpcode(ARM::tB);
456
289
      // Operand: target
457
289
      lowerOperand(MI->getOperand(0), MCOp);
458
289
      TmpInst.addOperand(MCOp);
459
289
      // Operand: p
460
289
      lowerOperand(MI->getOperand(1), MCOp);
461
289
      TmpInst.addOperand(MCOp);
462
289
      lowerOperand(MI->getOperand(2), MCOp);
463
289
      TmpInst.addOperand(MCOp);
464
289
      EmitToStreamer(OutStreamer, TmpInst);
465
289
      break;
466
786k
    }
467
786k
    case ARM::tTAILJMPr: {
468
104
      MCInst TmpInst;
469
104
      MCOperand MCOp;
470
104
      TmpInst.setOpcode(ARM::tBX);
471
104
      // Operand: Rm
472
104
      lowerOperand(MI->getOperand(0), MCOp);
473
104
      TmpInst.addOperand(MCOp);
474
104
      // Operand: p
475
104
      TmpInst.addOperand(MCOperand::createImm(14));
476
104
      TmpInst.addOperand(MCOperand::createReg(0));
477
104
      EmitToStreamer(OutStreamer, TmpInst);
478
104
      break;
479
21.9k
    }
480
21.9k
  }
481
21.9k
  return true;
482
21.9k
}
483