Coverage Report

Created: 2018-12-14 11:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenRegisterBank.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Register Bank Source Fragments                                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGBANK_DECLARATIONS
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#undef GET_REGBANK_DECLARATIONS
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namespace llvm {
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namespace ARM {
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enum {
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  FPRRegBankID,
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  GPRRegBankID,
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  NumRegisterBanks,
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};
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} // end namespace ARM
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} // end namespace llvm
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#endif // GET_REGBANK_DECLARATIONS
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#ifdef GET_TARGET_REGBANK_CLASS
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#undef GET_TARGET_REGBANK_CLASS
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private:
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  static RegisterBank *RegBanks[];
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protected:
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  ARMGenRegisterBankInfo();
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#endif // GET_TARGET_REGBANK_CLASS
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#ifdef GET_TARGET_REGBANK_IMPL
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#undef GET_TARGET_REGBANK_IMPL
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namespace llvm {
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namespace ARM {
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const uint32_t FPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (ARM::HPRRegClassID - 0)) |
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    (1u << (ARM::SPRRegClassID - 0)) |
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    (1u << (ARM::SPR_8RegClassID - 0)) |
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    (1u << (ARM::DPRRegClassID - 0)) |
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    (1u << (ARM::DPR_VFP2RegClassID - 0)) |
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    (1u << (ARM::DPR_8RegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (ARM::QPRRegClassID - 32)) |
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    (1u << (ARM::QPR_VFP2RegClassID - 32)) |
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    (1u << (ARM::QPR_8RegClassID - 32)) |
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    0,
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    // 64-95
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    0,
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    // 96-127
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    0,
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};
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const uint32_t GPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (ARM::GPRRegClassID - 0)) |
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    (1u << (ARM::GPRnopcRegClassID - 0)) |
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    (1u << (ARM::rGPRRegClassID - 0)) |
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    (1u << (ARM::tGPRRegClassID - 0)) |
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    (1u << (ARM::tGPR_and_tcGPRRegClassID - 0)) |
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    (1u << (ARM::hGPR_and_rGPRRegClassID - 0)) |
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    (1u << (ARM::hGPR_and_tcGPRRegClassID - 0)) |
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    (1u << (ARM::tcGPRRegClassID - 0)) |
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    (1u << (ARM::GPRnopc_and_hGPRRegClassID - 0)) |
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    (1u << (ARM::GPRspRegClassID - 0)) |
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    (1u << (ARM::tGPRwithpcRegClassID - 0)) |
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    (1u << (ARM::hGPR_and_tGPRwithpcRegClassID - 0)) |
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    (1u << (ARM::hGPRRegClassID - 0)) |
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    (1u << (ARM::GPRwithAPSRRegClassID - 0)) |
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    0,
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    // 32-63
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    0,
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    // 64-95
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    0,
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    // 96-127
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    0,
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};
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RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 103);
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RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 103);
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} // end namespace ARM
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RegisterBank *ARMGenRegisterBankInfo::RegBanks[] = {
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    &ARM::FPRRegBank,
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    &ARM::GPRRegBank,
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};
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ARMGenRegisterBankInfo::ARMGenRegisterBankInfo()
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6.86k
    : RegisterBankInfo(RegBanks, ARM::NumRegisterBanks) {
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6.86k
  // Assert that RegBank indices match their ID's
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#ifndef NDEBUG
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  unsigned Index = 0;
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  for (const auto &RB : RegBanks)
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    assert(Index++ == RB->getID() && "Index != ID");
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#endif // NDEBUG
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}
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} // end namespace llvm
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#endif // GET_TARGET_REGBANK_IMPL