Coverage Report

Created: 2018-12-14 11:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenRegisterInfo.inc
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass ARMMCRegisterClasses[];
17
18
namespace ARM {
19
enum {
20
  NoRegister,
21
  APSR = 1,
22
  APSR_NZCV = 2,
23
  CPSR = 3,
24
  FPEXC = 4,
25
  FPINST = 5,
26
  FPSCR = 6,
27
  FPSCR_NZCV = 7,
28
  FPSID = 8,
29
  ITSTATE = 9,
30
  LR = 10,
31
  PC = 11,
32
  SP = 12,
33
  SPSR = 13,
34
  D0 = 14,
35
  D1 = 15,
36
  D2 = 16,
37
  D3 = 17,
38
  D4 = 18,
39
  D5 = 19,
40
  D6 = 20,
41
  D7 = 21,
42
  D8 = 22,
43
  D9 = 23,
44
  D10 = 24,
45
  D11 = 25,
46
  D12 = 26,
47
  D13 = 27,
48
  D14 = 28,
49
  D15 = 29,
50
  D16 = 30,
51
  D17 = 31,
52
  D18 = 32,
53
  D19 = 33,
54
  D20 = 34,
55
  D21 = 35,
56
  D22 = 36,
57
  D23 = 37,
58
  D24 = 38,
59
  D25 = 39,
60
  D26 = 40,
61
  D27 = 41,
62
  D28 = 42,
63
  D29 = 43,
64
  D30 = 44,
65
  D31 = 45,
66
  FPINST2 = 46,
67
  MVFR0 = 47,
68
  MVFR1 = 48,
69
  MVFR2 = 49,
70
  Q0 = 50,
71
  Q1 = 51,
72
  Q2 = 52,
73
  Q3 = 53,
74
  Q4 = 54,
75
  Q5 = 55,
76
  Q6 = 56,
77
  Q7 = 57,
78
  Q8 = 58,
79
  Q9 = 59,
80
  Q10 = 60,
81
  Q11 = 61,
82
  Q12 = 62,
83
  Q13 = 63,
84
  Q14 = 64,
85
  Q15 = 65,
86
  R0 = 66,
87
  R1 = 67,
88
  R2 = 68,
89
  R3 = 69,
90
  R4 = 70,
91
  R5 = 71,
92
  R6 = 72,
93
  R7 = 73,
94
  R8 = 74,
95
  R9 = 75,
96
  R10 = 76,
97
  R11 = 77,
98
  R12 = 78,
99
  S0 = 79,
100
  S1 = 80,
101
  S2 = 81,
102
  S3 = 82,
103
  S4 = 83,
104
  S5 = 84,
105
  S6 = 85,
106
  S7 = 86,
107
  S8 = 87,
108
  S9 = 88,
109
  S10 = 89,
110
  S11 = 90,
111
  S12 = 91,
112
  S13 = 92,
113
  S14 = 93,
114
  S15 = 94,
115
  S16 = 95,
116
  S17 = 96,
117
  S18 = 97,
118
  S19 = 98,
119
  S20 = 99,
120
  S21 = 100,
121
  S22 = 101,
122
  S23 = 102,
123
  S24 = 103,
124
  S25 = 104,
125
  S26 = 105,
126
  S27 = 106,
127
  S28 = 107,
128
  S29 = 108,
129
  S30 = 109,
130
  S31 = 110,
131
  D0_D2 = 111,
132
  D1_D3 = 112,
133
  D2_D4 = 113,
134
  D3_D5 = 114,
135
  D4_D6 = 115,
136
  D5_D7 = 116,
137
  D6_D8 = 117,
138
  D7_D9 = 118,
139
  D8_D10 = 119,
140
  D9_D11 = 120,
141
  D10_D12 = 121,
142
  D11_D13 = 122,
143
  D12_D14 = 123,
144
  D13_D15 = 124,
145
  D14_D16 = 125,
146
  D15_D17 = 126,
147
  D16_D18 = 127,
148
  D17_D19 = 128,
149
  D18_D20 = 129,
150
  D19_D21 = 130,
151
  D20_D22 = 131,
152
  D21_D23 = 132,
153
  D22_D24 = 133,
154
  D23_D25 = 134,
155
  D24_D26 = 135,
156
  D25_D27 = 136,
157
  D26_D28 = 137,
158
  D27_D29 = 138,
159
  D28_D30 = 139,
160
  D29_D31 = 140,
161
  Q0_Q1 = 141,
162
  Q1_Q2 = 142,
163
  Q2_Q3 = 143,
164
  Q3_Q4 = 144,
165
  Q4_Q5 = 145,
166
  Q5_Q6 = 146,
167
  Q6_Q7 = 147,
168
  Q7_Q8 = 148,
169
  Q8_Q9 = 149,
170
  Q9_Q10 = 150,
171
  Q10_Q11 = 151,
172
  Q11_Q12 = 152,
173
  Q12_Q13 = 153,
174
  Q13_Q14 = 154,
175
  Q14_Q15 = 155,
176
  Q0_Q1_Q2_Q3 = 156,
177
  Q1_Q2_Q3_Q4 = 157,
178
  Q2_Q3_Q4_Q5 = 158,
179
  Q3_Q4_Q5_Q6 = 159,
180
  Q4_Q5_Q6_Q7 = 160,
181
  Q5_Q6_Q7_Q8 = 161,
182
  Q6_Q7_Q8_Q9 = 162,
183
  Q7_Q8_Q9_Q10 = 163,
184
  Q8_Q9_Q10_Q11 = 164,
185
  Q9_Q10_Q11_Q12 = 165,
186
  Q10_Q11_Q12_Q13 = 166,
187
  Q11_Q12_Q13_Q14 = 167,
188
  Q12_Q13_Q14_Q15 = 168,
189
  R12_SP = 169,
190
  R0_R1 = 170,
191
  R2_R3 = 171,
192
  R4_R5 = 172,
193
  R6_R7 = 173,
194
  R8_R9 = 174,
195
  R10_R11 = 175,
196
  D0_D1_D2 = 176,
197
  D1_D2_D3 = 177,
198
  D2_D3_D4 = 178,
199
  D3_D4_D5 = 179,
200
  D4_D5_D6 = 180,
201
  D5_D6_D7 = 181,
202
  D6_D7_D8 = 182,
203
  D7_D8_D9 = 183,
204
  D8_D9_D10 = 184,
205
  D9_D10_D11 = 185,
206
  D10_D11_D12 = 186,
207
  D11_D12_D13 = 187,
208
  D12_D13_D14 = 188,
209
  D13_D14_D15 = 189,
210
  D14_D15_D16 = 190,
211
  D15_D16_D17 = 191,
212
  D16_D17_D18 = 192,
213
  D17_D18_D19 = 193,
214
  D18_D19_D20 = 194,
215
  D19_D20_D21 = 195,
216
  D20_D21_D22 = 196,
217
  D21_D22_D23 = 197,
218
  D22_D23_D24 = 198,
219
  D23_D24_D25 = 199,
220
  D24_D25_D26 = 200,
221
  D25_D26_D27 = 201,
222
  D26_D27_D28 = 202,
223
  D27_D28_D29 = 203,
224
  D28_D29_D30 = 204,
225
  D29_D30_D31 = 205,
226
  D0_D2_D4 = 206,
227
  D1_D3_D5 = 207,
228
  D2_D4_D6 = 208,
229
  D3_D5_D7 = 209,
230
  D4_D6_D8 = 210,
231
  D5_D7_D9 = 211,
232
  D6_D8_D10 = 212,
233
  D7_D9_D11 = 213,
234
  D8_D10_D12 = 214,
235
  D9_D11_D13 = 215,
236
  D10_D12_D14 = 216,
237
  D11_D13_D15 = 217,
238
  D12_D14_D16 = 218,
239
  D13_D15_D17 = 219,
240
  D14_D16_D18 = 220,
241
  D15_D17_D19 = 221,
242
  D16_D18_D20 = 222,
243
  D17_D19_D21 = 223,
244
  D18_D20_D22 = 224,
245
  D19_D21_D23 = 225,
246
  D20_D22_D24 = 226,
247
  D21_D23_D25 = 227,
248
  D22_D24_D26 = 228,
249
  D23_D25_D27 = 229,
250
  D24_D26_D28 = 230,
251
  D25_D27_D29 = 231,
252
  D26_D28_D30 = 232,
253
  D27_D29_D31 = 233,
254
  D0_D2_D4_D6 = 234,
255
  D1_D3_D5_D7 = 235,
256
  D2_D4_D6_D8 = 236,
257
  D3_D5_D7_D9 = 237,
258
  D4_D6_D8_D10 = 238,
259
  D5_D7_D9_D11 = 239,
260
  D6_D8_D10_D12 = 240,
261
  D7_D9_D11_D13 = 241,
262
  D8_D10_D12_D14 = 242,
263
  D9_D11_D13_D15 = 243,
264
  D10_D12_D14_D16 = 244,
265
  D11_D13_D15_D17 = 245,
266
  D12_D14_D16_D18 = 246,
267
  D13_D15_D17_D19 = 247,
268
  D14_D16_D18_D20 = 248,
269
  D15_D17_D19_D21 = 249,
270
  D16_D18_D20_D22 = 250,
271
  D17_D19_D21_D23 = 251,
272
  D18_D20_D22_D24 = 252,
273
  D19_D21_D23_D25 = 253,
274
  D20_D22_D24_D26 = 254,
275
  D21_D23_D25_D27 = 255,
276
  D22_D24_D26_D28 = 256,
277
  D23_D25_D27_D29 = 257,
278
  D24_D26_D28_D30 = 258,
279
  D25_D27_D29_D31 = 259,
280
  D1_D2 = 260,
281
  D3_D4 = 261,
282
  D5_D6 = 262,
283
  D7_D8 = 263,
284
  D9_D10 = 264,
285
  D11_D12 = 265,
286
  D13_D14 = 266,
287
  D15_D16 = 267,
288
  D17_D18 = 268,
289
  D19_D20 = 269,
290
  D21_D22 = 270,
291
  D23_D24 = 271,
292
  D25_D26 = 272,
293
  D27_D28 = 273,
294
  D29_D30 = 274,
295
  D1_D2_D3_D4 = 275,
296
  D3_D4_D5_D6 = 276,
297
  D5_D6_D7_D8 = 277,
298
  D7_D8_D9_D10 = 278,
299
  D9_D10_D11_D12 = 279,
300
  D11_D12_D13_D14 = 280,
301
  D13_D14_D15_D16 = 281,
302
  D15_D16_D17_D18 = 282,
303
  D17_D18_D19_D20 = 283,
304
  D19_D20_D21_D22 = 284,
305
  D21_D22_D23_D24 = 285,
306
  D23_D24_D25_D26 = 286,
307
  D25_D26_D27_D28 = 287,
308
  D27_D28_D29_D30 = 288,
309
  NUM_TARGET_REGS   // 289
310
};
311
} // end namespace ARM
312
313
// Register classes
314
315
namespace ARM {
316
enum {
317
  HPRRegClassID = 0,
318
  SPRRegClassID = 1,
319
  GPRRegClassID = 2,
320
  GPRwithAPSRRegClassID = 3,
321
  SPR_8RegClassID = 4,
322
  GPRnopcRegClassID = 5,
323
  rGPRRegClassID = 6,
324
  tGPRwithpcRegClassID = 7,
325
  hGPRRegClassID = 8,
326
  tGPRRegClassID = 9,
327
  GPRnopc_and_hGPRRegClassID = 10,
328
  hGPR_and_rGPRRegClassID = 11,
329
  tcGPRRegClassID = 12,
330
  tGPR_and_tcGPRRegClassID = 13,
331
  CCRRegClassID = 14,
332
  GPRspRegClassID = 15,
333
  hGPR_and_tGPRwithpcRegClassID = 16,
334
  hGPR_and_tcGPRRegClassID = 17,
335
  DPRRegClassID = 18,
336
  DPR_VFP2RegClassID = 19,
337
  DPR_8RegClassID = 20,
338
  GPRPairRegClassID = 21,
339
  GPRPair_with_gsub_1_in_rGPRRegClassID = 22,
340
  GPRPair_with_gsub_0_in_tGPRRegClassID = 23,
341
  GPRPair_with_gsub_0_in_hGPRRegClassID = 24,
342
  GPRPair_with_gsub_0_in_tcGPRRegClassID = 25,
343
  GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 26,
344
  GPRPair_with_gsub_1_in_tcGPRRegClassID = 27,
345
  GPRPair_with_gsub_1_in_GPRspRegClassID = 28,
346
  DPairSpcRegClassID = 29,
347
  DPairSpc_with_ssub_0RegClassID = 30,
348
  DPairSpc_with_ssub_4RegClassID = 31,
349
  DPairSpc_with_dsub_0_in_DPR_8RegClassID = 32,
350
  DPairSpc_with_dsub_2_in_DPR_8RegClassID = 33,
351
  DPairRegClassID = 34,
352
  DPair_with_ssub_0RegClassID = 35,
353
  QPRRegClassID = 36,
354
  DPair_with_ssub_2RegClassID = 37,
355
  DPair_with_dsub_0_in_DPR_8RegClassID = 38,
356
  QPR_VFP2RegClassID = 39,
357
  DPair_with_dsub_1_in_DPR_8RegClassID = 40,
358
  QPR_8RegClassID = 41,
359
  DTripleRegClassID = 42,
360
  DTripleSpcRegClassID = 43,
361
  DTripleSpc_with_ssub_0RegClassID = 44,
362
  DTriple_with_ssub_0RegClassID = 45,
363
  DTriple_with_qsub_0_in_QPRRegClassID = 46,
364
  DTriple_with_ssub_2RegClassID = 47,
365
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 48,
366
  DTripleSpc_with_ssub_4RegClassID = 49,
367
  DTriple_with_ssub_4RegClassID = 50,
368
  DTripleSpc_with_ssub_8RegClassID = 51,
369
  DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 52,
370
  DTriple_with_dsub_0_in_DPR_8RegClassID = 53,
371
  DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 54,
372
  DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 55,
373
  DTriple_with_dsub_1_in_DPR_8RegClassID = 56,
374
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 57,
375
  DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID = 58,
376
  DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 59,
377
  DTriple_with_dsub_2_in_DPR_8RegClassID = 60,
378
  DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 61,
379
  DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 62,
380
  DTriple_with_qsub_0_in_QPR_8RegClassID = 63,
381
  DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 64,
382
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 65,
383
  DQuadSpcRegClassID = 66,
384
  DQuadSpc_with_ssub_0RegClassID = 67,
385
  DQuadSpc_with_ssub_4RegClassID = 68,
386
  DQuadSpc_with_ssub_8RegClassID = 69,
387
  DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 70,
388
  DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 71,
389
  DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 72,
390
  DQuadRegClassID = 73,
391
  DQuad_with_ssub_0RegClassID = 74,
392
  DQuad_with_ssub_2RegClassID = 75,
393
  QQPRRegClassID = 76,
394
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 77,
395
  DQuad_with_ssub_4RegClassID = 78,
396
  DQuad_with_ssub_6RegClassID = 79,
397
  DQuad_with_dsub_0_in_DPR_8RegClassID = 80,
398
  DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 81,
399
  DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82,
400
  DQuad_with_dsub_1_in_DPR_8RegClassID = 83,
401
  DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 84,
402
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 85,
403
  DQuad_with_dsub_2_in_DPR_8RegClassID = 86,
404
  DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 87,
405
  DQuad_with_dsub_3_in_DPR_8RegClassID = 88,
406
  DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89,
407
  DQuad_with_qsub_0_in_QPR_8RegClassID = 90,
408
  DQuad_with_qsub_1_in_QPR_8RegClassID = 91,
409
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 92,
410
  DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 93,
411
  QQQQPRRegClassID = 94,
412
  QQQQPR_with_ssub_0RegClassID = 95,
413
  QQQQPR_with_ssub_4RegClassID = 96,
414
  QQQQPR_with_ssub_8RegClassID = 97,
415
  QQQQPR_with_ssub_12RegClassID = 98,
416
  QQQQPR_with_dsub_0_in_DPR_8RegClassID = 99,
417
  QQQQPR_with_dsub_2_in_DPR_8RegClassID = 100,
418
  QQQQPR_with_dsub_4_in_DPR_8RegClassID = 101,
419
  QQQQPR_with_dsub_6_in_DPR_8RegClassID = 102,
420
421
  };
422
} // end namespace ARM
423
424
425
// Subregister indices
426
427
namespace ARM {
428
enum {
429
  NoSubRegister,
430
  dsub_0, // 1
431
  dsub_1, // 2
432
  dsub_2, // 3
433
  dsub_3, // 4
434
  dsub_4, // 5
435
  dsub_5, // 6
436
  dsub_6, // 7
437
  dsub_7, // 8
438
  gsub_0, // 9
439
  gsub_1, // 10
440
  qqsub_0,  // 11
441
  qqsub_1,  // 12
442
  qsub_0, // 13
443
  qsub_1, // 14
444
  qsub_2, // 15
445
  qsub_3, // 16
446
  ssub_0, // 17
447
  ssub_1, // 18
448
  ssub_2, // 19
449
  ssub_3, // 20
450
  ssub_4, // 21
451
  ssub_5, // 22
452
  ssub_6, // 23
453
  ssub_7, // 24
454
  ssub_8, // 25
455
  ssub_9, // 26
456
  ssub_10,  // 27
457
  ssub_11,  // 28
458
  ssub_12,  // 29
459
  ssub_13,  // 30
460
  dsub_7_then_ssub_0, // 31
461
  dsub_7_then_ssub_1, // 32
462
  ssub_0_ssub_1_ssub_4_ssub_5,  // 33
463
  ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5,  // 34
464
  ssub_2_ssub_3_ssub_6_ssub_7,  // 35
465
  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7,  // 36
466
  ssub_2_ssub_3_ssub_4_ssub_5,  // 37
467
  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9,  // 38
468
  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,  // 39
469
  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40
470
  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7,  // 41
471
  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,  // 42
472
  ssub_4_ssub_5_ssub_8_ssub_9,  // 43
473
  ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,  // 44
474
  ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,  // 45
475
  ssub_6_ssub_7_dsub_5, // 46
476
  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47
477
  ssub_6_ssub_7_dsub_5_dsub_7,  // 48
478
  ssub_6_ssub_7_ssub_8_ssub_9,  // 49
479
  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50
480
  ssub_8_ssub_9_ssub_12_ssub_13,  // 51
481
  ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52
482
  dsub_5_dsub_7,  // 53
483
  dsub_5_ssub_12_ssub_13_dsub_7,  // 54
484
  dsub_5_ssub_12_ssub_13, // 55
485
  ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56
486
  NUM_TARGET_SUBREGS
487
};
488
} // end namespace ARM
489
490
} // end namespace llvm
491
492
#endif // GET_REGINFO_ENUM
493
494
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
495
|*                                                                            *|
496
|* MC Register Information                                                    *|
497
|*                                                                            *|
498
|* Automatically generated file, do not edit!                                 *|
499
|*                                                                            *|
500
\*===----------------------------------------------------------------------===*/
501
502
503
#ifdef GET_REGINFO_MC_DESC
504
#undef GET_REGINFO_MC_DESC
505
506
namespace llvm {
507
508
extern const MCPhysReg ARMRegDiffLists[] = {
509
  /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
510
  /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
511
  /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
512
  /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
513
  /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0,
514
  /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0,
515
  /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0,
516
  /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0,
517
  /* 91 */ 40, 1, 1, 1, 1, 1, 0,
518
  /* 98 */ 65196, 1, 1, 1, 1, 1, 0,
519
  /* 105 */ 40, 1, 1, 1, 1, 0,
520
  /* 111 */ 42, 1, 1, 1, 1, 0,
521
  /* 117 */ 42, 1, 1, 1, 0,
522
  /* 122 */ 64510, 1, 1, 1, 0,
523
  /* 127 */ 65015, 1, 1, 1, 0,
524
  /* 132 */ 65282, 1, 1, 1, 0,
525
  /* 137 */ 65348, 1, 1, 1, 0,
526
  /* 142 */ 13, 1, 1, 0,
527
  /* 146 */ 42, 1, 1, 0,
528
  /* 150 */ 65388, 1, 1, 0,
529
  /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0,
530
  /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0,
531
  /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0,
532
  /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0,
533
  /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0,
534
  /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0,
535
  /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0,
536
  /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0,
537
  /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0,
538
  /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0,
539
  /* 254 */ 65489, 133, 65416, 1, 1, 0,
540
  /* 260 */ 65490, 133, 65416, 1, 1, 0,
541
  /* 266 */ 65491, 133, 65416, 1, 1, 0,
542
  /* 272 */ 65492, 133, 65416, 1, 1, 0,
543
  /* 278 */ 65493, 133, 65416, 1, 1, 0,
544
  /* 284 */ 65494, 133, 65416, 1, 1, 0,
545
  /* 290 */ 65495, 133, 65416, 1, 1, 0,
546
  /* 296 */ 65496, 133, 65416, 1, 1, 0,
547
  /* 302 */ 65497, 133, 65416, 1, 1, 0,
548
  /* 308 */ 65498, 133, 65416, 1, 1, 0,
549
  /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0,
550
  /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0,
551
  /* 332 */ 65136, 1, 3, 1, 3, 1, 0,
552
  /* 339 */ 65326, 1, 3, 1, 0,
553
  /* 344 */ 13, 1, 0,
554
  /* 347 */ 14, 1, 0,
555
  /* 350 */ 65, 1, 0,
556
  /* 353 */ 65500, 65, 1, 65471, 66, 1, 0,
557
  /* 360 */ 65291, 66, 1, 65470, 67, 1, 0,
558
  /* 367 */ 65439, 65, 1, 65472, 67, 1, 0,
559
  /* 374 */ 65501, 67, 1, 65469, 68, 1, 0,
560
  /* 381 */ 65439, 66, 1, 65471, 68, 1, 0,
561
  /* 388 */ 65292, 68, 1, 65468, 69, 1, 0,
562
  /* 395 */ 65439, 67, 1, 65470, 69, 1, 0,
563
  /* 402 */ 65502, 69, 1, 65467, 70, 1, 0,
564
  /* 409 */ 65439, 68, 1, 65469, 70, 1, 0,
565
  /* 416 */ 65293, 70, 1, 65466, 71, 1, 0,
566
  /* 423 */ 65439, 69, 1, 65468, 71, 1, 0,
567
  /* 430 */ 65503, 71, 1, 65465, 72, 1, 0,
568
  /* 437 */ 65439, 70, 1, 65467, 72, 1, 0,
569
  /* 444 */ 65294, 72, 1, 65464, 73, 1, 0,
570
  /* 451 */ 65439, 71, 1, 65466, 73, 1, 0,
571
  /* 458 */ 65504, 73, 1, 65463, 74, 1, 0,
572
  /* 465 */ 65439, 72, 1, 65465, 74, 1, 0,
573
  /* 472 */ 65295, 74, 1, 65462, 75, 1, 0,
574
  /* 479 */ 65439, 73, 1, 65464, 75, 1, 0,
575
  /* 486 */ 65505, 75, 1, 65461, 76, 1, 0,
576
  /* 493 */ 65439, 74, 1, 65463, 76, 1, 0,
577
  /* 500 */ 65296, 76, 1, 65460, 77, 1, 0,
578
  /* 507 */ 65439, 75, 1, 65462, 77, 1, 0,
579
  /* 514 */ 65506, 77, 1, 65459, 78, 1, 0,
580
  /* 521 */ 65439, 76, 1, 65461, 78, 1, 0,
581
  /* 528 */ 65297, 78, 1, 65458, 79, 1, 0,
582
  /* 535 */ 65439, 77, 1, 65460, 79, 1, 0,
583
  /* 542 */ 65507, 79, 1, 65457, 80, 1, 0,
584
  /* 549 */ 65439, 78, 1, 65459, 80, 1, 0,
585
  /* 556 */ 65045, 1, 0,
586
  /* 559 */ 65260, 1, 0,
587
  /* 562 */ 65299, 1, 0,
588
  /* 565 */ 65300, 1, 0,
589
  /* 568 */ 65301, 1, 0,
590
  /* 571 */ 65302, 1, 0,
591
  /* 574 */ 65303, 1, 0,
592
  /* 577 */ 65304, 1, 0,
593
  /* 580 */ 65305, 1, 0,
594
  /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0,
595
  /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0,
596
  /* 600 */ 65488, 13, 121, 65416, 1, 0,
597
  /* 606 */ 65489, 13, 121, 65416, 1, 0,
598
  /* 612 */ 65490, 13, 121, 65416, 1, 0,
599
  /* 618 */ 65491, 13, 121, 65416, 1, 0,
600
  /* 624 */ 65492, 13, 121, 65416, 1, 0,
601
  /* 630 */ 65493, 13, 121, 65416, 1, 0,
602
  /* 636 */ 65494, 13, 121, 65416, 1, 0,
603
  /* 642 */ 65495, 13, 121, 65416, 1, 0,
604
  /* 648 */ 65496, 13, 121, 65416, 1, 0,
605
  /* 654 */ 65497, 13, 121, 65416, 1, 0,
606
  /* 660 */ 65498, 13, 121, 65416, 1, 0,
607
  /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0,
608
  /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0,
609
  /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0,
610
  /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0,
611
  /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0,
612
  /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0,
613
  /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0,
614
  /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0,
615
  /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0,
616
  /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0,
617
  /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0,
618
  /* 765 */ 65488, 133, 65416, 1, 0,
619
  /* 770 */ 65499, 134, 65416, 1, 0,
620
  /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0,
621
  /* 783 */ 65432, 1, 0,
622
  /* 786 */ 65433, 1, 0,
623
  /* 789 */ 65434, 1, 0,
624
  /* 792 */ 65435, 1, 0,
625
  /* 795 */ 65436, 1, 0,
626
  /* 798 */ 65437, 1, 0,
627
  /* 801 */ 65464, 1, 0,
628
  /* 804 */ 65508, 1, 0,
629
  /* 807 */ 65509, 1, 0,
630
  /* 810 */ 65510, 1, 0,
631
  /* 813 */ 65511, 1, 0,
632
  /* 816 */ 65512, 1, 0,
633
  /* 819 */ 65513, 1, 0,
634
  /* 822 */ 65514, 1, 0,
635
  /* 825 */ 65515, 1, 0,
636
  /* 828 */ 65520, 1, 0,
637
  /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0,
638
  /* 839 */ 65136, 1, 3, 1, 2, 0,
639
  /* 845 */ 65326, 1, 2, 0,
640
  /* 849 */ 65080, 1, 3, 1, 2, 2, 0,
641
  /* 856 */ 65136, 1, 2, 2, 0,
642
  /* 861 */ 65080, 1, 2, 2, 2, 0,
643
  /* 867 */ 65330, 2, 2, 2, 0,
644
  /* 872 */ 65080, 1, 3, 2, 2, 0,
645
  /* 878 */ 65358, 2, 2, 0,
646
  /* 882 */ 65080, 1, 3, 1, 3, 2, 0,
647
  /* 889 */ 65136, 1, 3, 2, 0,
648
  /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0,
649
  /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0,
650
  /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0,
651
  /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0,
652
  /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0,
653
  /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0,
654
  /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0,
655
  /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0,
656
  /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0,
657
  /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0,
658
  /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0,
659
  /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0,
660
  /* 1038 */ 65344, 2, 2, 93, 2, 0,
661
  /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0,
662
  /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0,
663
  /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0,
664
  /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0,
665
  /* 1080 */ 65439, 2, 0,
666
  /* 1083 */ 65453, 2, 0,
667
  /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0,
668
  /* 1094 */ 65136, 1, 3, 1, 3, 0,
669
  /* 1100 */ 65326, 1, 3, 0,
670
  /* 1104 */ 5, 0,
671
  /* 1106 */ 140, 65486, 13, 0,
672
  /* 1110 */ 14, 0,
673
  /* 1112 */ 126, 65501, 15, 0,
674
  /* 1116 */ 10, 66, 0,
675
  /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0,
676
  /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0,
677
  /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0,
678
  /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0,
679
  /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0,
680
  /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0,
681
  /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0,
682
  /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0,
683
  /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0,
684
  /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0,
685
  /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0,
686
  /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0,
687
  /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0,
688
  /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0,
689
  /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0,
690
  /* 1359 */ 91, 0,
691
  /* 1361 */ 98, 0,
692
  /* 1363 */ 99, 0,
693
  /* 1365 */ 100, 0,
694
  /* 1367 */ 101, 0,
695
  /* 1369 */ 102, 0,
696
  /* 1371 */ 103, 0,
697
  /* 1373 */ 104, 0,
698
  /* 1375 */ 65374, 1, 1, 20, 75, 135, 0,
699
  /* 1382 */ 65374, 1, 1, 21, 74, 136, 0,
700
  /* 1389 */ 65374, 1, 1, 22, 73, 137, 0,
701
  /* 1396 */ 65374, 1, 1, 23, 72, 138, 0,
702
  /* 1403 */ 65374, 1, 1, 24, 71, 139, 0,
703
  /* 1410 */ 65374, 1, 1, 25, 70, 140, 0,
704
  /* 1417 */ 65374, 1, 1, 26, 69, 141, 0,
705
  /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0,
706
  /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0,
707
  /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0,
708
  /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0,
709
  /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0,
710
  /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0,
711
  /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0,
712
  /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0,
713
  /* 1526 */ 157, 0,
714
  /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0,
715
  /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0,
716
  /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0,
717
  /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0,
718
  /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0,
719
  /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0,
720
  /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0,
721
  /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0,
722
  /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0,
723
  /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0,
724
  /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0,
725
  /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0,
726
  /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0,
727
  /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0,
728
  /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0,
729
  /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0,
730
  /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0,
731
  /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0,
732
  /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0,
733
  /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0,
734
  /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0,
735
  /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0,
736
  /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0,
737
  /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0,
738
  /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0,
739
  /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0,
740
  /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0,
741
  /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0,
742
  /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0,
743
  /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0,
744
  /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0,
745
  /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0,
746
  /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0,
747
  /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0,
748
  /* 2455 */ 65487, 13, 121, 65416, 0,
749
  /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0,
750
  /* 2468 */ 65466, 1, 65486, 133, 65416, 0,
751
  /* 2474 */ 65487, 133, 65416, 0,
752
  /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
753
  /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
754
  /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0,
755
  /* 2509 */ 65452, 1, 65500, 134, 65417, 0,
756
  /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0,
757
  /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0,
758
  /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0,
759
  /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0,
760
  /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0,
761
  /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0,
762
  /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0,
763
  /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0,
764
  /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0,
765
  /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0,
766
  /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0,
767
  /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0,
768
  /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0,
769
  /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0,
770
  /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0,
771
  /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0,
772
  /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0,
773
  /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0,
774
  /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0,
775
  /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0,
776
  /* 2832 */ 26, 65446, 92, 65445, 0,
777
  /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0,
778
  /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0,
779
  /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0,
780
  /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0,
781
  /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
782
  /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
783
  /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0,
784
  /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0,
785
  /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
786
  /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
787
  /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0,
788
  /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0,
789
  /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
790
  /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
791
  /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0,
792
  /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0,
793
  /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
794
  /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
795
  /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
796
  /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
797
  /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0,
798
  /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
799
  /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
800
  /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
801
  /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
802
  /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0,
803
  /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
804
  /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
805
  /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
806
  /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
807
  /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
808
  /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0,
809
  /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
810
  /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
811
  /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
812
  /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
813
  /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
814
  /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0,
815
  /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
816
  /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
817
  /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
818
  /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
819
  /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
820
  /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0,
821
  /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
822
  /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
823
  /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
824
  /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
825
  /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
826
  /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0,
827
  /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
828
  /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
829
  /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
830
  /* 3839 */ 65298, 80, 1, 65456, 0,
831
  /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
832
  /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
833
  /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0,
834
  /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
835
  /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
836
  /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0,
837
  /* 3948 */ 65439, 80, 1, 65457, 0,
838
  /* 3953 */ 28, 65457, 0,
839
  /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
840
  /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
841
  /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
842
  /* 4002 */ 26, 65458, 80, 65457, 0,
843
  /* 4007 */ 65439, 79, 1, 65458, 0,
844
  /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0,
845
  /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0,
846
  /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0,
847
  /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0,
848
  /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0,
849
  /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0,
850
  /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0,
851
  /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0,
852
  /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0,
853
  /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0,
854
  /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0,
855
  /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0,
856
  /* 4114 */ 65445, 65470, 0,
857
  /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0,
858
  /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0,
859
  /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0,
860
  /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0,
861
  /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0,
862
  /* 4182 */ 65534, 0,
863
  /* 4184 */ 65535, 0,
864
};
865
866
extern const LaneBitmask ARMLaneMaskLists[] = {
867
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
868
  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
869
  /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask::getAll(),
870
  /* 8 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
871
  /* 11 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
872
  /* 16 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask::getAll(),
873
  /* 20 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask::getAll(),
874
  /* 23 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
875
  /* 28 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
876
  /* 35 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
877
  /* 39 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
878
  /* 42 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
879
  /* 48 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
880
  /* 53 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
881
  /* 57 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask::getAll(),
882
  /* 66 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000300), LaneBitmask::getAll(),
883
  /* 74 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
884
  /* 81 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
885
  /* 87 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
886
  /* 92 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask::getAll(),
887
  /* 99 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
888
  /* 105 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
889
  /* 110 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
890
  /* 114 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask::getAll(),
891
  /* 123 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
892
  /* 131 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
893
  /* 138 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
894
  /* 144 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
895
  /* 149 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask(0x00010000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
896
  /* 166 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
897
  /* 181 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
898
  /* 194 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
899
  /* 205 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
900
};
901
902
extern const uint16_t ARMSubRegIdxLists[] = {
903
  /* 0 */ 1, 2, 0,
904
  /* 3 */ 1, 17, 18, 2, 0,
905
  /* 8 */ 1, 3, 0,
906
  /* 11 */ 1, 17, 18, 3, 0,
907
  /* 16 */ 9, 10, 0,
908
  /* 19 */ 17, 18, 0,
909
  /* 22 */ 1, 17, 18, 2, 19, 20, 0,
910
  /* 29 */ 1, 17, 18, 3, 21, 22, 0,
911
  /* 36 */ 1, 2, 3, 13, 33, 37, 0,
912
  /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0,
913
  /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0,
914
  /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0,
915
  /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0,
916
  /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0,
917
  /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
918
  /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
919
  /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0,
920
  /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0,
921
  /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0,
922
  /* 188 */ 1, 3, 5, 33, 43, 0,
923
  /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0,
924
  /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0,
925
  /* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0,
926
  /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0,
927
  /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0,
928
  /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0,
929
  /* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0,
930
  /* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0,
931
  /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
932
  /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
933
  /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
934
  /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
935
  /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
936
};
937
938
extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[] = {
939
  { 65535, 65535 },
940
  { 0, 64 },  // dsub_0
941
  { 64, 64 }, // dsub_1
942
  { 128, 64 },  // dsub_2
943
  { 192, 64 },  // dsub_3
944
  { 256, 64 },  // dsub_4
945
  { 320, 64 },  // dsub_5
946
  { 384, 64 },  // dsub_6
947
  { 448, 64 },  // dsub_7
948
  { 0, 32 },  // gsub_0
949
  { 32, 32 }, // gsub_1
950
  { 0, 256 }, // qqsub_0
951
  { 256, 256 }, // qqsub_1
952
  { 0, 128 }, // qsub_0
953
  { 128, 128 }, // qsub_1
954
  { 256, 128 }, // qsub_2
955
  { 384, 128 }, // qsub_3
956
  { 0, 32 },  // ssub_0
957
  { 32, 32 }, // ssub_1
958
  { 64, 32 }, // ssub_2
959
  { 96, 32 }, // ssub_3
960
  { 128, 32 },  // ssub_4
961
  { 160, 32 },  // ssub_5
962
  { 192, 32 },  // ssub_6
963
  { 224, 32 },  // ssub_7
964
  { 256, 32 },  // ssub_8
965
  { 288, 32 },  // ssub_9
966
  { 320, 32 },  // ssub_10
967
  { 352, 32 },  // ssub_11
968
  { 384, 32 },  // ssub_12
969
  { 416, 32 },  // ssub_13
970
  { 448, 32 },  // dsub_7_then_ssub_0
971
  { 480, 32 },  // dsub_7_then_ssub_1
972
  { 65535, 128 }, // ssub_0_ssub_1_ssub_4_ssub_5
973
  { 0, 192 }, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
974
  { 65535, 128 }, // ssub_2_ssub_3_ssub_6_ssub_7
975
  { 64, 192 },  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
976
  { 64, 128 },  // ssub_2_ssub_3_ssub_4_ssub_5
977
  { 65535, 192 }, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
978
  { 65535, 256 }, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
979
  { 65535, 192 }, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
980
  { 65535, 256 }, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
981
  { 64, 256 },  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
982
  { 65535, 128 }, // ssub_4_ssub_5_ssub_8_ssub_9
983
  { 128, 192 }, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
984
  { 65535, 192 }, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
985
  { 65535, 128 }, // ssub_6_ssub_7_dsub_5
986
  { 192, 192 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
987
  { 65535, 192 }, // ssub_6_ssub_7_dsub_5_dsub_7
988
  { 192, 128 }, // ssub_6_ssub_7_ssub_8_ssub_9
989
  { 192, 256 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
990
  { 65535, 128 }, // ssub_8_ssub_9_ssub_12_ssub_13
991
  { 256, 192 }, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
992
  { 65535, 128 }, // dsub_5_dsub_7
993
  { 320, 192 }, // dsub_5_ssub_12_ssub_13_dsub_7
994
  { 320, 128 }, // dsub_5_ssub_12_ssub_13
995
  { 128, 256 }, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
996
};
997
998
extern const char ARMRegStrings[] = {
999
  /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
1000
  /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
1001
  /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
1002
  /* 39 */ 'R', '1', '0', 0,
1003
  /* 43 */ 'S', '1', '0', 0,
1004
  /* 47 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
1005
  /* 63 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
1006
  /* 79 */ 'S', '2', '0', 0,
1007
  /* 83 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
1008
  /* 99 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
1009
  /* 115 */ 'S', '3', '0', 0,
1010
  /* 119 */ 'D', '0', 0,
1011
  /* 122 */ 'Q', '0', 0,
1012
  /* 125 */ 'M', 'V', 'F', 'R', '0', 0,
1013
  /* 131 */ 'S', '0', 0,
1014
  /* 134 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
1015
  /* 145 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
1016
  /* 158 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
1017
  /* 172 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
1018
  /* 180 */ 'S', '1', '1', 0,
1019
  /* 184 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
1020
  /* 196 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
1021
  /* 212 */ 'S', '2', '1', 0,
1022
  /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
1023
  /* 228 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
1024
  /* 244 */ 'S', '3', '1', 0,
1025
  /* 248 */ 'D', '1', 0,
1026
  /* 251 */ 'Q', '0', '_', 'Q', '1', 0,
1027
  /* 257 */ 'M', 'V', 'F', 'R', '1', 0,
1028
  /* 263 */ 'R', '0', '_', 'R', '1', 0,
1029
  /* 269 */ 'S', '1', 0,
1030
  /* 272 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
1031
  /* 286 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
1032
  /* 301 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
1033
  /* 316 */ 'R', '1', '2', 0,
1034
  /* 320 */ 'S', '1', '2', 0,
1035
  /* 324 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
1036
  /* 340 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
1037
  /* 356 */ 'S', '2', '2', 0,
1038
  /* 360 */ 'D', '0', '_', 'D', '2', 0,
1039
  /* 366 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
1040
  /* 375 */ 'Q', '1', '_', 'Q', '2', 0,
1041
  /* 381 */ 'M', 'V', 'F', 'R', '2', 0,
1042
  /* 387 */ 'S', '2', 0,
1043
  /* 390 */ 'F', 'P', 'I', 'N', 'S', 'T', '2', 0,
1044
  /* 398 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
1045
  /* 412 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
1046
  /* 424 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
1047
  /* 440 */ 'S', '1', '3', 0,
1048
  /* 444 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
1049
  /* 460 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
1050
  /* 472 */ 'S', '2', '3', 0,
1051
  /* 476 */ 'D', '1', '_', 'D', '3', 0,
1052
  /* 482 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
1053
  /* 491 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
1054
  /* 503 */ 'R', '2', '_', 'R', '3', 0,
1055
  /* 509 */ 'S', '3', 0,
1056
  /* 512 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
1057
  /* 527 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
1058
  /* 543 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
1059
  /* 559 */ 'S', '1', '4', 0,
1060
  /* 563 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
1061
  /* 579 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
1062
  /* 595 */ 'S', '2', '4', 0,
1063
  /* 599 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
1064
  /* 608 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
1065
  /* 620 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
1066
  /* 632 */ 'R', '4', 0,
1067
  /* 635 */ 'S', '4', 0,
1068
  /* 638 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
1069
  /* 653 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
1070
  /* 665 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
1071
  /* 681 */ 'S', '1', '5', 0,
1072
  /* 685 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
1073
  /* 701 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
1074
  /* 713 */ 'S', '2', '5', 0,
1075
  /* 717 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
1076
  /* 726 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
1077
  /* 735 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
1078
  /* 747 */ 'R', '4', '_', 'R', '5', 0,
1079
  /* 753 */ 'S', '5', 0,
1080
  /* 756 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
1081
  /* 772 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
1082
  /* 788 */ 'S', '1', '6', 0,
1083
  /* 792 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
1084
  /* 808 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
1085
  /* 824 */ 'S', '2', '6', 0,
1086
  /* 828 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
1087
  /* 840 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
1088
  /* 852 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
1089
  /* 864 */ 'R', '6', 0,
1090
  /* 867 */ 'S', '6', 0,
1091
  /* 870 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
1092
  /* 886 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
1093
  /* 898 */ 'S', '1', '7', 0,
1094
  /* 902 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
1095
  /* 918 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
1096
  /* 930 */ 'S', '2', '7', 0,
1097
  /* 934 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
1098
  /* 946 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
1099
  /* 955 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
1100
  /* 967 */ 'R', '6', '_', 'R', '7', 0,
1101
  /* 973 */ 'S', '7', 0,
1102
  /* 976 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
1103
  /* 992 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
1104
  /* 1008 */ 'S', '1', '8', 0,
1105
  /* 1012 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
1106
  /* 1028 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
1107
  /* 1044 */ 'S', '2', '8', 0,
1108
  /* 1048 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
1109
  /* 1060 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
1110
  /* 1072 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
1111
  /* 1084 */ 'R', '8', 0,
1112
  /* 1087 */ 'S', '8', 0,
1113
  /* 1090 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
1114
  /* 1106 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
1115
  /* 1118 */ 'S', '1', '9', 0,
1116
  /* 1122 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
1117
  /* 1138 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
1118
  /* 1150 */ 'S', '2', '9', 0,
1119
  /* 1154 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
1120
  /* 1166 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
1121
  /* 1175 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
1122
  /* 1187 */ 'R', '8', '_', 'R', '9', 0,
1123
  /* 1193 */ 'S', '9', 0,
1124
  /* 1196 */ 'P', 'C', 0,
1125
  /* 1199 */ 'F', 'P', 'E', 'X', 'C', 0,
1126
  /* 1205 */ 'F', 'P', 'S', 'I', 'D', 0,
1127
  /* 1211 */ 'I', 'T', 'S', 'T', 'A', 'T', 'E', 0,
1128
  /* 1219 */ 'R', '1', '2', '_', 'S', 'P', 0,
1129
  /* 1226 */ 'F', 'P', 'S', 'C', 'R', 0,
1130
  /* 1232 */ 'L', 'R', 0,
1131
  /* 1235 */ 'A', 'P', 'S', 'R', 0,
1132
  /* 1240 */ 'C', 'P', 'S', 'R', 0,
1133
  /* 1245 */ 'S', 'P', 'S', 'R', 0,
1134
  /* 1250 */ 'F', 'P', 'I', 'N', 'S', 'T', 0,
1135
  /* 1257 */ 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 0,
1136
  /* 1268 */ 'A', 'P', 'S', 'R', '_', 'N', 'Z', 'C', 'V', 0,
1137
};
1138
1139
extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors
1140
  { 12, 0, 0, 0, 0, 0 },
1141
  { 1235, 16, 16, 2, 66945, 0 },
1142
  { 1268, 16, 16, 2, 66945, 0 },
1143
  { 1240, 16, 16, 2, 66945, 0 },
1144
  { 1199, 16, 16, 2, 66945, 0 },
1145
  { 1250, 16, 16, 2, 66945, 0 },
1146
  { 1226, 16, 16, 2, 17664, 0 },
1147
  { 1257, 16, 16, 2, 17664, 0 },
1148
  { 1205, 16, 16, 2, 66913, 0 },
1149
  { 1211, 16, 16, 2, 66913, 0 },
1150
  { 1232, 16, 16, 2, 66913, 0 },
1151
  { 1196, 16, 16, 2, 66913, 0 },
1152
  { 1223, 16, 1526, 2, 66913, 0 },
1153
  { 1245, 16, 16, 2, 66913, 0 },
1154
  { 119, 350, 4013, 19, 13250, 8 },
1155
  { 248, 357, 2479, 19, 13250, 8 },
1156
  { 363, 364, 3957, 19, 13250, 8 },
1157
  { 479, 378, 3845, 19, 13250, 8 },
1158
  { 605, 392, 3893, 19, 13250, 8 },
1159
  { 723, 406, 3724, 19, 13250, 8 },
1160
  { 837, 420, 3780, 19, 13250, 8 },
1161
  { 943, 434, 3604, 19, 13250, 8 },
1162
  { 1057, 448, 3664, 19, 13250, 8 },
1163
  { 1163, 462, 3484, 19, 13250, 8 },
1164
  { 9, 476, 3544, 19, 13250, 8 },
1165
  { 141, 490, 3364, 19, 13250, 8 },
1166
  { 282, 504, 3424, 19, 13250, 8 },
1167
  { 408, 518, 3244, 19, 13250, 8 },
1168
  { 523, 532, 3304, 19, 13250, 8 },
1169
  { 649, 546, 3149, 19, 13250, 8 },
1170
  { 768, 16, 3208, 2, 17761, 0 },
1171
  { 882, 16, 3078, 2, 17761, 0 },
1172
  { 988, 16, 3113, 2, 17761, 0 },
1173
  { 1102, 16, 3008, 2, 17761, 0 },
1174
  { 59, 16, 3043, 2, 17761, 0 },
1175
  { 192, 16, 2938, 2, 17761, 0 },
1176
  { 336, 16, 2973, 2, 17761, 0 },
1177
  { 456, 16, 2868, 2, 17761, 0 },
1178
  { 575, 16, 2903, 2, 17761, 0 },
1179
  { 697, 16, 2797, 2, 17761, 0 },
1180
  { 804, 16, 2837, 2, 17761, 0 },
1181
  { 914, 16, 2363, 2, 17761, 0 },
1182
  { 1024, 16, 2411, 2, 17761, 0 },
1183
  { 1134, 16, 2384, 2, 17761, 0 },
1184
  { 95, 16, 2429, 2, 17761, 0 },
1185
  { 224, 16, 2789, 2, 17761, 0 },
1186
  { 390, 16, 16, 2, 17761, 0 },
1187
  { 125, 16, 16, 2, 17761, 0 },
1188
  { 257, 16, 16, 2, 17761, 0 },
1189
  { 381, 16, 16, 2, 17761, 0 },
1190
  { 122, 353, 1112, 22, 2196, 11 },
1191
  { 254, 374, 775, 22, 2196, 11 },
1192
  { 378, 402, 314, 22, 2196, 11 },
1193
  { 500, 430, 244, 22, 2196, 11 },
1194
  { 629, 458, 234, 22, 2196, 11 },
1195
  { 744, 486, 224, 22, 2196, 11 },
1196
  { 861, 514, 214, 22, 2196, 11 },
1197
  { 964, 542, 204, 22, 2196, 11 },
1198
  { 1081, 804, 194, 0, 12818, 20 },
1199
  { 1184, 807, 184, 0, 12818, 20 },
1200
  { 35, 810, 174, 0, 12818, 20 },
1201
  { 168, 813, 164, 0, 12818, 20 },
1202
  { 312, 816, 154, 0, 12818, 20 },
1203
  { 436, 819, 591, 0, 12818, 20 },
1204
  { 555, 822, 2447, 0, 12818, 20 },
1205
  { 677, 825, 1106, 0, 12818, 20 },
1206
  { 128, 16, 1373, 2, 66913, 0 },
1207
  { 260, 16, 1371, 2, 66913, 0 },
1208
  { 384, 16, 1371, 2, 66913, 0 },
1209
  { 506, 16, 1369, 2, 66913, 0 },
1210
  { 632, 16, 1369, 2, 66913, 0 },
1211
  { 750, 16, 1367, 2, 66913, 0 },
1212
  { 864, 16, 1367, 2, 66913, 0 },
1213
  { 970, 16, 1365, 2, 66913, 0 },
1214
  { 1084, 16, 1365, 2, 66913, 0 },
1215
  { 1190, 16, 1363, 2, 66913, 0 },
1216
  { 39, 16, 1363, 2, 66913, 0 },
1217
  { 176, 16, 1361, 2, 66913, 0 },
1218
  { 316, 16, 1359, 2, 66913, 0 },
1219
  { 131, 16, 4021, 2, 65585, 0 },
1220
  { 269, 16, 4012, 2, 65585, 0 },
1221
  { 387, 16, 2490, 2, 65585, 0 },
1222
  { 509, 16, 2478, 2, 65585, 0 },
1223
  { 635, 16, 3974, 2, 65585, 0 },
1224
  { 753, 16, 3956, 2, 65585, 0 },
1225
  { 867, 16, 3863, 2, 65585, 0 },
1226
  { 973, 16, 3844, 2, 65585, 0 },
1227
  { 1087, 16, 3914, 2, 65585, 0 },
1228
  { 1193, 16, 3892, 2, 65585, 0 },
1229
  { 43, 16, 3745, 2, 65585, 0 },
1230
  { 180, 16, 3723, 2, 65585, 0 },
1231
  { 320, 16, 3803, 2, 65585, 0 },
1232
  { 440, 16, 3779, 2, 65585, 0 },
1233
  { 559, 16, 3627, 2, 65585, 0 },
1234
  { 681, 16, 3603, 2, 65585, 0 },
1235
  { 788, 16, 3687, 2, 65585, 0 },
1236
  { 898, 16, 3663, 2, 65585, 0 },
1237
  { 1008, 16, 3507, 2, 65585, 0 },
1238
  { 1118, 16, 3483, 2, 65585, 0 },
1239
  { 79, 16, 3567, 2, 65585, 0 },
1240
  { 212, 16, 3543, 2, 65585, 0 },
1241
  { 356, 16, 3387, 2, 65585, 0 },
1242
  { 472, 16, 3363, 2, 65585, 0 },
1243
  { 595, 16, 3447, 2, 65585, 0 },
1244
  { 713, 16, 3423, 2, 65585, 0 },
1245
  { 824, 16, 3267, 2, 65585, 0 },
1246
  { 930, 16, 3243, 2, 65585, 0 },
1247
  { 1044, 16, 3327, 2, 65585, 0 },
1248
  { 1150, 16, 3303, 2, 65585, 0 },
1249
  { 115, 16, 3172, 2, 65585, 0 },
1250
  { 244, 16, 3148, 2, 65585, 0 },
1251
  { 360, 367, 4015, 29, 5426, 23 },
1252
  { 476, 381, 2502, 29, 5426, 23 },
1253
  { 602, 395, 3992, 29, 5426, 23 },
1254
  { 720, 409, 3882, 29, 5426, 23 },
1255
  { 834, 423, 3936, 29, 5426, 23 },
1256
  { 940, 437, 3767, 29, 5426, 23 },
1257
  { 1054, 451, 3827, 29, 5426, 23 },
1258
  { 1160, 465, 3651, 29, 5426, 23 },
1259
  { 6, 479, 3711, 29, 5426, 23 },
1260
  { 151, 493, 3531, 29, 5426, 23 },
1261
  { 278, 507, 3591, 29, 5426, 23 },
1262
  { 404, 521, 3411, 29, 5426, 23 },
1263
  { 519, 535, 3471, 29, 5426, 23 },
1264
  { 645, 549, 3291, 29, 5426, 23 },
1265
  { 764, 4007, 3351, 11, 17602, 35 },
1266
  { 878, 3948, 3196, 11, 13522, 35 },
1267
  { 984, 1080, 3231, 8, 17329, 39 },
1268
  { 1098, 1080, 3101, 8, 17329, 39 },
1269
  { 55, 1080, 3136, 8, 17329, 39 },
1270
  { 204, 1080, 3031, 8, 17329, 39 },
1271
  { 332, 1080, 3066, 8, 17329, 39 },
1272
  { 452, 1080, 2961, 8, 17329, 39 },
1273
  { 571, 1080, 2996, 8, 17329, 39 },
1274
  { 693, 1080, 2891, 8, 17329, 39 },
1275
  { 800, 1080, 2926, 8, 17329, 39 },
1276
  { 910, 1080, 2820, 8, 17329, 39 },
1277
  { 1020, 1080, 2858, 8, 17329, 39 },
1278
  { 1130, 1080, 2401, 8, 17329, 39 },
1279
  { 91, 1080, 2440, 8, 17329, 39 },
1280
  { 236, 1080, 2791, 8, 17329, 39 },
1281
  { 251, 1339, 1114, 168, 1044, 57 },
1282
  { 375, 1319, 347, 168, 1044, 57 },
1283
  { 497, 1299, 142, 168, 1044, 57 },
1284
  { 626, 1279, 142, 168, 1044, 57 },
1285
  { 741, 1259, 142, 168, 1044, 57 },
1286
  { 858, 1239, 142, 168, 1044, 57 },
1287
  { 961, 1219, 142, 168, 1044, 57 },
1288
  { 1078, 1203, 142, 88, 1456, 74 },
1289
  { 1181, 1191, 142, 76, 2114, 87 },
1290
  { 32, 1179, 142, 76, 2114, 87 },
1291
  { 164, 1167, 142, 76, 2114, 87 },
1292
  { 308, 1155, 142, 76, 2114, 87 },
1293
  { 432, 1143, 142, 76, 2114, 87 },
1294
  { 551, 1131, 344, 76, 2114, 87 },
1295
  { 673, 1119, 1108, 76, 2114, 87 },
1296
  { 491, 2156, 16, 474, 4, 149 },
1297
  { 620, 2101, 16, 474, 4, 149 },
1298
  { 735, 2046, 16, 474, 4, 149 },
1299
  { 852, 1991, 16, 474, 4, 149 },
1300
  { 955, 1936, 16, 474, 4, 149 },
1301
  { 1072, 1885, 16, 423, 272, 166 },
1302
  { 1175, 1838, 16, 376, 512, 181 },
1303
  { 26, 1795, 16, 333, 720, 194 },
1304
  { 158, 1756, 16, 294, 1186, 205 },
1305
  { 301, 1717, 16, 294, 1186, 205 },
1306
  { 424, 1678, 16, 294, 1186, 205 },
1307
  { 543, 1639, 16, 294, 1186, 205 },
1308
  { 665, 1600, 16, 294, 1186, 205 },
1309
  { 1219, 4114, 16, 16, 17856, 2 },
1310
  { 263, 783, 16, 16, 8946, 5 },
1311
  { 503, 786, 16, 16, 8946, 5 },
1312
  { 747, 789, 16, 16, 8946, 5 },
1313
  { 967, 792, 16, 16, 8946, 5 },
1314
  { 1187, 795, 16, 16, 8946, 5 },
1315
  { 172, 798, 16, 16, 8946, 5 },
1316
  { 366, 1513, 1113, 63, 1570, 28 },
1317
  { 482, 4169, 2511, 63, 1570, 28 },
1318
  { 611, 1500, 778, 63, 1570, 28 },
1319
  { 726, 4156, 770, 63, 1570, 28 },
1320
  { 843, 1487, 317, 63, 1570, 28 },
1321
  { 946, 4143, 660, 63, 1570, 28 },
1322
  { 1063, 1474, 308, 63, 1570, 28 },
1323
  { 1166, 4130, 654, 63, 1570, 28 },
1324
  { 16, 1461, 302, 63, 1570, 28 },
1325
  { 134, 4117, 648, 63, 1570, 28 },
1326
  { 289, 1448, 296, 63, 1570, 28 },
1327
  { 412, 4101, 642, 63, 1570, 28 },
1328
  { 531, 1435, 290, 63, 1570, 28 },
1329
  { 653, 4088, 636, 63, 1570, 28 },
1330
  { 776, 1424, 284, 52, 1680, 42 },
1331
  { 886, 4079, 630, 43, 1872, 48 },
1332
  { 996, 1417, 278, 36, 2401, 53 },
1333
  { 1106, 4072, 624, 36, 2401, 53 },
1334
  { 67, 1410, 272, 36, 2401, 53 },
1335
  { 184, 4065, 618, 36, 2401, 53 },
1336
  { 344, 1403, 266, 36, 2401, 53 },
1337
  { 460, 4058, 612, 36, 2401, 53 },
1338
  { 583, 1396, 260, 36, 2401, 53 },
1339
  { 701, 4051, 606, 36, 2401, 53 },
1340
  { 812, 1389, 254, 36, 2401, 53 },
1341
  { 918, 4044, 600, 36, 2401, 53 },
1342
  { 1032, 1382, 765, 36, 2401, 53 },
1343
  { 1138, 4037, 2455, 36, 2401, 53 },
1344
  { 103, 1375, 2474, 36, 2401, 53 },
1345
  { 216, 4030, 1107, 36, 2401, 53 },
1346
  { 599, 1026, 4018, 212, 5314, 92 },
1347
  { 717, 1014, 3953, 212, 5314, 92 },
1348
  { 831, 1002, 4002, 212, 5314, 92 },
1349
  { 937, 990, 3909, 212, 5314, 92 },
1350
  { 1051, 978, 3909, 212, 5314, 92 },
1351
  { 1157, 966, 3798, 212, 5314, 92 },
1352
  { 3, 954, 3798, 212, 5314, 92 },
1353
  { 148, 942, 3682, 212, 5314, 92 },
1354
  { 275, 930, 3682, 212, 5314, 92 },
1355
  { 401, 918, 3562, 212, 5314, 92 },
1356
  { 515, 906, 3562, 212, 5314, 92 },
1357
  { 641, 894, 3442, 212, 5314, 92 },
1358
  { 760, 1070, 3442, 202, 17506, 99 },
1359
  { 874, 1060, 3322, 202, 13426, 99 },
1360
  { 980, 1052, 3322, 194, 14226, 105 },
1361
  { 1094, 1044, 3226, 194, 13698, 105 },
1362
  { 51, 1038, 3226, 188, 14049, 110 },
1363
  { 200, 1038, 3131, 188, 14049, 110 },
1364
  { 328, 1038, 3131, 188, 14049, 110 },
1365
  { 448, 1038, 3061, 188, 14049, 110 },
1366
  { 567, 1038, 3061, 188, 14049, 110 },
1367
  { 689, 1038, 2991, 188, 14049, 110 },
1368
  { 796, 1038, 2991, 188, 14049, 110 },
1369
  { 906, 1038, 2921, 188, 14049, 110 },
1370
  { 1016, 1038, 2921, 188, 14049, 110 },
1371
  { 1126, 1038, 2832, 188, 14049, 110 },
1372
  { 87, 1038, 2855, 188, 14049, 110 },
1373
  { 232, 1038, 2794, 188, 14049, 110 },
1374
  { 828, 2677, 4010, 276, 5170, 114 },
1375
  { 934, 2659, 3951, 276, 5170, 114 },
1376
  { 1048, 2641, 3951, 276, 5170, 114 },
1377
  { 1154, 2623, 3842, 276, 5170, 114 },
1378
  { 0, 2605, 3842, 276, 5170, 114 },
1379
  { 145, 2587, 3743, 276, 5170, 114 },
1380
  { 272, 2569, 3743, 276, 5170, 114 },
1381
  { 398, 2551, 3625, 276, 5170, 114 },
1382
  { 512, 2533, 3625, 276, 5170, 114 },
1383
  { 638, 2515, 3505, 276, 5170, 114 },
1384
  { 756, 2773, 3505, 260, 17378, 123 },
1385
  { 870, 2757, 3385, 260, 13298, 123 },
1386
  { 976, 2743, 3385, 246, 14114, 131 },
1387
  { 1090, 2729, 3265, 246, 13586, 131 },
1388
  { 47, 2717, 3265, 234, 13954, 138 },
1389
  { 196, 2705, 3170, 234, 13778, 138 },
1390
  { 324, 2695, 3170, 224, 13873, 144 },
1391
  { 444, 2695, 3099, 224, 13873, 144 },
1392
  { 563, 2695, 3099, 224, 13873, 144 },
1393
  { 685, 2695, 3029, 224, 13873, 144 },
1394
  { 792, 2695, 3029, 224, 13873, 144 },
1395
  { 902, 2695, 2959, 224, 13873, 144 },
1396
  { 1012, 2695, 2959, 224, 13873, 144 },
1397
  { 1122, 2695, 2856, 224, 13873, 144 },
1398
  { 83, 2695, 2856, 224, 13873, 144 },
1399
  { 228, 2695, 2795, 224, 13873, 144 },
1400
  { 369, 360, 2509, 22, 1956, 11 },
1401
  { 614, 388, 583, 22, 1956, 11 },
1402
  { 846, 416, 756, 22, 1956, 11 },
1403
  { 1066, 444, 747, 22, 1956, 11 },
1404
  { 19, 472, 738, 22, 1956, 11 },
1405
  { 293, 500, 729, 22, 1956, 11 },
1406
  { 535, 528, 720, 22, 1956, 11 },
1407
  { 780, 3839, 711, 3, 2336, 16 },
1408
  { 1000, 562, 702, 0, 8898, 20 },
1409
  { 71, 565, 693, 0, 8898, 20 },
1410
  { 348, 568, 684, 0, 8898, 20 },
1411
  { 587, 571, 675, 0, 8898, 20 },
1412
  { 816, 574, 666, 0, 8898, 20 },
1413
  { 1036, 577, 2460, 0, 8898, 20 },
1414
  { 107, 580, 2468, 0, 8898, 20 },
1415
  { 608, 2343, 2488, 148, 900, 57 },
1416
  { 840, 2323, 588, 148, 900, 57 },
1417
  { 1060, 2303, 588, 148, 900, 57 },
1418
  { 13, 2283, 588, 148, 900, 57 },
1419
  { 286, 2263, 588, 148, 900, 57 },
1420
  { 527, 2243, 588, 148, 900, 57 },
1421
  { 772, 2225, 588, 130, 1328, 66 },
1422
  { 992, 2211, 588, 116, 1776, 81 },
1423
  { 63, 1588, 588, 104, 2034, 87 },
1424
  { 340, 1576, 588, 104, 2034, 87 },
1425
  { 579, 1564, 588, 104, 2034, 87 },
1426
  { 808, 1552, 588, 104, 2034, 87 },
1427
  { 1028, 1540, 588, 104, 2034, 87 },
1428
  { 99, 1528, 2382, 104, 2034, 87 },
1429
};
1430
1431
extern const MCPhysReg ARMRegUnitRoots[][2] = {
1432
  { ARM::APSR },
1433
  { ARM::APSR_NZCV },
1434
  { ARM::CPSR },
1435
  { ARM::FPEXC },
1436
  { ARM::FPINST },
1437
  { ARM::FPSCR, ARM::FPSCR_NZCV },
1438
  { ARM::FPSID },
1439
  { ARM::ITSTATE },
1440
  { ARM::LR },
1441
  { ARM::PC },
1442
  { ARM::SP },
1443
  { ARM::SPSR },
1444
  { ARM::S0 },
1445
  { ARM::S1 },
1446
  { ARM::S2 },
1447
  { ARM::S3 },
1448
  { ARM::S4 },
1449
  { ARM::S5 },
1450
  { ARM::S6 },
1451
  { ARM::S7 },
1452
  { ARM::S8 },
1453
  { ARM::S9 },
1454
  { ARM::S10 },
1455
  { ARM::S11 },
1456
  { ARM::S12 },
1457
  { ARM::S13 },
1458
  { ARM::S14 },
1459
  { ARM::S15 },
1460
  { ARM::S16 },
1461
  { ARM::S17 },
1462
  { ARM::S18 },
1463
  { ARM::S19 },
1464
  { ARM::S20 },
1465
  { ARM::S21 },
1466
  { ARM::S22 },
1467
  { ARM::S23 },
1468
  { ARM::S24 },
1469
  { ARM::S25 },
1470
  { ARM::S26 },
1471
  { ARM::S27 },
1472
  { ARM::S28 },
1473
  { ARM::S29 },
1474
  { ARM::S30 },
1475
  { ARM::S31 },
1476
  { ARM::D16 },
1477
  { ARM::D17 },
1478
  { ARM::D18 },
1479
  { ARM::D19 },
1480
  { ARM::D20 },
1481
  { ARM::D21 },
1482
  { ARM::D22 },
1483
  { ARM::D23 },
1484
  { ARM::D24 },
1485
  { ARM::D25 },
1486
  { ARM::D26 },
1487
  { ARM::D27 },
1488
  { ARM::D28 },
1489
  { ARM::D29 },
1490
  { ARM::D30 },
1491
  { ARM::D31 },
1492
  { ARM::FPINST2 },
1493
  { ARM::MVFR0 },
1494
  { ARM::MVFR1 },
1495
  { ARM::MVFR2 },
1496
  { ARM::R0 },
1497
  { ARM::R1 },
1498
  { ARM::R2 },
1499
  { ARM::R3 },
1500
  { ARM::R4 },
1501
  { ARM::R5 },
1502
  { ARM::R6 },
1503
  { ARM::R7 },
1504
  { ARM::R8 },
1505
  { ARM::R9 },
1506
  { ARM::R10 },
1507
  { ARM::R11 },
1508
  { ARM::R12 },
1509
};
1510
1511
namespace {     // Register classes...
1512
  // HPR Register Class...
1513
  const MCPhysReg HPR[] = {
1514
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, 
1515
  };
1516
1517
  // HPR Bit set.
1518
  const uint8_t HPRBits[] = {
1519
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
1520
  };
1521
1522
  // SPR Register Class...
1523
  const MCPhysReg SPR[] = {
1524
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, 
1525
  };
1526
1527
  // SPR Bit set.
1528
  const uint8_t SPRBits[] = {
1529
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
1530
  };
1531
1532
  // GPR Register Class...
1533
  const MCPhysReg GPR[] = {
1534
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
1535
  };
1536
1537
  // GPR Bit set.
1538
  const uint8_t GPRBits[] = {
1539
    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1540
  };
1541
1542
  // GPRwithAPSR Register Class...
1543
  const MCPhysReg GPRwithAPSR[] = {
1544
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV, 
1545
  };
1546
1547
  // GPRwithAPSR Bit set.
1548
  const uint8_t GPRwithAPSRBits[] = {
1549
    0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1550
  };
1551
1552
  // SPR_8 Register Class...
1553
  const MCPhysReg SPR_8[] = {
1554
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, 
1555
  };
1556
1557
  // SPR_8 Bit set.
1558
  const uint8_t SPR_8Bits[] = {
1559
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
1560
  };
1561
1562
  // GPRnopc Register Class...
1563
  const MCPhysReg GPRnopc[] = {
1564
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
1565
  };
1566
1567
  // GPRnopc Bit set.
1568
  const uint8_t GPRnopcBits[] = {
1569
    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1570
  };
1571
1572
  // rGPR Register Class...
1573
  const MCPhysReg rGPR[] = {
1574
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
1575
  };
1576
1577
  // rGPR Bit set.
1578
  const uint8_t rGPRBits[] = {
1579
    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1580
  };
1581
1582
  // tGPRwithpc Register Class...
1583
  const MCPhysReg tGPRwithpc[] = {
1584
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC, 
1585
  };
1586
1587
  // tGPRwithpc Bit set.
1588
  const uint8_t tGPRwithpcBits[] = {
1589
    0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1590
  };
1591
1592
  // hGPR Register Class...
1593
  const MCPhysReg hGPR[] = {
1594
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
1595
  };
1596
1597
  // hGPR Bit set.
1598
  const uint8_t hGPRBits[] = {
1599
    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
1600
  };
1601
1602
  // tGPR Register Class...
1603
  const MCPhysReg tGPR[] = {
1604
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, 
1605
  };
1606
1607
  // tGPR Bit set.
1608
  const uint8_t tGPRBits[] = {
1609
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1610
  };
1611
1612
  // GPRnopc_and_hGPR Register Class...
1613
  const MCPhysReg GPRnopc_and_hGPR[] = {
1614
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
1615
  };
1616
1617
  // GPRnopc_and_hGPR Bit set.
1618
  const uint8_t GPRnopc_and_hGPRBits[] = {
1619
    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
1620
  };
1621
1622
  // hGPR_and_rGPR Register Class...
1623
  const MCPhysReg hGPR_and_rGPR[] = {
1624
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
1625
  };
1626
1627
  // hGPR_and_rGPR Bit set.
1628
  const uint8_t hGPR_and_rGPRBits[] = {
1629
    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
1630
  };
1631
1632
  // tcGPR Register Class...
1633
  const MCPhysReg tcGPR[] = {
1634
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, 
1635
  };
1636
1637
  // tcGPR Bit set.
1638
  const uint8_t tcGPRBits[] = {
1639
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40, 
1640
  };
1641
1642
  // tGPR_and_tcGPR Register Class...
1643
  const MCPhysReg tGPR_and_tcGPR[] = {
1644
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, 
1645
  };
1646
1647
  // tGPR_and_tcGPR Bit set.
1648
  const uint8_t tGPR_and_tcGPRBits[] = {
1649
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
1650
  };
1651
1652
  // CCR Register Class...
1653
  const MCPhysReg CCR[] = {
1654
    ARM::CPSR, 
1655
  };
1656
1657
  // CCR Bit set.
1658
  const uint8_t CCRBits[] = {
1659
    0x08, 
1660
  };
1661
1662
  // GPRsp Register Class...
1663
  const MCPhysReg GPRsp[] = {
1664
    ARM::SP, 
1665
  };
1666
1667
  // GPRsp Bit set.
1668
  const uint8_t GPRspBits[] = {
1669
    0x00, 0x10, 
1670
  };
1671
1672
  // hGPR_and_tGPRwithpc Register Class...
1673
  const MCPhysReg hGPR_and_tGPRwithpc[] = {
1674
    ARM::PC, 
1675
  };
1676
1677
  // hGPR_and_tGPRwithpc Bit set.
1678
  const uint8_t hGPR_and_tGPRwithpcBits[] = {
1679
    0x00, 0x08, 
1680
  };
1681
1682
  // hGPR_and_tcGPR Register Class...
1683
  const MCPhysReg hGPR_and_tcGPR[] = {
1684
    ARM::R12, 
1685
  };
1686
1687
  // hGPR_and_tcGPR Bit set.
1688
  const uint8_t hGPR_and_tcGPRBits[] = {
1689
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
1690
  };
1691
1692
  // DPR Register Class...
1693
  const MCPhysReg DPR[] = {
1694
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 
1695
  };
1696
1697
  // DPR Bit set.
1698
  const uint8_t DPRBits[] = {
1699
    0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
1700
  };
1701
1702
  // DPR_VFP2 Register Class...
1703
  const MCPhysReg DPR_VFP2[] = {
1704
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, 
1705
  };
1706
1707
  // DPR_VFP2 Bit set.
1708
  const uint8_t DPR_VFP2Bits[] = {
1709
    0x00, 0xc0, 0xff, 0x3f, 
1710
  };
1711
1712
  // DPR_8 Register Class...
1713
  const MCPhysReg DPR_8[] = {
1714
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, 
1715
  };
1716
1717
  // DPR_8 Bit set.
1718
  const uint8_t DPR_8Bits[] = {
1719
    0x00, 0xc0, 0x3f, 
1720
  };
1721
1722
  // GPRPair Register Class...
1723
  const MCPhysReg GPRPair[] = {
1724
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
1725
  };
1726
1727
  // GPRPair Bit set.
1728
  const uint8_t GPRPairBits[] = {
1729
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 
1730
  };
1731
1732
  // GPRPair_with_gsub_1_in_rGPR Register Class...
1733
  const MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = {
1734
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, 
1735
  };
1736
1737
  // GPRPair_with_gsub_1_in_rGPR Bit set.
1738
  const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = {
1739
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 
1740
  };
1741
1742
  // GPRPair_with_gsub_0_in_tGPR Register Class...
1743
  const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
1744
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 
1745
  };
1746
1747
  // GPRPair_with_gsub_0_in_tGPR Bit set.
1748
  const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
1749
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
1750
  };
1751
1752
  // GPRPair_with_gsub_0_in_hGPR Register Class...
1753
  const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
1754
    ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
1755
  };
1756
1757
  // GPRPair_with_gsub_0_in_hGPR Bit set.
1758
  const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
1759
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 
1760
  };
1761
1762
  // GPRPair_with_gsub_0_in_tcGPR Register Class...
1763
  const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
1764
    ARM::R0_R1, ARM::R2_R3, ARM::R12_SP, 
1765
  };
1766
1767
  // GPRPair_with_gsub_0_in_tcGPR Bit set.
1768
  const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
1769
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 
1770
  };
1771
1772
  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class...
1773
  const MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = {
1774
    ARM::R8_R9, ARM::R10_R11, 
1775
  };
1776
1777
  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set.
1778
  const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = {
1779
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 
1780
  };
1781
1782
  // GPRPair_with_gsub_1_in_tcGPR Register Class...
1783
  const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
1784
    ARM::R0_R1, ARM::R2_R3, 
1785
  };
1786
1787
  // GPRPair_with_gsub_1_in_tcGPR Bit set.
1788
  const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
1789
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 
1790
  };
1791
1792
  // GPRPair_with_gsub_1_in_GPRsp Register Class...
1793
  const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
1794
    ARM::R12_SP, 
1795
  };
1796
1797
  // GPRPair_with_gsub_1_in_GPRsp Bit set.
1798
  const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
1799
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
1800
  };
1801
1802
  // DPairSpc Register Class...
1803
  const MCPhysReg DPairSpc[] = {
1804
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31, 
1805
  };
1806
1807
  // DPairSpc Bit set.
1808
  const uint8_t DPairSpcBits[] = {
1809
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 
1810
  };
1811
1812
  // DPairSpc_with_ssub_0 Register Class...
1813
  const MCPhysReg DPairSpc_with_ssub_0[] = {
1814
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 
1815
  };
1816
1817
  // DPairSpc_with_ssub_0 Bit set.
1818
  const uint8_t DPairSpc_with_ssub_0Bits[] = {
1819
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
1820
  };
1821
1822
  // DPairSpc_with_ssub_4 Register Class...
1823
  const MCPhysReg DPairSpc_with_ssub_4[] = {
1824
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, 
1825
  };
1826
1827
  // DPairSpc_with_ssub_4 Bit set.
1828
  const uint8_t DPairSpc_with_ssub_4Bits[] = {
1829
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 
1830
  };
1831
1832
  // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
1833
  const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
1834
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 
1835
  };
1836
1837
  // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
1838
  const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
1839
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
1840
  };
1841
1842
  // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
1843
  const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
1844
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, 
1845
  };
1846
1847
  // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
1848
  const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
1849
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 
1850
  };
1851
1852
  // DPair Register Class...
1853
  const MCPhysReg DPair[] = {
1854
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15, 
1855
  };
1856
1857
  // DPair Bit set.
1858
  const uint8_t DPairBits[] = {
1859
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
1860
  };
1861
1862
  // DPair_with_ssub_0 Register Class...
1863
  const MCPhysReg DPair_with_ssub_0[] = {
1864
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, 
1865
  };
1866
1867
  // DPair_with_ssub_0 Bit set.
1868
  const uint8_t DPair_with_ssub_0Bits[] = {
1869
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
1870
  };
1871
1872
  // QPR Register Class...
1873
  const MCPhysReg QPR[] = {
1874
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 
1875
  };
1876
1877
  // QPR Bit set.
1878
  const uint8_t QPRBits[] = {
1879
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
1880
  };
1881
1882
  // DPair_with_ssub_2 Register Class...
1883
  const MCPhysReg DPair_with_ssub_2[] = {
1884
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, 
1885
  };
1886
1887
  // DPair_with_ssub_2 Bit set.
1888
  const uint8_t DPair_with_ssub_2Bits[] = {
1889
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
1890
  };
1891
1892
  // DPair_with_dsub_0_in_DPR_8 Register Class...
1893
  const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
1894
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, 
1895
  };
1896
1897
  // DPair_with_dsub_0_in_DPR_8 Bit set.
1898
  const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
1899
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
1900
  };
1901
1902
  // QPR_VFP2 Register Class...
1903
  const MCPhysReg QPR_VFP2[] = {
1904
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 
1905
  };
1906
1907
  // QPR_VFP2 Bit set.
1908
  const uint8_t QPR_VFP2Bits[] = {
1909
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1910
  };
1911
1912
  // DPair_with_dsub_1_in_DPR_8 Register Class...
1913
  const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
1914
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, 
1915
  };
1916
1917
  // DPair_with_dsub_1_in_DPR_8 Bit set.
1918
  const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
1919
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
1920
  };
1921
1922
  // QPR_8 Register Class...
1923
  const MCPhysReg QPR_8[] = {
1924
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 
1925
  };
1926
1927
  // QPR_8 Bit set.
1928
  const uint8_t QPR_8Bits[] = {
1929
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
1930
  };
1931
1932
  // DTriple Register Class...
1933
  const MCPhysReg DTriple[] = {
1934
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31, 
1935
  };
1936
1937
  // DTriple Bit set.
1938
  const uint8_t DTripleBits[] = {
1939
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, 
1940
  };
1941
1942
  // DTripleSpc Register Class...
1943
  const MCPhysReg DTripleSpc[] = {
1944
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
1945
  };
1946
1947
  // DTripleSpc Bit set.
1948
  const uint8_t DTripleSpcBits[] = {
1949
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
1950
  };
1951
1952
  // DTripleSpc_with_ssub_0 Register Class...
1953
  const MCPhysReg DTripleSpc_with_ssub_0[] = {
1954
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
1955
  };
1956
1957
  // DTripleSpc_with_ssub_0 Bit set.
1958
  const uint8_t DTripleSpc_with_ssub_0Bits[] = {
1959
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
1960
  };
1961
1962
  // DTriple_with_ssub_0 Register Class...
1963
  const MCPhysReg DTriple_with_ssub_0[] = {
1964
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, 
1965
  };
1966
1967
  // DTriple_with_ssub_0 Bit set.
1968
  const uint8_t DTriple_with_ssub_0Bits[] = {
1969
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
1970
  };
1971
1972
  // DTriple_with_qsub_0_in_QPR Register Class...
1973
  const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
1974
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30, 
1975
  };
1976
1977
  // DTriple_with_qsub_0_in_QPR Bit set.
1978
  const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
1979
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, 
1980
  };
1981
1982
  // DTriple_with_ssub_2 Register Class...
1983
  const MCPhysReg DTriple_with_ssub_2[] = {
1984
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, 
1985
  };
1986
1987
  // DTriple_with_ssub_2 Bit set.
1988
  const uint8_t DTriple_with_ssub_2Bits[] = {
1989
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 
1990
  };
1991
1992
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1993
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1994
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31, 
1995
  };
1996
1997
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1998
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1999
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a, 
2000
  };
2001
2002
  // DTripleSpc_with_ssub_4 Register Class...
2003
  const MCPhysReg DTripleSpc_with_ssub_4[] = {
2004
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
2005
  };
2006
2007
  // DTripleSpc_with_ssub_4 Bit set.
2008
  const uint8_t DTripleSpc_with_ssub_4Bits[] = {
2009
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
2010
  };
2011
2012
  // DTriple_with_ssub_4 Register Class...
2013
  const MCPhysReg DTriple_with_ssub_4[] = {
2014
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, 
2015
  };
2016
2017
  // DTriple_with_ssub_4 Bit set.
2018
  const uint8_t DTriple_with_ssub_4Bits[] = {
2019
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, 
2020
  };
2021
2022
  // DTripleSpc_with_ssub_8 Register Class...
2023
  const MCPhysReg DTripleSpc_with_ssub_8[] = {
2024
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
2025
  };
2026
2027
  // DTripleSpc_with_ssub_8 Bit set.
2028
  const uint8_t DTripleSpc_with_ssub_8Bits[] = {
2029
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
2030
  };
2031
2032
  // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
2033
  const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
2034
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
2035
  };
2036
2037
  // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
2038
  const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
2039
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2040
  };
2041
2042
  // DTriple_with_dsub_0_in_DPR_8 Register Class...
2043
  const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
2044
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, 
2045
  };
2046
2047
  // DTriple_with_dsub_0_in_DPR_8 Bit set.
2048
  const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
2049
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 
2050
  };
2051
2052
  // DTriple_with_qsub_0_in_QPR_VFP2 Register Class...
2053
  const MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = {
2054
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, 
2055
  };
2056
2057
  // DTriple_with_qsub_0_in_QPR_VFP2 Bit set.
2058
  const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = {
2059
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 
2060
  };
2061
2062
  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2063
  const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2064
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, 
2065
  };
2066
2067
  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2068
  const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2069
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 
2070
  };
2071
2072
  // DTriple_with_dsub_1_in_DPR_8 Register Class...
2073
  const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
2074
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, 
2075
  };
2076
2077
  // DTriple_with_dsub_1_in_DPR_8 Bit set.
2078
  const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
2079
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
2080
  };
2081
2082
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
2083
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
2084
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, 
2085
  };
2086
2087
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
2088
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
2089
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, 
2090
  };
2091
2092
  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Register Class...
2093
  const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR[] = {
2094
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, 
2095
  };
2096
2097
  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Bit set.
2098
  const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits[] = {
2099
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 
2100
  };
2101
2102
  // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
2103
  const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
2104
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
2105
  };
2106
2107
  // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
2108
  const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
2109
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
2110
  };
2111
2112
  // DTriple_with_dsub_2_in_DPR_8 Register Class...
2113
  const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
2114
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, 
2115
  };
2116
2117
  // DTriple_with_dsub_2_in_DPR_8 Bit set.
2118
  const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
2119
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 
2120
  };
2121
2122
  // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
2123
  const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
2124
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
2125
  };
2126
2127
  // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
2128
  const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
2129
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
2130
  };
2131
2132
  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2133
  const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2134
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, 
2135
  };
2136
2137
  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2138
  const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2139
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 
2140
  };
2141
2142
  // DTriple_with_qsub_0_in_QPR_8 Register Class...
2143
  const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
2144
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, 
2145
  };
2146
2147
  // DTriple_with_qsub_0_in_QPR_8 Bit set.
2148
  const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
2149
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 
2150
  };
2151
2152
  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class...
2153
  const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = {
2154
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, 
2155
  };
2156
2157
  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set.
2158
  const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = {
2159
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 
2160
  };
2161
2162
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
2163
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2164
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, 
2165
  };
2166
2167
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
2168
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
2169
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 
2170
  };
2171
2172
  // DQuadSpc Register Class...
2173
  const MCPhysReg DQuadSpc[] = {
2174
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
2175
  };
2176
2177
  // DQuadSpc Bit set.
2178
  const uint8_t DQuadSpcBits[] = {
2179
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
2180
  };
2181
2182
  // DQuadSpc_with_ssub_0 Register Class...
2183
  const MCPhysReg DQuadSpc_with_ssub_0[] = {
2184
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
2185
  };
2186
2187
  // DQuadSpc_with_ssub_0 Bit set.
2188
  const uint8_t DQuadSpc_with_ssub_0Bits[] = {
2189
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
2190
  };
2191
2192
  // DQuadSpc_with_ssub_4 Register Class...
2193
  const MCPhysReg DQuadSpc_with_ssub_4[] = {
2194
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
2195
  };
2196
2197
  // DQuadSpc_with_ssub_4 Bit set.
2198
  const uint8_t DQuadSpc_with_ssub_4Bits[] = {
2199
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
2200
  };
2201
2202
  // DQuadSpc_with_ssub_8 Register Class...
2203
  const MCPhysReg DQuadSpc_with_ssub_8[] = {
2204
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
2205
  };
2206
2207
  // DQuadSpc_with_ssub_8 Bit set.
2208
  const uint8_t DQuadSpc_with_ssub_8Bits[] = {
2209
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
2210
  };
2211
2212
  // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
2213
  const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
2214
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
2215
  };
2216
2217
  // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
2218
  const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
2219
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2220
  };
2221
2222
  // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
2223
  const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
2224
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
2225
  };
2226
2227
  // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
2228
  const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
2229
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
2230
  };
2231
2232
  // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
2233
  const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
2234
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
2235
  };
2236
2237
  // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
2238
  const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
2239
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
2240
  };
2241
2242
  // DQuad Register Class...
2243
  const MCPhysReg DQuad[] = {
2244
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15, 
2245
  };
2246
2247
  // DQuad Bit set.
2248
  const uint8_t DQuadBits[] = {
2249
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
2250
  };
2251
2252
  // DQuad_with_ssub_0 Register Class...
2253
  const MCPhysReg DQuad_with_ssub_0[] = {
2254
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, 
2255
  };
2256
2257
  // DQuad_with_ssub_0 Bit set.
2258
  const uint8_t DQuad_with_ssub_0Bits[] = {
2259
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
2260
  };
2261
2262
  // DQuad_with_ssub_2 Register Class...
2263
  const MCPhysReg DQuad_with_ssub_2[] = {
2264
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, 
2265
  };
2266
2267
  // DQuad_with_ssub_2 Bit set.
2268
  const uint8_t DQuad_with_ssub_2Bits[] = {
2269
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
2270
  };
2271
2272
  // QQPR Register Class...
2273
  const MCPhysReg QQPR[] = {
2274
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, 
2275
  };
2276
2277
  // QQPR Bit set.
2278
  const uint8_t QQPRBits[] = {
2279
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2280
  };
2281
2282
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2283
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2284
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30, 
2285
  };
2286
2287
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2288
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2289
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
2290
  };
2291
2292
  // DQuad_with_ssub_4 Register Class...
2293
  const MCPhysReg DQuad_with_ssub_4[] = {
2294
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, 
2295
  };
2296
2297
  // DQuad_with_ssub_4 Bit set.
2298
  const uint8_t DQuad_with_ssub_4Bits[] = {
2299
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
2300
  };
2301
2302
  // DQuad_with_ssub_6 Register Class...
2303
  const MCPhysReg DQuad_with_ssub_6[] = {
2304
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, 
2305
  };
2306
2307
  // DQuad_with_ssub_6 Bit set.
2308
  const uint8_t DQuad_with_ssub_6Bits[] = {
2309
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
2310
  };
2311
2312
  // DQuad_with_dsub_0_in_DPR_8 Register Class...
2313
  const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
2314
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, 
2315
  };
2316
2317
  // DQuad_with_dsub_0_in_DPR_8 Bit set.
2318
  const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
2319
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
2320
  };
2321
2322
  // DQuad_with_qsub_0_in_QPR_VFP2 Register Class...
2323
  const MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = {
2324
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, 
2325
  };
2326
2327
  // DQuad_with_qsub_0_in_QPR_VFP2 Bit set.
2328
  const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = {
2329
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2330
  };
2331
2332
  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2333
  const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2334
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, 
2335
  };
2336
2337
  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2338
  const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2339
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
2340
  };
2341
2342
  // DQuad_with_dsub_1_in_DPR_8 Register Class...
2343
  const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
2344
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, 
2345
  };
2346
2347
  // DQuad_with_dsub_1_in_DPR_8 Bit set.
2348
  const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
2349
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
2350
  };
2351
2352
  // DQuad_with_qsub_1_in_QPR_VFP2 Register Class...
2353
  const MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = {
2354
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, 
2355
  };
2356
2357
  // DQuad_with_qsub_1_in_QPR_VFP2 Bit set.
2358
  const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = {
2359
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
2360
  };
2361
2362
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
2363
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
2364
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, 
2365
  };
2366
2367
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
2368
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
2369
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
2370
  };
2371
2372
  // DQuad_with_dsub_2_in_DPR_8 Register Class...
2373
  const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
2374
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, 
2375
  };
2376
2377
  // DQuad_with_dsub_2_in_DPR_8 Bit set.
2378
  const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
2379
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
2380
  };
2381
2382
  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2383
  const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2384
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, 
2385
  };
2386
2387
  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2388
  const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2389
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
2390
  };
2391
2392
  // DQuad_with_dsub_3_in_DPR_8 Register Class...
2393
  const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
2394
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, 
2395
  };
2396
2397
  // DQuad_with_dsub_3_in_DPR_8 Bit set.
2398
  const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
2399
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
2400
  };
2401
2402
  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2403
  const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2404
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, 
2405
  };
2406
2407
  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2408
  const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2409
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
2410
  };
2411
2412
  // DQuad_with_qsub_0_in_QPR_8 Register Class...
2413
  const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
2414
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 
2415
  };
2416
2417
  // DQuad_with_qsub_0_in_QPR_8 Bit set.
2418
  const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
2419
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
2420
  };
2421
2422
  // DQuad_with_qsub_1_in_QPR_8 Register Class...
2423
  const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
2424
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, 
2425
  };
2426
2427
  // DQuad_with_qsub_1_in_QPR_8 Bit set.
2428
  const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
2429
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 
2430
  };
2431
2432
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
2433
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2434
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, 
2435
  };
2436
2437
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
2438
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
2439
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
2440
  };
2441
2442
  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2443
  const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2444
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, 
2445
  };
2446
2447
  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2448
  const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2449
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
2450
  };
2451
2452
  // QQQQPR Register Class...
2453
  const MCPhysReg QQQQPR[] = {
2454
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, 
2455
  };
2456
2457
  // QQQQPR Bit set.
2458
  const uint8_t QQQQPRBits[] = {
2459
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 
2460
  };
2461
2462
  // QQQQPR_with_ssub_0 Register Class...
2463
  const MCPhysReg QQQQPR_with_ssub_0[] = {
2464
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, 
2465
  };
2466
2467
  // QQQQPR_with_ssub_0 Bit set.
2468
  const uint8_t QQQQPR_with_ssub_0Bits[] = {
2469
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
2470
  };
2471
2472
  // QQQQPR_with_ssub_4 Register Class...
2473
  const MCPhysReg QQQQPR_with_ssub_4[] = {
2474
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, 
2475
  };
2476
2477
  // QQQQPR_with_ssub_4 Bit set.
2478
  const uint8_t QQQQPR_with_ssub_4Bits[] = {
2479
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
2480
  };
2481
2482
  // QQQQPR_with_ssub_8 Register Class...
2483
  const MCPhysReg QQQQPR_with_ssub_8[] = {
2484
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, 
2485
  };
2486
2487
  // QQQQPR_with_ssub_8 Bit set.
2488
  const uint8_t QQQQPR_with_ssub_8Bits[] = {
2489
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 
2490
  };
2491
2492
  // QQQQPR_with_ssub_12 Register Class...
2493
  const MCPhysReg QQQQPR_with_ssub_12[] = {
2494
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, 
2495
  };
2496
2497
  // QQQQPR_with_ssub_12 Bit set.
2498
  const uint8_t QQQQPR_with_ssub_12Bits[] = {
2499
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 
2500
  };
2501
2502
  // QQQQPR_with_dsub_0_in_DPR_8 Register Class...
2503
  const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = {
2504
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, 
2505
  };
2506
2507
  // QQQQPR_with_dsub_0_in_DPR_8 Bit set.
2508
  const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = {
2509
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
2510
  };
2511
2512
  // QQQQPR_with_dsub_2_in_DPR_8 Register Class...
2513
  const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = {
2514
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 
2515
  };
2516
2517
  // QQQQPR_with_dsub_2_in_DPR_8 Bit set.
2518
  const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = {
2519
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
2520
  };
2521
2522
  // QQQQPR_with_dsub_4_in_DPR_8 Register Class...
2523
  const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = {
2524
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, 
2525
  };
2526
2527
  // QQQQPR_with_dsub_4_in_DPR_8 Bit set.
2528
  const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = {
2529
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
2530
  };
2531
2532
  // QQQQPR_with_dsub_6_in_DPR_8 Register Class...
2533
  const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = {
2534
    ARM::Q0_Q1_Q2_Q3, 
2535
  };
2536
2537
  // QQQQPR_with_dsub_6_in_DPR_8 Bit set.
2538
  const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = {
2539
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
2540
  };
2541
2542
} // end anonymous namespace
2543
2544
extern const char ARMRegClassStrings[] = {
2545
  /* 0 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2546
  /* 19 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2547
  /* 40 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2548
  /* 63 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2549
  /* 84 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2550
  /* 102 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2551
  /* 122 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2552
  /* 140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '1', '2', 0,
2553
  /* 160 */ 'D', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2554
  /* 169 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2555
  /* 199 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2556
  /* 231 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2557
  /* 261 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2558
  /* 312 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2559
  /* 365 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2560
  /* 383 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2561
  /* 403 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2562
  /* 421 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2563
  /* 440 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2564
  /* 461 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2565
  /* 484 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2566
  /* 505 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2567
  /* 523 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2568
  /* 543 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', 0,
2569
  /* 561 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2570
  /* 589 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2571
  /* 619 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2572
  /* 651 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2573
  /* 681 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2574
  /* 708 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2575
  /* 737 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2576
  /* 764 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2577
  /* 791 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2578
  /* 820 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2579
  /* 847 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2580
  /* 875 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2581
  /* 905 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2582
  /* 937 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2583
  /* 967 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2584
  /* 994 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2585
  /* 1023 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2586
  /* 1050 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2587
  /* 1078 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2588
  /* 1108 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2589
  /* 1140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '6', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2590
  /* 1168 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2591
  /* 1195 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2592
  /* 1224 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2593
  /* 1251 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2594
  /* 1299 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2595
  /* 1349 */ 'S', 'P', 'R', '_', '8', 0,
2596
  /* 1355 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2597
  /* 1374 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2598
  /* 1395 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2599
  /* 1418 */ 'C', 'C', 'R', 0,
2600
  /* 1422 */ 'D', 'P', 'R', 0,
2601
  /* 1426 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
2602
  /* 1441 */ 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
2603
  /* 1456 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
2604
  /* 1485 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
2605
  /* 1514 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', '_', 'a', 'n', 'd', '_', 'h', 'G', 'P', 'R', 0,
2606
  /* 1531 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', 0,
2607
  /* 1559 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 'r', 'G', 'P', 'R', 0,
2608
  /* 1596 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'r', 'G', 'P', 'R', 0,
2609
  /* 1624 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'G', 'P', 'R', 0,
2610
  /* 1652 */ 'H', 'P', 'R', 0,
2611
  /* 1656 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', 0,
2612
  /* 1663 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2613
  /* 1714 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2614
  /* 1774 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2615
  /* 1842 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2616
  /* 1910 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2617
  /* 1987 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2618
  /* 2064 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2619
  /* 2136 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2620
  /* 2217 */ 'S', 'P', 'R', 0,
2621
  /* 2221 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 0,
2622
  /* 2233 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', 0,
2623
  /* 2242 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', 0,
2624
  /* 2253 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', 0,
2625
  /* 2262 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'w', 'i', 't', 'h', 'p', 'c', 0,
2626
  /* 2282 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', 0,
2627
  /* 2290 */ 'D', 'Q', 'u', 'a', 'd', 0,
2628
  /* 2296 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 0,
2629
  /* 2304 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'G', 'P', 'R', 's', 'p', 0,
2630
  /* 2333 */ 'D', 'P', 'a', 'i', 'r', 0,
2631
  /* 2339 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 0,
2632
};
2633
2634
extern const MCRegisterClass ARMMCRegisterClasses[] = {
2635
  { HPR, HPRBits, 1652, 32, sizeof(HPRBits), ARM::HPRRegClassID, 1, true },
2636
  { SPR, SPRBits, 2217, 32, sizeof(SPRBits), ARM::SPRRegClassID, 1, true },
2637
  { GPR, GPRBits, 1437, 16, sizeof(GPRBits), ARM::GPRRegClassID, 1, true },
2638
  { GPRwithAPSR, GPRwithAPSRBits, 2221, 16, sizeof(GPRwithAPSRBits), ARM::GPRwithAPSRRegClassID, 1, true },
2639
  { SPR_8, SPR_8Bits, 1349, 16, sizeof(SPR_8Bits), ARM::SPR_8RegClassID, 1, true },
2640
  { GPRnopc, GPRnopcBits, 2282, 15, sizeof(GPRnopcBits), ARM::GPRnopcRegClassID, 1, true },
2641
  { rGPR, rGPRBits, 1591, 14, sizeof(rGPRBits), ARM::rGPRRegClassID, 1, true },
2642
  { tGPRwithpc, tGPRwithpcBits, 2271, 9, sizeof(tGPRwithpcBits), ARM::tGPRwithpcRegClassID, 1, true },
2643
  { hGPR, hGPRBits, 1526, 8, sizeof(hGPRBits), ARM::hGPRRegClassID, 1, true },
2644
  { tGPR, tGPRBits, 1647, 8, sizeof(tGPRBits), ARM::tGPRRegClassID, 1, true },
2645
  { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 1514, 7, sizeof(GPRnopc_and_hGPRBits), ARM::GPRnopc_and_hGPRRegClassID, 1, true },
2646
  { hGPR_and_rGPR, hGPR_and_rGPRBits, 1582, 6, sizeof(hGPR_and_rGPRBits), ARM::hGPR_and_rGPRRegClassID, 1, true },
2647
  { tcGPR, tcGPRBits, 1435, 5, sizeof(tcGPRBits), ARM::tcGPRRegClassID, 1, true },
2648
  { tGPR_and_tcGPR, tGPR_and_tcGPRBits, 1441, 4, sizeof(tGPR_and_tcGPRBits), ARM::tGPR_and_tcGPRRegClassID, 1, true },
2649
  { CCR, CCRBits, 1418, 1, sizeof(CCRBits), ARM::CCRRegClassID, -1, false },
2650
  { GPRsp, GPRspBits, 2327, 1, sizeof(GPRspBits), ARM::GPRspRegClassID, 1, true },
2651
  { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, 2262, 1, sizeof(hGPR_and_tGPRwithpcBits), ARM::hGPR_and_tGPRwithpcRegClassID, 1, true },
2652
  { hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1426, 1, sizeof(hGPR_and_tcGPRBits), ARM::hGPR_and_tcGPRRegClassID, 1, true },
2653
  { DPR, DPRBits, 1422, 32, sizeof(DPRBits), ARM::DPRRegClassID, 1, true },
2654
  { DPR_VFP2, DPR_VFP2Bits, 160, 16, sizeof(DPR_VFP2Bits), ARM::DPR_VFP2RegClassID, 1, true },
2655
  { DPR_8, DPR_8Bits, 583, 8, sizeof(DPR_8Bits), ARM::DPR_8RegClassID, 1, true },
2656
  { GPRPair, GPRPairBits, 2339, 7, sizeof(GPRPairBits), ARM::GPRPairRegClassID, 1, true },
2657
  { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, 1596, 6, sizeof(GPRPair_with_gsub_1_in_rGPRBits), ARM::GPRPair_with_gsub_1_in_rGPRRegClassID, 1, true },
2658
  { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 1624, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, 1, true },
2659
  { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 1531, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, 1, true },
2660
  { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 1456, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID, 1, true },
2661
  { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, 1559, 2, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits), ARM::GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID, 1, true },
2662
  { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 1485, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM::GPRPair_with_gsub_1_in_tcGPRRegClassID, 1, true },
2663
  { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 2304, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM::GPRPair_with_gsub_1_in_GPRspRegClassID, 1, true },
2664
  { DPairSpc, DPairSpcBits, 2253, 30, sizeof(DPairSpcBits), ARM::DPairSpcRegClassID, 1, true },
2665
  { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 63, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM::DPairSpc_with_ssub_0RegClassID, 1, true },
2666
  { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, 484, 14, sizeof(DPairSpc_with_ssub_4Bits), ARM::DPairSpc_with_ssub_4RegClassID, 1, true },
2667
  { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 651, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID, 1, true },
2668
  { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 937, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID, 1, true },
2669
  { DPair, DPairBits, 2333, 31, sizeof(DPairBits), ARM::DPairRegClassID, 1, true },
2670
  { DPair_with_ssub_0, DPair_with_ssub_0Bits, 122, 16, sizeof(DPair_with_ssub_0Bits), ARM::DPair_with_ssub_0RegClassID, 1, true },
2671
  { QPR, QPRBits, 1659, 16, sizeof(QPRBits), ARM::QPRRegClassID, 1, true },
2672
  { DPair_with_ssub_2, DPair_with_ssub_2Bits, 403, 15, sizeof(DPair_with_ssub_2Bits), ARM::DPair_with_ssub_2RegClassID, 1, true },
2673
  { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 737, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM::DPair_with_dsub_0_in_DPR_8RegClassID, 1, true },
2674
  { QPR_VFP2, QPR_VFP2Bits, 190, 8, sizeof(QPR_VFP2Bits), ARM::QPR_VFP2RegClassID, 1, true },
2675
  { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 820, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM::DPair_with_dsub_1_in_DPR_8RegClassID, 1, true },
2676
  { QPR_8, QPR_8Bits, 1189, 4, sizeof(QPR_8Bits), ARM::QPR_8RegClassID, 1, true },
2677
  { DTriple, DTripleBits, 2296, 30, sizeof(DTripleBits), ARM::DTripleRegClassID, 1, true },
2678
  { DTripleSpc, DTripleSpcBits, 2242, 28, sizeof(DTripleSpcBits), ARM::DTripleSpcRegClassID, 1, true },
2679
  { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 40, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM::DTripleSpc_with_ssub_0RegClassID, 1, true },
2680
  { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 102, 16, sizeof(DTriple_with_ssub_0Bits), ARM::DTriple_with_ssub_0RegClassID, 1, true },
2681
  { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 1687, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_qsub_0_in_QPRRegClassID, 1, true },
2682
  { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 383, 15, sizeof(DTriple_with_ssub_2Bits), ARM::DTriple_with_ssub_2RegClassID, 1, true },
2683
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2088, 15, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2684
  { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, 461, 14, sizeof(DTripleSpc_with_ssub_4Bits), ARM::DTripleSpc_with_ssub_4RegClassID, 1, true },
2685
  { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, 523, 14, sizeof(DTriple_with_ssub_4Bits), ARM::DTriple_with_ssub_4RegClassID, 1, true },
2686
  { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, 1395, 12, sizeof(DTripleSpc_with_ssub_8Bits), ARM::DTripleSpc_with_ssub_8RegClassID, 1, true },
2687
  { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 619, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 1, true },
2688
  { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 708, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, 1, true },
2689
  { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, 199, 8, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits), ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClassID, 1, true },
2690
  { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2064, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2691
  { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 791, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, 1, true },
2692
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 312, 7, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 1, true },
2693
  { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits, 1663, 7, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID, 1, true },
2694
  { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 905, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 1, true },
2695
  { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 994, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, 1, true },
2696
  { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 1108, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 1, true },
2697
  { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2136, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2698
  { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 1195, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM::DTriple_with_qsub_0_in_QPR_8RegClassID, 1, true },
2699
  { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, 1714, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID, 1, true },
2700
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1299, 3, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 1, true },
2701
  { DQuadSpc, DQuadSpcBits, 2233, 28, sizeof(DQuadSpcBits), ARM::DQuadSpcRegClassID, 1, true },
2702
  { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 19, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM::DQuadSpc_with_ssub_0RegClassID, 1, true },
2703
  { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, 440, 14, sizeof(DQuadSpc_with_ssub_4Bits), ARM::DQuadSpc_with_ssub_4RegClassID, 1, true },
2704
  { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, 1374, 12, sizeof(DQuadSpc_with_ssub_8Bits), ARM::DQuadSpc_with_ssub_8RegClassID, 1, true },
2705
  { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 589, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 1, true },
2706
  { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 875, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 1, true },
2707
  { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 1078, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 1, true },
2708
  { DQuad, DQuadBits, 2290, 29, sizeof(DQuadBits), ARM::DQuadRegClassID, 1, true },
2709
  { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 84, 16, sizeof(DQuad_with_ssub_0Bits), ARM::DQuad_with_ssub_0RegClassID, 1, true },
2710
  { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 365, 15, sizeof(DQuad_with_ssub_2Bits), ARM::DQuad_with_ssub_2RegClassID, 1, true },
2711
  { QQPR, QQPRBits, 1658, 15, sizeof(QQPRBits), ARM::QQPRRegClassID, 1, true },
2712
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1796, 14, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2713
  { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, 505, 14, sizeof(DQuad_with_ssub_4Bits), ARM::DQuad_with_ssub_4RegClassID, 1, true },
2714
  { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, 543, 13, sizeof(DQuad_with_ssub_6Bits), ARM::DQuad_with_ssub_6RegClassID, 1, true },
2715
  { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 681, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, 1, true },
2716
  { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, 169, 8, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClassID, 1, true },
2717
  { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1774, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2718
  { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 764, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, 1, true },
2719
  { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, 231, 7, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID, 1, true },
2720
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 261, 7, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 1, true },
2721
  { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 967, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, 1, true },
2722
  { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1842, 6, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2723
  { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 1023, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, 1, true },
2724
  { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1910, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2725
  { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 1168, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM::DQuad_with_qsub_0_in_QPR_8RegClassID, 1, true },
2726
  { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 1224, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM::DQuad_with_qsub_1_in_QPR_8RegClassID, 1, true },
2727
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1251, 3, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 1, true },
2728
  { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1987, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2729
  { QQQQPR, QQQQPRBits, 1656, 13, sizeof(QQQQPRBits), ARM::QQQQPRRegClassID, 1, true },
2730
  { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 0, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM::QQQQPR_with_ssub_0RegClassID, 1, true },
2731
  { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, 421, 7, sizeof(QQQQPR_with_ssub_4Bits), ARM::QQQQPR_with_ssub_4RegClassID, 1, true },
2732
  { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, 1355, 6, sizeof(QQQQPR_with_ssub_8Bits), ARM::QQQQPR_with_ssub_8RegClassID, 1, true },
2733
  { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, 140, 5, sizeof(QQQQPR_with_ssub_12Bits), ARM::QQQQPR_with_ssub_12RegClassID, 1, true },
2734
  { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 561, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID, 1, true },
2735
  { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 847, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID, 1, true },
2736
  { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 1050, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID, 1, true },
2737
  { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 1140, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID, 1, true },
2738
};
2739
2740
// ARM Dwarf<->LLVM register mappings.
2741
extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
2742
  { 0U, ARM::R0 },
2743
  { 1U, ARM::R1 },
2744
  { 2U, ARM::R2 },
2745
  { 3U, ARM::R3 },
2746
  { 4U, ARM::R4 },
2747
  { 5U, ARM::R5 },
2748
  { 6U, ARM::R6 },
2749
  { 7U, ARM::R7 },
2750
  { 8U, ARM::R8 },
2751
  { 9U, ARM::R9 },
2752
  { 10U, ARM::R10 },
2753
  { 11U, ARM::R11 },
2754
  { 12U, ARM::R12 },
2755
  { 13U, ARM::SP },
2756
  { 14U, ARM::LR },
2757
  { 15U, ARM::PC },
2758
  { 256U, ARM::D0 },
2759
  { 257U, ARM::D1 },
2760
  { 258U, ARM::D2 },
2761
  { 259U, ARM::D3 },
2762
  { 260U, ARM::D4 },
2763
  { 261U, ARM::D5 },
2764
  { 262U, ARM::D6 },
2765
  { 263U, ARM::D7 },
2766
  { 264U, ARM::D8 },
2767
  { 265U, ARM::D9 },
2768
  { 266U, ARM::D10 },
2769
  { 267U, ARM::D11 },
2770
  { 268U, ARM::D12 },
2771
  { 269U, ARM::D13 },
2772
  { 270U, ARM::D14 },
2773
  { 271U, ARM::D15 },
2774
  { 272U, ARM::D16 },
2775
  { 273U, ARM::D17 },
2776
  { 274U, ARM::D18 },
2777
  { 275U, ARM::D19 },
2778
  { 276U, ARM::D20 },
2779
  { 277U, ARM::D21 },
2780
  { 278U, ARM::D22 },
2781
  { 279U, ARM::D23 },
2782
  { 280U, ARM::D24 },
2783
  { 281U, ARM::D25 },
2784
  { 282U, ARM::D26 },
2785
  { 283U, ARM::D27 },
2786
  { 284U, ARM::D28 },
2787
  { 285U, ARM::D29 },
2788
  { 286U, ARM::D30 },
2789
  { 287U, ARM::D31 },
2790
};
2791
extern const unsigned ARMDwarfFlavour0Dwarf2LSize = array_lengthof(ARMDwarfFlavour0Dwarf2L);
2792
2793
extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
2794
  { 0U, ARM::R0 },
2795
  { 1U, ARM::R1 },
2796
  { 2U, ARM::R2 },
2797
  { 3U, ARM::R3 },
2798
  { 4U, ARM::R4 },
2799
  { 5U, ARM::R5 },
2800
  { 6U, ARM::R6 },
2801
  { 7U, ARM::R7 },
2802
  { 8U, ARM::R8 },
2803
  { 9U, ARM::R9 },
2804
  { 10U, ARM::R10 },
2805
  { 11U, ARM::R11 },
2806
  { 12U, ARM::R12 },
2807
  { 13U, ARM::SP },
2808
  { 14U, ARM::LR },
2809
  { 15U, ARM::PC },
2810
  { 256U, ARM::D0 },
2811
  { 257U, ARM::D1 },
2812
  { 258U, ARM::D2 },
2813
  { 259U, ARM::D3 },
2814
  { 260U, ARM::D4 },
2815
  { 261U, ARM::D5 },
2816
  { 262U, ARM::D6 },
2817
  { 263U, ARM::D7 },
2818
  { 264U, ARM::D8 },
2819
  { 265U, ARM::D9 },
2820
  { 266U, ARM::D10 },
2821
  { 267U, ARM::D11 },
2822
  { 268U, ARM::D12 },
2823
  { 269U, ARM::D13 },
2824
  { 270U, ARM::D14 },
2825
  { 271U, ARM::D15 },
2826
  { 272U, ARM::D16 },
2827
  { 273U, ARM::D17 },
2828
  { 274U, ARM::D18 },
2829
  { 275U, ARM::D19 },
2830
  { 276U, ARM::D20 },
2831
  { 277U, ARM::D21 },
2832
  { 278U, ARM::D22 },
2833
  { 279U, ARM::D23 },
2834
  { 280U, ARM::D24 },
2835
  { 281U, ARM::D25 },
2836
  { 282U, ARM::D26 },
2837
  { 283U, ARM::D27 },
2838
  { 284U, ARM::D28 },
2839
  { 285U, ARM::D29 },
2840
  { 286U, ARM::D30 },
2841
  { 287U, ARM::D31 },
2842
};
2843
extern const unsigned ARMEHFlavour0Dwarf2LSize = array_lengthof(ARMEHFlavour0Dwarf2L);
2844
2845
extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
2846
  { ARM::LR, 14U },
2847
  { ARM::PC, 15U },
2848
  { ARM::SP, 13U },
2849
  { ARM::D0, 256U },
2850
  { ARM::D1, 257U },
2851
  { ARM::D2, 258U },
2852
  { ARM::D3, 259U },
2853
  { ARM::D4, 260U },
2854
  { ARM::D5, 261U },
2855
  { ARM::D6, 262U },
2856
  { ARM::D7, 263U },
2857
  { ARM::D8, 264U },
2858
  { ARM::D9, 265U },
2859
  { ARM::D10, 266U },
2860
  { ARM::D11, 267U },
2861
  { ARM::D12, 268U },
2862
  { ARM::D13, 269U },
2863
  { ARM::D14, 270U },
2864
  { ARM::D15, 271U },
2865
  { ARM::D16, 272U },
2866
  { ARM::D17, 273U },
2867
  { ARM::D18, 274U },
2868
  { ARM::D19, 275U },
2869
  { ARM::D20, 276U },
2870
  { ARM::D21, 277U },
2871
  { ARM::D22, 278U },
2872
  { ARM::D23, 279U },
2873
  { ARM::D24, 280U },
2874
  { ARM::D25, 281U },
2875
  { ARM::D26, 282U },
2876
  { ARM::D27, 283U },
2877
  { ARM::D28, 284U },
2878
  { ARM::D29, 285U },
2879
  { ARM::D30, 286U },
2880
  { ARM::D31, 287U },
2881
  { ARM::R0, 0U },
2882
  { ARM::R1, 1U },
2883
  { ARM::R2, 2U },
2884
  { ARM::R3, 3U },
2885
  { ARM::R4, 4U },
2886
  { ARM::R5, 5U },
2887
  { ARM::R6, 6U },
2888
  { ARM::R7, 7U },
2889
  { ARM::R8, 8U },
2890
  { ARM::R9, 9U },
2891
  { ARM::R10, 10U },
2892
  { ARM::R11, 11U },
2893
  { ARM::R12, 12U },
2894
};
2895
extern const unsigned ARMDwarfFlavour0L2DwarfSize = array_lengthof(ARMDwarfFlavour0L2Dwarf);
2896
2897
extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
2898
  { ARM::LR, 14U },
2899
  { ARM::PC, 15U },
2900
  { ARM::SP, 13U },
2901
  { ARM::D0, 256U },
2902
  { ARM::D1, 257U },
2903
  { ARM::D2, 258U },
2904
  { ARM::D3, 259U },
2905
  { ARM::D4, 260U },
2906
  { ARM::D5, 261U },
2907
  { ARM::D6, 262U },
2908
  { ARM::D7, 263U },
2909
  { ARM::D8, 264U },
2910
  { ARM::D9, 265U },
2911
  { ARM::D10, 266U },
2912
  { ARM::D11, 267U },
2913
  { ARM::D12, 268U },
2914
  { ARM::D13, 269U },
2915
  { ARM::D14, 270U },
2916
  { ARM::D15, 271U },
2917
  { ARM::D16, 272U },
2918
  { ARM::D17, 273U },
2919
  { ARM::D18, 274U },
2920
  { ARM::D19, 275U },
2921
  { ARM::D20, 276U },
2922
  { ARM::D21, 277U },
2923
  { ARM::D22, 278U },
2924
  { ARM::D23, 279U },
2925
  { ARM::D24, 280U },
2926
  { ARM::D25, 281U },
2927
  { ARM::D26, 282U },
2928
  { ARM::D27, 283U },
2929
  { ARM::D28, 284U },
2930
  { ARM::D29, 285U },
2931
  { ARM::D30, 286U },
2932
  { ARM::D31, 287U },
2933
  { ARM::R0, 0U },
2934
  { ARM::R1, 1U },
2935
  { ARM::R2, 2U },
2936
  { ARM::R3, 3U },
2937
  { ARM::R4, 4U },
2938
  { ARM::R5, 5U },
2939
  { ARM::R6, 6U },
2940
  { ARM::R7, 7U },
2941
  { ARM::R8, 8U },
2942
  { ARM::R9, 9U },
2943
  { ARM::R10, 10U },
2944
  { ARM::R11, 11U },
2945
  { ARM::R12, 12U },
2946
};
2947
extern const unsigned ARMEHFlavour0L2DwarfSize = array_lengthof(ARMEHFlavour0L2Dwarf);
2948
2949
extern const uint16_t ARMRegEncodingTable[] = {
2950
  0,
2951
  1,
2952
  15,
2953
  0,
2954
  8,
2955
  9,
2956
  3,
2957
  3,
2958
  0,
2959
  4,
2960
  14,
2961
  15,
2962
  13,
2963
  2,
2964
  0,
2965
  1,
2966
  2,
2967
  3,
2968
  4,
2969
  5,
2970
  6,
2971
  7,
2972
  8,
2973
  9,
2974
  10,
2975
  11,
2976
  12,
2977
  13,
2978
  14,
2979
  15,
2980
  16,
2981
  17,
2982
  18,
2983
  19,
2984
  20,
2985
  21,
2986
  22,
2987
  23,
2988
  24,
2989
  25,
2990
  26,
2991
  27,
2992
  28,
2993
  29,
2994
  30,
2995
  31,
2996
  10,
2997
  7,
2998
  6,
2999
  5,
3000
  0,
3001
  1,
3002
  2,
3003
  3,
3004
  4,
3005
  5,
3006
  6,
3007
  7,
3008
  8,
3009
  9,
3010
  10,
3011
  11,
3012
  12,
3013
  13,
3014
  14,
3015
  15,
3016
  0,
3017
  1,
3018
  2,
3019
  3,
3020
  4,
3021
  5,
3022
  6,
3023
  7,
3024
  8,
3025
  9,
3026
  10,
3027
  11,
3028
  12,
3029
  0,
3030
  1,
3031
  2,
3032
  3,
3033
  4,
3034
  5,
3035
  6,
3036
  7,
3037
  8,
3038
  9,
3039
  10,
3040
  11,
3041
  12,
3042
  13,
3043
  14,
3044
  15,
3045
  16,
3046
  17,
3047
  18,
3048
  19,
3049
  20,
3050
  21,
3051
  22,
3052
  23,
3053
  24,
3054
  25,
3055
  26,
3056
  27,
3057
  28,
3058
  29,
3059
  30,
3060
  31,
3061
  0,
3062
  1,
3063
  2,
3064
  3,
3065
  4,
3066
  5,
3067
  6,
3068
  7,
3069
  8,
3070
  9,
3071
  10,
3072
  11,
3073
  12,
3074
  13,
3075
  14,
3076
  15,
3077
  16,
3078
  17,
3079
  18,
3080
  19,
3081
  20,
3082
  21,
3083
  22,
3084
  23,
3085
  24,
3086
  25,
3087
  26,
3088
  27,
3089
  28,
3090
  29,
3091
  0,
3092
  1,
3093
  2,
3094
  3,
3095
  4,
3096
  5,
3097
  6,
3098
  7,
3099
  8,
3100
  9,
3101
  10,
3102
  11,
3103
  12,
3104
  13,
3105
  14,
3106
  0,
3107
  1,
3108
  2,
3109
  3,
3110
  4,
3111
  5,
3112
  6,
3113
  7,
3114
  8,
3115
  9,
3116
  10,
3117
  11,
3118
  12,
3119
  12,
3120
  0,
3121
  2,
3122
  4,
3123
  6,
3124
  8,
3125
  10,
3126
  0,
3127
  1,
3128
  2,
3129
  3,
3130
  4,
3131
  5,
3132
  6,
3133
  7,
3134
  8,
3135
  9,
3136
  10,
3137
  11,
3138
  12,
3139
  13,
3140
  14,
3141
  15,
3142
  16,
3143
  17,
3144
  18,
3145
  19,
3146
  20,
3147
  21,
3148
  22,
3149
  23,
3150
  24,
3151
  25,
3152
  26,
3153
  27,
3154
  28,
3155
  29,
3156
  0,
3157
  1,
3158
  2,
3159
  3,
3160
  4,
3161
  5,
3162
  6,
3163
  7,
3164
  8,
3165
  9,
3166
  10,
3167
  11,
3168
  12,
3169
  13,
3170
  14,
3171
  15,
3172
  16,
3173
  17,
3174
  18,
3175
  19,
3176
  20,
3177
  21,
3178
  22,
3179
  23,
3180
  24,
3181
  25,
3182
  26,
3183
  27,
3184
  0,
3185
  1,
3186
  2,
3187
  3,
3188
  4,
3189
  5,
3190
  6,
3191
  7,
3192
  8,
3193
  9,
3194
  10,
3195
  11,
3196
  12,
3197
  13,
3198
  14,
3199
  15,
3200
  16,
3201
  17,
3202
  18,
3203
  19,
3204
  20,
3205
  21,
3206
  22,
3207
  23,
3208
  24,
3209
  25,
3210
  1,
3211
  3,
3212
  5,
3213
  7,
3214
  9,
3215
  11,
3216
  13,
3217
  15,
3218
  17,
3219
  19,
3220
  21,
3221
  23,
3222
  25,
3223
  27,
3224
  29,
3225
  1,
3226
  3,
3227
  5,
3228
  7,
3229
  9,
3230
  11,
3231
  13,
3232
  15,
3233
  17,
3234
  19,
3235
  21,
3236
  23,
3237
  25,
3238
  27,
3239
};
3240
7.99k
static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3241
7.99k
  RI->InitMCRegisterInfo(ARMRegDesc, 289, RA, PC, ARMMCRegisterClasses, 103, ARMRegUnitRoots, 77, ARMRegDiffLists, ARMLaneMaskLists, ARMRegStrings, ARMRegClassStrings, ARMSubRegIdxLists, 57,
3242
7.99k
ARMSubRegIdxRanges, ARMRegEncodingTable);
3243
7.99k
3244
7.99k
  switch (DwarfFlavour) {
3245
7.99k
  default:
3246
0
    llvm_unreachable("Unknown DWARF flavour");
3247
7.99k
  case 0:
3248
7.99k
    RI->mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
3249
7.99k
    break;
3250
7.99k
  }
3251
7.99k
  switch (EHFlavour) {
3252
7.99k
  default:
3253
0
    llvm_unreachable("Unknown DWARF flavour");
3254
7.99k
  case 0:
3255
7.99k
    RI->mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
3256
7.99k
    break;
3257
7.99k
  }
3258
7.99k
  switch (DwarfFlavour) {
3259
7.99k
  default:
3260
0
    llvm_unreachable("Unknown DWARF flavour");
3261
7.99k
  case 0:
3262
7.99k
    RI->mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false);
3263
7.99k
    break;
3264
7.99k
  }
3265
7.99k
  switch (EHFlavour) {
3266
7.99k
  default:
3267
0
    llvm_unreachable("Unknown DWARF flavour");
3268
7.99k
  case 0:
3269
7.99k
    RI->mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true);
3270
7.99k
    break;
3271
7.99k
  }
3272
7.99k
}
3273
3274
} // end namespace llvm
3275
3276
#endif // GET_REGINFO_MC_DESC
3277
3278
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3279
|*                                                                            *|
3280
|* Register Information Header Fragment                                       *|
3281
|*                                                                            *|
3282
|* Automatically generated file, do not edit!                                 *|
3283
|*                                                                            *|
3284
\*===----------------------------------------------------------------------===*/
3285
3286
3287
#ifdef GET_REGINFO_HEADER
3288
#undef GET_REGINFO_HEADER
3289
3290
#include "llvm/CodeGen/TargetRegisterInfo.h"
3291
3292
namespace llvm {
3293
3294
class ARMFrameLowering;
3295
3296
struct ARMGenRegisterInfo : public TargetRegisterInfo {
3297
  explicit ARMGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3298
      unsigned PC = 0, unsigned HwMode = 0);
3299
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3300
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3301
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3302
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3303
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3304
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
3305
  unsigned getNumRegPressureSets() const override;
3306
  const char *getRegPressureSetName(unsigned Idx) const override;
3307
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3308
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3309
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3310
  ArrayRef<const char *> getRegMaskNames() const override;
3311
  ArrayRef<const uint32_t *> getRegMasks() const override;
3312
  /// Devirtualized TargetFrameLowering.
3313
  static const ARMFrameLowering *getFrameLowering(
3314
      const MachineFunction &MF);
3315
};
3316
3317
namespace ARM { // Register classes
3318
  extern const TargetRegisterClass HPRRegClass;
3319
  extern const TargetRegisterClass SPRRegClass;
3320
  extern const TargetRegisterClass GPRRegClass;
3321
  extern const TargetRegisterClass GPRwithAPSRRegClass;
3322
  extern const TargetRegisterClass SPR_8RegClass;
3323
  extern const TargetRegisterClass GPRnopcRegClass;
3324
  extern const TargetRegisterClass rGPRRegClass;
3325
  extern const TargetRegisterClass tGPRwithpcRegClass;
3326
  extern const TargetRegisterClass hGPRRegClass;
3327
  extern const TargetRegisterClass tGPRRegClass;
3328
  extern const TargetRegisterClass GPRnopc_and_hGPRRegClass;
3329
  extern const TargetRegisterClass hGPR_and_rGPRRegClass;
3330
  extern const TargetRegisterClass tcGPRRegClass;
3331
  extern const TargetRegisterClass tGPR_and_tcGPRRegClass;
3332
  extern const TargetRegisterClass CCRRegClass;
3333
  extern const TargetRegisterClass GPRspRegClass;
3334
  extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass;
3335
  extern const TargetRegisterClass hGPR_and_tcGPRRegClass;
3336
  extern const TargetRegisterClass DPRRegClass;
3337
  extern const TargetRegisterClass DPR_VFP2RegClass;
3338
  extern const TargetRegisterClass DPR_8RegClass;
3339
  extern const TargetRegisterClass GPRPairRegClass;
3340
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_rGPRRegClass;
3341
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass;
3342
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass;
3343
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass;
3344
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass;
3345
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass;
3346
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass;
3347
  extern const TargetRegisterClass DPairSpcRegClass;
3348
  extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass;
3349
  extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass;
3350
  extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass;
3351
  extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass;
3352
  extern const TargetRegisterClass DPairRegClass;
3353
  extern const TargetRegisterClass DPair_with_ssub_0RegClass;
3354
  extern const TargetRegisterClass QPRRegClass;
3355
  extern const TargetRegisterClass DPair_with_ssub_2RegClass;
3356
  extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass;
3357
  extern const TargetRegisterClass QPR_VFP2RegClass;
3358
  extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass;
3359
  extern const TargetRegisterClass QPR_8RegClass;
3360
  extern const TargetRegisterClass DTripleRegClass;
3361
  extern const TargetRegisterClass DTripleSpcRegClass;
3362
  extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass;
3363
  extern const TargetRegisterClass DTriple_with_ssub_0RegClass;
3364
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass;
3365
  extern const TargetRegisterClass DTriple_with_ssub_2RegClass;
3366
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3367
  extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass;
3368
  extern const TargetRegisterClass DTriple_with_ssub_4RegClass;
3369
  extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass;
3370
  extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass;
3371
  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass;
3372
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_VFP2RegClass;
3373
  extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3374
  extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass;
3375
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
3376
  extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass;
3377
  extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass;
3378
  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass;
3379
  extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass;
3380
  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3381
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass;
3382
  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass;
3383
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
3384
  extern const TargetRegisterClass DQuadSpcRegClass;
3385
  extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass;
3386
  extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass;
3387
  extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass;
3388
  extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass;
3389
  extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass;
3390
  extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass;
3391
  extern const TargetRegisterClass DQuadRegClass;
3392
  extern const TargetRegisterClass DQuad_with_ssub_0RegClass;
3393
  extern const TargetRegisterClass DQuad_with_ssub_2RegClass;
3394
  extern const TargetRegisterClass QQPRRegClass;
3395
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3396
  extern const TargetRegisterClass DQuad_with_ssub_4RegClass;
3397
  extern const TargetRegisterClass DQuad_with_ssub_6RegClass;
3398
  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass;
3399
  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_VFP2RegClass;
3400
  extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3401
  extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass;
3402
  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_VFP2RegClass;
3403
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
3404
  extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass;
3405
  extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3406
  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass;
3407
  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3408
  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass;
3409
  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass;
3410
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
3411
  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3412
  extern const TargetRegisterClass QQQQPRRegClass;
3413
  extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass;
3414
  extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass;
3415
  extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass;
3416
  extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass;
3417
  extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass;
3418
  extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass;
3419
  extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass;
3420
  extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass;
3421
} // end namespace ARM
3422
3423
} // end namespace llvm
3424
3425
#endif // GET_REGINFO_HEADER
3426
3427
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3428
|*                                                                            *|
3429
|* Target Register and Register Classes Information                           *|
3430
|*                                                                            *|
3431
|* Automatically generated file, do not edit!                                 *|
3432
|*                                                                            *|
3433
\*===----------------------------------------------------------------------===*/
3434
3435
3436
#ifdef GET_REGINFO_TARGET_DESC
3437
#undef GET_REGINFO_TARGET_DESC
3438
3439
namespace llvm {
3440
3441
extern const MCRegisterClass ARMMCRegisterClasses[];
3442
3443
static const MVT::SimpleValueType VTLists[] = {
3444
  /* 0 */ MVT::i32, MVT::Other,
3445
  /* 2 */ MVT::f16, MVT::Other,
3446
  /* 4 */ MVT::f32, MVT::Other,
3447
  /* 6 */ MVT::v2i64, MVT::Other,
3448
  /* 8 */ MVT::v4i64, MVT::Other,
3449
  /* 10 */ MVT::v8i64, MVT::Other,
3450
  /* 12 */ MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::v4f16, MVT::Other,
3451
  /* 20 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
3452
  /* 28 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other,
3453
  /* 35 */ MVT::Untyped, MVT::Other,
3454
};
3455
3456
static const char *const SubRegIndexNameTable[] = { "dsub_0", "dsub_1", "dsub_2", "dsub_3", "dsub_4", "dsub_5", "dsub_6", "dsub_7", "gsub_0", "gsub_1", "qqsub_0", "qqsub_1", "qsub_0", "qsub_1", "qsub_2", "qsub_3", "ssub_0", "ssub_1", "ssub_2", "ssub_3", "ssub_4", "ssub_5", "ssub_6", "ssub_7", "ssub_8", "ssub_9", "ssub_10", "ssub_11", "ssub_12", "ssub_13", "dsub_7_then_ssub_0", "dsub_7_then_ssub_1", "ssub_0_ssub_1_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5", "ssub_2_ssub_3_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_6_ssub_7_dsub_5", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5", "ssub_6_ssub_7_dsub_5_dsub_7", "ssub_6_ssub_7_ssub_8_ssub_9", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "ssub_8_ssub_9_ssub_12_ssub_13", "ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "dsub_5_dsub_7", "dsub_5_ssub_12_ssub_13_dsub_7", "dsub_5_ssub_12_ssub_13", "ssub_4_ssub_5_ssub_6_ssub_7_qsub_2", "" };
3457
3458
3459
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3460
  LaneBitmask::getAll(),
3461
  LaneBitmask(0x0000000C), // dsub_0
3462
  LaneBitmask(0x00000030), // dsub_1
3463
  LaneBitmask(0x000000C0), // dsub_2
3464
  LaneBitmask(0x00000300), // dsub_3
3465
  LaneBitmask(0x00000C00), // dsub_4
3466
  LaneBitmask(0x00003000), // dsub_5
3467
  LaneBitmask(0x0000C000), // dsub_6
3468
  LaneBitmask(0x00030000), // dsub_7
3469
  LaneBitmask(0x00000001), // gsub_0
3470
  LaneBitmask(0x00000002), // gsub_1
3471
  LaneBitmask(0x000003FC), // qqsub_0
3472
  LaneBitmask(0x0003FC00), // qqsub_1
3473
  LaneBitmask(0x0000003C), // qsub_0
3474
  LaneBitmask(0x000003C0), // qsub_1
3475
  LaneBitmask(0x00003C00), // qsub_2
3476
  LaneBitmask(0x0003C000), // qsub_3
3477
  LaneBitmask(0x00000004), // ssub_0
3478
  LaneBitmask(0x00000008), // ssub_1
3479
  LaneBitmask(0x00000010), // ssub_2
3480
  LaneBitmask(0x00000020), // ssub_3
3481
  LaneBitmask(0x00000040), // ssub_4
3482
  LaneBitmask(0x00000080), // ssub_5
3483
  LaneBitmask(0x00000100), // ssub_6
3484
  LaneBitmask(0x00000200), // ssub_7
3485
  LaneBitmask(0x00000400), // ssub_8
3486
  LaneBitmask(0x00000800), // ssub_9
3487
  LaneBitmask(0x00001000), // ssub_10
3488
  LaneBitmask(0x00002000), // ssub_11
3489
  LaneBitmask(0x00004000), // ssub_12
3490
  LaneBitmask(0x00008000), // ssub_13
3491
  LaneBitmask(0x00010000), // dsub_7_then_ssub_0
3492
  LaneBitmask(0x00020000), // dsub_7_then_ssub_1
3493
  LaneBitmask(0x000000CC), // ssub_0_ssub_1_ssub_4_ssub_5
3494
  LaneBitmask(0x000000FC), // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3495
  LaneBitmask(0x00000330), // ssub_2_ssub_3_ssub_6_ssub_7
3496
  LaneBitmask(0x000003F0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3497
  LaneBitmask(0x000000F0), // ssub_2_ssub_3_ssub_4_ssub_5
3498
  LaneBitmask(0x00000CCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
3499
  LaneBitmask(0x0000CCCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3500
  LaneBitmask(0x00003330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
3501
  LaneBitmask(0x00033330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
3502
  LaneBitmask(0x00000FF0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3503
  LaneBitmask(0x00000CC0), // ssub_4_ssub_5_ssub_8_ssub_9
3504
  LaneBitmask(0x00000FC0), // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3505
  LaneBitmask(0x0000CCC0), // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3506
  LaneBitmask(0x00003300), // ssub_6_ssub_7_dsub_5
3507
  LaneBitmask(0x00003F00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
3508
  LaneBitmask(0x00033300), // ssub_6_ssub_7_dsub_5_dsub_7
3509
  LaneBitmask(0x00000F00), // ssub_6_ssub_7_ssub_8_ssub_9
3510
  LaneBitmask(0x0000FF00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3511
  LaneBitmask(0x0000CC00), // ssub_8_ssub_9_ssub_12_ssub_13
3512
  LaneBitmask(0x0000FC00), // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3513
  LaneBitmask(0x00033000), // dsub_5_dsub_7
3514
  LaneBitmask(0x0003F000), // dsub_5_ssub_12_ssub_13_dsub_7
3515
  LaneBitmask(0x0000F000), // dsub_5_ssub_12_ssub_13
3516
  LaneBitmask(0x00003FC0), // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
3517
 };
3518
3519
3520
3521
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3522
  // Mode = 0 (Default)
3523
  { 16, 16, 32, VTLists+2 },    // HPR
3524
  { 32, 32, 32, VTLists+4 },    // SPR
3525
  { 32, 32, 32, VTLists+0 },    // GPR
3526
  { 32, 32, 32, VTLists+0 },    // GPRwithAPSR
3527
  { 32, 32, 32, VTLists+4 },    // SPR_8
3528
  { 32, 32, 32, VTLists+0 },    // GPRnopc
3529
  { 32, 32, 32, VTLists+0 },    // rGPR
3530
  { 32, 32, 32, VTLists+0 },    // tGPRwithpc
3531
  { 32, 32, 32, VTLists+0 },    // hGPR
3532
  { 32, 32, 32, VTLists+0 },    // tGPR
3533
  { 32, 32, 32, VTLists+0 },    // GPRnopc_and_hGPR
3534
  { 32, 32, 32, VTLists+0 },    // hGPR_and_rGPR
3535
  { 32, 32, 32, VTLists+0 },    // tcGPR
3536
  { 32, 32, 32, VTLists+0 },    // tGPR_and_tcGPR
3537
  { 32, 32, 32, VTLists+0 },    // CCR
3538
  { 32, 32, 32, VTLists+0 },    // GPRsp
3539
  { 32, 32, 32, VTLists+0 },    // hGPR_and_tGPRwithpc
3540
  { 32, 32, 32, VTLists+0 },    // hGPR_and_tcGPR
3541
  { 64, 64, 64, VTLists+12 },    // DPR
3542
  { 64, 64, 64, VTLists+12 },    // DPR_VFP2
3543
  { 64, 64, 64, VTLists+12 },    // DPR_8
3544
  { 64, 64, 64, VTLists+35 },    // GPRPair
3545
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_rGPR
3546
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_tGPR
3547
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_hGPR
3548
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_tcGPR
3549
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_hGPR_and_rGPR
3550
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_tcGPR
3551
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_GPRsp
3552
  { 128, 128, 64, VTLists+6 },    // DPairSpc
3553
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_ssub_0
3554
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_ssub_4
3555
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_dsub_0_in_DPR_8
3556
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_dsub_2_in_DPR_8
3557
  { 128, 128, 128, VTLists+28 },    // DPair
3558
  { 128, 128, 128, VTLists+28 },    // DPair_with_ssub_0
3559
  { 128, 128, 128, VTLists+20 },    // QPR
3560
  { 128, 128, 128, VTLists+28 },    // DPair_with_ssub_2
3561
  { 128, 128, 128, VTLists+28 },    // DPair_with_dsub_0_in_DPR_8
3562
  { 128, 128, 128, VTLists+28 },    // QPR_VFP2
3563
  { 128, 128, 128, VTLists+28 },    // DPair_with_dsub_1_in_DPR_8
3564
  { 128, 128, 128, VTLists+28 },    // QPR_8
3565
  { 192, 192, 64, VTLists+35 },    // DTriple
3566
  { 192, 192, 64, VTLists+35 },    // DTripleSpc
3567
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_0
3568
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_0
3569
  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR
3570
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2
3571
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3572
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_4
3573
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_4
3574
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_8
3575
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_0_in_DPR_8
3576
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_0_in_DPR_8
3577
  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR_VFP2
3578
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3579
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_1_in_DPR_8
3580
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
3581
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
3582
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_2_in_DPR_8
3583
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_2_in_DPR_8
3584
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_4_in_DPR_8
3585
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3586
  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR_8
3587
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
3588
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
3589
  { 256, 256, 64, VTLists+8 },    // DQuadSpc
3590
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_0
3591
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_4
3592
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_8
3593
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_0_in_DPR_8
3594
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_2_in_DPR_8
3595
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_4_in_DPR_8
3596
  { 256, 256, 256, VTLists+8 },    // DQuad
3597
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_0
3598
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2
3599
  { 256, 256, 256, VTLists+8 },    // QQPR
3600
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3601
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_4
3602
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_6
3603
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_0_in_DPR_8
3604
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_0_in_QPR_VFP2
3605
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3606
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_1_in_DPR_8
3607
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_1_in_QPR_VFP2
3608
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
3609
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_2_in_DPR_8
3610
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3611
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_3_in_DPR_8
3612
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3613
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_0_in_QPR_8
3614
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_1_in_QPR_8
3615
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
3616
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3617
  { 512, 512, 256, VTLists+10 },    // QQQQPR
3618
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_0
3619
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_4
3620
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_8
3621
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_12
3622
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_0_in_DPR_8
3623
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_2_in_DPR_8
3624
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_4_in_DPR_8
3625
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_6_in_DPR_8
3626
};
3627
3628
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
3629
3630
static const uint32_t HPRSubClassMask[] = {
3631
  0x00000013, 0x00000000, 0x00000000, 0x00000000, 
3632
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_0
3633
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_1
3634
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_2
3635
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_3
3636
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_4
3637
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_5
3638
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_6
3639
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_7
3640
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_8
3641
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_9
3642
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_10
3643
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_11
3644
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_12
3645
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_13
3646
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_0
3647
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_1
3648
};
3649
3650
static const uint32_t SPRSubClassMask[] = {
3651
  0x00000012, 0x00000000, 0x00000000, 0x00000000, 
3652
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_0
3653
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_1
3654
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_2
3655
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_3
3656
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_4
3657
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_5
3658
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_6
3659
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_7
3660
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_8
3661
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_9
3662
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_10
3663
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_11
3664
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_12
3665
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_13
3666
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_0
3667
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_1
3668
};
3669
3670
static const uint32_t GPRSubClassMask[] = {
3671
  0x0003bfe4, 0x00000000, 0x00000000, 0x00000000, 
3672
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3673
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3674
};
3675
3676
static const uint32_t GPRwithAPSRSubClassMask[] = {
3677
  0x0002be68, 0x00000000, 0x00000000, 0x00000000, 
3678
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3679
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3680
};
3681
3682
static const uint32_t SPR_8SubClassMask[] = {
3683
  0x00000010, 0x00000000, 0x00000000, 0x00000000, 
3684
  0x00100000, 0xf9300343, 0x3f4901c3, 0x00000078, // ssub_0
3685
  0x00100000, 0xf9300343, 0x3f4901c3, 0x00000078, // ssub_1
3686
  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // ssub_2
3687
  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // ssub_3
3688
  0x00000000, 0x38000002, 0x39400183, 0x00000070, // ssub_4
3689
  0x00000000, 0x38000002, 0x39400183, 0x00000070, // ssub_5
3690
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_6
3691
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_7
3692
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_8
3693
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_9
3694
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_10
3695
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_11
3696
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_12
3697
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_13
3698
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7_then_ssub_0
3699
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7_then_ssub_1
3700
};
3701
3702
static const uint32_t GPRnopcSubClassMask[] = {
3703
  0x0002be60, 0x00000000, 0x00000000, 0x00000000, 
3704
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3705
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3706
};
3707
3708
static const uint32_t rGPRSubClassMask[] = {
3709
  0x00023a40, 0x00000000, 0x00000000, 0x00000000, 
3710
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3711
  0x0cc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3712
};
3713
3714
static const uint32_t tGPRwithpcSubClassMask[] = {
3715
  0x00012280, 0x00000000, 0x00000000, 0x00000000, 
3716
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3717
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3718
};
3719
3720
static const uint32_t hGPRSubClassMask[] = {
3721
  0x00038d00, 0x00000000, 0x00000000, 0x00000000, 
3722
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3723
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3724
};
3725
3726
static const uint32_t tGPRSubClassMask[] = {
3727
  0x00002200, 0x00000000, 0x00000000, 0x00000000, 
3728
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3729
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3730
};
3731
3732
static const uint32_t GPRnopc_and_hGPRSubClassMask[] = {
3733
  0x00028c00, 0x00000000, 0x00000000, 0x00000000, 
3734
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3735
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3736
};
3737
3738
static const uint32_t hGPR_and_rGPRSubClassMask[] = {
3739
  0x00020800, 0x00000000, 0x00000000, 0x00000000, 
3740
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3741
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3742
};
3743
3744
static const uint32_t tcGPRSubClassMask[] = {
3745
  0x00023000, 0x00000000, 0x00000000, 0x00000000, 
3746
  0x1a000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3747
  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3748
};
3749
3750
static const uint32_t tGPR_and_tcGPRSubClassMask[] = {
3751
  0x00002000, 0x00000000, 0x00000000, 0x00000000, 
3752
  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3753
  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3754
};
3755
3756
static const uint32_t CCRSubClassMask[] = {
3757
  0x00004000, 0x00000000, 0x00000000, 0x00000000, 
3758
};
3759
3760
static const uint32_t GPRspSubClassMask[] = {
3761
  0x00008000, 0x00000000, 0x00000000, 0x00000000, 
3762
  0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3763
};
3764
3765
static const uint32_t hGPR_and_tGPRwithpcSubClassMask[] = {
3766
  0x00010000, 0x00000000, 0x00000000, 0x00000000, 
3767
};
3768
3769
static const uint32_t hGPR_and_tcGPRSubClassMask[] = {
3770
  0x00020000, 0x00000000, 0x00000000, 0x00000000, 
3771
  0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3772
};
3773
3774
static const uint32_t DPRSubClassMask[] = {
3775
  0x001c0000, 0x00000000, 0x00000000, 0x00000000, 
3776
  0xe0000000, 0xffffffff, 0xffffffff, 0x0000007f, // dsub_0
3777
  0x00000000, 0xd7e5e7fc, 0xfffffe03, 0x0000007f, // dsub_1
3778
  0xe0000000, 0xfffffc03, 0xffffffff, 0x0000007f, // dsub_2
3779
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // dsub_3
3780
  0x00000000, 0x281a1800, 0xc00001fc, 0x0000007f, // dsub_4
3781
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5
3782
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_6
3783
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_7
3784
};
3785
3786
static const uint32_t DPR_VFP2SubClassMask[] = {
3787
  0x00180000, 0x00000000, 0x00000000, 0x00000000, 
3788
  0xc0000000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // dsub_0
3789
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // dsub_1
3790
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // dsub_2
3791
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // dsub_3
3792
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // dsub_4
3793
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5
3794
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_6
3795
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7
3796
};
3797
3798
static const uint32_t DPR_8SubClassMask[] = {
3799
  0x00100000, 0x00000000, 0x00000000, 0x00000000, 
3800
  0x00000000, 0xf9300343, 0x3f4901c3, 0x00000078, // dsub_0
3801
  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // dsub_1
3802
  0x00000000, 0x38000002, 0x39400183, 0x00000070, // dsub_2
3803
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // dsub_3
3804
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // dsub_4
3805
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5
3806
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_6
3807
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7
3808
};
3809
3810
static const uint32_t GPRPairSubClassMask[] = {
3811
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, 
3812
};
3813
3814
static const uint32_t GPRPair_with_gsub_1_in_rGPRSubClassMask[] = {
3815
  0x0cc00000, 0x00000000, 0x00000000, 0x00000000, 
3816
};
3817
3818
static const uint32_t GPRPair_with_gsub_0_in_tGPRSubClassMask[] = {
3819
  0x08800000, 0x00000000, 0x00000000, 0x00000000, 
3820
};
3821
3822
static const uint32_t GPRPair_with_gsub_0_in_hGPRSubClassMask[] = {
3823
  0x15000000, 0x00000000, 0x00000000, 0x00000000, 
3824
};
3825
3826
static const uint32_t GPRPair_with_gsub_0_in_tcGPRSubClassMask[] = {
3827
  0x1a000000, 0x00000000, 0x00000000, 0x00000000, 
3828
};
3829
3830
static const uint32_t GPRPair_with_gsub_1_in_hGPR_and_rGPRSubClassMask[] = {
3831
  0x04000000, 0x00000000, 0x00000000, 0x00000000, 
3832
};
3833
3834
static const uint32_t GPRPair_with_gsub_1_in_tcGPRSubClassMask[] = {
3835
  0x08000000, 0x00000000, 0x00000000, 0x00000000, 
3836
};
3837
3838
static const uint32_t GPRPair_with_gsub_1_in_GPRspSubClassMask[] = {
3839
  0x10000000, 0x00000000, 0x00000000, 0x00000000, 
3840
};
3841
3842
static const uint32_t DPairSpcSubClassMask[] = {
3843
  0xe0000000, 0x00000003, 0x00000000, 0x00000000, 
3844
  0x00000000, 0xfffffc00, 0xffffffff, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
3845
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
3846
  0x00000000, 0x281a1800, 0xc00001fc, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9
3847
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5
3848
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_ssub_12_ssub_13
3849
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_dsub_7
3850
};
3851
3852
static const uint32_t DPairSpc_with_ssub_0SubClassMask[] = {
3853
  0xc0000000, 0x00000003, 0x00000000, 0x00000000, 
3854
  0x00000000, 0xfffeb000, 0xbfffcdfb, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
3855
  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
3856
  0x00000000, 0x281a0000, 0x000001f0, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9
3857
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5
3858
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_ssub_12_ssub_13
3859
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_dsub_7
3860
};
3861
3862
static const uint32_t DPairSpc_with_ssub_4SubClassMask[] = {
3863
  0x80000000, 0x00000003, 0x00000000, 0x00000000, 
3864
  0x00000000, 0xff3e0000, 0x3ff9c1f3, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
3865
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
3866
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9
3867
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5
3868
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_ssub_12_ssub_13
3869
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_dsub_7
3870
};
3871
3872
static const uint32_t DPairSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
3873
  0x00000000, 0x00000003, 0x00000000, 0x00000000, 
3874
  0x00000000, 0xf9300000, 0x3f4901c3, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5
3875
  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7
3876
  0x00000000, 0x28000000, 0x00000180, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9
3877
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5
3878
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_ssub_12_ssub_13
3879
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_dsub_7
3880
};
3881
3882
static const uint32_t DPairSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
3883
  0x00000000, 0x00000002, 0x00000000, 0x00000000, 
3884
  0x00000000, 0x38000000, 0x39400183, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5
3885
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7
3886
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9
3887
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5
3888
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_ssub_12_ssub_13
3889
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_dsub_7
3890
};
3891
3892
static const uint32_t DPairSubClassMask[] = {
3893
  0x00000000, 0x000003fc, 0x00000000, 0x00000000, 
3894
  0x00000000, 0xd7e5e400, 0xfffffe03, 0x0000007f, // qsub_0
3895
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // qsub_1
3896
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_2
3897
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_3
3898
  0x00000000, 0xd7e5e400, 0xfffffe03, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
3899
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9
3900
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13
3901
};
3902
3903
static const uint32_t DPair_with_ssub_0SubClassMask[] = {
3904
  0x00000000, 0x000003e8, 0x00000000, 0x00000000, 
3905
  0x00000000, 0xd7e4a000, 0xbfffcc03, 0x0000007f, // qsub_0
3906
  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // qsub_1
3907
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
3908
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
3909
  0x00000000, 0xd7648000, 0xbffbc803, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
3910
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9
3911
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13
3912
};
3913
3914
static const uint32_t QPRSubClassMask[] = {
3915
  0x00000000, 0x00000290, 0x00000000, 0x00000000, 
3916
  0x00000000, 0x84404000, 0xcc121001, 0x0000007f, // qsub_0
3917
  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // qsub_1
3918
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_2
3919
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_3
3920
  0x00000000, 0x42810000, 0x32a42002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3921
};
3922
3923
static const uint32_t DPair_with_ssub_2SubClassMask[] = {
3924
  0x00000000, 0x000003e0, 0x00000000, 0x00000000, 
3925
  0x00000000, 0xd7648000, 0xbffbc803, 0x0000007f, // qsub_0
3926
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // qsub_1
3927
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
3928
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
3929
  0x00000000, 0xd7240000, 0x3ff9c003, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
3930
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9
3931
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13
3932
};
3933
3934
static const uint32_t DPair_with_dsub_0_in_DPR_8SubClassMask[] = {
3935
  0x00000000, 0x00000340, 0x00000000, 0x00000000, 
3936
  0x00000000, 0xd1200000, 0x3f490003, 0x00000078, // qsub_0
3937
  0x00000000, 0x00000000, 0x39400000, 0x00000070, // qsub_1
3938
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
3939
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
3940
  0x00000000, 0x91000000, 0x3d480003, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5
3941
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9
3942
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13
3943
};
3944
3945
static const uint32_t QPR_VFP2SubClassMask[] = {
3946
  0x00000000, 0x00000280, 0x00000000, 0x00000000, 
3947
  0x00000000, 0x84400000, 0x8c120001, 0x0000007f, // qsub_0
3948
  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // qsub_1
3949
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
3950
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
3951
  0x00000000, 0x42000000, 0x32a00002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3952
};
3953
3954
static const uint32_t DPair_with_dsub_1_in_DPR_8SubClassMask[] = {
3955
  0x00000000, 0x00000300, 0x00000000, 0x00000000, 
3956
  0x00000000, 0x91000000, 0x3d480003, 0x00000078, // qsub_0
3957
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // qsub_1
3958
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
3959
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
3960
  0x00000000, 0x10000000, 0x39400003, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5
3961
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9
3962
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13
3963
};
3964
3965
static const uint32_t QPR_8SubClassMask[] = {
3966
  0x00000000, 0x00000200, 0x00000000, 0x00000000, 
3967
  0x00000000, 0x80000000, 0x0c000001, 0x00000078, // qsub_0
3968
  0x00000000, 0x00000000, 0x08000000, 0x00000070, // qsub_1
3969
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
3970
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
3971
  0x00000000, 0x00000000, 0x30000002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3972
};
3973
3974
static const uint32_t DTripleSubClassMask[] = {
3975
  0x00000000, 0xd7e5e400, 0x00000003, 0x00000000, 
3976
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3977
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3978
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3979
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
3980
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3981
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13_dsub_7
3982
};
3983
3984
static const uint32_t DTripleSpcSubClassMask[] = {
3985
  0x00000000, 0x281a1800, 0x000001fc, 0x00000000, 
3986
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
3987
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
3988
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3989
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
3990
};
3991
3992
static const uint32_t DTripleSpc_with_ssub_0SubClassMask[] = {
3993
  0x00000000, 0x281a1000, 0x000001f8, 0x00000000, 
3994
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
3995
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
3996
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3997
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
3998
};
3999
4000
static const uint32_t DTriple_with_ssub_0SubClassMask[] = {
4001
  0x00000000, 0xd7e4a000, 0x00000003, 0x00000000, 
4002
  0x00000000, 0x00000000, 0xbfffcc00, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4003
  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4004
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4005
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4006
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4007
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13_dsub_7
4008
};
4009
4010
static const uint32_t DTriple_with_qsub_0_in_QPRSubClassMask[] = {
4011
  0x00000000, 0x84404000, 0x00000001, 0x00000000, 
4012
  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4013
  0x00000000, 0x00000000, 0x32a42000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4014
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4015
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4016
};
4017
4018
static const uint32_t DTriple_with_ssub_2SubClassMask[] = {
4019
  0x00000000, 0xd7648000, 0x00000003, 0x00000000, 
4020
  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4021
  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4022
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4023
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4024
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4025
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
4026
};
4027
4028
static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4029
  0x00000000, 0x42810000, 0x00000002, 0x00000000, 
4030
  0x00000000, 0x00000000, 0x32a42000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4031
  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4032
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4033
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13_dsub_7
4034
};
4035
4036
static const uint32_t DTripleSpc_with_ssub_4SubClassMask[] = {
4037
  0x00000000, 0x281a0000, 0x000001f0, 0x00000000, 
4038
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4039
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4040
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4041
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5_dsub_7
4042
};
4043
4044
static const uint32_t DTriple_with_ssub_4SubClassMask[] = {
4045
  0x00000000, 0xd7240000, 0x00000003, 0x00000000, 
4046
  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4047
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4048
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4049
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4050
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4051
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
4052
};
4053
4054
static const uint32_t DTripleSpc_with_ssub_8SubClassMask[] = {
4055
  0x00000000, 0x28180000, 0x000001e0, 0x00000000, 
4056
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4057
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4058
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4059
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_dsub_5_dsub_7
4060
};
4061
4062
static const uint32_t DTripleSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
4063
  0x00000000, 0x28100000, 0x000001c0, 0x00000000, 
4064
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4065
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4066
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4067
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5_dsub_7
4068
};
4069
4070
static const uint32_t DTriple_with_dsub_0_in_DPR_8SubClassMask[] = {
4071
  0x00000000, 0xd1200000, 0x00000003, 0x00000000, 
4072
  0x00000000, 0x00000000, 0x3f490000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4073
  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4074
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4075
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4076
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4077
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13_dsub_7
4078
};
4079
4080
static const uint32_t DTriple_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
4081
  0x00000000, 0x84400000, 0x00000001, 0x00000000, 
4082
  0x00000000, 0x00000000, 0x8c120000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4083
  0x00000000, 0x00000000, 0x32a00000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4084
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4085
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4086
};
4087
4088
static const uint32_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4089
  0x00000000, 0x42800000, 0x00000002, 0x00000000, 
4090
  0x00000000, 0x00000000, 0x32a40000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4091
  0x00000000, 0x00000000, 0x8c120000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4092
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4093
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13_dsub_7
4094
};
4095
4096
static const uint32_t DTriple_with_dsub_1_in_DPR_8SubClassMask[] = {
4097
  0x00000000, 0x91000000, 0x00000003, 0x00000000, 
4098
  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4099
  0x00000000, 0x00000000, 0x39400000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4100
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4101
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4102
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4103
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
4104
};
4105
4106
static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
4107
  0x00000000, 0x42000000, 0x00000002, 0x00000000, 
4108
  0x00000000, 0x00000000, 0x32a00000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4109
  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4110
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4111
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
4112
};
4113
4114
static const uint32_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
4115
  0x00000000, 0x84000000, 0x00000001, 0x00000000, 
4116
  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4117
  0x00000000, 0x00000000, 0x32800000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4118
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4119
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4120
};
4121
4122
static const uint32_t DTripleSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
4123
  0x00000000, 0x28000000, 0x00000180, 0x00000000, 
4124
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4125
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4126
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4127
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5_dsub_7
4128
};
4129
4130
static const uint32_t DTriple_with_dsub_2_in_DPR_8SubClassMask[] = {
4131
  0x00000000, 0x10000000, 0x00000003, 0x00000000, 
4132
  0x00000000, 0x00000000, 0x39400000, 0x00000070, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4133
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4134
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4135
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4136
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4137
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
4138
};
4139
4140
static const uint32_t DTripleSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
4141
  0x00000000, 0x20000000, 0x00000100, 0x00000000, 
4142
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4143
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4144
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4145
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_dsub_5_dsub_7
4146
};
4147
4148
static const uint32_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4149
  0x00000000, 0x40000000, 0x00000002, 0x00000000, 
4150
  0x00000000, 0x00000000, 0x32000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4151
  0x00000000, 0x00000000, 0x0c000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4152
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4153
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13_dsub_7
4154
};
4155
4156
static const uint32_t DTriple_with_qsub_0_in_QPR_8SubClassMask[] = {
4157
  0x00000000, 0x80000000, 0x00000001, 0x00000000, 
4158
  0x00000000, 0x00000000, 0x0c000000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4159
  0x00000000, 0x00000000, 0x30000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4160
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4161
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4162
};
4163
4164
static const uint32_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
4165
  0x00000000, 0x00000000, 0x00000001, 0x00000000, 
4166
  0x00000000, 0x00000000, 0x08000000, 0x00000070, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4167
  0x00000000, 0x00000000, 0x20000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4168
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4169
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4170
};
4171
4172
static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
4173
  0x00000000, 0x00000000, 0x00000002, 0x00000000, 
4174
  0x00000000, 0x00000000, 0x30000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4175
  0x00000000, 0x00000000, 0x08000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4176
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4177
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
4178
};
4179
4180
static const uint32_t DQuadSpcSubClassMask[] = {
4181
  0x00000000, 0x00000000, 0x000001fc, 0x00000000, 
4182
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4183
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4184
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4185
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
4186
};
4187
4188
static const uint32_t DQuadSpc_with_ssub_0SubClassMask[] = {
4189
  0x00000000, 0x00000000, 0x000001f8, 0x00000000, 
4190
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4191
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4192
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4193
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
4194
};
4195
4196
static const uint32_t DQuadSpc_with_ssub_4SubClassMask[] = {
4197
  0x00000000, 0x00000000, 0x000001f0, 0x00000000, 
4198
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4199
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4200
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4201
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5_dsub_7
4202
};
4203
4204
static const uint32_t DQuadSpc_with_ssub_8SubClassMask[] = {
4205
  0x00000000, 0x00000000, 0x000001e0, 0x00000000, 
4206
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4207
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4208
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4209
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_dsub_5_dsub_7
4210
};
4211
4212
static const uint32_t DQuadSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
4213
  0x00000000, 0x00000000, 0x000001c0, 0x00000000, 
4214
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4215
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4216
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4217
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5_dsub_7
4218
};
4219
4220
static const uint32_t DQuadSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
4221
  0x00000000, 0x00000000, 0x00000180, 0x00000000, 
4222
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4223
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4224
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4225
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5_dsub_7
4226
};
4227
4228
static const uint32_t DQuadSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
4229
  0x00000000, 0x00000000, 0x00000100, 0x00000000, 
4230
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4231
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4232
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4233
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_dsub_5_dsub_7
4234
};
4235
4236
static const uint32_t DQuadSubClassMask[] = {
4237
  0x00000000, 0x00000000, 0x3ffffe00, 0x00000000, 
4238
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_0
4239
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_1
4240
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4241
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4242
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4243
};
4244
4245
static const uint32_t DQuad_with_ssub_0SubClassMask[] = {
4246
  0x00000000, 0x00000000, 0x3fffcc00, 0x00000000, 
4247
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
4248
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
4249
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4250
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4251
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4252
};
4253
4254
static const uint32_t DQuad_with_ssub_2SubClassMask[] = {
4255
  0x00000000, 0x00000000, 0x3ffbc800, 0x00000000, 
4256
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
4257
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
4258
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4259
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4260
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4261
};
4262
4263
static const uint32_t QQPRSubClassMask[] = {
4264
  0x00000000, 0x00000000, 0x0c121000, 0x00000000, 
4265
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_0
4266
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_1
4267
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4268
};
4269
4270
static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4271
  0x00000000, 0x00000000, 0x32a42000, 0x00000000, 
4272
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4273
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4274
};
4275
4276
static const uint32_t DQuad_with_ssub_4SubClassMask[] = {
4277
  0x00000000, 0x00000000, 0x3ff9c000, 0x00000000, 
4278
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
4279
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
4280
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4281
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4282
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4283
};
4284
4285
static const uint32_t DQuad_with_ssub_6SubClassMask[] = {
4286
  0x00000000, 0x00000000, 0x3fd98000, 0x00000000, 
4287
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
4288
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
4289
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4290
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4291
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4292
};
4293
4294
static const uint32_t DQuad_with_dsub_0_in_DPR_8SubClassMask[] = {
4295
  0x00000000, 0x00000000, 0x3f490000, 0x00000000, 
4296
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
4297
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
4298
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4299
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4300
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4301
};
4302
4303
static const uint32_t DQuad_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
4304
  0x00000000, 0x00000000, 0x0c120000, 0x00000000, 
4305
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
4306
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
4307
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4308
};
4309
4310
static const uint32_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4311
  0x00000000, 0x00000000, 0x32a40000, 0x00000000, 
4312
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4313
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4314
};
4315
4316
static const uint32_t DQuad_with_dsub_1_in_DPR_8SubClassMask[] = {
4317
  0x00000000, 0x00000000, 0x3d480000, 0x00000000, 
4318
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
4319
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
4320
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4321
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4322
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4323
};
4324
4325
static const uint32_t DQuad_with_qsub_1_in_QPR_VFP2SubClassMask[] = {
4326
  0x00000000, 0x00000000, 0x0c100000, 0x00000000, 
4327
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
4328
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
4329
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4330
};
4331
4332
static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
4333
  0x00000000, 0x00000000, 0x32a00000, 0x00000000, 
4334
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4335
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4336
};
4337
4338
static const uint32_t DQuad_with_dsub_2_in_DPR_8SubClassMask[] = {
4339
  0x00000000, 0x00000000, 0x39400000, 0x00000000, 
4340
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
4341
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
4342
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4343
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4344
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4345
};
4346
4347
static const uint32_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4348
  0x00000000, 0x00000000, 0x32800000, 0x00000000, 
4349
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4350
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4351
};
4352
4353
static const uint32_t DQuad_with_dsub_3_in_DPR_8SubClassMask[] = {
4354
  0x00000000, 0x00000000, 0x29000000, 0x00000000, 
4355
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
4356
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
4357
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4358
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4359
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4360
};
4361
4362
static const uint32_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4363
  0x00000000, 0x00000000, 0x32000000, 0x00000000, 
4364
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4365
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4366
};
4367
4368
static const uint32_t DQuad_with_qsub_0_in_QPR_8SubClassMask[] = {
4369
  0x00000000, 0x00000000, 0x0c000000, 0x00000000, 
4370
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
4371
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
4372
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4373
};
4374
4375
static const uint32_t DQuad_with_qsub_1_in_QPR_8SubClassMask[] = {
4376
  0x00000000, 0x00000000, 0x08000000, 0x00000000, 
4377
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
4378
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
4379
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4380
};
4381
4382
static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
4383
  0x00000000, 0x00000000, 0x30000000, 0x00000000, 
4384
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4385
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4386
};
4387
4388
static const uint32_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4389
  0x00000000, 0x00000000, 0x20000000, 0x00000000, 
4390
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4391
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4392
};
4393
4394
static const uint32_t QQQQPRSubClassMask[] = {
4395
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, 
4396
};
4397
4398
static const uint32_t QQQQPR_with_ssub_0SubClassMask[] = {
4399
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, 
4400
};
4401
4402
static const uint32_t QQQQPR_with_ssub_4SubClassMask[] = {
4403
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, 
4404
};
4405
4406
static const uint32_t QQQQPR_with_ssub_8SubClassMask[] = {
4407
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, 
4408
};
4409
4410
static const uint32_t QQQQPR_with_ssub_12SubClassMask[] = {
4411
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, 
4412
};
4413
4414
static const uint32_t QQQQPR_with_dsub_0_in_DPR_8SubClassMask[] = {
4415
  0x00000000, 0x00000000, 0x00000000, 0x00000078, 
4416
};
4417
4418
static const uint32_t QQQQPR_with_dsub_2_in_DPR_8SubClassMask[] = {
4419
  0x00000000, 0x00000000, 0x00000000, 0x00000070, 
4420
};
4421
4422
static const uint32_t QQQQPR_with_dsub_4_in_DPR_8SubClassMask[] = {
4423
  0x00000000, 0x00000000, 0x00000000, 0x00000060, 
4424
};
4425
4426
static const uint32_t QQQQPR_with_dsub_6_in_DPR_8SubClassMask[] = {
4427
  0x00000000, 0x00000000, 0x00000000, 0x00000040, 
4428
};
4429
4430
static const uint16_t SuperRegIdxSeqs[] = {
4431
  /* 0 */ 1, 2, 3, 4, 5, 6, 7, 8, 0,
4432
  /* 9 */ 9, 0,
4433
  /* 11 */ 9, 10, 0,
4434
  /* 14 */ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0,
4435
  /* 31 */ 13, 14, 15, 16, 37, 0,
4436
  /* 37 */ 38, 40, 45, 48, 0,
4437
  /* 42 */ 42, 50, 0,
4438
  /* 45 */ 34, 36, 44, 52, 0,
4439
  /* 50 */ 33, 35, 43, 46, 51, 53, 0,
4440
  /* 57 */ 34, 36, 47, 54, 0,
4441
  /* 62 */ 34, 36, 44, 47, 52, 54, 0,
4442
  /* 69 */ 13, 14, 15, 16, 37, 49, 55, 0,
4443
  /* 77 */ 11, 12, 56, 0,
4444
  /* 81 */ 11, 12, 42, 50, 56, 0,
4445
};
4446
4447
static const TargetRegisterClass *const SPRSuperclasses[] = {
4448
  &ARM::HPRRegClass,
4449
  nullptr
4450
};
4451
4452
static const TargetRegisterClass *const SPR_8Superclasses[] = {
4453
  &ARM::HPRRegClass,
4454
  &ARM::SPRRegClass,
4455
  nullptr
4456
};
4457
4458
static const TargetRegisterClass *const GPRnopcSuperclasses[] = {
4459
  &ARM::GPRRegClass,
4460
  &ARM::GPRwithAPSRRegClass,
4461
  nullptr
4462
};
4463
4464
static const TargetRegisterClass *const rGPRSuperclasses[] = {
4465
  &ARM::GPRRegClass,
4466
  &ARM::GPRwithAPSRRegClass,
4467
  &ARM::GPRnopcRegClass,
4468
  nullptr
4469
};
4470
4471
static const TargetRegisterClass *const tGPRwithpcSuperclasses[] = {
4472
  &ARM::GPRRegClass,
4473
  nullptr
4474
};
4475
4476
static const TargetRegisterClass *const hGPRSuperclasses[] = {
4477
  &ARM::GPRRegClass,
4478
  nullptr
4479
};
4480
4481
static const TargetRegisterClass *const tGPRSuperclasses[] = {
4482
  &ARM::GPRRegClass,
4483
  &ARM::GPRwithAPSRRegClass,
4484
  &ARM::GPRnopcRegClass,
4485
  &ARM::rGPRRegClass,
4486
  &ARM::tGPRwithpcRegClass,
4487
  nullptr
4488
};
4489
4490
static const TargetRegisterClass *const GPRnopc_and_hGPRSuperclasses[] = {
4491
  &ARM::GPRRegClass,
4492
  &ARM::GPRwithAPSRRegClass,
4493
  &ARM::GPRnopcRegClass,
4494
  &ARM::hGPRRegClass,
4495
  nullptr
4496
};
4497
4498
static const TargetRegisterClass *const hGPR_and_rGPRSuperclasses[] = {
4499
  &ARM::GPRRegClass,
4500
  &ARM::GPRwithAPSRRegClass,
4501
  &ARM::GPRnopcRegClass,
4502
  &ARM::rGPRRegClass,
4503
  &ARM::hGPRRegClass,
4504
  &ARM::GPRnopc_and_hGPRRegClass,
4505
  nullptr
4506
};
4507
4508
static const TargetRegisterClass *const tcGPRSuperclasses[] = {
4509
  &ARM::GPRRegClass,
4510
  &ARM::GPRwithAPSRRegClass,
4511
  &ARM::GPRnopcRegClass,
4512
  &ARM::rGPRRegClass,
4513
  nullptr
4514
};
4515
4516
static const TargetRegisterClass *const tGPR_and_tcGPRSuperclasses[] = {
4517
  &ARM::GPRRegClass,
4518
  &ARM::GPRwithAPSRRegClass,
4519
  &ARM::GPRnopcRegClass,
4520
  &ARM::rGPRRegClass,
4521
  &ARM::tGPRwithpcRegClass,
4522
  &ARM::tGPRRegClass,
4523
  &ARM::tcGPRRegClass,
4524
  nullptr
4525
};
4526
4527
static const TargetRegisterClass *const GPRspSuperclasses[] = {
4528
  &ARM::GPRRegClass,
4529
  &ARM::GPRwithAPSRRegClass,
4530
  &ARM::GPRnopcRegClass,
4531
  &ARM::hGPRRegClass,
4532
  &ARM::GPRnopc_and_hGPRRegClass,
4533
  nullptr
4534
};
4535
4536
static const TargetRegisterClass *const hGPR_and_tGPRwithpcSuperclasses[] = {
4537
  &ARM::GPRRegClass,
4538
  &ARM::tGPRwithpcRegClass,
4539
  &ARM::hGPRRegClass,
4540
  nullptr
4541
};
4542
4543
static const TargetRegisterClass *const hGPR_and_tcGPRSuperclasses[] = {
4544
  &ARM::GPRRegClass,
4545
  &ARM::GPRwithAPSRRegClass,
4546
  &ARM::GPRnopcRegClass,
4547
  &ARM::rGPRRegClass,
4548
  &ARM::hGPRRegClass,
4549
  &ARM::GPRnopc_and_hGPRRegClass,
4550
  &ARM::hGPR_and_rGPRRegClass,
4551
  &ARM::tcGPRRegClass,
4552
  nullptr
4553
};
4554
4555
static const TargetRegisterClass *const DPR_VFP2Superclasses[] = {
4556
  &ARM::DPRRegClass,
4557
  nullptr
4558
};
4559
4560
static const TargetRegisterClass *const DPR_8Superclasses[] = {
4561
  &ARM::DPRRegClass,
4562
  &ARM::DPR_VFP2RegClass,
4563
  nullptr
4564
};
4565
4566
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_rGPRSuperclasses[] = {
4567
  &ARM::GPRPairRegClass,
4568
  nullptr
4569
};
4570
4571
static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tGPRSuperclasses[] = {
4572
  &ARM::GPRPairRegClass,
4573
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4574
  nullptr
4575
};
4576
4577
static const TargetRegisterClass *const GPRPair_with_gsub_0_in_hGPRSuperclasses[] = {
4578
  &ARM::GPRPairRegClass,
4579
  nullptr
4580
};
4581
4582
static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tcGPRSuperclasses[] = {
4583
  &ARM::GPRPairRegClass,
4584
  nullptr
4585
};
4586
4587
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_hGPR_and_rGPRSuperclasses[] = {
4588
  &ARM::GPRPairRegClass,
4589
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4590
  &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
4591
  nullptr
4592
};
4593
4594
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_tcGPRSuperclasses[] = {
4595
  &ARM::GPRPairRegClass,
4596
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4597
  &ARM::GPRPair_with_gsub_0_in_tGPRRegClass,
4598
  &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
4599
  nullptr
4600
};
4601
4602
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_GPRspSuperclasses[] = {
4603
  &ARM::GPRPairRegClass,
4604
  &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
4605
  &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
4606
  nullptr
4607
};
4608
4609
static const TargetRegisterClass *const DPairSpc_with_ssub_0Superclasses[] = {
4610
  &ARM::DPairSpcRegClass,
4611
  nullptr
4612
};
4613
4614
static const TargetRegisterClass *const DPairSpc_with_ssub_4Superclasses[] = {
4615
  &ARM::DPairSpcRegClass,
4616
  &ARM::DPairSpc_with_ssub_0RegClass,
4617
  nullptr
4618
};
4619
4620
static const TargetRegisterClass *const DPairSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4621
  &ARM::DPairSpcRegClass,
4622
  &ARM::DPairSpc_with_ssub_0RegClass,
4623
  &ARM::DPairSpc_with_ssub_4RegClass,
4624
  nullptr
4625
};
4626
4627
static const TargetRegisterClass *const DPairSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4628
  &ARM::DPairSpcRegClass,
4629
  &ARM::DPairSpc_with_ssub_0RegClass,
4630
  &ARM::DPairSpc_with_ssub_4RegClass,
4631
  &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass,
4632
  nullptr
4633
};
4634
4635
static const TargetRegisterClass *const DPair_with_ssub_0Superclasses[] = {
4636
  &ARM::DPairRegClass,
4637
  nullptr
4638
};
4639
4640
static const TargetRegisterClass *const QPRSuperclasses[] = {
4641
  &ARM::DPairRegClass,
4642
  nullptr
4643
};
4644
4645
static const TargetRegisterClass *const DPair_with_ssub_2Superclasses[] = {
4646
  &ARM::DPairRegClass,
4647
  &ARM::DPair_with_ssub_0RegClass,
4648
  nullptr
4649
};
4650
4651
static const TargetRegisterClass *const DPair_with_dsub_0_in_DPR_8Superclasses[] = {
4652
  &ARM::DPairRegClass,
4653
  &ARM::DPair_with_ssub_0RegClass,
4654
  &ARM::DPair_with_ssub_2RegClass,
4655
  nullptr
4656
};
4657
4658
static const TargetRegisterClass *const QPR_VFP2Superclasses[] = {
4659
  &ARM::DPairRegClass,
4660
  &ARM::DPair_with_ssub_0RegClass,
4661
  &ARM::QPRRegClass,
4662
  &ARM::DPair_with_ssub_2RegClass,
4663
  nullptr
4664
};
4665
4666
static const TargetRegisterClass *const DPair_with_dsub_1_in_DPR_8Superclasses[] = {
4667
  &ARM::DPairRegClass,
4668
  &ARM::DPair_with_ssub_0RegClass,
4669
  &ARM::DPair_with_ssub_2RegClass,
4670
  &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
4671
  nullptr
4672
};
4673
4674
static const TargetRegisterClass *const QPR_8Superclasses[] = {
4675
  &ARM::DPairRegClass,
4676
  &ARM::DPair_with_ssub_0RegClass,
4677
  &ARM::QPRRegClass,
4678
  &ARM::DPair_with_ssub_2RegClass,
4679
  &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
4680
  &ARM::QPR_VFP2RegClass,
4681
  &ARM::DPair_with_dsub_1_in_DPR_8RegClass,
4682
  nullptr
4683
};
4684
4685
static const TargetRegisterClass *const DTripleSpc_with_ssub_0Superclasses[] = {
4686
  &ARM::DTripleSpcRegClass,
4687
  nullptr
4688
};
4689
4690
static const TargetRegisterClass *const DTriple_with_ssub_0Superclasses[] = {
4691
  &ARM::DTripleRegClass,
4692
  nullptr
4693
};
4694
4695
static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4696
  &ARM::DTripleRegClass,
4697
  nullptr
4698
};
4699
4700
static const TargetRegisterClass *const DTriple_with_ssub_2Superclasses[] = {
4701
  &ARM::DTripleRegClass,
4702
  &ARM::DTriple_with_ssub_0RegClass,
4703
  nullptr
4704
};
4705
4706
static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4707
  &ARM::DTripleRegClass,
4708
  nullptr
4709
};
4710
4711
static const TargetRegisterClass *const DTripleSpc_with_ssub_4Superclasses[] = {
4712
  &ARM::DTripleSpcRegClass,
4713
  &ARM::DTripleSpc_with_ssub_0RegClass,
4714
  nullptr
4715
};
4716
4717
static const TargetRegisterClass *const DTriple_with_ssub_4Superclasses[] = {
4718
  &ARM::DTripleRegClass,
4719
  &ARM::DTriple_with_ssub_0RegClass,
4720
  &ARM::DTriple_with_ssub_2RegClass,
4721
  nullptr
4722
};
4723
4724
static const TargetRegisterClass *const DTripleSpc_with_ssub_8Superclasses[] = {
4725
  &ARM::DTripleSpcRegClass,
4726
  &ARM::DTripleSpc_with_ssub_0RegClass,
4727
  &ARM::DTripleSpc_with_ssub_4RegClass,
4728
  nullptr
4729
};
4730
4731
static const TargetRegisterClass *const DTripleSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4732
  &ARM::DTripleSpcRegClass,
4733
  &ARM::DTripleSpc_with_ssub_0RegClass,
4734
  &ARM::DTripleSpc_with_ssub_4RegClass,
4735
  &ARM::DTripleSpc_with_ssub_8RegClass,
4736
  nullptr
4737
};
4738
4739
static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8Superclasses[] = {
4740
  &ARM::DTripleRegClass,
4741
  &ARM::DTriple_with_ssub_0RegClass,
4742
  &ARM::DTriple_with_ssub_2RegClass,
4743
  &ARM::DTriple_with_ssub_4RegClass,
4744
  nullptr
4745
};
4746
4747
static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_VFP2Superclasses[] = {
4748
  &ARM::DTripleRegClass,
4749
  &ARM::DTriple_with_ssub_0RegClass,
4750
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4751
  &ARM::DTriple_with_ssub_2RegClass,
4752
  nullptr
4753
};
4754
4755
static const TargetRegisterClass *const DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4756
  &ARM::DTripleRegClass,
4757
  &ARM::DTriple_with_ssub_0RegClass,
4758
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4759
  nullptr
4760
};
4761
4762
static const TargetRegisterClass *const DTriple_with_dsub_1_in_DPR_8Superclasses[] = {
4763
  &ARM::DTripleRegClass,
4764
  &ARM::DTriple_with_ssub_0RegClass,
4765
  &ARM::DTriple_with_ssub_2RegClass,
4766
  &ARM::DTriple_with_ssub_4RegClass,
4767
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4768
  nullptr
4769
};
4770
4771
static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
4772
  &ARM::DTripleRegClass,
4773
  &ARM::DTriple_with_ssub_0RegClass,
4774
  &ARM::DTriple_with_ssub_2RegClass,
4775
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4776
  &ARM::DTriple_with_ssub_4RegClass,
4777
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4778
  nullptr
4779
};
4780
4781
static const TargetRegisterClass *const DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4782
  &ARM::DTripleRegClass,
4783
  &ARM::DTriple_with_ssub_0RegClass,
4784
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4785
  &ARM::DTriple_with_ssub_2RegClass,
4786
  &ARM::DTriple_with_ssub_4RegClass,
4787
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4788
  nullptr
4789
};
4790
4791
static const TargetRegisterClass *const DTripleSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4792
  &ARM::DTripleSpcRegClass,
4793
  &ARM::DTripleSpc_with_ssub_0RegClass,
4794
  &ARM::DTripleSpc_with_ssub_4RegClass,
4795
  &ARM::DTripleSpc_with_ssub_8RegClass,
4796
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4797
  nullptr
4798
};
4799
4800
static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8Superclasses[] = {
4801
  &ARM::DTripleRegClass,
4802
  &ARM::DTriple_with_ssub_0RegClass,
4803
  &ARM::DTriple_with_ssub_2RegClass,
4804
  &ARM::DTriple_with_ssub_4RegClass,
4805
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4806
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4807
  nullptr
4808
};
4809
4810
static const TargetRegisterClass *const DTripleSpc_with_dsub_4_in_DPR_8Superclasses[] = {
4811
  &ARM::DTripleSpcRegClass,
4812
  &ARM::DTripleSpc_with_ssub_0RegClass,
4813
  &ARM::DTripleSpc_with_ssub_4RegClass,
4814
  &ARM::DTripleSpc_with_ssub_8RegClass,
4815
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4816
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4817
  nullptr
4818
};
4819
4820
static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4821
  &ARM::DTripleRegClass,
4822
  &ARM::DTriple_with_ssub_0RegClass,
4823
  &ARM::DTriple_with_ssub_2RegClass,
4824
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4825
  &ARM::DTriple_with_ssub_4RegClass,
4826
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4827
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4828
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
4829
  nullptr
4830
};
4831
4832
static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_8Superclasses[] = {
4833
  &ARM::DTripleRegClass,
4834
  &ARM::DTriple_with_ssub_0RegClass,
4835
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4836
  &ARM::DTriple_with_ssub_2RegClass,
4837
  &ARM::DTriple_with_ssub_4RegClass,
4838
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4839
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4840
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4841
  &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
4842
  nullptr
4843
};
4844
4845
static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4846
  &ARM::DTripleRegClass,
4847
  &ARM::DTriple_with_ssub_0RegClass,
4848
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4849
  &ARM::DTriple_with_ssub_2RegClass,
4850
  &ARM::DTriple_with_ssub_4RegClass,
4851
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4852
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4853
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4854
  &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
4855
  &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
4856
  &ARM::DTriple_with_qsub_0_in_QPR_8RegClass,
4857
  nullptr
4858
};
4859
4860
static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
4861
  &ARM::DTripleRegClass,
4862
  &ARM::DTriple_with_ssub_0RegClass,
4863
  &ARM::DTriple_with_ssub_2RegClass,
4864
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4865
  &ARM::DTriple_with_ssub_4RegClass,
4866
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4867
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4868
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4869
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
4870
  &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
4871
  &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4872
  nullptr
4873
};
4874
4875
static const TargetRegisterClass *const DQuadSpcSuperclasses[] = {
4876
  &ARM::DTripleSpcRegClass,
4877
  nullptr
4878
};
4879
4880
static const TargetRegisterClass *const DQuadSpc_with_ssub_0Superclasses[] = {
4881
  &ARM::DTripleSpcRegClass,
4882
  &ARM::DTripleSpc_with_ssub_0RegClass,
4883
  &ARM::DQuadSpcRegClass,
4884
  nullptr
4885
};
4886
4887
static const TargetRegisterClass *const DQuadSpc_with_ssub_4Superclasses[] = {
4888
  &ARM::DTripleSpcRegClass,
4889
  &ARM::DTripleSpc_with_ssub_0RegClass,
4890
  &ARM::DTripleSpc_with_ssub_4RegClass,
4891
  &ARM::DQuadSpcRegClass,
4892
  &ARM::DQuadSpc_with_ssub_0RegClass,
4893
  nullptr
4894
};
4895
4896
static const TargetRegisterClass *const DQuadSpc_with_ssub_8Superclasses[] = {
4897
  &ARM::DTripleSpcRegClass,
4898
  &ARM::DTripleSpc_with_ssub_0RegClass,
4899
  &ARM::DTripleSpc_with_ssub_4RegClass,
4900
  &ARM::DTripleSpc_with_ssub_8RegClass,
4901
  &ARM::DQuadSpcRegClass,
4902
  &ARM::DQuadSpc_with_ssub_0RegClass,
4903
  &ARM::DQuadSpc_with_ssub_4RegClass,
4904
  nullptr
4905
};
4906
4907
static const TargetRegisterClass *const DQuadSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4908
  &ARM::DTripleSpcRegClass,
4909
  &ARM::DTripleSpc_with_ssub_0RegClass,
4910
  &ARM::DTripleSpc_with_ssub_4RegClass,
4911
  &ARM::DTripleSpc_with_ssub_8RegClass,
4912
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4913
  &ARM::DQuadSpcRegClass,
4914
  &ARM::DQuadSpc_with_ssub_0RegClass,
4915
  &ARM::DQuadSpc_with_ssub_4RegClass,
4916
  &ARM::DQuadSpc_with_ssub_8RegClass,
4917
  nullptr
4918
};
4919
4920
static const TargetRegisterClass *const DQuadSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4921
  &ARM::DTripleSpcRegClass,
4922
  &ARM::DTripleSpc_with_ssub_0RegClass,
4923
  &ARM::DTripleSpc_with_ssub_4RegClass,
4924
  &ARM::DTripleSpc_with_ssub_8RegClass,
4925
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4926
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4927
  &ARM::DQuadSpcRegClass,
4928
  &ARM::DQuadSpc_with_ssub_0RegClass,
4929
  &ARM::DQuadSpc_with_ssub_4RegClass,
4930
  &ARM::DQuadSpc_with_ssub_8RegClass,
4931
  &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
4932
  nullptr
4933
};
4934
4935
static const TargetRegisterClass *const DQuadSpc_with_dsub_4_in_DPR_8Superclasses[] = {
4936
  &ARM::DTripleSpcRegClass,
4937
  &ARM::DTripleSpc_with_ssub_0RegClass,
4938
  &ARM::DTripleSpc_with_ssub_4RegClass,
4939
  &ARM::DTripleSpc_with_ssub_8RegClass,
4940
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4941
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4942
  &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass,
4943
  &ARM::DQuadSpcRegClass,
4944
  &ARM::DQuadSpc_with_ssub_0RegClass,
4945
  &ARM::DQuadSpc_with_ssub_4RegClass,
4946
  &ARM::DQuadSpc_with_ssub_8RegClass,
4947
  &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
4948
  &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass,
4949
  nullptr
4950
};
4951
4952
static const TargetRegisterClass *const DQuad_with_ssub_0Superclasses[] = {
4953
  &ARM::DQuadRegClass,
4954
  nullptr
4955
};
4956
4957
static const TargetRegisterClass *const DQuad_with_ssub_2Superclasses[] = {
4958
  &ARM::DQuadRegClass,
4959
  &ARM::DQuad_with_ssub_0RegClass,
4960
  nullptr
4961
};
4962
4963
static const TargetRegisterClass *const QQPRSuperclasses[] = {
4964
  &ARM::DQuadRegClass,
4965
  nullptr
4966
};
4967
4968
static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4969
  &ARM::DQuadRegClass,
4970
  nullptr
4971
};
4972
4973
static const TargetRegisterClass *const DQuad_with_ssub_4Superclasses[] = {
4974
  &ARM::DQuadRegClass,
4975
  &ARM::DQuad_with_ssub_0RegClass,
4976
  &ARM::DQuad_with_ssub_2RegClass,
4977
  nullptr
4978
};
4979
4980
static const TargetRegisterClass *const DQuad_with_ssub_6Superclasses[] = {
4981
  &ARM::DQuadRegClass,
4982
  &ARM::DQuad_with_ssub_0RegClass,
4983
  &ARM::DQuad_with_ssub_2RegClass,
4984
  &ARM::DQuad_with_ssub_4RegClass,
4985
  nullptr
4986
};
4987
4988
static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8Superclasses[] = {
4989
  &ARM::DQuadRegClass,
4990
  &ARM::DQuad_with_ssub_0RegClass,
4991
  &ARM::DQuad_with_ssub_2RegClass,
4992
  &ARM::DQuad_with_ssub_4RegClass,
4993
  &ARM::DQuad_with_ssub_6RegClass,
4994
  nullptr
4995
};
4996
4997
static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_VFP2Superclasses[] = {
4998
  &ARM::DQuadRegClass,
4999
  &ARM::DQuad_with_ssub_0RegClass,
5000
  &ARM::DQuad_with_ssub_2RegClass,
5001
  &ARM::QQPRRegClass,
5002
  nullptr
5003
};
5004
5005
static const TargetRegisterClass *const DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5006
  &ARM::DQuadRegClass,
5007
  &ARM::DQuad_with_ssub_0RegClass,
5008
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5009
  nullptr
5010
};
5011
5012
static const TargetRegisterClass *const DQuad_with_dsub_1_in_DPR_8Superclasses[] = {
5013
  &ARM::DQuadRegClass,
5014
  &ARM::DQuad_with_ssub_0RegClass,
5015
  &ARM::DQuad_with_ssub_2RegClass,
5016
  &ARM::DQuad_with_ssub_4RegClass,
5017
  &ARM::DQuad_with_ssub_6RegClass,
5018
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5019
  nullptr
5020
};
5021
5022
static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_VFP2Superclasses[] = {
5023
  &ARM::DQuadRegClass,
5024
  &ARM::DQuad_with_ssub_0RegClass,
5025
  &ARM::DQuad_with_ssub_2RegClass,
5026
  &ARM::QQPRRegClass,
5027
  &ARM::DQuad_with_ssub_4RegClass,
5028
  &ARM::DQuad_with_ssub_6RegClass,
5029
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
5030
  nullptr
5031
};
5032
5033
static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
5034
  &ARM::DQuadRegClass,
5035
  &ARM::DQuad_with_ssub_0RegClass,
5036
  &ARM::DQuad_with_ssub_2RegClass,
5037
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5038
  &ARM::DQuad_with_ssub_4RegClass,
5039
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5040
  nullptr
5041
};
5042
5043
static const TargetRegisterClass *const DQuad_with_dsub_2_in_DPR_8Superclasses[] = {
5044
  &ARM::DQuadRegClass,
5045
  &ARM::DQuad_with_ssub_0RegClass,
5046
  &ARM::DQuad_with_ssub_2RegClass,
5047
  &ARM::DQuad_with_ssub_4RegClass,
5048
  &ARM::DQuad_with_ssub_6RegClass,
5049
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5050
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5051
  nullptr
5052
};
5053
5054
static const TargetRegisterClass *const DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5055
  &ARM::DQuadRegClass,
5056
  &ARM::DQuad_with_ssub_0RegClass,
5057
  &ARM::DQuad_with_ssub_2RegClass,
5058
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5059
  &ARM::DQuad_with_ssub_4RegClass,
5060
  &ARM::DQuad_with_ssub_6RegClass,
5061
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5062
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5063
  nullptr
5064
};
5065
5066
static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8Superclasses[] = {
5067
  &ARM::DQuadRegClass,
5068
  &ARM::DQuad_with_ssub_0RegClass,
5069
  &ARM::DQuad_with_ssub_2RegClass,
5070
  &ARM::DQuad_with_ssub_4RegClass,
5071
  &ARM::DQuad_with_ssub_6RegClass,
5072
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5073
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5074
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5075
  nullptr
5076
};
5077
5078
static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5079
  &ARM::DQuadRegClass,
5080
  &ARM::DQuad_with_ssub_0RegClass,
5081
  &ARM::DQuad_with_ssub_2RegClass,
5082
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5083
  &ARM::DQuad_with_ssub_4RegClass,
5084
  &ARM::DQuad_with_ssub_6RegClass,
5085
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5086
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5087
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5088
  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5089
  nullptr
5090
};
5091
5092
static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_8Superclasses[] = {
5093
  &ARM::DQuadRegClass,
5094
  &ARM::DQuad_with_ssub_0RegClass,
5095
  &ARM::DQuad_with_ssub_2RegClass,
5096
  &ARM::QQPRRegClass,
5097
  &ARM::DQuad_with_ssub_4RegClass,
5098
  &ARM::DQuad_with_ssub_6RegClass,
5099
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5100
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
5101
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5102
  &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
5103
  nullptr
5104
};
5105
5106
static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_8Superclasses[] = {
5107
  &ARM::DQuadRegClass,
5108
  &ARM::DQuad_with_ssub_0RegClass,
5109
  &ARM::DQuad_with_ssub_2RegClass,
5110
  &ARM::QQPRRegClass,
5111
  &ARM::DQuad_with_ssub_4RegClass,
5112
  &ARM::DQuad_with_ssub_6RegClass,
5113
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5114
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
5115
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5116
  &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
5117
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5118
  &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
5119
  &ARM::DQuad_with_qsub_0_in_QPR_8RegClass,
5120
  nullptr
5121
};
5122
5123
static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
5124
  &ARM::DQuadRegClass,
5125
  &ARM::DQuad_with_ssub_0RegClass,
5126
  &ARM::DQuad_with_ssub_2RegClass,
5127
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5128
  &ARM::DQuad_with_ssub_4RegClass,
5129
  &ARM::DQuad_with_ssub_6RegClass,
5130
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5131
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5132
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5133
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5134
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5135
  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5136