Coverage Report

Created: 2019-03-24 22:13

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenRegisterInfo.inc
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass ARMMCRegisterClasses[];
17
18
namespace ARM {
19
enum {
20
  NoRegister,
21
  APSR = 1,
22
  APSR_NZCV = 2,
23
  CPSR = 3,
24
  FPEXC = 4,
25
  FPINST = 5,
26
  FPSCR = 6,
27
  FPSCR_NZCV = 7,
28
  FPSID = 8,
29
  ITSTATE = 9,
30
  LR = 10,
31
  PC = 11,
32
  SP = 12,
33
  SPSR = 13,
34
  D0 = 14,
35
  D1 = 15,
36
  D2 = 16,
37
  D3 = 17,
38
  D4 = 18,
39
  D5 = 19,
40
  D6 = 20,
41
  D7 = 21,
42
  D8 = 22,
43
  D9 = 23,
44
  D10 = 24,
45
  D11 = 25,
46
  D12 = 26,
47
  D13 = 27,
48
  D14 = 28,
49
  D15 = 29,
50
  D16 = 30,
51
  D17 = 31,
52
  D18 = 32,
53
  D19 = 33,
54
  D20 = 34,
55
  D21 = 35,
56
  D22 = 36,
57
  D23 = 37,
58
  D24 = 38,
59
  D25 = 39,
60
  D26 = 40,
61
  D27 = 41,
62
  D28 = 42,
63
  D29 = 43,
64
  D30 = 44,
65
  D31 = 45,
66
  FPINST2 = 46,
67
  MVFR0 = 47,
68
  MVFR1 = 48,
69
  MVFR2 = 49,
70
  Q0 = 50,
71
  Q1 = 51,
72
  Q2 = 52,
73
  Q3 = 53,
74
  Q4 = 54,
75
  Q5 = 55,
76
  Q6 = 56,
77
  Q7 = 57,
78
  Q8 = 58,
79
  Q9 = 59,
80
  Q10 = 60,
81
  Q11 = 61,
82
  Q12 = 62,
83
  Q13 = 63,
84
  Q14 = 64,
85
  Q15 = 65,
86
  R0 = 66,
87
  R1 = 67,
88
  R2 = 68,
89
  R3 = 69,
90
  R4 = 70,
91
  R5 = 71,
92
  R6 = 72,
93
  R7 = 73,
94
  R8 = 74,
95
  R9 = 75,
96
  R10 = 76,
97
  R11 = 77,
98
  R12 = 78,
99
  S0 = 79,
100
  S1 = 80,
101
  S2 = 81,
102
  S3 = 82,
103
  S4 = 83,
104
  S5 = 84,
105
  S6 = 85,
106
  S7 = 86,
107
  S8 = 87,
108
  S9 = 88,
109
  S10 = 89,
110
  S11 = 90,
111
  S12 = 91,
112
  S13 = 92,
113
  S14 = 93,
114
  S15 = 94,
115
  S16 = 95,
116
  S17 = 96,
117
  S18 = 97,
118
  S19 = 98,
119
  S20 = 99,
120
  S21 = 100,
121
  S22 = 101,
122
  S23 = 102,
123
  S24 = 103,
124
  S25 = 104,
125
  S26 = 105,
126
  S27 = 106,
127
  S28 = 107,
128
  S29 = 108,
129
  S30 = 109,
130
  S31 = 110,
131
  D0_D2 = 111,
132
  D1_D3 = 112,
133
  D2_D4 = 113,
134
  D3_D5 = 114,
135
  D4_D6 = 115,
136
  D5_D7 = 116,
137
  D6_D8 = 117,
138
  D7_D9 = 118,
139
  D8_D10 = 119,
140
  D9_D11 = 120,
141
  D10_D12 = 121,
142
  D11_D13 = 122,
143
  D12_D14 = 123,
144
  D13_D15 = 124,
145
  D14_D16 = 125,
146
  D15_D17 = 126,
147
  D16_D18 = 127,
148
  D17_D19 = 128,
149
  D18_D20 = 129,
150
  D19_D21 = 130,
151
  D20_D22 = 131,
152
  D21_D23 = 132,
153
  D22_D24 = 133,
154
  D23_D25 = 134,
155
  D24_D26 = 135,
156
  D25_D27 = 136,
157
  D26_D28 = 137,
158
  D27_D29 = 138,
159
  D28_D30 = 139,
160
  D29_D31 = 140,
161
  Q0_Q1 = 141,
162
  Q1_Q2 = 142,
163
  Q2_Q3 = 143,
164
  Q3_Q4 = 144,
165
  Q4_Q5 = 145,
166
  Q5_Q6 = 146,
167
  Q6_Q7 = 147,
168
  Q7_Q8 = 148,
169
  Q8_Q9 = 149,
170
  Q9_Q10 = 150,
171
  Q10_Q11 = 151,
172
  Q11_Q12 = 152,
173
  Q12_Q13 = 153,
174
  Q13_Q14 = 154,
175
  Q14_Q15 = 155,
176
  Q0_Q1_Q2_Q3 = 156,
177
  Q1_Q2_Q3_Q4 = 157,
178
  Q2_Q3_Q4_Q5 = 158,
179
  Q3_Q4_Q5_Q6 = 159,
180
  Q4_Q5_Q6_Q7 = 160,
181
  Q5_Q6_Q7_Q8 = 161,
182
  Q6_Q7_Q8_Q9 = 162,
183
  Q7_Q8_Q9_Q10 = 163,
184
  Q8_Q9_Q10_Q11 = 164,
185
  Q9_Q10_Q11_Q12 = 165,
186
  Q10_Q11_Q12_Q13 = 166,
187
  Q11_Q12_Q13_Q14 = 167,
188
  Q12_Q13_Q14_Q15 = 168,
189
  R12_SP = 169,
190
  R0_R1 = 170,
191
  R2_R3 = 171,
192
  R4_R5 = 172,
193
  R6_R7 = 173,
194
  R8_R9 = 174,
195
  R10_R11 = 175,
196
  D0_D1_D2 = 176,
197
  D1_D2_D3 = 177,
198
  D2_D3_D4 = 178,
199
  D3_D4_D5 = 179,
200
  D4_D5_D6 = 180,
201
  D5_D6_D7 = 181,
202
  D6_D7_D8 = 182,
203
  D7_D8_D9 = 183,
204
  D8_D9_D10 = 184,
205
  D9_D10_D11 = 185,
206
  D10_D11_D12 = 186,
207
  D11_D12_D13 = 187,
208
  D12_D13_D14 = 188,
209
  D13_D14_D15 = 189,
210
  D14_D15_D16 = 190,
211
  D15_D16_D17 = 191,
212
  D16_D17_D18 = 192,
213
  D17_D18_D19 = 193,
214
  D18_D19_D20 = 194,
215
  D19_D20_D21 = 195,
216
  D20_D21_D22 = 196,
217
  D21_D22_D23 = 197,
218
  D22_D23_D24 = 198,
219
  D23_D24_D25 = 199,
220
  D24_D25_D26 = 200,
221
  D25_D26_D27 = 201,
222
  D26_D27_D28 = 202,
223
  D27_D28_D29 = 203,
224
  D28_D29_D30 = 204,
225
  D29_D30_D31 = 205,
226
  D0_D2_D4 = 206,
227
  D1_D3_D5 = 207,
228
  D2_D4_D6 = 208,
229
  D3_D5_D7 = 209,
230
  D4_D6_D8 = 210,
231
  D5_D7_D9 = 211,
232
  D6_D8_D10 = 212,
233
  D7_D9_D11 = 213,
234
  D8_D10_D12 = 214,
235
  D9_D11_D13 = 215,
236
  D10_D12_D14 = 216,
237
  D11_D13_D15 = 217,
238
  D12_D14_D16 = 218,
239
  D13_D15_D17 = 219,
240
  D14_D16_D18 = 220,
241
  D15_D17_D19 = 221,
242
  D16_D18_D20 = 222,
243
  D17_D19_D21 = 223,
244
  D18_D20_D22 = 224,
245
  D19_D21_D23 = 225,
246
  D20_D22_D24 = 226,
247
  D21_D23_D25 = 227,
248
  D22_D24_D26 = 228,
249
  D23_D25_D27 = 229,
250
  D24_D26_D28 = 230,
251
  D25_D27_D29 = 231,
252
  D26_D28_D30 = 232,
253
  D27_D29_D31 = 233,
254
  D0_D2_D4_D6 = 234,
255
  D1_D3_D5_D7 = 235,
256
  D2_D4_D6_D8 = 236,
257
  D3_D5_D7_D9 = 237,
258
  D4_D6_D8_D10 = 238,
259
  D5_D7_D9_D11 = 239,
260
  D6_D8_D10_D12 = 240,
261
  D7_D9_D11_D13 = 241,
262
  D8_D10_D12_D14 = 242,
263
  D9_D11_D13_D15 = 243,
264
  D10_D12_D14_D16 = 244,
265
  D11_D13_D15_D17 = 245,
266
  D12_D14_D16_D18 = 246,
267
  D13_D15_D17_D19 = 247,
268
  D14_D16_D18_D20 = 248,
269
  D15_D17_D19_D21 = 249,
270
  D16_D18_D20_D22 = 250,
271
  D17_D19_D21_D23 = 251,
272
  D18_D20_D22_D24 = 252,
273
  D19_D21_D23_D25 = 253,
274
  D20_D22_D24_D26 = 254,
275
  D21_D23_D25_D27 = 255,
276
  D22_D24_D26_D28 = 256,
277
  D23_D25_D27_D29 = 257,
278
  D24_D26_D28_D30 = 258,
279
  D25_D27_D29_D31 = 259,
280
  D1_D2 = 260,
281
  D3_D4 = 261,
282
  D5_D6 = 262,
283
  D7_D8 = 263,
284
  D9_D10 = 264,
285
  D11_D12 = 265,
286
  D13_D14 = 266,
287
  D15_D16 = 267,
288
  D17_D18 = 268,
289
  D19_D20 = 269,
290
  D21_D22 = 270,
291
  D23_D24 = 271,
292
  D25_D26 = 272,
293
  D27_D28 = 273,
294
  D29_D30 = 274,
295
  D1_D2_D3_D4 = 275,
296
  D3_D4_D5_D6 = 276,
297
  D5_D6_D7_D8 = 277,
298
  D7_D8_D9_D10 = 278,
299
  D9_D10_D11_D12 = 279,
300
  D11_D12_D13_D14 = 280,
301
  D13_D14_D15_D16 = 281,
302
  D15_D16_D17_D18 = 282,
303
  D17_D18_D19_D20 = 283,
304
  D19_D20_D21_D22 = 284,
305
  D21_D22_D23_D24 = 285,
306
  D23_D24_D25_D26 = 286,
307
  D25_D26_D27_D28 = 287,
308
  D27_D28_D29_D30 = 288,
309
  NUM_TARGET_REGS   // 289
310
};
311
} // end namespace ARM
312
313
// Register classes
314
315
namespace ARM {
316
enum {
317
  HPRRegClassID = 0,
318
  SPRRegClassID = 1,
319
  GPRRegClassID = 2,
320
  GPRwithAPSRRegClassID = 3,
321
  SPR_8RegClassID = 4,
322
  GPRnopcRegClassID = 5,
323
  rGPRRegClassID = 6,
324
  tGPRwithpcRegClassID = 7,
325
  hGPRRegClassID = 8,
326
  tGPRRegClassID = 9,
327
  GPRnopc_and_hGPRRegClassID = 10,
328
  hGPR_and_rGPRRegClassID = 11,
329
  tcGPRRegClassID = 12,
330
  tGPR_and_tcGPRRegClassID = 13,
331
  CCRRegClassID = 14,
332
  GPRspRegClassID = 15,
333
  hGPR_and_tGPRwithpcRegClassID = 16,
334
  hGPR_and_tcGPRRegClassID = 17,
335
  DPRRegClassID = 18,
336
  DPR_VFP2RegClassID = 19,
337
  DPR_8RegClassID = 20,
338
  GPRPairRegClassID = 21,
339
  GPRPair_with_gsub_1_in_rGPRRegClassID = 22,
340
  GPRPair_with_gsub_0_in_tGPRRegClassID = 23,
341
  GPRPair_with_gsub_0_in_hGPRRegClassID = 24,
342
  GPRPair_with_gsub_0_in_tcGPRRegClassID = 25,
343
  GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 26,
344
  GPRPair_with_gsub_1_in_tcGPRRegClassID = 27,
345
  GPRPair_with_gsub_1_in_GPRspRegClassID = 28,
346
  DPairSpcRegClassID = 29,
347
  DPairSpc_with_ssub_0RegClassID = 30,
348
  DPairSpc_with_ssub_4RegClassID = 31,
349
  DPairSpc_with_dsub_0_in_DPR_8RegClassID = 32,
350
  DPairSpc_with_dsub_2_in_DPR_8RegClassID = 33,
351
  DPairRegClassID = 34,
352
  DPair_with_ssub_0RegClassID = 35,
353
  QPRRegClassID = 36,
354
  DPair_with_ssub_2RegClassID = 37,
355
  DPair_with_dsub_0_in_DPR_8RegClassID = 38,
356
  QPR_VFP2RegClassID = 39,
357
  DPair_with_dsub_1_in_DPR_8RegClassID = 40,
358
  QPR_8RegClassID = 41,
359
  DTripleRegClassID = 42,
360
  DTripleSpcRegClassID = 43,
361
  DTripleSpc_with_ssub_0RegClassID = 44,
362
  DTriple_with_ssub_0RegClassID = 45,
363
  DTriple_with_qsub_0_in_QPRRegClassID = 46,
364
  DTriple_with_ssub_2RegClassID = 47,
365
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 48,
366
  DTripleSpc_with_ssub_4RegClassID = 49,
367
  DTriple_with_ssub_4RegClassID = 50,
368
  DTripleSpc_with_ssub_8RegClassID = 51,
369
  DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 52,
370
  DTriple_with_dsub_0_in_DPR_8RegClassID = 53,
371
  DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 54,
372
  DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 55,
373
  DTriple_with_dsub_1_in_DPR_8RegClassID = 56,
374
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 57,
375
  DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID = 58,
376
  DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 59,
377
  DTriple_with_dsub_2_in_DPR_8RegClassID = 60,
378
  DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 61,
379
  DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 62,
380
  DTriple_with_qsub_0_in_QPR_8RegClassID = 63,
381
  DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 64,
382
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 65,
383
  DQuadSpcRegClassID = 66,
384
  DQuadSpc_with_ssub_0RegClassID = 67,
385
  DQuadSpc_with_ssub_4RegClassID = 68,
386
  DQuadSpc_with_ssub_8RegClassID = 69,
387
  DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 70,
388
  DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 71,
389
  DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 72,
390
  DQuadRegClassID = 73,
391
  DQuad_with_ssub_0RegClassID = 74,
392
  DQuad_with_ssub_2RegClassID = 75,
393
  QQPRRegClassID = 76,
394
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 77,
395
  DQuad_with_ssub_4RegClassID = 78,
396
  DQuad_with_ssub_6RegClassID = 79,
397
  DQuad_with_dsub_0_in_DPR_8RegClassID = 80,
398
  DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 81,
399
  DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82,
400
  DQuad_with_dsub_1_in_DPR_8RegClassID = 83,
401
  DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 84,
402
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 85,
403
  DQuad_with_dsub_2_in_DPR_8RegClassID = 86,
404
  DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 87,
405
  DQuad_with_dsub_3_in_DPR_8RegClassID = 88,
406
  DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89,
407
  DQuad_with_qsub_0_in_QPR_8RegClassID = 90,
408
  DQuad_with_qsub_1_in_QPR_8RegClassID = 91,
409
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 92,
410
  DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 93,
411
  QQQQPRRegClassID = 94,
412
  QQQQPR_with_ssub_0RegClassID = 95,
413
  QQQQPR_with_ssub_4RegClassID = 96,
414
  QQQQPR_with_ssub_8RegClassID = 97,
415
  QQQQPR_with_ssub_12RegClassID = 98,
416
  QQQQPR_with_dsub_0_in_DPR_8RegClassID = 99,
417
  QQQQPR_with_dsub_2_in_DPR_8RegClassID = 100,
418
  QQQQPR_with_dsub_4_in_DPR_8RegClassID = 101,
419
  QQQQPR_with_dsub_6_in_DPR_8RegClassID = 102,
420
421
  };
422
} // end namespace ARM
423
424
425
// Register alternate name indices
426
427
namespace ARM {
428
enum {
429
  NoRegAltName, // 0
430
  RegNamesRaw,  // 1
431
  NUM_TARGET_REG_ALT_NAMES = 2
432
};
433
} // end namespace ARM
434
435
436
// Subregister indices
437
438
namespace ARM {
439
enum {
440
  NoSubRegister,
441
  dsub_0, // 1
442
  dsub_1, // 2
443
  dsub_2, // 3
444
  dsub_3, // 4
445
  dsub_4, // 5
446
  dsub_5, // 6
447
  dsub_6, // 7
448
  dsub_7, // 8
449
  gsub_0, // 9
450
  gsub_1, // 10
451
  qqsub_0,  // 11
452
  qqsub_1,  // 12
453
  qsub_0, // 13
454
  qsub_1, // 14
455
  qsub_2, // 15
456
  qsub_3, // 16
457
  ssub_0, // 17
458
  ssub_1, // 18
459
  ssub_2, // 19
460
  ssub_3, // 20
461
  ssub_4, // 21
462
  ssub_5, // 22
463
  ssub_6, // 23
464
  ssub_7, // 24
465
  ssub_8, // 25
466
  ssub_9, // 26
467
  ssub_10,  // 27
468
  ssub_11,  // 28
469
  ssub_12,  // 29
470
  ssub_13,  // 30
471
  dsub_7_then_ssub_0, // 31
472
  dsub_7_then_ssub_1, // 32
473
  ssub_0_ssub_1_ssub_4_ssub_5,  // 33
474
  ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5,  // 34
475
  ssub_2_ssub_3_ssub_6_ssub_7,  // 35
476
  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7,  // 36
477
  ssub_2_ssub_3_ssub_4_ssub_5,  // 37
478
  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9,  // 38
479
  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,  // 39
480
  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40
481
  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7,  // 41
482
  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,  // 42
483
  ssub_4_ssub_5_ssub_8_ssub_9,  // 43
484
  ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,  // 44
485
  ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,  // 45
486
  ssub_6_ssub_7_dsub_5, // 46
487
  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47
488
  ssub_6_ssub_7_dsub_5_dsub_7,  // 48
489
  ssub_6_ssub_7_ssub_8_ssub_9,  // 49
490
  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50
491
  ssub_8_ssub_9_ssub_12_ssub_13,  // 51
492
  ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52
493
  dsub_5_dsub_7,  // 53
494
  dsub_5_ssub_12_ssub_13_dsub_7,  // 54
495
  dsub_5_ssub_12_ssub_13, // 55
496
  ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56
497
  NUM_TARGET_SUBREGS
498
};
499
} // end namespace ARM
500
501
} // end namespace llvm
502
503
#endif // GET_REGINFO_ENUM
504
505
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
506
|*                                                                            *|
507
|* MC Register Information                                                    *|
508
|*                                                                            *|
509
|* Automatically generated file, do not edit!                                 *|
510
|*                                                                            *|
511
\*===----------------------------------------------------------------------===*/
512
513
514
#ifdef GET_REGINFO_MC_DESC
515
#undef GET_REGINFO_MC_DESC
516
517
namespace llvm {
518
519
extern const MCPhysReg ARMRegDiffLists[] = {
520
  /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
521
  /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
522
  /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
523
  /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
524
  /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0,
525
  /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0,
526
  /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0,
527
  /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0,
528
  /* 91 */ 40, 1, 1, 1, 1, 1, 0,
529
  /* 98 */ 65196, 1, 1, 1, 1, 1, 0,
530
  /* 105 */ 40, 1, 1, 1, 1, 0,
531
  /* 111 */ 42, 1, 1, 1, 1, 0,
532
  /* 117 */ 42, 1, 1, 1, 0,
533
  /* 122 */ 64510, 1, 1, 1, 0,
534
  /* 127 */ 65015, 1, 1, 1, 0,
535
  /* 132 */ 65282, 1, 1, 1, 0,
536
  /* 137 */ 65348, 1, 1, 1, 0,
537
  /* 142 */ 13, 1, 1, 0,
538
  /* 146 */ 42, 1, 1, 0,
539
  /* 150 */ 65388, 1, 1, 0,
540
  /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0,
541
  /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0,
542
  /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0,
543
  /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0,
544
  /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0,
545
  /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0,
546
  /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0,
547
  /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0,
548
  /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0,
549
  /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0,
550
  /* 254 */ 65489, 133, 65416, 1, 1, 0,
551
  /* 260 */ 65490, 133, 65416, 1, 1, 0,
552
  /* 266 */ 65491, 133, 65416, 1, 1, 0,
553
  /* 272 */ 65492, 133, 65416, 1, 1, 0,
554
  /* 278 */ 65493, 133, 65416, 1, 1, 0,
555
  /* 284 */ 65494, 133, 65416, 1, 1, 0,
556
  /* 290 */ 65495, 133, 65416, 1, 1, 0,
557
  /* 296 */ 65496, 133, 65416, 1, 1, 0,
558
  /* 302 */ 65497, 133, 65416, 1, 1, 0,
559
  /* 308 */ 65498, 133, 65416, 1, 1, 0,
560
  /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0,
561
  /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0,
562
  /* 332 */ 65136, 1, 3, 1, 3, 1, 0,
563
  /* 339 */ 65326, 1, 3, 1, 0,
564
  /* 344 */ 13, 1, 0,
565
  /* 347 */ 14, 1, 0,
566
  /* 350 */ 65, 1, 0,
567
  /* 353 */ 65500, 65, 1, 65471, 66, 1, 0,
568
  /* 360 */ 65291, 66, 1, 65470, 67, 1, 0,
569
  /* 367 */ 65439, 65, 1, 65472, 67, 1, 0,
570
  /* 374 */ 65501, 67, 1, 65469, 68, 1, 0,
571
  /* 381 */ 65439, 66, 1, 65471, 68, 1, 0,
572
  /* 388 */ 65292, 68, 1, 65468, 69, 1, 0,
573
  /* 395 */ 65439, 67, 1, 65470, 69, 1, 0,
574
  /* 402 */ 65502, 69, 1, 65467, 70, 1, 0,
575
  /* 409 */ 65439, 68, 1, 65469, 70, 1, 0,
576
  /* 416 */ 65293, 70, 1, 65466, 71, 1, 0,
577
  /* 423 */ 65439, 69, 1, 65468, 71, 1, 0,
578
  /* 430 */ 65503, 71, 1, 65465, 72, 1, 0,
579
  /* 437 */ 65439, 70, 1, 65467, 72, 1, 0,
580
  /* 444 */ 65294, 72, 1, 65464, 73, 1, 0,
581
  /* 451 */ 65439, 71, 1, 65466, 73, 1, 0,
582
  /* 458 */ 65504, 73, 1, 65463, 74, 1, 0,
583
  /* 465 */ 65439, 72, 1, 65465, 74, 1, 0,
584
  /* 472 */ 65295, 74, 1, 65462, 75, 1, 0,
585
  /* 479 */ 65439, 73, 1, 65464, 75, 1, 0,
586
  /* 486 */ 65505, 75, 1, 65461, 76, 1, 0,
587
  /* 493 */ 65439, 74, 1, 65463, 76, 1, 0,
588
  /* 500 */ 65296, 76, 1, 65460, 77, 1, 0,
589
  /* 507 */ 65439, 75, 1, 65462, 77, 1, 0,
590
  /* 514 */ 65506, 77, 1, 65459, 78, 1, 0,
591
  /* 521 */ 65439, 76, 1, 65461, 78, 1, 0,
592
  /* 528 */ 65297, 78, 1, 65458, 79, 1, 0,
593
  /* 535 */ 65439, 77, 1, 65460, 79, 1, 0,
594
  /* 542 */ 65507, 79, 1, 65457, 80, 1, 0,
595
  /* 549 */ 65439, 78, 1, 65459, 80, 1, 0,
596
  /* 556 */ 65045, 1, 0,
597
  /* 559 */ 65260, 1, 0,
598
  /* 562 */ 65299, 1, 0,
599
  /* 565 */ 65300, 1, 0,
600
  /* 568 */ 65301, 1, 0,
601
  /* 571 */ 65302, 1, 0,
602
  /* 574 */ 65303, 1, 0,
603
  /* 577 */ 65304, 1, 0,
604
  /* 580 */ 65305, 1, 0,
605
  /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0,
606
  /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0,
607
  /* 600 */ 65488, 13, 121, 65416, 1, 0,
608
  /* 606 */ 65489, 13, 121, 65416, 1, 0,
609
  /* 612 */ 65490, 13, 121, 65416, 1, 0,
610
  /* 618 */ 65491, 13, 121, 65416, 1, 0,
611
  /* 624 */ 65492, 13, 121, 65416, 1, 0,
612
  /* 630 */ 65493, 13, 121, 65416, 1, 0,
613
  /* 636 */ 65494, 13, 121, 65416, 1, 0,
614
  /* 642 */ 65495, 13, 121, 65416, 1, 0,
615
  /* 648 */ 65496, 13, 121, 65416, 1, 0,
616
  /* 654 */ 65497, 13, 121, 65416, 1, 0,
617
  /* 660 */ 65498, 13, 121, 65416, 1, 0,
618
  /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0,
619
  /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0,
620
  /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0,
621
  /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0,
622
  /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0,
623
  /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0,
624
  /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0,
625
  /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0,
626
  /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0,
627
  /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0,
628
  /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0,
629
  /* 765 */ 65488, 133, 65416, 1, 0,
630
  /* 770 */ 65499, 134, 65416, 1, 0,
631
  /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0,
632
  /* 783 */ 65432, 1, 0,
633
  /* 786 */ 65433, 1, 0,
634
  /* 789 */ 65434, 1, 0,
635
  /* 792 */ 65435, 1, 0,
636
  /* 795 */ 65436, 1, 0,
637
  /* 798 */ 65437, 1, 0,
638
  /* 801 */ 65464, 1, 0,
639
  /* 804 */ 65508, 1, 0,
640
  /* 807 */ 65509, 1, 0,
641
  /* 810 */ 65510, 1, 0,
642
  /* 813 */ 65511, 1, 0,
643
  /* 816 */ 65512, 1, 0,
644
  /* 819 */ 65513, 1, 0,
645
  /* 822 */ 65514, 1, 0,
646
  /* 825 */ 65515, 1, 0,
647
  /* 828 */ 65520, 1, 0,
648
  /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0,
649
  /* 839 */ 65136, 1, 3, 1, 2, 0,
650
  /* 845 */ 65326, 1, 2, 0,
651
  /* 849 */ 65080, 1, 3, 1, 2, 2, 0,
652
  /* 856 */ 65136, 1, 2, 2, 0,
653
  /* 861 */ 65080, 1, 2, 2, 2, 0,
654
  /* 867 */ 65330, 2, 2, 2, 0,
655
  /* 872 */ 65080, 1, 3, 2, 2, 0,
656
  /* 878 */ 65358, 2, 2, 0,
657
  /* 882 */ 65080, 1, 3, 1, 3, 2, 0,
658
  /* 889 */ 65136, 1, 3, 2, 0,
659
  /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0,
660
  /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0,
661
  /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0,
662
  /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0,
663
  /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0,
664
  /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0,
665
  /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0,
666
  /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0,
667
  /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0,
668
  /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0,
669
  /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0,
670
  /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0,
671
  /* 1038 */ 65344, 2, 2, 93, 2, 0,
672
  /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0,
673
  /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0,
674
  /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0,
675
  /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0,
676
  /* 1080 */ 65439, 2, 0,
677
  /* 1083 */ 65453, 2, 0,
678
  /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0,
679
  /* 1094 */ 65136, 1, 3, 1, 3, 0,
680
  /* 1100 */ 65326, 1, 3, 0,
681
  /* 1104 */ 5, 0,
682
  /* 1106 */ 140, 65486, 13, 0,
683
  /* 1110 */ 14, 0,
684
  /* 1112 */ 126, 65501, 15, 0,
685
  /* 1116 */ 10, 66, 0,
686
  /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0,
687
  /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0,
688
  /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0,
689
  /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0,
690
  /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0,
691
  /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0,
692
  /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0,
693
  /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0,
694
  /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0,
695
  /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0,
696
  /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0,
697
  /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0,
698
  /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0,
699
  /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0,
700
  /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0,
701
  /* 1359 */ 91, 0,
702
  /* 1361 */ 98, 0,
703
  /* 1363 */ 99, 0,
704
  /* 1365 */ 100, 0,
705
  /* 1367 */ 101, 0,
706
  /* 1369 */ 102, 0,
707
  /* 1371 */ 103, 0,
708
  /* 1373 */ 104, 0,
709
  /* 1375 */ 65374, 1, 1, 20, 75, 135, 0,
710
  /* 1382 */ 65374, 1, 1, 21, 74, 136, 0,
711
  /* 1389 */ 65374, 1, 1, 22, 73, 137, 0,
712
  /* 1396 */ 65374, 1, 1, 23, 72, 138, 0,
713
  /* 1403 */ 65374, 1, 1, 24, 71, 139, 0,
714
  /* 1410 */ 65374, 1, 1, 25, 70, 140, 0,
715
  /* 1417 */ 65374, 1, 1, 26, 69, 141, 0,
716
  /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0,
717
  /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0,
718
  /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0,
719
  /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0,
720
  /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0,
721
  /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0,
722
  /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0,
723
  /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0,
724
  /* 1526 */ 157, 0,
725
  /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0,
726
  /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0,
727
  /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0,
728
  /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0,
729
  /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0,
730
  /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0,
731
  /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0,
732
  /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0,
733
  /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0,
734
  /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0,
735
  /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0,
736
  /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0,
737
  /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0,
738
  /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0,
739
  /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0,
740
  /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0,
741
  /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0,
742
  /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0,
743
  /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0,
744
  /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0,
745
  /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0,
746
  /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0,
747
  /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0,
748
  /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0,
749
  /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0,
750
  /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0,
751
  /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0,
752
  /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0,
753
  /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0,
754
  /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0,
755
  /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0,
756
  /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0,
757
  /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0,
758
  /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0,
759
  /* 2455 */ 65487, 13, 121, 65416, 0,
760
  /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0,
761
  /* 2468 */ 65466, 1, 65486, 133, 65416, 0,
762
  /* 2474 */ 65487, 133, 65416, 0,
763
  /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
764
  /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
765
  /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0,
766
  /* 2509 */ 65452, 1, 65500, 134, 65417, 0,
767
  /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0,
768
  /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0,
769
  /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0,
770
  /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0,
771
  /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0,
772
  /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0,
773
  /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0,
774
  /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0,
775
  /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0,
776
  /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0,
777
  /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0,
778
  /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0,
779
  /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0,
780
  /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0,
781
  /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0,
782
  /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0,
783
  /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0,
784
  /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0,
785
  /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0,
786
  /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0,
787
  /* 2832 */ 26, 65446, 92, 65445, 0,
788
  /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0,
789
  /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0,
790
  /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0,
791
  /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0,
792
  /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
793
  /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
794
  /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0,
795
  /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0,
796
  /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
797
  /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
798
  /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0,
799
  /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0,
800
  /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
801
  /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
802
  /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0,
803
  /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0,
804
  /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
805
  /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
806
  /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
807
  /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
808
  /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0,
809
  /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
810
  /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
811
  /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
812
  /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
813
  /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0,
814
  /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
815
  /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
816
  /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
817
  /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
818
  /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
819
  /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0,
820
  /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
821
  /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
822
  /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
823
  /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
824
  /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
825
  /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0,
826
  /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
827
  /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
828
  /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
829
  /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
830
  /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
831
  /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0,
832
  /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
833
  /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
834
  /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
835
  /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
836
  /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
837
  /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0,
838
  /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
839
  /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
840
  /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
841
  /* 3839 */ 65298, 80, 1, 65456, 0,
842
  /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
843
  /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
844
  /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0,
845
  /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
846
  /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
847
  /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0,
848
  /* 3948 */ 65439, 80, 1, 65457, 0,
849
  /* 3953 */ 28, 65457, 0,
850
  /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
851
  /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
852
  /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
853
  /* 4002 */ 26, 65458, 80, 65457, 0,
854
  /* 4007 */ 65439, 79, 1, 65458, 0,
855
  /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0,
856
  /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0,
857
  /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0,
858
  /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0,
859
  /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0,
860
  /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0,
861
  /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0,
862
  /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0,
863
  /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0,
864
  /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0,
865
  /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0,
866
  /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0,
867
  /* 4114 */ 65445, 65470, 0,
868
  /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0,
869
  /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0,
870
  /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0,
871
  /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0,
872
  /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0,
873
  /* 4182 */ 65534, 0,
874
  /* 4184 */ 65535, 0,
875
};
876
877
extern const LaneBitmask ARMLaneMaskLists[] = {
878
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
879
  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
880
  /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask::getAll(),
881
  /* 8 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
882
  /* 11 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
883
  /* 16 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask::getAll(),
884
  /* 20 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask::getAll(),
885
  /* 23 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
886
  /* 28 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
887
  /* 35 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
888
  /* 39 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
889
  /* 42 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
890
  /* 48 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
891
  /* 53 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
892
  /* 57 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask::getAll(),
893
  /* 66 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000300), LaneBitmask::getAll(),
894
  /* 74 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
895
  /* 81 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
896
  /* 87 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
897
  /* 92 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask::getAll(),
898
  /* 99 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
899
  /* 105 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
900
  /* 110 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
901
  /* 114 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask::getAll(),
902
  /* 123 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
903
  /* 131 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
904
  /* 138 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
905
  /* 144 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
906
  /* 149 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask(0x00010000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
907
  /* 166 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
908
  /* 181 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
909
  /* 194 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
910
  /* 205 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
911
};
912
913
extern const uint16_t ARMSubRegIdxLists[] = {
914
  /* 0 */ 1, 2, 0,
915
  /* 3 */ 1, 17, 18, 2, 0,
916
  /* 8 */ 1, 3, 0,
917
  /* 11 */ 1, 17, 18, 3, 0,
918
  /* 16 */ 9, 10, 0,
919
  /* 19 */ 17, 18, 0,
920
  /* 22 */ 1, 17, 18, 2, 19, 20, 0,
921
  /* 29 */ 1, 17, 18, 3, 21, 22, 0,
922
  /* 36 */ 1, 2, 3, 13, 33, 37, 0,
923
  /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0,
924
  /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0,
925
  /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0,
926
  /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0,
927
  /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0,
928
  /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
929
  /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
930
  /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0,
931
  /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0,
932
  /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0,
933
  /* 188 */ 1, 3, 5, 33, 43, 0,
934
  /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0,
935
  /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0,
936
  /* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0,
937
  /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0,
938
  /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0,
939
  /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0,
940
  /* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0,
941
  /* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0,
942
  /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
943
  /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
944
  /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
945
  /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
946
  /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
947
};
948
949
extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[] = {
950
  { 65535, 65535 },
951
  { 0, 64 },  // dsub_0
952
  { 64, 64 }, // dsub_1
953
  { 128, 64 },  // dsub_2
954
  { 192, 64 },  // dsub_3
955
  { 256, 64 },  // dsub_4
956
  { 320, 64 },  // dsub_5
957
  { 384, 64 },  // dsub_6
958
  { 448, 64 },  // dsub_7
959
  { 0, 32 },  // gsub_0
960
  { 32, 32 }, // gsub_1
961
  { 0, 256 }, // qqsub_0
962
  { 256, 256 }, // qqsub_1
963
  { 0, 128 }, // qsub_0
964
  { 128, 128 }, // qsub_1
965
  { 256, 128 }, // qsub_2
966
  { 384, 128 }, // qsub_3
967
  { 0, 32 },  // ssub_0
968
  { 32, 32 }, // ssub_1
969
  { 64, 32 }, // ssub_2
970
  { 96, 32 }, // ssub_3
971
  { 128, 32 },  // ssub_4
972
  { 160, 32 },  // ssub_5
973
  { 192, 32 },  // ssub_6
974
  { 224, 32 },  // ssub_7
975
  { 256, 32 },  // ssub_8
976
  { 288, 32 },  // ssub_9
977
  { 320, 32 },  // ssub_10
978
  { 352, 32 },  // ssub_11
979
  { 384, 32 },  // ssub_12
980
  { 416, 32 },  // ssub_13
981
  { 448, 32 },  // dsub_7_then_ssub_0
982
  { 480, 32 },  // dsub_7_then_ssub_1
983
  { 65535, 128 }, // ssub_0_ssub_1_ssub_4_ssub_5
984
  { 0, 192 }, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
985
  { 65535, 128 }, // ssub_2_ssub_3_ssub_6_ssub_7
986
  { 64, 192 },  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
987
  { 64, 128 },  // ssub_2_ssub_3_ssub_4_ssub_5
988
  { 65535, 192 }, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
989
  { 65535, 256 }, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
990
  { 65535, 192 }, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
991
  { 65535, 256 }, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
992
  { 64, 256 },  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
993
  { 65535, 128 }, // ssub_4_ssub_5_ssub_8_ssub_9
994
  { 128, 192 }, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
995
  { 65535, 192 }, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
996
  { 65535, 128 }, // ssub_6_ssub_7_dsub_5
997
  { 192, 192 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
998
  { 65535, 192 }, // ssub_6_ssub_7_dsub_5_dsub_7
999
  { 192, 128 }, // ssub_6_ssub_7_ssub_8_ssub_9
1000
  { 192, 256 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
1001
  { 65535, 128 }, // ssub_8_ssub_9_ssub_12_ssub_13
1002
  { 256, 192 }, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
1003
  { 65535, 128 }, // dsub_5_dsub_7
1004
  { 320, 192 }, // dsub_5_ssub_12_ssub_13_dsub_7
1005
  { 320, 128 }, // dsub_5_ssub_12_ssub_13
1006
  { 128, 256 }, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
1007
};
1008
1009
extern const char ARMRegStrings[] = {
1010
  /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
1011
  /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
1012
  /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
1013
  /* 39 */ 'R', '1', '0', 0,
1014
  /* 43 */ 'S', '1', '0', 0,
1015
  /* 47 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
1016
  /* 63 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
1017
  /* 79 */ 'S', '2', '0', 0,
1018
  /* 83 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
1019
  /* 99 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
1020
  /* 115 */ 'S', '3', '0', 0,
1021
  /* 119 */ 'D', '0', 0,
1022
  /* 122 */ 'Q', '0', 0,
1023
  /* 125 */ 'M', 'V', 'F', 'R', '0', 0,
1024
  /* 131 */ 'S', '0', 0,
1025
  /* 134 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
1026
  /* 145 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
1027
  /* 158 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
1028
  /* 172 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
1029
  /* 180 */ 'S', '1', '1', 0,
1030
  /* 184 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
1031
  /* 196 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
1032
  /* 212 */ 'S', '2', '1', 0,
1033
  /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
1034
  /* 228 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
1035
  /* 244 */ 'S', '3', '1', 0,
1036
  /* 248 */ 'D', '1', 0,
1037
  /* 251 */ 'Q', '0', '_', 'Q', '1', 0,
1038
  /* 257 */ 'M', 'V', 'F', 'R', '1', 0,
1039
  /* 263 */ 'R', '0', '_', 'R', '1', 0,
1040
  /* 269 */ 'S', '1', 0,
1041
  /* 272 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
1042
  /* 286 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
1043
  /* 301 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
1044
  /* 316 */ 'R', '1', '2', 0,
1045
  /* 320 */ 'S', '1', '2', 0,
1046
  /* 324 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
1047
  /* 340 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
1048
  /* 356 */ 'S', '2', '2', 0,
1049
  /* 360 */ 'D', '0', '_', 'D', '2', 0,
1050
  /* 366 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
1051
  /* 375 */ 'Q', '1', '_', 'Q', '2', 0,
1052
  /* 381 */ 'M', 'V', 'F', 'R', '2', 0,
1053
  /* 387 */ 'S', '2', 0,
1054
  /* 390 */ 'F', 'P', 'I', 'N', 'S', 'T', '2', 0,
1055
  /* 398 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
1056
  /* 412 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
1057
  /* 424 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
1058
  /* 440 */ 'S', '1', '3', 0,
1059
  /* 444 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
1060
  /* 460 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
1061
  /* 472 */ 'S', '2', '3', 0,
1062
  /* 476 */ 'D', '1', '_', 'D', '3', 0,
1063
  /* 482 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
1064
  /* 491 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
1065
  /* 503 */ 'R', '2', '_', 'R', '3', 0,
1066
  /* 509 */ 'S', '3', 0,
1067
  /* 512 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
1068
  /* 527 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
1069
  /* 543 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
1070
  /* 559 */ 'S', '1', '4', 0,
1071
  /* 563 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
1072
  /* 579 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
1073
  /* 595 */ 'S', '2', '4', 0,
1074
  /* 599 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
1075
  /* 608 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
1076
  /* 620 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
1077
  /* 632 */ 'R', '4', 0,
1078
  /* 635 */ 'S', '4', 0,
1079
  /* 638 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
1080
  /* 653 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
1081
  /* 665 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
1082
  /* 681 */ 'S', '1', '5', 0,
1083
  /* 685 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
1084
  /* 701 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
1085
  /* 713 */ 'S', '2', '5', 0,
1086
  /* 717 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
1087
  /* 726 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
1088
  /* 735 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
1089
  /* 747 */ 'R', '4', '_', 'R', '5', 0,
1090
  /* 753 */ 'S', '5', 0,
1091
  /* 756 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
1092
  /* 772 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
1093
  /* 788 */ 'S', '1', '6', 0,
1094
  /* 792 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
1095
  /* 808 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
1096
  /* 824 */ 'S', '2', '6', 0,
1097
  /* 828 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
1098
  /* 840 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
1099
  /* 852 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
1100
  /* 864 */ 'R', '6', 0,
1101
  /* 867 */ 'S', '6', 0,
1102
  /* 870 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
1103
  /* 886 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
1104
  /* 898 */ 'S', '1', '7', 0,
1105
  /* 902 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
1106
  /* 918 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
1107
  /* 930 */ 'S', '2', '7', 0,
1108
  /* 934 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
1109
  /* 946 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
1110
  /* 955 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
1111
  /* 967 */ 'R', '6', '_', 'R', '7', 0,
1112
  /* 973 */ 'S', '7', 0,
1113
  /* 976 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
1114
  /* 992 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
1115
  /* 1008 */ 'S', '1', '8', 0,
1116
  /* 1012 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
1117
  /* 1028 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
1118
  /* 1044 */ 'S', '2', '8', 0,
1119
  /* 1048 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
1120
  /* 1060 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
1121
  /* 1072 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
1122
  /* 1084 */ 'R', '8', 0,
1123
  /* 1087 */ 'S', '8', 0,
1124
  /* 1090 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
1125
  /* 1106 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
1126
  /* 1118 */ 'S', '1', '9', 0,
1127
  /* 1122 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
1128
  /* 1138 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
1129
  /* 1150 */ 'S', '2', '9', 0,
1130
  /* 1154 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
1131
  /* 1166 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
1132
  /* 1175 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
1133
  /* 1187 */ 'R', '8', '_', 'R', '9', 0,
1134
  /* 1193 */ 'S', '9', 0,
1135
  /* 1196 */ 'P', 'C', 0,
1136
  /* 1199 */ 'F', 'P', 'E', 'X', 'C', 0,
1137
  /* 1205 */ 'F', 'P', 'S', 'I', 'D', 0,
1138
  /* 1211 */ 'I', 'T', 'S', 'T', 'A', 'T', 'E', 0,
1139
  /* 1219 */ 'R', '1', '2', '_', 'S', 'P', 0,
1140
  /* 1226 */ 'F', 'P', 'S', 'C', 'R', 0,
1141
  /* 1232 */ 'L', 'R', 0,
1142
  /* 1235 */ 'A', 'P', 'S', 'R', 0,
1143
  /* 1240 */ 'C', 'P', 'S', 'R', 0,
1144
  /* 1245 */ 'S', 'P', 'S', 'R', 0,
1145
  /* 1250 */ 'F', 'P', 'I', 'N', 'S', 'T', 0,
1146
  /* 1257 */ 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 0,
1147
  /* 1268 */ 'A', 'P', 'S', 'R', '_', 'N', 'Z', 'C', 'V', 0,
1148
};
1149
1150
extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors
1151
  { 12, 0, 0, 0, 0, 0 },
1152
  { 1235, 16, 16, 2, 66945, 0 },
1153
  { 1268, 16, 16, 2, 66945, 0 },
1154
  { 1240, 16, 16, 2, 66945, 0 },
1155
  { 1199, 16, 16, 2, 66945, 0 },
1156
  { 1250, 16, 16, 2, 66945, 0 },
1157
  { 1226, 16, 16, 2, 17664, 0 },
1158
  { 1257, 16, 16, 2, 17664, 0 },
1159
  { 1205, 16, 16, 2, 66913, 0 },
1160
  { 1211, 16, 16, 2, 66913, 0 },
1161
  { 1232, 16, 16, 2, 66913, 0 },
1162
  { 1196, 16, 16, 2, 66913, 0 },
1163
  { 1223, 16, 1526, 2, 66913, 0 },
1164
  { 1245, 16, 16, 2, 66913, 0 },
1165
  { 119, 350, 4013, 19, 13250, 8 },
1166
  { 248, 357, 2479, 19, 13250, 8 },
1167
  { 363, 364, 3957, 19, 13250, 8 },
1168
  { 479, 378, 3845, 19, 13250, 8 },
1169
  { 605, 392, 3893, 19, 13250, 8 },
1170
  { 723, 406, 3724, 19, 13250, 8 },
1171
  { 837, 420, 3780, 19, 13250, 8 },
1172
  { 943, 434, 3604, 19, 13250, 8 },
1173
  { 1057, 448, 3664, 19, 13250, 8 },
1174
  { 1163, 462, 3484, 19, 13250, 8 },
1175
  { 9, 476, 3544, 19, 13250, 8 },
1176
  { 141, 490, 3364, 19, 13250, 8 },
1177
  { 282, 504, 3424, 19, 13250, 8 },
1178
  { 408, 518, 3244, 19, 13250, 8 },
1179
  { 523, 532, 3304, 19, 13250, 8 },
1180
  { 649, 546, 3149, 19, 13250, 8 },
1181
  { 768, 16, 3208, 2, 17761, 0 },
1182
  { 882, 16, 3078, 2, 17761, 0 },
1183
  { 988, 16, 3113, 2, 17761, 0 },
1184
  { 1102, 16, 3008, 2, 17761, 0 },
1185
  { 59, 16, 3043, 2, 17761, 0 },
1186
  { 192, 16, 2938, 2, 17761, 0 },
1187
  { 336, 16, 2973, 2, 17761, 0 },
1188
  { 456, 16, 2868, 2, 17761, 0 },
1189
  { 575, 16, 2903, 2, 17761, 0 },
1190
  { 697, 16, 2797, 2, 17761, 0 },
1191
  { 804, 16, 2837, 2, 17761, 0 },
1192
  { 914, 16, 2363, 2, 17761, 0 },
1193
  { 1024, 16, 2411, 2, 17761, 0 },
1194
  { 1134, 16, 2384, 2, 17761, 0 },
1195
  { 95, 16, 2429, 2, 17761, 0 },
1196
  { 224, 16, 2789, 2, 17761, 0 },
1197
  { 390, 16, 16, 2, 17761, 0 },
1198
  { 125, 16, 16, 2, 17761, 0 },
1199
  { 257, 16, 16, 2, 17761, 0 },
1200
  { 381, 16, 16, 2, 17761, 0 },
1201
  { 122, 353, 1112, 22, 2196, 11 },
1202
  { 254, 374, 775, 22, 2196, 11 },
1203
  { 378, 402, 314, 22, 2196, 11 },
1204
  { 500, 430, 244, 22, 2196, 11 },
1205
  { 629, 458, 234, 22, 2196, 11 },
1206
  { 744, 486, 224, 22, 2196, 11 },
1207
  { 861, 514, 214, 22, 2196, 11 },
1208
  { 964, 542, 204, 22, 2196, 11 },
1209
  { 1081, 804, 194, 0, 12818, 20 },
1210
  { 1184, 807, 184, 0, 12818, 20 },
1211
  { 35, 810, 174, 0, 12818, 20 },
1212
  { 168, 813, 164, 0, 12818, 20 },
1213
  { 312, 816, 154, 0, 12818, 20 },
1214
  { 436, 819, 591, 0, 12818, 20 },
1215
  { 555, 822, 2447, 0, 12818, 20 },
1216
  { 677, 825, 1106, 0, 12818, 20 },
1217
  { 128, 16, 1373, 2, 66913, 0 },
1218
  { 260, 16, 1371, 2, 66913, 0 },
1219
  { 384, 16, 1371, 2, 66913, 0 },
1220
  { 506, 16, 1369, 2, 66913, 0 },
1221
  { 632, 16, 1369, 2, 66913, 0 },
1222
  { 750, 16, 1367, 2, 66913, 0 },
1223
  { 864, 16, 1367, 2, 66913, 0 },
1224
  { 970, 16, 1365, 2, 66913, 0 },
1225
  { 1084, 16, 1365, 2, 66913, 0 },
1226
  { 1190, 16, 1363, 2, 66913, 0 },
1227
  { 39, 16, 1363, 2, 66913, 0 },
1228
  { 176, 16, 1361, 2, 66913, 0 },
1229
  { 316, 16, 1359, 2, 66913, 0 },
1230
  { 131, 16, 4021, 2, 65585, 0 },
1231
  { 269, 16, 4012, 2, 65585, 0 },
1232
  { 387, 16, 2490, 2, 65585, 0 },
1233
  { 509, 16, 2478, 2, 65585, 0 },
1234
  { 635, 16, 3974, 2, 65585, 0 },
1235
  { 753, 16, 3956, 2, 65585, 0 },
1236
  { 867, 16, 3863, 2, 65585, 0 },
1237
  { 973, 16, 3844, 2, 65585, 0 },
1238
  { 1087, 16, 3914, 2, 65585, 0 },
1239
  { 1193, 16, 3892, 2, 65585, 0 },
1240
  { 43, 16, 3745, 2, 65585, 0 },
1241
  { 180, 16, 3723, 2, 65585, 0 },
1242
  { 320, 16, 3803, 2, 65585, 0 },
1243
  { 440, 16, 3779, 2, 65585, 0 },
1244
  { 559, 16, 3627, 2, 65585, 0 },
1245
  { 681, 16, 3603, 2, 65585, 0 },
1246
  { 788, 16, 3687, 2, 65585, 0 },
1247
  { 898, 16, 3663, 2, 65585, 0 },
1248
  { 1008, 16, 3507, 2, 65585, 0 },
1249
  { 1118, 16, 3483, 2, 65585, 0 },
1250
  { 79, 16, 3567, 2, 65585, 0 },
1251
  { 212, 16, 3543, 2, 65585, 0 },
1252
  { 356, 16, 3387, 2, 65585, 0 },
1253
  { 472, 16, 3363, 2, 65585, 0 },
1254
  { 595, 16, 3447, 2, 65585, 0 },
1255
  { 713, 16, 3423, 2, 65585, 0 },
1256
  { 824, 16, 3267, 2, 65585, 0 },
1257
  { 930, 16, 3243, 2, 65585, 0 },
1258
  { 1044, 16, 3327, 2, 65585, 0 },
1259
  { 1150, 16, 3303, 2, 65585, 0 },
1260
  { 115, 16, 3172, 2, 65585, 0 },
1261
  { 244, 16, 3148, 2, 65585, 0 },
1262
  { 360, 367, 4015, 29, 5426, 23 },
1263
  { 476, 381, 2502, 29, 5426, 23 },
1264
  { 602, 395, 3992, 29, 5426, 23 },
1265
  { 720, 409, 3882, 29, 5426, 23 },
1266
  { 834, 423, 3936, 29, 5426, 23 },
1267
  { 940, 437, 3767, 29, 5426, 23 },
1268
  { 1054, 451, 3827, 29, 5426, 23 },
1269
  { 1160, 465, 3651, 29, 5426, 23 },
1270
  { 6, 479, 3711, 29, 5426, 23 },
1271
  { 151, 493, 3531, 29, 5426, 23 },
1272
  { 278, 507, 3591, 29, 5426, 23 },
1273
  { 404, 521, 3411, 29, 5426, 23 },
1274
  { 519, 535, 3471, 29, 5426, 23 },
1275
  { 645, 549, 3291, 29, 5426, 23 },
1276
  { 764, 4007, 3351, 11, 17602, 35 },
1277
  { 878, 3948, 3196, 11, 13522, 35 },
1278
  { 984, 1080, 3231, 8, 17329, 39 },
1279
  { 1098, 1080, 3101, 8, 17329, 39 },
1280
  { 55, 1080, 3136, 8, 17329, 39 },
1281
  { 204, 1080, 3031, 8, 17329, 39 },
1282
  { 332, 1080, 3066, 8, 17329, 39 },
1283
  { 452, 1080, 2961, 8, 17329, 39 },
1284
  { 571, 1080, 2996, 8, 17329, 39 },
1285
  { 693, 1080, 2891, 8, 17329, 39 },
1286
  { 800, 1080, 2926, 8, 17329, 39 },
1287
  { 910, 1080, 2820, 8, 17329, 39 },
1288
  { 1020, 1080, 2858, 8, 17329, 39 },
1289
  { 1130, 1080, 2401, 8, 17329, 39 },
1290
  { 91, 1080, 2440, 8, 17329, 39 },
1291
  { 236, 1080, 2791, 8, 17329, 39 },
1292
  { 251, 1339, 1114, 168, 1044, 57 },
1293
  { 375, 1319, 347, 168, 1044, 57 },
1294
  { 497, 1299, 142, 168, 1044, 57 },
1295
  { 626, 1279, 142, 168, 1044, 57 },
1296
  { 741, 1259, 142, 168, 1044, 57 },
1297
  { 858, 1239, 142, 168, 1044, 57 },
1298
  { 961, 1219, 142, 168, 1044, 57 },
1299
  { 1078, 1203, 142, 88, 1456, 74 },
1300
  { 1181, 1191, 142, 76, 2114, 87 },
1301
  { 32, 1179, 142, 76, 2114, 87 },
1302
  { 164, 1167, 142, 76, 2114, 87 },
1303
  { 308, 1155, 142, 76, 2114, 87 },
1304
  { 432, 1143, 142, 76, 2114, 87 },
1305
  { 551, 1131, 344, 76, 2114, 87 },
1306
  { 673, 1119, 1108, 76, 2114, 87 },
1307
  { 491, 2156, 16, 474, 4, 149 },
1308
  { 620, 2101, 16, 474, 4, 149 },
1309
  { 735, 2046, 16, 474, 4, 149 },
1310
  { 852, 1991, 16, 474, 4, 149 },
1311
  { 955, 1936, 16, 474, 4, 149 },
1312
  { 1072, 1885, 16, 423, 272, 166 },
1313
  { 1175, 1838, 16, 376, 512, 181 },
1314
  { 26, 1795, 16, 333, 720, 194 },
1315
  { 158, 1756, 16, 294, 1186, 205 },
1316
  { 301, 1717, 16, 294, 1186, 205 },
1317
  { 424, 1678, 16, 294, 1186, 205 },
1318
  { 543, 1639, 16, 294, 1186, 205 },
1319
  { 665, 1600, 16, 294, 1186, 205 },
1320
  { 1219, 4114, 16, 16, 17856, 2 },
1321
  { 263, 783, 16, 16, 8946, 5 },
1322
  { 503, 786, 16, 16, 8946, 5 },
1323
  { 747, 789, 16, 16, 8946, 5 },
1324
  { 967, 792, 16, 16, 8946, 5 },
1325
  { 1187, 795, 16, 16, 8946, 5 },
1326
  { 172, 798, 16, 16, 8946, 5 },
1327
  { 366, 1513, 1113, 63, 1570, 28 },
1328
  { 482, 4169, 2511, 63, 1570, 28 },
1329
  { 611, 1500, 778, 63, 1570, 28 },
1330
  { 726, 4156, 770, 63, 1570, 28 },
1331
  { 843, 1487, 317, 63, 1570, 28 },
1332
  { 946, 4143, 660, 63, 1570, 28 },
1333
  { 1063, 1474, 308, 63, 1570, 28 },
1334
  { 1166, 4130, 654, 63, 1570, 28 },
1335
  { 16, 1461, 302, 63, 1570, 28 },
1336
  { 134, 4117, 648, 63, 1570, 28 },
1337
  { 289, 1448, 296, 63, 1570, 28 },
1338
  { 412, 4101, 642, 63, 1570, 28 },
1339
  { 531, 1435, 290, 63, 1570, 28 },
1340
  { 653, 4088, 636, 63, 1570, 28 },
1341
  { 776, 1424, 284, 52, 1680, 42 },
1342
  { 886, 4079, 630, 43, 1872, 48 },
1343
  { 996, 1417, 278, 36, 2401, 53 },
1344
  { 1106, 4072, 624, 36, 2401, 53 },
1345
  { 67, 1410, 272, 36, 2401, 53 },
1346
  { 184, 4065, 618, 36, 2401, 53 },
1347
  { 344, 1403, 266, 36, 2401, 53 },
1348
  { 460, 4058, 612, 36, 2401, 53 },
1349
  { 583, 1396, 260, 36, 2401, 53 },
1350
  { 701, 4051, 606, 36, 2401, 53 },
1351
  { 812, 1389, 254, 36, 2401, 53 },
1352
  { 918, 4044, 600, 36, 2401, 53 },
1353
  { 1032, 1382, 765, 36, 2401, 53 },
1354
  { 1138, 4037, 2455, 36, 2401, 53 },
1355
  { 103, 1375, 2474, 36, 2401, 53 },
1356
  { 216, 4030, 1107, 36, 2401, 53 },
1357
  { 599, 1026, 4018, 212, 5314, 92 },
1358
  { 717, 1014, 3953, 212, 5314, 92 },
1359
  { 831, 1002, 4002, 212, 5314, 92 },
1360
  { 937, 990, 3909, 212, 5314, 92 },
1361
  { 1051, 978, 3909, 212, 5314, 92 },
1362
  { 1157, 966, 3798, 212, 5314, 92 },
1363
  { 3, 954, 3798, 212, 5314, 92 },
1364
  { 148, 942, 3682, 212, 5314, 92 },
1365
  { 275, 930, 3682, 212, 5314, 92 },
1366
  { 401, 918, 3562, 212, 5314, 92 },
1367
  { 515, 906, 3562, 212, 5314, 92 },
1368
  { 641, 894, 3442, 212, 5314, 92 },
1369
  { 760, 1070, 3442, 202, 17506, 99 },
1370
  { 874, 1060, 3322, 202, 13426, 99 },
1371
  { 980, 1052, 3322, 194, 14226, 105 },
1372
  { 1094, 1044, 3226, 194, 13698, 105 },
1373
  { 51, 1038, 3226, 188, 14049, 110 },
1374
  { 200, 1038, 3131, 188, 14049, 110 },
1375
  { 328, 1038, 3131, 188, 14049, 110 },
1376
  { 448, 1038, 3061, 188, 14049, 110 },
1377
  { 567, 1038, 3061, 188, 14049, 110 },
1378
  { 689, 1038, 2991, 188, 14049, 110 },
1379
  { 796, 1038, 2991, 188, 14049, 110 },
1380
  { 906, 1038, 2921, 188, 14049, 110 },
1381
  { 1016, 1038, 2921, 188, 14049, 110 },
1382
  { 1126, 1038, 2832, 188, 14049, 110 },
1383
  { 87, 1038, 2855, 188, 14049, 110 },
1384
  { 232, 1038, 2794, 188, 14049, 110 },
1385
  { 828, 2677, 4010, 276, 5170, 114 },
1386
  { 934, 2659, 3951, 276, 5170, 114 },
1387
  { 1048, 2641, 3951, 276, 5170, 114 },
1388
  { 1154, 2623, 3842, 276, 5170, 114 },
1389
  { 0, 2605, 3842, 276, 5170, 114 },
1390
  { 145, 2587, 3743, 276, 5170, 114 },
1391
  { 272, 2569, 3743, 276, 5170, 114 },
1392
  { 398, 2551, 3625, 276, 5170, 114 },
1393
  { 512, 2533, 3625, 276, 5170, 114 },
1394
  { 638, 2515, 3505, 276, 5170, 114 },
1395
  { 756, 2773, 3505, 260, 17378, 123 },
1396
  { 870, 2757, 3385, 260, 13298, 123 },
1397
  { 976, 2743, 3385, 246, 14114, 131 },
1398
  { 1090, 2729, 3265, 246, 13586, 131 },
1399
  { 47, 2717, 3265, 234, 13954, 138 },
1400
  { 196, 2705, 3170, 234, 13778, 138 },
1401
  { 324, 2695, 3170, 224, 13873, 144 },
1402
  { 444, 2695, 3099, 224, 13873, 144 },
1403
  { 563, 2695, 3099, 224, 13873, 144 },
1404
  { 685, 2695, 3029, 224, 13873, 144 },
1405
  { 792, 2695, 3029, 224, 13873, 144 },
1406
  { 902, 2695, 2959, 224, 13873, 144 },
1407
  { 1012, 2695, 2959, 224, 13873, 144 },
1408
  { 1122, 2695, 2856, 224, 13873, 144 },
1409
  { 83, 2695, 2856, 224, 13873, 144 },
1410
  { 228, 2695, 2795, 224, 13873, 144 },
1411
  { 369, 360, 2509, 22, 1956, 11 },
1412
  { 614, 388, 583, 22, 1956, 11 },
1413
  { 846, 416, 756, 22, 1956, 11 },
1414
  { 1066, 444, 747, 22, 1956, 11 },
1415
  { 19, 472, 738, 22, 1956, 11 },
1416
  { 293, 500, 729, 22, 1956, 11 },
1417
  { 535, 528, 720, 22, 1956, 11 },
1418
  { 780, 3839, 711, 3, 2336, 16 },
1419
  { 1000, 562, 702, 0, 8898, 20 },
1420
  { 71, 565, 693, 0, 8898, 20 },
1421
  { 348, 568, 684, 0, 8898, 20 },
1422
  { 587, 571, 675, 0, 8898, 20 },
1423
  { 816, 574, 666, 0, 8898, 20 },
1424
  { 1036, 577, 2460, 0, 8898, 20 },
1425
  { 107, 580, 2468, 0, 8898, 20 },
1426
  { 608, 2343, 2488, 148, 900, 57 },
1427
  { 840, 2323, 588, 148, 900, 57 },
1428
  { 1060, 2303, 588, 148, 900, 57 },
1429
  { 13, 2283, 588, 148, 900, 57 },
1430
  { 286, 2263, 588, 148, 900, 57 },
1431
  { 527, 2243, 588, 148, 900, 57 },
1432
  { 772, 2225, 588, 130, 1328, 66 },
1433
  { 992, 2211, 588, 116, 1776, 81 },
1434
  { 63, 1588, 588, 104, 2034, 87 },
1435
  { 340, 1576, 588, 104, 2034, 87 },
1436
  { 579, 1564, 588, 104, 2034, 87 },
1437
  { 808, 1552, 588, 104, 2034, 87 },
1438
  { 1028, 1540, 588, 104, 2034, 87 },
1439
  { 99, 1528, 2382, 104, 2034, 87 },
1440
};
1441
1442
extern const MCPhysReg ARMRegUnitRoots[][2] = {
1443
  { ARM::APSR },
1444
  { ARM::APSR_NZCV },
1445
  { ARM::CPSR },
1446
  { ARM::FPEXC },
1447
  { ARM::FPINST },
1448
  { ARM::FPSCR, ARM::FPSCR_NZCV },
1449
  { ARM::FPSID },
1450
  { ARM::ITSTATE },
1451
  { ARM::LR },
1452
  { ARM::PC },
1453
  { ARM::SP },
1454
  { ARM::SPSR },
1455
  { ARM::S0 },
1456
  { ARM::S1 },
1457
  { ARM::S2 },
1458
  { ARM::S3 },
1459
  { ARM::S4 },
1460
  { ARM::S5 },
1461
  { ARM::S6 },
1462
  { ARM::S7 },
1463
  { ARM::S8 },
1464
  { ARM::S9 },
1465
  { ARM::S10 },
1466
  { ARM::S11 },
1467
  { ARM::S12 },
1468
  { ARM::S13 },
1469
  { ARM::S14 },
1470
  { ARM::S15 },
1471
  { ARM::S16 },
1472
  { ARM::S17 },
1473
  { ARM::S18 },
1474
  { ARM::S19 },
1475
  { ARM::S20 },
1476
  { ARM::S21 },
1477
  { ARM::S22 },
1478
  { ARM::S23 },
1479
  { ARM::S24 },
1480
  { ARM::S25 },
1481
  { ARM::S26 },
1482
  { ARM::S27 },
1483
  { ARM::S28 },
1484
  { ARM::S29 },
1485
  { ARM::S30 },
1486
  { ARM::S31 },
1487
  { ARM::D16 },
1488
  { ARM::D17 },
1489
  { ARM::D18 },
1490
  { ARM::D19 },
1491
  { ARM::D20 },
1492
  { ARM::D21 },
1493
  { ARM::D22 },
1494
  { ARM::D23 },
1495
  { ARM::D24 },
1496
  { ARM::D25 },
1497
  { ARM::D26 },
1498
  { ARM::D27 },
1499
  { ARM::D28 },
1500
  { ARM::D29 },
1501
  { ARM::D30 },
1502
  { ARM::D31 },
1503
  { ARM::FPINST2 },
1504
  { ARM::MVFR0 },
1505
  { ARM::MVFR1 },
1506
  { ARM::MVFR2 },
1507
  { ARM::R0 },
1508
  { ARM::R1 },
1509
  { ARM::R2 },
1510
  { ARM::R3 },
1511
  { ARM::R4 },
1512
  { ARM::R5 },
1513
  { ARM::R6 },
1514
  { ARM::R7 },
1515
  { ARM::R8 },
1516
  { ARM::R9 },
1517
  { ARM::R10 },
1518
  { ARM::R11 },
1519
  { ARM::R12 },
1520
};
1521
1522
namespace {     // Register classes...
1523
  // HPR Register Class...
1524
  const MCPhysReg HPR[] = {
1525
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, 
1526
  };
1527
1528
  // HPR Bit set.
1529
  const uint8_t HPRBits[] = {
1530
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
1531
  };
1532
1533
  // SPR Register Class...
1534
  const MCPhysReg SPR[] = {
1535
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, 
1536
  };
1537
1538
  // SPR Bit set.
1539
  const uint8_t SPRBits[] = {
1540
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
1541
  };
1542
1543
  // GPR Register Class...
1544
  const MCPhysReg GPR[] = {
1545
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
1546
  };
1547
1548
  // GPR Bit set.
1549
  const uint8_t GPRBits[] = {
1550
    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1551
  };
1552
1553
  // GPRwithAPSR Register Class...
1554
  const MCPhysReg GPRwithAPSR[] = {
1555
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV, 
1556
  };
1557
1558
  // GPRwithAPSR Bit set.
1559
  const uint8_t GPRwithAPSRBits[] = {
1560
    0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1561
  };
1562
1563
  // SPR_8 Register Class...
1564
  const MCPhysReg SPR_8[] = {
1565
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, 
1566
  };
1567
1568
  // SPR_8 Bit set.
1569
  const uint8_t SPR_8Bits[] = {
1570
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
1571
  };
1572
1573
  // GPRnopc Register Class...
1574
  const MCPhysReg GPRnopc[] = {
1575
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
1576
  };
1577
1578
  // GPRnopc Bit set.
1579
  const uint8_t GPRnopcBits[] = {
1580
    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1581
  };
1582
1583
  // rGPR Register Class...
1584
  const MCPhysReg rGPR[] = {
1585
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
1586
  };
1587
1588
  // rGPR Bit set.
1589
  const uint8_t rGPRBits[] = {
1590
    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
1591
  };
1592
1593
  // tGPRwithpc Register Class...
1594
  const MCPhysReg tGPRwithpc[] = {
1595
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC, 
1596
  };
1597
1598
  // tGPRwithpc Bit set.
1599
  const uint8_t tGPRwithpcBits[] = {
1600
    0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1601
  };
1602
1603
  // hGPR Register Class...
1604
  const MCPhysReg hGPR[] = {
1605
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
1606
  };
1607
1608
  // hGPR Bit set.
1609
  const uint8_t hGPRBits[] = {
1610
    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
1611
  };
1612
1613
  // tGPR Register Class...
1614
  const MCPhysReg tGPR[] = {
1615
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, 
1616
  };
1617
1618
  // tGPR Bit set.
1619
  const uint8_t tGPRBits[] = {
1620
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1621
  };
1622
1623
  // GPRnopc_and_hGPR Register Class...
1624
  const MCPhysReg GPRnopc_and_hGPR[] = {
1625
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
1626
  };
1627
1628
  // GPRnopc_and_hGPR Bit set.
1629
  const uint8_t GPRnopc_and_hGPRBits[] = {
1630
    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
1631
  };
1632
1633
  // hGPR_and_rGPR Register Class...
1634
  const MCPhysReg hGPR_and_rGPR[] = {
1635
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
1636
  };
1637
1638
  // hGPR_and_rGPR Bit set.
1639
  const uint8_t hGPR_and_rGPRBits[] = {
1640
    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
1641
  };
1642
1643
  // tcGPR Register Class...
1644
  const MCPhysReg tcGPR[] = {
1645
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, 
1646
  };
1647
1648
  // tcGPR Bit set.
1649
  const uint8_t tcGPRBits[] = {
1650
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40, 
1651
  };
1652
1653
  // tGPR_and_tcGPR Register Class...
1654
  const MCPhysReg tGPR_and_tcGPR[] = {
1655
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, 
1656
  };
1657
1658
  // tGPR_and_tcGPR Bit set.
1659
  const uint8_t tGPR_and_tcGPRBits[] = {
1660
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
1661
  };
1662
1663
  // CCR Register Class...
1664
  const MCPhysReg CCR[] = {
1665
    ARM::CPSR, 
1666
  };
1667
1668
  // CCR Bit set.
1669
  const uint8_t CCRBits[] = {
1670
    0x08, 
1671
  };
1672
1673
  // GPRsp Register Class...
1674
  const MCPhysReg GPRsp[] = {
1675
    ARM::SP, 
1676
  };
1677
1678
  // GPRsp Bit set.
1679
  const uint8_t GPRspBits[] = {
1680
    0x00, 0x10, 
1681
  };
1682
1683
  // hGPR_and_tGPRwithpc Register Class...
1684
  const MCPhysReg hGPR_and_tGPRwithpc[] = {
1685
    ARM::PC, 
1686
  };
1687
1688
  // hGPR_and_tGPRwithpc Bit set.
1689
  const uint8_t hGPR_and_tGPRwithpcBits[] = {
1690
    0x00, 0x08, 
1691
  };
1692
1693
  // hGPR_and_tcGPR Register Class...
1694
  const MCPhysReg hGPR_and_tcGPR[] = {
1695
    ARM::R12, 
1696
  };
1697
1698
  // hGPR_and_tcGPR Bit set.
1699
  const uint8_t hGPR_and_tcGPRBits[] = {
1700
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
1701
  };
1702
1703
  // DPR Register Class...
1704
  const MCPhysReg DPR[] = {
1705
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 
1706
  };
1707
1708
  // DPR Bit set.
1709
  const uint8_t DPRBits[] = {
1710
    0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
1711
  };
1712
1713
  // DPR_VFP2 Register Class...
1714
  const MCPhysReg DPR_VFP2[] = {
1715
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, 
1716
  };
1717
1718
  // DPR_VFP2 Bit set.
1719
  const uint8_t DPR_VFP2Bits[] = {
1720
    0x00, 0xc0, 0xff, 0x3f, 
1721
  };
1722
1723
  // DPR_8 Register Class...
1724
  const MCPhysReg DPR_8[] = {
1725
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, 
1726
  };
1727
1728
  // DPR_8 Bit set.
1729
  const uint8_t DPR_8Bits[] = {
1730
    0x00, 0xc0, 0x3f, 
1731
  };
1732
1733
  // GPRPair Register Class...
1734
  const MCPhysReg GPRPair[] = {
1735
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
1736
  };
1737
1738
  // GPRPair Bit set.
1739
  const uint8_t GPRPairBits[] = {
1740
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 
1741
  };
1742
1743
  // GPRPair_with_gsub_1_in_rGPR Register Class...
1744
  const MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = {
1745
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, 
1746
  };
1747
1748
  // GPRPair_with_gsub_1_in_rGPR Bit set.
1749
  const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = {
1750
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 
1751
  };
1752
1753
  // GPRPair_with_gsub_0_in_tGPR Register Class...
1754
  const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
1755
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 
1756
  };
1757
1758
  // GPRPair_with_gsub_0_in_tGPR Bit set.
1759
  const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
1760
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
1761
  };
1762
1763
  // GPRPair_with_gsub_0_in_hGPR Register Class...
1764
  const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
1765
    ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
1766
  };
1767
1768
  // GPRPair_with_gsub_0_in_hGPR Bit set.
1769
  const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
1770
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 
1771
  };
1772
1773
  // GPRPair_with_gsub_0_in_tcGPR Register Class...
1774
  const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
1775
    ARM::R0_R1, ARM::R2_R3, ARM::R12_SP, 
1776
  };
1777
1778
  // GPRPair_with_gsub_0_in_tcGPR Bit set.
1779
  const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
1780
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 
1781
  };
1782
1783
  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class...
1784
  const MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = {
1785
    ARM::R8_R9, ARM::R10_R11, 
1786
  };
1787
1788
  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set.
1789
  const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = {
1790
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 
1791
  };
1792
1793
  // GPRPair_with_gsub_1_in_tcGPR Register Class...
1794
  const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
1795
    ARM::R0_R1, ARM::R2_R3, 
1796
  };
1797
1798
  // GPRPair_with_gsub_1_in_tcGPR Bit set.
1799
  const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
1800
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 
1801
  };
1802
1803
  // GPRPair_with_gsub_1_in_GPRsp Register Class...
1804
  const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
1805
    ARM::R12_SP, 
1806
  };
1807
1808
  // GPRPair_with_gsub_1_in_GPRsp Bit set.
1809
  const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
1810
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
1811
  };
1812
1813
  // DPairSpc Register Class...
1814
  const MCPhysReg DPairSpc[] = {
1815
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31, 
1816
  };
1817
1818
  // DPairSpc Bit set.
1819
  const uint8_t DPairSpcBits[] = {
1820
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 
1821
  };
1822
1823
  // DPairSpc_with_ssub_0 Register Class...
1824
  const MCPhysReg DPairSpc_with_ssub_0[] = {
1825
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 
1826
  };
1827
1828
  // DPairSpc_with_ssub_0 Bit set.
1829
  const uint8_t DPairSpc_with_ssub_0Bits[] = {
1830
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
1831
  };
1832
1833
  // DPairSpc_with_ssub_4 Register Class...
1834
  const MCPhysReg DPairSpc_with_ssub_4[] = {
1835
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, 
1836
  };
1837
1838
  // DPairSpc_with_ssub_4 Bit set.
1839
  const uint8_t DPairSpc_with_ssub_4Bits[] = {
1840
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 
1841
  };
1842
1843
  // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
1844
  const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
1845
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 
1846
  };
1847
1848
  // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
1849
  const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
1850
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
1851
  };
1852
1853
  // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
1854
  const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
1855
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, 
1856
  };
1857
1858
  // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
1859
  const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
1860
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 
1861
  };
1862
1863
  // DPair Register Class...
1864
  const MCPhysReg DPair[] = {
1865
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15, 
1866
  };
1867
1868
  // DPair Bit set.
1869
  const uint8_t DPairBits[] = {
1870
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
1871
  };
1872
1873
  // DPair_with_ssub_0 Register Class...
1874
  const MCPhysReg DPair_with_ssub_0[] = {
1875
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, 
1876
  };
1877
1878
  // DPair_with_ssub_0 Bit set.
1879
  const uint8_t DPair_with_ssub_0Bits[] = {
1880
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
1881
  };
1882
1883
  // QPR Register Class...
1884
  const MCPhysReg QPR[] = {
1885
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 
1886
  };
1887
1888
  // QPR Bit set.
1889
  const uint8_t QPRBits[] = {
1890
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
1891
  };
1892
1893
  // DPair_with_ssub_2 Register Class...
1894
  const MCPhysReg DPair_with_ssub_2[] = {
1895
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, 
1896
  };
1897
1898
  // DPair_with_ssub_2 Bit set.
1899
  const uint8_t DPair_with_ssub_2Bits[] = {
1900
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
1901
  };
1902
1903
  // DPair_with_dsub_0_in_DPR_8 Register Class...
1904
  const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
1905
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, 
1906
  };
1907
1908
  // DPair_with_dsub_0_in_DPR_8 Bit set.
1909
  const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
1910
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
1911
  };
1912
1913
  // QPR_VFP2 Register Class...
1914
  const MCPhysReg QPR_VFP2[] = {
1915
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 
1916
  };
1917
1918
  // QPR_VFP2 Bit set.
1919
  const uint8_t QPR_VFP2Bits[] = {
1920
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1921
  };
1922
1923
  // DPair_with_dsub_1_in_DPR_8 Register Class...
1924
  const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
1925
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, 
1926
  };
1927
1928
  // DPair_with_dsub_1_in_DPR_8 Bit set.
1929
  const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
1930
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
1931
  };
1932
1933
  // QPR_8 Register Class...
1934
  const MCPhysReg QPR_8[] = {
1935
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 
1936
  };
1937
1938
  // QPR_8 Bit set.
1939
  const uint8_t QPR_8Bits[] = {
1940
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
1941
  };
1942
1943
  // DTriple Register Class...
1944
  const MCPhysReg DTriple[] = {
1945
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31, 
1946
  };
1947
1948
  // DTriple Bit set.
1949
  const uint8_t DTripleBits[] = {
1950
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, 
1951
  };
1952
1953
  // DTripleSpc Register Class...
1954
  const MCPhysReg DTripleSpc[] = {
1955
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
1956
  };
1957
1958
  // DTripleSpc Bit set.
1959
  const uint8_t DTripleSpcBits[] = {
1960
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
1961
  };
1962
1963
  // DTripleSpc_with_ssub_0 Register Class...
1964
  const MCPhysReg DTripleSpc_with_ssub_0[] = {
1965
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
1966
  };
1967
1968
  // DTripleSpc_with_ssub_0 Bit set.
1969
  const uint8_t DTripleSpc_with_ssub_0Bits[] = {
1970
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
1971
  };
1972
1973
  // DTriple_with_ssub_0 Register Class...
1974
  const MCPhysReg DTriple_with_ssub_0[] = {
1975
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, 
1976
  };
1977
1978
  // DTriple_with_ssub_0 Bit set.
1979
  const uint8_t DTriple_with_ssub_0Bits[] = {
1980
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
1981
  };
1982
1983
  // DTriple_with_qsub_0_in_QPR Register Class...
1984
  const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
1985
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30, 
1986
  };
1987
1988
  // DTriple_with_qsub_0_in_QPR Bit set.
1989
  const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
1990
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, 
1991
  };
1992
1993
  // DTriple_with_ssub_2 Register Class...
1994
  const MCPhysReg DTriple_with_ssub_2[] = {
1995
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, 
1996
  };
1997
1998
  // DTriple_with_ssub_2 Bit set.
1999
  const uint8_t DTriple_with_ssub_2Bits[] = {
2000
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 
2001
  };
2002
2003
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2004
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2005
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31, 
2006
  };
2007
2008
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2009
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2010
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a, 
2011
  };
2012
2013
  // DTripleSpc_with_ssub_4 Register Class...
2014
  const MCPhysReg DTripleSpc_with_ssub_4[] = {
2015
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
2016
  };
2017
2018
  // DTripleSpc_with_ssub_4 Bit set.
2019
  const uint8_t DTripleSpc_with_ssub_4Bits[] = {
2020
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
2021
  };
2022
2023
  // DTriple_with_ssub_4 Register Class...
2024
  const MCPhysReg DTriple_with_ssub_4[] = {
2025
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, 
2026
  };
2027
2028
  // DTriple_with_ssub_4 Bit set.
2029
  const uint8_t DTriple_with_ssub_4Bits[] = {
2030
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, 
2031
  };
2032
2033
  // DTripleSpc_with_ssub_8 Register Class...
2034
  const MCPhysReg DTripleSpc_with_ssub_8[] = {
2035
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
2036
  };
2037
2038
  // DTripleSpc_with_ssub_8 Bit set.
2039
  const uint8_t DTripleSpc_with_ssub_8Bits[] = {
2040
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
2041
  };
2042
2043
  // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
2044
  const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
2045
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
2046
  };
2047
2048
  // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
2049
  const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
2050
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2051
  };
2052
2053
  // DTriple_with_dsub_0_in_DPR_8 Register Class...
2054
  const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
2055
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, 
2056
  };
2057
2058
  // DTriple_with_dsub_0_in_DPR_8 Bit set.
2059
  const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
2060
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 
2061
  };
2062
2063
  // DTriple_with_qsub_0_in_QPR_VFP2 Register Class...
2064
  const MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = {
2065
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, 
2066
  };
2067
2068
  // DTriple_with_qsub_0_in_QPR_VFP2 Bit set.
2069
  const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = {
2070
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 
2071
  };
2072
2073
  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2074
  const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2075
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, 
2076
  };
2077
2078
  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2079
  const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2080
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 
2081
  };
2082
2083
  // DTriple_with_dsub_1_in_DPR_8 Register Class...
2084
  const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
2085
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, 
2086
  };
2087
2088
  // DTriple_with_dsub_1_in_DPR_8 Bit set.
2089
  const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
2090
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
2091
  };
2092
2093
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
2094
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
2095
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, 
2096
  };
2097
2098
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
2099
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
2100
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, 
2101
  };
2102
2103
  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Register Class...
2104
  const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR[] = {
2105
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, 
2106
  };
2107
2108
  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Bit set.
2109
  const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits[] = {
2110
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 
2111
  };
2112
2113
  // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
2114
  const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
2115
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
2116
  };
2117
2118
  // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
2119
  const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
2120
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
2121
  };
2122
2123
  // DTriple_with_dsub_2_in_DPR_8 Register Class...
2124
  const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
2125
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, 
2126
  };
2127
2128
  // DTriple_with_dsub_2_in_DPR_8 Bit set.
2129
  const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
2130
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 
2131
  };
2132
2133
  // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
2134
  const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
2135
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
2136
  };
2137
2138
  // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
2139
  const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
2140
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
2141
  };
2142
2143
  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2144
  const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2145
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, 
2146
  };
2147
2148
  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2149
  const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2150
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 
2151
  };
2152
2153
  // DTriple_with_qsub_0_in_QPR_8 Register Class...
2154
  const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
2155
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, 
2156
  };
2157
2158
  // DTriple_with_qsub_0_in_QPR_8 Bit set.
2159
  const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
2160
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 
2161
  };
2162
2163
  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class...
2164
  const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = {
2165
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, 
2166
  };
2167
2168
  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set.
2169
  const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = {
2170
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 
2171
  };
2172
2173
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
2174
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2175
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, 
2176
  };
2177
2178
  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
2179
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
2180
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 
2181
  };
2182
2183
  // DQuadSpc Register Class...
2184
  const MCPhysReg DQuadSpc[] = {
2185
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
2186
  };
2187
2188
  // DQuadSpc Bit set.
2189
  const uint8_t DQuadSpcBits[] = {
2190
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
2191
  };
2192
2193
  // DQuadSpc_with_ssub_0 Register Class...
2194
  const MCPhysReg DQuadSpc_with_ssub_0[] = {
2195
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
2196
  };
2197
2198
  // DQuadSpc_with_ssub_0 Bit set.
2199
  const uint8_t DQuadSpc_with_ssub_0Bits[] = {
2200
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
2201
  };
2202
2203
  // DQuadSpc_with_ssub_4 Register Class...
2204
  const MCPhysReg DQuadSpc_with_ssub_4[] = {
2205
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
2206
  };
2207
2208
  // DQuadSpc_with_ssub_4 Bit set.
2209
  const uint8_t DQuadSpc_with_ssub_4Bits[] = {
2210
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
2211
  };
2212
2213
  // DQuadSpc_with_ssub_8 Register Class...
2214
  const MCPhysReg DQuadSpc_with_ssub_8[] = {
2215
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
2216
  };
2217
2218
  // DQuadSpc_with_ssub_8 Bit set.
2219
  const uint8_t DQuadSpc_with_ssub_8Bits[] = {
2220
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
2221
  };
2222
2223
  // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
2224
  const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
2225
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
2226
  };
2227
2228
  // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
2229
  const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
2230
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2231
  };
2232
2233
  // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
2234
  const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
2235
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
2236
  };
2237
2238
  // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
2239
  const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
2240
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
2241
  };
2242
2243
  // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
2244
  const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
2245
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
2246
  };
2247
2248
  // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
2249
  const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
2250
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
2251
  };
2252
2253
  // DQuad Register Class...
2254
  const MCPhysReg DQuad[] = {
2255
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15, 
2256
  };
2257
2258
  // DQuad Bit set.
2259
  const uint8_t DQuadBits[] = {
2260
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
2261
  };
2262
2263
  // DQuad_with_ssub_0 Register Class...
2264
  const MCPhysReg DQuad_with_ssub_0[] = {
2265
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, 
2266
  };
2267
2268
  // DQuad_with_ssub_0 Bit set.
2269
  const uint8_t DQuad_with_ssub_0Bits[] = {
2270
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
2271
  };
2272
2273
  // DQuad_with_ssub_2 Register Class...
2274
  const MCPhysReg DQuad_with_ssub_2[] = {
2275
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, 
2276
  };
2277
2278
  // DQuad_with_ssub_2 Bit set.
2279
  const uint8_t DQuad_with_ssub_2Bits[] = {
2280
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
2281
  };
2282
2283
  // QQPR Register Class...
2284
  const MCPhysReg QQPR[] = {
2285
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, 
2286
  };
2287
2288
  // QQPR Bit set.
2289
  const uint8_t QQPRBits[] = {
2290
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
2291
  };
2292
2293
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2294
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2295
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30, 
2296
  };
2297
2298
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2299
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2300
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
2301
  };
2302
2303
  // DQuad_with_ssub_4 Register Class...
2304
  const MCPhysReg DQuad_with_ssub_4[] = {
2305
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, 
2306
  };
2307
2308
  // DQuad_with_ssub_4 Bit set.
2309
  const uint8_t DQuad_with_ssub_4Bits[] = {
2310
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
2311
  };
2312
2313
  // DQuad_with_ssub_6 Register Class...
2314
  const MCPhysReg DQuad_with_ssub_6[] = {
2315
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, 
2316
  };
2317
2318
  // DQuad_with_ssub_6 Bit set.
2319
  const uint8_t DQuad_with_ssub_6Bits[] = {
2320
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
2321
  };
2322
2323
  // DQuad_with_dsub_0_in_DPR_8 Register Class...
2324
  const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
2325
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, 
2326
  };
2327
2328
  // DQuad_with_dsub_0_in_DPR_8 Bit set.
2329
  const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
2330
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
2331
  };
2332
2333
  // DQuad_with_qsub_0_in_QPR_VFP2 Register Class...
2334
  const MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = {
2335
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, 
2336
  };
2337
2338
  // DQuad_with_qsub_0_in_QPR_VFP2 Bit set.
2339
  const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = {
2340
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2341
  };
2342
2343
  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2344
  const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2345
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, 
2346
  };
2347
2348
  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2349
  const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2350
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
2351
  };
2352
2353
  // DQuad_with_dsub_1_in_DPR_8 Register Class...
2354
  const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
2355
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, 
2356
  };
2357
2358
  // DQuad_with_dsub_1_in_DPR_8 Bit set.
2359
  const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
2360
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
2361
  };
2362
2363
  // DQuad_with_qsub_1_in_QPR_VFP2 Register Class...
2364
  const MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = {
2365
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, 
2366
  };
2367
2368
  // DQuad_with_qsub_1_in_QPR_VFP2 Bit set.
2369
  const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = {
2370
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
2371
  };
2372
2373
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
2374
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
2375
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, 
2376
  };
2377
2378
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
2379
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
2380
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
2381
  };
2382
2383
  // DQuad_with_dsub_2_in_DPR_8 Register Class...
2384
  const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
2385
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, 
2386
  };
2387
2388
  // DQuad_with_dsub_2_in_DPR_8 Bit set.
2389
  const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
2390
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
2391
  };
2392
2393
  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2394
  const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2395
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, 
2396
  };
2397
2398
  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2399
  const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2400
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
2401
  };
2402
2403
  // DQuad_with_dsub_3_in_DPR_8 Register Class...
2404
  const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
2405
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, 
2406
  };
2407
2408
  // DQuad_with_dsub_3_in_DPR_8 Bit set.
2409
  const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
2410
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
2411
  };
2412
2413
  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2414
  const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2415
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, 
2416
  };
2417
2418
  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2419
  const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2420
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
2421
  };
2422
2423
  // DQuad_with_qsub_0_in_QPR_8 Register Class...
2424
  const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
2425
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 
2426
  };
2427
2428
  // DQuad_with_qsub_0_in_QPR_8 Bit set.
2429
  const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
2430
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
2431
  };
2432
2433
  // DQuad_with_qsub_1_in_QPR_8 Register Class...
2434
  const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
2435
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, 
2436
  };
2437
2438
  // DQuad_with_qsub_1_in_QPR_8 Bit set.
2439
  const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
2440
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 
2441
  };
2442
2443
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
2444
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2445
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, 
2446
  };
2447
2448
  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
2449
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
2450
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
2451
  };
2452
2453
  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2454
  const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2455
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, 
2456
  };
2457
2458
  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2459
  const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2460
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
2461
  };
2462
2463
  // QQQQPR Register Class...
2464
  const MCPhysReg QQQQPR[] = {
2465
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, 
2466
  };
2467
2468
  // QQQQPR Bit set.
2469
  const uint8_t QQQQPRBits[] = {
2470
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 
2471
  };
2472
2473
  // QQQQPR_with_ssub_0 Register Class...
2474
  const MCPhysReg QQQQPR_with_ssub_0[] = {
2475
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, 
2476
  };
2477
2478
  // QQQQPR_with_ssub_0 Bit set.
2479
  const uint8_t QQQQPR_with_ssub_0Bits[] = {
2480
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
2481
  };
2482
2483
  // QQQQPR_with_ssub_4 Register Class...
2484
  const MCPhysReg QQQQPR_with_ssub_4[] = {
2485
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, 
2486
  };
2487
2488
  // QQQQPR_with_ssub_4 Bit set.
2489
  const uint8_t QQQQPR_with_ssub_4Bits[] = {
2490
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
2491
  };
2492
2493
  // QQQQPR_with_ssub_8 Register Class...
2494
  const MCPhysReg QQQQPR_with_ssub_8[] = {
2495
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, 
2496
  };
2497
2498
  // QQQQPR_with_ssub_8 Bit set.
2499
  const uint8_t QQQQPR_with_ssub_8Bits[] = {
2500
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 
2501
  };
2502
2503
  // QQQQPR_with_ssub_12 Register Class...
2504
  const MCPhysReg QQQQPR_with_ssub_12[] = {
2505
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, 
2506
  };
2507
2508
  // QQQQPR_with_ssub_12 Bit set.
2509
  const uint8_t QQQQPR_with_ssub_12Bits[] = {
2510
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 
2511
  };
2512
2513
  // QQQQPR_with_dsub_0_in_DPR_8 Register Class...
2514
  const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = {
2515
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, 
2516
  };
2517
2518
  // QQQQPR_with_dsub_0_in_DPR_8 Bit set.
2519
  const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = {
2520
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
2521
  };
2522
2523
  // QQQQPR_with_dsub_2_in_DPR_8 Register Class...
2524
  const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = {
2525
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 
2526
  };
2527
2528
  // QQQQPR_with_dsub_2_in_DPR_8 Bit set.
2529
  const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = {
2530
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
2531
  };
2532
2533
  // QQQQPR_with_dsub_4_in_DPR_8 Register Class...
2534
  const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = {
2535
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, 
2536
  };
2537
2538
  // QQQQPR_with_dsub_4_in_DPR_8 Bit set.
2539
  const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = {
2540
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
2541
  };
2542
2543
  // QQQQPR_with_dsub_6_in_DPR_8 Register Class...
2544
  const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = {
2545
    ARM::Q0_Q1_Q2_Q3, 
2546
  };
2547
2548
  // QQQQPR_with_dsub_6_in_DPR_8 Bit set.
2549
  const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = {
2550
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
2551
  };
2552
2553
} // end anonymous namespace
2554
2555
extern const char ARMRegClassStrings[] = {
2556
  /* 0 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2557
  /* 19 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2558
  /* 40 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2559
  /* 63 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2560
  /* 84 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2561
  /* 102 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2562
  /* 122 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2563
  /* 140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '1', '2', 0,
2564
  /* 160 */ 'D', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2565
  /* 169 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2566
  /* 199 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2567
  /* 231 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2568
  /* 261 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2569
  /* 312 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2570
  /* 365 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2571
  /* 383 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2572
  /* 403 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2573
  /* 421 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2574
  /* 440 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2575
  /* 461 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2576
  /* 484 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2577
  /* 505 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2578
  /* 523 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2579
  /* 543 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', 0,
2580
  /* 561 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2581
  /* 589 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2582
  /* 619 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2583
  /* 651 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2584
  /* 681 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2585
  /* 708 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2586
  /* 737 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2587
  /* 764 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2588
  /* 791 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2589
  /* 820 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2590
  /* 847 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2591
  /* 875 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2592
  /* 905 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2593
  /* 937 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2594
  /* 967 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2595
  /* 994 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2596
  /* 1023 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2597
  /* 1050 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2598
  /* 1078 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2599
  /* 1108 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2600
  /* 1140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '6', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2601
  /* 1168 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2602
  /* 1195 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2603
  /* 1224 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2604
  /* 1251 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2605
  /* 1299 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2606
  /* 1349 */ 'S', 'P', 'R', '_', '8', 0,
2607
  /* 1355 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2608
  /* 1374 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2609
  /* 1395 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2610
  /* 1418 */ 'C', 'C', 'R', 0,
2611
  /* 1422 */ 'D', 'P', 'R', 0,
2612
  /* 1426 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
2613
  /* 1441 */ 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
2614
  /* 1456 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
2615
  /* 1485 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
2616
  /* 1514 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', '_', 'a', 'n', 'd', '_', 'h', 'G', 'P', 'R', 0,
2617
  /* 1531 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', 0,
2618
  /* 1559 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 'r', 'G', 'P', 'R', 0,
2619
  /* 1596 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'r', 'G', 'P', 'R', 0,
2620
  /* 1624 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'G', 'P', 'R', 0,
2621
  /* 1652 */ 'H', 'P', 'R', 0,
2622
  /* 1656 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', 0,
2623
  /* 1663 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2624
  /* 1714 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2625
  /* 1774 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2626
  /* 1842 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2627
  /* 1910 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2628
  /* 1987 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2629
  /* 2064 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2630
  /* 2136 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2631
  /* 2217 */ 'S', 'P', 'R', 0,
2632
  /* 2221 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 0,
2633
  /* 2233 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', 0,
2634
  /* 2242 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', 0,
2635
  /* 2253 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', 0,
2636
  /* 2262 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'w', 'i', 't', 'h', 'p', 'c', 0,
2637
  /* 2282 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', 0,
2638
  /* 2290 */ 'D', 'Q', 'u', 'a', 'd', 0,
2639
  /* 2296 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 0,
2640
  /* 2304 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'G', 'P', 'R', 's', 'p', 0,
2641
  /* 2333 */ 'D', 'P', 'a', 'i', 'r', 0,
2642
  /* 2339 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 0,
2643
};
2644
2645
extern const MCRegisterClass ARMMCRegisterClasses[] = {
2646
  { HPR, HPRBits, 1652, 32, sizeof(HPRBits), ARM::HPRRegClassID, 1, true },
2647
  { SPR, SPRBits, 2217, 32, sizeof(SPRBits), ARM::SPRRegClassID, 1, true },
2648
  { GPR, GPRBits, 1437, 16, sizeof(GPRBits), ARM::GPRRegClassID, 1, true },
2649
  { GPRwithAPSR, GPRwithAPSRBits, 2221, 16, sizeof(GPRwithAPSRBits), ARM::GPRwithAPSRRegClassID, 1, true },
2650
  { SPR_8, SPR_8Bits, 1349, 16, sizeof(SPR_8Bits), ARM::SPR_8RegClassID, 1, true },
2651
  { GPRnopc, GPRnopcBits, 2282, 15, sizeof(GPRnopcBits), ARM::GPRnopcRegClassID, 1, true },
2652
  { rGPR, rGPRBits, 1591, 14, sizeof(rGPRBits), ARM::rGPRRegClassID, 1, true },
2653
  { tGPRwithpc, tGPRwithpcBits, 2271, 9, sizeof(tGPRwithpcBits), ARM::tGPRwithpcRegClassID, 1, true },
2654
  { hGPR, hGPRBits, 1526, 8, sizeof(hGPRBits), ARM::hGPRRegClassID, 1, true },
2655
  { tGPR, tGPRBits, 1647, 8, sizeof(tGPRBits), ARM::tGPRRegClassID, 1, true },
2656
  { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 1514, 7, sizeof(GPRnopc_and_hGPRBits), ARM::GPRnopc_and_hGPRRegClassID, 1, true },
2657
  { hGPR_and_rGPR, hGPR_and_rGPRBits, 1582, 6, sizeof(hGPR_and_rGPRBits), ARM::hGPR_and_rGPRRegClassID, 1, true },
2658
  { tcGPR, tcGPRBits, 1435, 5, sizeof(tcGPRBits), ARM::tcGPRRegClassID, 1, true },
2659
  { tGPR_and_tcGPR, tGPR_and_tcGPRBits, 1441, 4, sizeof(tGPR_and_tcGPRBits), ARM::tGPR_and_tcGPRRegClassID, 1, true },
2660
  { CCR, CCRBits, 1418, 1, sizeof(CCRBits), ARM::CCRRegClassID, -1, false },
2661
  { GPRsp, GPRspBits, 2327, 1, sizeof(GPRspBits), ARM::GPRspRegClassID, 1, true },
2662
  { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, 2262, 1, sizeof(hGPR_and_tGPRwithpcBits), ARM::hGPR_and_tGPRwithpcRegClassID, 1, true },
2663
  { hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1426, 1, sizeof(hGPR_and_tcGPRBits), ARM::hGPR_and_tcGPRRegClassID, 1, true },
2664
  { DPR, DPRBits, 1422, 32, sizeof(DPRBits), ARM::DPRRegClassID, 1, true },
2665
  { DPR_VFP2, DPR_VFP2Bits, 160, 16, sizeof(DPR_VFP2Bits), ARM::DPR_VFP2RegClassID, 1, true },
2666
  { DPR_8, DPR_8Bits, 583, 8, sizeof(DPR_8Bits), ARM::DPR_8RegClassID, 1, true },
2667
  { GPRPair, GPRPairBits, 2339, 7, sizeof(GPRPairBits), ARM::GPRPairRegClassID, 1, true },
2668
  { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, 1596, 6, sizeof(GPRPair_with_gsub_1_in_rGPRBits), ARM::GPRPair_with_gsub_1_in_rGPRRegClassID, 1, true },
2669
  { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 1624, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, 1, true },
2670
  { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 1531, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, 1, true },
2671
  { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 1456, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID, 1, true },
2672
  { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, 1559, 2, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits), ARM::GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID, 1, true },
2673
  { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 1485, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM::GPRPair_with_gsub_1_in_tcGPRRegClassID, 1, true },
2674
  { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 2304, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM::GPRPair_with_gsub_1_in_GPRspRegClassID, 1, true },
2675
  { DPairSpc, DPairSpcBits, 2253, 30, sizeof(DPairSpcBits), ARM::DPairSpcRegClassID, 1, true },
2676
  { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 63, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM::DPairSpc_with_ssub_0RegClassID, 1, true },
2677
  { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, 484, 14, sizeof(DPairSpc_with_ssub_4Bits), ARM::DPairSpc_with_ssub_4RegClassID, 1, true },
2678
  { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 651, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID, 1, true },
2679
  { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 937, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID, 1, true },
2680
  { DPair, DPairBits, 2333, 31, sizeof(DPairBits), ARM::DPairRegClassID, 1, true },
2681
  { DPair_with_ssub_0, DPair_with_ssub_0Bits, 122, 16, sizeof(DPair_with_ssub_0Bits), ARM::DPair_with_ssub_0RegClassID, 1, true },
2682
  { QPR, QPRBits, 1659, 16, sizeof(QPRBits), ARM::QPRRegClassID, 1, true },
2683
  { DPair_with_ssub_2, DPair_with_ssub_2Bits, 403, 15, sizeof(DPair_with_ssub_2Bits), ARM::DPair_with_ssub_2RegClassID, 1, true },
2684
  { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 737, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM::DPair_with_dsub_0_in_DPR_8RegClassID, 1, true },
2685
  { QPR_VFP2, QPR_VFP2Bits, 190, 8, sizeof(QPR_VFP2Bits), ARM::QPR_VFP2RegClassID, 1, true },
2686
  { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 820, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM::DPair_with_dsub_1_in_DPR_8RegClassID, 1, true },
2687
  { QPR_8, QPR_8Bits, 1189, 4, sizeof(QPR_8Bits), ARM::QPR_8RegClassID, 1, true },
2688
  { DTriple, DTripleBits, 2296, 30, sizeof(DTripleBits), ARM::DTripleRegClassID, 1, true },
2689
  { DTripleSpc, DTripleSpcBits, 2242, 28, sizeof(DTripleSpcBits), ARM::DTripleSpcRegClassID, 1, true },
2690
  { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 40, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM::DTripleSpc_with_ssub_0RegClassID, 1, true },
2691
  { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 102, 16, sizeof(DTriple_with_ssub_0Bits), ARM::DTriple_with_ssub_0RegClassID, 1, true },
2692
  { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 1687, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_qsub_0_in_QPRRegClassID, 1, true },
2693
  { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 383, 15, sizeof(DTriple_with_ssub_2Bits), ARM::DTriple_with_ssub_2RegClassID, 1, true },
2694
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2088, 15, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2695
  { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, 461, 14, sizeof(DTripleSpc_with_ssub_4Bits), ARM::DTripleSpc_with_ssub_4RegClassID, 1, true },
2696
  { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, 523, 14, sizeof(DTriple_with_ssub_4Bits), ARM::DTriple_with_ssub_4RegClassID, 1, true },
2697
  { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, 1395, 12, sizeof(DTripleSpc_with_ssub_8Bits), ARM::DTripleSpc_with_ssub_8RegClassID, 1, true },
2698
  { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 619, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 1, true },
2699
  { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 708, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, 1, true },
2700
  { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, 199, 8, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits), ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClassID, 1, true },
2701
  { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2064, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2702
  { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 791, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, 1, true },
2703
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 312, 7, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 1, true },
2704
  { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits, 1663, 7, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID, 1, true },
2705
  { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 905, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 1, true },
2706
  { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 994, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, 1, true },
2707
  { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 1108, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 1, true },
2708
  { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2136, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2709
  { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 1195, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM::DTriple_with_qsub_0_in_QPR_8RegClassID, 1, true },
2710
  { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, 1714, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID, 1, true },
2711
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1299, 3, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 1, true },
2712
  { DQuadSpc, DQuadSpcBits, 2233, 28, sizeof(DQuadSpcBits), ARM::DQuadSpcRegClassID, 1, true },
2713
  { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 19, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM::DQuadSpc_with_ssub_0RegClassID, 1, true },
2714
  { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, 440, 14, sizeof(DQuadSpc_with_ssub_4Bits), ARM::DQuadSpc_with_ssub_4RegClassID, 1, true },
2715
  { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, 1374, 12, sizeof(DQuadSpc_with_ssub_8Bits), ARM::DQuadSpc_with_ssub_8RegClassID, 1, true },
2716
  { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 589, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 1, true },
2717
  { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 875, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 1, true },
2718
  { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 1078, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 1, true },
2719
  { DQuad, DQuadBits, 2290, 29, sizeof(DQuadBits), ARM::DQuadRegClassID, 1, true },
2720
  { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 84, 16, sizeof(DQuad_with_ssub_0Bits), ARM::DQuad_with_ssub_0RegClassID, 1, true },
2721
  { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 365, 15, sizeof(DQuad_with_ssub_2Bits), ARM::DQuad_with_ssub_2RegClassID, 1, true },
2722
  { QQPR, QQPRBits, 1658, 15, sizeof(QQPRBits), ARM::QQPRRegClassID, 1, true },
2723
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1796, 14, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2724
  { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, 505, 14, sizeof(DQuad_with_ssub_4Bits), ARM::DQuad_with_ssub_4RegClassID, 1, true },
2725
  { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, 543, 13, sizeof(DQuad_with_ssub_6Bits), ARM::DQuad_with_ssub_6RegClassID, 1, true },
2726
  { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 681, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, 1, true },
2727
  { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, 169, 8, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClassID, 1, true },
2728
  { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1774, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2729
  { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 764, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, 1, true },
2730
  { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, 231, 7, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID, 1, true },
2731
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 261, 7, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 1, true },
2732
  { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 967, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, 1, true },
2733
  { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1842, 6, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2734
  { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 1023, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, 1, true },
2735
  { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1910, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2736
  { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 1168, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM::DQuad_with_qsub_0_in_QPR_8RegClassID, 1, true },
2737
  { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 1224, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM::DQuad_with_qsub_1_in_QPR_8RegClassID, 1, true },
2738
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1251, 3, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 1, true },
2739
  { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1987, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
2740
  { QQQQPR, QQQQPRBits, 1656, 13, sizeof(QQQQPRBits), ARM::QQQQPRRegClassID, 1, true },
2741
  { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 0, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM::QQQQPR_with_ssub_0RegClassID, 1, true },
2742
  { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, 421, 7, sizeof(QQQQPR_with_ssub_4Bits), ARM::QQQQPR_with_ssub_4RegClassID, 1, true },
2743
  { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, 1355, 6, sizeof(QQQQPR_with_ssub_8Bits), ARM::QQQQPR_with_ssub_8RegClassID, 1, true },
2744
  { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, 140, 5, sizeof(QQQQPR_with_ssub_12Bits), ARM::QQQQPR_with_ssub_12RegClassID, 1, true },
2745
  { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 561, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID, 1, true },
2746
  { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 847, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID, 1, true },
2747
  { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 1050, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID, 1, true },
2748
  { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 1140, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID, 1, true },
2749
};
2750
2751
// ARM Dwarf<->LLVM register mappings.
2752
extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
2753
  { 0U, ARM::R0 },
2754
  { 1U, ARM::R1 },
2755
  { 2U, ARM::R2 },
2756
  { 3U, ARM::R3 },
2757
  { 4U, ARM::R4 },
2758
  { 5U, ARM::R5 },
2759
  { 6U, ARM::R6 },
2760
  { 7U, ARM::R7 },
2761
  { 8U, ARM::R8 },
2762
  { 9U, ARM::R9 },
2763
  { 10U, ARM::R10 },
2764
  { 11U, ARM::R11 },
2765
  { 12U, ARM::R12 },
2766
  { 13U, ARM::SP },
2767
  { 14U, ARM::LR },
2768
  { 15U, ARM::PC },
2769
  { 256U, ARM::D0 },
2770
  { 257U, ARM::D1 },
2771
  { 258U, ARM::D2 },
2772
  { 259U, ARM::D3 },
2773
  { 260U, ARM::D4 },
2774
  { 261U, ARM::D5 },
2775
  { 262U, ARM::D6 },
2776
  { 263U, ARM::D7 },
2777
  { 264U, ARM::D8 },
2778
  { 265U, ARM::D9 },
2779
  { 266U, ARM::D10 },
2780
  { 267U, ARM::D11 },
2781
  { 268U, ARM::D12 },
2782
  { 269U, ARM::D13 },
2783
  { 270U, ARM::D14 },
2784
  { 271U, ARM::D15 },
2785
  { 272U, ARM::D16 },
2786
  { 273U, ARM::D17 },
2787
  { 274U, ARM::D18 },
2788
  { 275U, ARM::D19 },
2789
  { 276U, ARM::D20 },
2790
  { 277U, ARM::D21 },
2791
  { 278U, ARM::D22 },
2792
  { 279U, ARM::D23 },
2793
  { 280U, ARM::D24 },
2794
  { 281U, ARM::D25 },
2795
  { 282U, ARM::D26 },
2796
  { 283U, ARM::D27 },
2797
  { 284U, ARM::D28 },
2798
  { 285U, ARM::D29 },
2799
  { 286U, ARM::D30 },
2800
  { 287U, ARM::D31 },
2801
};
2802
extern const unsigned ARMDwarfFlavour0Dwarf2LSize = array_lengthof(ARMDwarfFlavour0Dwarf2L);
2803
2804
extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
2805
  { 0U, ARM::R0 },
2806
  { 1U, ARM::R1 },
2807
  { 2U, ARM::R2 },
2808
  { 3U, ARM::R3 },
2809
  { 4U, ARM::R4 },
2810
  { 5U, ARM::R5 },
2811
  { 6U, ARM::R6 },
2812
  { 7U, ARM::R7 },
2813
  { 8U, ARM::R8 },
2814
  { 9U, ARM::R9 },
2815
  { 10U, ARM::R10 },
2816
  { 11U, ARM::R11 },
2817
  { 12U, ARM::R12 },
2818
  { 13U, ARM::SP },
2819
  { 14U, ARM::LR },
2820
  { 15U, ARM::PC },
2821
  { 256U, ARM::D0 },
2822
  { 257U, ARM::D1 },
2823
  { 258U, ARM::D2 },
2824
  { 259U, ARM::D3 },
2825
  { 260U, ARM::D4 },
2826
  { 261U, ARM::D5 },
2827
  { 262U, ARM::D6 },
2828
  { 263U, ARM::D7 },
2829
  { 264U, ARM::D8 },
2830
  { 265U, ARM::D9 },
2831
  { 266U, ARM::D10 },
2832
  { 267U, ARM::D11 },
2833
  { 268U, ARM::D12 },
2834
  { 269U, ARM::D13 },
2835
  { 270U, ARM::D14 },
2836
  { 271U, ARM::D15 },
2837
  { 272U, ARM::D16 },
2838
  { 273U, ARM::D17 },
2839
  { 274U, ARM::D18 },
2840
  { 275U, ARM::D19 },
2841
  { 276U, ARM::D20 },
2842
  { 277U, ARM::D21 },
2843
  { 278U, ARM::D22 },
2844
  { 279U, ARM::D23 },
2845
  { 280U, ARM::D24 },
2846
  { 281U, ARM::D25 },
2847
  { 282U, ARM::D26 },
2848
  { 283U, ARM::D27 },
2849
  { 284U, ARM::D28 },
2850
  { 285U, ARM::D29 },
2851
  { 286U, ARM::D30 },
2852
  { 287U, ARM::D31 },
2853
};
2854
extern const unsigned ARMEHFlavour0Dwarf2LSize = array_lengthof(ARMEHFlavour0Dwarf2L);
2855
2856
extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
2857
  { ARM::LR, 14U },
2858
  { ARM::PC, 15U },
2859
  { ARM::SP, 13U },
2860
  { ARM::D0, 256U },
2861
  { ARM::D1, 257U },
2862
  { ARM::D2, 258U },
2863
  { ARM::D3, 259U },
2864
  { ARM::D4, 260U },
2865
  { ARM::D5, 261U },
2866
  { ARM::D6, 262U },
2867
  { ARM::D7, 263U },
2868
  { ARM::D8, 264U },
2869
  { ARM::D9, 265U },
2870
  { ARM::D10, 266U },
2871
  { ARM::D11, 267U },
2872
  { ARM::D12, 268U },
2873
  { ARM::D13, 269U },
2874
  { ARM::D14, 270U },
2875
  { ARM::D15, 271U },
2876
  { ARM::D16, 272U },
2877
  { ARM::D17, 273U },
2878
  { ARM::D18, 274U },
2879
  { ARM::D19, 275U },
2880
  { ARM::D20, 276U },
2881
  { ARM::D21, 277U },
2882
  { ARM::D22, 278U },
2883
  { ARM::D23, 279U },
2884
  { ARM::D24, 280U },
2885
  { ARM::D25, 281U },
2886
  { ARM::D26, 282U },
2887
  { ARM::D27, 283U },
2888
  { ARM::D28, 284U },
2889
  { ARM::D29, 285U },
2890
  { ARM::D30, 286U },
2891
  { ARM::D31, 287U },
2892
  { ARM::R0, 0U },
2893
  { ARM::R1, 1U },
2894
  { ARM::R2, 2U },
2895
  { ARM::R3, 3U },
2896
  { ARM::R4, 4U },
2897
  { ARM::R5, 5U },
2898
  { ARM::R6, 6U },
2899
  { ARM::R7, 7U },
2900
  { ARM::R8, 8U },
2901
  { ARM::R9, 9U },
2902
  { ARM::R10, 10U },
2903
  { ARM::R11, 11U },
2904
  { ARM::R12, 12U },
2905
};
2906
extern const unsigned ARMDwarfFlavour0L2DwarfSize = array_lengthof(ARMDwarfFlavour0L2Dwarf);
2907
2908
extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
2909
  { ARM::LR, 14U },
2910
  { ARM::PC, 15U },
2911
  { ARM::SP, 13U },
2912
  { ARM::D0, 256U },
2913
  { ARM::D1, 257U },
2914
  { ARM::D2, 258U },
2915
  { ARM::D3, 259U },
2916
  { ARM::D4, 260U },
2917
  { ARM::D5, 261U },
2918
  { ARM::D6, 262U },
2919
  { ARM::D7, 263U },
2920
  { ARM::D8, 264U },
2921
  { ARM::D9, 265U },
2922
  { ARM::D10, 266U },
2923
  { ARM::D11, 267U },
2924
  { ARM::D12, 268U },
2925
  { ARM::D13, 269U },
2926
  { ARM::D14, 270U },
2927
  { ARM::D15, 271U },
2928
  { ARM::D16, 272U },
2929
  { ARM::D17, 273U },
2930
  { ARM::D18, 274U },
2931
  { ARM::D19, 275U },
2932
  { ARM::D20, 276U },
2933
  { ARM::D21, 277U },
2934
  { ARM::D22, 278U },
2935
  { ARM::D23, 279U },
2936
  { ARM::D24, 280U },
2937
  { ARM::D25, 281U },
2938
  { ARM::D26, 282U },
2939
  { ARM::D27, 283U },
2940
  { ARM::D28, 284U },
2941
  { ARM::D29, 285U },
2942
  { ARM::D30, 286U },
2943
  { ARM::D31, 287U },
2944
  { ARM::R0, 0U },
2945
  { ARM::R1, 1U },
2946
  { ARM::R2, 2U },
2947
  { ARM::R3, 3U },
2948
  { ARM::R4, 4U },
2949
  { ARM::R5, 5U },
2950
  { ARM::R6, 6U },
2951
  { ARM::R7, 7U },
2952
  { ARM::R8, 8U },
2953
  { ARM::R9, 9U },
2954
  { ARM::R10, 10U },
2955
  { ARM::R11, 11U },
2956
  { ARM::R12, 12U },
2957
};
2958
extern const unsigned ARMEHFlavour0L2DwarfSize = array_lengthof(ARMEHFlavour0L2Dwarf);
2959
2960
extern const uint16_t ARMRegEncodingTable[] = {
2961
  0,
2962
  1,
2963
  15,
2964
  0,
2965
  8,
2966
  9,
2967
  3,
2968
  3,
2969
  0,
2970
  4,
2971
  14,
2972
  15,
2973
  13,
2974
  2,
2975
  0,
2976
  1,
2977
  2,
2978
  3,
2979
  4,
2980
  5,
2981
  6,
2982
  7,
2983
  8,
2984
  9,
2985
  10,
2986
  11,
2987
  12,
2988
  13,
2989
  14,
2990
  15,
2991
  16,
2992
  17,
2993
  18,
2994
  19,
2995
  20,
2996
  21,
2997
  22,
2998
  23,
2999
  24,
3000
  25,
3001
  26,
3002
  27,
3003
  28,
3004
  29,
3005
  30,
3006
  31,
3007
  10,
3008
  7,
3009
  6,
3010
  5,
3011
  0,
3012
  1,
3013
  2,
3014
  3,
3015
  4,
3016
  5,
3017
  6,
3018
  7,
3019
  8,
3020
  9,
3021
  10,
3022
  11,
3023
  12,
3024
  13,
3025
  14,
3026
  15,
3027
  0,
3028
  1,
3029
  2,
3030
  3,
3031
  4,
3032
  5,
3033
  6,
3034
  7,
3035
  8,
3036
  9,
3037
  10,
3038
  11,
3039
  12,
3040
  0,
3041
  1,
3042
  2,
3043
  3,
3044
  4,
3045
  5,
3046
  6,
3047
  7,
3048
  8,
3049
  9,
3050
  10,
3051
  11,
3052
  12,
3053
  13,
3054
  14,
3055
  15,
3056
  16,
3057
  17,
3058
  18,
3059
  19,
3060
  20,
3061
  21,
3062
  22,
3063
  23,
3064
  24,
3065
  25,
3066
  26,
3067
  27,
3068
  28,
3069
  29,
3070
  30,
3071
  31,
3072
  0,
3073
  1,
3074
  2,
3075
  3,
3076
  4,
3077
  5,
3078
  6,
3079
  7,
3080
  8,
3081
  9,
3082
  10,
3083
  11,
3084
  12,
3085
  13,
3086
  14,
3087
  15,
3088
  16,
3089
  17,
3090
  18,
3091
  19,
3092
  20,
3093
  21,
3094
  22,
3095
  23,
3096
  24,
3097
  25,
3098
  26,
3099
  27,
3100
  28,
3101
  29,
3102
  0,
3103
  1,
3104
  2,
3105
  3,
3106
  4,
3107
  5,
3108
  6,
3109
  7,
3110
  8,
3111
  9,
3112
  10,
3113
  11,
3114
  12,
3115
  13,
3116
  14,
3117
  0,
3118
  1,
3119
  2,
3120
  3,
3121
  4,
3122
  5,
3123
  6,
3124
  7,
3125
  8,
3126
  9,
3127
  10,
3128
  11,
3129
  12,
3130
  12,
3131
  0,
3132
  2,
3133
  4,
3134
  6,
3135
  8,
3136
  10,
3137
  0,
3138
  1,
3139
  2,
3140
  3,
3141
  4,
3142
  5,
3143
  6,
3144
  7,
3145
  8,
3146
  9,
3147
  10,
3148
  11,
3149
  12,
3150
  13,
3151
  14,
3152
  15,
3153
  16,
3154
  17,
3155
  18,
3156
  19,
3157
  20,
3158
  21,
3159
  22,
3160
  23,
3161
  24,
3162
  25,
3163
  26,
3164
  27,
3165
  28,
3166
  29,
3167
  0,
3168
  1,
3169
  2,
3170
  3,
3171
  4,
3172
  5,
3173
  6,
3174
  7,
3175
  8,
3176
  9,
3177
  10,
3178
  11,
3179
  12,
3180
  13,
3181
  14,
3182
  15,
3183
  16,
3184
  17,
3185
  18,
3186
  19,
3187
  20,
3188
  21,
3189
  22,
3190
  23,
3191
  24,
3192
  25,
3193
  26,
3194
  27,
3195
  0,
3196
  1,
3197
  2,
3198
  3,
3199
  4,
3200
  5,
3201
  6,
3202
  7,
3203
  8,
3204
  9,
3205
  10,
3206
  11,
3207
  12,
3208
  13,
3209
  14,
3210
  15,
3211
  16,
3212
  17,
3213
  18,
3214
  19,
3215
  20,
3216
  21,
3217
  22,
3218
  23,
3219
  24,
3220
  25,
3221
  1,
3222
  3,
3223
  5,
3224
  7,
3225
  9,
3226
  11,
3227
  13,
3228
  15,
3229
  17,
3230
  19,
3231
  21,
3232
  23,
3233
  25,
3234
  27,
3235
  29,
3236
  1,
3237
  3,
3238
  5,
3239
  7,
3240
  9,
3241
  11,
3242
  13,
3243
  15,
3244
  17,
3245
  19,
3246
  21,
3247
  23,
3248
  25,
3249
  27,
3250
};
3251
8.18k
static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3252
8.18k
  RI->InitMCRegisterInfo(ARMRegDesc, 289, RA, PC, ARMMCRegisterClasses, 103, ARMRegUnitRoots, 77, ARMRegDiffLists, ARMLaneMaskLists, ARMRegStrings, ARMRegClassStrings, ARMSubRegIdxLists, 57,
3253
8.18k
ARMSubRegIdxRanges, ARMRegEncodingTable);
3254
8.18k
3255
8.18k
  switch (DwarfFlavour) {
3256
8.18k
  default:
3257
0
    llvm_unreachable("Unknown DWARF flavour");
3258
8.18k
  case 0:
3259
8.18k
    RI->mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
3260
8.18k
    break;
3261
8.18k
  }
3262
8.18k
  switch (EHFlavour) {
3263
8.18k
  default:
3264
0
    llvm_unreachable("Unknown DWARF flavour");
3265
8.18k
  case 0:
3266
8.18k
    RI->mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
3267
8.18k
    break;
3268
8.18k
  }
3269
8.18k
  switch (DwarfFlavour) {
3270
8.18k
  default:
3271
0
    llvm_unreachable("Unknown DWARF flavour");
3272
8.18k
  case 0:
3273
8.18k
    RI->mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false);
3274
8.18k
    break;
3275
8.18k
  }
3276
8.18k
  switch (EHFlavour) {
3277
8.18k
  default:
3278
0
    llvm_unreachable("Unknown DWARF flavour");
3279
8.18k
  case 0:
3280
8.18k
    RI->mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true);
3281
8.18k
    break;
3282
8.18k
  }
3283
8.18k
}
3284
3285
} // end namespace llvm
3286
3287
#endif // GET_REGINFO_MC_DESC
3288
3289
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3290
|*                                                                            *|
3291
|* Register Information Header Fragment                                       *|
3292
|*                                                                            *|
3293
|* Automatically generated file, do not edit!                                 *|
3294
|*                                                                            *|
3295
\*===----------------------------------------------------------------------===*/
3296
3297
3298
#ifdef GET_REGINFO_HEADER
3299
#undef GET_REGINFO_HEADER
3300
3301
#include "llvm/CodeGen/TargetRegisterInfo.h"
3302
3303
namespace llvm {
3304
3305
class ARMFrameLowering;
3306
3307
struct ARMGenRegisterInfo : public TargetRegisterInfo {
3308
  explicit ARMGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3309
      unsigned PC = 0, unsigned HwMode = 0);
3310
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3311
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3312
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3313
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3314
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3315
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
3316
  unsigned getNumRegPressureSets() const override;
3317
  const char *getRegPressureSetName(unsigned Idx) const override;
3318
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3319
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3320
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3321
  ArrayRef<const char *> getRegMaskNames() const override;
3322
  ArrayRef<const uint32_t *> getRegMasks() const override;
3323
  /// Devirtualized TargetFrameLowering.
3324
  static const ARMFrameLowering *getFrameLowering(
3325
      const MachineFunction &MF);
3326
};
3327
3328
namespace ARM { // Register classes
3329
  extern const TargetRegisterClass HPRRegClass;
3330
  extern const TargetRegisterClass SPRRegClass;
3331
  extern const TargetRegisterClass GPRRegClass;
3332
  extern const TargetRegisterClass GPRwithAPSRRegClass;
3333
  extern const TargetRegisterClass SPR_8RegClass;
3334
  extern const TargetRegisterClass GPRnopcRegClass;
3335
  extern const TargetRegisterClass rGPRRegClass;
3336
  extern const TargetRegisterClass tGPRwithpcRegClass;
3337
  extern const TargetRegisterClass hGPRRegClass;
3338
  extern const TargetRegisterClass tGPRRegClass;
3339
  extern const TargetRegisterClass GPRnopc_and_hGPRRegClass;
3340
  extern const TargetRegisterClass hGPR_and_rGPRRegClass;
3341
  extern const TargetRegisterClass tcGPRRegClass;
3342
  extern const TargetRegisterClass tGPR_and_tcGPRRegClass;
3343
  extern const TargetRegisterClass CCRRegClass;
3344
  extern const TargetRegisterClass GPRspRegClass;
3345
  extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass;
3346
  extern const TargetRegisterClass hGPR_and_tcGPRRegClass;
3347
  extern const TargetRegisterClass DPRRegClass;
3348
  extern const TargetRegisterClass DPR_VFP2RegClass;
3349
  extern const TargetRegisterClass DPR_8RegClass;
3350
  extern const TargetRegisterClass GPRPairRegClass;
3351
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_rGPRRegClass;
3352
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass;
3353
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass;
3354
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass;
3355
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass;
3356
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass;
3357
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass;
3358
  extern const TargetRegisterClass DPairSpcRegClass;
3359
  extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass;
3360
  extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass;
3361
  extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass;
3362
  extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass;
3363
  extern const TargetRegisterClass DPairRegClass;
3364
  extern const TargetRegisterClass DPair_with_ssub_0RegClass;
3365
  extern const TargetRegisterClass QPRRegClass;
3366
  extern const TargetRegisterClass DPair_with_ssub_2RegClass;
3367
  extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass;
3368
  extern const TargetRegisterClass QPR_VFP2RegClass;
3369
  extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass;
3370
  extern const TargetRegisterClass QPR_8RegClass;
3371
  extern const TargetRegisterClass DTripleRegClass;
3372
  extern const TargetRegisterClass DTripleSpcRegClass;
3373
  extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass;
3374
  extern const TargetRegisterClass DTriple_with_ssub_0RegClass;
3375
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass;
3376
  extern const TargetRegisterClass DTriple_with_ssub_2RegClass;
3377
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3378
  extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass;
3379
  extern const TargetRegisterClass DTriple_with_ssub_4RegClass;
3380
  extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass;
3381
  extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass;
3382
  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass;
3383
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_VFP2RegClass;
3384
  extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3385
  extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass;
3386
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
3387
  extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass;
3388
  extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass;
3389
  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass;
3390
  extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass;
3391
  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3392
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass;
3393
  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass;
3394
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
3395
  extern const TargetRegisterClass DQuadSpcRegClass;
3396
  extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass;
3397
  extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass;
3398
  extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass;
3399
  extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass;
3400
  extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass;
3401
  extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass;
3402
  extern const TargetRegisterClass DQuadRegClass;
3403
  extern const TargetRegisterClass DQuad_with_ssub_0RegClass;
3404
  extern const TargetRegisterClass DQuad_with_ssub_2RegClass;
3405
  extern const TargetRegisterClass QQPRRegClass;
3406
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3407
  extern const TargetRegisterClass DQuad_with_ssub_4RegClass;
3408
  extern const TargetRegisterClass DQuad_with_ssub_6RegClass;
3409
  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass;
3410
  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_VFP2RegClass;
3411
  extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3412
  extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass;
3413
  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_VFP2RegClass;
3414
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
3415
  extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass;
3416
  extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3417
  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass;
3418
  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3419
  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass;
3420
  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass;
3421
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
3422
  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3423
  extern const TargetRegisterClass QQQQPRRegClass;
3424
  extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass;
3425
  extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass;
3426
  extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass;
3427
  extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass;
3428
  extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass;
3429
  extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass;
3430
  extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass;
3431
  extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass;
3432
} // end namespace ARM
3433
3434
} // end namespace llvm
3435
3436
#endif // GET_REGINFO_HEADER
3437
3438
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3439
|*                                                                            *|
3440
|* Target Register and Register Classes Information                           *|
3441
|*                                                                            *|
3442
|* Automatically generated file, do not edit!                                 *|
3443
|*                                                                            *|
3444
\*===----------------------------------------------------------------------===*/
3445
3446
3447
#ifdef GET_REGINFO_TARGET_DESC
3448
#undef GET_REGINFO_TARGET_DESC
3449
3450
namespace llvm {
3451
3452
extern const MCRegisterClass ARMMCRegisterClasses[];
3453
3454
static const MVT::SimpleValueType VTLists[] = {
3455
  /* 0 */ MVT::i32, MVT::Other,
3456
  /* 2 */ MVT::f16, MVT::Other,
3457
  /* 4 */ MVT::f32, MVT::Other,
3458
  /* 6 */ MVT::v2i64, MVT::Other,
3459
  /* 8 */ MVT::v4i64, MVT::Other,
3460
  /* 10 */ MVT::v8i64, MVT::Other,
3461
  /* 12 */ MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::v4f16, MVT::Other,
3462
  /* 20 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
3463
  /* 28 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other,
3464
  /* 35 */ MVT::Untyped, MVT::Other,
3465
};
3466
3467
static const char *const SubRegIndexNameTable[] = { "dsub_0", "dsub_1", "dsub_2", "dsub_3", "dsub_4", "dsub_5", "dsub_6", "dsub_7", "gsub_0", "gsub_1", "qqsub_0", "qqsub_1", "qsub_0", "qsub_1", "qsub_2", "qsub_3", "ssub_0", "ssub_1", "ssub_2", "ssub_3", "ssub_4", "ssub_5", "ssub_6", "ssub_7", "ssub_8", "ssub_9", "ssub_10", "ssub_11", "ssub_12", "ssub_13", "dsub_7_then_ssub_0", "dsub_7_then_ssub_1", "ssub_0_ssub_1_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5", "ssub_2_ssub_3_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_6_ssub_7_dsub_5", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5", "ssub_6_ssub_7_dsub_5_dsub_7", "ssub_6_ssub_7_ssub_8_ssub_9", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "ssub_8_ssub_9_ssub_12_ssub_13", "ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "dsub_5_dsub_7", "dsub_5_ssub_12_ssub_13_dsub_7", "dsub_5_ssub_12_ssub_13", "ssub_4_ssub_5_ssub_6_ssub_7_qsub_2", "" };
3468
3469
3470
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3471
  LaneBitmask::getAll(),
3472
  LaneBitmask(0x0000000C), // dsub_0
3473
  LaneBitmask(0x00000030), // dsub_1
3474
  LaneBitmask(0x000000C0), // dsub_2
3475
  LaneBitmask(0x00000300), // dsub_3
3476
  LaneBitmask(0x00000C00), // dsub_4
3477
  LaneBitmask(0x00003000), // dsub_5
3478
  LaneBitmask(0x0000C000), // dsub_6
3479
  LaneBitmask(0x00030000), // dsub_7
3480
  LaneBitmask(0x00000001), // gsub_0
3481
  LaneBitmask(0x00000002), // gsub_1
3482
  LaneBitmask(0x000003FC), // qqsub_0
3483
  LaneBitmask(0x0003FC00), // qqsub_1
3484
  LaneBitmask(0x0000003C), // qsub_0
3485
  LaneBitmask(0x000003C0), // qsub_1
3486
  LaneBitmask(0x00003C00), // qsub_2
3487
  LaneBitmask(0x0003C000), // qsub_3
3488
  LaneBitmask(0x00000004), // ssub_0
3489
  LaneBitmask(0x00000008), // ssub_1
3490
  LaneBitmask(0x00000010), // ssub_2
3491
  LaneBitmask(0x00000020), // ssub_3
3492
  LaneBitmask(0x00000040), // ssub_4
3493
  LaneBitmask(0x00000080), // ssub_5
3494
  LaneBitmask(0x00000100), // ssub_6
3495
  LaneBitmask(0x00000200), // ssub_7
3496
  LaneBitmask(0x00000400), // ssub_8
3497
  LaneBitmask(0x00000800), // ssub_9
3498
  LaneBitmask(0x00001000), // ssub_10
3499
  LaneBitmask(0x00002000), // ssub_11
3500
  LaneBitmask(0x00004000), // ssub_12
3501
  LaneBitmask(0x00008000), // ssub_13
3502
  LaneBitmask(0x00010000), // dsub_7_then_ssub_0
3503
  LaneBitmask(0x00020000), // dsub_7_then_ssub_1
3504
  LaneBitmask(0x000000CC), // ssub_0_ssub_1_ssub_4_ssub_5
3505
  LaneBitmask(0x000000FC), // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3506
  LaneBitmask(0x00000330), // ssub_2_ssub_3_ssub_6_ssub_7
3507
  LaneBitmask(0x000003F0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3508
  LaneBitmask(0x000000F0), // ssub_2_ssub_3_ssub_4_ssub_5
3509
  LaneBitmask(0x00000CCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
3510
  LaneBitmask(0x0000CCCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3511
  LaneBitmask(0x00003330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
3512
  LaneBitmask(0x00033330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
3513
  LaneBitmask(0x00000FF0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3514
  LaneBitmask(0x00000CC0), // ssub_4_ssub_5_ssub_8_ssub_9
3515
  LaneBitmask(0x00000FC0), // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3516
  LaneBitmask(0x0000CCC0), // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3517
  LaneBitmask(0x00003300), // ssub_6_ssub_7_dsub_5
3518
  LaneBitmask(0x00003F00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
3519
  LaneBitmask(0x00033300), // ssub_6_ssub_7_dsub_5_dsub_7
3520
  LaneBitmask(0x00000F00), // ssub_6_ssub_7_ssub_8_ssub_9
3521
  LaneBitmask(0x0000FF00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3522
  LaneBitmask(0x0000CC00), // ssub_8_ssub_9_ssub_12_ssub_13
3523
  LaneBitmask(0x0000FC00), // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3524
  LaneBitmask(0x00033000), // dsub_5_dsub_7
3525
  LaneBitmask(0x0003F000), // dsub_5_ssub_12_ssub_13_dsub_7
3526
  LaneBitmask(0x0000F000), // dsub_5_ssub_12_ssub_13
3527
  LaneBitmask(0x00003FC0), // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
3528
 };
3529
3530
3531
3532
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3533
  // Mode = 0 (Default)
3534
  { 16, 16, 32, VTLists+2 },    // HPR
3535
  { 32, 32, 32, VTLists+4 },    // SPR
3536
  { 32, 32, 32, VTLists+0 },    // GPR
3537
  { 32, 32, 32, VTLists+0 },    // GPRwithAPSR
3538
  { 32, 32, 32, VTLists+4 },    // SPR_8
3539
  { 32, 32, 32, VTLists+0 },    // GPRnopc
3540
  { 32, 32, 32, VTLists+0 },    // rGPR
3541
  { 32, 32, 32, VTLists+0 },    // tGPRwithpc
3542
  { 32, 32, 32, VTLists+0 },    // hGPR
3543
  { 32, 32, 32, VTLists+0 },    // tGPR
3544
  { 32, 32, 32, VTLists+0 },    // GPRnopc_and_hGPR
3545
  { 32, 32, 32, VTLists+0 },    // hGPR_and_rGPR
3546
  { 32, 32, 32, VTLists+0 },    // tcGPR
3547
  { 32, 32, 32, VTLists+0 },    // tGPR_and_tcGPR
3548
  { 32, 32, 32, VTLists+0 },    // CCR
3549
  { 32, 32, 32, VTLists+0 },    // GPRsp
3550
  { 32, 32, 32, VTLists+0 },    // hGPR_and_tGPRwithpc
3551
  { 32, 32, 32, VTLists+0 },    // hGPR_and_tcGPR
3552
  { 64, 64, 64, VTLists+12 },    // DPR
3553
  { 64, 64, 64, VTLists+12 },    // DPR_VFP2
3554
  { 64, 64, 64, VTLists+12 },    // DPR_8
3555
  { 64, 64, 64, VTLists+35 },    // GPRPair
3556
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_rGPR
3557
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_tGPR
3558
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_hGPR
3559
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_tcGPR
3560
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_hGPR_and_rGPR
3561
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_tcGPR
3562
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_GPRsp
3563
  { 128, 128, 64, VTLists+6 },    // DPairSpc
3564
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_ssub_0
3565
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_ssub_4
3566
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_dsub_0_in_DPR_8
3567
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_dsub_2_in_DPR_8
3568
  { 128, 128, 128, VTLists+28 },    // DPair
3569
  { 128, 128, 128, VTLists+28 },    // DPair_with_ssub_0
3570
  { 128, 128, 128, VTLists+20 },    // QPR
3571
  { 128, 128, 128, VTLists+28 },    // DPair_with_ssub_2
3572
  { 128, 128, 128, VTLists+28 },    // DPair_with_dsub_0_in_DPR_8
3573
  { 128, 128, 128, VTLists+28 },    // QPR_VFP2
3574
  { 128, 128, 128, VTLists+28 },    // DPair_with_dsub_1_in_DPR_8
3575
  { 128, 128, 128, VTLists+28 },    // QPR_8
3576
  { 192, 192, 64, VTLists+35 },    // DTriple
3577
  { 192, 192, 64, VTLists+35 },    // DTripleSpc
3578
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_0
3579
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_0
3580
  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR
3581
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2
3582
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3583
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_4
3584
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_4
3585
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_8
3586
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_0_in_DPR_8
3587
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_0_in_DPR_8
3588
  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR_VFP2
3589
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3590
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_1_in_DPR_8
3591
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
3592
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
3593
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_2_in_DPR_8
3594
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_2_in_DPR_8
3595
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_4_in_DPR_8
3596
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3597
  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR_8
3598
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
3599
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
3600
  { 256, 256, 64, VTLists+8 },    // DQuadSpc
3601
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_0
3602
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_4
3603
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_8
3604
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_0_in_DPR_8
3605
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_2_in_DPR_8
3606
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_4_in_DPR_8
3607
  { 256, 256, 256, VTLists+8 },    // DQuad
3608
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_0
3609
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2
3610
  { 256, 256, 256, VTLists+8 },    // QQPR
3611
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3612
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_4
3613
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_6
3614
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_0_in_DPR_8
3615
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_0_in_QPR_VFP2
3616
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3617
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_1_in_DPR_8
3618
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_1_in_QPR_VFP2
3619
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
3620
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_2_in_DPR_8
3621
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3622
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_3_in_DPR_8
3623
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3624
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_0_in_QPR_8
3625
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_1_in_QPR_8
3626
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
3627
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3628
  { 512, 512, 256, VTLists+10 },    // QQQQPR
3629
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_0
3630
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_4
3631
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_8
3632
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_12
3633
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_0_in_DPR_8
3634
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_2_in_DPR_8
3635
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_4_in_DPR_8
3636
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_6_in_DPR_8
3637
};
3638
3639
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
3640
3641
static const uint32_t HPRSubClassMask[] = {
3642
  0x00000013, 0x00000000, 0x00000000, 0x00000000, 
3643
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_0
3644
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_1
3645
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_2
3646
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_3
3647
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_4
3648
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_5
3649
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_6
3650
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_7
3651
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_8
3652
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_9
3653
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_10
3654
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_11
3655
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_12
3656
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_13
3657
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_0
3658
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_1
3659
};
3660
3661
static const uint32_t SPRSubClassMask[] = {
3662
  0x00000012, 0x00000000, 0x00000000, 0x00000000, 
3663
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_0
3664
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_1
3665
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_2
3666
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_3
3667
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_4
3668
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_5
3669
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_6
3670
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_7
3671
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_8
3672
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_9
3673
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_10
3674
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_11
3675
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_12
3676
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_13
3677
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_0
3678
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_1
3679
};
3680
3681
static const uint32_t GPRSubClassMask[] = {
3682
  0x0003bfe4, 0x00000000, 0x00000000, 0x00000000, 
3683
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3684
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3685
};
3686
3687
static const uint32_t GPRwithAPSRSubClassMask[] = {
3688
  0x0002be68, 0x00000000, 0x00000000, 0x00000000, 
3689
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3690
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3691
};
3692
3693
static const uint32_t SPR_8SubClassMask[] = {
3694
  0x00000010, 0x00000000, 0x00000000, 0x00000000, 
3695
  0x00100000, 0xf9300343, 0x3f4901c3, 0x00000078, // ssub_0
3696
  0x00100000, 0xf9300343, 0x3f4901c3, 0x00000078, // ssub_1
3697
  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // ssub_2
3698
  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // ssub_3
3699
  0x00000000, 0x38000002, 0x39400183, 0x00000070, // ssub_4
3700
  0x00000000, 0x38000002, 0x39400183, 0x00000070, // ssub_5
3701
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_6
3702
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_7
3703
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_8
3704
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_9
3705
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_10
3706
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_11
3707
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_12
3708
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_13
3709
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7_then_ssub_0
3710
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7_then_ssub_1
3711
};
3712
3713
static const uint32_t GPRnopcSubClassMask[] = {
3714
  0x0002be60, 0x00000000, 0x00000000, 0x00000000, 
3715
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3716
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3717
};
3718
3719
static const uint32_t rGPRSubClassMask[] = {
3720
  0x00023a40, 0x00000000, 0x00000000, 0x00000000, 
3721
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3722
  0x0cc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3723
};
3724
3725
static const uint32_t tGPRwithpcSubClassMask[] = {
3726
  0x00012280, 0x00000000, 0x00000000, 0x00000000, 
3727
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3728
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3729
};
3730
3731
static const uint32_t hGPRSubClassMask[] = {
3732
  0x00038d00, 0x00000000, 0x00000000, 0x00000000, 
3733
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3734
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3735
};
3736
3737
static const uint32_t tGPRSubClassMask[] = {
3738
  0x00002200, 0x00000000, 0x00000000, 0x00000000, 
3739
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3740
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3741
};
3742
3743
static const uint32_t GPRnopc_and_hGPRSubClassMask[] = {
3744
  0x00028c00, 0x00000000, 0x00000000, 0x00000000, 
3745
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3746
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3747
};
3748
3749
static const uint32_t hGPR_and_rGPRSubClassMask[] = {
3750
  0x00020800, 0x00000000, 0x00000000, 0x00000000, 
3751
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3752
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3753
};
3754
3755
static const uint32_t tcGPRSubClassMask[] = {
3756
  0x00023000, 0x00000000, 0x00000000, 0x00000000, 
3757
  0x1a000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3758
  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3759
};
3760
3761
static const uint32_t tGPR_and_tcGPRSubClassMask[] = {
3762
  0x00002000, 0x00000000, 0x00000000, 0x00000000, 
3763
  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3764
  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3765
};
3766
3767
static const uint32_t CCRSubClassMask[] = {
3768
  0x00004000, 0x00000000, 0x00000000, 0x00000000, 
3769
};
3770
3771
static const uint32_t GPRspSubClassMask[] = {
3772
  0x00008000, 0x00000000, 0x00000000, 0x00000000, 
3773
  0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3774
};
3775
3776
static const uint32_t hGPR_and_tGPRwithpcSubClassMask[] = {
3777
  0x00010000, 0x00000000, 0x00000000, 0x00000000, 
3778
};
3779
3780
static const uint32_t hGPR_and_tcGPRSubClassMask[] = {
3781
  0x00020000, 0x00000000, 0x00000000, 0x00000000, 
3782
  0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3783
};
3784
3785
static const uint32_t DPRSubClassMask[] = {
3786
  0x001c0000, 0x00000000, 0x00000000, 0x00000000, 
3787
  0xe0000000, 0xffffffff, 0xffffffff, 0x0000007f, // dsub_0
3788
  0x00000000, 0xd7e5e7fc, 0xfffffe03, 0x0000007f, // dsub_1
3789
  0xe0000000, 0xfffffc03, 0xffffffff, 0x0000007f, // dsub_2
3790
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // dsub_3
3791
  0x00000000, 0x281a1800, 0xc00001fc, 0x0000007f, // dsub_4
3792
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5
3793
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_6
3794
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_7
3795
};
3796
3797
static const uint32_t DPR_VFP2SubClassMask[] = {
3798
  0x00180000, 0x00000000, 0x00000000, 0x00000000, 
3799
  0xc0000000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // dsub_0
3800
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // dsub_1
3801
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // dsub_2
3802
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // dsub_3
3803
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // dsub_4
3804
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5
3805
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_6
3806
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7
3807
};
3808
3809
static const uint32_t DPR_8SubClassMask[] = {
3810
  0x00100000, 0x00000000, 0x00000000, 0x00000000, 
3811
  0x00000000, 0xf9300343, 0x3f4901c3, 0x00000078, // dsub_0
3812
  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // dsub_1
3813
  0x00000000, 0x38000002, 0x39400183, 0x00000070, // dsub_2
3814
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // dsub_3
3815
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // dsub_4
3816
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5
3817
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_6
3818
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7
3819
};
3820
3821
static const uint32_t GPRPairSubClassMask[] = {
3822
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, 
3823
};
3824
3825
static const uint32_t GPRPair_with_gsub_1_in_rGPRSubClassMask[] = {
3826
  0x0cc00000, 0x00000000, 0x00000000, 0x00000000, 
3827
};
3828
3829
static const uint32_t GPRPair_with_gsub_0_in_tGPRSubClassMask[] = {
3830
  0x08800000, 0x00000000, 0x00000000, 0x00000000, 
3831
};
3832
3833
static const uint32_t GPRPair_with_gsub_0_in_hGPRSubClassMask[] = {
3834
  0x15000000, 0x00000000, 0x00000000, 0x00000000, 
3835
};
3836
3837
static const uint32_t GPRPair_with_gsub_0_in_tcGPRSubClassMask[] = {
3838
  0x1a000000, 0x00000000, 0x00000000, 0x00000000, 
3839
};
3840
3841
static const uint32_t GPRPair_with_gsub_1_in_hGPR_and_rGPRSubClassMask[] = {
3842
  0x04000000, 0x00000000, 0x00000000, 0x00000000, 
3843
};
3844
3845
static const uint32_t GPRPair_with_gsub_1_in_tcGPRSubClassMask[] = {
3846
  0x08000000, 0x00000000, 0x00000000, 0x00000000, 
3847
};
3848
3849
static const uint32_t GPRPair_with_gsub_1_in_GPRspSubClassMask[] = {
3850
  0x10000000, 0x00000000, 0x00000000, 0x00000000, 
3851
};
3852
3853
static const uint32_t DPairSpcSubClassMask[] = {
3854
  0xe0000000, 0x00000003, 0x00000000, 0x00000000, 
3855
  0x00000000, 0xfffffc00, 0xffffffff, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
3856
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
3857
  0x00000000, 0x281a1800, 0xc00001fc, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9
3858
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5
3859
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_ssub_12_ssub_13
3860
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_dsub_7
3861
};
3862
3863
static const uint32_t DPairSpc_with_ssub_0SubClassMask[] = {
3864
  0xc0000000, 0x00000003, 0x00000000, 0x00000000, 
3865
  0x00000000, 0xfffeb000, 0xbfffcdfb, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
3866
  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
3867
  0x00000000, 0x281a0000, 0x000001f0, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9
3868
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5
3869
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_ssub_12_ssub_13
3870
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_dsub_7
3871
};
3872
3873
static const uint32_t DPairSpc_with_ssub_4SubClassMask[] = {
3874
  0x80000000, 0x00000003, 0x00000000, 0x00000000, 
3875
  0x00000000, 0xff3e0000, 0x3ff9c1f3, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
3876
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
3877
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9
3878
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5
3879
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_ssub_12_ssub_13
3880
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_dsub_7
3881
};
3882
3883
static const uint32_t DPairSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
3884
  0x00000000, 0x00000003, 0x00000000, 0x00000000, 
3885
  0x00000000, 0xf9300000, 0x3f4901c3, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5
3886
  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7
3887
  0x00000000, 0x28000000, 0x00000180, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9
3888
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5
3889
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_ssub_12_ssub_13
3890
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_dsub_7
3891
};
3892
3893
static const uint32_t DPairSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
3894
  0x00000000, 0x00000002, 0x00000000, 0x00000000, 
3895
  0x00000000, 0x38000000, 0x39400183, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5
3896
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7
3897
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9
3898
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5
3899
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_ssub_12_ssub_13
3900
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_dsub_7
3901
};
3902
3903
static const uint32_t DPairSubClassMask[] = {
3904
  0x00000000, 0x000003fc, 0x00000000, 0x00000000, 
3905
  0x00000000, 0xd7e5e400, 0xfffffe03, 0x0000007f, // qsub_0
3906
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // qsub_1
3907
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_2
3908
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_3
3909
  0x00000000, 0xd7e5e400, 0xfffffe03, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
3910
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9
3911
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13
3912
};
3913
3914
static const uint32_t DPair_with_ssub_0SubClassMask[] = {
3915
  0x00000000, 0x000003e8, 0x00000000, 0x00000000, 
3916
  0x00000000, 0xd7e4a000, 0xbfffcc03, 0x0000007f, // qsub_0
3917
  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // qsub_1
3918
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
3919
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
3920
  0x00000000, 0xd7648000, 0xbffbc803, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
3921
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9
3922
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13
3923
};
3924
3925
static const uint32_t QPRSubClassMask[] = {
3926
  0x00000000, 0x00000290, 0x00000000, 0x00000000, 
3927
  0x00000000, 0x84404000, 0xcc121001, 0x0000007f, // qsub_0
3928
  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // qsub_1
3929
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_2
3930
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_3
3931
  0x00000000, 0x42810000, 0x32a42002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3932
};
3933
3934
static const uint32_t DPair_with_ssub_2SubClassMask[] = {
3935
  0x00000000, 0x000003e0, 0x00000000, 0x00000000, 
3936
  0x00000000, 0xd7648000, 0xbffbc803, 0x0000007f, // qsub_0
3937
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // qsub_1
3938
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
3939
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
3940
  0x00000000, 0xd7240000, 0x3ff9c003, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
3941
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9
3942
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13
3943
};
3944
3945
static const uint32_t DPair_with_dsub_0_in_DPR_8SubClassMask[] = {
3946
  0x00000000, 0x00000340, 0x00000000, 0x00000000, 
3947
  0x00000000, 0xd1200000, 0x3f490003, 0x00000078, // qsub_0
3948
  0x00000000, 0x00000000, 0x39400000, 0x00000070, // qsub_1
3949
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
3950
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
3951
  0x00000000, 0x91000000, 0x3d480003, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5
3952
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9
3953
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13
3954
};
3955
3956
static const uint32_t QPR_VFP2SubClassMask[] = {
3957
  0x00000000, 0x00000280, 0x00000000, 0x00000000, 
3958
  0x00000000, 0x84400000, 0x8c120001, 0x0000007f, // qsub_0
3959
  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // qsub_1
3960
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
3961
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
3962
  0x00000000, 0x42000000, 0x32a00002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3963
};
3964
3965
static const uint32_t DPair_with_dsub_1_in_DPR_8SubClassMask[] = {
3966
  0x00000000, 0x00000300, 0x00000000, 0x00000000, 
3967
  0x00000000, 0x91000000, 0x3d480003, 0x00000078, // qsub_0
3968
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // qsub_1
3969
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
3970
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
3971
  0x00000000, 0x10000000, 0x39400003, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5
3972
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9
3973
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13
3974
};
3975
3976
static const uint32_t QPR_8SubClassMask[] = {
3977
  0x00000000, 0x00000200, 0x00000000, 0x00000000, 
3978
  0x00000000, 0x80000000, 0x0c000001, 0x00000078, // qsub_0
3979
  0x00000000, 0x00000000, 0x08000000, 0x00000070, // qsub_1
3980
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
3981
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
3982
  0x00000000, 0x00000000, 0x30000002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3983
};
3984
3985
static const uint32_t DTripleSubClassMask[] = {
3986
  0x00000000, 0xd7e5e400, 0x00000003, 0x00000000, 
3987
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3988
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3989
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3990
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
3991
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3992
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13_dsub_7
3993
};
3994
3995
static const uint32_t DTripleSpcSubClassMask[] = {
3996
  0x00000000, 0x281a1800, 0x000001fc, 0x00000000, 
3997
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
3998
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
3999
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4000
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
4001
};
4002
4003
static const uint32_t DTripleSpc_with_ssub_0SubClassMask[] = {
4004
  0x00000000, 0x281a1000, 0x000001f8, 0x00000000, 
4005
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4006
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4007
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4008
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
4009
};
4010
4011
static const uint32_t DTriple_with_ssub_0SubClassMask[] = {
4012
  0x00000000, 0xd7e4a000, 0x00000003, 0x00000000, 
4013
  0x00000000, 0x00000000, 0xbfffcc00, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4014
  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4015
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4016
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4017
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4018
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13_dsub_7
4019
};
4020
4021
static const uint32_t DTriple_with_qsub_0_in_QPRSubClassMask[] = {
4022
  0x00000000, 0x84404000, 0x00000001, 0x00000000, 
4023
  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4024
  0x00000000, 0x00000000, 0x32a42000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4025
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4026
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4027
};
4028
4029
static const uint32_t DTriple_with_ssub_2SubClassMask[] = {
4030
  0x00000000, 0xd7648000, 0x00000003, 0x00000000, 
4031
  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4032
  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4033
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4034
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4035
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4036
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
4037
};
4038
4039
static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4040
  0x00000000, 0x42810000, 0x00000002, 0x00000000, 
4041
  0x00000000, 0x00000000, 0x32a42000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4042
  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4043
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4044
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13_dsub_7
4045
};
4046
4047
static const uint32_t DTripleSpc_with_ssub_4SubClassMask[] = {
4048
  0x00000000, 0x281a0000, 0x000001f0, 0x00000000, 
4049
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4050
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4051
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4052
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5_dsub_7
4053
};
4054
4055
static const uint32_t DTriple_with_ssub_4SubClassMask[] = {
4056
  0x00000000, 0xd7240000, 0x00000003, 0x00000000, 
4057
  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4058
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4059
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4060
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4061
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4062
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
4063
};
4064
4065
static const uint32_t DTripleSpc_with_ssub_8SubClassMask[] = {
4066
  0x00000000, 0x28180000, 0x000001e0, 0x00000000, 
4067
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4068
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4069
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4070
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_dsub_5_dsub_7
4071
};
4072
4073
static const uint32_t DTripleSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
4074
  0x00000000, 0x28100000, 0x000001c0, 0x00000000, 
4075
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4076
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4077
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4078
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5_dsub_7
4079
};
4080
4081
static const uint32_t DTriple_with_dsub_0_in_DPR_8SubClassMask[] = {
4082
  0x00000000, 0xd1200000, 0x00000003, 0x00000000, 
4083
  0x00000000, 0x00000000, 0x3f490000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4084
  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4085
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4086
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4087
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4088
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13_dsub_7
4089
};
4090
4091
static const uint32_t DTriple_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
4092
  0x00000000, 0x84400000, 0x00000001, 0x00000000, 
4093
  0x00000000, 0x00000000, 0x8c120000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4094
  0x00000000, 0x00000000, 0x32a00000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4095
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4096
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4097
};
4098
4099
static const uint32_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4100
  0x00000000, 0x42800000, 0x00000002, 0x00000000, 
4101
  0x00000000, 0x00000000, 0x32a40000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4102
  0x00000000, 0x00000000, 0x8c120000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4103
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4104
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13_dsub_7
4105
};
4106
4107
static const uint32_t DTriple_with_dsub_1_in_DPR_8SubClassMask[] = {
4108
  0x00000000, 0x91000000, 0x00000003, 0x00000000, 
4109
  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4110
  0x00000000, 0x00000000, 0x39400000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4111
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4112
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4113
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4114
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
4115
};
4116
4117
static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
4118
  0x00000000, 0x42000000, 0x00000002, 0x00000000, 
4119
  0x00000000, 0x00000000, 0x32a00000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4120
  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4121
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4122
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
4123
};
4124
4125
static const uint32_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
4126
  0x00000000, 0x84000000, 0x00000001, 0x00000000, 
4127
  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4128
  0x00000000, 0x00000000, 0x32800000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4129
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4130
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4131
};
4132
4133
static const uint32_t DTripleSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
4134
  0x00000000, 0x28000000, 0x00000180, 0x00000000, 
4135
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4136
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4137
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4138
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5_dsub_7
4139
};
4140
4141
static const uint32_t DTriple_with_dsub_2_in_DPR_8SubClassMask[] = {
4142
  0x00000000, 0x10000000, 0x00000003, 0x00000000, 
4143
  0x00000000, 0x00000000, 0x39400000, 0x00000070, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4144
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4145
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4146
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4147
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4148
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
4149
};
4150
4151
static const uint32_t DTripleSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
4152
  0x00000000, 0x20000000, 0x00000100, 0x00000000, 
4153
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4154
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4155
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4156
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_dsub_5_dsub_7
4157
};
4158
4159
static const uint32_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4160
  0x00000000, 0x40000000, 0x00000002, 0x00000000, 
4161
  0x00000000, 0x00000000, 0x32000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4162
  0x00000000, 0x00000000, 0x0c000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4163
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4164
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13_dsub_7
4165
};
4166
4167
static const uint32_t DTriple_with_qsub_0_in_QPR_8SubClassMask[] = {
4168
  0x00000000, 0x80000000, 0x00000001, 0x00000000, 
4169
  0x00000000, 0x00000000, 0x0c000000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4170
  0x00000000, 0x00000000, 0x30000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4171
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4172
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4173
};
4174
4175
static const uint32_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
4176
  0x00000000, 0x00000000, 0x00000001, 0x00000000, 
4177
  0x00000000, 0x00000000, 0x08000000, 0x00000070, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4178
  0x00000000, 0x00000000, 0x20000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4179
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4180
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4181
};
4182
4183
static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
4184
  0x00000000, 0x00000000, 0x00000002, 0x00000000, 
4185
  0x00000000, 0x00000000, 0x30000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4186
  0x00000000, 0x00000000, 0x08000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4187
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4188
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
4189
};
4190
4191
static const uint32_t DQuadSpcSubClassMask[] = {
4192
  0x00000000, 0x00000000, 0x000001fc, 0x00000000, 
4193
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4194
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4195
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4196
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
4197
};
4198
4199
static const uint32_t DQuadSpc_with_ssub_0SubClassMask[] = {
4200
  0x00000000, 0x00000000, 0x000001f8, 0x00000000, 
4201
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4202
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4203
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4204
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
4205
};
4206
4207
static const uint32_t DQuadSpc_with_ssub_4SubClassMask[] = {
4208
  0x00000000, 0x00000000, 0x000001f0, 0x00000000, 
4209
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4210
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4211
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4212
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5_dsub_7
4213
};
4214
4215
static const uint32_t DQuadSpc_with_ssub_8SubClassMask[] = {
4216
  0x00000000, 0x00000000, 0x000001e0, 0x00000000, 
4217
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4218
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4219
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4220
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_dsub_5_dsub_7
4221
};
4222
4223
static const uint32_t DQuadSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
4224
  0x00000000, 0x00000000, 0x000001c0, 0x00000000, 
4225
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4226
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4227
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4228
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5_dsub_7
4229
};
4230
4231
static const uint32_t DQuadSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
4232
  0x00000000, 0x00000000, 0x00000180, 0x00000000, 
4233
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4234
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4235
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4236
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5_dsub_7
4237
};
4238
4239
static const uint32_t DQuadSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
4240
  0x00000000, 0x00000000, 0x00000100, 0x00000000, 
4241
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4242
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4243
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4244
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_dsub_5_dsub_7
4245
};
4246
4247
static const uint32_t DQuadSubClassMask[] = {
4248
  0x00000000, 0x00000000, 0x3ffffe00, 0x00000000, 
4249
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_0
4250
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_1
4251
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4252
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4253
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4254
};
4255
4256
static const uint32_t DQuad_with_ssub_0SubClassMask[] = {
4257
  0x00000000, 0x00000000, 0x3fffcc00, 0x00000000, 
4258
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
4259
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
4260
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4261
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4262
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4263
};
4264
4265
static const uint32_t DQuad_with_ssub_2SubClassMask[] = {
4266
  0x00000000, 0x00000000, 0x3ffbc800, 0x00000000, 
4267
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
4268
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
4269
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4270
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4271
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4272
};
4273
4274
static const uint32_t QQPRSubClassMask[] = {
4275
  0x00000000, 0x00000000, 0x0c121000, 0x00000000, 
4276
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_0
4277
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_1
4278
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4279
};
4280
4281
static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4282
  0x00000000, 0x00000000, 0x32a42000, 0x00000000, 
4283
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4284
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4285
};
4286
4287
static const uint32_t DQuad_with_ssub_4SubClassMask[] = {
4288
  0x00000000, 0x00000000, 0x3ff9c000, 0x00000000, 
4289
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
4290
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
4291
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4292
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4293
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4294
};
4295
4296
static const uint32_t DQuad_with_ssub_6SubClassMask[] = {
4297
  0x00000000, 0x00000000, 0x3fd98000, 0x00000000, 
4298
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
4299
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
4300
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4301
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4302
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4303
};
4304
4305
static const uint32_t DQuad_with_dsub_0_in_DPR_8SubClassMask[] = {
4306
  0x00000000, 0x00000000, 0x3f490000, 0x00000000, 
4307
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
4308
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
4309
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4310
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4311
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4312
};
4313
4314
static const uint32_t DQuad_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
4315
  0x00000000, 0x00000000, 0x0c120000, 0x00000000, 
4316
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
4317
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
4318
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4319
};
4320
4321
static const uint32_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4322
  0x00000000, 0x00000000, 0x32a40000, 0x00000000, 
4323
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4324
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4325
};
4326
4327
static const uint32_t DQuad_with_dsub_1_in_DPR_8SubClassMask[] = {
4328
  0x00000000, 0x00000000, 0x3d480000, 0x00000000, 
4329
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
4330
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
4331
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4332
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4333
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4334
};
4335
4336
static const uint32_t DQuad_with_qsub_1_in_QPR_VFP2SubClassMask[] = {
4337
  0x00000000, 0x00000000, 0x0c100000, 0x00000000, 
4338
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
4339
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
4340
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4341
};
4342
4343
static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
4344
  0x00000000, 0x00000000, 0x32a00000, 0x00000000, 
4345
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4346
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4347
};
4348
4349
static const uint32_t DQuad_with_dsub_2_in_DPR_8SubClassMask[] = {
4350
  0x00000000, 0x00000000, 0x39400000, 0x00000000, 
4351
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
4352
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
4353
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4354
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4355
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4356
};
4357
4358
static const uint32_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4359
  0x00000000, 0x00000000, 0x32800000, 0x00000000, 
4360
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4361
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4362
};
4363
4364
static const uint32_t DQuad_with_dsub_3_in_DPR_8SubClassMask[] = {
4365
  0x00000000, 0x00000000, 0x29000000, 0x00000000, 
4366
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
4367
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
4368
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4369
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4370
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4371
};
4372
4373
static const uint32_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4374
  0x00000000, 0x00000000, 0x32000000, 0x00000000, 
4375
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4376
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4377
};
4378
4379
static const uint32_t DQuad_with_qsub_0_in_QPR_8SubClassMask[] = {
4380
  0x00000000, 0x00000000, 0x0c000000, 0x00000000, 
4381
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
4382
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
4383
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4384
};
4385
4386
static const uint32_t DQuad_with_qsub_1_in_QPR_8SubClassMask[] = {
4387
  0x00000000, 0x00000000, 0x08000000, 0x00000000, 
4388
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
4389
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
4390
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4391
};
4392
4393
static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
4394
  0x00000000, 0x00000000, 0x30000000, 0x00000000, 
4395
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4396
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4397
};
4398
4399
static const uint32_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4400
  0x00000000, 0x00000000, 0x20000000, 0x00000000, 
4401
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4402
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4403
};
4404
4405
static const uint32_t QQQQPRSubClassMask[] = {
4406
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, 
4407
};
4408
4409
static const uint32_t QQQQPR_with_ssub_0SubClassMask[] = {
4410
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, 
4411
};
4412
4413
static const uint32_t QQQQPR_with_ssub_4SubClassMask[] = {
4414
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, 
4415
};
4416
4417
static const uint32_t QQQQPR_with_ssub_8SubClassMask[] = {
4418
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, 
4419
};
4420
4421
static const uint32_t QQQQPR_with_ssub_12SubClassMask[] = {
4422
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, 
4423
};
4424
4425
static const uint32_t QQQQPR_with_dsub_0_in_DPR_8SubClassMask[] = {
4426
  0x00000000, 0x00000000, 0x00000000, 0x00000078, 
4427
};
4428
4429
static const uint32_t QQQQPR_with_dsub_2_in_DPR_8SubClassMask[] = {
4430
  0x00000000, 0x00000000, 0x00000000, 0x00000070, 
4431
};
4432
4433
static const uint32_t QQQQPR_with_dsub_4_in_DPR_8SubClassMask[] = {
4434
  0x00000000, 0x00000000, 0x00000000, 0x00000060, 
4435
};
4436
4437
static const uint32_t QQQQPR_with_dsub_6_in_DPR_8SubClassMask[] = {
4438
  0x00000000, 0x00000000, 0x00000000, 0x00000040, 
4439
};
4440
4441
static const uint16_t SuperRegIdxSeqs[] = {
4442
  /* 0 */ 1, 2, 3, 4, 5, 6, 7, 8, 0,
4443
  /* 9 */ 9, 0,
4444
  /* 11 */ 9, 10, 0,
4445
  /* 14 */ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0,
4446
  /* 31 */ 13, 14, 15, 16, 37, 0,
4447
  /* 37 */ 38, 40, 45, 48, 0,
4448
  /* 42 */ 42, 50, 0,
4449
  /* 45 */ 34, 36, 44, 52, 0,
4450
  /* 50 */ 33, 35, 43, 46, 51, 53, 0,
4451
  /* 57 */ 34, 36, 47, 54, 0,
4452
  /* 62 */ 34, 36, 44, 47, 52, 54, 0,
4453
  /* 69 */ 13, 14, 15, 16, 37, 49, 55, 0,
4454
  /* 77 */ 11, 12, 56, 0,
4455
  /* 81 */ 11, 12, 42, 50, 56, 0,
4456
};
4457
4458
static const TargetRegisterClass *const SPRSuperclasses[] = {
4459
  &ARM::HPRRegClass,
4460
  nullptr
4461
};
4462
4463
static const TargetRegisterClass *const SPR_8Superclasses[] = {
4464
  &ARM::HPRRegClass,
4465
  &ARM::SPRRegClass,
4466
  nullptr
4467
};
4468
4469
static const TargetRegisterClass *const GPRnopcSuperclasses[] = {
4470
  &ARM::GPRRegClass,
4471
  &ARM::GPRwithAPSRRegClass,
4472
  nullptr
4473
};
4474
4475
static const TargetRegisterClass *const rGPRSuperclasses[] = {
4476
  &ARM::GPRRegClass,
4477
  &ARM::GPRwithAPSRRegClass,
4478
  &ARM::GPRnopcRegClass,
4479
  nullptr
4480
};
4481
4482
static const TargetRegisterClass *const tGPRwithpcSuperclasses[] = {
4483
  &ARM::GPRRegClass,
4484
  nullptr
4485
};
4486
4487
static const TargetRegisterClass *const hGPRSuperclasses[] = {
4488
  &ARM::GPRRegClass,
4489
  nullptr
4490
};
4491
4492
static const TargetRegisterClass *const tGPRSuperclasses[] = {
4493
  &ARM::GPRRegClass,
4494
  &ARM::GPRwithAPSRRegClass,
4495
  &ARM::GPRnopcRegClass,
4496
  &ARM::rGPRRegClass,
4497
  &ARM::tGPRwithpcRegClass,
4498
  nullptr
4499
};
4500
4501
static const TargetRegisterClass *const GPRnopc_and_hGPRSuperclasses[] = {
4502
  &ARM::GPRRegClass,
4503
  &ARM::GPRwithAPSRRegClass,
4504
  &ARM::GPRnopcRegClass,
4505
  &ARM::hGPRRegClass,
4506
  nullptr
4507
};
4508
4509
static const TargetRegisterClass *const hGPR_and_rGPRSuperclasses[] = {
4510
  &ARM::GPRRegClass,
4511
  &ARM::GPRwithAPSRRegClass,
4512
  &ARM::GPRnopcRegClass,
4513
  &ARM::rGPRRegClass,
4514
  &ARM::hGPRRegClass,
4515
  &ARM::GPRnopc_and_hGPRRegClass,
4516
  nullptr
4517
};
4518
4519
static const TargetRegisterClass *const tcGPRSuperclasses[] = {
4520
  &ARM::GPRRegClass,
4521
  &ARM::GPRwithAPSRRegClass,
4522
  &ARM::GPRnopcRegClass,
4523
  &ARM::rGPRRegClass,
4524
  nullptr
4525
};
4526
4527
static const TargetRegisterClass *const tGPR_and_tcGPRSuperclasses[] = {
4528
  &ARM::GPRRegClass,
4529
  &ARM::GPRwithAPSRRegClass,
4530
  &ARM::GPRnopcRegClass,
4531
  &ARM::rGPRRegClass,
4532
  &ARM::tGPRwithpcRegClass,
4533
  &ARM::tGPRRegClass,
4534
  &ARM::tcGPRRegClass,
4535
  nullptr
4536
};
4537
4538
static const TargetRegisterClass *const GPRspSuperclasses[] = {
4539
  &ARM::GPRRegClass,
4540
  &ARM::GPRwithAPSRRegClass,
4541
  &ARM::GPRnopcRegClass,
4542
  &ARM::hGPRRegClass,
4543
  &ARM::GPRnopc_and_hGPRRegClass,
4544
  nullptr
4545
};
4546
4547
static const TargetRegisterClass *const hGPR_and_tGPRwithpcSuperclasses[] = {
4548
  &ARM::GPRRegClass,
4549
  &ARM::tGPRwithpcRegClass,
4550
  &ARM::hGPRRegClass,
4551
  nullptr
4552
};
4553
4554
static const TargetRegisterClass *const hGPR_and_tcGPRSuperclasses[] = {
4555
  &ARM::GPRRegClass,
4556
  &ARM::GPRwithAPSRRegClass,
4557
  &ARM::GPRnopcRegClass,
4558
  &ARM::rGPRRegClass,
4559
  &ARM::hGPRRegClass,
4560
  &ARM::GPRnopc_and_hGPRRegClass,
4561
  &ARM::hGPR_and_rGPRRegClass,
4562
  &ARM::tcGPRRegClass,
4563
  nullptr
4564
};
4565
4566
static const TargetRegisterClass *const DPR_VFP2Superclasses[] = {
4567
  &ARM::DPRRegClass,
4568
  nullptr
4569
};
4570
4571
static const TargetRegisterClass *const DPR_8Superclasses[] = {
4572
  &ARM::DPRRegClass,
4573
  &ARM::DPR_VFP2RegClass,
4574
  nullptr
4575
};
4576
4577
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_rGPRSuperclasses[] = {
4578
  &ARM::GPRPairRegClass,
4579
  nullptr
4580
};
4581
4582
static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tGPRSuperclasses[] = {
4583
  &ARM::GPRPairRegClass,
4584
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4585
  nullptr
4586
};
4587
4588
static const TargetRegisterClass *const GPRPair_with_gsub_0_in_hGPRSuperclasses[] = {
4589
  &ARM::GPRPairRegClass,
4590
  nullptr
4591
};
4592
4593
static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tcGPRSuperclasses[] = {
4594
  &ARM::GPRPairRegClass,
4595
  nullptr
4596
};
4597
4598
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_hGPR_and_rGPRSuperclasses[] = {
4599
  &ARM::GPRPairRegClass,
4600
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4601
  &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
4602
  nullptr
4603
};
4604
4605
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_tcGPRSuperclasses[] = {
4606
  &ARM::GPRPairRegClass,
4607
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4608
  &ARM::GPRPair_with_gsub_0_in_tGPRRegClass,
4609
  &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
4610
  nullptr
4611
};
4612
4613
static const TargetRegisterClass *const GPRPair_with_gsub_1_in_GPRspSuperclasses[] = {
4614
  &ARM::GPRPairRegClass,
4615
  &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
4616
  &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
4617
  nullptr
4618
};
4619
4620
static const TargetRegisterClass *const DPairSpc_with_ssub_0Superclasses[] = {
4621
  &ARM::DPairSpcRegClass,
4622
  nullptr
4623
};
4624
4625
static const TargetRegisterClass *const DPairSpc_with_ssub_4Superclasses[] = {
4626
  &ARM::DPairSpcRegClass,
4627
  &ARM::DPairSpc_with_ssub_0RegClass,
4628
  nullptr
4629
};
4630
4631
static const TargetRegisterClass *const DPairSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4632
  &ARM::DPairSpcRegClass,
4633
  &ARM::DPairSpc_with_ssub_0RegClass,
4634
  &ARM::DPairSpc_with_ssub_4RegClass,
4635
  nullptr
4636
};
4637
4638
static const TargetRegisterClass *const DPairSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4639
  &ARM::DPairSpcRegClass,
4640
  &ARM::DPairSpc_with_ssub_0RegClass,
4641
  &ARM::DPairSpc_with_ssub_4RegClass,
4642
  &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass,
4643
  nullptr
4644
};
4645
4646
static const TargetRegisterClass *const DPair_with_ssub_0Superclasses[] = {
4647
  &ARM::DPairRegClass,
4648
  nullptr
4649
};
4650
4651
static const TargetRegisterClass *const QPRSuperclasses[] = {
4652
  &ARM::DPairRegClass,
4653
  nullptr
4654
};
4655
4656
static const TargetRegisterClass *const DPair_with_ssub_2Superclasses[] = {
4657
  &ARM::DPairRegClass,
4658
  &ARM::DPair_with_ssub_0RegClass,
4659
  nullptr
4660
};
4661
4662
static const TargetRegisterClass *const DPair_with_dsub_0_in_DPR_8Superclasses[] = {
4663
  &ARM::DPairRegClass,
4664
  &ARM::DPair_with_ssub_0RegClass,
4665
  &ARM::DPair_with_ssub_2RegClass,
4666
  nullptr
4667
};
4668
4669
static const TargetRegisterClass *const QPR_VFP2Superclasses[] = {
4670
  &ARM::DPairRegClass,
4671
  &ARM::DPair_with_ssub_0RegClass,
4672
  &ARM::QPRRegClass,
4673
  &ARM::DPair_with_ssub_2RegClass,
4674
  nullptr
4675
};
4676
4677
static const TargetRegisterClass *const DPair_with_dsub_1_in_DPR_8Superclasses[] = {
4678
  &ARM::DPairRegClass,
4679
  &ARM::DPair_with_ssub_0RegClass,
4680
  &ARM::DPair_with_ssub_2RegClass,
4681
  &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
4682
  nullptr
4683
};
4684
4685
static const TargetRegisterClass *const QPR_8Superclasses[] = {
4686
  &ARM::DPairRegClass,
4687
  &ARM::DPair_with_ssub_0RegClass,
4688
  &ARM::QPRRegClass,
4689
  &ARM::DPair_with_ssub_2RegClass,
4690
  &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
4691
  &ARM::QPR_VFP2RegClass,
4692
  &ARM::DPair_with_dsub_1_in_DPR_8RegClass,
4693
  nullptr
4694
};
4695
4696
static const TargetRegisterClass *const DTripleSpc_with_ssub_0Superclasses[] = {
4697
  &ARM::DTripleSpcRegClass,
4698
  nullptr
4699
};
4700
4701
static const TargetRegisterClass *const DTriple_with_ssub_0Superclasses[] = {
4702
  &ARM::DTripleRegClass,
4703
  nullptr
4704
};
4705
4706
static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4707
  &ARM::DTripleRegClass,
4708
  nullptr
4709
};
4710
4711
static const TargetRegisterClass *const DTriple_with_ssub_2Superclasses[] = {
4712
  &ARM::DTripleRegClass,
4713
  &ARM::DTriple_with_ssub_0RegClass,
4714
  nullptr
4715
};
4716
4717
static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4718
  &ARM::DTripleRegClass,
4719
  nullptr
4720
};
4721
4722
static const TargetRegisterClass *const DTripleSpc_with_ssub_4Superclasses[] = {
4723
  &ARM::DTripleSpcRegClass,
4724
  &ARM::DTripleSpc_with_ssub_0RegClass,
4725
  nullptr
4726
};
4727
4728
static const TargetRegisterClass *const DTriple_with_ssub_4Superclasses[] = {
4729
  &ARM::DTripleRegClass,
4730
  &ARM::DTriple_with_ssub_0RegClass,
4731
  &ARM::DTriple_with_ssub_2RegClass,
4732
  nullptr
4733
};
4734
4735
static const TargetRegisterClass *const DTripleSpc_with_ssub_8Superclasses[] = {
4736
  &ARM::DTripleSpcRegClass,
4737
  &ARM::DTripleSpc_with_ssub_0RegClass,
4738
  &ARM::DTripleSpc_with_ssub_4RegClass,
4739
  nullptr
4740
};
4741
4742
static const TargetRegisterClass *const DTripleSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4743
  &ARM::DTripleSpcRegClass,
4744
  &ARM::DTripleSpc_with_ssub_0RegClass,
4745
  &ARM::DTripleSpc_with_ssub_4RegClass,
4746
  &ARM::DTripleSpc_with_ssub_8RegClass,
4747
  nullptr
4748
};
4749
4750
static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8Superclasses[] = {
4751
  &ARM::DTripleRegClass,
4752
  &ARM::DTriple_with_ssub_0RegClass,
4753
  &ARM::DTriple_with_ssub_2RegClass,
4754
  &ARM::DTriple_with_ssub_4RegClass,
4755
  nullptr
4756
};
4757
4758
static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_VFP2Superclasses[] = {
4759
  &ARM::DTripleRegClass,
4760
  &ARM::DTriple_with_ssub_0RegClass,
4761
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4762
  &ARM::DTriple_with_ssub_2RegClass,
4763
  nullptr
4764
};
4765
4766
static const TargetRegisterClass *const DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4767
  &ARM::DTripleRegClass,
4768
  &ARM::DTriple_with_ssub_0RegClass,
4769
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4770
  nullptr
4771
};
4772
4773
static const TargetRegisterClass *const DTriple_with_dsub_1_in_DPR_8Superclasses[] = {
4774
  &ARM::DTripleRegClass,
4775
  &ARM::DTriple_with_ssub_0RegClass,
4776
  &ARM::DTriple_with_ssub_2RegClass,
4777
  &ARM::DTriple_with_ssub_4RegClass,
4778
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4779
  nullptr
4780
};
4781
4782
static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
4783
  &ARM::DTripleRegClass,
4784
  &ARM::DTriple_with_ssub_0RegClass,
4785
  &ARM::DTriple_with_ssub_2RegClass,
4786
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4787
  &ARM::DTriple_with_ssub_4RegClass,
4788
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4789
  nullptr
4790
};
4791
4792
static const TargetRegisterClass *const DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4793
  &ARM::DTripleRegClass,
4794
  &ARM::DTriple_with_ssub_0RegClass,
4795
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4796
  &ARM::DTriple_with_ssub_2RegClass,
4797
  &ARM::DTriple_with_ssub_4RegClass,
4798
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4799
  nullptr
4800
};
4801
4802
static const TargetRegisterClass *const DTripleSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4803
  &ARM::DTripleSpcRegClass,
4804
  &ARM::DTripleSpc_with_ssub_0RegClass,
4805
  &ARM::DTripleSpc_with_ssub_4RegClass,
4806
  &ARM::DTripleSpc_with_ssub_8RegClass,
4807
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4808
  nullptr
4809
};
4810
4811
static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8Superclasses[] = {
4812
  &ARM::DTripleRegClass,
4813
  &ARM::DTriple_with_ssub_0RegClass,
4814
  &ARM::DTriple_with_ssub_2RegClass,
4815
  &ARM::DTriple_with_ssub_4RegClass,
4816
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4817
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4818
  nullptr
4819
};
4820
4821
static const TargetRegisterClass *const DTripleSpc_with_dsub_4_in_DPR_8Superclasses[] = {
4822
  &ARM::DTripleSpcRegClass,
4823
  &ARM::DTripleSpc_with_ssub_0RegClass,
4824
  &ARM::DTripleSpc_with_ssub_4RegClass,
4825
  &ARM::DTripleSpc_with_ssub_8RegClass,
4826
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4827
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4828
  nullptr
4829
};
4830
4831
static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4832
  &ARM::DTripleRegClass,
4833
  &ARM::DTriple_with_ssub_0RegClass,
4834
  &ARM::DTriple_with_ssub_2RegClass,
4835
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4836
  &ARM::DTriple_with_ssub_4RegClass,
4837
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4838
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4839
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
4840
  nullptr
4841
};
4842
4843
static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_8Superclasses[] = {
4844
  &ARM::DTripleRegClass,
4845
  &ARM::DTriple_with_ssub_0RegClass,
4846
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4847
  &ARM::DTriple_with_ssub_2RegClass,
4848
  &ARM::DTriple_with_ssub_4RegClass,
4849
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4850
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4851
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4852
  &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
4853
  nullptr
4854
};
4855
4856
static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4857
  &ARM::DTripleRegClass,
4858
  &ARM::DTriple_with_ssub_0RegClass,
4859
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4860
  &ARM::DTriple_with_ssub_2RegClass,
4861
  &ARM::DTriple_with_ssub_4RegClass,
4862
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4863
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4864
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4865
  &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
4866
  &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
4867
  &ARM::DTriple_with_qsub_0_in_QPR_8RegClass,
4868
  nullptr
4869
};
4870
4871
static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
4872
  &ARM::DTripleRegClass,
4873
  &ARM::DTriple_with_ssub_0RegClass,
4874
  &ARM::DTriple_with_ssub_2RegClass,
4875
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4876
  &ARM::DTriple_with_ssub_4RegClass,
4877
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4878
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4879
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4880
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
4881
  &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
4882
  &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4883
  nullptr
4884
};
4885
4886
static const TargetRegisterClass *const DQuadSpcSuperclasses[] = {
4887
  &ARM::DTripleSpcRegClass,
4888
  nullptr
4889
};
4890
4891
static const TargetRegisterClass *const DQuadSpc_with_ssub_0Superclasses[] = {
4892
  &ARM::DTripleSpcRegClass,
4893
  &ARM::DTripleSpc_with_ssub_0RegClass,
4894
  &ARM::DQuadSpcRegClass,
4895
  nullptr
4896
};
4897
4898
static const TargetRegisterClass *const DQuadSpc_with_ssub_4Superclasses[] = {
4899
  &ARM::DTripleSpcRegClass,
4900
  &ARM::DTripleSpc_with_ssub_0RegClass,
4901
  &ARM::DTripleSpc_with_ssub_4RegClass,
4902
  &ARM::DQuadSpcRegClass,
4903
  &ARM::DQuadSpc_with_ssub_0RegClass,
4904
  nullptr
4905
};
4906
4907
static const TargetRegisterClass *const DQuadSpc_with_ssub_8Superclasses[] = {
4908
  &ARM::DTripleSpcRegClass,
4909
  &ARM::DTripleSpc_with_ssub_0RegClass,
4910
  &ARM::DTripleSpc_with_ssub_4RegClass,
4911
  &ARM::DTripleSpc_with_ssub_8RegClass,
4912
  &ARM::DQuadSpcRegClass,
4913
  &ARM::DQuadSpc_with_ssub_0RegClass,
4914
  &ARM::DQuadSpc_with_ssub_4RegClass,
4915
  nullptr
4916
};
4917
4918
static const TargetRegisterClass *const DQuadSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4919
  &ARM::DTripleSpcRegClass,
4920
  &ARM::DTripleSpc_with_ssub_0RegClass,
4921
  &ARM::DTripleSpc_with_ssub_4RegClass,
4922
  &ARM::DTripleSpc_with_ssub_8RegClass,
4923
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4924
  &ARM::DQuadSpcRegClass,
4925
  &ARM::DQuadSpc_with_ssub_0RegClass,
4926
  &ARM::DQuadSpc_with_ssub_4RegClass,
4927
  &ARM::DQuadSpc_with_ssub_8RegClass,
4928
  nullptr
4929
};
4930
4931
static const TargetRegisterClass *const DQuadSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4932
  &ARM::DTripleSpcRegClass,
4933
  &ARM::DTripleSpc_with_ssub_0RegClass,
4934
  &ARM::DTripleSpc_with_ssub_4RegClass,
4935
  &ARM::DTripleSpc_with_ssub_8RegClass,
4936
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4937
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4938
  &ARM::DQuadSpcRegClass,
4939
  &ARM::DQuadSpc_with_ssub_0RegClass,
4940
  &ARM::DQuadSpc_with_ssub_4RegClass,
4941
  &ARM::DQuadSpc_with_ssub_8RegClass,
4942
  &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
4943
  nullptr
4944
};
4945
4946
static const TargetRegisterClass *const DQuadSpc_with_dsub_4_in_DPR_8Superclasses[] = {
4947
  &ARM::DTripleSpcRegClass,
4948
  &ARM::DTripleSpc_with_ssub_0RegClass,
4949
  &ARM::DTripleSpc_with_ssub_4RegClass,
4950
  &ARM::DTripleSpc_with_ssub_8RegClass,
4951
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4952
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4953
  &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass,
4954
  &ARM::DQuadSpcRegClass,
4955
  &ARM::DQuadSpc_with_ssub_0RegClass,
4956
  &ARM::DQuadSpc_with_ssub_4RegClass,
4957
  &ARM::DQuadSpc_with_ssub_8RegClass,
4958
  &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
4959
  &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass,
4960
  nullptr
4961
};
4962
4963
static const TargetRegisterClass *const DQuad_with_ssub_0Superclasses[] = {
4964
  &ARM::DQuadRegClass,
4965
  nullptr
4966
};
4967
4968
static const TargetRegisterClass *const DQuad_with_ssub_2Superclasses[] = {
4969
  &ARM::DQuadRegClass,
4970
  &ARM::DQuad_with_ssub_0RegClass,
4971
  nullptr
4972
};
4973
4974
static const TargetRegisterClass *const QQPRSuperclasses[] = {
4975
  &ARM::DQuadRegClass,
4976
  nullptr
4977
};
4978
4979
static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4980
  &ARM::DQuadRegClass,
4981
  nullptr
4982
};
4983
4984
static const TargetRegisterClass *const DQuad_with_ssub_4Superclasses[] = {
4985
  &ARM::DQuadRegClass,
4986
  &ARM::DQuad_with_ssub_0RegClass,
4987
  &ARM::DQuad_with_ssub_2RegClass,
4988
  nullptr
4989
};
4990
4991
static const TargetRegisterClass *const DQuad_with_ssub_6Superclasses[] = {
4992
  &ARM::DQuadRegClass,
4993
  &ARM::DQuad_with_ssub_0RegClass,
4994
  &ARM::DQuad_with_ssub_2RegClass,
4995
  &ARM::DQuad_with_ssub_4RegClass,
4996
  nullptr
4997
};
4998
4999
static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8Superclasses[] = {
5000
  &ARM::DQuadRegClass,
5001
  &ARM::DQuad_with_ssub_0RegClass,
5002
  &ARM::DQuad_with_ssub_2RegClass,
5003
  &ARM::DQuad_with_ssub_4RegClass,
5004
  &ARM::DQuad_with_ssub_6RegClass,
5005
  nullptr
5006
};
5007
5008
static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_VFP2Superclasses[] = {
5009
  &ARM::DQuadRegClass,
5010
  &ARM::DQuad_with_ssub_0RegClass,
5011
  &ARM::DQuad_with_ssub_2RegClass,
5012
  &ARM::QQPRRegClass,
5013
  nullptr
5014
};
5015
5016
static const TargetRegisterClass *const DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5017
  &ARM::DQuadRegClass,
5018
  &ARM::DQuad_with_ssub_0RegClass,
5019
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5020
  nullptr
5021
};
5022
5023
static const TargetRegisterClass *const DQuad_with_dsub_1_in_DPR_8Superclasses[] = {
5024
  &ARM::DQuadRegClass,
5025
  &ARM::DQuad_with_ssub_0RegClass,
5026
  &ARM::DQuad_with_ssub_2RegClass,
5027
  &ARM::DQuad_with_ssub_4RegClass,
5028
  &ARM::DQuad_with_ssub_6RegClass,
5029
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5030
  nullptr
5031
};
5032
5033
static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_VFP2Superclasses[] = {
5034
  &ARM::DQuadRegClass,
5035
  &ARM::DQuad_with_ssub_0RegClass,
5036
  &ARM::DQuad_with_ssub_2RegClass,
5037
  &ARM::QQPRRegClass,
5038
  &ARM::DQuad_with_ssub_4RegClass,
5039
  &ARM::DQuad_with_ssub_6RegClass,
5040
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
5041
  nullptr
5042
};
5043
5044
static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
5045
  &ARM::DQuadRegClass,
5046
  &ARM::DQuad_with_ssub_0RegClass,
5047
  &ARM::DQuad_with_ssub_2RegClass,
5048
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5049
  &ARM::DQuad_with_ssub_4RegClass,
5050
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5051
  nullptr
5052
};
5053
5054
static const TargetRegisterClass *const DQuad_with_dsub_2_in_DPR_8Superclasses[] = {
5055
  &ARM::DQuadRegClass,
5056
  &ARM::DQuad_with_ssub_0RegClass,
5057
  &ARM::DQuad_with_ssub_2RegClass,
5058
  &ARM::DQuad_with_ssub_4RegClass,
5059
  &ARM::DQuad_with_ssub_6RegClass,
5060
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5061
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5062
  nullptr
5063
};
5064
5065
static const TargetRegisterClass *const DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5066
  &ARM::DQuadRegClass,
5067
  &ARM::DQuad_with_ssub_0RegClass,
5068
  &ARM::DQuad_with_ssub_2RegClass,
5069
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5070
  &ARM::DQuad_with_ssub_4RegClass,
5071
  &ARM::DQuad_with_ssub_6RegClass,
5072
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5073
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5074
  nullptr
5075
};
5076
5077
static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8Superclasses[] = {
5078
  &ARM::DQuadRegClass,
5079
  &ARM::DQuad_with_ssub_0RegClass,
5080
  &ARM::DQuad_with_ssub_2RegClass,
5081
  &ARM::DQuad_with_ssub_4RegClass,
5082
  &ARM::DQuad_with_ssub_6RegClass,
5083
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5084
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5085
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5086
  nullptr
5087
};
5088
5089
static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5090
  &ARM::DQuadRegClass,
5091
  &ARM::DQuad_with_ssub_0RegClass,
5092
  &ARM::DQuad_with_ssub_2RegClass,
5093
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5094
  &ARM::DQuad_with_ssub_4RegClass,
5095
  &ARM::DQuad_with_ssub_6RegClass,
5096
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5097
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5098
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5099
  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5100
  nullptr
5101
};
5102
5103
static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_8Superclasses[] = {
5104
  &ARM::DQuadRegClass,
5105
  &ARM::DQuad_with_ssub_0RegClass,
5106
  &ARM::DQuad_with_ssub_2RegClass,
5107
  &ARM::QQPRRegClass,
5108
  &ARM::DQuad_with_ssub_4RegClass,
5109
  &ARM::DQuad_with_ssub_6RegClass,
5110
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5111
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
5112
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5113
  &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
5114
  nullptr
5115
};
5116
5117
static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_8Superclasses[] = {
5118
  &ARM::DQuadRegClass,
5119
  &ARM::DQuad_with_ssub_0RegClass,
5120
  &ARM::DQuad_with_ssub_2RegClass,
5121
  &ARM::QQPRRegClass,
5122
  &ARM::DQuad_with_ssub_4RegClass,
5123
  &ARM::DQuad_with_ssub_6RegClass,
5124
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5125
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
5126
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5127
  &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
5128
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5129
  &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
5130
  &ARM::DQuad_with_qsub_0_in_QPR_8RegClass,
5131
  nullptr
5132
};
5133
5134
static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
5135
  &ARM::DQuadRegClass,
5136
  &ARM::DQuad_with_ssub_0RegClass,
5137
  &ARM::DQuad_with_ssub_2RegClass,
5138
  &ARM::DQuad_with_ssub_2_ssub