/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/ARM/ARMGenSystemRegister.inc
Line | Count | Source (jump to first uncovered line) |
1 | | #ifdef GET_BANKEDREG_DECL |
2 | | enum BankedRegValues { |
3 | | elr_hyp = 0, |
4 | | lr_abt = 1, |
5 | | lr_fiq = 2, |
6 | | lr_irq = 3, |
7 | | lr_mon = 4, |
8 | | lr_svc = 5, |
9 | | lr_und = 6, |
10 | | lr_usr = 7, |
11 | | r10_fiq = 8, |
12 | | r10_usr = 9, |
13 | | r11_fiq = 10, |
14 | | r11_usr = 11, |
15 | | r12_fiq = 12, |
16 | | r12_usr = 13, |
17 | | r8_fiq = 14, |
18 | | r8_usr = 15, |
19 | | r9_fiq = 16, |
20 | | r9_usr = 17, |
21 | | sp_abt = 18, |
22 | | sp_fiq = 19, |
23 | | sp_hyp = 20, |
24 | | sp_irq = 21, |
25 | | sp_mon = 22, |
26 | | sp_svc = 23, |
27 | | sp_und = 24, |
28 | | sp_usr = 25, |
29 | | spsr_abt = 26, |
30 | | spsr_fiq = 27, |
31 | | spsr_hyp = 28, |
32 | | spsr_irq = 29, |
33 | | spsr_mon = 30, |
34 | | spsr_svc = 31, |
35 | | spsr_und = 32, |
36 | | }; |
37 | | #endif |
38 | | |
39 | | #ifdef GET_MCLASSSYSREG_DECL |
40 | | enum MClassSysRegValues { |
41 | | apsr_g = 1024, |
42 | | apsr_nzcvqg = 3072, |
43 | | iapsr_g = 1025, |
44 | | iapsr_nzcvqg = 3073, |
45 | | eapsr_g = 1026, |
46 | | eapsr_nzcvqg = 3074, |
47 | | xpsr_g = 1027, |
48 | | xpsr_nzcvqg = 3075, |
49 | | apsr = 2048, |
50 | | apsr_nzcvq = 2048, |
51 | | iapsr = 2049, |
52 | | iapsr_nzcvq = 2049, |
53 | | eapsr = 2050, |
54 | | eapsr_nzcvq = 2050, |
55 | | xpsr = 2051, |
56 | | xpsr_nzcvq = 2051, |
57 | | ipsr = 2053, |
58 | | epsr = 2054, |
59 | | iepsr = 2055, |
60 | | msp = 2056, |
61 | | psp = 2057, |
62 | | msplim = 2058, |
63 | | psplim = 2059, |
64 | | primask = 2064, |
65 | | basepri = 2065, |
66 | | basepri_max = 2066, |
67 | | faultmask = 2067, |
68 | | control = 2068, |
69 | | msp_ns = 2184, |
70 | | psp_ns = 2185, |
71 | | msplim_ns = 2186, |
72 | | psplim_ns = 2187, |
73 | | primask_ns = 2192, |
74 | | basepri_ns = 2193, |
75 | | faultmask_ns = 2195, |
76 | | control_ns = 2196, |
77 | | sp_ns = 2200, |
78 | | }; |
79 | | #endif |
80 | | |
81 | | #ifdef GET_BANKEDREG_DECL |
82 | | const BankedReg *lookupBankedRegByName(StringRef Name); |
83 | | const BankedReg *lookupBankedRegByEncoding(uint8_t Encoding); |
84 | | #endif |
85 | | |
86 | | #ifdef GET_BANKEDREG_IMPL |
87 | | const BankedReg BankedRegsList[] = { |
88 | | { "r8_usr", 0x0 }, // 0 |
89 | | { "r9_usr", 0x1 }, // 1 |
90 | | { "r10_usr", 0x2 }, // 2 |
91 | | { "r11_usr", 0x3 }, // 3 |
92 | | { "r12_usr", 0x4 }, // 4 |
93 | | { "sp_usr", 0x5 }, // 5 |
94 | | { "lr_usr", 0x6 }, // 6 |
95 | | { "r8_fiq", 0x8 }, // 7 |
96 | | { "r9_fiq", 0x9 }, // 8 |
97 | | { "r10_fiq", 0xA }, // 9 |
98 | | { "r11_fiq", 0xB }, // 10 |
99 | | { "r12_fiq", 0xC }, // 11 |
100 | | { "sp_fiq", 0xD }, // 12 |
101 | | { "lr_fiq", 0xE }, // 13 |
102 | | { "lr_irq", 0x10 }, // 14 |
103 | | { "sp_irq", 0x11 }, // 15 |
104 | | { "lr_svc", 0x12 }, // 16 |
105 | | { "sp_svc", 0x13 }, // 17 |
106 | | { "lr_abt", 0x14 }, // 18 |
107 | | { "sp_abt", 0x15 }, // 19 |
108 | | { "lr_und", 0x16 }, // 20 |
109 | | { "sp_und", 0x17 }, // 21 |
110 | | { "lr_mon", 0x1C }, // 22 |
111 | | { "sp_mon", 0x1D }, // 23 |
112 | | { "elr_hyp", 0x1E }, // 24 |
113 | | { "sp_hyp", 0x1F }, // 25 |
114 | | { "spsr_fiq", 0x2E }, // 26 |
115 | | { "spsr_irq", 0x30 }, // 27 |
116 | | { "spsr_svc", 0x32 }, // 28 |
117 | | { "spsr_abt", 0x34 }, // 29 |
118 | | { "spsr_und", 0x36 }, // 30 |
119 | | { "spsr_mon", 0x3C }, // 31 |
120 | | { "spsr_hyp", 0x3E }, // 32 |
121 | | }; |
122 | | |
123 | 365 | const BankedReg *lookupBankedRegByName(StringRef Name) { |
124 | 365 | struct IndexType { |
125 | 365 | const char * Name; |
126 | 365 | unsigned _index; |
127 | 365 | }; |
128 | 365 | static const struct IndexType Index[] = { |
129 | 365 | { "ELR_HYP", 24 }, |
130 | 365 | { "LR_ABT", 18 }, |
131 | 365 | { "LR_FIQ", 13 }, |
132 | 365 | { "LR_IRQ", 14 }, |
133 | 365 | { "LR_MON", 22 }, |
134 | 365 | { "LR_SVC", 16 }, |
135 | 365 | { "LR_UND", 20 }, |
136 | 365 | { "LR_USR", 6 }, |
137 | 365 | { "R10_FIQ", 9 }, |
138 | 365 | { "R10_USR", 2 }, |
139 | 365 | { "R11_FIQ", 10 }, |
140 | 365 | { "R11_USR", 3 }, |
141 | 365 | { "R12_FIQ", 11 }, |
142 | 365 | { "R12_USR", 4 }, |
143 | 365 | { "R8_FIQ", 7 }, |
144 | 365 | { "R8_USR", 0 }, |
145 | 365 | { "R9_FIQ", 8 }, |
146 | 365 | { "R9_USR", 1 }, |
147 | 365 | { "SPSR_ABT", 29 }, |
148 | 365 | { "SPSR_FIQ", 26 }, |
149 | 365 | { "SPSR_HYP", 32 }, |
150 | 365 | { "SPSR_IRQ", 27 }, |
151 | 365 | { "SPSR_MON", 31 }, |
152 | 365 | { "SPSR_SVC", 28 }, |
153 | 365 | { "SPSR_UND", 30 }, |
154 | 365 | { "SP_ABT", 19 }, |
155 | 365 | { "SP_FIQ", 12 }, |
156 | 365 | { "SP_HYP", 25 }, |
157 | 365 | { "SP_IRQ", 15 }, |
158 | 365 | { "SP_MON", 23 }, |
159 | 365 | { "SP_SVC", 17 }, |
160 | 365 | { "SP_UND", 21 }, |
161 | 365 | { "SP_USR", 5 }, |
162 | 365 | }; |
163 | 365 | |
164 | 365 | struct KeyType { |
165 | 365 | std::string Name; |
166 | 365 | }; |
167 | 365 | KeyType Key = { Name.upper() }; |
168 | 365 | auto Table = makeArrayRef(Index); |
169 | 365 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, |
170 | 1.99k | [](const IndexType &LHS, const KeyType &RHS) { |
171 | 1.99k | int CmpName = StringRef(LHS.Name).compare(RHS.Name); |
172 | 1.99k | if (CmpName < 0) return true636 ; |
173 | 1.36k | if (CmpName > 0) return false1.22k ; |
174 | 132 | return false; |
175 | 132 | }); |
176 | 365 | |
177 | 365 | if (Idx == Table.end() || |
178 | 365 | Key.Name != Idx->Name350 ) |
179 | 233 | return nullptr; |
180 | 132 | return &BankedRegsList[Idx->_index]; |
181 | 132 | } |
182 | | |
183 | 402 | const BankedReg *lookupBankedRegByEncoding(uint8_t Encoding) { |
184 | 402 | struct IndexType { |
185 | 402 | uint8_t Encoding; |
186 | 402 | unsigned _index; |
187 | 402 | }; |
188 | 402 | static const struct IndexType Index[] = { |
189 | 402 | { 0x0, 0 }, |
190 | 402 | { 0x1, 1 }, |
191 | 402 | { 0x2, 2 }, |
192 | 402 | { 0x3, 3 }, |
193 | 402 | { 0x4, 4 }, |
194 | 402 | { 0x5, 5 }, |
195 | 402 | { 0x6, 6 }, |
196 | 402 | { 0x8, 7 }, |
197 | 402 | { 0x9, 8 }, |
198 | 402 | { 0xA, 9 }, |
199 | 402 | { 0xB, 10 }, |
200 | 402 | { 0xC, 11 }, |
201 | 402 | { 0xD, 12 }, |
202 | 402 | { 0xE, 13 }, |
203 | 402 | { 0x10, 14 }, |
204 | 402 | { 0x11, 15 }, |
205 | 402 | { 0x12, 16 }, |
206 | 402 | { 0x13, 17 }, |
207 | 402 | { 0x14, 18 }, |
208 | 402 | { 0x15, 19 }, |
209 | 402 | { 0x16, 20 }, |
210 | 402 | { 0x17, 21 }, |
211 | 402 | { 0x1C, 22 }, |
212 | 402 | { 0x1D, 23 }, |
213 | 402 | { 0x1E, 24 }, |
214 | 402 | { 0x1F, 25 }, |
215 | 402 | { 0x2E, 26 }, |
216 | 402 | { 0x30, 27 }, |
217 | 402 | { 0x32, 28 }, |
218 | 402 | { 0x34, 29 }, |
219 | 402 | { 0x36, 30 }, |
220 | 402 | { 0x3C, 31 }, |
221 | 402 | { 0x3E, 32 }, |
222 | 402 | }; |
223 | 402 | |
224 | 402 | struct KeyType { |
225 | 402 | uint8_t Encoding; |
226 | 402 | }; |
227 | 402 | KeyType Key = { Encoding }; |
228 | 402 | auto Table = makeArrayRef(Index); |
229 | 402 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, |
230 | 2.05k | [](const IndexType &LHS, const KeyType &RHS) { |
231 | 2.05k | if (LHS.Encoding < RHS.Encoding) |
232 | 966 | return true; |
233 | 1.09k | if (LHS.Encoding > RHS.Encoding) |
234 | 696 | return false; |
235 | 396 | return false; |
236 | 396 | }); |
237 | 402 | |
238 | 402 | if (Idx == Table.end() || |
239 | 402 | Key.Encoding != Idx->Encoding396 ) |
240 | 6 | return nullptr; |
241 | 396 | return &BankedRegsList[Idx->_index]; |
242 | 396 | } |
243 | | #endif |
244 | | |
245 | | #ifdef GET_MCLASSSYSREG_DECL |
246 | | const MClassSysReg *lookupMClassSysRegByName(StringRef Name); |
247 | | const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12); |
248 | | const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8); |
249 | | const MClassSysReg *lookupMClassSysRegByEncoding(uint16_t Encoding); |
250 | | #endif |
251 | | |
252 | | #ifdef GET_MCLASSSYSREG_IMPL |
253 | | const MClassSysReg MClassSysRegsList[] = { |
254 | | { "apsr_g", 0x400, 0x0, 0x400, {ARM::FeatureDSP} }, // 0 |
255 | | { "apsr_nzcvqg", 0xC00, 0x300, 0xC00, {ARM::FeatureDSP} }, // 1 |
256 | | { "iapsr_g", 0x401, 0x1, 0x401, {ARM::FeatureDSP} }, // 2 |
257 | | { "iapsr_nzcvqg", 0xC01, 0x301, 0xC01, {ARM::FeatureDSP} }, // 3 |
258 | | { "eapsr_g", 0x402, 0x2, 0x402, {ARM::FeatureDSP} }, // 4 |
259 | | { "eapsr_nzcvqg", 0xC02, 0x302, 0xC02, {ARM::FeatureDSP} }, // 5 |
260 | | { "xpsr_g", 0x403, 0x3, 0x403, {ARM::FeatureDSP} }, // 6 |
261 | | { "xpsr_nzcvqg", 0xC03, 0x303, 0xC03, {ARM::FeatureDSP} }, // 7 |
262 | | { "apsr", 0x800, 0x100, 0x800, {} }, // 8 |
263 | | { "apsr_nzcvq", 0x1800, 0x200, 0x800, {} }, // 9 |
264 | | { "iapsr", 0x801, 0x101, 0x801, {} }, // 10 |
265 | | { "iapsr_nzcvq", 0x1801, 0x201, 0x801, {} }, // 11 |
266 | | { "eapsr", 0x802, 0x102, 0x802, {} }, // 12 |
267 | | { "eapsr_nzcvq", 0x1802, 0x202, 0x802, {} }, // 13 |
268 | | { "xpsr", 0x803, 0x103, 0x803, {} }, // 14 |
269 | | { "xpsr_nzcvq", 0x1803, 0x203, 0x803, {} }, // 15 |
270 | | { "ipsr", 0x805, 0x105, 0x805, {} }, // 16 |
271 | | { "epsr", 0x806, 0x106, 0x806, {} }, // 17 |
272 | | { "iepsr", 0x807, 0x107, 0x807, {} }, // 18 |
273 | | { "msp", 0x808, 0x108, 0x808, {} }, // 19 |
274 | | { "psp", 0x809, 0x109, 0x809, {} }, // 20 |
275 | | { "msplim", 0x80A, 0x10A, 0x80A, {ARM::HasV8MBaselineOps} }, // 21 |
276 | | { "psplim", 0x80B, 0x10B, 0x80B, {ARM::HasV8MBaselineOps} }, // 22 |
277 | | { "primask", 0x810, 0x110, 0x810, {} }, // 23 |
278 | | { "basepri", 0x811, 0x111, 0x811, {ARM::HasV7Ops} }, // 24 |
279 | | { "basepri_max", 0x812, 0x112, 0x812, {ARM::HasV7Ops} }, // 25 |
280 | | { "faultmask", 0x813, 0x113, 0x813, {ARM::HasV7Ops} }, // 26 |
281 | | { "control", 0x814, 0x114, 0x814, {} }, // 27 |
282 | | { "msp_ns", 0x888, 0x188, 0x888, {ARM::Feature8MSecExt} }, // 28 |
283 | | { "psp_ns", 0x889, 0x189, 0x889, {ARM::Feature8MSecExt} }, // 29 |
284 | | { "msplim_ns", 0x88A, 0x18A, 0x88A, {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }, // 30 |
285 | | { "psplim_ns", 0x88B, 0x18B, 0x88B, {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }, // 31 |
286 | | { "primask_ns", 0x890, 0x190, 0x890, {} }, // 32 |
287 | | { "basepri_ns", 0x891, 0x191, 0x891, {ARM::Feature8MSecExt, ARM::HasV7Ops} }, // 33 |
288 | | { "faultmask_ns", 0x893, 0x193, 0x893, {ARM::Feature8MSecExt, ARM::HasV7Ops} }, // 34 |
289 | | { "control_ns", 0x894, 0x194, 0x894, {ARM::Feature8MSecExt} }, // 35 |
290 | | { "sp_ns", 0x898, 0x198, 0x898, {ARM::Feature8MSecExt} }, // 36 |
291 | | }; |
292 | | |
293 | 297 | const MClassSysReg *lookupMClassSysRegByName(StringRef Name) { |
294 | 297 | struct IndexType { |
295 | 297 | const char * Name; |
296 | 297 | unsigned _index; |
297 | 297 | }; |
298 | 297 | static const struct IndexType Index[] = { |
299 | 297 | { "APSR", 8 }, |
300 | 297 | { "APSR_G", 0 }, |
301 | 297 | { "APSR_NZCVQ", 9 }, |
302 | 297 | { "APSR_NZCVQG", 1 }, |
303 | 297 | { "BASEPRI", 24 }, |
304 | 297 | { "BASEPRI_MAX", 25 }, |
305 | 297 | { "BASEPRI_NS", 33 }, |
306 | 297 | { "CONTROL", 27 }, |
307 | 297 | { "CONTROL_NS", 35 }, |
308 | 297 | { "EAPSR", 12 }, |
309 | 297 | { "EAPSR_G", 4 }, |
310 | 297 | { "EAPSR_NZCVQ", 13 }, |
311 | 297 | { "EAPSR_NZCVQG", 5 }, |
312 | 297 | { "EPSR", 17 }, |
313 | 297 | { "FAULTMASK", 26 }, |
314 | 297 | { "FAULTMASK_NS", 34 }, |
315 | 297 | { "IAPSR", 10 }, |
316 | 297 | { "IAPSR_G", 2 }, |
317 | 297 | { "IAPSR_NZCVQ", 11 }, |
318 | 297 | { "IAPSR_NZCVQG", 3 }, |
319 | 297 | { "IEPSR", 18 }, |
320 | 297 | { "IPSR", 16 }, |
321 | 297 | { "MSP", 19 }, |
322 | 297 | { "MSPLIM", 21 }, |
323 | 297 | { "MSPLIM_NS", 30 }, |
324 | 297 | { "MSP_NS", 28 }, |
325 | 297 | { "PRIMASK", 23 }, |
326 | 297 | { "PRIMASK_NS", 32 }, |
327 | 297 | { "PSP", 20 }, |
328 | 297 | { "PSPLIM", 22 }, |
329 | 297 | { "PSPLIM_NS", 31 }, |
330 | 297 | { "PSP_NS", 29 }, |
331 | 297 | { "SP_NS", 36 }, |
332 | 297 | { "XPSR", 14 }, |
333 | 297 | { "XPSR_G", 6 }, |
334 | 297 | { "XPSR_NZCVQ", 15 }, |
335 | 297 | { "XPSR_NZCVQG", 7 }, |
336 | 297 | }; |
337 | 297 | |
338 | 297 | struct KeyType { |
339 | 297 | std::string Name; |
340 | 297 | }; |
341 | 297 | KeyType Key = { Name.upper() }; |
342 | 297 | auto Table = makeArrayRef(Index); |
343 | 297 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, |
344 | 1.57k | [](const IndexType &LHS, const KeyType &RHS) { |
345 | 1.57k | int CmpName = StringRef(LHS.Name).compare(RHS.Name); |
346 | 1.57k | if (CmpName < 0) return true696 ; |
347 | 878 | if (CmpName > 0) return false582 ; |
348 | 296 | return false; |
349 | 296 | }); |
350 | 297 | |
351 | 297 | if (Idx == Table.end() || |
352 | 297 | Key.Name != Idx->Name) |
353 | 1 | return nullptr; |
354 | 296 | return &MClassSysRegsList[Idx->_index]; |
355 | 296 | } |
356 | | |
357 | 106 | const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12) { |
358 | 106 | struct IndexType { |
359 | 106 | uint16_t M1Encoding12; |
360 | 106 | unsigned _index; |
361 | 106 | }; |
362 | 106 | static const struct IndexType Index[] = { |
363 | 106 | { 0x400, 0 }, |
364 | 106 | { 0x401, 2 }, |
365 | 106 | { 0x402, 4 }, |
366 | 106 | { 0x403, 6 }, |
367 | 106 | { 0x800, 8 }, |
368 | 106 | { 0x801, 10 }, |
369 | 106 | { 0x802, 12 }, |
370 | 106 | { 0x803, 14 }, |
371 | 106 | { 0x805, 16 }, |
372 | 106 | { 0x806, 17 }, |
373 | 106 | { 0x807, 18 }, |
374 | 106 | { 0x808, 19 }, |
375 | 106 | { 0x809, 20 }, |
376 | 106 | { 0x80A, 21 }, |
377 | 106 | { 0x80B, 22 }, |
378 | 106 | { 0x810, 23 }, |
379 | 106 | { 0x811, 24 }, |
380 | 106 | { 0x812, 25 }, |
381 | 106 | { 0x813, 26 }, |
382 | 106 | { 0x814, 27 }, |
383 | 106 | { 0x888, 28 }, |
384 | 106 | { 0x889, 29 }, |
385 | 106 | { 0x88A, 30 }, |
386 | 106 | { 0x88B, 31 }, |
387 | 106 | { 0x890, 32 }, |
388 | 106 | { 0x891, 33 }, |
389 | 106 | { 0x893, 34 }, |
390 | 106 | { 0x894, 35 }, |
391 | 106 | { 0x898, 36 }, |
392 | 106 | { 0xC00, 1 }, |
393 | 106 | { 0xC01, 3 }, |
394 | 106 | { 0xC02, 5 }, |
395 | 106 | { 0xC03, 7 }, |
396 | 106 | { 0x1800, 9 }, |
397 | 106 | { 0x1801, 11 }, |
398 | 106 | { 0x1802, 13 }, |
399 | 106 | { 0x1803, 15 }, |
400 | 106 | }; |
401 | 106 | |
402 | 106 | struct KeyType { |
403 | 106 | uint16_t M1Encoding12; |
404 | 106 | }; |
405 | 106 | KeyType Key = { M1Encoding12 }; |
406 | 106 | auto Table = makeArrayRef(Index); |
407 | 106 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, |
408 | 573 | [](const IndexType &LHS, const KeyType &RHS) { |
409 | 573 | if (LHS.M1Encoding12 < RHS.M1Encoding12) |
410 | 215 | return true; |
411 | 358 | if (LHS.M1Encoding12 > RHS.M1Encoding12) |
412 | 256 | return false; |
413 | 102 | return false; |
414 | 102 | }); |
415 | 106 | |
416 | 106 | if (Idx == Table.end() || |
417 | 106 | Key.M1Encoding12 != Idx->M1Encoding12) |
418 | 4 | return nullptr; |
419 | 102 | return &MClassSysRegsList[Idx->_index]; |
420 | 102 | } |
421 | | |
422 | 381 | const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8) { |
423 | 381 | struct IndexType { |
424 | 381 | uint16_t M2M3Encoding8; |
425 | 381 | unsigned _index; |
426 | 381 | }; |
427 | 381 | static const struct IndexType Index[] = { |
428 | 381 | { 0x0, 0 }, |
429 | 381 | { 0x1, 2 }, |
430 | 381 | { 0x2, 4 }, |
431 | 381 | { 0x3, 6 }, |
432 | 381 | { 0x100, 8 }, |
433 | 381 | { 0x101, 10 }, |
434 | 381 | { 0x102, 12 }, |
435 | 381 | { 0x103, 14 }, |
436 | 381 | { 0x105, 16 }, |
437 | 381 | { 0x106, 17 }, |
438 | 381 | { 0x107, 18 }, |
439 | 381 | { 0x108, 19 }, |
440 | 381 | { 0x109, 20 }, |
441 | 381 | { 0x10A, 21 }, |
442 | 381 | { 0x10B, 22 }, |
443 | 381 | { 0x110, 23 }, |
444 | 381 | { 0x111, 24 }, |
445 | 381 | { 0x112, 25 }, |
446 | 381 | { 0x113, 26 }, |
447 | 381 | { 0x114, 27 }, |
448 | 381 | { 0x188, 28 }, |
449 | 381 | { 0x189, 29 }, |
450 | 381 | { 0x18A, 30 }, |
451 | 381 | { 0x18B, 31 }, |
452 | 381 | { 0x190, 32 }, |
453 | 381 | { 0x191, 33 }, |
454 | 381 | { 0x193, 34 }, |
455 | 381 | { 0x194, 35 }, |
456 | 381 | { 0x198, 36 }, |
457 | 381 | { 0x200, 9 }, |
458 | 381 | { 0x201, 11 }, |
459 | 381 | { 0x202, 13 }, |
460 | 381 | { 0x203, 15 }, |
461 | 381 | { 0x300, 1 }, |
462 | 381 | { 0x301, 3 }, |
463 | 381 | { 0x302, 5 }, |
464 | 381 | { 0x303, 7 }, |
465 | 381 | }; |
466 | 381 | |
467 | 381 | struct KeyType { |
468 | 381 | uint16_t M2M3Encoding8; |
469 | 381 | }; |
470 | 381 | KeyType Key = { M2M3Encoding8 }; |
471 | 381 | auto Table = makeArrayRef(Index); |
472 | 381 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, |
473 | 2.01k | [](const IndexType &LHS, const KeyType &RHS) { |
474 | 2.01k | if (LHS.M2M3Encoding8 < RHS.M2M3Encoding8) |
475 | 1.00k | return true; |
476 | 1.01k | if (LHS.M2M3Encoding8 > RHS.M2M3Encoding8) |
477 | 715 | return false; |
478 | 296 | return false; |
479 | 296 | }); |
480 | 381 | |
481 | 381 | if (Idx == Table.end() || |
482 | 381 | Key.M2M3Encoding8 != Idx->M2M3Encoding8) |
483 | 85 | return nullptr; |
484 | 296 | return &MClassSysRegsList[Idx->_index]; |
485 | 296 | } |
486 | | |
487 | 0 | const MClassSysReg *lookupMClassSysRegByEncoding(uint16_t Encoding) { |
488 | 0 | struct IndexType { |
489 | 0 | uint16_t Encoding; |
490 | 0 | unsigned _index; |
491 | 0 | }; |
492 | 0 | static const struct IndexType Index[] = { |
493 | 0 | { 0x400, 0 }, |
494 | 0 | { 0x401, 2 }, |
495 | 0 | { 0x402, 4 }, |
496 | 0 | { 0x403, 6 }, |
497 | 0 | { 0x800, 8 }, |
498 | 0 | { 0x800, 9 }, |
499 | 0 | { 0x801, 10 }, |
500 | 0 | { 0x801, 11 }, |
501 | 0 | { 0x802, 12 }, |
502 | 0 | { 0x802, 13 }, |
503 | 0 | { 0x803, 14 }, |
504 | 0 | { 0x803, 15 }, |
505 | 0 | { 0x805, 16 }, |
506 | 0 | { 0x806, 17 }, |
507 | 0 | { 0x807, 18 }, |
508 | 0 | { 0x808, 19 }, |
509 | 0 | { 0x809, 20 }, |
510 | 0 | { 0x80A, 21 }, |
511 | 0 | { 0x80B, 22 }, |
512 | 0 | { 0x810, 23 }, |
513 | 0 | { 0x811, 24 }, |
514 | 0 | { 0x812, 25 }, |
515 | 0 | { 0x813, 26 }, |
516 | 0 | { 0x814, 27 }, |
517 | 0 | { 0x888, 28 }, |
518 | 0 | { 0x889, 29 }, |
519 | 0 | { 0x88A, 30 }, |
520 | 0 | { 0x88B, 31 }, |
521 | 0 | { 0x890, 32 }, |
522 | 0 | { 0x891, 33 }, |
523 | 0 | { 0x893, 34 }, |
524 | 0 | { 0x894, 35 }, |
525 | 0 | { 0x898, 36 }, |
526 | 0 | { 0xC00, 1 }, |
527 | 0 | { 0xC01, 3 }, |
528 | 0 | { 0xC02, 5 }, |
529 | 0 | { 0xC03, 7 }, |
530 | 0 | }; |
531 | 0 |
|
532 | 0 | struct KeyType { |
533 | 0 | uint16_t Encoding; |
534 | 0 | }; |
535 | 0 | KeyType Key = { Encoding }; |
536 | 0 | auto Table = makeArrayRef(Index); |
537 | 0 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, |
538 | 0 | [](const IndexType &LHS, const KeyType &RHS) { |
539 | 0 | if (LHS.Encoding < RHS.Encoding) |
540 | 0 | return true; |
541 | 0 | if (LHS.Encoding > RHS.Encoding) |
542 | 0 | return false; |
543 | 0 | return false; |
544 | 0 | }); |
545 | 0 |
|
546 | 0 | if (Idx == Table.end() || |
547 | 0 | Key.Encoding != Idx->Encoding) |
548 | 0 | return nullptr; |
549 | 0 | return &MClassSysRegsList[Idx->_index]; |
550 | 0 | } |
551 | | #endif |
552 | | |
553 | | #undef GET_BANKEDREG_DECL |
554 | | #undef GET_BANKEDREG_IMPL |
555 | | #undef GET_MCLASSSYSREG_DECL |
556 | | #undef GET_MCLASSSYSREG_IMPL |